From 7efcd872b51f52d385def4e0275937ddd111b771 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 6 Feb 2025 21:28:30 -0800 Subject: [PATCH] working on reg_alloc --- Cargo.toml | 3 + crates/cpu/src/config.rs | 15 +- crates/cpu/src/instruction.rs | 611 +- crates/cpu/src/reg_alloc.rs | 220 +- crates/cpu/src/unit.rs | 83 +- crates/cpu/src/unit/alu_branch.rs | 23 +- crates/cpu/src/util.rs | 2 +- crates/cpu/tests/expected/reg_alloc.txt | 103655 +++++++++++++++++++-- crates/cpu/tests/expected/reg_alloc.vcd | 11741 ++- crates/cpu/tests/reg_alloc.rs | 3262 +- 10 files changed, 112441 insertions(+), 7174 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 7cd59a9..5f7aded 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -15,3 +15,6 @@ rust-version = "1.82.0" [workspace.dependencies] fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" } + +[profile.dev] +opt-level = 1 diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index 9335f51..90b88e4 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -1,8 +1,8 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information use crate::{ - instruction::{PRegNum, UnitNum, CONST_ZERO_UNIT_NUM}, - unit::UnitKind, + instruction::{PRegNum, UnitNum, UnitOutRegNum, CONST_ZERO_UNIT_NUM}, + unit::{UnitKind, UnitMOp}, }; use fayalite::prelude::*; use std::num::NonZeroUsize; @@ -34,12 +34,21 @@ impl CpuConfig { (CONST_ZERO_UNIT_NUM + 1)..(self.unit_kinds.len() + 1) } pub fn unit_num_width(&self) -> usize { - UInt::range(self.non_const_unit_nums()).width() + UInt::range(CONST_ZERO_UNIT_NUM..self.non_const_unit_nums().end).width() } pub fn unit_num(&self) -> UnitNum { UnitNum[self.unit_num_width()] } + pub fn unit_out_reg_num(&self) -> UnitOutRegNum { + UnitOutRegNum[self.out_reg_num_width] + } pub fn p_reg_num(&self) -> PRegNum { PRegNum[self.unit_num_width()][self.out_reg_num_width] } + pub fn p_reg_num_width(&self) -> usize { + self.unit_num_width() + self.out_reg_num_width + } + pub fn unit_mop_in_unit(&self) -> UnitMOp, DynSize> { + UnitMOp[self.unit_out_reg_num()][self.p_reg_num_width()] + } } diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index 5810c90..c073049 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -1,11 +1,108 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information -use crate::unit::UnitMOp; +use crate::{unit::UnitMOp, util::range_u32_len}; use fayalite::{expr::ops::ArrayLiteral, intern::Interned, prelude::*}; -use std::marker::PhantomData; +use std::{marker::PhantomData, ops::Range}; pub mod power_isa; +pub trait MOpTrait: Type { + type Mapped: MOpTrait; + type DestReg: Type; + type SrcRegWidth: Size; + fn dest_reg_ty(self) -> Self::DestReg; + fn dest_reg(input: impl ToExpr) -> Expr; + fn mapped_ty( + self, + new_dest_reg: NewDestReg, + new_src_reg_width: NewSrcRegWidth::SizeType, + ) -> Self::Mapped; + fn map_regs( + input: impl ToExpr, + new_dest: impl ToExpr, + new_src_reg_width: NewSrcRegWidth::SizeType, + map_src: &mut impl FnMut( + Expr>, + usize, + ) -> Expr>, + ) -> Expr>; +} + +pub trait CommonMOpTrait: MOpTrait { + type PrefixPad: KnownSize; + type SrcCount: KnownSize; + type CommonMOpTraitMapped: CommonMOpTrait; + type CommonMOpTraitDestReg: Type; + type CommonMOpTraitSrcRegWidth: Size; + fn common_mop_ty( + self, + ) -> CommonMOp; + fn common_mop( + input: impl ToExpr, + ) -> Expr>; + fn with_common_mop_ty( + self, + new_common_mop_ty: CommonMOp, + ) -> Self::Mapped; + fn with_common_mop( + input: impl ToExpr, + new_common_mop: impl ToExpr< + Type = CommonMOp, + >, + ) -> Expr>; +} + +impl MOpTrait for T { + type Mapped = + T::CommonMOpTraitMapped; + type DestReg = T::CommonMOpTraitDestReg; + type SrcRegWidth = T::CommonMOpTraitSrcRegWidth; + fn dest_reg_ty(self) -> Self::DestReg { + self.common_mop_ty().dest + } + fn dest_reg(input: impl ToExpr) -> Expr { + T::common_mop(input).dest + } + fn mapped_ty( + self, + new_dest_reg: NewDestReg, + new_src_reg_width: NewSrcRegWidth::SizeType, + ) -> Self::Mapped { + self.with_common_mop_ty( + CommonMOp[T::PrefixPad::SIZE][new_dest_reg][new_src_reg_width][T::SrcCount::SIZE], + ) + } + fn map_regs( + input: impl ToExpr, + new_dest: impl ToExpr, + new_src_reg_width: NewSrcRegWidth::SizeType, + map_src: &mut impl FnMut( + Expr>, + usize, + ) -> Expr>, + ) -> Expr> { + let input = input.to_expr(); + let common = T::common_mop(input); + let new_dest = new_dest.to_expr(); + T::with_common_mop( + input, + CommonMOp::new( + common.prefix_pad, + new_dest, + ArrayLiteral::new( + UIntType[new_src_reg_width], + Interned::from_iter( + (0..T::SrcCount::VALUE) + .map(|index| Expr::canonical(map_src(common.src[index], index))), + ), + ) + .to_expr(), + CommonMOp::imm(common), + ), + ) + } +} + #[hdl] pub enum OutputIntegerMode { Full64, @@ -25,15 +122,51 @@ pub const COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM: usize = 2; pub const COMMON_MOP_IMM_LOW_WIDTH: usize = CommonMOpWithMaxSrcCount::IMM_WIDTH - 1; #[hdl] -pub struct CommonMOp { +pub struct CommonMOp { pub prefix_pad: UIntType, - pub dest: UIntType, - pub src: Array, { COMMON_MOP_SRC_LEN }>, + pub dest: DestReg, + pub src: Array, { COMMON_MOP_SRC_LEN }>, pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>, pub imm_sign: SInt<1>, pub _phantom: PhantomData, } +impl CommonMOpTrait + for CommonMOp +{ + type PrefixPad = PrefixPad; + type SrcCount = SrcCount; + type CommonMOpTraitMapped = + CommonMOp; + type CommonMOpTraitDestReg = DestReg; + type CommonMOpTraitSrcRegWidth = SrcRegWidth; + fn common_mop_ty( + self, + ) -> CommonMOp { + self + } + fn common_mop( + input: impl ToExpr, + ) -> Expr> { + input.to_expr() + } + fn with_common_mop_ty( + self, + new_common_mop_ty: CommonMOp, + ) -> Self::Mapped { + new_common_mop_ty + } + fn with_common_mop( + input: impl ToExpr, + new_common_mop: impl ToExpr< + Type = CommonMOp, + >, + ) -> Expr> { + let _ = input.to_expr(); + new_common_mop.to_expr() + } +} + #[hdl] pub struct CommonMOpImmParts { // fields must be in this exact order @@ -45,7 +178,7 @@ pub struct CommonMOpImmParts { type CommonMOpWithMaxSrcCount = CommonMOpForImm<{ COMMON_MOP_SRC_LEN }>; type CommonMOpForImm = - CommonMOp, ConstUsize<{ MOP_MIN_REG_WIDTH }>, ConstUsize>; + CommonMOp, (), ConstUsize<{ MOP_MIN_REG_WIDTH }>, ConstUsize>; pub const COMMON_MOP_0_IMM_WIDTH: usize = CommonMOpForImm::<0>::IMM_WIDTH; pub const COMMON_MOP_1_IMM_WIDTH: usize = CommonMOpForImm::<1>::IMM_WIDTH; @@ -53,8 +186,8 @@ pub const COMMON_MOP_2_IMM_WIDTH: usize = CommonMOpForImm::<2>::IMM_WIDTH; pub const COMMON_MOP_3_IMM_WIDTH: usize = CommonMOpForImm::<3>::IMM_WIDTH; const COMMON_MOP_0_IMM_IN_SRC_COUNT: usize = CommonMOpForImm::<0>::IMM_IN_SRC_COUNT; -impl - CommonMOp +impl + CommonMOp { pub const IMM_IN_SRC_COUNT: usize = { assert!(SrcCount::VALUE <= COMMON_MOP_SRC_LEN, "too many sources"); @@ -62,7 +195,7 @@ impl (COMMON_MOP_SRC_LEN - COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM) - SrcCount::VALUE.saturating_sub(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM) }; - pub const IMM_IN_SRC_RANGE: std::ops::Range = + pub const IMM_IN_SRC_RANGE: Range = (COMMON_MOP_SRC_LEN - Self::IMM_IN_SRC_COUNT)..COMMON_MOP_SRC_LEN; pub const IMM_WIDTH: usize = { MOP_IMM_WIDTH - (COMMON_MOP_0_IMM_IN_SRC_COUNT - Self::IMM_IN_SRC_COUNT) * MOP_MIN_REG_WIDTH @@ -82,8 +215,8 @@ impl #[hdl] pub fn new( prefix_pad: impl ToExpr>, - dest: impl ToExpr>, - src: impl ToExpr, SrcCount>>, + dest: impl ToExpr, + src: impl ToExpr, SrcCount>>, imm: impl ToExpr, ) -> Expr { let prefix_pad = prefix_pad.to_expr(); @@ -91,22 +224,21 @@ impl let src_in = src.to_expr(); let imm = imm.to_expr(); assert_eq!(Expr::ty(imm), Self::imm_ty()); - let reg_ty = Expr::ty(dest); - assert_eq!(reg_ty, Expr::ty(src_in).element()); + let src_reg_ty = Expr::ty(src_in).element(); let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty()); - let mut src = [0_hdl_u0.cast_to(reg_ty); COMMON_MOP_SRC_LEN]; + let mut src = [0_hdl_u0.cast_to(src_reg_ty); COMMON_MOP_SRC_LEN]; for i in 0..SrcCount::VALUE { src[i] = src_in[i]; } for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() { - src[src_index] = imm_parts.reversed_src[reversed_src_index].cast_to(reg_ty); + src[src_index] = imm_parts.reversed_src[reversed_src_index].cast_to(src_reg_ty); } #[hdl] Self { prefix_pad, dest, src: ArrayLiteral::new( - reg_ty, + src_reg_ty, Interned::from_iter(src.iter().map(|v| Expr::canonical(*v))), ) .to_expr(), @@ -136,17 +268,16 @@ impl #[hdl] pub fn connect_to_imm(expr: impl ToExpr, imm: impl ToExpr) { let expr = expr.to_expr(); - let reg_ty = Expr::ty(expr).dest; - assert_eq!(reg_ty, Expr::ty(expr).src.element()); + let src_reg_ty = Expr::ty(expr).src.element(); let imm = imm.to_expr(); assert_eq!(Expr::ty(imm), Self::imm_ty()); let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty()); - let mut src = [Some(0_hdl_u0.cast_to(reg_ty)); COMMON_MOP_SRC_LEN]; + let mut src = [Some(0_hdl_u0.cast_to(src_reg_ty)); COMMON_MOP_SRC_LEN]; for i in 0..SrcCount::VALUE { src[i] = None; } for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() { - src[src_index] = Some(imm_parts.reversed_src[reversed_src_index].cast_to(reg_ty)); + src[src_index] = Some(imm_parts.reversed_src[reversed_src_index].cast_to(src_reg_ty)); } for i in 0..COMMON_MOP_SRC_LEN { if let Some(v) = src[i] { @@ -156,82 +287,307 @@ impl } } -#[hdl] -pub struct AluCommonMOp { - pub common: CommonMOp, RegWidth, SrcCount>, - pub output_integer_mode: OutputIntegerMode, +macro_rules! common_mop_struct { + ( + #[mapped(<$NewDestReg:ident, $SrcRegWidth:ident> $mapped_ty:ty)] + $(#[$struct_meta:meta])* + $vis:vis struct $MOp:ident<$($Generic:ident: $GenericBound:ident),* $(,)?> { + #[common] + $(#[$common_meta:meta])* + $common_vis:vis $common:ident: $common_ty:ty, + $( + $(#[$field_meta:meta])* + $field_vis:vis $field:ident: $field_ty:ty, + )* + } + ) => { + $(#[$struct_meta])* + $vis struct $MOp<$($Generic: $GenericBound),*> { + $(#[$common_meta])* + $common_vis $common: $common_ty, + $( + $(#[$field_meta])* + $field_vis $field: $field_ty, + )* + } + + impl<$($Generic: $GenericBound),*> CommonMOpTrait for $MOp<$($Generic),*> { + type PrefixPad = <$common_ty as CommonMOpTrait>::PrefixPad; + type SrcCount = <$common_ty as CommonMOpTrait>::SrcCount; + type CommonMOpTraitMapped<$NewDestReg: Type, $SrcRegWidth: Size> = $mapped_ty; + type CommonMOpTraitDestReg = <$common_ty as CommonMOpTrait>::CommonMOpTraitDestReg; + type CommonMOpTraitSrcRegWidth = <$common_ty as CommonMOpTrait>::CommonMOpTraitSrcRegWidth; + + fn common_mop_ty( + self, + ) -> CommonMOp { + CommonMOpTrait::common_mop_ty(self.$common) + } + fn common_mop( + input: impl ToExpr, + ) -> Expr> { + CommonMOpTrait::common_mop(input.to_expr().$common) + } + fn with_common_mop_ty( + self, + new_common_mop_ty: CommonMOp, + ) -> Self::Mapped { + $MOp { + $common: CommonMOpTrait::with_common_mop_ty(self.$common, new_common_mop_ty), + $($field: self.$field,)* + } + } + #[hdl] + fn with_common_mop( + input: impl ToExpr, + new_common_mop: impl ToExpr< + Type = CommonMOp, + >, + ) -> Expr> { + let input = input.to_expr(); + #[hdl] + $MOp { + $common: CommonMOpTrait::with_common_mop(input.$common, new_common_mop), + $($field: input.$field,)* + } + } + } + }; } -#[hdl] -pub struct AddSubMOp { - pub alu_common: AluCommonMOp, - pub invert_src0: Bool, - pub invert_carry_in: Bool, - pub invert_carry_out: Bool, - pub add_pc: Bool, +macro_rules! mop_enum { + ( + $(#[$enum_meta:meta])* + $vis:vis enum $MOp:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size> { + $(#[$first_variant_meta:meta])* + $FirstVariant:ident($first_ty:ty), + $( + $(#[$variant_meta:meta])* + $Variant:ident($ty:ty), + )* + } + ) => { + $(#[$enum_meta])* + $vis enum $MOp<$DestReg: Type, $SrcRegWidth: Size> { + $(#[$first_variant_meta])* + $FirstVariant($first_ty), + $( + $(#[$variant_meta])* + $Variant($ty), + )* + } + + impl<$DestReg: Type, $SrcRegWidth: Size> MOpTrait for $MOp<$DestReg, $SrcRegWidth> { + type Mapped = $MOp; + type DestReg = $DestReg; + type SrcRegWidth = $SrcRegWidth; + fn dest_reg_ty(self) -> Self::DestReg { + self.$FirstVariant.dest_reg_ty() + } + #[hdl] + fn dest_reg(input: impl ToExpr) -> Expr { + let input = input.to_expr(); + #[hdl] + let dest_reg = wire(Expr::ty(input).dest_reg_ty()); + #[hdl] + match input { + $MOp::<_, _>::$FirstVariant(v) => connect(dest_reg, MOpTrait::dest_reg(v)), + $($MOp::<_, _>::$Variant(v) => connect(dest_reg, MOpTrait::dest_reg(v)),)* + } + dest_reg + } + fn mapped_ty( + self, + new_dest_reg: NewDestReg, + new_src_reg_width: NewSrcRegWidth::SizeType, + ) -> Self::Mapped { + $MOp[new_dest_reg][new_src_reg_width] + } + #[hdl] + fn map_regs( + input: impl ToExpr, + new_dest: impl ToExpr, + new_src_reg_width: NewSrcRegWidth::SizeType, + map_src: &mut impl FnMut( + Expr>, + usize, + ) -> Expr>, + ) -> Expr> { + let input = input.to_expr(); + let new_dest = new_dest.to_expr(); + let mapped_ty = Expr::ty(input).mapped_ty(Expr::ty(new_dest), new_src_reg_width); + #[hdl] + let mapped_regs = wire(mapped_ty); + #[hdl] + match input { + $MOp::<_, _>::$FirstVariant(v) => connect(mapped_regs, mapped_ty.$FirstVariant(MOpTrait::map_regs(v, new_dest, new_src_reg_width, map_src))), + $($MOp::<_, _>::$Variant(v) => connect(mapped_regs, mapped_ty.$Variant(MOpTrait::map_regs(v, new_dest, new_src_reg_width, map_src))),)* + } + mapped_regs + } + } + }; } -#[hdl] -pub struct LogicalMOp { - pub alu_common: AluCommonMOp>, - pub lut: UInt<4>, +pub(crate) use mop_enum; + +common_mop_struct! { + #[mapped( AluCommonMOp)] + #[hdl] + pub struct AluCommonMOp { + #[common] + pub common: CommonMOp, DestReg, SrcRegWidth, SrcCount>, + pub output_integer_mode: OutputIntegerMode, + } } -#[hdl] -pub struct BranchMOp { - pub alu_common: AluCommonMOp>, - pub lut: UInt<4>, +common_mop_struct! { + #[mapped( AddSubMOp)] + #[hdl] + pub struct AddSubMOp { + #[common] + pub alu_common: AluCommonMOp, + pub invert_src0: Bool, + pub invert_carry_in: Bool, + pub invert_carry_out: Bool, + pub add_pc: Bool, + } } -#[hdl] -pub enum AluBranchMOp { - AddSub(AddSubMOp>), - AddSubI(AddSubMOp>), - Logical(LogicalMOp), +common_mop_struct! { + #[mapped( LogicalMOp)] + #[hdl] + pub struct LogicalMOp { + #[common] + pub alu_common: AluCommonMOp>, + pub lut: UInt<4>, + } } -#[hdl] -pub struct ReadL2RegMOp { - pub common: CommonMOp, RegWidth, ConstUsize<0>>, +common_mop_struct! { + #[mapped( BranchMOp)] + #[hdl] + pub struct BranchMOp { + #[common] + pub alu_common: AluCommonMOp>, + pub lut: UInt<4>, + } } -#[hdl] -pub struct WriteL2RegMOp { - pub common: CommonMOp, RegWidth, ConstUsize<1>>, +mop_enum! { + #[hdl] + pub enum AluBranchMOp { + AddSub(AddSubMOp>), + AddSubI(AddSubMOp>), + Logical(LogicalMOp), + } } -#[hdl] -pub enum L2RegisterFileMOp { - ReadL2Reg(ReadL2RegMOp), - WriteL2Reg(WriteL2RegMOp), +common_mop_struct! { + #[mapped( ReadL2RegMOp)] + #[hdl] + pub struct ReadL2RegMOp { + #[common] + pub common: CommonMOp, DestReg, SrcRegWidth, ConstUsize<0>>, + } } -#[hdl] -pub struct LoadStoreCommonMOp { - pub common: CommonMOp, RegWidth, SrcCount>, +common_mop_struct! { + #[mapped( WriteL2RegMOp)] + #[hdl] + pub struct WriteL2RegMOp { + #[common] + pub common: CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>, + } } -#[hdl] -pub struct LoadMOp { - pub load_store_common: LoadStoreCommonMOp>, +mop_enum! { + #[hdl] + pub enum L2RegisterFileMOp { + ReadL2Reg(ReadL2RegMOp), + WriteL2Reg(WriteL2RegMOp), + } } -#[hdl] -pub struct StoreMOp { - pub load_store_common: LoadStoreCommonMOp>, +common_mop_struct! { + #[mapped( LoadStoreCommonMOp)] + #[hdl] + pub struct LoadStoreCommonMOp { + #[common] + pub common: CommonMOp, DestReg, SrcRegWidth, SrcCount>, + } } -#[hdl] -pub enum LoadStoreMOp { - Load(CommonMOp, RegWidth, ConstUsize<0>>), - Store(CommonMOp, RegWidth, ConstUsize<1>>), +common_mop_struct! { + #[mapped( LoadMOp)] + #[hdl] + pub struct LoadMOp { + #[common] + pub load_store_common: LoadStoreCommonMOp>, + } +} + +common_mop_struct! { + #[mapped( StoreMOp)] + #[hdl] + pub struct StoreMOp { + #[common] + pub load_store_common: LoadStoreCommonMOp>, + } +} + +mop_enum! { + #[hdl] + pub enum LoadStoreMOp { + Load(CommonMOp, DestReg, SrcRegWidth, ConstUsize<0>>), + Store(CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>), + } } #[hdl] /// there may be more than one unit of a given kind, so UnitNum is not the same as UnitKind. /// zero is used for built-in constants, such as the zero register pub struct UnitNum { - pub value: UIntType, + pub adj_value: UIntType, +} + +impl UnitNum { + #[hdl] + pub fn const_zero(self) -> Expr { + #[hdl] + UnitNum { + adj_value: CONST_ZERO_UNIT_NUM.cast_to(self.adj_value), + } + } + #[hdl] + pub fn from_index(self, index: usize) -> Expr { + #[hdl] + UnitNum { + adj_value: (index + 1).cast_to(self.adj_value), + } + } + pub fn is_index(expr: impl ToExpr, index: usize) -> Expr { + let expr = expr.to_expr(); + Expr::ty(expr) + .from_index(index) + .adj_value + .cmp_eq(expr.adj_value) + } + #[hdl] + pub fn as_index(expr: impl ToExpr) -> Expr>> { + let expr = expr.to_expr(); + #[hdl] + let unit_index = wire(HdlOption[Expr::ty(expr).adj_value]); + connect(unit_index, Expr::ty(unit_index).HdlNone()); + #[hdl] + if expr.adj_value.cmp_ne(0u8) { + connect( + unit_index, + HdlSome((expr.adj_value - 1u8).cast_to(Expr::ty(expr).adj_value)), + ); + } + unit_index + } } pub const CONST_ZERO_UNIT_NUM: usize = 0; @@ -248,6 +604,20 @@ pub struct PRegNum { pub unit_out_reg: UnitOutRegNum, } +impl PRegNum { + #[hdl] + pub fn const_zero(self) -> Expr { + #[hdl] + PRegNum { + unit_num: self.unit_num.const_zero(), + unit_out_reg: #[hdl] + UnitOutRegNum { + value: 0u8.cast_to(self.unit_out_reg.value), + }, + } + } +} + #[hdl] /// µOp Register Number -- register in a micro-operation before register renaming #[doc(alias = "UOpRegNum")] // help you find it in the docs if you mis-spell it @@ -261,7 +631,110 @@ pub struct MOpRegNum { impl MOpRegNum { pub const WIDTH: usize = 8; pub const CONST_ZERO_REG_NUM: u32 = 0; + #[hdl] + pub fn const_zero() -> Expr { + #[hdl] + MOpRegNum { + value: Self::CONST_ZERO_REG_NUM.cast_to_static(), + } + } + /// a lot of instructions write to flag registers that we want + /// to register allocate separately. + /// + /// e.g. x86 `CF` is not modified by `INC`, but is by `ADD`, so to not slow down `INC`, + /// we'd need to have `CF` be renamed separately from other flags such as `ZF`. + /// + /// Note this doesn't mean that each instruction has to write to multiple physical registers, + /// all registers written by an instruction are renamed to the same physical register. + // + // TODO: maybe add more registers later. + pub const FLAG_REG_NUMS: Range = 0xFE..0x100; + /// registers handled by a special small rename table (for flags and stuff, since it has more read/write ports) + pub const SPECIAL_REG_NUMS: Range = Self::FLAG_REG_NUMS; + /// registers handled by the large rename table for normal registers (has less read/write ports) + pub const NORMAL_REG_NUMS: Range = + Self::CONST_ZERO_REG_NUM + 1..Self::SPECIAL_REG_NUMS.start; } #[hdl] -pub type MOp = UnitMOp>; +/// all the registers this instruction will write to, they are all renamed to the same physical register. +pub struct MOpDestReg { + /// some instructions have multiple destination registers, e.g. x86 div + pub normal_regs: Array, + /// a lot of instructions also write to flag registers. + /// + /// when an element with index `index` is `HdlSome(())`, + /// then the register to write to is [`MOpRegNum::FLAG_REG_NUMS[index]`][MOpRegNum::FLAG_REG_NUMS]. + pub flag_regs: Array, { range_u32_len(&MOpRegNum::FLAG_REG_NUMS) }>, +} + +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +pub enum MOpDestRegKind { + NormalReg { + /// index in `MOpDestReg::normal_regs` + dest_reg_index: usize, + }, + FlagReg { + /// index in `MOpDestReg::flag_regs` + flag_reg_index: usize, + /// value for `MOpRegNum::value` + reg_num: u32, + }, +} + +impl MOpDestReg { + pub const NORMAL_REG_COUNT: usize = 2; + pub const REG_COUNT: usize = Self::NORMAL_REG_COUNT + range_u32_len(&MOpRegNum::FLAG_REG_NUMS); + pub const REG_KINDS: [MOpDestRegKind; Self::REG_COUNT] = { + let mut retval = [MOpDestRegKind::NormalReg { dest_reg_index: 0 }; Self::REG_COUNT]; + let mut write_index = 0; + let mut dest_reg_index = 0; + while dest_reg_index < Self::NORMAL_REG_COUNT { + retval[write_index] = MOpDestRegKind::NormalReg { dest_reg_index }; + write_index += 1; + dest_reg_index += 1; + } + let mut flag_reg_index = 0; + while flag_reg_index < range_u32_len(&MOpRegNum::FLAG_REG_NUMS) { + retval[write_index] = MOpDestRegKind::FlagReg { + flag_reg_index, + reg_num: flag_reg_index as u32 + MOpRegNum::FLAG_REG_NUMS.start, + }; + write_index += 1; + flag_reg_index += 1; + } + // make sure we didn't miss filling any + assert!(write_index == Self::REG_COUNT); + retval + }; + #[hdl] + pub fn regs(this: impl ToExpr) -> [Expr; Self::REG_COUNT] { + let this = this.to_expr(); + std::array::from_fn(|index| match Self::REG_KINDS[index] { + MOpDestRegKind::NormalReg { dest_reg_index } => this.normal_regs[dest_reg_index], + MOpDestRegKind::FlagReg { + flag_reg_index, + reg_num, + } => { + #[hdl] + let flag_reg = wire(); + connect(flag_reg, MOpRegNum::const_zero()); + #[hdl] + if let HdlSome(v) = this.flag_regs[flag_reg_index] { + let () = *v; + connect( + flag_reg, + #[hdl] + MOpRegNum { + value: reg_num.cast_to_static(), + }, + ); + } + flag_reg + } + }) + } +} + +#[hdl] +pub type MOp = UnitMOp>; diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs index 9f059a9..3d32261 100644 --- a/crates/cpu/src/reg_alloc.rs +++ b/crates/cpu/src/reg_alloc.rs @@ -2,7 +2,9 @@ // See Notices.txt for copyright information use crate::{ config::CpuConfig, - instruction::MOp, + instruction::{ + MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, UnitOutRegNum, COMMON_MOP_SRC_LEN, + }, unit::{TrapData, UnitTrait}, util::tree_reduce::tree_reduce_with_state, }; @@ -17,7 +19,7 @@ pub mod unit_free_regs_tracker; #[hdl] pub struct FetchedDecodedMOp { - pub uop: MOp, + pub mop: MOp, /// true if pc doesn't have to be related to the previous instruction. /// (enable to stop detecting when the current instruction isn't /// supposed to be run next, e.g. on branch mis-prediction) @@ -52,11 +54,27 @@ pub fn reg_alloc(config: &CpuConfig) { HdlNone(), ); // TODO: finish + + // the large rename table for normal registers (has less read/write ports) + #[hdl] + let mut rename_table_normal_mem = memory(config.p_reg_num()); + rename_table_normal_mem.depth(MOpRegNum::NORMAL_REG_NUMS.len()); + + // a special small rename table (for flags and stuff, since it has more read/write ports) + #[hdl] + let mut rename_table_special_mem = memory(config.p_reg_num()); + rename_table_special_mem.depth(MOpRegNum::SPECIAL_REG_NUMS.len()); + #[hdl] let available_units = wire(Array[Array[Bool][config.unit_kinds.len()]][config.fetch_width.get()]); #[hdl] - let selected_unit_nums = wire(Array[HdlOption[config.unit_num()]][config.fetch_width.get()]); + let selected_unit_indexes = + wire(Array[HdlOption[UInt[config.unit_num_width()]]][config.fetch_width.get()]); + #[hdl] + let renamed_mops = wire(Array[HdlOption[config.unit_mop_in_unit()]][config.fetch_width.get()]); + #[hdl] + let renamed_mops_out_reg = wire(Array[HdlOption[config.p_reg_num()]][config.fetch_width.get()]); for fetch_index in 0..config.fetch_width.get() { connect( fetch_decode_interface.decoded_insns[fetch_index].ready, @@ -66,50 +84,160 @@ pub fn reg_alloc(config: &CpuConfig) { available_units[fetch_index], repeat(false, config.unit_kinds.len()), ); + connect( + renamed_mops[fetch_index], + Expr::ty(renamed_mops).element().HdlNone(), + ); + #[hdl] + struct RenameTableReadPort { + addr: MOpRegNum, + #[hdl(flip)] + data: HdlOption, + } + let make_rename_table_read_port = + |mem: &mut MemBuilder<_>, + reg_range: std::ops::Range, + src_index: usize, + table_name: &str| { + let read_port = mem.new_read_port(); + connect(read_port.clk, cd.clk); + connect_any(read_port.addr, 0u8); + connect(read_port.en, false); + let wire = wire_with_loc( + &format!("{table_name}_{fetch_index}_src_{src_index}"), + SourceLocation::caller(), + RenameTableReadPort[config.p_reg_num()], + ); + connect(wire.addr, MOpRegNum::const_zero()); + connect(wire.data, Expr::ty(wire.data).HdlNone()); + #[hdl] + if wire.addr.value.cmp_ge(reg_range.start) & wire.addr.value.cmp_lt(reg_range.end) { + connect_any(read_port.addr, wire.addr.value - reg_range.start); + connect(read_port.en, true); + connect(wire.data, HdlSome(read_port.data)); + for prev_fetch_index in 0..fetch_index { + #[hdl] + if let HdlSome(decoded_insn) = + fetch_decode_interface.decoded_insns[prev_fetch_index].data + { + #[hdl] + if let HdlSome(renamed_mop_out_reg) = + renamed_mops_out_reg[prev_fetch_index] + { + let dest_reg = MOpTrait::dest_reg(decoded_insn.mop); + for dest_reg in MOpDestReg::regs(dest_reg) { + #[hdl] + if dest_reg.value.cmp_eq(wire.addr.value) { + connect(wire.data, HdlSome(renamed_mop_out_reg)); + } + } + } + } + } + } + wire + }; + let rename_table_normal_read_ports: [_; COMMON_MOP_SRC_LEN] = + std::array::from_fn(|src_index| { + make_rename_table_read_port( + &mut rename_table_normal_mem, + MOpRegNum::NORMAL_REG_NUMS, + src_index, + "rename_table_normal", + ) + }); + let rename_table_special_read_ports: [_; COMMON_MOP_SRC_LEN] = + std::array::from_fn(|src_index| { + make_rename_table_read_port( + &mut rename_table_special_mem, + MOpRegNum::FLAG_REG_NUMS, + src_index, + "rename_table_special", + ) + }); #[hdl] if let HdlSome(decoded_insn) = fetch_decode_interface.decoded_insns[fetch_index].data { connect( available_units[fetch_index], - config.available_units_for_kind(MOp::kind(decoded_insn.uop)), + config.available_units_for_kind(MOp::kind(decoded_insn.mop)), ); + #[hdl] + if let HdlSome(renamed_mop_out_reg) = renamed_mops_out_reg[fetch_index] { + let dest_reg = MOpTrait::dest_reg(decoded_insn.mop); + connect( + renamed_mops[fetch_index], + HdlSome(MOpTrait::map_regs( + decoded_insn.mop, + renamed_mop_out_reg.unit_out_reg, + config.p_reg_num_width(), + &mut |src_reg, src_index| { + let src_reg = #[hdl] + MOpRegNum { value: src_reg }; + let renamed_src_reg = wire_with_loc( + &format!("renamed_src_reg_{fetch_index}_{src_index}"), + SourceLocation::caller(), + config.p_reg_num(), + ); + connect(rename_table_normal_read_ports[src_index].addr, src_reg); + connect(rename_table_special_read_ports[src_index].addr, src_reg); + #[hdl] + if let HdlSome(v) = rename_table_normal_read_ports[src_index].data { + connect(renamed_src_reg, v); + } else if let HdlSome(v) = + rename_table_special_read_ports[src_index].data + { + connect(renamed_src_reg, v); + } else { + connect(renamed_src_reg, config.p_reg_num().const_zero()); + } + renamed_src_reg.cast_to_bits() + }, + )), + ); + // TODO: write dest_reg to rename table + // rename_table_mem.new_write_port() + } } connect( - selected_unit_nums[fetch_index], + selected_unit_indexes[fetch_index], tree_reduce_with_state( 0..config.unit_kinds.len(), &mut 0usize, |_state, unit_index| { - let selected_unit_leaf = wire_with_loc( - &format!("selected_unit_leaf_{fetch_index}_{unit_index}"), + let selected_unit_index_leaf = wire_with_loc( + &format!("selected_unit_index_leaf_{fetch_index}_{unit_index}"), SourceLocation::caller(), - HdlOption[config.unit_num()], + HdlOption[UInt[config.unit_num_width()]], ); - connect(selected_unit_leaf, HdlOption[config.unit_num()].HdlNone()); - let unit_num = wire_with_loc( - &format!("unit_num_{fetch_index}_{unit_index}"), + connect( + selected_unit_index_leaf, + Expr::ty(selected_unit_index_leaf).HdlNone(), + ); + let unit_index_wire = wire_with_loc( + &format!("unit_index_{fetch_index}_{unit_index}"), SourceLocation::caller(), - config.unit_num(), + UInt[config.unit_num_width()], ); - connect_any(unit_num.value, unit_index); + connect_any(unit_index_wire, unit_index); #[hdl] if available_units[fetch_index][unit_index] { - connect(selected_unit_leaf, HdlSome(unit_num)) + connect(selected_unit_index_leaf, HdlSome(unit_index_wire)) } - selected_unit_leaf + selected_unit_index_leaf }, |state, l, r| { - let selected_unit_node = wire_with_loc( - &format!("selected_unit_node_{fetch_index}_{state}"), + let selected_unit_index_node = wire_with_loc( + &format!("selected_unit_index_node_{fetch_index}_{state}"), SourceLocation::caller(), Expr::ty(l), ); *state += 1; - connect(selected_unit_node, l); + connect(selected_unit_index_node, l); #[hdl] if let HdlNone = l { - connect(selected_unit_node, r); + connect(selected_unit_index_node, r); } - selected_unit_node + selected_unit_index_node }, ) .expect("expected at least one unit"), @@ -120,14 +248,21 @@ pub fn reg_alloc(config: &CpuConfig) { // TODO: handle assigning multiple instructions to a unit at a time for later_fetch_index in fetch_index + 1..config.fetch_width.get() { #[hdl] - if let HdlSome(selected_unit_num) = selected_unit_nums[fetch_index] { + if let HdlSome(selected_unit_index) = selected_unit_indexes[fetch_index] { connect( - available_units[later_fetch_index][selected_unit_num.value], + available_units[later_fetch_index][selected_unit_index], false, ); } } } + connect( + renamed_mops_out_reg, + repeat( + HdlOption[config.p_reg_num()].HdlNone(), + config.fetch_width.get(), + ), + ); for (unit_index, &unit_kind) in config.unit_kinds.iter().enumerate() { let dyn_unit = unit_kind.unit(config); let unit = instance_with_loc( @@ -136,6 +271,7 @@ pub fn reg_alloc(config: &CpuConfig) { SourceLocation::caller(), ); connect(dyn_unit.cd(unit), cd); + let unit_input = dyn_unit.input(unit); // TODO: handle assigning multiple instructions to a unit at a time let assign_to_unit_at_once = NonZeroUsize::new(1).unwrap(); // TODO: handle retiring multiple instructions from a unit at a time @@ -156,6 +292,7 @@ pub fn reg_alloc(config: &CpuConfig) { HdlOption[UInt[config.out_reg_num_width]].uninit(), // FIXME: just for debugging ); connect(unit_free_regs_tracker.alloc_out[0].ready, false); + connect(unit_input.data, Expr::ty(unit_input).data.HdlNone()); for fetch_index in 0..config.fetch_width.get() { #[hdl] if let HdlNone = unit_free_regs_tracker.alloc_out[0].data { @@ -163,10 +300,45 @@ pub fn reg_alloc(config: &CpuConfig) { connect(available_units[fetch_index][unit_index], false); } #[hdl] - if let HdlSome(unit_num) = selected_unit_nums[fetch_index] { + if !unit_input.ready { + // must come after to override connects in loops above + connect(available_units[fetch_index][unit_index], false); + } + #[hdl] + if let HdlSome(selected_unit_index) = selected_unit_indexes[fetch_index] { #[hdl] - if unit_num.value.cmp_eq(unit_index) { + if selected_unit_index.cmp_eq(unit_index) { connect(unit_free_regs_tracker.alloc_out[0].ready, true); + #[hdl] + if let HdlSome(renamed_mop) = + HdlOption::and_then(renamed_mops[fetch_index], |v| dyn_unit.extract_mop(v)) + { + connect(unit_input.data, HdlSome(renamed_mop)); + } else { + connect( + unit_input.data, + HdlSome(Expr::ty(unit_input).data.HdlSome.uninit()), + ); + // FIXME: add hdl_assert(cd.clk, false.to_expr(), ""); + } + #[hdl] + if let HdlSome(unit_out_reg) = unit_free_regs_tracker.alloc_out[0].data { + let unit_num = config.unit_num().from_index(unit_index); + let unit_out_reg = #[hdl] + UnitOutRegNum { + value: unit_out_reg, + }; + connect( + renamed_mops_out_reg[fetch_index], + HdlSome( + #[hdl] + PRegNum { + unit_num, + unit_out_reg, + }, + ), + ); + } } } } diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index a6bcaeb..eeee98f 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -3,7 +3,9 @@ use crate::{ config::CpuConfig, - instruction::{AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, PRegNum}, + instruction::{ + mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, PRegNum, UnitOutRegNum, + }, register::PRegValue, }; use fayalite::{ @@ -21,9 +23,10 @@ macro_rules! all_units { #[unit_kind = $UnitKind:ident] #[hdl] $(#[$enum_meta:meta])* - $vis:vis enum $UnitMOpEnum:ident<$RegWidth:ident: Size> { + $vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size> { $( #[create_dyn_unit_fn = $create_dyn_unit_fn:expr] + #[extract = $extract:ident] $(#[$variant_meta:meta])* $Unit:ident($Op:ty), )* @@ -65,26 +68,43 @@ macro_rules! all_units { )* } - #[hdl] - $(#[$enum_meta])* - $vis enum $UnitMOpEnum<$RegWidth: Size> { - $( - $(#[$variant_meta])* - $Unit($Op), - )* + mop_enum! { + #[hdl] + $(#[$enum_meta])* + $vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size> { + $( + $(#[$variant_meta])* + $Unit($Op), + )* + } } - impl<$RegWidth: Size> $UnitMOpEnum<$RegWidth> { + impl<$DestReg: Type, $SrcRegWidth: Size> $UnitMOpEnum<$DestReg, $SrcRegWidth> { #[hdl] $vis fn kind(expr: impl ToExpr) -> Expr<$HdlUnitKind> { #[hdl] let unit_kind = wire(); #[hdl] match expr { - $($UnitMOpEnum::<$RegWidth>::$Unit(_) => connect(unit_kind, $HdlUnitKind.$Unit()),)* + $($UnitMOpEnum::<_, _>::$Unit(_) => connect(unit_kind, $HdlUnitKind.$Unit()),)* } unit_kind } + $( + #[hdl] + $vis fn $extract(expr: impl ToExpr) -> Expr> { + let expr = expr.to_expr(); + let ty = Expr::ty(expr); + #[hdl] + let $extract = wire(HdlOption[ty.$Unit]); + connect($extract, HdlOption[ty.$Unit].HdlNone()); + #[hdl] + if let $UnitMOpEnum::<_, _>::$Unit(v) = expr { + connect($extract, HdlSome(v)); + } + $extract + } + )* } impl CpuConfig { @@ -108,13 +128,16 @@ all_units! { #[hdl_unit_kind = HdlUnitKind] #[unit_kind = UnitKind] #[hdl] - pub enum UnitMOp { + pub enum UnitMOp { #[create_dyn_unit_fn = |config| alu_branch::AluBranch::new(config).to_dyn()] - AluBranch(AluBranchMOp), + #[extract = alu_branch_mop] + AluBranch(AluBranchMOp), #[create_dyn_unit_fn = |config| todo!()] - L2RegisterFile(L2RegisterFileMOp), + #[extract = l2_register_file_mop] + L2RegisterFile(L2RegisterFileMOp), #[create_dyn_unit_fn = |config| todo!()] - LoadStore(LoadStoreMOp), + #[extract = load_store_mop] + LoadStore(LoadStoreMOp), } } @@ -159,9 +182,15 @@ pub trait UnitTrait: fn unit_kind(&self) -> UnitKind; + fn extract_mop( + &self, + mop: Expr, DynSize>>, + ) -> Expr>; + fn make_module(&self) -> Interned>; - // TODO: add other inputs + fn input(&self, this: Expr) -> Expr>; + fn cancel_input( &self, this: Expr, @@ -214,10 +243,21 @@ impl UnitTrait for DynUnit { self.unit_kind } + fn extract_mop( + &self, + mop: Expr, DynSize>>, + ) -> Expr> { + self.unit.extract_mop(mop) + } + fn make_module(&self) -> Interned> { self.unit.make_module() } + fn input(&self, this: Expr) -> Expr> { + self.unit.input(this) + } + fn cancel_input( &self, this: Expr, @@ -265,10 +305,21 @@ impl UnitTrait for DynUnitWrapper, DynSize>>, + ) -> Expr> { + Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop))) + } + fn make_module(&self) -> Interned> { self.0.make_module().canonical().intern_sized() } + fn input(&self, this: Expr) -> Expr> { + Expr::from_bundle(Expr::as_bundle(self.0.input(Expr::from_bundle(this)))) + } + fn cancel_input( &self, this: Expr, diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index d98ca40..2a09588 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -3,8 +3,8 @@ use crate::{ config::CpuConfig, - instruction::AluBranchMOp, - unit::{DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitOutput, UnitTrait}, + instruction::{AluBranchMOp, UnitOutRegNum}, + unit::{DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitMOp, UnitOutput, UnitTrait}, }; use fayalite::{ intern::{Intern, Interned}, @@ -16,7 +16,11 @@ use fayalite::{ pub fn alu_branch(config: &CpuConfig) { #[hdl] let cd: ClockDomain = m.input(); + #[hdl] + let input: ReadyValid, DynSize>> = + m.input(ReadyValid[AluBranchMOp[config.unit_out_reg_num()][config.p_reg_num_width()]]); // TODO: finish + connect(input.ready, true); } #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] @@ -37,7 +41,7 @@ impl AluBranch { impl UnitTrait for AluBranch { type Type = alu_branch; type ExtraOut = (); - type MOp = AluBranchMOp; + type MOp = AluBranchMOp, DynSize>; fn ty(&self) -> Self::Type { self.module.io_ty() @@ -48,17 +52,28 @@ impl UnitTrait for AluBranch { } fn mop_ty(&self) -> Self::MOp { - AluBranchMOp[self.config.p_reg_num().canonical().bit_width()] + self.module.io_ty().input.data.HdlSome } fn unit_kind(&self) -> UnitKind { UnitKind::AluBranch } + fn extract_mop( + &self, + mop: Expr, DynSize>>, + ) -> Expr> { + UnitMOp::alu_branch_mop(mop) + } + fn make_module(&self) -> Interned> { self.module } + fn input(&self, this: Expr) -> Expr> { + this.input + } + fn cancel_input( &self, this: Expr, diff --git a/crates/cpu/src/util.rs b/crates/cpu/src/util.rs index 9d18b31..e006bb1 100644 --- a/crates/cpu/src/util.rs +++ b/crates/cpu/src/util.rs @@ -5,7 +5,7 @@ pub mod tree_reduce; pub(crate) const fn range_u32_len(range: &std::ops::Range) -> usize { let retval = range.end.saturating_sub(range.start); - assert!(retval as usize as u32 != retval, "len overflowed"); + assert!(retval as usize as u32 == retval, "len overflowed"); retval as usize } diff --git a/crates/cpu/tests/expected/reg_alloc.txt b/crates/cpu/tests/expected/reg_alloc.txt index 7eb2c09..db4461e 100644 --- a/crates/cpu/tests/expected/reg_alloc.txt +++ b/crates/cpu/tests/expected/reg_alloc.txt @@ -4,7 +4,7 @@ Simulation { state_layout: StateLayout { ty: TypeLayout { small_slots: StatePartLayout { - len: 50, + len: 319, debug_data: [ SlotDebugData { name: "", @@ -29,6 +29,20 @@ Simulation { Logical, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -42,6 +56,20 @@ Simulation { SignExt8, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -62,6 +90,20 @@ Simulation { WriteL2Reg, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -76,6 +118,20 @@ Simulation { HdlSome, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -92,6 +148,20 @@ Simulation { Logical, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -105,6 +175,20 @@ Simulation { SignExt8, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -125,6 +209,20 @@ Simulation { WriteL2Reg, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -139,6 +237,20 @@ Simulation { HdlSome, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Enum { @@ -148,47 +260,239 @@ Simulation { }, SlotDebugData { name: "", - ty: Enum { - HdlNone, - HdlSome, - }, + ty: Bool, }, SlotDebugData { name: "", - ty: Enum { - HdlNone, - HdlSome, - }, + ty: Bool, }, SlotDebugData { name: "", - ty: Enum { - AluBranch, - L2RegisterFile, - LoadStore, - }, + ty: Bool, }, SlotDebugData { name: "", - ty: Enum { - HdlNone, - HdlSome, - }, + ty: Bool, }, SlotDebugData { name: "", - ty: Enum { - AluBranch, - L2RegisterFile, - LoadStore, - }, + ty: UInt<8>, }, SlotDebugData { name: "", - ty: Enum { - HdlNone, - HdlSome, - }, + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, }, SlotDebugData { name: "", @@ -208,6 +512,1044 @@ Simulation { HdlSome, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, SlotDebugData { name: "", ty: Bool, @@ -320,11 +1662,547 @@ Simulation { HdlSome, }, }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, ], .. }, big_slots: StatePartLayout { - len: 685, + len: 4696, debug_data: [ SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", @@ -338,7 +2216,7 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -349,7 +2227,7 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -368,11 +2246,11 @@ Simulation { ty: Bool, }, SlotDebugData { - name: ".uop", + name: ".mop", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, SlotDebugData { @@ -385,22 +2263,22 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<135>, + ty: UInt<145>, }, SlotDebugData { name: "", - ty: UInt<134>, + ty: UInt<144>, }, SlotDebugData { name: "", - ty: UInt<69>, + ty: UInt<79>, }, SlotDebugData { name: "", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, SlotDebugData { @@ -417,18 +2295,18 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<69>, + ty: UInt<79>, }, SlotDebugData { name: "", - ty: UInt<67>, + ty: UInt<77>, }, SlotDebugData { name: "", ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, }, SlotDebugData { @@ -436,9 +2314,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".alu_common.common.dest", + name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".alu_common.common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8>, @@ -493,9 +2389,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".common.dest", + name: ".common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".common.src[0]", ty: UInt<8>, @@ -534,9 +2448,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -559,28 +2491,126 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<67>, + ty: UInt<77>, }, SlotDebugData { name: "", - ty: UInt<65>, + ty: UInt<75>, }, SlotDebugData { name: "", - ty: UInt<61>, + ty: UInt<71>, }, SlotDebugData { name: "", - ty: UInt<58>, + ty: UInt<68>, }, SlotDebugData { name: "", ty: UInt<0>, }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, SlotDebugData { name: "", ty: UInt<8>, }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: "[0]", ty: UInt<8>, @@ -675,9 +2705,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".alu_common.common.dest", + name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".alu_common.common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8>, @@ -721,13 +2769,13 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, }, SlotDebugData { @@ -735,9 +2783,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".common.dest", + name: ".common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".common.src[0]", ty: UInt<8>, @@ -763,9 +2829,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -788,15 +2872,99 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, }, SlotDebugData { name: "", @@ -804,7 +2972,21 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<8>, + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, SlotDebugData { name: "[0]", @@ -849,8 +3031,8 @@ Simulation { SlotDebugData { name: "", ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, }, SlotDebugData { @@ -858,9 +3040,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -883,11 +3083,95 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, }, SlotDebugData { name: "", @@ -895,7 +3179,21 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<8>, + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, SlotDebugData { name: "[0]", @@ -938,11 +3236,11 @@ Simulation { ty: SInt<1>, }, SlotDebugData { - name: ".uop", + name: ".mop", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, SlotDebugData { @@ -955,22 +3253,22 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<135>, + ty: UInt<145>, }, SlotDebugData { name: "", - ty: UInt<134>, + ty: UInt<144>, }, SlotDebugData { name: "", - ty: UInt<69>, + ty: UInt<79>, }, SlotDebugData { name: "", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, SlotDebugData { @@ -987,18 +3285,18 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<69>, + ty: UInt<79>, }, SlotDebugData { name: "", - ty: UInt<67>, + ty: UInt<77>, }, SlotDebugData { name: "", ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, }, SlotDebugData { @@ -1006,9 +3304,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".alu_common.common.dest", + name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".alu_common.common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8>, @@ -1063,9 +3379,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".common.dest", + name: ".common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".common.src[0]", ty: UInt<8>, @@ -1104,9 +3438,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -1129,28 +3481,126 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<67>, + ty: UInt<77>, }, SlotDebugData { name: "", - ty: UInt<65>, + ty: UInt<75>, }, SlotDebugData { name: "", - ty: UInt<61>, + ty: UInt<71>, }, SlotDebugData { name: "", - ty: UInt<58>, + ty: UInt<68>, }, SlotDebugData { name: "", ty: UInt<0>, }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, SlotDebugData { name: "", ty: UInt<8>, }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: "[0]", ty: UInt<8>, @@ -1245,9 +3695,27 @@ Simulation { ty: UInt<0>, }, SlotDebugData { - name: ".alu_common.common.dest", + name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".alu_common.common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".alu_common.common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8>, @@ -1291,13 +3759,13 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, }, SlotDebugData { @@ -1305,9 +3773,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".common.dest", + name: ".common.dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".common.dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".common.dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".common.src[0]", ty: UInt<8>, @@ -1333,9 +3819,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -1358,15 +3862,99 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, }, SlotDebugData { name: "", @@ -1374,7 +3962,21 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<8>, + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, SlotDebugData { name: "[0]", @@ -1419,8 +4021,8 @@ Simulation { SlotDebugData { name: "", ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, }, SlotDebugData { @@ -1428,9 +4030,27 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".dest", + name: ".dest.normal_regs[0].value", ty: UInt<8>, }, + SlotDebugData { + name: ".dest.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".dest.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".dest.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, SlotDebugData { name: ".src[0]", ty: UInt<8>, @@ -1453,11 +4073,95 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<60>, + ty: UInt<70>, }, SlotDebugData { name: "", - ty: UInt<59>, + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: ".flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<16>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, }, SlotDebugData { name: "", @@ -1465,7 +4169,21 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<8>, + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, SlotDebugData { name: "[0]", @@ -1522,6 +4240,246 @@ Simulation { ICacheFlush, }, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.addr", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_out_reg.value", + ty: UInt<4>, + }, SlotDebugData { name: "", ty: UInt<2>, @@ -1537,55 +4495,1279 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", + ty: Bool, + }, SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[0]", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(UInt<2>), }, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[1]", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(UInt<2>), }, }, SlotDebugData { - name: ".value", - ty: UInt<1>, + name: "", + ty: UInt<3>, }, SlotDebugData { name: "", ty: UInt<2>, }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[0]", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[1]", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, SlotDebugData { name: "", ty: UInt<1>, }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", ty: UInt<1>, }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", - ty: UInt<1>, + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, }, SlotDebugData { name: "", - ty: UInt<1>, + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, }, SlotDebugData { name: "", @@ -1595,10 +5777,732 @@ Simulation { name: "[0]", ty: Bool, }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, SlotDebugData { name: "", ty: Bool, }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<32>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<32>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<32>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<32>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum { @@ -1644,19 +6548,310 @@ Simulation { ty: Bool, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(Bundle {}), }, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, SlotDebugData { name: ".value", - ty: UInt<1>, + ty: UInt<4>, }, SlotDebugData { name: "", - ty: UInt<2>, + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, }, SlotDebugData { name: "", @@ -1664,23 +6859,4418 @@ Simulation { }, SlotDebugData { name: "", - ty: UInt<1>, + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, }, SlotDebugData { name: "", ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, }, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", + name: "", ty: UInt<1>, }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, SlotDebugData { name: "", ty: UInt<64>, }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".1.add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<26>, + }, + SlotDebugData { + name: "", + ty: UInt<26>, + }, + SlotDebugData { + name: "", + ty: SInt<26>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".1.add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.lut", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_1", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<32>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, SlotDebugData { name: "", ty: UInt<1>, @@ -1690,32 +11280,596 @@ Simulation { ty: UInt<1>, }, SlotDebugData { - name: ".1.value", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", + name: ".1.unit_num.adj_value", ty: UInt<2>, }, SlotDebugData { - name: "", - ty: UInt<2>, + name: ".1.unit_out_reg.value", + ty: UInt<4>, }, SlotDebugData { name: "", - ty: UInt<2>, + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, }, SlotDebugData { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), }, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum { @@ -1729,57 +11883,3890 @@ Simulation { ty: Bool, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(Bundle {}), }, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, SlotDebugData { name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", ty: UInt<1>, }, SlotDebugData { name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2>, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".1.add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, SlotDebugData { name: "", - ty: UInt<1>, + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { - name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", + name: "", + ty: UInt<26>, + }, + SlotDebugData { + name: "", + ty: UInt<26>, + }, + SlotDebugData { + name: "", + ty: SInt<26>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", ty: UInt<1>, }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".1.invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".1.add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<53>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<54>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".1.alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".1.alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".1.lut", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<22>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<47>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, SlotDebugData { name: ".0", ty: UInt<1>, }, SlotDebugData { - name: ".1.value", + name: ".1.common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", ty: UInt<1>, }, SlotDebugData { name: "", - ty: UInt<2>, + ty: UInt<34>, }, SlotDebugData { name: "", - ty: UInt<2>, + ty: UInt<34>, }, SlotDebugData { name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2>, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".value", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".1.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".1.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".1.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".reversed_src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<33>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: SInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<34>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<12>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<23>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<49>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<50>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<52>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, SlotDebugData { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_0", + ty: UInt<2>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_1", + ty: UInt<2>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), }, }, SlotDebugData { @@ -1790,6 +15777,17 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.ready", + ty: Bool, + }, SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.clk", ty: Clock, @@ -1798,6 +15796,641 @@ Simulation { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.rst", ty: SyncReset, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.data", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock, @@ -2160,10 +16793,6 @@ Simulation { name: "[0]", ty: UInt<0>, }, - SlotDebugData { - name: "", - ty: UInt<0>, - }, SlotDebugData { name: "", ty: UInt<1>, @@ -2176,10 +16805,6 @@ Simulation { name: "", ty: UInt<0>, }, - SlotDebugData { - name: "", - ty: UInt<64>, - }, SlotDebugData { name: "", ty: UInt<65>, @@ -3246,6 +17871,17 @@ Simulation { name: "", ty: UInt<4>, }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, SlotDebugData { name: "", ty: Bool, @@ -3254,4084 +17890,37643 @@ Simulation { name: "", ty: Bool, }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.data", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".1.unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".unit_num.adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: ".unit_out_reg.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".adj_value", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: UInt<7>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<55>, + }, + SlotDebugData { + name: "", + ty: UInt<51>, + }, + SlotDebugData { + name: "", + ty: UInt<48>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: ".value", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<18>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<6>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest.value", + ty: UInt<4>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<6>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<57>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, ], .. }, }, memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], + len: 2, + debug_data: [ + (), + (), + ], + layout_data: [ + MemoryData { + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + data: [ + // len = 0xfd + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + [0x4]: 0x00, + [0x5]: 0x00, + [0x6]: 0x00, + [0x7]: 0x00, + [0x8]: 0x00, + [0x9]: 0x00, + [0xa]: 0x00, + [0xb]: 0x00, + [0xc]: 0x00, + [0xd]: 0x00, + [0xe]: 0x00, + [0xf]: 0x00, + [0x10]: 0x00, + [0x11]: 0x00, + [0x12]: 0x00, + [0x13]: 0x00, + [0x14]: 0x00, + [0x15]: 0x00, + [0x16]: 0x00, + [0x17]: 0x00, + [0x18]: 0x00, + [0x19]: 0x00, + [0x1a]: 0x00, + [0x1b]: 0x00, + [0x1c]: 0x00, + [0x1d]: 0x00, + [0x1e]: 0x00, + [0x1f]: 0x00, + [0x20]: 0x00, + [0x21]: 0x00, + [0x22]: 0x00, + [0x23]: 0x00, + [0x24]: 0x00, + [0x25]: 0x00, + [0x26]: 0x00, + [0x27]: 0x00, + [0x28]: 0x00, + [0x29]: 0x00, + [0x2a]: 0x00, + [0x2b]: 0x00, + [0x2c]: 0x00, + [0x2d]: 0x00, + [0x2e]: 0x00, + [0x2f]: 0x00, + [0x30]: 0x00, + [0x31]: 0x00, + [0x32]: 0x00, + [0x33]: 0x00, + [0x34]: 0x00, + [0x35]: 0x00, + [0x36]: 0x00, + [0x37]: 0x00, + [0x38]: 0x00, + [0x39]: 0x00, + [0x3a]: 0x00, + [0x3b]: 0x00, + [0x3c]: 0x00, + [0x3d]: 0x00, + [0x3e]: 0x00, + [0x3f]: 0x00, + [0x40]: 0x00, + [0x41]: 0x00, + [0x42]: 0x00, + [0x43]: 0x00, + [0x44]: 0x00, + [0x45]: 0x00, + [0x46]: 0x00, + [0x47]: 0x00, + [0x48]: 0x00, + [0x49]: 0x00, + [0x4a]: 0x00, + [0x4b]: 0x00, + [0x4c]: 0x00, + [0x4d]: 0x00, + [0x4e]: 0x00, + [0x4f]: 0x00, + [0x50]: 0x00, + [0x51]: 0x00, + [0x52]: 0x00, + [0x53]: 0x00, + [0x54]: 0x00, + [0x55]: 0x00, + [0x56]: 0x00, + [0x57]: 0x00, + [0x58]: 0x00, + [0x59]: 0x00, + [0x5a]: 0x00, + [0x5b]: 0x00, + [0x5c]: 0x00, + [0x5d]: 0x00, + [0x5e]: 0x00, + [0x5f]: 0x00, + [0x60]: 0x00, + [0x61]: 0x00, + [0x62]: 0x00, + [0x63]: 0x00, + [0x64]: 0x00, + [0x65]: 0x00, + [0x66]: 0x00, + [0x67]: 0x00, + [0x68]: 0x00, + [0x69]: 0x00, + [0x6a]: 0x00, + [0x6b]: 0x00, + [0x6c]: 0x00, + [0x6d]: 0x00, + [0x6e]: 0x00, + [0x6f]: 0x00, + [0x70]: 0x00, + [0x71]: 0x00, + [0x72]: 0x00, + [0x73]: 0x00, + [0x74]: 0x00, + [0x75]: 0x00, + [0x76]: 0x00, + [0x77]: 0x00, + [0x78]: 0x00, + [0x79]: 0x00, + [0x7a]: 0x00, + [0x7b]: 0x00, + [0x7c]: 0x00, + [0x7d]: 0x00, + [0x7e]: 0x00, + [0x7f]: 0x00, + [0x80]: 0x00, + [0x81]: 0x00, + [0x82]: 0x00, + [0x83]: 0x00, + [0x84]: 0x00, + [0x85]: 0x00, + [0x86]: 0x00, + [0x87]: 0x00, + [0x88]: 0x00, + [0x89]: 0x00, + [0x8a]: 0x00, + [0x8b]: 0x00, + [0x8c]: 0x00, + [0x8d]: 0x00, + [0x8e]: 0x00, + [0x8f]: 0x00, + [0x90]: 0x00, + [0x91]: 0x00, + [0x92]: 0x00, + [0x93]: 0x00, + [0x94]: 0x00, + [0x95]: 0x00, + [0x96]: 0x00, + [0x97]: 0x00, + [0x98]: 0x00, + [0x99]: 0x00, + [0x9a]: 0x00, + [0x9b]: 0x00, + [0x9c]: 0x00, + [0x9d]: 0x00, + [0x9e]: 0x00, + [0x9f]: 0x00, + [0xa0]: 0x00, + [0xa1]: 0x00, + [0xa2]: 0x00, + [0xa3]: 0x00, + [0xa4]: 0x00, + [0xa5]: 0x00, + [0xa6]: 0x00, + [0xa7]: 0x00, + [0xa8]: 0x00, + [0xa9]: 0x00, + [0xaa]: 0x00, + [0xab]: 0x00, + [0xac]: 0x00, + [0xad]: 0x00, + [0xae]: 0x00, + [0xaf]: 0x00, + [0xb0]: 0x00, + [0xb1]: 0x00, + [0xb2]: 0x00, + [0xb3]: 0x00, + [0xb4]: 0x00, + [0xb5]: 0x00, + [0xb6]: 0x00, + [0xb7]: 0x00, + [0xb8]: 0x00, + [0xb9]: 0x00, + [0xba]: 0x00, + [0xbb]: 0x00, + [0xbc]: 0x00, + [0xbd]: 0x00, + [0xbe]: 0x00, + [0xbf]: 0x00, + [0xc0]: 0x00, + [0xc1]: 0x00, + [0xc2]: 0x00, + [0xc3]: 0x00, + [0xc4]: 0x00, + [0xc5]: 0x00, + [0xc6]: 0x00, + [0xc7]: 0x00, + [0xc8]: 0x00, + [0xc9]: 0x00, + [0xca]: 0x00, + [0xcb]: 0x00, + [0xcc]: 0x00, + [0xcd]: 0x00, + [0xce]: 0x00, + [0xcf]: 0x00, + [0xd0]: 0x00, + [0xd1]: 0x00, + [0xd2]: 0x00, + [0xd3]: 0x00, + [0xd4]: 0x00, + [0xd5]: 0x00, + [0xd6]: 0x00, + [0xd7]: 0x00, + [0xd8]: 0x00, + [0xd9]: 0x00, + [0xda]: 0x00, + [0xdb]: 0x00, + [0xdc]: 0x00, + [0xdd]: 0x00, + [0xde]: 0x00, + [0xdf]: 0x00, + [0xe0]: 0x00, + [0xe1]: 0x00, + [0xe2]: 0x00, + [0xe3]: 0x00, + [0xe4]: 0x00, + [0xe5]: 0x00, + [0xe6]: 0x00, + [0xe7]: 0x00, + [0xe8]: 0x00, + [0xe9]: 0x00, + [0xea]: 0x00, + [0xeb]: 0x00, + [0xec]: 0x00, + [0xed]: 0x00, + [0xee]: 0x00, + [0xef]: 0x00, + [0xf0]: 0x00, + [0xf1]: 0x00, + [0xf2]: 0x00, + [0xf3]: 0x00, + [0xf4]: 0x00, + [0xf5]: 0x00, + [0xf6]: 0x00, + [0xf7]: 0x00, + [0xf8]: 0x00, + [0xf9]: 0x00, + [0xfa]: 0x00, + [0xfb]: 0x00, + [0xfc]: 0x00, + ], + }, + MemoryData { + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], .. }, }, insns: [ - // at: reg_alloc.rs:152:9 + // at: reg_alloc.rs:288:9 0: Copy { - dest: StatePartIndex(327), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + dest: StatePartIndex(4058), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.clk", ty: Clock }, src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, 1: Copy { - dest: StatePartIndex(328), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + dest: StatePartIndex(4059), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.rst", ty: SyncReset }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, }, - // at: reg_alloc.rs:150:13 + // at: reg_alloc.rs:286:13 2: Copy { - dest: StatePartIndex(333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, - src: StatePartIndex(327), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + dest: StatePartIndex(4064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, + src: StatePartIndex(4058), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.clk", ty: Clock }, }, 3: Copy { - dest: StatePartIndex(334), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, - src: StatePartIndex(328), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + dest: StatePartIndex(4065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, + src: StatePartIndex(4059), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.cd.rst", ty: SyncReset }, }, // at: unit_free_regs_tracker.rs:7:1 - 4: Const { - dest: StatePartIndex(665), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, - value: 0x8, - }, - 5: NotU { - dest: StatePartIndex(606), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(358), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + 4: NotU { + dest: StatePartIndex(4313), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4089), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, width: 1, }, - 6: Copy { - dest: StatePartIndex(607), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(606), // (0x0) SlotDebugData { name: "", ty: Bool }, + 5: Copy { + dest: StatePartIndex(4314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4313), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 7: CastToUInt { - dest: StatePartIndex(608), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(607), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 6: CastToUInt { + dest: StatePartIndex(4315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 8: NotU { - dest: StatePartIndex(603), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(357), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + 7: NotU { + dest: StatePartIndex(4310), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4088), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, width: 1, }, - 9: Copy { - dest: StatePartIndex(604), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(603), // (0x0) SlotDebugData { name: "", ty: Bool }, + 8: Copy { + dest: StatePartIndex(4311), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4310), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 10: CastToUInt { - dest: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(604), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 9: CastToUInt { + dest: StatePartIndex(4312), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4311), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 11: Add { - dest: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(608), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 10: Add { + dest: StatePartIndex(4316), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4312), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 12: CastToUInt { - dest: StatePartIndex(610), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 11: CastToUInt { + dest: StatePartIndex(4317), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4316), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 13: Copy { - dest: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, - src: StatePartIndex(610), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 12: Copy { + dest: StatePartIndex(4309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + src: StatePartIndex(4317), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 14: CmpNe { - dest: StatePartIndex(612), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + 13: CmpNe { + dest: StatePartIndex(4319), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4316), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, }, - 15: NotU { - dest: StatePartIndex(586), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(356), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + 14: NotU { + dest: StatePartIndex(4293), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4087), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, width: 1, }, - 16: Copy { - dest: StatePartIndex(587), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(586), // (0x0) SlotDebugData { name: "", ty: Bool }, + 15: Copy { + dest: StatePartIndex(4294), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4293), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 17: CastToUInt { - dest: StatePartIndex(588), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(587), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 16: CastToUInt { + dest: StatePartIndex(4295), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4294), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 18: NotU { - dest: StatePartIndex(583), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(355), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + 17: NotU { + dest: StatePartIndex(4290), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4086), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, width: 1, }, - 19: Copy { - dest: StatePartIndex(584), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(583), // (0x0) SlotDebugData { name: "", ty: Bool }, + 18: Copy { + dest: StatePartIndex(4291), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4290), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 20: CastToUInt { - dest: StatePartIndex(585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(584), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 19: CastToUInt { + dest: StatePartIndex(4292), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4291), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 21: Add { - dest: StatePartIndex(589), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(588), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 20: Add { + dest: StatePartIndex(4296), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4292), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4295), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 22: CastToUInt { - dest: StatePartIndex(590), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(589), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 21: CastToUInt { + dest: StatePartIndex(4297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4296), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 23: Copy { - dest: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, - src: StatePartIndex(590), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 22: Copy { + dest: StatePartIndex(4289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + src: StatePartIndex(4297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 24: Add { - dest: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, - rhs: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + 23: Add { + dest: StatePartIndex(4330), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + rhs: StatePartIndex(4309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, }, - 25: CastToUInt { - dest: StatePartIndex(624), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 24: CastToUInt { + dest: StatePartIndex(4331), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4330), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 26: Copy { - dest: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, - src: StatePartIndex(624), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 25: Copy { + dest: StatePartIndex(4329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + src: StatePartIndex(4331), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 + 26: CmpNe { + dest: StatePartIndex(4333), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4330), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + }, 27: CmpNe { - dest: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + dest: StatePartIndex(4299), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4296), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, }, - 28: CmpNe { - dest: StatePartIndex(592), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(589), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, - }, - 29: NotU { - dest: StatePartIndex(551), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(354), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + 28: NotU { + dest: StatePartIndex(4258), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4085), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, width: 1, }, - 30: Copy { - dest: StatePartIndex(552), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(551), // (0x0) SlotDebugData { name: "", ty: Bool }, + 29: Copy { + dest: StatePartIndex(4259), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4258), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 31: CastToUInt { - dest: StatePartIndex(553), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(552), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 30: CastToUInt { + dest: StatePartIndex(4260), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4259), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 32: NotU { - dest: StatePartIndex(548), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(353), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + 31: NotU { + dest: StatePartIndex(4255), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4084), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, width: 1, }, - 33: Copy { - dest: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(548), // (0x0) SlotDebugData { name: "", ty: Bool }, + 32: Copy { + dest: StatePartIndex(4256), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4255), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 34: CastToUInt { - dest: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 33: CastToUInt { + dest: StatePartIndex(4257), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4256), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 35: Add { - dest: StatePartIndex(554), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(553), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 34: Add { + dest: StatePartIndex(4261), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4257), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4260), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 36: CastToUInt { - dest: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(554), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 35: CastToUInt { + dest: StatePartIndex(4262), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4261), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 37: Copy { - dest: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, - src: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 36: Copy { + dest: StatePartIndex(4254), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + src: StatePartIndex(4262), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 38: CmpNe { - dest: StatePartIndex(557), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(554), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + 37: CmpNe { + dest: StatePartIndex(4264), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4261), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4254), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, }, - 39: NotU { - dest: StatePartIndex(531), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(352), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + 38: NotU { + dest: StatePartIndex(4238), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4083), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, width: 1, }, - 40: Copy { - dest: StatePartIndex(532), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(531), // (0x0) SlotDebugData { name: "", ty: Bool }, + 39: Copy { + dest: StatePartIndex(4239), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4238), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 41: CastToUInt { - dest: StatePartIndex(533), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(532), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 40: CastToUInt { + dest: StatePartIndex(4240), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4239), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 42: NotU { - dest: StatePartIndex(528), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(351), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + 41: NotU { + dest: StatePartIndex(4235), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4082), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, width: 1, }, - 43: Copy { - dest: StatePartIndex(529), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(528), // (0x0) SlotDebugData { name: "", ty: Bool }, + 42: Copy { + dest: StatePartIndex(4236), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4235), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 44: CastToUInt { - dest: StatePartIndex(530), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(529), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 43: CastToUInt { + dest: StatePartIndex(4237), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4236), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 45: Add { - dest: StatePartIndex(534), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(530), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(533), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 44: Add { + dest: StatePartIndex(4241), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4237), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4240), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 46: CastToUInt { - dest: StatePartIndex(535), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(534), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 45: CastToUInt { + dest: StatePartIndex(4242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4241), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 47: Copy { - dest: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, - src: StatePartIndex(535), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 46: Copy { + dest: StatePartIndex(4234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + src: StatePartIndex(4242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 48: Add { - dest: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, - rhs: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + 47: Add { + dest: StatePartIndex(4275), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + rhs: StatePartIndex(4254), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, }, - 49: CastToUInt { - dest: StatePartIndex(569), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 48: CastToUInt { + dest: StatePartIndex(4276), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4275), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 50: Copy { - dest: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, - src: StatePartIndex(569), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 49: Copy { + dest: StatePartIndex(4274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + src: StatePartIndex(4276), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 51: Add { - dest: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, - rhs: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + 50: Add { + dest: StatePartIndex(4345), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + rhs: StatePartIndex(4329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, }, - 52: CastToUInt { - dest: StatePartIndex(639), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 51: CastToUInt { + dest: StatePartIndex(4346), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4345), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 53: Copy { - dest: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, - src: StatePartIndex(639), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 52: Copy { + dest: StatePartIndex(4344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + src: StatePartIndex(4346), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 + 53: CmpNe { + dest: StatePartIndex(4348), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4345), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + }, 54: CmpNe { - dest: StatePartIndex(641), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + dest: StatePartIndex(4278), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4275), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, }, 55: CmpNe { - dest: StatePartIndex(571), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + dest: StatePartIndex(4244), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4241), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, }, - 56: CmpNe { - dest: StatePartIndex(537), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(534), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, - }, - 57: Const { - dest: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, - value: 0x4, - }, - 58: NotU { - dest: StatePartIndex(480), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(350), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + 56: NotU { + dest: StatePartIndex(4188), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4081), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, width: 1, }, - 59: Copy { - dest: StatePartIndex(481), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(480), // (0x0) SlotDebugData { name: "", ty: Bool }, + 57: Copy { + dest: StatePartIndex(4189), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4188), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 60: CastToUInt { - dest: StatePartIndex(482), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(481), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 58: CastToUInt { + dest: StatePartIndex(4190), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4189), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 61: NotU { - dest: StatePartIndex(477), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(349), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + 59: NotU { + dest: StatePartIndex(4185), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4080), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, width: 1, }, - 62: Copy { - dest: StatePartIndex(478), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(477), // (0x0) SlotDebugData { name: "", ty: Bool }, + 60: Copy { + dest: StatePartIndex(4186), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4185), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 61: CastToUInt { + dest: StatePartIndex(4187), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4186), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 62: Add { + dest: StatePartIndex(4191), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4187), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4190), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, 63: CastToUInt { - dest: StatePartIndex(479), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(478), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 64: Add { - dest: StatePartIndex(483), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(479), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(482), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 65: CastToUInt { - dest: StatePartIndex(484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(483), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(4192), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4191), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 66: Copy { - dest: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, - src: StatePartIndex(484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 64: Copy { + dest: StatePartIndex(4184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + src: StatePartIndex(4192), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 67: CmpNe { - dest: StatePartIndex(486), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(483), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + 65: CmpNe { + dest: StatePartIndex(4194), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4191), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, }, - 68: NotU { - dest: StatePartIndex(460), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(348), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + 66: NotU { + dest: StatePartIndex(4168), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4079), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, width: 1, }, - 69: Copy { - dest: StatePartIndex(461), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(460), // (0x0) SlotDebugData { name: "", ty: Bool }, + 67: Copy { + dest: StatePartIndex(4169), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4168), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 70: CastToUInt { - dest: StatePartIndex(462), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(461), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 68: CastToUInt { + dest: StatePartIndex(4170), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4169), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 71: NotU { - dest: StatePartIndex(457), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(347), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + 69: NotU { + dest: StatePartIndex(4165), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4078), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, width: 1, }, - 72: Copy { - dest: StatePartIndex(458), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(457), // (0x0) SlotDebugData { name: "", ty: Bool }, + 70: Copy { + dest: StatePartIndex(4166), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4165), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 71: CastToUInt { + dest: StatePartIndex(4167), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4166), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 72: Add { + dest: StatePartIndex(4171), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4167), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4170), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, 73: CastToUInt { - dest: StatePartIndex(459), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(458), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 74: Add { - dest: StatePartIndex(463), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(459), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(462), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 75: CastToUInt { - dest: StatePartIndex(464), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(463), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(4172), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4171), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 76: Copy { - dest: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, - src: StatePartIndex(464), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 74: Copy { + dest: StatePartIndex(4164), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + src: StatePartIndex(4172), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 77: Add { - dest: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, - rhs: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + 75: Add { + dest: StatePartIndex(4205), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4164), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + rhs: StatePartIndex(4184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, }, - 78: CastToUInt { - dest: StatePartIndex(498), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 76: CastToUInt { + dest: StatePartIndex(4206), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4205), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 79: Copy { - dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, - src: StatePartIndex(498), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 77: Copy { + dest: StatePartIndex(4204), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + src: StatePartIndex(4206), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 80: CmpNe { - dest: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + 78: CmpNe { + dest: StatePartIndex(4208), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4205), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4204), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, }, - 81: CmpNe { - dest: StatePartIndex(466), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(463), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + 79: CmpNe { + dest: StatePartIndex(4174), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4171), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4164), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, }, - 82: Const { - dest: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, - value: 0x2, + 80: NotU { + dest: StatePartIndex(4133), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4077), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + width: 1, + }, + 81: Copy { + dest: StatePartIndex(4134), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4133), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 82: CastToUInt { + dest: StatePartIndex(4135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4134), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, }, 83: NotU { - dest: StatePartIndex(424), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(346), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + dest: StatePartIndex(4130), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, width: 1, }, 84: Copy { - dest: StatePartIndex(425), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(424), // (0x0) SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(4131), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4130), // (0x0) SlotDebugData { name: "", ty: Bool }, }, 85: CastToUInt { - dest: StatePartIndex(426), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(425), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(4132), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4131), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 86: NotU { - dest: StatePartIndex(421), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(345), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, - width: 1, + 86: Add { + dest: StatePartIndex(4136), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4132), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 87: Copy { - dest: StatePartIndex(422), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(421), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 88: CastToUInt { - dest: StatePartIndex(423), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(422), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 89: Add { - dest: StatePartIndex(427), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(423), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(426), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 90: CastToUInt { - dest: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(427), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 87: CastToUInt { + dest: StatePartIndex(4137), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4136), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 + 88: Copy { + dest: StatePartIndex(4129), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + src: StatePartIndex(4137), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 89: CmpNe { + dest: StatePartIndex(4139), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4136), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4129), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 90: NotU { + dest: StatePartIndex(4113), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4075), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + width: 1, + }, 91: Copy { - dest: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, - src: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(4114), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4113), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - // at: unit_free_regs_tracker.rs:7:1 - 92: CmpNe { - dest: StatePartIndex(430), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(427), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, - }, - 93: Const { - dest: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - value: 0x1, - }, - 94: Const { - dest: StatePartIndex(413), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - value: 0x0, - }, - 95: Copy { - dest: StatePartIndex(412), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, - src: StatePartIndex(413), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - }, - 96: CastToUInt { - dest: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(412), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, + 92: CastToUInt { + dest: StatePartIndex(4115), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4114), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, dest_width: 1, }, - 97: NotU { - dest: StatePartIndex(400), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(344), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + 93: NotU { + dest: StatePartIndex(4110), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, width: 1, }, + 94: Copy { + dest: StatePartIndex(4111), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4110), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 95: CastToUInt { + dest: StatePartIndex(4112), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4111), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 96: Add { + dest: StatePartIndex(4116), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4112), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(4115), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 97: CastToUInt { + dest: StatePartIndex(4117), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4116), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 98: Copy { - dest: StatePartIndex(401), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(400), // (0x0) SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(4109), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + src: StatePartIndex(4117), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 99: CastToUInt { - dest: StatePartIndex(402), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(401), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + // at: unit_free_regs_tracker.rs:7:1 + 99: Add { + dest: StatePartIndex(4150), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4109), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + rhs: StatePartIndex(4129), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 100: CastToUInt { + dest: StatePartIndex(4151), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4150), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, - 100: NotU { - dest: StatePartIndex(397), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(343), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, - width: 1, - }, + // at: unit_free_regs_tracker.rs:63:13 101: Copy { - dest: StatePartIndex(398), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(397), // (0x0) SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(4149), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + src: StatePartIndex(4151), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 102: CastToUInt { - dest: StatePartIndex(399), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(398), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, + // at: unit_free_regs_tracker.rs:7:1 + 102: Add { + dest: StatePartIndex(4220), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4149), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + rhs: StatePartIndex(4204), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, }, - 103: Add { - dest: StatePartIndex(403), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(399), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(402), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 104: CastToUInt { - dest: StatePartIndex(404), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(403), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 103: CastToUInt { + dest: StatePartIndex(4221), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4220), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 105: Copy { - dest: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, - src: StatePartIndex(404), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 104: Copy { + dest: StatePartIndex(4219), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + src: StatePartIndex(4221), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 106: Add { - dest: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, - rhs: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + 105: Add { + dest: StatePartIndex(4360), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(4219), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + rhs: StatePartIndex(4344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, }, - 107: CastToUInt { - dest: StatePartIndex(442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + 106: CastToUInt { + dest: StatePartIndex(4361), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4360), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 1, }, // at: unit_free_regs_tracker.rs:63:13 - 108: Copy { - dest: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, - src: StatePartIndex(442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 107: Copy { + dest: StatePartIndex(4359), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + src: StatePartIndex(4361), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: unit_free_regs_tracker.rs:7:1 - 109: Add { - dest: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, - rhs: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + 108: CmpNe { + dest: StatePartIndex(4363), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4360), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4359), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, }, - 110: CastToUInt { - dest: StatePartIndex(513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - dest_width: 1, + 109: CmpNe { + dest: StatePartIndex(4223), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4220), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4219), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:63:13 - 111: Copy { - dest: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, - src: StatePartIndex(513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 110: CmpNe { + dest: StatePartIndex(4153), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4150), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4149), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 112: Add { - dest: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, - rhs: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + 111: CmpNe { + dest: StatePartIndex(4119), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4116), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(4109), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, }, - 113: CastToUInt { - dest: StatePartIndex(654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - dest_width: 1, + // at: unit_free_regs_tracker.rs:27:25 + 112: IsNonZeroDestIsSmall { + dest: StatePartIndex(281), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, }, - // at: unit_free_regs_tracker.rs:63:13 - 114: Copy { - dest: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, - src: StatePartIndex(654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 113: IsNonZeroDestIsSmall { + dest: StatePartIndex(280), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:7:1 - 115: CmpNe { - dest: StatePartIndex(656), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + 114: AndSmall { + dest: StatePartIndex(279), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(280), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(278), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 116: CmpNe { - dest: StatePartIndex(515), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + // at: reg_alloc.rs:273:9 + 115: Copy { + dest: StatePartIndex(3914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - 117: CmpNe { - dest: StatePartIndex(444), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + 116: Copy { + dest: StatePartIndex(3915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.rst", ty: SyncReset }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, }, - 118: CmpNe { - dest: StatePartIndex(406), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(403), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + // at: reg_alloc.rs:271:13 + 117: Copy { + dest: StatePartIndex(3918), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::cd.clk", ty: Clock }, + src: StatePartIndex(3914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.clk", ty: Clock }, }, + 118: Copy { + dest: StatePartIndex(3919), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::cd.rst", ty: SyncReset }, + src: StatePartIndex(3915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.cd.rst", ty: SyncReset }, + }, + // at: reg_alloc.rs:43:1 119: Const { - dest: StatePartIndex(394), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + dest: StatePartIndex(3734), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, value: 0x0, }, 120: Copy { - dest: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(394), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + dest: StatePartIndex(3735), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3734), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, }, - // at: ready_valid.rs:31:9 - 121: Copy { - dest: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 121: Const { + dest: StatePartIndex(3583), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + value: 0x0, }, 122: Copy { - dest: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + dest: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3583), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, }, - // at: reg_alloc.rs:154:9 + // at: reg_alloc.rs:295:9 123: Copy { - dest: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + dest: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, }, - // at: reg_alloc.rs:150:13 + // at: unit.rs:127:1 124: Copy { - dest: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + dest: StatePartIndex(3656), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, }, - 125: AndBigWithSmallImmediate { - dest: StatePartIndex(48), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 125: Copy { + dest: StatePartIndex(3831), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:295:9 + 126: Copy { + dest: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: unit.rs:127:1 + 127: Copy { + dest: StatePartIndex(4460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 128: Copy { + dest: StatePartIndex(4620), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:288:9 + 129: Copy { + dest: StatePartIndex(3229), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + 130: Copy { + dest: StatePartIndex(3230), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, + }, + // at: reg_alloc.rs:286:13 + 131: Copy { + dest: StatePartIndex(3235), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, + src: StatePartIndex(3229), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + }, + 132: Copy { + dest: StatePartIndex(3236), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, + src: StatePartIndex(3230), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 133: Const { + dest: StatePartIndex(3565), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x8, + }, + 134: NotU { + dest: StatePartIndex(3506), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3260), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + width: 1, + }, + 135: Copy { + dest: StatePartIndex(3507), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3506), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 136: CastToUInt { + dest: StatePartIndex(3508), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3507), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 137: NotU { + dest: StatePartIndex(3503), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3259), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + width: 1, + }, + 138: Copy { + dest: StatePartIndex(3504), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3503), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 139: CastToUInt { + dest: StatePartIndex(3505), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3504), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 140: Add { + dest: StatePartIndex(3509), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3505), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3508), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 141: CastToUInt { + dest: StatePartIndex(3510), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3509), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 142: Copy { + dest: StatePartIndex(3502), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + src: StatePartIndex(3510), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 143: CmpNe { + dest: StatePartIndex(3512), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3509), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3502), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + }, + 144: NotU { + dest: StatePartIndex(3486), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3258), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + width: 1, + }, + 145: Copy { + dest: StatePartIndex(3487), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3486), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 146: CastToUInt { + dest: StatePartIndex(3488), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3487), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 147: NotU { + dest: StatePartIndex(3483), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3257), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + width: 1, + }, + 148: Copy { + dest: StatePartIndex(3484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3483), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 149: CastToUInt { + dest: StatePartIndex(3485), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 150: Add { + dest: StatePartIndex(3489), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3485), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3488), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 151: CastToUInt { + dest: StatePartIndex(3490), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3489), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 152: Copy { + dest: StatePartIndex(3482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + src: StatePartIndex(3490), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 153: Add { + dest: StatePartIndex(3523), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + rhs: StatePartIndex(3502), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + }, + 154: CastToUInt { + dest: StatePartIndex(3524), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3523), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 155: Copy { + dest: StatePartIndex(3522), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + src: StatePartIndex(3524), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 156: CmpNe { + dest: StatePartIndex(3526), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3523), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3522), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + }, + 157: CmpNe { + dest: StatePartIndex(3492), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3489), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + }, + 158: NotU { + dest: StatePartIndex(3451), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3256), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + width: 1, + }, + 159: Copy { + dest: StatePartIndex(3452), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3451), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 160: CastToUInt { + dest: StatePartIndex(3453), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3452), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 161: NotU { + dest: StatePartIndex(3448), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3255), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + width: 1, + }, + 162: Copy { + dest: StatePartIndex(3449), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3448), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 163: CastToUInt { + dest: StatePartIndex(3450), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3449), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 164: Add { + dest: StatePartIndex(3454), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3450), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3453), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 165: CastToUInt { + dest: StatePartIndex(3455), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3454), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 166: Copy { + dest: StatePartIndex(3447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + src: StatePartIndex(3455), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 167: CmpNe { + dest: StatePartIndex(3457), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3454), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + }, + 168: NotU { + dest: StatePartIndex(3431), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3254), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + width: 1, + }, + 169: Copy { + dest: StatePartIndex(3432), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3431), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 170: CastToUInt { + dest: StatePartIndex(3433), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3432), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 171: NotU { + dest: StatePartIndex(3428), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3253), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + width: 1, + }, + 172: Copy { + dest: StatePartIndex(3429), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3428), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 173: CastToUInt { + dest: StatePartIndex(3430), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3429), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 174: Add { + dest: StatePartIndex(3434), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3430), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3433), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 175: CastToUInt { + dest: StatePartIndex(3435), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3434), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 176: Copy { + dest: StatePartIndex(3427), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + src: StatePartIndex(3435), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 177: Add { + dest: StatePartIndex(3468), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3427), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + rhs: StatePartIndex(3447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + }, + 178: CastToUInt { + dest: StatePartIndex(3469), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3468), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 179: Copy { + dest: StatePartIndex(3467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + src: StatePartIndex(3469), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 180: Add { + dest: StatePartIndex(3538), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + rhs: StatePartIndex(3522), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + }, + 181: CastToUInt { + dest: StatePartIndex(3539), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3538), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 182: Copy { + dest: StatePartIndex(3537), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + src: StatePartIndex(3539), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 183: CmpNe { + dest: StatePartIndex(3541), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3538), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3537), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + }, + 184: CmpNe { + dest: StatePartIndex(3471), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3468), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + }, + 185: CmpNe { + dest: StatePartIndex(3437), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3434), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3427), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + }, + 186: Const { + dest: StatePartIndex(3424), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 187: NotU { + dest: StatePartIndex(3380), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3252), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + width: 1, + }, + 188: Copy { + dest: StatePartIndex(3381), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3380), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 189: CastToUInt { + dest: StatePartIndex(3382), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3381), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 190: NotU { + dest: StatePartIndex(3377), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3251), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + width: 1, + }, + 191: Copy { + dest: StatePartIndex(3378), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3377), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 192: CastToUInt { + dest: StatePartIndex(3379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3378), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 193: Add { + dest: StatePartIndex(3383), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3382), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 194: CastToUInt { + dest: StatePartIndex(3384), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3383), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 195: Copy { + dest: StatePartIndex(3376), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + src: StatePartIndex(3384), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 196: CmpNe { + dest: StatePartIndex(3386), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3383), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3376), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + }, + 197: NotU { + dest: StatePartIndex(3360), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3250), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + width: 1, + }, + 198: Copy { + dest: StatePartIndex(3361), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3360), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 199: CastToUInt { + dest: StatePartIndex(3362), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3361), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 200: NotU { + dest: StatePartIndex(3357), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3249), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + width: 1, + }, + 201: Copy { + dest: StatePartIndex(3358), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3357), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 202: CastToUInt { + dest: StatePartIndex(3359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3358), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 203: Add { + dest: StatePartIndex(3363), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3362), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 204: CastToUInt { + dest: StatePartIndex(3364), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3363), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 205: Copy { + dest: StatePartIndex(3356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + src: StatePartIndex(3364), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 206: Add { + dest: StatePartIndex(3397), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + rhs: StatePartIndex(3376), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + }, + 207: CastToUInt { + dest: StatePartIndex(3398), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3397), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 208: Copy { + dest: StatePartIndex(3396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + src: StatePartIndex(3398), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 209: CmpNe { + dest: StatePartIndex(3400), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3397), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + }, + 210: CmpNe { + dest: StatePartIndex(3366), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3363), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + }, + 211: Const { + dest: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + // at: reg_alloc.rs:43:1 + 212: CastToUInt { + dest: StatePartIndex(4542), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 213: Copy { + dest: StatePartIndex(4541), // (0x2) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(4542), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 214: NotU { + dest: StatePartIndex(3324), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3248), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + width: 1, + }, + 215: Copy { + dest: StatePartIndex(3325), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3324), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 216: CastToUInt { + dest: StatePartIndex(3326), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3325), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 217: NotU { + dest: StatePartIndex(3321), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + width: 1, + }, + 218: Copy { + dest: StatePartIndex(3322), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3321), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 219: CastToUInt { + dest: StatePartIndex(3323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3322), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 220: Add { + dest: StatePartIndex(3327), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3326), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 221: CastToUInt { + dest: StatePartIndex(3328), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3327), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 222: Copy { + dest: StatePartIndex(3320), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + src: StatePartIndex(3328), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 223: CmpNe { + dest: StatePartIndex(3330), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3327), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3320), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 224: NotU { + dest: StatePartIndex(3302), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3246), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + width: 1, + }, + 225: Copy { + dest: StatePartIndex(3303), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3302), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 226: CastToUInt { + dest: StatePartIndex(3304), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3303), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 227: NotU { + dest: StatePartIndex(3299), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3245), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + width: 1, + }, + 228: Copy { + dest: StatePartIndex(3300), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3299), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 229: CastToUInt { + dest: StatePartIndex(3301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3300), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 230: Add { + dest: StatePartIndex(3305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3304), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 231: CastToUInt { + dest: StatePartIndex(3306), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 232: Copy { + dest: StatePartIndex(3298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + src: StatePartIndex(3306), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 233: Add { + dest: StatePartIndex(3341), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + rhs: StatePartIndex(3320), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 234: CastToUInt { + dest: StatePartIndex(3342), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3341), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 235: Copy { + dest: StatePartIndex(3340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + src: StatePartIndex(3342), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 236: Add { + dest: StatePartIndex(3412), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + rhs: StatePartIndex(3396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + }, + 237: CastToUInt { + dest: StatePartIndex(3413), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3412), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 238: Copy { + dest: StatePartIndex(3411), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + src: StatePartIndex(3413), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 239: Add { + dest: StatePartIndex(3553), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(3411), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + rhs: StatePartIndex(3537), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + }, + 240: CastToUInt { + dest: StatePartIndex(3554), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3553), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 241: Copy { + dest: StatePartIndex(3552), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + src: StatePartIndex(3554), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 242: CmpNe { + dest: StatePartIndex(3556), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3553), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3552), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + }, + 243: CmpNe { + dest: StatePartIndex(3415), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3412), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3411), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + }, + 244: CmpNe { + dest: StatePartIndex(3344), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3341), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + }, + 245: CmpNe { + dest: StatePartIndex(3308), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + }, + 246: Const { + dest: StatePartIndex(3296), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + value: 0x0, + }, + 247: Copy { + dest: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3296), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + // at: ready_valid.rs:31:9 + 248: Copy { + dest: StatePartIndex(3293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 249: Copy { + dest: StatePartIndex(3568), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:290:9 + 250: Copy { + dest: StatePartIndex(3231), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:286:13 + 251: Copy { + dest: StatePartIndex(3237), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3231), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 252: AndBigWithSmallImmediate { + dest: StatePartIndex(250), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3231), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, rhs: 0x1, }, - // at: reg_alloc.rs:41:1 - 126: Copy { - dest: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + // at: reg_alloc.rs:43:1 + 253: Copy { + dest: StatePartIndex(3579), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3231), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, }, - 127: SliceInt { - dest: StatePartIndex(680), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + 254: SliceInt { + dest: StatePartIndex(3580), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3579), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: ready_valid.rs:31:9 + 255: Copy { + dest: StatePartIndex(4106), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 256: Copy { + dest: StatePartIndex(4374), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:290:9 + 257: Copy { + dest: StatePartIndex(4060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:286:13 + 258: Copy { + dest: StatePartIndex(4066), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:17:11 + 259: AndBigWithSmallImmediate { + dest: StatePartIndex(276), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4066), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 260: Copy { + dest: StatePartIndex(4068), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4066), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 261: SliceInt { + dest: StatePartIndex(4069), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4068), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: reg_alloc.rs:286:13 + 262: AndBigWithSmallImmediate { + dest: StatePartIndex(301), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 263: Copy { + dest: StatePartIndex(4385), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 264: SliceInt { + dest: StatePartIndex(4386), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4385), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, start: 1, len: 4, }, // at: unit_free_regs_tracker.rs:27:25 - 128: IsNonZeroDestIsSmall { - dest: StatePartIndex(28), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(334), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, + 265: IsNonZeroDestIsSmall { + dest: StatePartIndex(230), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3236), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, }, - 129: IsNonZeroDestIsSmall { - dest: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, + 266: IsNonZeroDestIsSmall { + dest: StatePartIndex(229), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3235), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, }, - 130: AndSmall { - dest: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + 267: AndSmall { + dest: StatePartIndex(228), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(229), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(227), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, // at: unit_free_regs_tracker.rs:7:1 - 131: Copy { - dest: StatePartIndex(337), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 268: Copy { + dest: StatePartIndex(3239), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3237), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, }, - 132: SliceInt { - dest: StatePartIndex(338), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(337), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + 269: SliceInt { + dest: StatePartIndex(3240), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3239), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, start: 1, len: 4, }, // at: unit_free_regs_tracker.rs:17:11 - 133: AndBigWithSmallImmediate { - dest: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 270: AndBigWithSmallImmediate { + dest: StatePartIndex(225), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3237), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, rhs: 0x1, }, - // at: reg_alloc.rs:138:9 - 134: Copy { - dest: StatePartIndex(323), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, + // at: reg_alloc.rs:273:9 + 271: Copy { + dest: StatePartIndex(3085), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - 135: Copy { - dest: StatePartIndex(324), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, + 272: Copy { + dest: StatePartIndex(3086), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, }, - // at: reg_alloc.rs:136:13 - 136: Copy { - dest: StatePartIndex(325), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.clk", ty: Clock }, - src: StatePartIndex(323), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, - }, - 137: Copy { - dest: StatePartIndex(326), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.rst", ty: SyncReset }, - src: StatePartIndex(324), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, - }, - // at: reg_alloc.rs:41:1 - 138: Const { - dest: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - value: 0x1, - }, - 139: Const { - dest: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - value: 0x0, - }, - 140: CastToUInt { - dest: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - dest_width: 1, - }, - // at: reg_alloc.rs:93:21 - 141: Copy { - dest: StatePartIndex(299), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", ty: UInt<1> }, - src: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: reg_alloc.rs:41:1 - 142: Copy { - dest: StatePartIndex(302), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 143: Copy { - dest: StatePartIndex(303), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, - src: StatePartIndex(299), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", ty: UInt<1> }, - }, - 144: Shl { - dest: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(303), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, - rhs: 1, - }, - 145: Or { - dest: StatePartIndex(306), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(302), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - rhs: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - 146: CastToUInt { - dest: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(306), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - dest_width: 2, - }, - 147: Copy { - dest: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: reg_alloc.rs:93:21 - 148: Copy { - dest: StatePartIndex(316), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", ty: UInt<1> }, - src: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: reg_alloc.rs:41:1 - 149: Copy { - dest: StatePartIndex(317), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 150: Copy { - dest: StatePartIndex(318), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, - src: StatePartIndex(316), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", ty: UInt<1> }, - }, - 151: Shl { - dest: StatePartIndex(319), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(318), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, - rhs: 1, - }, - 152: Or { - dest: StatePartIndex(320), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(317), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - rhs: StatePartIndex(319), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - 153: CastToUInt { - dest: StatePartIndex(321), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(320), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - dest_width: 2, - }, - 154: Copy { - dest: StatePartIndex(322), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(321), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 155: CmpLt { - dest: StatePartIndex(410), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(399), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 156: SubU { - dest: StatePartIndex(415), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(399), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 157: CastBigToArrayIndex { - dest: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(415), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 158: ReadIndexed { - dest: StatePartIndex(416), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(31) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 159: Add { - dest: StatePartIndex(418), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(416), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 160: CastToUInt { - dest: StatePartIndex(419), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(418), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 161: CmpLt { - dest: StatePartIndex(434), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(423), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 162: SubU { - dest: StatePartIndex(436), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(423), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 163: CastBigToArrayIndex { - dest: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(436), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 164: ReadIndexed { - dest: StatePartIndex(437), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(32) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 165: Add { - dest: StatePartIndex(438), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(437), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 166: CastToUInt { - dest: StatePartIndex(439), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(438), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 167: CmpLt { - dest: StatePartIndex(448), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, - }, - 168: SubU { - dest: StatePartIndex(451), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, - dest_width: 65, - }, - 169: CastBigToArrayIndex { - dest: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(451), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 170: CmpLt { - dest: StatePartIndex(470), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(459), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 171: SubU { - dest: StatePartIndex(472), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(459), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 172: CastBigToArrayIndex { - dest: StatePartIndex(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(472), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 173: ReadIndexed { - dest: StatePartIndex(473), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(34) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 174: Add { - dest: StatePartIndex(474), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(473), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 175: CastToUInt { - dest: StatePartIndex(475), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(474), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 176: CmpLt { - dest: StatePartIndex(490), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(479), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 177: SubU { - dest: StatePartIndex(492), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(479), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 178: CastBigToArrayIndex { - dest: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(492), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 179: ReadIndexed { - dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(35) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 180: Add { - dest: StatePartIndex(494), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(493), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 181: CastToUInt { - dest: StatePartIndex(495), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(494), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 182: CmpLt { - dest: StatePartIndex(504), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, - }, - 183: SubU { - dest: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, - dest_width: 65, - }, - 184: CastBigToArrayIndex { - dest: StatePartIndex(36), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 185: CmpLt { - dest: StatePartIndex(519), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, - }, - 186: SubU { - dest: StatePartIndex(522), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, - dest_width: 65, - }, - 187: CastBigToArrayIndex { - dest: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(522), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 188: CmpLt { - dest: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(530), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 189: SubU { - dest: StatePartIndex(543), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(530), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 190: CastBigToArrayIndex { - dest: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(543), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 191: ReadIndexed { - dest: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(38) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 192: Add { - dest: StatePartIndex(545), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 193: CastToUInt { - dest: StatePartIndex(546), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(545), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 194: CmpLt { - dest: StatePartIndex(561), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 195: SubU { - dest: StatePartIndex(563), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 196: CastBigToArrayIndex { - dest: StatePartIndex(39), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(563), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 197: ReadIndexed { - dest: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(39) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 198: Add { - dest: StatePartIndex(565), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 199: CastToUInt { - dest: StatePartIndex(566), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(565), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 200: CmpLt { - dest: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, - }, - 201: SubU { - dest: StatePartIndex(578), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, - dest_width: 65, - }, - 202: CastBigToArrayIndex { - dest: StatePartIndex(40), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(578), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 203: CmpLt { - dest: StatePartIndex(596), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 204: SubU { - dest: StatePartIndex(598), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 205: CastBigToArrayIndex { - dest: StatePartIndex(41), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(598), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 206: ReadIndexed { - dest: StatePartIndex(599), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(41) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 207: Add { - dest: StatePartIndex(600), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(599), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 208: CastToUInt { - dest: StatePartIndex(601), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(600), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 209: CmpLt { - dest: StatePartIndex(616), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 210: SubU { - dest: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 65, - }, - 211: CastBigToArrayIndex { - dest: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 212: ReadIndexed { - dest: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(42) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 213: Add { - dest: StatePartIndex(620), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, - }, - 214: CastToUInt { - dest: StatePartIndex(621), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(620), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 1, - }, - 215: CmpLt { - dest: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, - }, - 216: SubU { - dest: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, - dest_width: 65, - }, - 217: CastBigToArrayIndex { - dest: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 218: CmpLt { - dest: StatePartIndex(645), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, - }, - 219: SubU { - dest: StatePartIndex(648), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, - dest_width: 65, - }, - 220: CastBigToArrayIndex { - dest: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(648), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 221: CmpLt { - dest: StatePartIndex(660), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, - }, - 222: SubU { - dest: StatePartIndex(663), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, - dest_width: 65, - }, - 223: CastBigToArrayIndex { - dest: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(663), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, - }, - 224: CmpLt { - dest: StatePartIndex(671), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - rhs: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, - }, - // at: reg_alloc.rs:41:1 - 225: Const { - dest: StatePartIndex(290), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x2, - }, - 226: Copy { - dest: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(290), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, - }, - 227: Const { - dest: StatePartIndex(288), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x1, - }, - 228: Copy { - dest: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(288), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - 229: Const { - dest: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - value: 0x0, - }, - 230: Copy { - dest: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:65:9 - 231: Copy { - dest: StatePartIndex(271), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, - src: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, - }, - 232: Copy { - dest: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, - src: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 233: Copy { - dest: StatePartIndex(375), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 234: Copy { - dest: StatePartIndex(376), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 235: Copy { - dest: StatePartIndex(377), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 236: Copy { - dest: StatePartIndex(378), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 237: Copy { - dest: StatePartIndex(379), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 238: Copy { - dest: StatePartIndex(380), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 239: Copy { - dest: StatePartIndex(381), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 240: Copy { - dest: StatePartIndex(382), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 241: Copy { - dest: StatePartIndex(383), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 242: Copy { - dest: StatePartIndex(384), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 243: Copy { - dest: StatePartIndex(385), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 244: Copy { - dest: StatePartIndex(386), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 245: Copy { - dest: StatePartIndex(387), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 246: Copy { - dest: StatePartIndex(388), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 247: Copy { - dest: StatePartIndex(389), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 248: Copy { - dest: StatePartIndex(390), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 249: Or { - dest: StatePartIndex(407), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(406), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 250: Or { - dest: StatePartIndex(408), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(407), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:69:13 - 251: Copy { - dest: StatePartIndex(405), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, - src: StatePartIndex(408), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 252: Or { - dest: StatePartIndex(445), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(444), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(405), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, - }, - 253: Or { - dest: StatePartIndex(449), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(405), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, - rhs: StatePartIndex(448), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 254: Or { - dest: StatePartIndex(411), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(410), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 255: BranchIfZero { - target: 257, - value: StatePartIndex(411), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:81:21 - 256: Copy { - dest: StatePartIndex(409), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 257: BranchIfNonZero { - target: 259, - value: StatePartIndex(411), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 - 258: Copy { - dest: StatePartIndex(409), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, - src: StatePartIndex(419), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 259: CastToUInt { - dest: StatePartIndex(450), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(409), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, - dest_width: 2, - }, - // at: unit_free_regs_tracker.rs:80:17 - 260: BranchIfZero { - target: 262, - value: StatePartIndex(449), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:81:21 - 261: Copy { - dest: StatePartIndex(447), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, - src: StatePartIndex(450), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 262: Or { - dest: StatePartIndex(431), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(430), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 263: Or { - dest: StatePartIndex(432), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(431), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:69:13 - 264: Copy { - dest: StatePartIndex(429), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, - src: StatePartIndex(432), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 265: Or { - dest: StatePartIndex(446), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(445), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(429), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:69:13 - 266: Copy { - dest: StatePartIndex(443), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, - src: StatePartIndex(446), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 267: Or { - dest: StatePartIndex(516), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(515), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(443), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, - }, - 268: Or { - dest: StatePartIndex(520), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(443), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, - rhs: StatePartIndex(519), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 269: Or { - dest: StatePartIndex(435), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(434), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 270: BranchIfZero { - target: 272, - value: StatePartIndex(435), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:81:21 - 271: Copy { - dest: StatePartIndex(433), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 272: BranchIfNonZero { - target: 274, - value: StatePartIndex(435), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 + // at: reg_alloc.rs:271:13 273: Copy { - dest: StatePartIndex(433), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, - src: StatePartIndex(439), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(3089), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.clk", ty: Clock }, + src: StatePartIndex(3085), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:7:1 - 274: ReadIndexed { - dest: StatePartIndex(452), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(433) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> } */ [StatePartIndex(33) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + 274: Copy { + dest: StatePartIndex(3090), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.rst", ty: SyncReset }, + src: StatePartIndex(3086), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, }, - 275: Add { - dest: StatePartIndex(454), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(452), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + // at: reg_alloc.rs:103:17 + 275: Copy { + dest: StatePartIndex(488), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - 276: CastToUInt { - dest: StatePartIndex(455), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(454), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 2, + 276: Copy { + dest: StatePartIndex(483), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:80:17 - 277: BranchIfNonZero { - target: 279, - value: StatePartIndex(449), // (0x0) SlotDebugData { name: "", ty: Bool }, + 277: Copy { + dest: StatePartIndex(478), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:83:21 278: Copy { - dest: StatePartIndex(447), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, - src: StatePartIndex(455), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(458), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:7:1 - 279: CastToUInt { - dest: StatePartIndex(521), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(447), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, - dest_width: 3, + 279: Copy { + dest: StatePartIndex(453), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:80:17 - 280: BranchIfZero { - target: 282, - value: StatePartIndex(520), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:43:1 + 280: Const { + dest: StatePartIndex(1925), // (0xff) SlotDebugData { name: "", ty: UInt<32> }, + value: 0xff, }, - // at: unit_free_regs_tracker.rs:81:21 - 281: Copy { - dest: StatePartIndex(518), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, - src: StatePartIndex(521), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + 281: CastToUInt { + dest: StatePartIndex(1926), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1925), // (0xff) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 8, }, - // at: unit_free_regs_tracker.rs:7:1 - 282: Or { - dest: StatePartIndex(467), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(466), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 282: Copy { + dest: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(1926), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, }, - 283: Or { - dest: StatePartIndex(468), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(467), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:103:17 + 283: Copy { + dest: StatePartIndex(448), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:69:13 - 284: Copy { - dest: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, - src: StatePartIndex(468), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:43:1 + 284: Const { + dest: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, }, - // at: unit_free_regs_tracker.rs:7:1 - 285: Or { - dest: StatePartIndex(501), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + 285: CastToUInt { + dest: StatePartIndex(1868), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, }, - 286: Or { - dest: StatePartIndex(505), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, - rhs: StatePartIndex(504), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:221:21 + 286: Copy { + dest: StatePartIndex(1866), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_1", ty: UInt<2> }, + src: StatePartIndex(1868), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, - 287: Or { - dest: StatePartIndex(471), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(470), // (0x0) SlotDebugData { name: "", ty: Bool }, + 287: Copy { + dest: StatePartIndex(3073), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_1", ty: UInt<2> }, + src: StatePartIndex(1868), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 288: BranchIfZero { - target: 290, - value: StatePartIndex(471), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:43:1 + 288: Copy { + dest: StatePartIndex(3753), // (0x1) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(1868), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, - // at: unit_free_regs_tracker.rs:81:21 - 289: Copy { - dest: StatePartIndex(469), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 289: Const { + dest: StatePartIndex(1854), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + value: 0x0, }, - // at: unit_free_regs_tracker.rs:80:17 - 290: BranchIfNonZero { - target: 292, - value: StatePartIndex(471), // (0x0) SlotDebugData { name: "", ty: Bool }, + 290: Copy { + dest: StatePartIndex(1855), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1854), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, }, - // at: unit_free_regs_tracker.rs:83:21 + // at: reg_alloc.rs:212:21 291: Copy { - dest: StatePartIndex(469), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, - src: StatePartIndex(475), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(1851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1855), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, }, - // at: unit_free_regs_tracker.rs:7:1 - 292: CastToUInt { - dest: StatePartIndex(506), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(469), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, - dest_width: 2, + 292: Copy { + dest: StatePartIndex(1863), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1855), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, }, - // at: unit_free_regs_tracker.rs:80:17 - 293: BranchIfZero { - target: 295, - value: StatePartIndex(505), // (0x0) SlotDebugData { name: "", ty: Bool }, + 293: Copy { + dest: StatePartIndex(3060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1855), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, }, - // at: unit_free_regs_tracker.rs:81:21 294: Copy { - dest: StatePartIndex(503), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, - src: StatePartIndex(506), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(3070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1855), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:43:1 + 295: Const { + dest: StatePartIndex(1542), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + 296: Const { + dest: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 297: Shl { + dest: StatePartIndex(1243), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 25, + }, + 298: Shl { + dest: StatePartIndex(1264), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 299: Shl { + dest: StatePartIndex(1377), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 300: Shl { + dest: StatePartIndex(1484), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 301: CastToUInt { + dest: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 6, + }, + 302: Shl { + dest: StatePartIndex(1598), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 303: Shl { + dest: StatePartIndex(1672), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 304: Shl { + dest: StatePartIndex(1764), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 305: Shl { + dest: StatePartIndex(1831), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 306: Shl { + dest: StatePartIndex(2454), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 25, + }, + 307: Shl { + dest: StatePartIndex(2475), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 308: Shl { + dest: StatePartIndex(2588), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 309: Shl { + dest: StatePartIndex(2695), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 48, + }, + 310: Shl { + dest: StatePartIndex(2807), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 311: Shl { + dest: StatePartIndex(2881), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 312: Shl { + dest: StatePartIndex(2973), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, + }, + 313: Shl { + dest: StatePartIndex(3040), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: 49, }, // at: unit_free_regs_tracker.rs:7:1 - 295: Or { - dest: StatePartIndex(487), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(486), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 314: Copy { + dest: StatePartIndex(3314), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, + src: StatePartIndex(1242), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, }, - 296: Or { - dest: StatePartIndex(488), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(487), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 315: CastToUInt { + dest: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3314), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:69:13 - 297: Copy { - dest: StatePartIndex(485), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, - src: StatePartIndex(488), // (0x0) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:43:1 + 316: Const { + dest: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, }, - // at: unit_free_regs_tracker.rs:7:1 - 298: Or { - dest: StatePartIndex(502), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(501), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(485), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:69:13 - 299: Copy { - dest: StatePartIndex(499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, - src: StatePartIndex(502), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 300: Or { - dest: StatePartIndex(517), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(516), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:69:13 - 301: Copy { - dest: StatePartIndex(514), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, - src: StatePartIndex(517), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 302: Or { - dest: StatePartIndex(657), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(656), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(514), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, - }, - 303: Or { - dest: StatePartIndex(661), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(514), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, - rhs: StatePartIndex(660), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 304: Or { - dest: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(490), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 305: BranchIfZero { - target: 307, - value: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:81:21 - 306: Copy { - dest: StatePartIndex(489), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:80:17 - 307: BranchIfNonZero { - target: 309, - value: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 - 308: Copy { - dest: StatePartIndex(489), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, - src: StatePartIndex(495), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 309: ReadIndexed { - dest: StatePartIndex(508), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(489) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> } */ [StatePartIndex(36) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 310: Add { - dest: StatePartIndex(509), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(508), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, - }, - 311: CastToUInt { - dest: StatePartIndex(510), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(509), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + 317: CastToUInt { + dest: StatePartIndex(1179), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, dest_width: 2, }, - // at: unit_free_regs_tracker.rs:80:17 - 312: BranchIfNonZero { - target: 314, - value: StatePartIndex(505), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 - 313: Copy { - dest: StatePartIndex(503), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, - src: StatePartIndex(510), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: unit_free_regs_tracker.rs:7:1 - 314: ReadIndexed { - dest: StatePartIndex(523), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(503) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> } */ [StatePartIndex(37) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, - }, - 315: Add { - dest: StatePartIndex(525), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(523), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, - }, - 316: CastToUInt { - dest: StatePartIndex(526), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(525), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 3, - }, - // at: unit_free_regs_tracker.rs:80:17 - 317: BranchIfNonZero { - target: 319, - value: StatePartIndex(520), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 318: Copy { - dest: StatePartIndex(518), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, - src: StatePartIndex(526), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest: StatePartIndex(1177), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(1179), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:221:21 + 319: Copy { + dest: StatePartIndex(1856), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_0", ty: UInt<2> }, + src: StatePartIndex(1179), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 320: Copy { + dest: StatePartIndex(3063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_0", ty: UInt<2> }, + src: StatePartIndex(1179), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, // at: unit_free_regs_tracker.rs:7:1 - 319: CastToUInt { - dest: StatePartIndex(662), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(518), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, - dest_width: 4, + 321: CmpLt { + dest: StatePartIndex(3312), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 320: BranchIfZero { - target: 322, - value: StatePartIndex(661), // (0x0) SlotDebugData { name: "", ty: Bool }, + 322: SubU { + dest: StatePartIndex(3316), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:81:21 - 321: Copy { - dest: StatePartIndex(659), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, - src: StatePartIndex(662), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, + 323: CastBigToArrayIndex { + dest: StatePartIndex(233), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3316), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 322: Or { - dest: StatePartIndex(538), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(537), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 324: ReadIndexed { + dest: StatePartIndex(3317), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(233) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - 323: Or { - dest: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(538), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 325: Add { + dest: StatePartIndex(3318), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3317), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 324: Copy { - dest: StatePartIndex(536), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, - src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: Bool }, + 326: CastToUInt { + dest: StatePartIndex(3319), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3318), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:7:1 - 325: Or { - dest: StatePartIndex(572), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(571), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(536), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + 327: CmpLt { + dest: StatePartIndex(3334), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 326: Or { - dest: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(536), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, - rhs: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: Bool }, + 328: SubU { + dest: StatePartIndex(3336), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - 327: Or { - dest: StatePartIndex(542), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: Bool }, + 329: CastBigToArrayIndex { + dest: StatePartIndex(234), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3336), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 328: BranchIfZero { - target: 330, - value: StatePartIndex(542), // (0x0) SlotDebugData { name: "", ty: Bool }, + 330: ReadIndexed { + dest: StatePartIndex(3337), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(234) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:81:21 - 329: Copy { - dest: StatePartIndex(540), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 331: Add { + dest: StatePartIndex(3338), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3337), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 330: BranchIfNonZero { - target: 332, - value: StatePartIndex(542), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: unit_free_regs_tracker.rs:83:21 - 331: Copy { - dest: StatePartIndex(540), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, - src: StatePartIndex(546), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: unit_free_regs_tracker.rs:7:1 332: CastToUInt { - dest: StatePartIndex(577), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(540), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, - dest_width: 2, + dest: StatePartIndex(3339), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3338), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:80:17 - 333: BranchIfZero { - target: 335, - value: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: Bool }, + 333: CmpLt { + dest: StatePartIndex(3348), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:81:21 - 334: Copy { - dest: StatePartIndex(574), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, - src: StatePartIndex(577), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + 334: SubU { + dest: StatePartIndex(3351), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 335: Or { - dest: StatePartIndex(558), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(557), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 335: CastBigToArrayIndex { + dest: StatePartIndex(235), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3351), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 336: Or { - dest: StatePartIndex(559), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(558), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 336: CmpLt { + dest: StatePartIndex(3370), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 337: Copy { - dest: StatePartIndex(556), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, - src: StatePartIndex(559), // (0x0) SlotDebugData { name: "", ty: Bool }, + 337: SubU { + dest: StatePartIndex(3372), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 338: Or { - dest: StatePartIndex(573), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(572), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(556), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + 338: CastBigToArrayIndex { + dest: StatePartIndex(236), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3372), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 339: Copy { - dest: StatePartIndex(570), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, - src: StatePartIndex(573), // (0x0) SlotDebugData { name: "", ty: Bool }, + 339: ReadIndexed { + dest: StatePartIndex(3373), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(236) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:7:1 - 340: Or { - dest: StatePartIndex(642), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(641), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(570), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + 340: Add { + dest: StatePartIndex(3374), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3373), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - 341: Or { - dest: StatePartIndex(646), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(570), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, - rhs: StatePartIndex(645), // (0x0) SlotDebugData { name: "", ty: Bool }, + 341: CastToUInt { + dest: StatePartIndex(3375), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3374), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - 342: Or { - dest: StatePartIndex(562), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(561), // (0x0) SlotDebugData { name: "", ty: Bool }, + 342: CmpLt { + dest: StatePartIndex(3390), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 343: BranchIfZero { - target: 345, - value: StatePartIndex(562), // (0x0) SlotDebugData { name: "", ty: Bool }, + 343: SubU { + dest: StatePartIndex(3392), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:81:21 - 344: Copy { - dest: StatePartIndex(560), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 344: CastBigToArrayIndex { + dest: StatePartIndex(237), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3392), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 345: BranchIfNonZero { - target: 347, - value: StatePartIndex(562), // (0x0) SlotDebugData { name: "", ty: Bool }, + 345: ReadIndexed { + dest: StatePartIndex(3393), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(237) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:83:21 - 346: Copy { - dest: StatePartIndex(560), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, - src: StatePartIndex(566), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + 346: Add { + dest: StatePartIndex(3394), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3393), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 347: ReadIndexed { - dest: StatePartIndex(579), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(560) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> } */ [StatePartIndex(40) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + 347: CastToUInt { + dest: StatePartIndex(3395), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3394), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - 348: Add { - dest: StatePartIndex(580), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(579), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + 348: CmpLt { + dest: StatePartIndex(3404), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, }, - 349: CastToUInt { - dest: StatePartIndex(581), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(580), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 2, + 349: SubU { + dest: StatePartIndex(3407), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:80:17 - 350: BranchIfNonZero { - target: 352, - value: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: Bool }, + 350: CastBigToArrayIndex { + dest: StatePartIndex(238), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3407), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:83:21 - 351: Copy { - dest: StatePartIndex(574), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, - src: StatePartIndex(581), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + 351: CmpLt { + dest: StatePartIndex(3419), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 352: CastToUInt { - dest: StatePartIndex(647), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(574), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, - dest_width: 3, + 352: SubU { + dest: StatePartIndex(3422), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:80:17 - 353: BranchIfZero { - target: 355, - value: StatePartIndex(646), // (0x0) SlotDebugData { name: "", ty: Bool }, + 353: CastBigToArrayIndex { + dest: StatePartIndex(239), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3422), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:81:21 - 354: Copy { - dest: StatePartIndex(644), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, - src: StatePartIndex(647), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + 354: CmpLt { + dest: StatePartIndex(3441), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3430), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 355: Or { - dest: StatePartIndex(593), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(592), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 355: SubU { + dest: StatePartIndex(3443), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3430), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - 356: Or { - dest: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(593), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 356: CastBigToArrayIndex { + dest: StatePartIndex(240), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3443), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 357: Copy { - dest: StatePartIndex(591), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, - src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: Bool }, + 357: ReadIndexed { + dest: StatePartIndex(3444), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(240) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:7:1 - 358: Or { - dest: StatePartIndex(627), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(591), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + 358: Add { + dest: StatePartIndex(3445), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3444), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - 359: Or { - dest: StatePartIndex(631), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(591), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, - rhs: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: Bool }, + 359: CastToUInt { + dest: StatePartIndex(3446), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3445), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - 360: Or { - dest: StatePartIndex(597), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(596), // (0x0) SlotDebugData { name: "", ty: Bool }, + 360: CmpLt { + dest: StatePartIndex(3461), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3450), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 361: BranchIfZero { - target: 363, - value: StatePartIndex(597), // (0x0) SlotDebugData { name: "", ty: Bool }, + 361: SubU { + dest: StatePartIndex(3463), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3450), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:81:21 - 362: Copy { - dest: StatePartIndex(595), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 362: CastBigToArrayIndex { + dest: StatePartIndex(241), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3463), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 363: BranchIfNonZero { - target: 365, - value: StatePartIndex(597), // (0x0) SlotDebugData { name: "", ty: Bool }, + 363: ReadIndexed { + dest: StatePartIndex(3464), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(241) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:83:21 - 364: Copy { - dest: StatePartIndex(595), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, - src: StatePartIndex(601), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + 364: Add { + dest: StatePartIndex(3465), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3464), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:7:1 365: CastToUInt { - dest: StatePartIndex(632), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(595), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, - dest_width: 2, + dest: StatePartIndex(3466), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3465), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:80:17 - 366: BranchIfZero { - target: 368, - value: StatePartIndex(631), // (0x0) SlotDebugData { name: "", ty: Bool }, + 366: CmpLt { + dest: StatePartIndex(3475), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3427), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:81:21 - 367: Copy { - dest: StatePartIndex(629), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, - src: StatePartIndex(632), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + 367: SubU { + dest: StatePartIndex(3478), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3427), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 368: Or { - dest: StatePartIndex(613), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(612), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 368: CastBigToArrayIndex { + dest: StatePartIndex(242), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3478), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 369: Or { - dest: StatePartIndex(614), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(613), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 369: CmpLt { + dest: StatePartIndex(3496), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3485), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 370: Copy { - dest: StatePartIndex(611), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, - src: StatePartIndex(614), // (0x0) SlotDebugData { name: "", ty: Bool }, + 370: SubU { + dest: StatePartIndex(3498), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3485), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 371: Or { - dest: StatePartIndex(628), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(627), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(611), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + 371: CastBigToArrayIndex { + dest: StatePartIndex(243), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3498), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 372: Copy { - dest: StatePartIndex(625), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, - src: StatePartIndex(628), // (0x0) SlotDebugData { name: "", ty: Bool }, + 372: ReadIndexed { + dest: StatePartIndex(3499), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(243) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:7:1 - 373: Or { - dest: StatePartIndex(643), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(642), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(625), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + 373: Add { + dest: StatePartIndex(3500), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3499), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 374: Copy { - dest: StatePartIndex(640), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, - src: StatePartIndex(643), // (0x0) SlotDebugData { name: "", ty: Bool }, + 374: CastToUInt { + dest: StatePartIndex(3501), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3500), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:7:1 - 375: Or { - dest: StatePartIndex(658), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(657), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(640), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + 375: CmpLt { + dest: StatePartIndex(3516), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3505), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:69:13 - 376: Copy { - dest: StatePartIndex(655), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, - src: StatePartIndex(658), // (0x0) SlotDebugData { name: "", ty: Bool }, + 376: SubU { + dest: StatePartIndex(3518), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3505), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 377: Or { - dest: StatePartIndex(672), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(655), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, - rhs: StatePartIndex(671), // (0x0) SlotDebugData { name: "", ty: Bool }, + 377: CastBigToArrayIndex { + dest: StatePartIndex(244), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3518), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 378: Or { - dest: StatePartIndex(617), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(616), // (0x0) SlotDebugData { name: "", ty: Bool }, + 378: ReadIndexed { + dest: StatePartIndex(3519), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(244) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: unit_free_regs_tracker.rs:80:17 - 379: BranchIfZero { - target: 381, - value: StatePartIndex(617), // (0x0) SlotDebugData { name: "", ty: Bool }, + 379: Add { + dest: StatePartIndex(3520), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3519), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:81:21 - 380: Copy { - dest: StatePartIndex(615), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, - src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + 380: CastToUInt { + dest: StatePartIndex(3521), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3520), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:80:17 - 381: BranchIfNonZero { - target: 383, - value: StatePartIndex(617), // (0x0) SlotDebugData { name: "", ty: Bool }, + 381: CmpLt { + dest: StatePartIndex(3530), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:83:21 - 382: Copy { - dest: StatePartIndex(615), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, - src: StatePartIndex(621), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + 382: SubU { + dest: StatePartIndex(3533), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 383: ReadIndexed { - dest: StatePartIndex(634), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(615) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> } */ [StatePartIndex(43) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + 383: CastBigToArrayIndex { + dest: StatePartIndex(245), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3533), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 384: Add { - dest: StatePartIndex(635), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(634), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + 384: CmpLt { + dest: StatePartIndex(3545), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, }, - 385: CastToUInt { - dest: StatePartIndex(636), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(635), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 2, + 385: SubU { + dest: StatePartIndex(3548), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:80:17 - 386: BranchIfNonZero { - target: 388, - value: StatePartIndex(631), // (0x0) SlotDebugData { name: "", ty: Bool }, + 386: CastBigToArrayIndex { + dest: StatePartIndex(246), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3548), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:83:21 - 387: Copy { - dest: StatePartIndex(629), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, - src: StatePartIndex(636), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + 387: CmpLt { + dest: StatePartIndex(3560), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3411), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 388: ReadIndexed { - dest: StatePartIndex(649), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(629) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> } */ [StatePartIndex(44) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + 388: SubU { + dest: StatePartIndex(3563), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3411), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + dest_width: 65, }, - 389: Add { - dest: StatePartIndex(650), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(649), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + 389: CastBigToArrayIndex { + dest: StatePartIndex(247), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(3563), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 390: CastToUInt { - dest: StatePartIndex(651), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(650), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 3, + 390: CmpLt { + dest: StatePartIndex(3571), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(3552), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 391: BranchIfNonZero { - target: 393, - value: StatePartIndex(646), // (0x0) SlotDebugData { name: "", ty: Bool }, + 391: CmpLt { + dest: StatePartIndex(4123), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4112), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:83:21 - 392: Copy { - dest: StatePartIndex(644), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, - src: StatePartIndex(651), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + 392: SubU { + dest: StatePartIndex(4125), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4112), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:7:1 - 393: ReadIndexed { - dest: StatePartIndex(664), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(644) /* (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> } */ [StatePartIndex(45) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + 393: CastBigToArrayIndex { + dest: StatePartIndex(284), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4125), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 394: Add { - dest: StatePartIndex(666), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, - lhs: StatePartIndex(664), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, - rhs: StatePartIndex(665), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + 394: ReadIndexed { + dest: StatePartIndex(4126), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(284) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - 395: CastToUInt { - dest: StatePartIndex(667), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(666), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, - dest_width: 4, + 395: Add { + dest: StatePartIndex(4127), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4126), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: unit_free_regs_tracker.rs:80:17 - 396: BranchIfNonZero { - target: 398, - value: StatePartIndex(661), // (0x0) SlotDebugData { name: "", ty: Bool }, + 396: CastToUInt { + dest: StatePartIndex(4128), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4127), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - // at: unit_free_regs_tracker.rs:83:21 - 397: Copy { - dest: StatePartIndex(659), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, - src: StatePartIndex(667), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + 397: CmpLt { + dest: StatePartIndex(4143), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4132), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 398: Copy { - dest: StatePartIndex(673), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + 398: SubU { + dest: StatePartIndex(4145), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4132), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - 399: Copy { - dest: StatePartIndex(674), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, - src: StatePartIndex(659), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + 399: CastBigToArrayIndex { + dest: StatePartIndex(285), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4145), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - 400: Shl { - dest: StatePartIndex(675), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(674), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, - rhs: 1, + 400: ReadIndexed { + dest: StatePartIndex(4146), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(285) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - 401: Or { - dest: StatePartIndex(676), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(673), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, - rhs: StatePartIndex(675), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, + 401: Add { + dest: StatePartIndex(4147), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4146), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, 402: CastToUInt { - dest: StatePartIndex(677), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(676), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, - dest_width: 5, + dest: StatePartIndex(4148), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4147), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - 403: Copy { - dest: StatePartIndex(678), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(677), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + 403: CmpLt { + dest: StatePartIndex(4157), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4109), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:106:9 - 404: BranchIfZero { - target: 406, - value: StatePartIndex(672), // (0x0) SlotDebugData { name: "", ty: Bool }, + 404: SubU { + dest: StatePartIndex(4160), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4109), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:107:13 - 405: Copy { - dest: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(678), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 405: CastBigToArrayIndex { + dest: StatePartIndex(286), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4160), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:106:9 - 406: BranchIfNonZero { - target: 408, - value: StatePartIndex(672), // (0x0) SlotDebugData { name: "", ty: Bool }, + 406: CmpLt { + dest: StatePartIndex(4178), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4167), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: unit_free_regs_tracker.rs:112:13 - 407: Copy { - dest: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 407: SubU { + dest: StatePartIndex(4180), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4167), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - // at: unit_free_regs_tracker.rs:20:11 - 408: AndBigWithSmallImmediate { - dest: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - rhs: 0x1, + 408: CastBigToArrayIndex { + dest: StatePartIndex(287), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4180), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: unit_free_regs_tracker.rs:7:1 - 409: Copy { - dest: StatePartIndex(341), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 409: ReadIndexed { + dest: StatePartIndex(4181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(287) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - 410: SliceInt { - dest: StatePartIndex(342), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(341), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - start: 1, - len: 4, + 410: Add { + dest: StatePartIndex(4182), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, }, - // at: reg_alloc.rs:150:13 - 411: Copy { - dest: StatePartIndex(331), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 411: CastToUInt { + dest: StatePartIndex(4183), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4182), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, }, - 412: AndBigWithSmallImmediate { - dest: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(331), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - rhs: 0x1, + 412: CmpLt { + dest: StatePartIndex(4198), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4187), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - // at: reg_alloc.rs:41:1 - 413: Copy { - dest: StatePartIndex(681), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(331), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 413: SubU { + dest: StatePartIndex(4200), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4187), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, }, - 414: SliceInt { - dest: StatePartIndex(682), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(681), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - start: 1, - len: 4, + 414: CastBigToArrayIndex { + dest: StatePartIndex(288), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4200), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, }, - // at: reg_alloc.rs:158:9 - 415: Copy { - dest: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + 415: ReadIndexed { + dest: StatePartIndex(4201), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(288) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, }, - // at: reg_alloc.rs:41:1 - 416: Const { - dest: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + 416: Add { + dest: StatePartIndex(4202), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4201), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 417: CastToUInt { + dest: StatePartIndex(4203), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4202), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 418: CmpLt { + dest: StatePartIndex(4212), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4164), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + }, + 419: SubU { + dest: StatePartIndex(4215), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4164), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + dest_width: 65, + }, + 420: CastBigToArrayIndex { + dest: StatePartIndex(289), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4215), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 421: CmpLt { + dest: StatePartIndex(4227), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4149), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + }, + 422: SubU { + dest: StatePartIndex(4230), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4149), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + dest_width: 65, + }, + 423: CastBigToArrayIndex { + dest: StatePartIndex(290), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4230), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 424: CmpLt { + dest: StatePartIndex(4248), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4237), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 425: SubU { + dest: StatePartIndex(4250), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4237), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 426: CastBigToArrayIndex { + dest: StatePartIndex(291), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4250), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 427: ReadIndexed { + dest: StatePartIndex(4251), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(291) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 428: Add { + dest: StatePartIndex(4252), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4251), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 429: CastToUInt { + dest: StatePartIndex(4253), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4252), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 430: CmpLt { + dest: StatePartIndex(4268), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4257), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 431: SubU { + dest: StatePartIndex(4270), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4257), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 432: CastBigToArrayIndex { + dest: StatePartIndex(292), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4270), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 433: ReadIndexed { + dest: StatePartIndex(4271), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(292) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 434: Add { + dest: StatePartIndex(4272), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4271), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 435: CastToUInt { + dest: StatePartIndex(4273), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4272), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 436: CmpLt { + dest: StatePartIndex(4282), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + }, + 437: SubU { + dest: StatePartIndex(4285), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + dest_width: 65, + }, + 438: CastBigToArrayIndex { + dest: StatePartIndex(293), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4285), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 439: CmpLt { + dest: StatePartIndex(4303), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4292), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 440: SubU { + dest: StatePartIndex(4305), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4292), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 441: CastBigToArrayIndex { + dest: StatePartIndex(294), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4305), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 442: ReadIndexed { + dest: StatePartIndex(4306), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(294) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 443: Add { + dest: StatePartIndex(4307), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4306), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 444: CastToUInt { + dest: StatePartIndex(4308), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4307), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 445: CmpLt { + dest: StatePartIndex(4323), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4312), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 446: SubU { + dest: StatePartIndex(4325), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4312), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 447: CastBigToArrayIndex { + dest: StatePartIndex(295), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4325), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 448: ReadIndexed { + dest: StatePartIndex(4326), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3314) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(295) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 449: Add { + dest: StatePartIndex(4327), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4326), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 450: CastToUInt { + dest: StatePartIndex(4328), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4327), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 451: CmpLt { + dest: StatePartIndex(4337), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + }, + 452: SubU { + dest: StatePartIndex(4340), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + dest_width: 65, + }, + 453: CastBigToArrayIndex { + dest: StatePartIndex(296), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4340), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 454: CmpLt { + dest: StatePartIndex(4352), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + }, + 455: SubU { + dest: StatePartIndex(4355), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + dest_width: 65, + }, + 456: CastBigToArrayIndex { + dest: StatePartIndex(297), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4355), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 457: CmpLt { + dest: StatePartIndex(4367), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4219), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + }, + 458: SubU { + dest: StatePartIndex(4370), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4219), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + dest_width: 65, + }, + 459: CastBigToArrayIndex { + dest: StatePartIndex(298), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(4370), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 460: CmpLt { + dest: StatePartIndex(4377), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(4359), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + }, + // at: reg_alloc.rs:43:1 + 461: Const { + dest: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x2, + }, + 462: Copy { + dest: StatePartIndex(961), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 463: Const { + dest: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, value: 0x1, }, - // at: reg_alloc.rs:61:9 - 417: Copy { - dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].ready", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + 464: Copy { + dest: StatePartIndex(959), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, - 418: Copy { - dest: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].ready", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:103:17 + 465: Copy { + dest: StatePartIndex(473), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: unit_free_regs_tracker.rs:29:9 - 419: Copy { - dest: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + 466: Copy { + dest: StatePartIndex(468), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: ready_valid.rs:33:9 - 420: BranchIfZero { - target: 422, - value: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + // at: reg_alloc.rs:43:1 + 467: Const { + dest: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + value: 0x100, }, - // at: ready_valid.rs:34:13 - 421: Copy { - dest: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + // at: reg_alloc.rs:103:17 + 468: Copy { + dest: StatePartIndex(463), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, }, - // at: ready_valid.rs:30:27 - 422: AndBigWithSmallImmediate { - dest: StatePartIndex(29), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 469: Copy { + dest: StatePartIndex(443), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + 470: Copy { + dest: StatePartIndex(438), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + // at: reg_alloc.rs:43:1 + 471: Const { + dest: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 472: Copy { + dest: StatePartIndex(1857), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 473: Copy { + dest: StatePartIndex(1858), // (0x0) SlotDebugData { name: ".1", ty: UInt<2> }, + src: StatePartIndex(1856), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_0", ty: UInt<2> }, + }, + 474: Shl { + dest: StatePartIndex(1859), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(1858), // (0x0) SlotDebugData { name: ".1", ty: UInt<2> }, + rhs: 1, + }, + 475: Or { + dest: StatePartIndex(1860), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(1857), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1859), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 476: CastToUInt { + dest: StatePartIndex(1861), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1860), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 3, + }, + 477: Copy { + dest: StatePartIndex(1862), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1861), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + }, + 478: Copy { + dest: StatePartIndex(1869), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 479: Copy { + dest: StatePartIndex(1870), // (0x1) SlotDebugData { name: ".1", ty: UInt<2> }, + src: StatePartIndex(1866), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_0_1", ty: UInt<2> }, + }, + 480: Shl { + dest: StatePartIndex(1871), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(1870), // (0x1) SlotDebugData { name: ".1", ty: UInt<2> }, + rhs: 1, + }, + 481: Or { + dest: StatePartIndex(1872), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(1869), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1871), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + }, + 482: CastToUInt { + dest: StatePartIndex(1873), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1872), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 3, + }, + 483: Copy { + dest: StatePartIndex(1874), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1873), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + 484: Copy { + dest: StatePartIndex(3064), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 485: Copy { + dest: StatePartIndex(3065), // (0x0) SlotDebugData { name: ".1", ty: UInt<2> }, + src: StatePartIndex(3063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_0", ty: UInt<2> }, + }, + 486: Shl { + dest: StatePartIndex(3066), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(3065), // (0x0) SlotDebugData { name: ".1", ty: UInt<2> }, + rhs: 1, + }, + 487: Or { + dest: StatePartIndex(3067), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(3064), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3066), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 488: CastToUInt { + dest: StatePartIndex(3068), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3067), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 3, + }, + 489: Copy { + dest: StatePartIndex(3069), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3068), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + }, + 490: Copy { + dest: StatePartIndex(3074), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 491: Copy { + dest: StatePartIndex(3075), // (0x1) SlotDebugData { name: ".1", ty: UInt<2> }, + src: StatePartIndex(3073), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_index_1_1", ty: UInt<2> }, + }, + 492: Shl { + dest: StatePartIndex(3076), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(3075), // (0x1) SlotDebugData { name: ".1", ty: UInt<2> }, + rhs: 1, + }, + 493: Or { + dest: StatePartIndex(3077), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(3074), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3076), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + }, + 494: CastToUInt { + dest: StatePartIndex(3078), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3077), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 3, + }, + 495: Copy { + dest: StatePartIndex(3079), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3078), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + 496: Copy { + dest: StatePartIndex(3732), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 497: Copy { + dest: StatePartIndex(3733), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3735), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 498: Copy { + dest: StatePartIndex(3736), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3733), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 499: Shl { + dest: StatePartIndex(3737), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3736), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 500: Or { + dest: StatePartIndex(3738), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3732), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3737), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 501: CastToUInt { + dest: StatePartIndex(3739), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3738), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 502: Copy { + dest: StatePartIndex(3740), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3739), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + 503: Const { + dest: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + value: 0xfe, + }, + 504: CastToUInt { + dest: StatePartIndex(1922), // (0xfe) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 8, + }, + 505: Copy { + dest: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(1922), // (0xfe) SlotDebugData { name: "", ty: UInt<8> }, + }, + 506: Const { + dest: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + value: 0x1, + }, + 507: Const { + dest: StatePartIndex(805), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + value: 0x0, + }, + 508: Copy { + dest: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(805), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:112:17 + 509: Copy { + dest: StatePartIndex(791), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 510: Copy { + dest: StatePartIndex(825), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 511: Copy { + dest: StatePartIndex(851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 512: Copy { + dest: StatePartIndex(878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 513: Copy { + dest: StatePartIndex(905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 514: Copy { + dest: StatePartIndex(931), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 515: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 516: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 517: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 518: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 519: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 520: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 521: Copy { + dest: StatePartIndex(3083), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 522: Copy { + dest: StatePartIndex(3084), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(806), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:259:5 + 523: Copy { + dest: StatePartIndex(761), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(3083), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 524: Copy { + dest: StatePartIndex(762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(3084), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 525: Const { + dest: StatePartIndex(803), // (0x0) SlotDebugData { name: "", ty: UInt<32> }, + value: 0x0, + }, + 526: CastToUInt { + dest: StatePartIndex(804), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(803), // (0x0) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 8, + }, + 527: Copy { + dest: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(804), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 528: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 529: Copy { + dest: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 530: Copy { + dest: StatePartIndex(850), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 531: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 532: Copy { + dest: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 533: Copy { + dest: StatePartIndex(930), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 534: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 535: Copy { + dest: StatePartIndex(1920), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 536: Copy { + dest: StatePartIndex(1923), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 537: Copy { + dest: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 538: Copy { + dest: StatePartIndex(1982), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 539: Copy { + dest: StatePartIndex(1983), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 540: Copy { + dest: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 541: Copy { + dest: StatePartIndex(2030), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 542: Copy { + dest: StatePartIndex(2031), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 543: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 544: Copy { + dest: StatePartIndex(2078), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 545: Copy { + dest: StatePartIndex(2079), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 546: Copy { + dest: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 547: Copy { + dest: StatePartIndex(2126), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 548: Copy { + dest: StatePartIndex(2127), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:111:17 + 549: Copy { + dest: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:721:17 + 550: Copy { + dest: StatePartIndex(2174), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 551: Copy { + dest: StatePartIndex(2175), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(802), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 552: Const { + dest: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: reg_alloc.rs:104:17 + 553: Copy { + dest: StatePartIndex(431), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 554: Copy { + dest: StatePartIndex(436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 555: Copy { + dest: StatePartIndex(441), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 556: CastToUInt { + dest: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + dest_width: 1, + }, + // at: reg_alloc.rs:104:17 + 557: Copy { + dest: StatePartIndex(461), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 558: Copy { + dest: StatePartIndex(466), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 559: Copy { + dest: StatePartIndex(471), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 560: Copy { + dest: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 561: Copy { + dest: StatePartIndex(481), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 562: Copy { + dest: StatePartIndex(486), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.addr", ty: UInt<1> }, + src: StatePartIndex(876), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:43:1 + 563: CastToUInt { + dest: StatePartIndex(1181), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + dest_width: 4, + }, + 564: Copy { + dest: StatePartIndex(1180), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1181), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 565: Copy { + dest: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1177), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 566: Copy { + dest: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1180), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:104:17 + 567: Copy { + dest: StatePartIndex(446), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 568: Copy { + dest: StatePartIndex(451), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 569: Copy { + dest: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.addr", ty: UInt<8> }, + src: StatePartIndex(789), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:103:17 + 570: Copy { + dest: StatePartIndex(433), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + // at: reg_alloc.rs:43:1 + 571: Const { + dest: StatePartIndex(787), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + value: 0x0, + }, + 572: Copy { + dest: StatePartIndex(788), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(787), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:87:9 + 573: Copy { + dest: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[0]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(788), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + 574: Copy { + dest: StatePartIndex(504), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[1]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(788), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + // at: reg_alloc.rs:43:1 + 575: Const { + dest: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + 576: Copy { + dest: StatePartIndex(784), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 577: Copy { + dest: StatePartIndex(785), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:83:9 + 578: Copy { + dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(784), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 579: Copy { + dest: StatePartIndex(494), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", ty: Bool }, + src: StatePartIndex(785), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 580: Copy { + dest: StatePartIndex(495), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(784), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 581: Copy { + dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", ty: Bool }, + src: StatePartIndex(785), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + // at: reg_alloc.rs:105:17 + 582: Copy { + dest: StatePartIndex(432), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 583: Copy { + dest: StatePartIndex(437), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 584: Copy { + dest: StatePartIndex(442), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 585: Copy { + dest: StatePartIndex(462), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 586: Copy { + dest: StatePartIndex(467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 587: Copy { + dest: StatePartIndex(472), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 588: Copy { + dest: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 589: Copy { + dest: StatePartIndex(452), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 590: Copy { + dest: StatePartIndex(457), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 591: Copy { + dest: StatePartIndex(477), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 592: Copy { + dest: StatePartIndex(482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 593: Copy { + dest: StatePartIndex(487), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.en", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 594: Copy { + dest: StatePartIndex(3277), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 595: Copy { + dest: StatePartIndex(3278), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 596: Copy { + dest: StatePartIndex(3279), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 597: Copy { + dest: StatePartIndex(3280), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 598: Copy { + dest: StatePartIndex(3281), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 599: Copy { + dest: StatePartIndex(3282), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 600: Copy { + dest: StatePartIndex(3283), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 601: Copy { + dest: StatePartIndex(3284), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 602: Copy { + dest: StatePartIndex(3285), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 603: Copy { + dest: StatePartIndex(3286), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 604: Copy { + dest: StatePartIndex(3287), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 605: Copy { + dest: StatePartIndex(3288), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 606: Copy { + dest: StatePartIndex(3289), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 607: Copy { + dest: StatePartIndex(3290), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 608: Copy { + dest: StatePartIndex(3291), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 609: Copy { + dest: StatePartIndex(3292), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 610: Or { + dest: StatePartIndex(3309), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3308), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 611: Or { + dest: StatePartIndex(3310), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3309), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 612: Copy { + dest: StatePartIndex(3307), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + src: StatePartIndex(3310), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 613: Or { + dest: StatePartIndex(3345), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3344), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3307), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + }, + 614: Or { + dest: StatePartIndex(3349), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3307), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + rhs: StatePartIndex(3348), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 615: Or { + dest: StatePartIndex(3313), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3312), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 616: BranchIfZero { + target: 618, + value: StatePartIndex(3313), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 617: Copy { + dest: StatePartIndex(3311), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 618: BranchIfNonZero { + target: 620, + value: StatePartIndex(3313), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 619: Copy { + dest: StatePartIndex(3311), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(3319), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 620: CastToUInt { + dest: StatePartIndex(3350), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3311), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 621: BranchIfZero { + target: 623, + value: StatePartIndex(3349), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 622: Copy { + dest: StatePartIndex(3347), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(3350), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 623: Or { + dest: StatePartIndex(3331), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3330), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 624: Or { + dest: StatePartIndex(3332), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3331), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 625: Copy { + dest: StatePartIndex(3329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + src: StatePartIndex(3332), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 626: Or { + dest: StatePartIndex(3346), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3345), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 627: Copy { + dest: StatePartIndex(3343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + src: StatePartIndex(3346), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 628: Or { + dest: StatePartIndex(3416), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3415), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + }, + 629: Or { + dest: StatePartIndex(3420), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + rhs: StatePartIndex(3419), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 630: Or { + dest: StatePartIndex(3335), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3334), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 631: BranchIfZero { + target: 633, + value: StatePartIndex(3335), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 632: Copy { + dest: StatePartIndex(3333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 633: BranchIfNonZero { + target: 635, + value: StatePartIndex(3335), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 634: Copy { + dest: StatePartIndex(3333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(3339), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 635: ReadIndexed { + dest: StatePartIndex(3352), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3333) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> } */ [StatePartIndex(235) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 636: Add { + dest: StatePartIndex(3354), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3352), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 637: CastToUInt { + dest: StatePartIndex(3355), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3354), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 638: BranchIfNonZero { + target: 640, + value: StatePartIndex(3349), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 639: Copy { + dest: StatePartIndex(3347), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(3355), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 640: CastToUInt { + dest: StatePartIndex(3421), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3347), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 641: BranchIfZero { + target: 643, + value: StatePartIndex(3420), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 642: Copy { + dest: StatePartIndex(3418), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(3421), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 643: Or { + dest: StatePartIndex(3367), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3366), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 644: Or { + dest: StatePartIndex(3368), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3367), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 645: Copy { + dest: StatePartIndex(3365), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + src: StatePartIndex(3368), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 646: Or { + dest: StatePartIndex(3401), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3400), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3365), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + }, + 647: Or { + dest: StatePartIndex(3405), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3365), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + rhs: StatePartIndex(3404), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 648: Or { + dest: StatePartIndex(3371), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3370), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 649: BranchIfZero { + target: 651, + value: StatePartIndex(3371), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 650: Copy { + dest: StatePartIndex(3369), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 651: BranchIfNonZero { + target: 653, + value: StatePartIndex(3371), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 652: Copy { + dest: StatePartIndex(3369), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(3375), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 653: CastToUInt { + dest: StatePartIndex(3406), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3369), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 654: BranchIfZero { + target: 656, + value: StatePartIndex(3405), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 655: Copy { + dest: StatePartIndex(3403), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(3406), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 656: Or { + dest: StatePartIndex(3387), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3386), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 657: Or { + dest: StatePartIndex(3388), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3387), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 658: Copy { + dest: StatePartIndex(3385), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + src: StatePartIndex(3388), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 659: Or { + dest: StatePartIndex(3402), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3401), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3385), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 660: Copy { + dest: StatePartIndex(3399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + src: StatePartIndex(3402), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 661: Or { + dest: StatePartIndex(3417), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3416), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 662: Copy { + dest: StatePartIndex(3414), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + src: StatePartIndex(3417), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 663: Or { + dest: StatePartIndex(3557), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3556), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3414), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + }, + 664: Or { + dest: StatePartIndex(3561), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3414), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + rhs: StatePartIndex(3560), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 665: Or { + dest: StatePartIndex(3391), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3390), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 666: BranchIfZero { + target: 668, + value: StatePartIndex(3391), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 667: Copy { + dest: StatePartIndex(3389), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 668: BranchIfNonZero { + target: 670, + value: StatePartIndex(3391), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 669: Copy { + dest: StatePartIndex(3389), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(3395), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 670: ReadIndexed { + dest: StatePartIndex(3408), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3389) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> } */ [StatePartIndex(238) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 671: Add { + dest: StatePartIndex(3409), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3408), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 672: CastToUInt { + dest: StatePartIndex(3410), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3409), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 673: BranchIfNonZero { + target: 675, + value: StatePartIndex(3405), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 674: Copy { + dest: StatePartIndex(3403), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(3410), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 675: ReadIndexed { + dest: StatePartIndex(3423), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3403) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> } */ [StatePartIndex(239) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 676: Add { + dest: StatePartIndex(3425), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3423), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3424), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 677: CastToUInt { + dest: StatePartIndex(3426), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3425), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 678: BranchIfNonZero { + target: 680, + value: StatePartIndex(3420), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 679: Copy { + dest: StatePartIndex(3418), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(3426), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 680: CastToUInt { + dest: StatePartIndex(3562), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3418), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 681: BranchIfZero { + target: 683, + value: StatePartIndex(3561), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 682: Copy { + dest: StatePartIndex(3559), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(3562), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 683: Or { + dest: StatePartIndex(3438), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3437), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 684: Or { + dest: StatePartIndex(3439), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3438), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 685: Copy { + dest: StatePartIndex(3436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + src: StatePartIndex(3439), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 686: Or { + dest: StatePartIndex(3472), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3471), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + }, + 687: Or { + dest: StatePartIndex(3476), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + rhs: StatePartIndex(3475), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 688: Or { + dest: StatePartIndex(3442), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3441), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 689: BranchIfZero { + target: 691, + value: StatePartIndex(3442), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 690: Copy { + dest: StatePartIndex(3440), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 691: BranchIfNonZero { + target: 693, + value: StatePartIndex(3442), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 692: Copy { + dest: StatePartIndex(3440), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(3446), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 693: CastToUInt { + dest: StatePartIndex(3477), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3440), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 694: BranchIfZero { + target: 696, + value: StatePartIndex(3476), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 695: Copy { + dest: StatePartIndex(3474), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(3477), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 696: Or { + dest: StatePartIndex(3458), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3457), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 697: Or { + dest: StatePartIndex(3459), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3458), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 698: Copy { + dest: StatePartIndex(3456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + src: StatePartIndex(3459), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 699: Or { + dest: StatePartIndex(3473), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3472), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 700: Copy { + dest: StatePartIndex(3470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + src: StatePartIndex(3473), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 701: Or { + dest: StatePartIndex(3542), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3541), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + }, + 702: Or { + dest: StatePartIndex(3546), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + rhs: StatePartIndex(3545), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 703: Or { + dest: StatePartIndex(3462), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3461), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 704: BranchIfZero { + target: 706, + value: StatePartIndex(3462), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 705: Copy { + dest: StatePartIndex(3460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 706: BranchIfNonZero { + target: 708, + value: StatePartIndex(3462), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 707: Copy { + dest: StatePartIndex(3460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(3466), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 708: ReadIndexed { + dest: StatePartIndex(3479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3460) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> } */ [StatePartIndex(242) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 709: Add { + dest: StatePartIndex(3480), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 710: CastToUInt { + dest: StatePartIndex(3481), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3480), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 711: BranchIfNonZero { + target: 713, + value: StatePartIndex(3476), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 712: Copy { + dest: StatePartIndex(3474), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(3481), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 713: CastToUInt { + dest: StatePartIndex(3547), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3474), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 714: BranchIfZero { + target: 716, + value: StatePartIndex(3546), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 715: Copy { + dest: StatePartIndex(3544), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(3547), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 716: Or { + dest: StatePartIndex(3493), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3492), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 717: Or { + dest: StatePartIndex(3494), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3493), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 718: Copy { + dest: StatePartIndex(3491), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + src: StatePartIndex(3494), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 719: Or { + dest: StatePartIndex(3527), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3526), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3491), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + }, + 720: Or { + dest: StatePartIndex(3531), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3491), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + rhs: StatePartIndex(3530), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 721: Or { + dest: StatePartIndex(3497), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3496), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 722: BranchIfZero { + target: 724, + value: StatePartIndex(3497), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 723: Copy { + dest: StatePartIndex(3495), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 724: BranchIfNonZero { + target: 726, + value: StatePartIndex(3497), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 725: Copy { + dest: StatePartIndex(3495), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(3501), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 726: CastToUInt { + dest: StatePartIndex(3532), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3495), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 727: BranchIfZero { + target: 729, + value: StatePartIndex(3531), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 728: Copy { + dest: StatePartIndex(3529), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(3532), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 729: Or { + dest: StatePartIndex(3513), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3512), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 730: Or { + dest: StatePartIndex(3514), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3513), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 731: Copy { + dest: StatePartIndex(3511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + src: StatePartIndex(3514), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 732: Or { + dest: StatePartIndex(3528), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3527), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 733: Copy { + dest: StatePartIndex(3525), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + src: StatePartIndex(3528), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 734: Or { + dest: StatePartIndex(3543), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3542), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3525), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 735: Copy { + dest: StatePartIndex(3540), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + src: StatePartIndex(3543), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 736: Or { + dest: StatePartIndex(3558), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3557), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3540), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 737: Copy { + dest: StatePartIndex(3555), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + src: StatePartIndex(3558), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 738: Or { + dest: StatePartIndex(3572), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3555), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + rhs: StatePartIndex(3571), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 739: Or { + dest: StatePartIndex(3517), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3516), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 740: BranchIfZero { + target: 742, + value: StatePartIndex(3517), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 741: Copy { + dest: StatePartIndex(3515), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 742: BranchIfNonZero { + target: 744, + value: StatePartIndex(3517), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 743: Copy { + dest: StatePartIndex(3515), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(3521), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 744: ReadIndexed { + dest: StatePartIndex(3534), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3515) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> } */ [StatePartIndex(245) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 745: Add { + dest: StatePartIndex(3535), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3534), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 746: CastToUInt { + dest: StatePartIndex(3536), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3535), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 747: BranchIfNonZero { + target: 749, + value: StatePartIndex(3531), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 748: Copy { + dest: StatePartIndex(3529), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(3536), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 749: ReadIndexed { + dest: StatePartIndex(3549), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3529) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> } */ [StatePartIndex(246) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 750: Add { + dest: StatePartIndex(3550), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3549), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3424), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 751: CastToUInt { + dest: StatePartIndex(3551), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3550), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 752: BranchIfNonZero { + target: 754, + value: StatePartIndex(3546), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 753: Copy { + dest: StatePartIndex(3544), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(3551), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 754: ReadIndexed { + dest: StatePartIndex(3564), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3544) /* (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> } */ [StatePartIndex(247) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 755: Add { + dest: StatePartIndex(3566), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(3564), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + rhs: StatePartIndex(3565), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + }, + 756: CastToUInt { + dest: StatePartIndex(3567), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3566), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 757: BranchIfNonZero { + target: 759, + value: StatePartIndex(3561), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 758: Copy { + dest: StatePartIndex(3559), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(3567), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 759: Copy { + dest: StatePartIndex(3573), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 760: Copy { + dest: StatePartIndex(3574), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, + src: StatePartIndex(3559), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + }, + 761: Shl { + dest: StatePartIndex(3575), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3574), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, + rhs: 1, + }, + 762: Or { + dest: StatePartIndex(3576), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3573), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3575), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, + }, + 763: CastToUInt { + dest: StatePartIndex(3577), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3576), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + dest_width: 5, + }, + 764: Copy { + dest: StatePartIndex(3578), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3577), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 765: BranchIfZero { + target: 767, + value: StatePartIndex(3572), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:107:13 + 766: Copy { + dest: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3578), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 767: BranchIfNonZero { + target: 769, + value: StatePartIndex(3572), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:112:13 + 768: Copy { + dest: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:20:11 + 769: AndBigWithSmallImmediate { + dest: StatePartIndex(226), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, rhs: 0x1, }, // at: unit_free_regs_tracker.rs:7:1 - 423: Copy { - dest: StatePartIndex(392), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 770: Copy { + dest: StatePartIndex(3243), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, }, - 424: SliceInt { - dest: StatePartIndex(393), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(392), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + 771: SliceInt { + dest: StatePartIndex(3244), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3243), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, start: 1, len: 4, }, - 425: CastBigToArrayIndex { - dest: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(393), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + // at: reg_alloc.rs:286:13 + 772: Copy { + dest: StatePartIndex(3233), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 773: AndBigWithSmallImmediate { + dest: StatePartIndex(251), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3233), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 774: Copy { + dest: StatePartIndex(3581), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3233), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 775: SliceInt { + dest: StatePartIndex(3582), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3581), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 776: Copy { + dest: StatePartIndex(3754), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3582), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 777: Copy { + dest: StatePartIndex(3751), // (0x1) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(3753), // (0x1) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 778: Copy { + dest: StatePartIndex(3752), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(3754), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 779: Copy { + dest: StatePartIndex(3748), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 780: Copy { + dest: StatePartIndex(3749), // (0x1) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(3751), // (0x1) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 781: Copy { + dest: StatePartIndex(3750), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(3752), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 782: Shl { + dest: StatePartIndex(3755), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(3750), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 783: Or { + dest: StatePartIndex(3756), // (0x1) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(3749), // (0x1) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(3755), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 784: Shl { + dest: StatePartIndex(3757), // (0x2) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(3756), // (0x1) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 785: Or { + dest: StatePartIndex(3758), // (0x3) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(3748), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3757), // (0x2) SlotDebugData { name: "", ty: UInt<7> }, + }, + 786: CastToUInt { + dest: StatePartIndex(3759), // (0x3) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(3758), // (0x3) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 787: Copy { + dest: StatePartIndex(3760), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(3759), // (0x3) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:294:9 + 788: Copy { + dest: StatePartIndex(3234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 789: Or { + dest: StatePartIndex(4120), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4119), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 790: Or { + dest: StatePartIndex(4121), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4120), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 791: Copy { + dest: StatePartIndex(4118), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + src: StatePartIndex(4121), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 792: Or { + dest: StatePartIndex(4154), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4153), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4118), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + }, + 793: Or { + dest: StatePartIndex(4158), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4118), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + rhs: StatePartIndex(4157), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 794: Or { + dest: StatePartIndex(4124), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4123), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 795: BranchIfZero { + target: 797, + value: StatePartIndex(4124), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 796: Copy { + dest: StatePartIndex(4122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 797: BranchIfNonZero { + target: 799, + value: StatePartIndex(4124), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 798: Copy { + dest: StatePartIndex(4122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(4128), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 799: CastToUInt { + dest: StatePartIndex(4159), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 800: BranchIfZero { + target: 802, + value: StatePartIndex(4158), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 801: Copy { + dest: StatePartIndex(4156), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(4159), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 802: Or { + dest: StatePartIndex(4140), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4139), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 803: Or { + dest: StatePartIndex(4141), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4140), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 804: Copy { + dest: StatePartIndex(4138), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + src: StatePartIndex(4141), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 805: Or { + dest: StatePartIndex(4155), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4154), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4138), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 806: Copy { + dest: StatePartIndex(4152), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + src: StatePartIndex(4155), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 807: Or { + dest: StatePartIndex(4224), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4223), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4152), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + }, + 808: Or { + dest: StatePartIndex(4228), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4152), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + rhs: StatePartIndex(4227), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 809: Or { + dest: StatePartIndex(4144), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4143), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 810: BranchIfZero { + target: 812, + value: StatePartIndex(4144), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 811: Copy { + dest: StatePartIndex(4142), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 812: BranchIfNonZero { + target: 814, + value: StatePartIndex(4144), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 813: Copy { + dest: StatePartIndex(4142), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(4148), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 814: ReadIndexed { + dest: StatePartIndex(4161), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4142) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> } */ [StatePartIndex(286) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 815: Add { + dest: StatePartIndex(4162), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4161), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 816: CastToUInt { + dest: StatePartIndex(4163), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4162), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 817: BranchIfNonZero { + target: 819, + value: StatePartIndex(4158), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 818: Copy { + dest: StatePartIndex(4156), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(4163), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 819: CastToUInt { + dest: StatePartIndex(4229), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4156), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 820: BranchIfZero { + target: 822, + value: StatePartIndex(4228), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 821: Copy { + dest: StatePartIndex(4226), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(4229), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 822: Or { + dest: StatePartIndex(4175), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4174), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 823: Or { + dest: StatePartIndex(4176), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4175), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 824: Copy { + dest: StatePartIndex(4173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + src: StatePartIndex(4176), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 825: Or { + dest: StatePartIndex(4209), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4208), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + }, + 826: Or { + dest: StatePartIndex(4213), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + rhs: StatePartIndex(4212), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 827: Or { + dest: StatePartIndex(4179), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4178), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 828: BranchIfZero { + target: 830, + value: StatePartIndex(4179), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 829: Copy { + dest: StatePartIndex(4177), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 830: BranchIfNonZero { + target: 832, + value: StatePartIndex(4179), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 831: Copy { + dest: StatePartIndex(4177), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(4183), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 832: CastToUInt { + dest: StatePartIndex(4214), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4177), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 833: BranchIfZero { + target: 835, + value: StatePartIndex(4213), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 834: Copy { + dest: StatePartIndex(4211), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(4214), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 835: Or { + dest: StatePartIndex(4195), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4194), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 836: Or { + dest: StatePartIndex(4196), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4195), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 837: Copy { + dest: StatePartIndex(4193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + src: StatePartIndex(4196), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 838: Or { + dest: StatePartIndex(4210), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4209), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 839: Copy { + dest: StatePartIndex(4207), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + src: StatePartIndex(4210), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 840: Or { + dest: StatePartIndex(4225), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4224), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4207), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 841: Copy { + dest: StatePartIndex(4222), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + src: StatePartIndex(4225), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 842: Or { + dest: StatePartIndex(4364), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4363), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4222), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + }, + 843: Or { + dest: StatePartIndex(4368), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4222), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + rhs: StatePartIndex(4367), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 844: Or { + dest: StatePartIndex(4199), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4198), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 845: BranchIfZero { + target: 847, + value: StatePartIndex(4199), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 846: Copy { + dest: StatePartIndex(4197), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 847: BranchIfNonZero { + target: 849, + value: StatePartIndex(4199), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 848: Copy { + dest: StatePartIndex(4197), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(4203), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 849: ReadIndexed { + dest: StatePartIndex(4216), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4197) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> } */ [StatePartIndex(289) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 850: Add { + dest: StatePartIndex(4217), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4216), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 851: CastToUInt { + dest: StatePartIndex(4218), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4217), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 852: BranchIfNonZero { + target: 854, + value: StatePartIndex(4213), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 853: Copy { + dest: StatePartIndex(4211), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(4218), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 854: ReadIndexed { + dest: StatePartIndex(4231), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4211) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> } */ [StatePartIndex(290) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 855: Add { + dest: StatePartIndex(4232), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4231), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3424), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 856: CastToUInt { + dest: StatePartIndex(4233), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4232), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 857: BranchIfNonZero { + target: 859, + value: StatePartIndex(4228), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 858: Copy { + dest: StatePartIndex(4226), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(4233), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 859: CastToUInt { + dest: StatePartIndex(4369), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4226), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 860: BranchIfZero { + target: 862, + value: StatePartIndex(4368), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 861: Copy { + dest: StatePartIndex(4366), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(4369), // (0x7) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 862: Or { + dest: StatePartIndex(4245), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4244), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 863: Or { + dest: StatePartIndex(4246), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4245), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 864: Copy { + dest: StatePartIndex(4243), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + src: StatePartIndex(4246), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 865: Or { + dest: StatePartIndex(4279), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4278), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4243), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + }, + 866: Or { + dest: StatePartIndex(4283), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4243), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + rhs: StatePartIndex(4282), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 867: Or { + dest: StatePartIndex(4249), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4248), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 868: BranchIfZero { + target: 870, + value: StatePartIndex(4249), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 869: Copy { + dest: StatePartIndex(4247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 870: BranchIfNonZero { + target: 872, + value: StatePartIndex(4249), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 871: Copy { + dest: StatePartIndex(4247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(4253), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 872: CastToUInt { + dest: StatePartIndex(4284), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 873: BranchIfZero { + target: 875, + value: StatePartIndex(4283), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 874: Copy { + dest: StatePartIndex(4281), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(4284), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 875: Or { + dest: StatePartIndex(4265), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4264), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 876: Or { + dest: StatePartIndex(4266), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4265), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 877: Copy { + dest: StatePartIndex(4263), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + src: StatePartIndex(4266), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 878: Or { + dest: StatePartIndex(4280), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4279), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4263), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 879: Copy { + dest: StatePartIndex(4277), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + src: StatePartIndex(4280), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 880: Or { + dest: StatePartIndex(4349), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4348), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4277), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + }, + 881: Or { + dest: StatePartIndex(4353), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4277), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + rhs: StatePartIndex(4352), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 882: Or { + dest: StatePartIndex(4269), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4268), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 883: BranchIfZero { + target: 885, + value: StatePartIndex(4269), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 884: Copy { + dest: StatePartIndex(4267), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 885: BranchIfNonZero { + target: 887, + value: StatePartIndex(4269), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 886: Copy { + dest: StatePartIndex(4267), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(4273), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 887: ReadIndexed { + dest: StatePartIndex(4286), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4267) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> } */ [StatePartIndex(293) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 888: Add { + dest: StatePartIndex(4287), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4286), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 889: CastToUInt { + dest: StatePartIndex(4288), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4287), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 890: BranchIfNonZero { + target: 892, + value: StatePartIndex(4283), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 891: Copy { + dest: StatePartIndex(4281), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(4288), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 892: CastToUInt { + dest: StatePartIndex(4354), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4281), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 893: BranchIfZero { + target: 895, + value: StatePartIndex(4353), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 894: Copy { + dest: StatePartIndex(4351), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(4354), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 895: Or { + dest: StatePartIndex(4300), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4299), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 896: Or { + dest: StatePartIndex(4301), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4300), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 897: Copy { + dest: StatePartIndex(4298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + src: StatePartIndex(4301), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 898: Or { + dest: StatePartIndex(4334), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4333), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + }, + 899: Or { + dest: StatePartIndex(4338), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4298), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + rhs: StatePartIndex(4337), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 900: Or { + dest: StatePartIndex(4304), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4303), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 901: BranchIfZero { + target: 903, + value: StatePartIndex(4304), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 902: Copy { + dest: StatePartIndex(4302), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 903: BranchIfNonZero { + target: 905, + value: StatePartIndex(4304), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 904: Copy { + dest: StatePartIndex(4302), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(4308), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 905: CastToUInt { + dest: StatePartIndex(4339), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4302), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 906: BranchIfZero { + target: 908, + value: StatePartIndex(4338), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 907: Copy { + dest: StatePartIndex(4336), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(4339), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 908: Or { + dest: StatePartIndex(4320), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4319), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 909: Or { + dest: StatePartIndex(4321), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4320), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 910: Copy { + dest: StatePartIndex(4318), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + src: StatePartIndex(4321), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 911: Or { + dest: StatePartIndex(4335), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4334), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4318), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 912: Copy { + dest: StatePartIndex(4332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + src: StatePartIndex(4335), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 913: Or { + dest: StatePartIndex(4350), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4349), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 914: Copy { + dest: StatePartIndex(4347), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + src: StatePartIndex(4350), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 915: Or { + dest: StatePartIndex(4365), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4364), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4347), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 916: Copy { + dest: StatePartIndex(4362), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + src: StatePartIndex(4365), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 917: Or { + dest: StatePartIndex(4378), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4362), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + rhs: StatePartIndex(4377), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 918: Or { + dest: StatePartIndex(4324), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(4323), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 919: BranchIfZero { + target: 921, + value: StatePartIndex(4324), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 920: Copy { + dest: StatePartIndex(4322), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(3315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 921: BranchIfNonZero { + target: 923, + value: StatePartIndex(4324), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 922: Copy { + dest: StatePartIndex(4322), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(4328), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 923: ReadIndexed { + dest: StatePartIndex(4341), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4322) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> } */ [StatePartIndex(296) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 924: Add { + dest: StatePartIndex(4342), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4341), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(3353), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 925: CastToUInt { + dest: StatePartIndex(4343), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4342), // (0x3) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 926: BranchIfNonZero { + target: 928, + value: StatePartIndex(4338), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 927: Copy { + dest: StatePartIndex(4336), // (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(4343), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 928: ReadIndexed { + dest: StatePartIndex(4356), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4336) /* (0x3) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> } */ [StatePartIndex(297) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 929: Add { + dest: StatePartIndex(4357), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4356), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(3424), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 930: CastToUInt { + dest: StatePartIndex(4358), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4357), // (0x7) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 931: BranchIfNonZero { + target: 933, + value: StatePartIndex(4353), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 932: Copy { + dest: StatePartIndex(4351), // (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(4358), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 933: ReadIndexed { + dest: StatePartIndex(4371), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4351) /* (0x7) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> } */ [StatePartIndex(298) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 934: Add { + dest: StatePartIndex(4372), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(4371), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + rhs: StatePartIndex(3565), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + }, + 935: CastToUInt { + dest: StatePartIndex(4373), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4372), // (0xf) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 936: BranchIfNonZero { + target: 938, + value: StatePartIndex(4368), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 937: Copy { + dest: StatePartIndex(4366), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(4373), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 938: Copy { + dest: StatePartIndex(4379), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 939: Copy { + dest: StatePartIndex(4380), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, + src: StatePartIndex(4366), // (0xf) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + }, + 940: Shl { + dest: StatePartIndex(4381), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(4380), // (0xf) SlotDebugData { name: ".1", ty: UInt<4> }, + rhs: 1, + }, + 941: Or { + dest: StatePartIndex(4382), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(4379), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(4381), // (0x1e) SlotDebugData { name: "", ty: UInt<5> }, + }, + 942: CastToUInt { + dest: StatePartIndex(4383), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4382), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + dest_width: 5, + }, + 943: Copy { + dest: StatePartIndex(4384), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4383), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 944: BranchIfZero { + target: 946, + value: StatePartIndex(4378), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:107:13 + 945: Copy { + dest: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4384), // (0x1f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 946: BranchIfNonZero { + target: 948, + value: StatePartIndex(4378), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:112:13 + 947: Copy { + dest: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3297), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:20:11 + 948: AndBigWithSmallImmediate { + dest: StatePartIndex(277), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 949: Copy { + dest: StatePartIndex(4072), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 950: SliceInt { + dest: StatePartIndex(4073), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4072), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: reg_alloc.rs:286:13 + 951: Copy { + dest: StatePartIndex(4062), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 952: AndBigWithSmallImmediate { + dest: StatePartIndex(302), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4062), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 953: Copy { + dest: StatePartIndex(4387), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4062), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 954: SliceInt { + dest: StatePartIndex(4388), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4387), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 955: Copy { + dest: StatePartIndex(4543), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4388), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 956: Copy { + dest: StatePartIndex(4539), // (0x2) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(4541), // (0x2) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 957: Copy { + dest: StatePartIndex(4540), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(4543), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 958: Copy { + dest: StatePartIndex(4536), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 959: Copy { + dest: StatePartIndex(4537), // (0x2) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(4539), // (0x2) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 960: Copy { + dest: StatePartIndex(4538), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(4540), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 961: Shl { + dest: StatePartIndex(4544), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(4538), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 962: Or { + dest: StatePartIndex(4545), // (0x2) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(4537), // (0x2) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(4544), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 963: Shl { + dest: StatePartIndex(4546), // (0x4) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(4545), // (0x2) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 964: Or { + dest: StatePartIndex(4547), // (0x5) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(4536), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(4546), // (0x4) SlotDebugData { name: "", ty: UInt<7> }, + }, + 965: CastToUInt { + dest: StatePartIndex(4548), // (0x5) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(4547), // (0x5) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 966: Copy { + dest: StatePartIndex(4549), // (0x5) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(4548), // (0x5) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:294:9 + 967: Copy { + dest: StatePartIndex(4063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 968: Const { + dest: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: reg_alloc.rs:79:9 + 969: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 970: Copy { + dest: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: alu_branch.rs:23:5 + 971: Copy { + dest: StatePartIndex(3092), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:271:13 + 972: Copy { + dest: StatePartIndex(3088), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.ready", ty: Bool }, + src: StatePartIndex(3092), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.ready", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 973: NotU { + dest: StatePartIndex(3585), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3088), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.ready", ty: Bool }, + width: 1, + }, + // at: unit_free_regs_tracker.rs:29:9 + 974: Copy { + dest: StatePartIndex(3238), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:33:9 + 975: BranchIfZero { + target: 977, + value: StatePartIndex(3238), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:34:13 + 976: Copy { + dest: StatePartIndex(3293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3237), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: ready_valid.rs:30:27 + 977: AndBigWithSmallImmediate { + dest: StatePartIndex(231), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 978: Copy { + dest: StatePartIndex(3294), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 979: SliceInt { + dest: StatePartIndex(3295), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3294), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 980: CastBigToArrayIndex { + dest: StatePartIndex(232), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3295), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, // at: unit_free_regs_tracker.rs:31:9 - 426: BranchIfSmallNeImmediate { - target: 428, - lhs: StatePartIndex(29), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + 981: BranchIfSmallNeImmediate { + target: 983, + lhs: StatePartIndex(231), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, rhs: 0x1, }, // at: unit_free_regs_tracker.rs:32:13 - 427: WriteIndexed { - dest: StatePartIndex(359) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(30) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:150:13 - 428: Copy { - dest: StatePartIndex(330), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].ready", ty: Bool }, - src: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, - }, - // at: reg_alloc.rs:41:1 - 429: Const { - dest: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x0, - }, - 430: Copy { - dest: StatePartIndex(270), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, - src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: reg_alloc.rs:50:5 - 431: Copy { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, - src: StatePartIndex(270), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, - }, - // at: reg_alloc.rs:41:1 - 432: Copy { - dest: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - 433: Copy { - dest: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: reg_alloc.rs:87:21 - 434: Copy { - dest: StatePartIndex(293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - 435: Copy { - dest: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - // at: reg_alloc.rs:41:1 - 436: Copy { - dest: StatePartIndex(266), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, - }, - 437: SliceInt { - dest: StatePartIndex(267), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(266), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - start: 1, - len: 1, - }, - 438: Copy { - dest: StatePartIndex(268), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, - src: StatePartIndex(267), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: reg_alloc.rs:48:11 - 439: AndBigWithSmallImmediate { - dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Enum {Trap, ICacheFlush} }, - lhs: StatePartIndex(268), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, - rhs: 0x1, - }, - 440: AndBigWithSmallImmediate { - dest: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 441: Copy { - dest: StatePartIndex(140), // (0x802180000000000806051) SlotDebugData { name: "", ty: UInt<135> }, - src: StatePartIndex(4), // (0x802180000000000806051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, - }, - 442: SliceInt { - dest: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, - src: StatePartIndex(140), // (0x802180000000000806051) SlotDebugData { name: "", ty: UInt<135> }, - start: 1, - len: 134, - }, - 443: SliceInt { - dest: StatePartIndex(142), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, - src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, - start: 0, - len: 69, - }, - 444: Copy { - dest: StatePartIndex(143), // (0xc0000000000403028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - src: StatePartIndex(142), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, - }, - 445: SliceInt { - dest: StatePartIndex(144), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, - start: 69, - len: 1, - }, - 446: Copy { - dest: StatePartIndex(145), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(144), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 447: SliceInt { - dest: StatePartIndex(146), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, - start: 70, - len: 64, - }, - 448: Copy { - dest: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - src: StatePartIndex(143), // (0xc0000000000403028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - }, - 449: Copy { - dest: StatePartIndex(138), // (0x0) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, - src: StatePartIndex(145), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 450: Copy { - dest: StatePartIndex(139), // (0x1004) SlotDebugData { name: ".pc", ty: UInt<64> }, - src: StatePartIndex(146), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, - }, - // at: reg_alloc.rs:48:11 - 451: AndBigWithSmallImmediate { - dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - lhs: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - rhs: 0x3, - }, - // at: unit.rs:107:1 - 452: BranchIfSmallNeImmediate { - target: 454, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x0, - }, - 453: Copy { - dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 454: BranchIfSmallNeImmediate { - target: 456, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x1, - }, - 455: Copy { - dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 456: BranchIfSmallNeImmediate { - target: 458, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x2, - }, - 457: Copy { - dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 458: AndBigWithSmallImmediate { - dest: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - lhs: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x3, - }, - 459: BranchIfSmallNeImmediate { - target: 461, - lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x0, - }, - 460: Copy { - dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 461: BranchIfSmallNeImmediate { - target: 463, - lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x1, - }, - 462: Copy { - dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 463: BranchIfSmallNeImmediate { - target: 465, - lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x2, - }, - 464: Copy { - dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:41:1 - 465: Copy { - dest: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, - src: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - }, - 466: SliceInt { - dest: StatePartIndex(148), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, - src: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, - start: 2, - len: 67, - }, - 467: Copy { - dest: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - src: StatePartIndex(148), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, - }, - // at: reg_alloc.rs:48:11 - 468: AndBigWithSmallImmediate { - dest: StatePartIndex(9), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, - lhs: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - rhs: 0x3, - }, - // at: reg_alloc.rs:41:1 - 469: Copy { - dest: StatePartIndex(177), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, - src: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - }, - 470: SliceInt { - dest: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - src: StatePartIndex(177), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, - start: 2, - len: 65, - }, - 471: SliceInt { - dest: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 0, - len: 61, - }, - 472: SliceInt { - dest: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - src: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, - start: 0, - len: 58, - }, - 473: SliceInt { - dest: StatePartIndex(181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - start: 0, - len: 0, - }, - 474: SliceInt { - dest: StatePartIndex(182), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - start: 0, - len: 8, - }, - 475: SliceInt { - dest: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - start: 8, - len: 24, - }, - 476: SliceInt { - dest: StatePartIndex(187), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 477: SliceInt { - dest: StatePartIndex(188), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 478: SliceInt { - dest: StatePartIndex(189), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 479: Copy { - dest: StatePartIndex(183), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(187), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 480: Copy { - dest: StatePartIndex(184), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(188), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 481: Copy { - dest: StatePartIndex(185), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(189), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - 482: SliceInt { - dest: StatePartIndex(190), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - start: 32, - len: 25, - }, - 483: SliceInt { - dest: StatePartIndex(191), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, - start: 57, - len: 1, - }, - 484: CastToSInt { - dest: StatePartIndex(192), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(191), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 485: Copy { - dest: StatePartIndex(170), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, - src: StatePartIndex(181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - }, - 486: Copy { - dest: StatePartIndex(171), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(182), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 487: Copy { - dest: StatePartIndex(172), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(183), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 488: Copy { - dest: StatePartIndex(173), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(184), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 489: Copy { - dest: StatePartIndex(174), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(185), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 490: Copy { - dest: StatePartIndex(175), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(190), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - }, - 491: Copy { - dest: StatePartIndex(176), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(192), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - 492: SliceInt { - dest: StatePartIndex(193), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, - start: 58, - len: 3, - }, - 493: Copy { - dest: StatePartIndex(194), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(193), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - }, - 494: Copy { - dest: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(170), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, - }, - 495: Copy { - dest: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - src: StatePartIndex(171), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, - }, - 496: Copy { - dest: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - src: StatePartIndex(172), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - }, - 497: Copy { - dest: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - src: StatePartIndex(173), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - }, - 498: Copy { - dest: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - src: StatePartIndex(174), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - }, - 499: Copy { - dest: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - src: StatePartIndex(175), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - }, - 500: Copy { - dest: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - }, - 501: Copy { - dest: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(194), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 502: SliceInt { - dest: StatePartIndex(195), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 61, - len: 1, - }, - 503: Copy { - dest: StatePartIndex(196), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(195), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 504: SliceInt { - dest: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 62, - len: 1, - }, - 505: Copy { - dest: StatePartIndex(198), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 506: SliceInt { - dest: StatePartIndex(199), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 63, - len: 1, - }, - 507: Copy { - dest: StatePartIndex(200), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(199), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 508: SliceInt { - dest: StatePartIndex(201), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 64, - len: 1, - }, - 509: Copy { - dest: StatePartIndex(202), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(201), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 510: Copy { - dest: StatePartIndex(150), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - }, - 511: Copy { - dest: StatePartIndex(151), // (0x2) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, - src: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - }, - 512: Copy { - dest: StatePartIndex(152), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, - src: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - }, - 513: Copy { - dest: StatePartIndex(153), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, - src: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - }, - 514: Copy { - dest: StatePartIndex(154), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, - src: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - }, - 515: Copy { - dest: StatePartIndex(155), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, - src: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - }, - 516: Copy { - dest: StatePartIndex(156), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - }, - 517: Copy { - dest: StatePartIndex(157), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 518: Copy { - dest: StatePartIndex(158), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, - src: StatePartIndex(196), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 519: Copy { - dest: StatePartIndex(159), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, - src: StatePartIndex(198), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 520: Copy { - dest: StatePartIndex(160), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, - src: StatePartIndex(200), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 521: Copy { - dest: StatePartIndex(161), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, - src: StatePartIndex(202), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:48:11 - 522: AndBigWithSmallImmediate { - dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - lhs: StatePartIndex(157), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - rhs: 0x7, - }, - // at: reg_alloc.rs:41:1 - 523: SliceInt { - dest: StatePartIndex(212), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, - start: 61, - len: 4, - }, - 524: Copy { - dest: StatePartIndex(203), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - }, - 525: Copy { - dest: StatePartIndex(204), // (0x2) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, - src: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - }, - 526: Copy { - dest: StatePartIndex(205), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, - src: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - }, - 527: Copy { - dest: StatePartIndex(206), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, - src: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - }, - 528: Copy { - dest: StatePartIndex(207), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, - src: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - }, - 529: Copy { - dest: StatePartIndex(208), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, - src: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - }, - 530: Copy { - dest: StatePartIndex(209), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - }, - 531: Copy { - dest: StatePartIndex(210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 532: Copy { - dest: StatePartIndex(211), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, - src: StatePartIndex(212), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: reg_alloc.rs:48:11 - 533: AndBigWithSmallImmediate { - dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - lhs: StatePartIndex(210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - rhs: 0x7, - }, - // at: reg_alloc.rs:41:1 - 534: SliceInt { - dest: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, - start: 2, - len: 60, - }, - 535: Copy { - dest: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - src: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - }, - // at: reg_alloc.rs:48:11 - 536: AndBigWithSmallImmediate { - dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, - lhs: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 537: Copy { - dest: StatePartIndex(229), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - }, - 538: SliceInt { - dest: StatePartIndex(230), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(229), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - start: 1, - len: 59, - }, - 539: SliceInt { - dest: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(230), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 59, - }, - 540: SliceInt { - dest: StatePartIndex(232), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 1, - }, - 541: SliceInt { - dest: StatePartIndex(233), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 1, - len: 8, - }, - 542: SliceInt { - dest: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 9, - len: 24, - }, - 543: SliceInt { - dest: StatePartIndex(238), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 544: SliceInt { - dest: StatePartIndex(239), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 545: SliceInt { - dest: StatePartIndex(240), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 546: Copy { - dest: StatePartIndex(234), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(238), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 547: Copy { - dest: StatePartIndex(235), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(239), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 548: Copy { - dest: StatePartIndex(236), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(240), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - 549: SliceInt { - dest: StatePartIndex(241), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 33, - len: 25, - }, - 550: SliceInt { - dest: StatePartIndex(242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 58, - len: 1, - }, - 551: CastToSInt { - dest: StatePartIndex(243), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 552: Copy { - dest: StatePartIndex(222), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - src: StatePartIndex(232), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 553: Copy { - dest: StatePartIndex(223), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(233), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 554: Copy { - dest: StatePartIndex(224), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(234), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 555: Copy { - dest: StatePartIndex(225), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(235), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 556: Copy { - dest: StatePartIndex(226), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(236), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 557: Copy { - dest: StatePartIndex(227), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(241), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - }, - 558: Copy { - dest: StatePartIndex(228), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(243), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - 559: Copy { - dest: StatePartIndex(215), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, - src: StatePartIndex(222), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - }, - 560: Copy { - dest: StatePartIndex(216), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - src: StatePartIndex(223), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, - }, - 561: Copy { - dest: StatePartIndex(217), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - src: StatePartIndex(224), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - }, - 562: Copy { - dest: StatePartIndex(218), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - src: StatePartIndex(225), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - }, - 563: Copy { - dest: StatePartIndex(219), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - src: StatePartIndex(226), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - }, - 564: Copy { - dest: StatePartIndex(220), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - src: StatePartIndex(227), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - }, - 565: Copy { - dest: StatePartIndex(221), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(228), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - }, - 566: Copy { - dest: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - src: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - }, - // at: reg_alloc.rs:48:11 - 567: AndBigWithSmallImmediate { - dest: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, - lhs: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 568: Copy { - dest: StatePartIndex(252), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - }, - 569: SliceInt { - dest: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(252), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, - start: 1, - len: 59, - }, - 570: SliceInt { - dest: StatePartIndex(254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 1, - }, - 571: SliceInt { - dest: StatePartIndex(255), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 1, - len: 8, - }, - 572: SliceInt { - dest: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 9, - len: 24, - }, - 573: SliceInt { - dest: StatePartIndex(260), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 574: SliceInt { - dest: StatePartIndex(261), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 575: SliceInt { - dest: StatePartIndex(262), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 576: Copy { - dest: StatePartIndex(256), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(260), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 577: Copy { - dest: StatePartIndex(257), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(261), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 578: Copy { - dest: StatePartIndex(258), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(262), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - 579: SliceInt { - dest: StatePartIndex(263), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 33, - len: 25, - }, - 580: SliceInt { - dest: StatePartIndex(264), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, - start: 58, - len: 1, - }, - 581: CastToSInt { - dest: StatePartIndex(265), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(264), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 582: Copy { - dest: StatePartIndex(245), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - src: StatePartIndex(254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 583: Copy { - dest: StatePartIndex(246), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(255), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 584: Copy { - dest: StatePartIndex(247), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(256), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 585: Copy { - dest: StatePartIndex(248), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(257), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 586: Copy { - dest: StatePartIndex(249), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(258), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 587: Copy { - dest: StatePartIndex(250), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(263), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, - }, - 588: Copy { - dest: StatePartIndex(251), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(265), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - // at: reg_alloc.rs:48:11 - 589: AndBigWithSmallImmediate { - dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(4), // (0x802180000000000806051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:70:9 - 590: BranchIfSmallNeImmediate { - target: 592, - lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:71:13 - 591: Copy { - dest: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, - src: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - }, - // at: reg_alloc.rs:41:1 - 592: Copy { - dest: StatePartIndex(11), // (0x8007c0002468080604021) SlotDebugData { name: "", ty: UInt<135> }, - src: StatePartIndex(2), // (0x8007c0002468080604021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, - }, - 593: SliceInt { - dest: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, - src: StatePartIndex(11), // (0x8007c0002468080604021) SlotDebugData { name: "", ty: UInt<135> }, - start: 1, - len: 134, - }, - 594: SliceInt { - dest: StatePartIndex(13), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, - src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, - start: 0, - len: 69, - }, - 595: Copy { - dest: StatePartIndex(14), // (0x1e0001234040302010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - src: StatePartIndex(13), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, - }, - 596: SliceInt { - dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, - start: 69, - len: 1, - }, - 597: Copy { - dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 598: SliceInt { - dest: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, - src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, - start: 70, - len: 64, - }, - 599: Copy { - dest: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - src: StatePartIndex(14), // (0x1e0001234040302010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - }, - 600: Copy { - dest: StatePartIndex(9), // (0x1) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, - src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 601: Copy { - dest: StatePartIndex(10), // (0x1000) SlotDebugData { name: ".pc", ty: UInt<64> }, - src: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, - }, - // at: reg_alloc.rs:48:11 - 602: AndBigWithSmallImmediate { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - lhs: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - rhs: 0x3, - }, - // at: unit.rs:107:1 - 603: BranchIfSmallNeImmediate { - target: 605, - lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x0, - }, - 604: Copy { - dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 605: BranchIfSmallNeImmediate { - target: 607, - lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x1, - }, - 606: Copy { - dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 607: BranchIfSmallNeImmediate { - target: 609, - lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x2, - }, - 608: Copy { - dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - src: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - }, - 609: AndBigWithSmallImmediate { - dest: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - lhs: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x3, - }, - 610: BranchIfSmallNeImmediate { - target: 612, - lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x0, - }, - 611: Copy { - dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 612: BranchIfSmallNeImmediate { - target: 614, - lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x1, - }, - 613: Copy { - dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 614: BranchIfSmallNeImmediate { - target: 616, - lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, - rhs: 0x2, - }, - 615: Copy { - dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:41:1 - 616: Copy { - dest: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, - src: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, - }, - 617: SliceInt { - dest: StatePartIndex(19), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, - src: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, - start: 2, - len: 67, - }, - 618: Copy { - dest: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - src: StatePartIndex(19), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, - }, - // at: reg_alloc.rs:48:11 - 619: AndBigWithSmallImmediate { - dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, - lhs: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - rhs: 0x3, - }, - // at: reg_alloc.rs:41:1 - 620: Copy { - dest: StatePartIndex(48), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, - src: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, - }, - 621: SliceInt { - dest: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - src: StatePartIndex(48), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, - start: 2, - len: 65, - }, - 622: SliceInt { - dest: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 0, - len: 61, - }, - 623: SliceInt { - dest: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - src: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, - start: 0, - len: 58, - }, - 624: SliceInt { - dest: StatePartIndex(52), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - start: 0, - len: 0, - }, - 625: SliceInt { - dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - start: 0, - len: 8, - }, - 626: SliceInt { - dest: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - start: 8, - len: 24, - }, - 627: SliceInt { - dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 628: SliceInt { - dest: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 629: SliceInt { - dest: StatePartIndex(60), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 630: Copy { - dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 631: Copy { - dest: StatePartIndex(55), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 632: Copy { - dest: StatePartIndex(56), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(60), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 633: SliceInt { - dest: StatePartIndex(61), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - start: 32, - len: 25, - }, - 634: SliceInt { - dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, - start: 57, - len: 1, - }, - 635: CastToSInt { - dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 636: Copy { - dest: StatePartIndex(41), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, - src: StatePartIndex(52), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - }, - 637: Copy { - dest: StatePartIndex(42), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - 638: Copy { - dest: StatePartIndex(43), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(54), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 639: Copy { - dest: StatePartIndex(44), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(55), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 640: Copy { - dest: StatePartIndex(45), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(56), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 641: Copy { - dest: StatePartIndex(46), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(61), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - }, - 642: Copy { - dest: StatePartIndex(47), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - 643: SliceInt { - dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - src: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, - start: 58, - len: 3, - }, - 644: Copy { - dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - }, - 645: Copy { - dest: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(41), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, - }, - 646: Copy { - dest: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - src: StatePartIndex(42), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, - }, - 647: Copy { - dest: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - src: StatePartIndex(43), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - }, - 648: Copy { - dest: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - src: StatePartIndex(44), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - }, - 649: Copy { - dest: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - src: StatePartIndex(45), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - }, - 650: Copy { - dest: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - src: StatePartIndex(46), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - }, - 651: Copy { - dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(47), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - }, - 652: Copy { - dest: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 653: SliceInt { - dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 61, - len: 1, - }, - 654: Copy { - dest: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(66), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 655: SliceInt { - dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 62, - len: 1, - }, - 656: Copy { - dest: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 657: SliceInt { - dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 63, - len: 1, - }, - 658: Copy { - dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 659: SliceInt { - dest: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 64, - len: 1, - }, - 660: Copy { - dest: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, - }, - 661: Copy { - dest: StatePartIndex(21), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - }, - 662: Copy { - dest: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, - src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - }, - 663: Copy { - dest: StatePartIndex(23), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, - src: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - }, - 664: Copy { - dest: StatePartIndex(24), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, - src: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - }, - 665: Copy { - dest: StatePartIndex(25), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, - src: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - }, - 666: Copy { - dest: StatePartIndex(26), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, - src: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - }, - 667: Copy { - dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - }, - 668: Copy { - dest: StatePartIndex(28), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 669: Copy { - dest: StatePartIndex(29), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, - src: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 670: Copy { - dest: StatePartIndex(30), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, - src: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 671: Copy { - dest: StatePartIndex(31), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, - src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 672: Copy { - dest: StatePartIndex(32), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, - src: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:48:11 - 673: AndBigWithSmallImmediate { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - lhs: StatePartIndex(28), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - rhs: 0x7, - }, - // at: reg_alloc.rs:41:1 - 674: SliceInt { - dest: StatePartIndex(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, - start: 61, - len: 4, - }, - 675: Copy { - dest: StatePartIndex(74), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, - src: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, - }, - 676: Copy { - dest: StatePartIndex(75), // (0x1) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, - src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - }, - 677: Copy { - dest: StatePartIndex(76), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, - src: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - }, - 678: Copy { - dest: StatePartIndex(77), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, - src: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - }, - 679: Copy { - dest: StatePartIndex(78), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, - src: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - }, - 680: Copy { - dest: StatePartIndex(79), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, - src: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - }, - 681: Copy { - dest: StatePartIndex(80), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - }, - 682: Copy { - dest: StatePartIndex(81), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - }, - 683: Copy { - dest: StatePartIndex(82), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, - src: StatePartIndex(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: reg_alloc.rs:48:11 - 684: AndBigWithSmallImmediate { - dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - lhs: StatePartIndex(81), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, - rhs: 0x7, - }, - // at: reg_alloc.rs:41:1 - 685: SliceInt { - dest: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, - start: 2, - len: 60, - }, - 686: Copy { - dest: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - src: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - }, - // at: reg_alloc.rs:48:11 - 687: AndBigWithSmallImmediate { - dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, - lhs: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 688: Copy { - dest: StatePartIndex(100), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, - }, - 689: SliceInt { - dest: StatePartIndex(101), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(100), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - start: 1, - len: 59, - }, - 690: SliceInt { - dest: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(101), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 59, - }, - 691: SliceInt { - dest: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 1, - }, - 692: SliceInt { - dest: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 1, - len: 8, - }, - 693: SliceInt { - dest: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 9, - len: 24, - }, - 694: SliceInt { - dest: StatePartIndex(109), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 695: SliceInt { - dest: StatePartIndex(110), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 696: SliceInt { - dest: StatePartIndex(111), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 697: Copy { - dest: StatePartIndex(105), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(109), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 698: Copy { - dest: StatePartIndex(106), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(110), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 699: Copy { - dest: StatePartIndex(107), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(111), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 700: SliceInt { - dest: StatePartIndex(112), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 33, - len: 25, - }, - 701: SliceInt { - dest: StatePartIndex(113), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 58, - len: 1, - }, - 702: CastToSInt { - dest: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(113), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 703: Copy { - dest: StatePartIndex(93), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - src: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 704: Copy { - dest: StatePartIndex(94), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - 705: Copy { - dest: StatePartIndex(95), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(105), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 706: Copy { - dest: StatePartIndex(96), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(106), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 707: Copy { - dest: StatePartIndex(97), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(107), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 708: Copy { - dest: StatePartIndex(98), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(112), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - }, - 709: Copy { - dest: StatePartIndex(99), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - 710: Copy { - dest: StatePartIndex(86), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, - src: StatePartIndex(93), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - }, - 711: Copy { - dest: StatePartIndex(87), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, - src: StatePartIndex(94), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, - }, - 712: Copy { - dest: StatePartIndex(88), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, - src: StatePartIndex(95), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - }, - 713: Copy { - dest: StatePartIndex(89), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, - src: StatePartIndex(96), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - }, - 714: Copy { - dest: StatePartIndex(90), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, - src: StatePartIndex(97), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - }, - 715: Copy { - dest: StatePartIndex(91), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, - src: StatePartIndex(98), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - }, - 716: Copy { - dest: StatePartIndex(92), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, - src: StatePartIndex(99), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - }, - 717: Copy { - dest: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - src: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - }, - // at: reg_alloc.rs:48:11 - 718: AndBigWithSmallImmediate { - dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, - lhs: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 719: Copy { - dest: StatePartIndex(123), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - src: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, - }, - 720: SliceInt { - dest: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - src: StatePartIndex(123), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, - start: 1, - len: 59, - }, - 721: SliceInt { - dest: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 0, - len: 1, - }, - 722: SliceInt { - dest: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 1, - len: 8, - }, - 723: SliceInt { - dest: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 9, - len: 24, - }, - 724: SliceInt { - dest: StatePartIndex(131), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 0, - len: 8, - }, - 725: SliceInt { - dest: StatePartIndex(132), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 8, - len: 8, - }, - 726: SliceInt { - dest: StatePartIndex(133), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, - start: 16, - len: 8, - }, - 727: Copy { - dest: StatePartIndex(127), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - src: StatePartIndex(131), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - 728: Copy { - dest: StatePartIndex(128), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - src: StatePartIndex(132), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - 729: Copy { - dest: StatePartIndex(129), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - src: StatePartIndex(133), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, - }, - 730: SliceInt { - dest: StatePartIndex(134), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 33, - len: 25, - }, - 731: SliceInt { - dest: StatePartIndex(135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, - start: 58, - len: 1, - }, - 732: CastToSInt { - dest: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - src: StatePartIndex(135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - dest_width: 1, - }, - 733: Copy { - dest: StatePartIndex(116), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, - src: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 734: Copy { - dest: StatePartIndex(117), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, - src: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - 735: Copy { - dest: StatePartIndex(118), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, - src: StatePartIndex(127), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, - }, - 736: Copy { - dest: StatePartIndex(119), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, - src: StatePartIndex(128), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, - }, - 737: Copy { - dest: StatePartIndex(120), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, - src: StatePartIndex(129), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, - }, - 738: Copy { - dest: StatePartIndex(121), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, - src: StatePartIndex(134), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, - }, - 739: Copy { - dest: StatePartIndex(122), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, - src: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, - }, - // at: reg_alloc.rs:48:11 - 740: AndBigWithSmallImmediate { - dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(2), // (0x8007c0002468080604021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:70:9 - 741: BranchIfSmallNeImmediate { - target: 743, - lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:71:13 - 742: Copy { - dest: StatePartIndex(271), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, - src: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, - }, - // at: reg_alloc.rs:161:13 - 743: BranchIfSmallNeImmediate { - target: 745, - lhs: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x0, - }, - // at: reg_alloc.rs:163:17 - 744: Copy { - dest: StatePartIndex(271), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:95:21 - 745: BranchIfZero { - target: 747, - value: StatePartIndex(271), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, - }, - // at: reg_alloc.rs:96:25 - 746: Copy { - dest: StatePartIndex(293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - // at: reg_alloc.rs:84:25 - 747: AndBigWithSmallImmediate { - dest: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 748: Copy { - dest: StatePartIndex(295), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - 749: SliceInt { - dest: StatePartIndex(296), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(295), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - start: 1, - len: 1, - }, - 750: SliceInt { - dest: StatePartIndex(297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(296), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - start: 0, - len: 1, - }, - 751: Copy { - dest: StatePartIndex(294), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - src: StatePartIndex(297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: reg_alloc.rs:76:9 - 752: Copy { - dest: StatePartIndex(273), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(293), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - // at: reg_alloc.rs:59:30 - 753: AndBigWithSmallImmediate { - dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(273), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 754: Copy { - dest: StatePartIndex(276), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(273), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - 755: SliceInt { - dest: StatePartIndex(277), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(276), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - start: 1, - len: 1, - }, - 756: SliceInt { - dest: StatePartIndex(278), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(277), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - start: 0, - len: 1, - }, - 757: Copy { - dest: StatePartIndex(275), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - src: StatePartIndex(278), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 758: CastBigToArrayIndex { - dest: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(275), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - }, - // at: reg_alloc.rs:123:13 - 759: BranchIfSmallNeImmediate { - target: 761, - lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:124:17 - 760: WriteIndexed { - dest: StatePartIndex(272) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool } */ [StatePartIndex(22) /* (0x0 0) SlotDebugData { name: "", ty: UInt<1> } */ , len=1, stride=1],, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:161:13 - 761: BranchIfSmallNeImmediate { - target: 763, - lhs: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x0, - }, - // at: reg_alloc.rs:163:17 - 762: Copy { - dest: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, - src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:95:21 - 763: BranchIfZero { - target: 765, - value: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, - }, - // at: reg_alloc.rs:96:25 - 764: Copy { - dest: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(322), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - // at: reg_alloc.rs:84:25 - 765: AndBigWithSmallImmediate { - dest: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 766: Copy { - dest: StatePartIndex(313), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - 767: SliceInt { - dest: StatePartIndex(314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(313), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - start: 1, - len: 1, - }, - 768: SliceInt { - dest: StatePartIndex(315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - start: 0, - len: 1, - }, - 769: Copy { - dest: StatePartIndex(312), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - src: StatePartIndex(315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - // at: reg_alloc.rs:76:9 - 770: Copy { - dest: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - src: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - // at: reg_alloc.rs:59:30 - 771: AndBigWithSmallImmediate { - dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:41:1 - 772: Copy { - dest: StatePartIndex(280), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, - }, - 773: SliceInt { - dest: StatePartIndex(281), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(280), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - start: 1, - len: 1, - }, - 774: SliceInt { - dest: StatePartIndex(282), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(281), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - start: 0, - len: 1, - }, - 775: Copy { - dest: StatePartIndex(279), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - src: StatePartIndex(282), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - }, - 776: CmpEq { - dest: StatePartIndex(684), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(279), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - rhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - }, - 777: CmpEq { - dest: StatePartIndex(683), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(275), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, - rhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, - }, - // at: reg_alloc.rs:166:13 - 778: BranchIfSmallNeImmediate { - target: 781, - lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:168:17 - 779: BranchIfZero { - target: 781, - value: StatePartIndex(683), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:169:21 - 780: Copy { - dest: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:166:13 - 781: BranchIfSmallNeImmediate { - target: 784, - lhs: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - rhs: 0x1, - }, - // at: reg_alloc.rs:168:17 - 782: BranchIfZero { - target: 784, - value: StatePartIndex(684), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:169:21 - 783: Copy { - dest: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: reg_alloc.rs:150:13 - 784: Copy { - dest: StatePartIndex(340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, - src: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + 982: WriteIndexed { + dest: StatePartIndex(3261) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(232) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:286:13 + 983: Copy { + dest: StatePartIndex(3232), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].ready", ty: Bool }, + src: StatePartIndex(3238), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + }, + // at: alu_branch.rs:23:5 + 984: Copy { + dest: StatePartIndex(3921), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:271:13 + 985: Copy { + dest: StatePartIndex(3917), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.ready", ty: Bool }, + src: StatePartIndex(3921), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.ready", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 986: NotU { + dest: StatePartIndex(4389), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3917), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.ready", ty: Bool }, + width: 1, + }, + // at: unit_free_regs_tracker.rs:29:9 + 987: Copy { + dest: StatePartIndex(4067), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: ready_valid.rs:33:9 - 785: BranchIfZero { - target: 787, - value: StatePartIndex(340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + 988: BranchIfZero { + target: 990, + value: StatePartIndex(4067), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, }, // at: ready_valid.rs:34:13 - 786: Copy { - dest: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, - src: StatePartIndex(339), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 989: Copy { + dest: StatePartIndex(4106), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4066), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, }, // at: ready_valid.rs:30:27 - 787: AndBigWithSmallImmediate { - dest: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, - lhs: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 990: AndBigWithSmallImmediate { + dest: StatePartIndex(282), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4106), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, rhs: 0x1, }, // at: unit_free_regs_tracker.rs:7:1 - 788: Copy { - dest: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - src: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + 991: Copy { + dest: StatePartIndex(4107), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4106), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, }, - 789: SliceInt { - dest: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + 992: SliceInt { + dest: StatePartIndex(4108), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4107), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, start: 1, len: 4, }, - 790: CastBigToArrayIndex { - dest: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + 993: CastBigToArrayIndex { + dest: StatePartIndex(283), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4108), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:31:9 + 994: BranchIfSmallNeImmediate { + target: 996, + lhs: StatePartIndex(282), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:32:13 + 995: WriteIndexed { + dest: StatePartIndex(4090) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(283) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:286:13 + 996: Copy { + dest: StatePartIndex(4061), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.free_in[0].ready", ty: Bool }, + src: StatePartIndex(4067), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 997: Const { + dest: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + 998: Copy { + dest: StatePartIndex(492), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:52:5 + 999: Copy { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + src: StatePartIndex(492), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + }, + // at: reg_alloc.rs:43:1 + 1000: Copy { + dest: StatePartIndex(957), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:65:40 + 1001: IsNonZeroDestIsSmall { + dest: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(488), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.clk", ty: Clock }, + }, + 1002: AndSmall { + dest: StatePartIndex(88), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(87), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1003: IsNonZeroDestIsSmall { + dest: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(483), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.clk", ty: Clock }, + }, + 1004: AndSmall { + dest: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1005: IsNonZeroDestIsSmall { + dest: StatePartIndex(79), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(478), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.clk", ty: Clock }, + }, + 1006: AndSmall { + dest: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(79), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(77), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1007: IsNonZeroDestIsSmall { + dest: StatePartIndex(74), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(473), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.clk", ty: Clock }, + }, + 1008: AndSmall { + dest: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(74), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(72), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1009: IsNonZeroDestIsSmall { + dest: StatePartIndex(69), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(468), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.clk", ty: Clock }, + }, + 1010: AndSmall { + dest: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(69), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1011: IsNonZeroDestIsSmall { + dest: StatePartIndex(64), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(463), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.clk", ty: Clock }, + }, + 1012: AndSmall { + dest: StatePartIndex(63), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(64), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 1013: IsNonZeroDestIsSmall { + dest: StatePartIndex(59), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(458), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.clk", ty: Clock }, + }, + 1014: AndSmall { + dest: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(59), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1015: IsNonZeroDestIsSmall { + dest: StatePartIndex(54), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(453), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.clk", ty: Clock }, + }, + 1016: AndSmall { + dest: StatePartIndex(53), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(54), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(52), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1017: IsNonZeroDestIsSmall { + dest: StatePartIndex(49), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(448), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.clk", ty: Clock }, + }, + 1018: AndSmall { + dest: StatePartIndex(48), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(49), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1019: IsNonZeroDestIsSmall { + dest: StatePartIndex(44), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(443), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.clk", ty: Clock }, + }, + 1020: AndSmall { + dest: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(44), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1021: IsNonZeroDestIsSmall { + dest: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(438), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.clk", ty: Clock }, + }, + 1022: AndSmall { + dest: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 1023: IsNonZeroDestIsSmall { + dest: StatePartIndex(34), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(433), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.clk", ty: Clock }, + }, + 1024: AndSmall { + dest: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 1025: Copy { + dest: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + }, + 1026: SliceInt { + dest: StatePartIndex(429), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1027: Copy { + dest: StatePartIndex(430), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, + src: StatePartIndex(429), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:50:11 + 1028: AndBigWithSmallImmediate { + dest: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Enum {Trap, ICacheFlush} }, + lhs: StatePartIndex(430), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, + rhs: 0x1, + }, + 1029: AndBigWithSmallImmediate { + dest: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 1030: Copy { + dest: StatePartIndex(221), // (0x200860000000000201c00051) SlotDebugData { name: "", ty: UInt<145> }, + src: StatePartIndex(4), // (0x200860000000000201c00051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + }, + 1031: SliceInt { + dest: StatePartIndex(222), // (0x100430000000000100e00028) SlotDebugData { name: "", ty: UInt<144> }, + src: StatePartIndex(221), // (0x200860000000000201c00051) SlotDebugData { name: "", ty: UInt<145> }, + start: 1, + len: 144, + }, + 1032: SliceInt { + dest: StatePartIndex(223), // (0x30000000000100e00028) SlotDebugData { name: "", ty: UInt<79> }, + src: StatePartIndex(222), // (0x100430000000000100e00028) SlotDebugData { name: "", ty: UInt<144> }, + start: 0, + len: 79, + }, + 1033: Copy { + dest: StatePartIndex(224), // (0x30000000000100e00028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(223), // (0x30000000000100e00028) SlotDebugData { name: "", ty: UInt<79> }, + }, + 1034: SliceInt { + dest: StatePartIndex(225), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(222), // (0x100430000000000100e00028) SlotDebugData { name: "", ty: UInt<144> }, + start: 79, + len: 1, + }, + 1035: Copy { + dest: StatePartIndex(226), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(225), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1036: SliceInt { + dest: StatePartIndex(227), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(222), // (0x100430000000000100e00028) SlotDebugData { name: "", ty: UInt<144> }, + start: 80, + len: 64, + }, + 1037: Copy { + dest: StatePartIndex(218), // (0x30000000000100e00028) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(224), // (0x30000000000100e00028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 1038: Copy { + dest: StatePartIndex(219), // (0x0) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, + src: StatePartIndex(226), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1039: Copy { + dest: StatePartIndex(220), // (0x1004) SlotDebugData { name: ".pc", ty: UInt<64> }, + src: StatePartIndex(227), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:50:11 + 1040: AndBigWithSmallImmediate { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(218), // (0x30000000000100e00028) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: unit.rs:127:1 + 1041: BranchIfSmallNeImmediate { + target: 1043, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1042: Copy { + dest: StatePartIndex(2180), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(957), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1043: BranchIfSmallNeImmediate { + target: 1045, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1044: Copy { + dest: StatePartIndex(2180), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(959), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1045: BranchIfSmallNeImmediate { + target: 1047, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 1046: Copy { + dest: StatePartIndex(2180), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(961), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1047: AndBigWithSmallImmediate { + dest: StatePartIndex(193), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(2180), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x3, + }, + 1048: BranchIfSmallNeImmediate { + target: 1051, + lhs: StatePartIndex(193), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1049: Copy { + dest: StatePartIndex(2181), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1050: Copy { + dest: StatePartIndex(2182), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1051: BranchIfSmallNeImmediate { + target: 1054, + lhs: StatePartIndex(193), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1052: Copy { + dest: StatePartIndex(2181), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1053: Copy { + dest: StatePartIndex(2182), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1054: BranchIfSmallNeImmediate { + target: 1057, + lhs: StatePartIndex(193), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 1055: Copy { + dest: StatePartIndex(2181), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1056: Copy { + dest: StatePartIndex(2182), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 1057: Copy { + dest: StatePartIndex(228), // (0x30000000000100e00028) SlotDebugData { name: "", ty: UInt<79> }, + src: StatePartIndex(218), // (0x30000000000100e00028) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 1058: SliceInt { + dest: StatePartIndex(229), // (0xc00000000004038000a) SlotDebugData { name: "", ty: UInt<77> }, + src: StatePartIndex(228), // (0x30000000000100e00028) SlotDebugData { name: "", ty: UInt<79> }, + start: 2, + len: 77, + }, + 1059: Copy { + dest: StatePartIndex(230), // (0xc00000000004038000a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(229), // (0xc00000000004038000a) SlotDebugData { name: "", ty: UInt<77> }, + }, + // at: reg_alloc.rs:50:11 + 1060: AndBigWithSmallImmediate { + dest: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(230), // (0xc00000000004038000a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 1061: Copy { + dest: StatePartIndex(267), // (0xc00000000004038000a) SlotDebugData { name: "", ty: UInt<77> }, + src: StatePartIndex(230), // (0xc00000000004038000a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 1062: SliceInt { + dest: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + src: StatePartIndex(267), // (0xc00000000004038000a) SlotDebugData { name: "", ty: UInt<77> }, + start: 2, + len: 75, + }, + 1063: SliceInt { + dest: StatePartIndex(269), // (0x100e0002) SlotDebugData { name: "", ty: UInt<71> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 0, + len: 71, + }, + 1064: SliceInt { + dest: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + src: StatePartIndex(269), // (0x100e0002) SlotDebugData { name: "", ty: UInt<71> }, + start: 0, + len: 68, + }, + 1065: SliceInt { + dest: StatePartIndex(271), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + start: 0, + len: 0, + }, + 1066: SliceInt { + dest: StatePartIndex(279), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + start: 0, + len: 18, + }, + 1067: SliceInt { + dest: StatePartIndex(280), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(279), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 1068: SliceInt { + dest: StatePartIndex(281), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(280), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 1069: SliceInt { + dest: StatePartIndex(282), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(281), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1070: Copy { + dest: StatePartIndex(278), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(282), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1071: SliceInt { + dest: StatePartIndex(284), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(280), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 1072: SliceInt { + dest: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(284), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1073: Copy { + dest: StatePartIndex(283), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1074: Copy { + dest: StatePartIndex(276), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(278), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1075: Copy { + dest: StatePartIndex(277), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(283), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1076: SliceInt { + dest: StatePartIndex(288), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(279), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 1077: SliceInt { + dest: StatePartIndex(289), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(288), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 1078: Copy { + dest: StatePartIndex(290), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(289), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1079: SliceInt { + dest: StatePartIndex(291), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(288), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1080: Copy { + dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(291), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1081: Copy { + dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(290), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1082: Copy { + dest: StatePartIndex(287), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(292), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1083: Copy { + dest: StatePartIndex(272), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(276), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 1084: Copy { + dest: StatePartIndex(273), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(277), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 1085: Copy { + dest: StatePartIndex(274), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(286), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1086: Copy { + dest: StatePartIndex(275), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(287), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1087: SliceInt { + dest: StatePartIndex(296), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + start: 18, + len: 24, + }, + 1088: SliceInt { + dest: StatePartIndex(297), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(296), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 1089: SliceInt { + dest: StatePartIndex(298), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(296), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 1090: SliceInt { + dest: StatePartIndex(299), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(296), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 1091: Copy { + dest: StatePartIndex(293), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(297), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1092: Copy { + dest: StatePartIndex(294), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(298), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1093: Copy { + dest: StatePartIndex(295), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(299), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1094: SliceInt { + dest: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + start: 42, + len: 25, + }, + 1095: SliceInt { + dest: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(270), // (0x100e0002) SlotDebugData { name: "", ty: UInt<68> }, + start: 67, + len: 1, + }, + 1096: CastToSInt { + dest: StatePartIndex(302), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1097: Copy { + dest: StatePartIndex(257), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(271), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 1098: Copy { + dest: StatePartIndex(258), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(272), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 1099: Copy { + dest: StatePartIndex(259), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(273), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 1100: Copy { + dest: StatePartIndex(260), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(274), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1101: Copy { + dest: StatePartIndex(261), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(275), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1102: Copy { + dest: StatePartIndex(262), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(293), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1103: Copy { + dest: StatePartIndex(263), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(294), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 1104: Copy { + dest: StatePartIndex(264), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(295), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 1105: Copy { + dest: StatePartIndex(265), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1106: Copy { + dest: StatePartIndex(266), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(302), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1107: SliceInt { + dest: StatePartIndex(303), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(269), // (0x100e0002) SlotDebugData { name: "", ty: UInt<71> }, + start: 68, + len: 3, + }, + 1108: Copy { + dest: StatePartIndex(304), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(303), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 1109: Copy { + dest: StatePartIndex(246), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(257), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 1110: Copy { + dest: StatePartIndex(247), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(258), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1111: Copy { + dest: StatePartIndex(248), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(259), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1112: Copy { + dest: StatePartIndex(249), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(260), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1113: Copy { + dest: StatePartIndex(250), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(261), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1114: Copy { + dest: StatePartIndex(251), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(262), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 1115: Copy { + dest: StatePartIndex(252), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(263), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 1116: Copy { + dest: StatePartIndex(253), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(264), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 1117: Copy { + dest: StatePartIndex(254), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(265), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1118: Copy { + dest: StatePartIndex(255), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(266), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 1119: Copy { + dest: StatePartIndex(256), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(304), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1120: SliceInt { + dest: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 71, + len: 1, + }, + 1121: Copy { + dest: StatePartIndex(306), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1122: SliceInt { + dest: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 72, + len: 1, + }, + 1123: Copy { + dest: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1124: SliceInt { + dest: StatePartIndex(309), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 73, + len: 1, + }, + 1125: Copy { + dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(309), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1126: SliceInt { + dest: StatePartIndex(311), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 74, + len: 1, + }, + 1127: Copy { + dest: StatePartIndex(312), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(311), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1128: Copy { + dest: StatePartIndex(231), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(246), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 1129: Copy { + dest: StatePartIndex(232), // (0x2) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(247), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1130: Copy { + dest: StatePartIndex(233), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(248), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1131: Copy { + dest: StatePartIndex(234), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(249), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1132: Copy { + dest: StatePartIndex(235), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(250), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1133: Copy { + dest: StatePartIndex(236), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(251), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 1134: Copy { + dest: StatePartIndex(237), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(252), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 1135: Copy { + dest: StatePartIndex(238), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(253), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 1136: Copy { + dest: StatePartIndex(239), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(254), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1137: Copy { + dest: StatePartIndex(240), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(255), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1138: Copy { + dest: StatePartIndex(241), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(256), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1139: Copy { + dest: StatePartIndex(242), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(306), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1140: Copy { + dest: StatePartIndex(243), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1141: Copy { + dest: StatePartIndex(244), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(310), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1142: Copy { + dest: StatePartIndex(245), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(312), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:50:11 + 1143: AndBigWithSmallImmediate { + dest: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(234), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1144: AndBigWithSmallImmediate { + dest: StatePartIndex(19), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(235), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:477:1 + 1145: BranchIfSmallNeImmediate { + target: 1150, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1146: Copy { + dest: StatePartIndex(2187), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(232), // (0x2) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1147: Copy { + dest: StatePartIndex(2188), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(233), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1148: Copy { + dest: StatePartIndex(2189), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(234), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1149: Copy { + dest: StatePartIndex(2190), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(235), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1150: BranchIfSmallNeImmediate { + target: 1155, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1151: Copy { + dest: StatePartIndex(2187), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(232), // (0x2) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1152: Copy { + dest: StatePartIndex(2188), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(233), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1153: Copy { + dest: StatePartIndex(2189), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(234), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1154: Copy { + dest: StatePartIndex(2190), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(235), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 1155: Copy { + dest: StatePartIndex(2393), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(236), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1156: Copy { + dest: StatePartIndex(2498), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(236), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1157: Copy { + dest: StatePartIndex(2396), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(237), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1158: Copy { + dest: StatePartIndex(2501), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(237), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1159: Copy { + dest: StatePartIndex(2399), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(238), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + }, + 1160: CastToUInt { + dest: StatePartIndex(2558), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(238), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1161: Copy { + dest: StatePartIndex(2557), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2558), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1162: Copy { + dest: StatePartIndex(2452), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(239), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1163: Copy { + dest: StatePartIndex(2453), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(240), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1164: Or { + dest: StatePartIndex(2455), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + lhs: StatePartIndex(2452), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2454), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1165: CastToUInt { + dest: StatePartIndex(2456), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2453), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1166: Shl { + dest: StatePartIndex(2457), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + lhs: StatePartIndex(2456), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 25, + }, + 1167: Or { + dest: StatePartIndex(2458), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + lhs: StatePartIndex(2455), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + rhs: StatePartIndex(2457), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + }, + 1168: CastToSInt { + dest: StatePartIndex(2459), // (0x0) SlotDebugData { name: "", ty: SInt<26> }, + src: StatePartIndex(2458), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + dest_width: 26, + }, + 1169: SliceInt { + dest: StatePartIndex(2460), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2459), // (0x0) SlotDebugData { name: "", ty: SInt<26> }, + start: 0, + len: 25, + }, + 1170: Shr { + dest: StatePartIndex(2461), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2459), // (0x0) SlotDebugData { name: "", ty: SInt<26> }, + rhs: 25, + }, + 1171: Copy { + dest: StatePartIndex(2554), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(239), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1172: Copy { + dest: StatePartIndex(2555), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2557), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1173: Copy { + dest: StatePartIndex(2556), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(240), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1174: Shl { + dest: StatePartIndex(2559), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2555), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1175: Or { + dest: StatePartIndex(2560), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2554), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2559), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1176: CastToUInt { + dest: StatePartIndex(2561), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2556), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1177: Shl { + dest: StatePartIndex(2562), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2561), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1178: Or { + dest: StatePartIndex(2563), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2560), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(2562), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1179: CastToSInt { + dest: StatePartIndex(2564), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(2563), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1180: CastToUInt { + dest: StatePartIndex(2565), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(2564), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1181: SliceInt { + dest: StatePartIndex(2566), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2565), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1182: SliceInt { + dest: StatePartIndex(2568), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2565), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1183: SliceInt { + dest: StatePartIndex(2569), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2568), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1184: Copy { + dest: StatePartIndex(2567), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2569), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1185: SliceInt { + dest: StatePartIndex(2570), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2565), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1186: CastToSInt { + dest: StatePartIndex(2571), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2570), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1187: Copy { + dest: StatePartIndex(2551), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2566), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1188: Copy { + dest: StatePartIndex(2552), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2567), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1189: Copy { + dest: StatePartIndex(2553), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2571), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1190: CastToUInt { + dest: StatePartIndex(2572), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2552), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1191: SliceInt { + dest: StatePartIndex(2573), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2564), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1192: Shr { + dest: StatePartIndex(2574), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2564), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 1193: AndBigWithSmallImmediate { + dest: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(241), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 1194: SliceInt { + dest: StatePartIndex(325), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(268), // (0x30000000000100e0002) SlotDebugData { name: "", ty: UInt<75> }, + start: 71, + len: 4, + }, + 1195: Copy { + dest: StatePartIndex(313), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(246), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 1196: Copy { + dest: StatePartIndex(314), // (0x2) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(247), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1197: Copy { + dest: StatePartIndex(315), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(248), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1198: Copy { + dest: StatePartIndex(316), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(249), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1199: Copy { + dest: StatePartIndex(317), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(250), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1200: Copy { + dest: StatePartIndex(318), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(251), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 1201: Copy { + dest: StatePartIndex(319), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(252), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 1202: Copy { + dest: StatePartIndex(320), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(253), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 1203: Copy { + dest: StatePartIndex(321), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(254), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1204: Copy { + dest: StatePartIndex(322), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(255), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1205: Copy { + dest: StatePartIndex(323), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(256), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1206: Copy { + dest: StatePartIndex(324), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(325), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:50:11 + 1207: AndBigWithSmallImmediate { + dest: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(316), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1208: AndBigWithSmallImmediate { + dest: StatePartIndex(22), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(317), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:477:1 + 1209: BranchIfSmallNeImmediate { + target: 1214, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1210: Copy { + dest: StatePartIndex(2187), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(314), // (0x2) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1211: Copy { + dest: StatePartIndex(2188), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(315), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1212: Copy { + dest: StatePartIndex(2189), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(316), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1213: Copy { + dest: StatePartIndex(2190), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(317), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1214: AndBigWithSmallImmediate { + dest: StatePartIndex(196), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2189), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1215: AndBigWithSmallImmediate { + dest: StatePartIndex(197), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2190), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1216: BranchIfSmallNeImmediate { + target: 1221, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1217: Copy { + dest: StatePartIndex(2183), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2187), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1218: Copy { + dest: StatePartIndex(2184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2188), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1219: Copy { + dest: StatePartIndex(2185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2189), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1220: Copy { + dest: StatePartIndex(2186), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2190), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 1221: Copy { + dest: StatePartIndex(2611), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(318), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1222: Copy { + dest: StatePartIndex(2614), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(319), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1223: CastToUInt { + dest: StatePartIndex(2665), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(320), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1224: Copy { + dest: StatePartIndex(2664), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2665), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1225: Copy { + dest: StatePartIndex(2661), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(321), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1226: Copy { + dest: StatePartIndex(2662), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2664), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1227: Copy { + dest: StatePartIndex(2663), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(322), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1228: Shl { + dest: StatePartIndex(2666), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2662), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1229: Or { + dest: StatePartIndex(2667), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2661), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2666), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1230: CastToUInt { + dest: StatePartIndex(2668), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2663), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1231: Shl { + dest: StatePartIndex(2669), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2668), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1232: Or { + dest: StatePartIndex(2670), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2667), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(2669), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1233: CastToSInt { + dest: StatePartIndex(2671), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(2670), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1234: CastToUInt { + dest: StatePartIndex(2672), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(2671), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1235: SliceInt { + dest: StatePartIndex(2673), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2672), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1236: SliceInt { + dest: StatePartIndex(2675), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2672), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1237: SliceInt { + dest: StatePartIndex(2676), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2675), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1238: Copy { + dest: StatePartIndex(2674), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2676), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1239: SliceInt { + dest: StatePartIndex(2677), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2672), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1240: CastToSInt { + dest: StatePartIndex(2678), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2677), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1241: Copy { + dest: StatePartIndex(2658), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2673), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1242: Copy { + dest: StatePartIndex(2659), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2674), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1243: Copy { + dest: StatePartIndex(2660), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2678), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1244: CastToUInt { + dest: StatePartIndex(2679), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2659), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1245: SliceInt { + dest: StatePartIndex(2680), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2671), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1246: Shr { + dest: StatePartIndex(2681), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2671), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 1247: AndBigWithSmallImmediate { + dest: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(323), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 1248: SliceInt { + dest: StatePartIndex(326), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(228), // (0x30000000000100e00028) SlotDebugData { name: "", ty: UInt<79> }, + start: 2, + len: 70, + }, + 1249: Copy { + dest: StatePartIndex(327), // (0x4038000a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(326), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + }, + // at: reg_alloc.rs:50:11 + 1250: AndBigWithSmallImmediate { + dest: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(327), // (0x4038000a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 1251: Copy { + dest: StatePartIndex(348), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(327), // (0x4038000a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 1252: SliceInt { + dest: StatePartIndex(349), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(348), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + start: 1, + len: 69, + }, + 1253: SliceInt { + dest: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(349), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 69, + }, + 1254: SliceInt { + dest: StatePartIndex(351), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 1, + }, + 1255: SliceInt { + dest: StatePartIndex(359), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 1, + len: 18, + }, + 1256: SliceInt { + dest: StatePartIndex(360), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(359), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 1257: SliceInt { + dest: StatePartIndex(361), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(360), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 1258: SliceInt { + dest: StatePartIndex(362), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(361), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1259: Copy { + dest: StatePartIndex(358), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(362), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1260: SliceInt { + dest: StatePartIndex(364), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(360), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 1261: SliceInt { + dest: StatePartIndex(365), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(364), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1262: Copy { + dest: StatePartIndex(363), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(365), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1263: Copy { + dest: StatePartIndex(356), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(358), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1264: Copy { + dest: StatePartIndex(357), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(363), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1265: SliceInt { + dest: StatePartIndex(368), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(359), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 1266: SliceInt { + dest: StatePartIndex(369), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(368), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 1267: Copy { + dest: StatePartIndex(370), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(369), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1268: SliceInt { + dest: StatePartIndex(371), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(368), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1269: Copy { + dest: StatePartIndex(372), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(371), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1270: Copy { + dest: StatePartIndex(366), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(370), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1271: Copy { + dest: StatePartIndex(367), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(372), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1272: Copy { + dest: StatePartIndex(352), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(356), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 1273: Copy { + dest: StatePartIndex(353), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(357), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 1274: Copy { + dest: StatePartIndex(354), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(366), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1275: Copy { + dest: StatePartIndex(355), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(367), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1276: SliceInt { + dest: StatePartIndex(376), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 19, + len: 24, + }, + 1277: SliceInt { + dest: StatePartIndex(377), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(376), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 1278: SliceInt { + dest: StatePartIndex(378), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(376), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 1279: SliceInt { + dest: StatePartIndex(379), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(376), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 1280: Copy { + dest: StatePartIndex(373), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(377), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1281: Copy { + dest: StatePartIndex(374), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(378), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1282: Copy { + dest: StatePartIndex(375), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(379), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1283: SliceInt { + dest: StatePartIndex(380), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 43, + len: 25, + }, + 1284: SliceInt { + dest: StatePartIndex(381), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(350), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 68, + len: 1, + }, + 1285: CastToSInt { + dest: StatePartIndex(382), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(381), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1286: Copy { + dest: StatePartIndex(338), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(351), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1287: Copy { + dest: StatePartIndex(339), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(352), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 1288: Copy { + dest: StatePartIndex(340), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(353), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 1289: Copy { + dest: StatePartIndex(341), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(354), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1290: Copy { + dest: StatePartIndex(342), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(355), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1291: Copy { + dest: StatePartIndex(343), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(373), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1292: Copy { + dest: StatePartIndex(344), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(374), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 1293: Copy { + dest: StatePartIndex(345), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(375), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 1294: Copy { + dest: StatePartIndex(346), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(380), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1295: Copy { + dest: StatePartIndex(347), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(382), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1296: Copy { + dest: StatePartIndex(328), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(338), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 1297: Copy { + dest: StatePartIndex(329), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(339), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1298: Copy { + dest: StatePartIndex(330), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(340), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1299: Copy { + dest: StatePartIndex(331), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(341), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1300: Copy { + dest: StatePartIndex(332), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(342), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1301: Copy { + dest: StatePartIndex(333), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(343), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 1302: Copy { + dest: StatePartIndex(334), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(344), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 1303: Copy { + dest: StatePartIndex(335), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(345), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 1304: Copy { + dest: StatePartIndex(336), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(346), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1305: Copy { + dest: StatePartIndex(337), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(347), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + // at: reg_alloc.rs:50:11 + 1306: AndBigWithSmallImmediate { + dest: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(331), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1307: AndBigWithSmallImmediate { + dest: StatePartIndex(26), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(332), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:504:1 + 1308: BranchIfSmallNeImmediate { + target: 1313, + lhs: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1309: Copy { + dest: StatePartIndex(2191), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(329), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1310: Copy { + dest: StatePartIndex(2192), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(330), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1311: Copy { + dest: StatePartIndex(2193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(331), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1312: Copy { + dest: StatePartIndex(2194), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(332), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1313: BranchIfSmallNeImmediate { + target: 1318, + lhs: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1314: Copy { + dest: StatePartIndex(2191), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(329), // (0x2) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1315: Copy { + dest: StatePartIndex(2192), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(330), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1316: Copy { + dest: StatePartIndex(2193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(331), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1317: Copy { + dest: StatePartIndex(2194), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(332), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1318: AndBigWithSmallImmediate { + dest: StatePartIndex(198), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1319: AndBigWithSmallImmediate { + dest: StatePartIndex(199), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2194), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1320: BranchIfSmallNeImmediate { + target: 1325, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1321: Copy { + dest: StatePartIndex(2183), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2191), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1322: Copy { + dest: StatePartIndex(2184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2192), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1323: Copy { + dest: StatePartIndex(2185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2193), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1324: Copy { + dest: StatePartIndex(2186), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2194), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 1325: Copy { + dest: StatePartIndex(2815), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(333), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 1326: CastToUInt { + dest: StatePartIndex(2777), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(335), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1327: Copy { + dest: StatePartIndex(2776), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2777), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1328: CastToUInt { + dest: StatePartIndex(2851), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(335), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1329: Copy { + dest: StatePartIndex(2850), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2851), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1330: Copy { + dest: StatePartIndex(2773), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(336), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1331: Copy { + dest: StatePartIndex(2774), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2776), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1332: Copy { + dest: StatePartIndex(2775), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(337), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1333: Shl { + dest: StatePartIndex(2778), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2774), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1334: Or { + dest: StatePartIndex(2779), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2773), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2778), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1335: CastToUInt { + dest: StatePartIndex(2780), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2775), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1336: Shl { + dest: StatePartIndex(2781), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2780), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1337: Or { + dest: StatePartIndex(2782), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2779), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(2781), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1338: CastToSInt { + dest: StatePartIndex(2783), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(2782), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1339: CastToUInt { + dest: StatePartIndex(2784), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(2783), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1340: SliceInt { + dest: StatePartIndex(2785), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2784), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1341: SliceInt { + dest: StatePartIndex(2787), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2784), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1342: SliceInt { + dest: StatePartIndex(2788), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2787), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1343: Copy { + dest: StatePartIndex(2786), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2788), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1344: SliceInt { + dest: StatePartIndex(2789), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2784), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1345: CastToSInt { + dest: StatePartIndex(2790), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2789), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1346: Copy { + dest: StatePartIndex(2770), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2785), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1347: Copy { + dest: StatePartIndex(2771), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2786), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1348: Copy { + dest: StatePartIndex(2772), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2790), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1349: CastToUInt { + dest: StatePartIndex(2791), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2771), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1350: Copy { + dest: StatePartIndex(2767), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1351: Copy { + dest: StatePartIndex(2768), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1352: Copy { + dest: StatePartIndex(2769), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2791), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1353: SliceInt { + dest: StatePartIndex(2792), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2783), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1354: Shr { + dest: StatePartIndex(2793), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2783), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 1355: Copy { + dest: StatePartIndex(2847), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(336), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1356: Copy { + dest: StatePartIndex(2848), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2850), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1357: Copy { + dest: StatePartIndex(2849), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(337), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1358: Shl { + dest: StatePartIndex(2852), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2848), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1359: Or { + dest: StatePartIndex(2853), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2847), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2852), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1360: CastToUInt { + dest: StatePartIndex(2854), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2849), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1361: Shl { + dest: StatePartIndex(2855), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2854), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1362: Or { + dest: StatePartIndex(2856), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2853), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(2855), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1363: CastToSInt { + dest: StatePartIndex(2857), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(2856), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1364: CastToUInt { + dest: StatePartIndex(2858), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(2857), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1365: SliceInt { + dest: StatePartIndex(2859), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2858), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1366: SliceInt { + dest: StatePartIndex(2861), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2858), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1367: SliceInt { + dest: StatePartIndex(2862), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2861), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1368: Copy { + dest: StatePartIndex(2860), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2862), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1369: SliceInt { + dest: StatePartIndex(2863), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2858), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1370: CastToSInt { + dest: StatePartIndex(2864), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2863), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1371: Copy { + dest: StatePartIndex(2844), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2859), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1372: Copy { + dest: StatePartIndex(2845), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2860), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1373: Copy { + dest: StatePartIndex(2846), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2864), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1374: CastToUInt { + dest: StatePartIndex(2865), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2845), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1375: SliceInt { + dest: StatePartIndex(2866), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2857), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1376: Shr { + dest: StatePartIndex(2867), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2857), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 1377: Copy { + dest: StatePartIndex(383), // (0x4038000a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(326), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + }, + // at: reg_alloc.rs:50:11 + 1378: AndBigWithSmallImmediate { + dest: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(383), // (0x4038000a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 1379: Copy { + dest: StatePartIndex(394), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(383), // (0x4038000a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 1380: SliceInt { + dest: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(394), // (0x4038000a) SlotDebugData { name: "", ty: UInt<70> }, + start: 1, + len: 69, + }, + 1381: SliceInt { + dest: StatePartIndex(396), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 1, + }, + 1382: SliceInt { + dest: StatePartIndex(404), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 1, + len: 18, + }, + 1383: SliceInt { + dest: StatePartIndex(405), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(404), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 1384: SliceInt { + dest: StatePartIndex(406), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(405), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 1385: SliceInt { + dest: StatePartIndex(407), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(406), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1386: Copy { + dest: StatePartIndex(403), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(407), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1387: SliceInt { + dest: StatePartIndex(409), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(405), // (0x2) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 1388: SliceInt { + dest: StatePartIndex(410), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(409), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1389: Copy { + dest: StatePartIndex(408), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(410), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1390: Copy { + dest: StatePartIndex(401), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(403), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1391: Copy { + dest: StatePartIndex(402), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(408), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1392: SliceInt { + dest: StatePartIndex(413), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(404), // (0x20002) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 1393: SliceInt { + dest: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(413), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 1394: Copy { + dest: StatePartIndex(415), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1395: SliceInt { + dest: StatePartIndex(416), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(413), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1396: Copy { + dest: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(416), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1397: Copy { + dest: StatePartIndex(411), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(415), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1398: Copy { + dest: StatePartIndex(412), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1399: Copy { + dest: StatePartIndex(397), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(401), // (0x2) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 1400: Copy { + dest: StatePartIndex(398), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(402), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 1401: Copy { + dest: StatePartIndex(399), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(411), // (0x0) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1402: Copy { + dest: StatePartIndex(400), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(412), // (0x1) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1403: SliceInt { + dest: StatePartIndex(421), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 19, + len: 24, + }, + 1404: SliceInt { + dest: StatePartIndex(422), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(421), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 1405: SliceInt { + dest: StatePartIndex(423), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(421), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 1406: SliceInt { + dest: StatePartIndex(424), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(421), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 1407: Copy { + dest: StatePartIndex(418), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(422), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1408: Copy { + dest: StatePartIndex(419), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(423), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1409: Copy { + dest: StatePartIndex(420), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(424), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1410: SliceInt { + dest: StatePartIndex(425), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 43, + len: 25, + }, + 1411: SliceInt { + dest: StatePartIndex(426), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(395), // (0x201c0005) SlotDebugData { name: "", ty: UInt<69> }, + start: 68, + len: 1, + }, + 1412: CastToSInt { + dest: StatePartIndex(427), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(426), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1413: Copy { + dest: StatePartIndex(384), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(396), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1414: Copy { + dest: StatePartIndex(385), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(397), // (0x2) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 1415: Copy { + dest: StatePartIndex(386), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(398), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 1416: Copy { + dest: StatePartIndex(387), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(399), // (0x0) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1417: Copy { + dest: StatePartIndex(388), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(400), // (0x1) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1418: Copy { + dest: StatePartIndex(389), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(418), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1419: Copy { + dest: StatePartIndex(390), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(419), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 1420: Copy { + dest: StatePartIndex(391), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(420), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 1421: Copy { + dest: StatePartIndex(392), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(425), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1422: Copy { + dest: StatePartIndex(393), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(427), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: reg_alloc.rs:50:11 + 1423: AndBigWithSmallImmediate { + dest: StatePartIndex(28), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(387), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1424: AndBigWithSmallImmediate { + dest: StatePartIndex(29), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(388), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:539:1 + 1425: BranchIfSmallNeImmediate { + target: 1430, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 1426: Copy { + dest: StatePartIndex(2195), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(385), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1427: Copy { + dest: StatePartIndex(2196), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(386), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1428: Copy { + dest: StatePartIndex(2197), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(387), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1429: Copy { + dest: StatePartIndex(2198), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(388), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1430: BranchIfSmallNeImmediate { + target: 1435, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 1431: Copy { + dest: StatePartIndex(2195), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(385), // (0x2) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1432: Copy { + dest: StatePartIndex(2196), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(386), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1433: Copy { + dest: StatePartIndex(2197), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(387), // (0x0) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1434: Copy { + dest: StatePartIndex(2198), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(388), // (0x1) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1435: AndBigWithSmallImmediate { + dest: StatePartIndex(200), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2197), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1436: AndBigWithSmallImmediate { + dest: StatePartIndex(201), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2198), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1437: BranchIfSmallNeImmediate { + target: 1442, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 1438: Copy { + dest: StatePartIndex(2183), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2195), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1439: Copy { + dest: StatePartIndex(2184), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2196), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1440: Copy { + dest: StatePartIndex(2185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2197), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1441: Copy { + dest: StatePartIndex(2186), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2198), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1442: AndBigWithSmallImmediate { + dest: StatePartIndex(194), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1443: AndBigWithSmallImmediate { + dest: StatePartIndex(195), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2186), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 1444: Copy { + dest: StatePartIndex(2981), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(389), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 1445: CastToUInt { + dest: StatePartIndex(2943), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(391), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1446: Copy { + dest: StatePartIndex(2942), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2943), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1447: CastToUInt { + dest: StatePartIndex(3010), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(391), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1448: Copy { + dest: StatePartIndex(3009), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(3010), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1449: Copy { + dest: StatePartIndex(2939), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(392), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1450: Copy { + dest: StatePartIndex(2940), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2942), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1451: Copy { + dest: StatePartIndex(2941), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(393), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 1452: Shl { + dest: StatePartIndex(2944), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2940), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1453: Or { + dest: StatePartIndex(2945), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2939), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(2944), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1454: CastToUInt { + dest: StatePartIndex(2946), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2941), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1455: Shl { + dest: StatePartIndex(2947), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2946), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1456: Or { + dest: StatePartIndex(2948), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(2945), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(2947), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1457: CastToSInt { + dest: StatePartIndex(2949), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(2948), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1458: CastToUInt { + dest: StatePartIndex(2950), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(2949), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1459: SliceInt { + dest: StatePartIndex(2951), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2950), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1460: SliceInt { + dest: StatePartIndex(2953), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2950), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1461: SliceInt { + dest: StatePartIndex(2954), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2953), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1462: Copy { + dest: StatePartIndex(2952), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(2954), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1463: SliceInt { + dest: StatePartIndex(2955), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2950), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1464: CastToSInt { + dest: StatePartIndex(2956), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2955), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1465: Copy { + dest: StatePartIndex(2936), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2951), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1466: Copy { + dest: StatePartIndex(2937), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(2952), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1467: Copy { + dest: StatePartIndex(2938), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2956), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1468: CastToUInt { + dest: StatePartIndex(2957), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2937), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1469: Copy { + dest: StatePartIndex(2933), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1470: Copy { + dest: StatePartIndex(2934), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1471: Copy { + dest: StatePartIndex(2935), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2957), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 1472: SliceInt { + dest: StatePartIndex(2958), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2949), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1473: Shr { + dest: StatePartIndex(2959), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(2949), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 1474: Copy { + dest: StatePartIndex(3006), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(392), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1475: Copy { + dest: StatePartIndex(3007), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(3009), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1476: Copy { + dest: StatePartIndex(3008), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(393), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 1477: Shl { + dest: StatePartIndex(3011), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(3007), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1478: Or { + dest: StatePartIndex(3012), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(3006), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(3011), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1479: CastToUInt { + dest: StatePartIndex(3013), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3008), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1480: Shl { + dest: StatePartIndex(3014), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(3013), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1481: Or { + dest: StatePartIndex(3015), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(3012), // (0x0) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(3014), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1482: CastToSInt { + dest: StatePartIndex(3016), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(3015), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1483: CastToUInt { + dest: StatePartIndex(3017), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(3016), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1484: SliceInt { + dest: StatePartIndex(3018), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3017), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1485: SliceInt { + dest: StatePartIndex(3020), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(3017), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1486: SliceInt { + dest: StatePartIndex(3021), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(3020), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1487: Copy { + dest: StatePartIndex(3019), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(3021), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1488: SliceInt { + dest: StatePartIndex(3022), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3017), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1489: CastToSInt { + dest: StatePartIndex(3023), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3022), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1490: Copy { + dest: StatePartIndex(3003), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3018), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1491: Copy { + dest: StatePartIndex(3004), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(3019), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1492: Copy { + dest: StatePartIndex(3005), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3023), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1493: CastToUInt { + dest: StatePartIndex(3024), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3004), // (0x0) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1494: SliceInt { + dest: StatePartIndex(3025), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3016), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1495: Shr { + dest: StatePartIndex(3026), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(3016), // (0x0) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 1496: AndBigWithSmallImmediate { + dest: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4), // (0x200860000000000201c00051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:159:9 + 1497: BranchIfSmallNeImmediate { + target: 1500, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:160:13 + 1498: Copy { + dest: StatePartIndex(495), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(2181), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + }, + 1499: Copy { + dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", ty: Bool }, + src: StatePartIndex(2182), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 1500: Copy { + dest: StatePartIndex(11), // (0x2001f000091a020181200021) SlotDebugData { name: "", ty: UInt<145> }, + src: StatePartIndex(2), // (0x2001f000091a020181200021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + }, + 1501: SliceInt { + dest: StatePartIndex(12), // (0x1000f800048d0100c0900010) SlotDebugData { name: "", ty: UInt<144> }, + src: StatePartIndex(11), // (0x2001f000091a020181200021) SlotDebugData { name: "", ty: UInt<145> }, + start: 1, + len: 144, + }, + 1502: SliceInt { + dest: StatePartIndex(13), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: UInt<79> }, + src: StatePartIndex(12), // (0x1000f800048d0100c0900010) SlotDebugData { name: "", ty: UInt<144> }, + start: 0, + len: 79, + }, + 1503: Copy { + dest: StatePartIndex(14), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(13), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: UInt<79> }, + }, + 1504: SliceInt { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(12), // (0x1000f800048d0100c0900010) SlotDebugData { name: "", ty: UInt<144> }, + start: 79, + len: 1, + }, + 1505: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1506: SliceInt { + dest: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(12), // (0x1000f800048d0100c0900010) SlotDebugData { name: "", ty: UInt<144> }, + start: 80, + len: 64, + }, + 1507: Copy { + dest: StatePartIndex(8), // (0x7800048d0100c0900010) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(14), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 1508: Copy { + dest: StatePartIndex(9), // (0x1) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1509: Copy { + dest: StatePartIndex(10), // (0x1000) SlotDebugData { name: ".pc", ty: UInt<64> }, + src: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:50:11 + 1510: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(8), // (0x7800048d0100c0900010) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: unit.rs:127:1 + 1511: BranchIfSmallNeImmediate { + target: 1513, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1512: Copy { + dest: StatePartIndex(956), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(957), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1513: BranchIfSmallNeImmediate { + target: 1515, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1514: Copy { + dest: StatePartIndex(956), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(959), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1515: BranchIfSmallNeImmediate { + target: 1517, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 1516: Copy { + dest: StatePartIndex(956), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(961), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 1517: AndBigWithSmallImmediate { + dest: StatePartIndex(116), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(956), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x3, + }, + 1518: BranchIfSmallNeImmediate { + target: 1521, + lhs: StatePartIndex(116), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1519: Copy { + dest: StatePartIndex(962), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1520: Copy { + dest: StatePartIndex(963), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1521: BranchIfSmallNeImmediate { + target: 1524, + lhs: StatePartIndex(116), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1522: Copy { + dest: StatePartIndex(962), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1523: Copy { + dest: StatePartIndex(963), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1524: BranchIfSmallNeImmediate { + target: 1527, + lhs: StatePartIndex(116), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 1525: Copy { + dest: StatePartIndex(962), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 1526: Copy { + dest: StatePartIndex(963), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 1527: Copy { + dest: StatePartIndex(18), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: UInt<79> }, + src: StatePartIndex(8), // (0x7800048d0100c0900010) SlotDebugData { name: ".mop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 1528: SliceInt { + dest: StatePartIndex(19), // (0x1e000123404030240004) SlotDebugData { name: "", ty: UInt<77> }, + src: StatePartIndex(18), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: UInt<79> }, + start: 2, + len: 77, + }, + 1529: Copy { + dest: StatePartIndex(20), // (0x1e000123404030240004) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(19), // (0x1e000123404030240004) SlotDebugData { name: "", ty: UInt<77> }, + }, + // at: reg_alloc.rs:50:11 + 1530: AndBigWithSmallImmediate { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(20), // (0x1e000123404030240004) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 1531: Copy { + dest: StatePartIndex(57), // (0x1e000123404030240004) SlotDebugData { name: "", ty: UInt<77> }, + src: StatePartIndex(20), // (0x1e000123404030240004) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 1532: SliceInt { + dest: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + src: StatePartIndex(57), // (0x1e000123404030240004) SlotDebugData { name: "", ty: UInt<77> }, + start: 2, + len: 75, + }, + 1533: SliceInt { + dest: StatePartIndex(59), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<71> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 0, + len: 71, + }, + 1534: SliceInt { + dest: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + src: StatePartIndex(59), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<71> }, + start: 0, + len: 68, + }, + 1535: SliceInt { + dest: StatePartIndex(61), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + start: 0, + len: 0, + }, + 1536: SliceInt { + dest: StatePartIndex(69), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + start: 0, + len: 18, + }, + 1537: SliceInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(69), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 1538: SliceInt { + dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 1539: SliceInt { + dest: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1540: Copy { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1541: SliceInt { + dest: StatePartIndex(74), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 1542: SliceInt { + dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(74), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1543: Copy { + dest: StatePartIndex(73), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(75), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1544: Copy { + dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1545: Copy { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(73), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1546: SliceInt { + dest: StatePartIndex(78), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 1547: SliceInt { + dest: StatePartIndex(79), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(78), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 1548: Copy { + dest: StatePartIndex(80), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(79), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1549: SliceInt { + dest: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(78), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1550: Copy { + dest: StatePartIndex(82), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1551: Copy { + dest: StatePartIndex(76), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(80), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1552: Copy { + dest: StatePartIndex(77), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(82), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1553: Copy { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 1554: Copy { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 1555: Copy { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(76), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1556: Copy { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(77), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1557: SliceInt { + dest: StatePartIndex(86), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + start: 18, + len: 24, + }, + 1558: SliceInt { + dest: StatePartIndex(87), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(86), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 1559: SliceInt { + dest: StatePartIndex(88), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(86), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 1560: SliceInt { + dest: StatePartIndex(89), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(86), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 1561: Copy { + dest: StatePartIndex(83), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(87), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1562: Copy { + dest: StatePartIndex(84), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(88), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1563: Copy { + dest: StatePartIndex(85), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(89), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1564: SliceInt { + dest: StatePartIndex(90), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + start: 42, + len: 25, + }, + 1565: SliceInt { + dest: StatePartIndex(91), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<68> }, + start: 67, + len: 1, + }, + 1566: CastToSInt { + dest: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(91), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1567: Copy { + dest: StatePartIndex(47), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(61), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 1568: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 1569: Copy { + dest: StatePartIndex(49), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 1570: Copy { + dest: StatePartIndex(50), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1571: Copy { + dest: StatePartIndex(51), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1572: Copy { + dest: StatePartIndex(52), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(83), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1573: Copy { + dest: StatePartIndex(53), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(84), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 1574: Copy { + dest: StatePartIndex(54), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(85), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 1575: Copy { + dest: StatePartIndex(55), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(90), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1576: Copy { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1577: SliceInt { + dest: StatePartIndex(93), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(59), // (0x48d0100c090001) SlotDebugData { name: "", ty: UInt<71> }, + start: 68, + len: 3, + }, + 1578: Copy { + dest: StatePartIndex(94), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(93), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 1579: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 1580: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1581: Copy { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(49), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1582: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(50), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1583: Copy { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(51), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1584: Copy { + dest: StatePartIndex(41), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(52), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 1585: Copy { + dest: StatePartIndex(42), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(53), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 1586: Copy { + dest: StatePartIndex(43), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(54), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 1587: Copy { + dest: StatePartIndex(44), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(55), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1588: Copy { + dest: StatePartIndex(45), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 1589: Copy { + dest: StatePartIndex(46), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(94), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1590: SliceInt { + dest: StatePartIndex(95), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 71, + len: 1, + }, + 1591: Copy { + dest: StatePartIndex(96), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(95), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1592: SliceInt { + dest: StatePartIndex(97), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 72, + len: 1, + }, + 1593: Copy { + dest: StatePartIndex(98), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(97), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1594: SliceInt { + dest: StatePartIndex(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 73, + len: 1, + }, + 1595: Copy { + dest: StatePartIndex(100), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1596: SliceInt { + dest: StatePartIndex(101), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 74, + len: 1, + }, + 1597: Copy { + dest: StatePartIndex(102), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(101), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1598: Copy { + dest: StatePartIndex(21), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 1599: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(37), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1600: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1601: Copy { + dest: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1602: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1603: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(41), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 1604: Copy { + dest: StatePartIndex(27), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(42), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 1605: Copy { + dest: StatePartIndex(28), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(43), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 1606: Copy { + dest: StatePartIndex(29), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(44), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1607: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(45), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1608: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(46), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1609: Copy { + dest: StatePartIndex(32), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(96), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1610: Copy { + dest: StatePartIndex(33), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(98), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1611: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(100), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 1612: Copy { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(102), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:50:11 + 1613: AndBigWithSmallImmediate { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1614: AndBigWithSmallImmediate { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:477:1 + 1615: BranchIfSmallNeImmediate { + target: 1620, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1616: Copy { + dest: StatePartIndex(968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1617: Copy { + dest: StatePartIndex(969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1618: Copy { + dest: StatePartIndex(970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1619: Copy { + dest: StatePartIndex(971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1620: BranchIfSmallNeImmediate { + target: 1625, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1621: Copy { + dest: StatePartIndex(968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1622: Copy { + dest: StatePartIndex(969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1623: Copy { + dest: StatePartIndex(970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1624: Copy { + dest: StatePartIndex(971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1625: BranchIfSmallNeImmediate { + target: 1630, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1626: Copy { + dest: StatePartIndex(1908), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1627: Copy { + dest: StatePartIndex(1909), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1628: Copy { + dest: StatePartIndex(1910), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1629: Copy { + dest: StatePartIndex(1911), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1630: BranchIfSmallNeImmediate { + target: 1635, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1631: Copy { + dest: StatePartIndex(1908), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1632: Copy { + dest: StatePartIndex(1909), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1633: Copy { + dest: StatePartIndex(1910), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1634: Copy { + dest: StatePartIndex(1911), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1635: BranchIfSmallNeImmediate { + target: 1640, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1636: Copy { + dest: StatePartIndex(1970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1637: Copy { + dest: StatePartIndex(1971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1638: Copy { + dest: StatePartIndex(1972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1639: Copy { + dest: StatePartIndex(1973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1640: BranchIfSmallNeImmediate { + target: 1645, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1641: Copy { + dest: StatePartIndex(1970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1642: Copy { + dest: StatePartIndex(1971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1643: Copy { + dest: StatePartIndex(1972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1644: Copy { + dest: StatePartIndex(1973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1645: BranchIfSmallNeImmediate { + target: 1650, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1646: Copy { + dest: StatePartIndex(2018), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1647: Copy { + dest: StatePartIndex(2019), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1648: Copy { + dest: StatePartIndex(2020), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1649: Copy { + dest: StatePartIndex(2021), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1650: BranchIfSmallNeImmediate { + target: 1655, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1651: Copy { + dest: StatePartIndex(2018), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1652: Copy { + dest: StatePartIndex(2019), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1653: Copy { + dest: StatePartIndex(2020), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1654: Copy { + dest: StatePartIndex(2021), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1655: BranchIfSmallNeImmediate { + target: 1660, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1656: Copy { + dest: StatePartIndex(2066), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1657: Copy { + dest: StatePartIndex(2067), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1658: Copy { + dest: StatePartIndex(2068), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1659: Copy { + dest: StatePartIndex(2069), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1660: BranchIfSmallNeImmediate { + target: 1665, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1661: Copy { + dest: StatePartIndex(2066), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1662: Copy { + dest: StatePartIndex(2067), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1663: Copy { + dest: StatePartIndex(2068), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1664: Copy { + dest: StatePartIndex(2069), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1665: BranchIfSmallNeImmediate { + target: 1670, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1666: Copy { + dest: StatePartIndex(2114), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1667: Copy { + dest: StatePartIndex(2115), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1668: Copy { + dest: StatePartIndex(2116), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1669: Copy { + dest: StatePartIndex(2117), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1670: BranchIfSmallNeImmediate { + target: 1675, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1671: Copy { + dest: StatePartIndex(2114), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1672: Copy { + dest: StatePartIndex(2115), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1673: Copy { + dest: StatePartIndex(2116), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1674: Copy { + dest: StatePartIndex(2117), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1675: BranchIfSmallNeImmediate { + target: 1680, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 1676: Copy { + dest: StatePartIndex(2162), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1677: Copy { + dest: StatePartIndex(2163), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1678: Copy { + dest: StatePartIndex(2164), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1679: Copy { + dest: StatePartIndex(2165), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1680: BranchIfSmallNeImmediate { + target: 1685, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 1681: Copy { + dest: StatePartIndex(2162), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1682: Copy { + dest: StatePartIndex(2163), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1683: Copy { + dest: StatePartIndex(2164), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(24), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1684: Copy { + dest: StatePartIndex(2165), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 1685: Copy { + dest: StatePartIndex(1174), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1686: Copy { + dest: StatePartIndex(1287), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1687: Copy { + dest: StatePartIndex(1184), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(27), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1688: Copy { + dest: StatePartIndex(1290), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(27), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1689: Copy { + dest: StatePartIndex(1187), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(28), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + }, + 1690: CastToUInt { + dest: StatePartIndex(1347), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(28), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1691: Copy { + dest: StatePartIndex(1346), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1347), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1692: Copy { + dest: StatePartIndex(1240), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(29), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1693: Copy { + dest: StatePartIndex(1241), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1694: Or { + dest: StatePartIndex(1244), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + lhs: StatePartIndex(1240), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1243), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1695: CastToUInt { + dest: StatePartIndex(1245), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1241), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1696: Shl { + dest: StatePartIndex(1246), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + lhs: StatePartIndex(1245), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 25, + }, + 1697: Or { + dest: StatePartIndex(1247), // (0x1234) SlotDebugData { name: "", ty: UInt<26> }, + lhs: StatePartIndex(1244), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + rhs: StatePartIndex(1246), // (0x0) SlotDebugData { name: "", ty: UInt<26> }, + }, + 1698: CastToSInt { + dest: StatePartIndex(1248), // (0x1234) SlotDebugData { name: "", ty: SInt<26> }, + src: StatePartIndex(1247), // (0x1234) SlotDebugData { name: "", ty: UInt<26> }, + dest_width: 26, + }, + 1699: SliceInt { + dest: StatePartIndex(1249), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1248), // (0x1234) SlotDebugData { name: "", ty: SInt<26> }, + start: 0, + len: 25, + }, + 1700: Shr { + dest: StatePartIndex(1250), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1248), // (0x1234) SlotDebugData { name: "", ty: SInt<26> }, + rhs: 25, + }, + 1701: Copy { + dest: StatePartIndex(1343), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(29), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1702: Copy { + dest: StatePartIndex(1344), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1346), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1703: Copy { + dest: StatePartIndex(1345), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1704: Shl { + dest: StatePartIndex(1348), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1344), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1705: Or { + dest: StatePartIndex(1349), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1343), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1348), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1706: CastToUInt { + dest: StatePartIndex(1350), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1345), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1707: Shl { + dest: StatePartIndex(1351), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1350), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1708: Or { + dest: StatePartIndex(1352), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1349), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1351), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1709: CastToSInt { + dest: StatePartIndex(1353), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1352), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1710: CastToUInt { + dest: StatePartIndex(1354), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1353), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1711: SliceInt { + dest: StatePartIndex(1355), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1354), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1712: SliceInt { + dest: StatePartIndex(1357), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1354), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1713: SliceInt { + dest: StatePartIndex(1358), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1357), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1714: Copy { + dest: StatePartIndex(1356), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1358), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1715: SliceInt { + dest: StatePartIndex(1359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1354), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1716: CastToSInt { + dest: StatePartIndex(1360), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1359), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1717: Copy { + dest: StatePartIndex(1340), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1355), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1718: Copy { + dest: StatePartIndex(1341), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1356), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1719: Copy { + dest: StatePartIndex(1342), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1360), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1720: CastToUInt { + dest: StatePartIndex(1361), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1341), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1721: SliceInt { + dest: StatePartIndex(1362), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1353), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1722: Shr { + dest: StatePartIndex(1363), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1353), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 1723: AndBigWithSmallImmediate { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(31), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 1724: SliceInt { + dest: StatePartIndex(115), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(58), // (0x7800048d0100c090001) SlotDebugData { name: "", ty: UInt<75> }, + start: 71, + len: 4, + }, + 1725: Copy { + dest: StatePartIndex(103), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 1726: Copy { + dest: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(37), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1727: Copy { + dest: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1728: Copy { + dest: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1729: Copy { + dest: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1730: Copy { + dest: StatePartIndex(108), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(41), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 1731: Copy { + dest: StatePartIndex(109), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(42), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 1732: Copy { + dest: StatePartIndex(110), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(43), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 1733: Copy { + dest: StatePartIndex(111), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(44), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 1734: Copy { + dest: StatePartIndex(112), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(45), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 1735: Copy { + dest: StatePartIndex(113), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(46), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 1736: Copy { + dest: StatePartIndex(114), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(115), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:50:11 + 1737: AndBigWithSmallImmediate { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1738: AndBigWithSmallImmediate { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:477:1 + 1739: BranchIfSmallNeImmediate { + target: 1744, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1740: Copy { + dest: StatePartIndex(968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1741: Copy { + dest: StatePartIndex(969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1742: Copy { + dest: StatePartIndex(970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1743: Copy { + dest: StatePartIndex(971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1744: AndBigWithSmallImmediate { + dest: StatePartIndex(119), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1745: AndBigWithSmallImmediate { + dest: StatePartIndex(120), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1746: BranchIfSmallNeImmediate { + target: 1751, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1747: Copy { + dest: StatePartIndex(964), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1748: Copy { + dest: StatePartIndex(965), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1749: Copy { + dest: StatePartIndex(966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1750: Copy { + dest: StatePartIndex(967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1751: BranchIfSmallNeImmediate { + target: 1756, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1752: Copy { + dest: StatePartIndex(1908), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1753: Copy { + dest: StatePartIndex(1909), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1754: Copy { + dest: StatePartIndex(1910), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1755: Copy { + dest: StatePartIndex(1911), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1756: AndBigWithSmallImmediate { + dest: StatePartIndex(142), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1910), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1757: AndBigWithSmallImmediate { + dest: StatePartIndex(143), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1911), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1758: BranchIfSmallNeImmediate { + target: 1763, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1759: Copy { + dest: StatePartIndex(1904), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1908), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1760: Copy { + dest: StatePartIndex(1905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1909), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1761: Copy { + dest: StatePartIndex(1906), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1910), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1762: Copy { + dest: StatePartIndex(1907), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1911), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1763: BranchIfSmallNeImmediate { + target: 1768, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1764: Copy { + dest: StatePartIndex(1970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1765: Copy { + dest: StatePartIndex(1971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1766: Copy { + dest: StatePartIndex(1972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1767: Copy { + dest: StatePartIndex(1973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1768: AndBigWithSmallImmediate { + dest: StatePartIndex(151), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1769: AndBigWithSmallImmediate { + dest: StatePartIndex(152), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1770: BranchIfSmallNeImmediate { + target: 1775, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1771: Copy { + dest: StatePartIndex(1966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1970), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1772: Copy { + dest: StatePartIndex(1967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1971), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1773: Copy { + dest: StatePartIndex(1968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1774: Copy { + dest: StatePartIndex(1969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1775: BranchIfSmallNeImmediate { + target: 1780, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1776: Copy { + dest: StatePartIndex(2018), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1777: Copy { + dest: StatePartIndex(2019), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1778: Copy { + dest: StatePartIndex(2020), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1779: Copy { + dest: StatePartIndex(2021), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1780: AndBigWithSmallImmediate { + dest: StatePartIndex(160), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2020), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1781: AndBigWithSmallImmediate { + dest: StatePartIndex(161), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2021), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1782: BranchIfSmallNeImmediate { + target: 1787, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1783: Copy { + dest: StatePartIndex(2014), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2018), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1784: Copy { + dest: StatePartIndex(2015), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2019), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1785: Copy { + dest: StatePartIndex(2016), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2020), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1786: Copy { + dest: StatePartIndex(2017), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2021), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1787: BranchIfSmallNeImmediate { + target: 1792, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1788: Copy { + dest: StatePartIndex(2066), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1789: Copy { + dest: StatePartIndex(2067), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1790: Copy { + dest: StatePartIndex(2068), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1791: Copy { + dest: StatePartIndex(2069), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1792: AndBigWithSmallImmediate { + dest: StatePartIndex(169), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2068), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1793: AndBigWithSmallImmediate { + dest: StatePartIndex(170), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2069), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1794: BranchIfSmallNeImmediate { + target: 1799, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1795: Copy { + dest: StatePartIndex(2062), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2066), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1796: Copy { + dest: StatePartIndex(2063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2067), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1797: Copy { + dest: StatePartIndex(2064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2068), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1798: Copy { + dest: StatePartIndex(2065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2069), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1799: BranchIfSmallNeImmediate { + target: 1804, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1800: Copy { + dest: StatePartIndex(2114), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1801: Copy { + dest: StatePartIndex(2115), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1802: Copy { + dest: StatePartIndex(2116), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1803: Copy { + dest: StatePartIndex(2117), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1804: AndBigWithSmallImmediate { + dest: StatePartIndex(178), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2116), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1805: AndBigWithSmallImmediate { + dest: StatePartIndex(179), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2117), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1806: BranchIfSmallNeImmediate { + target: 1811, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1807: Copy { + dest: StatePartIndex(2110), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2114), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1808: Copy { + dest: StatePartIndex(2111), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2115), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1809: Copy { + dest: StatePartIndex(2112), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2116), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1810: Copy { + dest: StatePartIndex(2113), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2117), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:477:1 + 1811: BranchIfSmallNeImmediate { + target: 1816, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 1812: Copy { + dest: StatePartIndex(2162), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: ".alu_common.common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1813: Copy { + dest: StatePartIndex(2163), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(105), // (0x0) SlotDebugData { name: ".alu_common.common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1814: Copy { + dest: StatePartIndex(2164), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: ".alu_common.common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1815: Copy { + dest: StatePartIndex(2165), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: ".alu_common.common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1816: AndBigWithSmallImmediate { + dest: StatePartIndex(187), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2164), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1817: AndBigWithSmallImmediate { + dest: StatePartIndex(188), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2165), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1818: BranchIfSmallNeImmediate { + target: 1823, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 1819: Copy { + dest: StatePartIndex(2158), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2162), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1820: Copy { + dest: StatePartIndex(2159), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2163), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1821: Copy { + dest: StatePartIndex(2160), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2164), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1822: Copy { + dest: StatePartIndex(2161), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2165), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 1823: Copy { + dest: StatePartIndex(1400), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(108), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + }, + 1824: Copy { + dest: StatePartIndex(1403), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(109), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + }, + 1825: CastToUInt { + dest: StatePartIndex(1454), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(110), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 1826: Copy { + dest: StatePartIndex(1453), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1454), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1827: Copy { + dest: StatePartIndex(1450), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(111), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 1828: Copy { + dest: StatePartIndex(1451), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1453), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1829: Copy { + dest: StatePartIndex(1452), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(112), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 1830: Shl { + dest: StatePartIndex(1455), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1451), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 1831: Or { + dest: StatePartIndex(1456), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1450), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1455), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 1832: CastToUInt { + dest: StatePartIndex(1457), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1452), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 1833: Shl { + dest: StatePartIndex(1458), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1457), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 1834: Or { + dest: StatePartIndex(1459), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1456), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1458), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 1835: CastToSInt { + dest: StatePartIndex(1460), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1459), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 1836: CastToUInt { + dest: StatePartIndex(1461), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1460), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 1837: SliceInt { + dest: StatePartIndex(1462), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1461), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 1838: SliceInt { + dest: StatePartIndex(1464), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1461), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 1839: SliceInt { + dest: StatePartIndex(1465), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1464), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1840: Copy { + dest: StatePartIndex(1463), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1465), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1841: SliceInt { + dest: StatePartIndex(1466), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1461), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 1842: CastToSInt { + dest: StatePartIndex(1467), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1466), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1843: Copy { + dest: StatePartIndex(1447), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1462), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1844: Copy { + dest: StatePartIndex(1448), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1463), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1845: Copy { + dest: StatePartIndex(1449), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1467), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1846: CastToUInt { + dest: StatePartIndex(1468), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1448), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 1847: SliceInt { + dest: StatePartIndex(1469), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1460), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 1848: Shr { + dest: StatePartIndex(1470), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1460), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 1849: AndBigWithSmallImmediate { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(113), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 1850: SliceInt { + dest: StatePartIndex(116), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(18), // (0x7800048d0100c0900010) SlotDebugData { name: "", ty: UInt<79> }, + start: 2, + len: 70, + }, + 1851: Copy { + dest: StatePartIndex(117), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(116), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + }, + // at: reg_alloc.rs:50:11 + 1852: AndBigWithSmallImmediate { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(117), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 1853: Copy { + dest: StatePartIndex(138), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(117), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 1854: SliceInt { + dest: StatePartIndex(139), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(138), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + start: 1, + len: 69, + }, + 1855: SliceInt { + dest: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(139), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 69, + }, + 1856: SliceInt { + dest: StatePartIndex(141), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 1, + }, + 1857: SliceInt { + dest: StatePartIndex(149), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 1, + len: 18, + }, + 1858: SliceInt { + dest: StatePartIndex(150), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(149), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 1859: SliceInt { + dest: StatePartIndex(151), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(150), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 1860: SliceInt { + dest: StatePartIndex(152), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(151), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1861: Copy { + dest: StatePartIndex(148), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(152), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1862: SliceInt { + dest: StatePartIndex(154), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(150), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 1863: SliceInt { + dest: StatePartIndex(155), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(154), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 1864: Copy { + dest: StatePartIndex(153), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(155), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1865: Copy { + dest: StatePartIndex(146), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(148), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1866: Copy { + dest: StatePartIndex(147), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(153), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 1867: SliceInt { + dest: StatePartIndex(158), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(149), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 1868: SliceInt { + dest: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(158), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 1869: Copy { + dest: StatePartIndex(160), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1870: SliceInt { + dest: StatePartIndex(161), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(158), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 1871: Copy { + dest: StatePartIndex(162), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(161), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1872: Copy { + dest: StatePartIndex(156), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(160), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1873: Copy { + dest: StatePartIndex(157), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(162), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1874: Copy { + dest: StatePartIndex(142), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(146), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 1875: Copy { + dest: StatePartIndex(143), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(147), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 1876: Copy { + dest: StatePartIndex(144), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(156), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1877: Copy { + dest: StatePartIndex(145), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(157), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1878: SliceInt { + dest: StatePartIndex(166), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 19, + len: 24, + }, + 1879: SliceInt { + dest: StatePartIndex(167), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(166), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 1880: SliceInt { + dest: StatePartIndex(168), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(166), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 1881: SliceInt { + dest: StatePartIndex(169), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(166), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 1882: Copy { + dest: StatePartIndex(163), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(167), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1883: Copy { + dest: StatePartIndex(164), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(168), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1884: Copy { + dest: StatePartIndex(165), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(169), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 1885: SliceInt { + dest: StatePartIndex(170), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 43, + len: 25, + }, + 1886: SliceInt { + dest: StatePartIndex(171), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(140), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 68, + len: 1, + }, + 1887: CastToSInt { + dest: StatePartIndex(172), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(171), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 1888: Copy { + dest: StatePartIndex(128), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(141), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 1889: Copy { + dest: StatePartIndex(129), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(142), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 1890: Copy { + dest: StatePartIndex(130), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(143), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 1891: Copy { + dest: StatePartIndex(131), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(144), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1892: Copy { + dest: StatePartIndex(132), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(145), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1893: Copy { + dest: StatePartIndex(133), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(163), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 1894: Copy { + dest: StatePartIndex(134), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(164), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 1895: Copy { + dest: StatePartIndex(135), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(165), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 1896: Copy { + dest: StatePartIndex(136), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(170), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 1897: Copy { + dest: StatePartIndex(137), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(172), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 1898: Copy { + dest: StatePartIndex(118), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(128), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 1899: Copy { + dest: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(129), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1900: Copy { + dest: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(130), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1901: Copy { + dest: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(131), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1902: Copy { + dest: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(132), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1903: Copy { + dest: StatePartIndex(123), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(133), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 1904: Copy { + dest: StatePartIndex(124), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(134), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 1905: Copy { + dest: StatePartIndex(125), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(135), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 1906: Copy { + dest: StatePartIndex(126), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(136), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 1907: Copy { + dest: StatePartIndex(127), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(137), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + // at: reg_alloc.rs:50:11 + 1908: AndBigWithSmallImmediate { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1909: AndBigWithSmallImmediate { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:504:1 + 1910: BranchIfSmallNeImmediate { + target: 1915, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1911: Copy { + dest: StatePartIndex(972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1912: Copy { + dest: StatePartIndex(973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1913: Copy { + dest: StatePartIndex(974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1914: Copy { + dest: StatePartIndex(975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1915: BranchIfSmallNeImmediate { + target: 1920, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1916: Copy { + dest: StatePartIndex(972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1917: Copy { + dest: StatePartIndex(973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1918: Copy { + dest: StatePartIndex(974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1919: Copy { + dest: StatePartIndex(975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1920: AndBigWithSmallImmediate { + dest: StatePartIndex(121), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1921: AndBigWithSmallImmediate { + dest: StatePartIndex(122), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1922: BranchIfSmallNeImmediate { + target: 1927, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1923: Copy { + dest: StatePartIndex(964), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(972), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1924: Copy { + dest: StatePartIndex(965), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(973), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1925: Copy { + dest: StatePartIndex(966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1926: Copy { + dest: StatePartIndex(967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 1927: BranchIfSmallNeImmediate { + target: 1932, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1928: Copy { + dest: StatePartIndex(1912), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1929: Copy { + dest: StatePartIndex(1913), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1930: Copy { + dest: StatePartIndex(1914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1931: Copy { + dest: StatePartIndex(1915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1932: BranchIfSmallNeImmediate { + target: 1937, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1933: Copy { + dest: StatePartIndex(1912), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1934: Copy { + dest: StatePartIndex(1913), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1935: Copy { + dest: StatePartIndex(1914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1936: Copy { + dest: StatePartIndex(1915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1937: AndBigWithSmallImmediate { + dest: StatePartIndex(144), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1938: AndBigWithSmallImmediate { + dest: StatePartIndex(145), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1939: BranchIfSmallNeImmediate { + target: 1944, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1940: Copy { + dest: StatePartIndex(1904), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1912), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1941: Copy { + dest: StatePartIndex(1905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1913), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1942: Copy { + dest: StatePartIndex(1906), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1914), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1943: Copy { + dest: StatePartIndex(1907), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1915), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 1944: BranchIfSmallNeImmediate { + target: 1949, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1945: Copy { + dest: StatePartIndex(1974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1946: Copy { + dest: StatePartIndex(1975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1947: Copy { + dest: StatePartIndex(1976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1948: Copy { + dest: StatePartIndex(1977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1949: BranchIfSmallNeImmediate { + target: 1954, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1950: Copy { + dest: StatePartIndex(1974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1951: Copy { + dest: StatePartIndex(1975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1952: Copy { + dest: StatePartIndex(1976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1953: Copy { + dest: StatePartIndex(1977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1954: AndBigWithSmallImmediate { + dest: StatePartIndex(153), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1955: AndBigWithSmallImmediate { + dest: StatePartIndex(154), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1956: BranchIfSmallNeImmediate { + target: 1961, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1957: Copy { + dest: StatePartIndex(1966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1974), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1958: Copy { + dest: StatePartIndex(1967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1975), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1959: Copy { + dest: StatePartIndex(1968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1960: Copy { + dest: StatePartIndex(1969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 1961: BranchIfSmallNeImmediate { + target: 1966, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1962: Copy { + dest: StatePartIndex(2022), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1963: Copy { + dest: StatePartIndex(2023), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1964: Copy { + dest: StatePartIndex(2024), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1965: Copy { + dest: StatePartIndex(2025), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1966: BranchIfSmallNeImmediate { + target: 1971, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1967: Copy { + dest: StatePartIndex(2022), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1968: Copy { + dest: StatePartIndex(2023), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1969: Copy { + dest: StatePartIndex(2024), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1970: Copy { + dest: StatePartIndex(2025), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1971: AndBigWithSmallImmediate { + dest: StatePartIndex(162), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2024), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1972: AndBigWithSmallImmediate { + dest: StatePartIndex(163), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2025), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1973: BranchIfSmallNeImmediate { + target: 1978, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1974: Copy { + dest: StatePartIndex(2014), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2022), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1975: Copy { + dest: StatePartIndex(2015), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2023), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1976: Copy { + dest: StatePartIndex(2016), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2024), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1977: Copy { + dest: StatePartIndex(2017), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2025), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 1978: BranchIfSmallNeImmediate { + target: 1983, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1979: Copy { + dest: StatePartIndex(2070), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1980: Copy { + dest: StatePartIndex(2071), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1981: Copy { + dest: StatePartIndex(2072), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1982: Copy { + dest: StatePartIndex(2073), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1983: BranchIfSmallNeImmediate { + target: 1988, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 1984: Copy { + dest: StatePartIndex(2070), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1985: Copy { + dest: StatePartIndex(2071), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1986: Copy { + dest: StatePartIndex(2072), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1987: Copy { + dest: StatePartIndex(2073), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1988: AndBigWithSmallImmediate { + dest: StatePartIndex(171), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2072), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 1989: AndBigWithSmallImmediate { + dest: StatePartIndex(172), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2073), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 1990: BranchIfSmallNeImmediate { + target: 1995, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 1991: Copy { + dest: StatePartIndex(2062), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2070), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 1992: Copy { + dest: StatePartIndex(2063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2071), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 1993: Copy { + dest: StatePartIndex(2064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2072), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1994: Copy { + dest: StatePartIndex(2065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2073), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 1995: BranchIfSmallNeImmediate { + target: 2000, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 1996: Copy { + dest: StatePartIndex(2118), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 1997: Copy { + dest: StatePartIndex(2119), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 1998: Copy { + dest: StatePartIndex(2120), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 1999: Copy { + dest: StatePartIndex(2121), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2000: BranchIfSmallNeImmediate { + target: 2005, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 2001: Copy { + dest: StatePartIndex(2118), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2002: Copy { + dest: StatePartIndex(2119), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2003: Copy { + dest: StatePartIndex(2120), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2004: Copy { + dest: StatePartIndex(2121), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2005: AndBigWithSmallImmediate { + dest: StatePartIndex(180), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2120), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2006: AndBigWithSmallImmediate { + dest: StatePartIndex(181), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2121), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2007: BranchIfSmallNeImmediate { + target: 2012, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 2008: Copy { + dest: StatePartIndex(2110), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2118), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2009: Copy { + dest: StatePartIndex(2111), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2119), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2010: Copy { + dest: StatePartIndex(2112), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2120), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2011: Copy { + dest: StatePartIndex(2113), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2121), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: instruction.rs:504:1 + 2012: BranchIfSmallNeImmediate { + target: 2017, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 2013: Copy { + dest: StatePartIndex(2166), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2014: Copy { + dest: StatePartIndex(2167), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2015: Copy { + dest: StatePartIndex(2168), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2016: Copy { + dest: StatePartIndex(2169), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2017: BranchIfSmallNeImmediate { + target: 2022, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 2018: Copy { + dest: StatePartIndex(2166), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(119), // (0x1) SlotDebugData { name: ".common.dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2019: Copy { + dest: StatePartIndex(2167), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: ".common.dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2020: Copy { + dest: StatePartIndex(2168), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(121), // (0x1) SlotDebugData { name: ".common.dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2021: Copy { + dest: StatePartIndex(2169), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: ".common.dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2022: AndBigWithSmallImmediate { + dest: StatePartIndex(189), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2168), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2023: AndBigWithSmallImmediate { + dest: StatePartIndex(190), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2169), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2024: BranchIfSmallNeImmediate { + target: 2029, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 2025: Copy { + dest: StatePartIndex(2158), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2166), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2026: Copy { + dest: StatePartIndex(2159), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2167), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2027: Copy { + dest: StatePartIndex(2160), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2168), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2028: Copy { + dest: StatePartIndex(2161), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2169), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + // at: reg_alloc.rs:43:1 + 2029: Copy { + dest: StatePartIndex(1606), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(123), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 2030: CastToUInt { + dest: StatePartIndex(1568), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(125), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 2031: Copy { + dest: StatePartIndex(1567), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1568), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2032: CastToUInt { + dest: StatePartIndex(1642), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(125), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 2033: Copy { + dest: StatePartIndex(1641), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1642), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2034: Copy { + dest: StatePartIndex(1564), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(126), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 2035: Copy { + dest: StatePartIndex(1565), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1567), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2036: Copy { + dest: StatePartIndex(1566), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(127), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 2037: Shl { + dest: StatePartIndex(1569), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1565), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 2038: Or { + dest: StatePartIndex(1570), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1564), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1569), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 2039: CastToUInt { + dest: StatePartIndex(1571), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1566), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2040: Shl { + dest: StatePartIndex(1572), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1571), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 2041: Or { + dest: StatePartIndex(1573), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1570), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1572), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 2042: CastToSInt { + dest: StatePartIndex(1574), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1573), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 2043: CastToUInt { + dest: StatePartIndex(1575), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1574), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 2044: SliceInt { + dest: StatePartIndex(1576), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1575), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 2045: SliceInt { + dest: StatePartIndex(1578), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1575), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 2046: SliceInt { + dest: StatePartIndex(1579), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1578), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2047: Copy { + dest: StatePartIndex(1577), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1579), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2048: SliceInt { + dest: StatePartIndex(1580), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1575), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 2049: CastToSInt { + dest: StatePartIndex(1581), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1580), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 2050: Copy { + dest: StatePartIndex(1561), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1576), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2051: Copy { + dest: StatePartIndex(1562), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1577), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2052: Copy { + dest: StatePartIndex(1563), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1581), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2053: CastToUInt { + dest: StatePartIndex(1582), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1562), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 2054: Copy { + dest: StatePartIndex(1557), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2055: Copy { + dest: StatePartIndex(1558), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2056: Copy { + dest: StatePartIndex(1559), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1582), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2057: SliceInt { + dest: StatePartIndex(1583), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1574), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 2058: Shr { + dest: StatePartIndex(1584), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1574), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 2059: Copy { + dest: StatePartIndex(1638), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(126), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 2060: Copy { + dest: StatePartIndex(1639), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1641), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2061: Copy { + dest: StatePartIndex(1640), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(127), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 2062: Shl { + dest: StatePartIndex(1643), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1639), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 2063: Or { + dest: StatePartIndex(1644), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1638), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1643), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 2064: CastToUInt { + dest: StatePartIndex(1645), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1640), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2065: Shl { + dest: StatePartIndex(1646), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1645), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 2066: Or { + dest: StatePartIndex(1647), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1644), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1646), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 2067: CastToSInt { + dest: StatePartIndex(1648), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1647), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 2068: CastToUInt { + dest: StatePartIndex(1649), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1648), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 2069: SliceInt { + dest: StatePartIndex(1650), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1649), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 2070: SliceInt { + dest: StatePartIndex(1652), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1649), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 2071: SliceInt { + dest: StatePartIndex(1653), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1652), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2072: Copy { + dest: StatePartIndex(1651), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1653), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2073: SliceInt { + dest: StatePartIndex(1654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1649), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 2074: CastToSInt { + dest: StatePartIndex(1655), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 2075: Copy { + dest: StatePartIndex(1635), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1650), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2076: Copy { + dest: StatePartIndex(1636), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1651), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2077: Copy { + dest: StatePartIndex(1637), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1655), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2078: CastToUInt { + dest: StatePartIndex(1656), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1636), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 2079: SliceInt { + dest: StatePartIndex(1657), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1648), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 2080: Shr { + dest: StatePartIndex(1658), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1648), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 2081: Copy { + dest: StatePartIndex(173), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(116), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + }, + // at: reg_alloc.rs:50:11 + 2082: AndBigWithSmallImmediate { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(173), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2083: Copy { + dest: StatePartIndex(184), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + src: StatePartIndex(173), // (0x123404030240004) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 2084: SliceInt { + dest: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(184), // (0x123404030240004) SlotDebugData { name: "", ty: UInt<70> }, + start: 1, + len: 69, + }, + 2085: SliceInt { + dest: StatePartIndex(186), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 0, + len: 1, + }, + 2086: SliceInt { + dest: StatePartIndex(194), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 1, + len: 18, + }, + 2087: SliceInt { + dest: StatePartIndex(195), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + src: StatePartIndex(194), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 16, + }, + 2088: SliceInt { + dest: StatePartIndex(196), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(195), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 0, + len: 8, + }, + 2089: SliceInt { + dest: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(196), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2090: Copy { + dest: StatePartIndex(193), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2091: SliceInt { + dest: StatePartIndex(199), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(195), // (0x1) SlotDebugData { name: "", ty: UInt<16> }, + start: 8, + len: 8, + }, + 2092: SliceInt { + dest: StatePartIndex(200), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(199), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2093: Copy { + dest: StatePartIndex(198), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(200), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2094: Copy { + dest: StatePartIndex(191), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + src: StatePartIndex(193), // (0x1) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 2095: Copy { + dest: StatePartIndex(192), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + src: StatePartIndex(198), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + 2096: SliceInt { + dest: StatePartIndex(203), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(194), // (0x10001) SlotDebugData { name: "", ty: UInt<18> }, + start: 16, + len: 2, + }, + 2097: SliceInt { + dest: StatePartIndex(204), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(203), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 1, + }, + 2098: Copy { + dest: StatePartIndex(205), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(204), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2099: SliceInt { + dest: StatePartIndex(206), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(203), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 2100: Copy { + dest: StatePartIndex(207), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(206), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2101: Copy { + dest: StatePartIndex(201), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(205), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2102: Copy { + dest: StatePartIndex(202), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(207), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2103: Copy { + dest: StatePartIndex(187), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(191), // (0x1) SlotDebugData { name: "[0].value", ty: UInt<8> }, + }, + 2104: Copy { + dest: StatePartIndex(188), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(192), // (0x0) SlotDebugData { name: "[1].value", ty: UInt<8> }, + }, + 2105: Copy { + dest: StatePartIndex(189), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(201), // (0x1) SlotDebugData { name: "[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2106: Copy { + dest: StatePartIndex(190), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(202), // (0x0) SlotDebugData { name: "[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2107: SliceInt { + dest: StatePartIndex(211), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 19, + len: 24, + }, + 2108: SliceInt { + dest: StatePartIndex(212), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(211), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 2109: SliceInt { + dest: StatePartIndex(213), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(211), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 2110: SliceInt { + dest: StatePartIndex(214), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(211), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 2111: Copy { + dest: StatePartIndex(208), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(212), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2112: Copy { + dest: StatePartIndex(209), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(213), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2113: Copy { + dest: StatePartIndex(210), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(214), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2114: SliceInt { + dest: StatePartIndex(215), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 43, + len: 25, + }, + 2115: SliceInt { + dest: StatePartIndex(216), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(185), // (0x91a02018120002) SlotDebugData { name: "", ty: UInt<69> }, + start: 68, + len: 1, + }, + 2116: CastToSInt { + dest: StatePartIndex(217), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(216), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 2117: Copy { + dest: StatePartIndex(174), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(186), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2118: Copy { + dest: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(187), // (0x1) SlotDebugData { name: ".normal_regs[0].value", ty: UInt<8> }, + }, + 2119: Copy { + dest: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(188), // (0x0) SlotDebugData { name: ".normal_regs[1].value", ty: UInt<8> }, + }, + 2120: Copy { + dest: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(189), // (0x1) SlotDebugData { name: ".flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2121: Copy { + dest: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(190), // (0x0) SlotDebugData { name: ".flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2122: Copy { + dest: StatePartIndex(179), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(208), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2123: Copy { + dest: StatePartIndex(180), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(209), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 2124: Copy { + dest: StatePartIndex(181), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(210), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 2125: Copy { + dest: StatePartIndex(182), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(215), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2126: Copy { + dest: StatePartIndex(183), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(217), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: reg_alloc.rs:50:11 + 2127: AndBigWithSmallImmediate { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2128: AndBigWithSmallImmediate { + dest: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:539:1 + 2129: BranchIfSmallNeImmediate { + target: 2134, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2130: Copy { + dest: StatePartIndex(976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2131: Copy { + dest: StatePartIndex(977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2132: Copy { + dest: StatePartIndex(978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2133: Copy { + dest: StatePartIndex(979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2134: BranchIfSmallNeImmediate { + target: 2139, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2135: Copy { + dest: StatePartIndex(976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2136: Copy { + dest: StatePartIndex(977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2137: Copy { + dest: StatePartIndex(978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2138: Copy { + dest: StatePartIndex(979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2139: AndBigWithSmallImmediate { + dest: StatePartIndex(123), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2140: AndBigWithSmallImmediate { + dest: StatePartIndex(124), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2141: BranchIfSmallNeImmediate { + target: 2146, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2142: Copy { + dest: StatePartIndex(964), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(976), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2143: Copy { + dest: StatePartIndex(965), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(977), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2144: Copy { + dest: StatePartIndex(966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2145: Copy { + dest: StatePartIndex(967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2146: AndBigWithSmallImmediate { + dest: StatePartIndex(117), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2147: AndBigWithSmallImmediate { + dest: StatePartIndex(118), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:539:1 + 2148: BranchIfSmallNeImmediate { + target: 2153, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2149: Copy { + dest: StatePartIndex(1916), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2150: Copy { + dest: StatePartIndex(1917), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2151: Copy { + dest: StatePartIndex(1918), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2152: Copy { + dest: StatePartIndex(1919), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2153: BranchIfSmallNeImmediate { + target: 2158, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2154: Copy { + dest: StatePartIndex(1916), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2155: Copy { + dest: StatePartIndex(1917), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2156: Copy { + dest: StatePartIndex(1918), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2157: Copy { + dest: StatePartIndex(1919), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2158: AndBigWithSmallImmediate { + dest: StatePartIndex(146), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1918), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2159: AndBigWithSmallImmediate { + dest: StatePartIndex(147), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1919), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2160: BranchIfSmallNeImmediate { + target: 2165, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2161: Copy { + dest: StatePartIndex(1904), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1916), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2162: Copy { + dest: StatePartIndex(1905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1917), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2163: Copy { + dest: StatePartIndex(1906), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1918), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2164: Copy { + dest: StatePartIndex(1907), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1919), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2165: AndBigWithSmallImmediate { + dest: StatePartIndex(140), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1906), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2166: BranchIfSmallNeImmediate { + target: 2168, + lhs: StatePartIndex(140), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2167: Copy { + dest: StatePartIndex(1920), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2168: AndBigWithSmallImmediate { + dest: StatePartIndex(141), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1907), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2169: BranchIfSmallNeImmediate { + target: 2171, + lhs: StatePartIndex(141), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2170: Copy { + dest: StatePartIndex(1923), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:539:1 + 2171: BranchIfSmallNeImmediate { + target: 2176, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2172: Copy { + dest: StatePartIndex(1978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2173: Copy { + dest: StatePartIndex(1979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2174: Copy { + dest: StatePartIndex(1980), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2175: Copy { + dest: StatePartIndex(1981), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2176: BranchIfSmallNeImmediate { + target: 2181, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2177: Copy { + dest: StatePartIndex(1978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2178: Copy { + dest: StatePartIndex(1979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2179: Copy { + dest: StatePartIndex(1980), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2180: Copy { + dest: StatePartIndex(1981), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2181: AndBigWithSmallImmediate { + dest: StatePartIndex(155), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1980), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2182: AndBigWithSmallImmediate { + dest: StatePartIndex(156), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1981), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2183: BranchIfSmallNeImmediate { + target: 2188, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2184: Copy { + dest: StatePartIndex(1966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(1978), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2185: Copy { + dest: StatePartIndex(1967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(1979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2186: Copy { + dest: StatePartIndex(1968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1980), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2187: Copy { + dest: StatePartIndex(1969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(1981), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2188: AndBigWithSmallImmediate { + dest: StatePartIndex(149), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1968), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2189: BranchIfSmallNeImmediate { + target: 2191, + lhs: StatePartIndex(149), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2190: Copy { + dest: StatePartIndex(1982), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2191: AndBigWithSmallImmediate { + dest: StatePartIndex(150), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1969), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2192: BranchIfSmallNeImmediate { + target: 2194, + lhs: StatePartIndex(150), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2193: Copy { + dest: StatePartIndex(1983), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:539:1 + 2194: BranchIfSmallNeImmediate { + target: 2199, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2195: Copy { + dest: StatePartIndex(2026), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2196: Copy { + dest: StatePartIndex(2027), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2197: Copy { + dest: StatePartIndex(2028), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2198: Copy { + dest: StatePartIndex(2029), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2199: BranchIfSmallNeImmediate { + target: 2204, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2200: Copy { + dest: StatePartIndex(2026), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2201: Copy { + dest: StatePartIndex(2027), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2202: Copy { + dest: StatePartIndex(2028), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2203: Copy { + dest: StatePartIndex(2029), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2204: AndBigWithSmallImmediate { + dest: StatePartIndex(164), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2028), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2205: AndBigWithSmallImmediate { + dest: StatePartIndex(165), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2029), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2206: BranchIfSmallNeImmediate { + target: 2211, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2207: Copy { + dest: StatePartIndex(2014), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2026), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2208: Copy { + dest: StatePartIndex(2015), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2027), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2209: Copy { + dest: StatePartIndex(2016), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2028), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2210: Copy { + dest: StatePartIndex(2017), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2029), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2211: AndBigWithSmallImmediate { + dest: StatePartIndex(158), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2016), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2212: BranchIfSmallNeImmediate { + target: 2214, + lhs: StatePartIndex(158), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2213: Copy { + dest: StatePartIndex(2030), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2214: AndBigWithSmallImmediate { + dest: StatePartIndex(159), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2017), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2215: BranchIfSmallNeImmediate { + target: 2217, + lhs: StatePartIndex(159), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2216: Copy { + dest: StatePartIndex(2031), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:539:1 + 2217: BranchIfSmallNeImmediate { + target: 2222, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2218: Copy { + dest: StatePartIndex(2074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2219: Copy { + dest: StatePartIndex(2075), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2220: Copy { + dest: StatePartIndex(2076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2221: Copy { + dest: StatePartIndex(2077), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2222: BranchIfSmallNeImmediate { + target: 2227, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2223: Copy { + dest: StatePartIndex(2074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2224: Copy { + dest: StatePartIndex(2075), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2225: Copy { + dest: StatePartIndex(2076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2226: Copy { + dest: StatePartIndex(2077), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2227: AndBigWithSmallImmediate { + dest: StatePartIndex(173), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2228: AndBigWithSmallImmediate { + dest: StatePartIndex(174), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2077), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2229: BranchIfSmallNeImmediate { + target: 2234, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2230: Copy { + dest: StatePartIndex(2062), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2231: Copy { + dest: StatePartIndex(2063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2075), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2232: Copy { + dest: StatePartIndex(2064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2233: Copy { + dest: StatePartIndex(2065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2077), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2234: AndBigWithSmallImmediate { + dest: StatePartIndex(167), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2064), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2235: BranchIfSmallNeImmediate { + target: 2237, + lhs: StatePartIndex(167), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2236: Copy { + dest: StatePartIndex(2078), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2237: AndBigWithSmallImmediate { + dest: StatePartIndex(168), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2065), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2238: BranchIfSmallNeImmediate { + target: 2240, + lhs: StatePartIndex(168), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2239: Copy { + dest: StatePartIndex(2079), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:539:1 + 2240: BranchIfSmallNeImmediate { + target: 2245, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2241: Copy { + dest: StatePartIndex(2122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2242: Copy { + dest: StatePartIndex(2123), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2243: Copy { + dest: StatePartIndex(2124), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2244: Copy { + dest: StatePartIndex(2125), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2245: BranchIfSmallNeImmediate { + target: 2250, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2246: Copy { + dest: StatePartIndex(2122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2247: Copy { + dest: StatePartIndex(2123), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2248: Copy { + dest: StatePartIndex(2124), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2249: Copy { + dest: StatePartIndex(2125), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2250: AndBigWithSmallImmediate { + dest: StatePartIndex(182), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2124), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2251: AndBigWithSmallImmediate { + dest: StatePartIndex(183), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2125), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2252: BranchIfSmallNeImmediate { + target: 2257, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2253: Copy { + dest: StatePartIndex(2110), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2122), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2254: Copy { + dest: StatePartIndex(2111), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2123), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2255: Copy { + dest: StatePartIndex(2112), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2124), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2256: Copy { + dest: StatePartIndex(2113), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2125), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2257: AndBigWithSmallImmediate { + dest: StatePartIndex(176), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2112), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2258: BranchIfSmallNeImmediate { + target: 2260, + lhs: StatePartIndex(176), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2259: Copy { + dest: StatePartIndex(2126), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2260: AndBigWithSmallImmediate { + dest: StatePartIndex(177), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2113), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2261: BranchIfSmallNeImmediate { + target: 2263, + lhs: StatePartIndex(177), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2262: Copy { + dest: StatePartIndex(2127), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:539:1 + 2263: BranchIfSmallNeImmediate { + target: 2268, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2264: Copy { + dest: StatePartIndex(2170), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2265: Copy { + dest: StatePartIndex(2171), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2266: Copy { + dest: StatePartIndex(2172), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2267: Copy { + dest: StatePartIndex(2173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2268: BranchIfSmallNeImmediate { + target: 2273, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 2269: Copy { + dest: StatePartIndex(2170), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(175), // (0x1) SlotDebugData { name: ".dest.normal_regs[0].value", ty: UInt<8> }, + }, + 2270: Copy { + dest: StatePartIndex(2171), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".dest.normal_regs[1].value", ty: UInt<8> }, + }, + 2271: Copy { + dest: StatePartIndex(2172), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(177), // (0x1) SlotDebugData { name: ".dest.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2272: Copy { + dest: StatePartIndex(2173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(178), // (0x0) SlotDebugData { name: ".dest.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2273: AndBigWithSmallImmediate { + dest: StatePartIndex(191), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2172), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + 2274: AndBigWithSmallImmediate { + dest: StatePartIndex(192), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2275: BranchIfSmallNeImmediate { + target: 2280, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 2276: Copy { + dest: StatePartIndex(2158), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + src: StatePartIndex(2170), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + }, + 2277: Copy { + dest: StatePartIndex(2159), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + src: StatePartIndex(2171), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + }, + 2278: Copy { + dest: StatePartIndex(2160), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2172), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2279: Copy { + dest: StatePartIndex(2161), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + src: StatePartIndex(2173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + }, + 2280: AndBigWithSmallImmediate { + dest: StatePartIndex(185), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2160), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[0]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2281: BranchIfSmallNeImmediate { + target: 2283, + lhs: StatePartIndex(185), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2282: Copy { + dest: StatePartIndex(2174), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1921), // (0xfe) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2283: AndBigWithSmallImmediate { + dest: StatePartIndex(186), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2161), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.flag_regs[1]", ty: Enum {HdlNone, HdlSome(Bundle {})} }, + rhs: 0x1, + }, + // at: instruction.rs:723:17 + 2284: BranchIfSmallNeImmediate { + target: 2286, + lhs: StatePartIndex(186), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: instruction.rs:725:21 + 2285: Copy { + dest: StatePartIndex(2175), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + src: StatePartIndex(1924), // (0xff) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2286: Copy { + dest: StatePartIndex(1772), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + src: StatePartIndex(179), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 2287: CastToUInt { + dest: StatePartIndex(1734), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(181), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 2288: Copy { + dest: StatePartIndex(1733), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1734), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2289: CastToUInt { + dest: StatePartIndex(1801), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(181), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + dest_width: 8, + }, + 2290: Copy { + dest: StatePartIndex(1800), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1801), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2291: Copy { + dest: StatePartIndex(1730), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(182), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2292: Copy { + dest: StatePartIndex(1731), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1733), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2293: Copy { + dest: StatePartIndex(1732), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(183), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2294: Shl { + dest: StatePartIndex(1735), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1731), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 2295: Or { + dest: StatePartIndex(1736), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1730), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1735), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 2296: CastToUInt { + dest: StatePartIndex(1737), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1732), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2297: Shl { + dest: StatePartIndex(1738), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1737), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 2298: Or { + dest: StatePartIndex(1739), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1736), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1738), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 2299: CastToSInt { + dest: StatePartIndex(1740), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1739), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 2300: CastToUInt { + dest: StatePartIndex(1741), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1740), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 2301: SliceInt { + dest: StatePartIndex(1742), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1741), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 2302: SliceInt { + dest: StatePartIndex(1744), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1741), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 2303: SliceInt { + dest: StatePartIndex(1745), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1744), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2304: Copy { + dest: StatePartIndex(1743), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1745), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2305: SliceInt { + dest: StatePartIndex(1746), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1741), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 2306: CastToSInt { + dest: StatePartIndex(1747), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1746), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 2307: Copy { + dest: StatePartIndex(1727), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1742), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2308: Copy { + dest: StatePartIndex(1728), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1743), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2309: Copy { + dest: StatePartIndex(1729), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1747), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2310: CastToUInt { + dest: StatePartIndex(1748), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1728), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 2311: Copy { + dest: StatePartIndex(1724), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2312: Copy { + dest: StatePartIndex(1725), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2313: Copy { + dest: StatePartIndex(1726), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1748), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2314: SliceInt { + dest: StatePartIndex(1749), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1740), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 2315: Shr { + dest: StatePartIndex(1750), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1740), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + 2316: Copy { + dest: StatePartIndex(1797), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(182), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2317: Copy { + dest: StatePartIndex(1798), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1800), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2318: Copy { + dest: StatePartIndex(1799), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(183), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2319: Shl { + dest: StatePartIndex(1802), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1798), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + rhs: 25, + }, + 2320: Or { + dest: StatePartIndex(1803), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1797), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + rhs: StatePartIndex(1802), // (0x8000000) SlotDebugData { name: "", ty: UInt<33> }, + }, + 2321: CastToUInt { + dest: StatePartIndex(1804), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1799), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2322: Shl { + dest: StatePartIndex(1805), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1804), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 33, + }, + 2323: Or { + dest: StatePartIndex(1806), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + lhs: StatePartIndex(1803), // (0x8001234) SlotDebugData { name: "", ty: UInt<33> }, + rhs: StatePartIndex(1805), // (0x0) SlotDebugData { name: "", ty: UInt<34> }, + }, + 2324: CastToSInt { + dest: StatePartIndex(1807), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + src: StatePartIndex(1806), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + dest_width: 34, + }, + 2325: CastToUInt { + dest: StatePartIndex(1808), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + src: StatePartIndex(1807), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + dest_width: 34, + }, + 2326: SliceInt { + dest: StatePartIndex(1809), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1808), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 0, + len: 25, + }, + 2327: SliceInt { + dest: StatePartIndex(1811), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1808), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 25, + len: 8, + }, + 2328: SliceInt { + dest: StatePartIndex(1812), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1811), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + start: 0, + len: 8, + }, + 2329: Copy { + dest: StatePartIndex(1810), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(1812), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 2330: SliceInt { + dest: StatePartIndex(1813), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1808), // (0x8001234) SlotDebugData { name: "", ty: UInt<34> }, + start: 33, + len: 1, + }, + 2331: CastToSInt { + dest: StatePartIndex(1814), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1813), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 2332: Copy { + dest: StatePartIndex(1794), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1809), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2333: Copy { + dest: StatePartIndex(1795), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + src: StatePartIndex(1810), // (0x4) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 2334: Copy { + dest: StatePartIndex(1796), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1814), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2335: CastToUInt { + dest: StatePartIndex(1815), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1795), // (0x4) SlotDebugData { name: ".reversed_src[0]", ty: UInt<8> }, + dest_width: 6, + }, + 2336: SliceInt { + dest: StatePartIndex(1816), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1807), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + start: 0, + len: 25, + }, + 2337: Shr { + dest: StatePartIndex(1817), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + lhs: StatePartIndex(1807), // (0x8001234) SlotDebugData { name: "", ty: SInt<34> }, + rhs: 33, + }, + // at: reg_alloc.rs:50:11 + 2338: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x2001f000091a020181200021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:159:9 + 2339: BranchIfSmallNeImmediate { + target: 2342, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:160:13 + 2340: Copy { + dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(962), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + }, + 2341: Copy { + dest: StatePartIndex(494), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", ty: Bool }, + src: StatePartIndex(963), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[1]", ty: Bool }, + }, + // at: reg_alloc.rs:298:13 + 2342: BranchIfSmallNeImmediate { + target: 2344, + lhs: StatePartIndex(251), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:300:17 + 2343: Copy { + dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:303:13 + 2344: BranchIfZero { + target: 2346, + value: StatePartIndex(3585), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:305:17 + 2345: Copy { + dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:298:13 + 2346: BranchIfSmallNeImmediate { + target: 2348, + lhs: StatePartIndex(302), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:300:17 + 2347: Copy { + dest: StatePartIndex(494), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:303:13 + 2348: BranchIfZero { + target: 2350, + value: StatePartIndex(4389), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:305:17 + 2349: Copy { + dest: StatePartIndex(494), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:223:21 + 2350: BranchIfZero { + target: 2352, + value: StatePartIndex(493), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + }, + // at: reg_alloc.rs:224:25 + 2351: Copy { + dest: StatePartIndex(1851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1862), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:209:25 + 2352: AndBigWithSmallImmediate { + dest: StatePartIndex(136), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2353: Copy { + dest: StatePartIndex(1852), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2354: SliceInt { + dest: StatePartIndex(1853), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1852), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:235:21 + 2355: Copy { + dest: StatePartIndex(1875), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:223:21 + 2356: BranchIfZero { + target: 2358, + value: StatePartIndex(494), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][1]", ty: Bool }, + }, + // at: reg_alloc.rs:224:25 + 2357: Copy { + dest: StatePartIndex(1863), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1874), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:209:25 + 2358: AndBigWithSmallImmediate { + dest: StatePartIndex(137), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1863), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2359: Copy { + dest: StatePartIndex(1864), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1863), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2360: SliceInt { + dest: StatePartIndex(1865), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1864), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:237:21 + 2361: BranchIfSmallNeImmediate { + target: 2363, + lhs: StatePartIndex(136), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:238:25 + 2362: Copy { + dest: StatePartIndex(1875), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1863), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_0_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:231:25 + 2363: AndBigWithSmallImmediate { + dest: StatePartIndex(138), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1875), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2364: Copy { + dest: StatePartIndex(1876), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1875), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2365: SliceInt { + dest: StatePartIndex(1877), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1876), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:201:9 + 2366: Copy { + dest: StatePartIndex(497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[0]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(1875), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_0_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:73:9 + 2367: AndBigWithSmallImmediate { + dest: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[0]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2368: Copy { + dest: StatePartIndex(499), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[0]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2369: SliceInt { + dest: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(499), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + 2370: CastBigToArrayIndex { + dest: StatePartIndex(216), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:251:13 + 2371: BranchIfSmallNeImmediate { + target: 2373, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:252:17 + 2372: WriteIndexed { + dest: StatePartIndex(495) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool } */ [StatePartIndex(216) /* (0x0 0) SlotDebugData { name: "", ty: UInt<2> } */ , len=2, stride=1],, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:298:13 + 2373: BranchIfSmallNeImmediate { + target: 2375, + lhs: StatePartIndex(251), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:300:17 + 2374: Copy { + dest: StatePartIndex(495), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:303:13 + 2375: BranchIfZero { + target: 2377, + value: StatePartIndex(3585), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:305:17 + 2376: Copy { + dest: StatePartIndex(495), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:298:13 + 2377: BranchIfSmallNeImmediate { + target: 2379, + lhs: StatePartIndex(302), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:300:17 + 2378: Copy { + dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:303:13 + 2379: BranchIfZero { + target: 2381, + value: StatePartIndex(4389), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:305:17 + 2380: Copy { + dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", ty: Bool }, + src: StatePartIndex(786), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:223:21 + 2381: BranchIfZero { + target: 2383, + value: StatePartIndex(495), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + }, + // at: reg_alloc.rs:224:25 + 2382: Copy { + dest: StatePartIndex(3060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3069), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:209:25 + 2383: AndBigWithSmallImmediate { + dest: StatePartIndex(213), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2384: Copy { + dest: StatePartIndex(3061), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2385: SliceInt { + dest: StatePartIndex(3062), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3061), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:235:21 + 2386: Copy { + dest: StatePartIndex(3080), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3060), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:223:21 + 2387: BranchIfZero { + target: 2389, + value: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][1]", ty: Bool }, + }, + // at: reg_alloc.rs:224:25 + 2388: Copy { + dest: StatePartIndex(3070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3079), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:209:25 + 2389: AndBigWithSmallImmediate { + dest: StatePartIndex(214), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2390: Copy { + dest: StatePartIndex(3071), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2391: SliceInt { + dest: StatePartIndex(3072), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3071), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:237:21 + 2392: BranchIfSmallNeImmediate { + target: 2394, + lhs: StatePartIndex(213), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:238:25 + 2393: Copy { + dest: StatePartIndex(3080), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_leaf_1_1", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:231:25 + 2394: AndBigWithSmallImmediate { + dest: StatePartIndex(215), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3080), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2395: Copy { + dest: StatePartIndex(3081), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3080), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2396: SliceInt { + dest: StatePartIndex(3082), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(3081), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + // at: reg_alloc.rs:201:9 + 2397: Copy { + dest: StatePartIndex(498), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[1]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + src: StatePartIndex(3080), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_index_node_1_0", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + // at: reg_alloc.rs:73:9 + 2398: AndBigWithSmallImmediate { + dest: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(498), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[1]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2399: Copy { + dest: StatePartIndex(501), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(498), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_indexes[1]", ty: Enum {HdlNone, HdlSome(UInt<2>)} }, + }, + 2400: SliceInt { + dest: StatePartIndex(502), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(501), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + start: 1, + len: 2, + }, + 2401: CmpEq { + dest: StatePartIndex(3761), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(502), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:308:13 + 2402: BranchIfSmallNeImmediate { + target: 2406, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2403: BranchIfZero { + target: 2406, + value: StatePartIndex(3761), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:325:21 + 2404: BranchIfSmallNeImmediate { + target: 2406, + lhs: StatePartIndex(251), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:331:25 + 2405: Copy { + dest: StatePartIndex(762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(3760), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2406: CmpEq { + dest: StatePartIndex(4550), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(502), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:308:13 + 2407: BranchIfSmallNeImmediate { + target: 2411, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2408: BranchIfZero { + target: 2411, + value: StatePartIndex(4550), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:325:21 + 2409: BranchIfSmallNeImmediate { + target: 2411, + lhs: StatePartIndex(302), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:331:25 + 2410: Copy { + dest: StatePartIndex(762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(4549), // (0x5) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:77:32 + 2411: AndBigWithSmallImmediate { + dest: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:159:9 + 2412: BranchIfSmallNeImmediate { + target: 2421, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2413: BranchIfSmallNeImmediate { + target: 2421, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2414: BranchIfSmallNeImmediate { + target: 2421, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2415: BranchIfSmallNeImmediate { + target: 2421, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:181:29 + 2416: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2393), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2417: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2393), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2418: Copy { + dest: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2396), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2419: Copy { + dest: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2396), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2420: Copy { + dest: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(2399), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2421: CmpLe { + dest: StatePartIndex(2000), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + }, + 2422: CmpLt { + dest: StatePartIndex(2001), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2423: And { + dest: StatePartIndex(2002), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2000), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2001), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2424: BranchIfZero { + target: 2426, + value: StatePartIndex(2002), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2425: Copy { + dest: StatePartIndex(457), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 2426: IsNonZeroDestIsSmall { + dest: StatePartIndex(60), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(457), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2427: SubU { + dest: StatePartIndex(2003), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2428: CastToUInt { + dest: StatePartIndex(2004), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(2003), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 2429: BranchIfZero { + target: 2431, + value: StatePartIndex(2002), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2430: Copy { + dest: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.addr", ty: UInt<8> }, + src: StatePartIndex(2004), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 2431: CastBigToArrayIndex { + dest: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.addr", ty: UInt<8> }, + }, + 2432: BranchIfSmallZero { + target: 2436, + value: StatePartIndex(60), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2433: MemoryReadUInt { + dest: StatePartIndex(459), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 2434: MemoryReadUInt { + dest: StatePartIndex(460), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 2435: Branch { + target: 2438, + }, + 2436: Const { + dest: StatePartIndex(459), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2437: Const { + dest: StatePartIndex(460), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2438: Copy { + dest: StatePartIndex(2005), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2439: Copy { + dest: StatePartIndex(2006), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(459), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2440: Copy { + dest: StatePartIndex(2007), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(460), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2441: Shl { + dest: StatePartIndex(2008), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2007), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2442: Or { + dest: StatePartIndex(2009), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2006), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2008), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2443: Shl { + dest: StatePartIndex(2010), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2009), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2444: Or { + dest: StatePartIndex(2011), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2005), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2010), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2445: CastToUInt { + dest: StatePartIndex(2012), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2011), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2446: Copy { + dest: StatePartIndex(2013), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2012), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2447: BranchIfZero { + target: 2449, + value: StatePartIndex(2002), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2448: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2013), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2449: CmpEq { + dest: StatePartIndex(2032), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2014), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + }, + 2450: CmpEq { + dest: StatePartIndex(2033), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2015), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + }, + 2451: CmpEq { + dest: StatePartIndex(2034), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2030), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + }, + 2452: CmpEq { + dest: StatePartIndex(2035), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2031), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1988), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.addr.value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:159:9 + 2453: BranchIfSmallNeImmediate { + target: 2458, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2454: BranchIfSmallNeImmediate { + target: 2458, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2455: BranchIfSmallNeImmediate { + target: 2458, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2456: BranchIfSmallNeImmediate { + target: 2458, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:182:29 + 2457: Copy { + dest: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(2399), // (0x0) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2458: CmpLe { + dest: StatePartIndex(2144), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + }, + 2459: CmpLt { + dest: StatePartIndex(2145), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2460: And { + dest: StatePartIndex(2146), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2144), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2145), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2461: BranchIfZero { + target: 2463, + value: StatePartIndex(2146), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2462: Copy { + dest: StatePartIndex(487), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 2463: IsNonZeroDestIsSmall { + dest: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(487), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2464: SubU { + dest: StatePartIndex(2147), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2465: CastToUInt { + dest: StatePartIndex(2148), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2147), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 2466: BranchIfZero { + target: 2468, + value: StatePartIndex(2146), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2467: Copy { + dest: StatePartIndex(486), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.addr", ty: UInt<1> }, + src: StatePartIndex(2148), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 2468: CastBigToArrayIndex { + dest: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(486), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.addr", ty: UInt<1> }, + }, + 2469: BranchIfSmallZero { + target: 2473, + value: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2470: MemoryReadUInt { + dest: StatePartIndex(489), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 2471: MemoryReadUInt { + dest: StatePartIndex(490), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 2472: Branch { + target: 2475, + }, + 2473: Const { + dest: StatePartIndex(489), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2474: Const { + dest: StatePartIndex(490), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2475: Copy { + dest: StatePartIndex(2149), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2476: Copy { + dest: StatePartIndex(2150), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(489), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2477: Copy { + dest: StatePartIndex(2151), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(490), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r5.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2478: Shl { + dest: StatePartIndex(2152), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2151), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2479: Or { + dest: StatePartIndex(2153), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2150), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2152), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2480: Shl { + dest: StatePartIndex(2154), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2153), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2481: Or { + dest: StatePartIndex(2155), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2149), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2154), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2482: CastToUInt { + dest: StatePartIndex(2156), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2155), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2483: Copy { + dest: StatePartIndex(2157), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2156), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2484: BranchIfZero { + target: 2486, + value: StatePartIndex(2146), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2485: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2157), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2486: CmpEq { + dest: StatePartIndex(2176), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2158), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + }, + 2487: CmpEq { + dest: StatePartIndex(2177), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2159), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + }, + 2488: CmpEq { + dest: StatePartIndex(2178), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2174), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + }, + 2489: CmpEq { + dest: StatePartIndex(2179), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2175), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2132), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.addr.value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:159:9 + 2490: BranchIfSmallNeImmediate { + target: 2502, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2491: BranchIfSmallNeImmediate { + target: 2502, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2492: BranchIfSmallNeImmediate { + target: 2502, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2493: BranchIfSmallNeImmediate { + target: 2498, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 2494: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2498), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2495: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2498), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2496: Copy { + dest: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2501), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2497: Copy { + dest: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2501), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:477:1 + 2498: BranchIfSmallNeImmediate { + target: 2502, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + // at: reg_alloc.rs:181:29 + 2499: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2611), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2500: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2611), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2501: Copy { + dest: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2614), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2502: CmpLe { + dest: StatePartIndex(1952), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + }, + 2503: CmpLt { + dest: StatePartIndex(1953), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2504: And { + dest: StatePartIndex(1954), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1952), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(1953), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2505: BranchIfZero { + target: 2507, + value: StatePartIndex(1954), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2506: Copy { + dest: StatePartIndex(452), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 2507: IsNonZeroDestIsSmall { + dest: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(452), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2508: SubU { + dest: StatePartIndex(1955), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2509: CastToUInt { + dest: StatePartIndex(1956), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1955), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 2510: BranchIfZero { + target: 2512, + value: StatePartIndex(1954), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2511: Copy { + dest: StatePartIndex(451), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.addr", ty: UInt<8> }, + src: StatePartIndex(1956), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 2512: CastBigToArrayIndex { + dest: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(451), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.addr", ty: UInt<8> }, + }, + 2513: BranchIfSmallZero { + target: 2517, + value: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2514: MemoryReadUInt { + dest: StatePartIndex(454), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 2515: MemoryReadUInt { + dest: StatePartIndex(455), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 2516: Branch { + target: 2519, + }, + 2517: Const { + dest: StatePartIndex(454), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2518: Const { + dest: StatePartIndex(455), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2519: Copy { + dest: StatePartIndex(1957), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2520: Copy { + dest: StatePartIndex(1958), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(454), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2521: Copy { + dest: StatePartIndex(1959), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(455), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2522: Shl { + dest: StatePartIndex(1960), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1959), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2523: Or { + dest: StatePartIndex(1961), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1958), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1960), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2524: Shl { + dest: StatePartIndex(1962), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1961), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2525: Or { + dest: StatePartIndex(1963), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1957), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1962), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2526: CastToUInt { + dest: StatePartIndex(1964), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1963), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2527: Copy { + dest: StatePartIndex(1965), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1964), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2528: BranchIfZero { + target: 2530, + value: StatePartIndex(1954), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2529: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1965), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2530: CmpEq { + dest: StatePartIndex(1984), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1966), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + }, + 2531: CmpEq { + dest: StatePartIndex(1985), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1967), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + }, + 2532: CmpEq { + dest: StatePartIndex(1986), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1982), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + }, + 2533: CmpEq { + dest: StatePartIndex(1987), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1983), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1940), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.addr.value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:159:9 + 2534: BranchIfSmallNeImmediate { + target: 2539, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2535: BranchIfSmallNeImmediate { + target: 2539, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2536: BranchIfSmallNeImmediate { + target: 2539, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2537: BranchIfSmallNeImmediate { + target: 2539, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + // at: reg_alloc.rs:182:29 + 2538: Copy { + dest: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(2614), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2539: CmpLe { + dest: StatePartIndex(2096), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + }, + 2540: CmpLt { + dest: StatePartIndex(2097), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2541: And { + dest: StatePartIndex(2098), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2096), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2097), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2542: BranchIfZero { + target: 2544, + value: StatePartIndex(2098), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2543: Copy { + dest: StatePartIndex(482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 2544: IsNonZeroDestIsSmall { + dest: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(482), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2545: SubU { + dest: StatePartIndex(2099), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2546: CastToUInt { + dest: StatePartIndex(2100), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2099), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 2547: BranchIfZero { + target: 2549, + value: StatePartIndex(2098), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2548: Copy { + dest: StatePartIndex(481), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.addr", ty: UInt<1> }, + src: StatePartIndex(2100), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 2549: CastBigToArrayIndex { + dest: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(481), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.addr", ty: UInt<1> }, + }, + 2550: BranchIfSmallZero { + target: 2554, + value: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2551: MemoryReadUInt { + dest: StatePartIndex(484), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 2552: MemoryReadUInt { + dest: StatePartIndex(485), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 2553: Branch { + target: 2556, + }, + 2554: Const { + dest: StatePartIndex(484), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2555: Const { + dest: StatePartIndex(485), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2556: Copy { + dest: StatePartIndex(2101), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2557: Copy { + dest: StatePartIndex(2102), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(484), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2558: Copy { + dest: StatePartIndex(2103), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(485), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r4.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2559: Shl { + dest: StatePartIndex(2104), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2103), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2560: Or { + dest: StatePartIndex(2105), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2102), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2104), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2561: Shl { + dest: StatePartIndex(2106), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2105), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2562: Or { + dest: StatePartIndex(2107), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2101), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2106), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2563: CastToUInt { + dest: StatePartIndex(2108), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2107), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2564: Copy { + dest: StatePartIndex(2109), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2108), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2565: BranchIfZero { + target: 2567, + value: StatePartIndex(2098), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2566: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2109), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2567: CmpEq { + dest: StatePartIndex(2128), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2110), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + }, + 2568: CmpEq { + dest: StatePartIndex(2129), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2111), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + }, + 2569: CmpEq { + dest: StatePartIndex(2130), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2126), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + }, + 2570: CmpEq { + dest: StatePartIndex(2131), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2127), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2084), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.addr.value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:159:9 + 2571: BranchIfSmallNeImmediate { + target: 2580, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2572: BranchIfSmallNeImmediate { + target: 2580, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2573: BranchIfSmallNeImmediate { + target: 2577, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + // at: instruction.rs:504:1 + 2574: BranchIfSmallNeImmediate { + target: 2577, + lhs: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 2575: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2815), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2576: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2815), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 2577: BranchIfSmallNeImmediate { + target: 2580, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + // at: instruction.rs:539:1 + 2578: BranchIfSmallNeImmediate { + target: 2580, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 2579: Copy { + dest: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2981), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2580: CmpLe { + dest: StatePartIndex(1890), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + }, + 2581: CmpLt { + dest: StatePartIndex(1891), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2582: And { + dest: StatePartIndex(1892), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1890), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(1891), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2583: BranchIfZero { + target: 2585, + value: StatePartIndex(1892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2584: Copy { + dest: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 2585: IsNonZeroDestIsSmall { + dest: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2586: SubU { + dest: StatePartIndex(1893), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2587: CastToUInt { + dest: StatePartIndex(1894), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(1893), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 2588: BranchIfZero { + target: 2590, + value: StatePartIndex(1892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2589: Copy { + dest: StatePartIndex(446), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.addr", ty: UInt<8> }, + src: StatePartIndex(1894), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 2590: CastBigToArrayIndex { + dest: StatePartIndex(51), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(446), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.addr", ty: UInt<8> }, + }, + 2591: BranchIfSmallZero { + target: 2595, + value: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2592: MemoryReadUInt { + dest: StatePartIndex(449), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(51), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 2593: MemoryReadUInt { + dest: StatePartIndex(450), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(51), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 2594: Branch { + target: 2597, + }, + 2595: Const { + dest: StatePartIndex(449), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2596: Const { + dest: StatePartIndex(450), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2597: Copy { + dest: StatePartIndex(1895), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2598: Copy { + dest: StatePartIndex(1896), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(449), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2599: Copy { + dest: StatePartIndex(1897), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(450), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2600: Shl { + dest: StatePartIndex(1898), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1897), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2601: Or { + dest: StatePartIndex(1899), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1896), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1898), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2602: Shl { + dest: StatePartIndex(1900), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1899), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2603: Or { + dest: StatePartIndex(1901), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1895), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1900), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2604: CastToUInt { + dest: StatePartIndex(1902), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1901), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2605: Copy { + dest: StatePartIndex(1903), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1902), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2606: BranchIfZero { + target: 2608, + value: StatePartIndex(1892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2607: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1903), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2608: CmpEq { + dest: StatePartIndex(1927), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1904), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + }, + 2609: CmpEq { + dest: StatePartIndex(1937), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + }, + 2610: CmpEq { + dest: StatePartIndex(1938), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1920), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + }, + 2611: CmpEq { + dest: StatePartIndex(1939), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(1923), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(1878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.addr.value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:159:9 + 2612: BranchIfSmallNeImmediate { + target: 2617, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2613: BranchIfSmallNeImmediate { + target: 2617, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2614: BranchIfSmallNeImmediate { + target: 2617, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + // at: instruction.rs:539:1 + 2615: BranchIfSmallNeImmediate { + target: 2617, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:182:29 + 2616: Copy { + dest: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(2981), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2617: CmpLe { + dest: StatePartIndex(2048), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + }, + 2618: CmpLt { + dest: StatePartIndex(2049), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2619: And { + dest: StatePartIndex(2050), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2048), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2049), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2620: BranchIfZero { + target: 2622, + value: StatePartIndex(2050), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2621: Copy { + dest: StatePartIndex(477), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 2622: IsNonZeroDestIsSmall { + dest: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(477), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2623: SubU { + dest: StatePartIndex(2051), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2624: CastToUInt { + dest: StatePartIndex(2052), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2051), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 2625: BranchIfZero { + target: 2627, + value: StatePartIndex(2050), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2626: Copy { + dest: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.addr", ty: UInt<1> }, + src: StatePartIndex(2052), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 2627: CastBigToArrayIndex { + dest: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.addr", ty: UInt<1> }, + }, + 2628: BranchIfSmallZero { + target: 2632, + value: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2629: MemoryReadUInt { + dest: StatePartIndex(479), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 2630: MemoryReadUInt { + dest: StatePartIndex(480), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 2631: Branch { + target: 2634, + }, + 2632: Const { + dest: StatePartIndex(479), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2633: Const { + dest: StatePartIndex(480), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2634: Copy { + dest: StatePartIndex(2053), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2635: Copy { + dest: StatePartIndex(2054), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(479), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2636: Copy { + dest: StatePartIndex(2055), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(480), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r3.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2637: Shl { + dest: StatePartIndex(2056), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2055), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2638: Or { + dest: StatePartIndex(2057), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2054), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2056), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2639: Shl { + dest: StatePartIndex(2058), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2057), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2640: Or { + dest: StatePartIndex(2059), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(2053), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2058), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2641: CastToUInt { + dest: StatePartIndex(2060), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2059), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2642: Copy { + dest: StatePartIndex(2061), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2060), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2643: BranchIfZero { + target: 2645, + value: StatePartIndex(2050), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2644: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(2061), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2645: CmpEq { + dest: StatePartIndex(2080), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2062), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[0].value", ty: UInt<8> }, + rhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + }, + 2646: CmpEq { + dest: StatePartIndex(2081), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::dest_reg.normal_regs[1].value", ty: UInt<8> }, + rhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + }, + 2647: CmpEq { + dest: StatePartIndex(2082), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2078), // (0xfe) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + }, + 2648: CmpEq { + dest: StatePartIndex(2083), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2079), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::flag_reg.value", ty: UInt<8> }, + rhs: StatePartIndex(2036), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.addr.value", ty: UInt<8> }, + }, + 2649: Copy { + dest: StatePartIndex(776), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[1]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 2650: SliceInt { + dest: StatePartIndex(777), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(776), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 2651: SliceInt { + dest: StatePartIndex(778), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(777), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 2652: SliceInt { + dest: StatePartIndex(779), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(778), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 2653: Copy { + dest: StatePartIndex(775), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(779), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 2654: SliceInt { + dest: StatePartIndex(781), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(777), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 2655: SliceInt { + dest: StatePartIndex(782), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(781), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 2656: Copy { + dest: StatePartIndex(780), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(782), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 2657: Copy { + dest: StatePartIndex(773), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(775), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 2658: Copy { + dest: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(780), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 2659: Copy { + dest: StatePartIndex(2760), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(328), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 2660: Copy { + dest: StatePartIndex(2761), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 2661: Copy { + dest: StatePartIndex(2762), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2767), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 2662: Copy { + dest: StatePartIndex(2763), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2768), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 2663: Copy { + dest: StatePartIndex(2764), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2769), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 2664: Copy { + dest: StatePartIndex(2765), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2792), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2665: Copy { + dest: StatePartIndex(2766), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2793), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2666: Copy { + dest: StatePartIndex(2753), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2760), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2667: Copy { + dest: StatePartIndex(2754), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2761), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 2668: Copy { + dest: StatePartIndex(2755), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2762), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 2669: Copy { + dest: StatePartIndex(2756), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2763), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 2670: Copy { + dest: StatePartIndex(2757), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2764), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 2671: Copy { + dest: StatePartIndex(2758), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2765), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2672: Copy { + dest: StatePartIndex(2759), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2766), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2673: Copy { + dest: StatePartIndex(2745), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(1542), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2674: Copy { + dest: StatePartIndex(2746), // (0x1) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2753), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 2675: Copy { + dest: StatePartIndex(2747), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2754), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 2676: Copy { + dest: StatePartIndex(2748), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2755), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 2677: Copy { + dest: StatePartIndex(2749), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2756), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 2678: Copy { + dest: StatePartIndex(2750), // (0x0) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2757), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 2679: Copy { + dest: StatePartIndex(2751), // (0x0) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2758), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 2680: Copy { + dest: StatePartIndex(2752), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2759), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 2681: Shl { + dest: StatePartIndex(2794), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2747), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 2682: Or { + dest: StatePartIndex(2795), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2746), // (0x1) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(2794), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 2683: Shl { + dest: StatePartIndex(2796), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2749), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 2684: Or { + dest: StatePartIndex(2797), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2748), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2796), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 2685: Shl { + dest: StatePartIndex(2798), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2750), // (0x0) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 2686: Or { + dest: StatePartIndex(2799), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2797), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2798), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 2687: Shl { + dest: StatePartIndex(2800), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2799), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 2688: Or { + dest: StatePartIndex(2801), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2795), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(2800), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + }, + 2689: Shl { + dest: StatePartIndex(2802), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2751), // (0x0) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 2690: Or { + dest: StatePartIndex(2803), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2801), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(2802), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 2691: CastToUInt { + dest: StatePartIndex(2804), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2752), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2692: Shl { + dest: StatePartIndex(2805), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2804), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 2693: Or { + dest: StatePartIndex(2806), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2803), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2805), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2694: Or { + dest: StatePartIndex(2808), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2806), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(2807), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2695: Shl { + dest: StatePartIndex(2809), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2808), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 2696: Or { + dest: StatePartIndex(2810), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2745), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2809), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + 2697: CastToUInt { + dest: StatePartIndex(2811), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2810), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 2698: Copy { + dest: StatePartIndex(2812), // (0x2) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2811), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:504:1 + 2699: BranchIfSmallNeImmediate { + target: 2701, + lhs: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 2700: Copy { + dest: StatePartIndex(2713), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2812), // (0x2) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + // at: reg_alloc.rs:43:1 + 2701: Copy { + dest: StatePartIndex(2926), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(384), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2702: Copy { + dest: StatePartIndex(2927), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 2703: Copy { + dest: StatePartIndex(2928), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2933), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 2704: Copy { + dest: StatePartIndex(2929), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2934), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 2705: Copy { + dest: StatePartIndex(2930), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2935), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 2706: Copy { + dest: StatePartIndex(2931), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2958), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2707: Copy { + dest: StatePartIndex(2932), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2959), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2708: Copy { + dest: StatePartIndex(2918), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(1542), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2709: Copy { + dest: StatePartIndex(2919), // (0x1) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2926), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2710: Copy { + dest: StatePartIndex(2920), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + src: StatePartIndex(2927), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 2711: Copy { + dest: StatePartIndex(2921), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + src: StatePartIndex(2928), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 2712: Copy { + dest: StatePartIndex(2922), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + src: StatePartIndex(2929), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 2713: Copy { + dest: StatePartIndex(2923), // (0x0) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + src: StatePartIndex(2930), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 2714: Copy { + dest: StatePartIndex(2924), // (0x0) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + src: StatePartIndex(2931), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2715: Copy { + dest: StatePartIndex(2925), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2932), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2716: Shl { + dest: StatePartIndex(2960), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2920), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 2717: Or { + dest: StatePartIndex(2961), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2919), // (0x1) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(2960), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 2718: Shl { + dest: StatePartIndex(2962), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2922), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 2719: Or { + dest: StatePartIndex(2963), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2921), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2962), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 2720: Shl { + dest: StatePartIndex(2964), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2923), // (0x0) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 2721: Or { + dest: StatePartIndex(2965), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2963), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2964), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 2722: Shl { + dest: StatePartIndex(2966), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2965), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 2723: Or { + dest: StatePartIndex(2967), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2961), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(2966), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + }, + 2724: Shl { + dest: StatePartIndex(2968), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2924), // (0x0) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 2725: Or { + dest: StatePartIndex(2969), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2967), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(2968), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 2726: CastToUInt { + dest: StatePartIndex(2970), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2925), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2727: Shl { + dest: StatePartIndex(2971), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2970), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 2728: Or { + dest: StatePartIndex(2972), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2969), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2971), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2729: Or { + dest: StatePartIndex(2974), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2972), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(2973), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2730: Shl { + dest: StatePartIndex(2975), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2974), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 2731: Or { + dest: StatePartIndex(2976), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2918), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2975), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + 2732: CastToUInt { + dest: StatePartIndex(2977), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2976), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 2733: Copy { + dest: StatePartIndex(2978), // (0x2) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(2977), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:539:1 + 2734: BranchIfSmallNeImmediate { + target: 2736, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2735: Copy { + dest: StatePartIndex(2894), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(2978), // (0x2) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + // at: reg_alloc.rs:43:1 + 2736: CmpEq { + dest: StatePartIndex(3586), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(1178), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:308:13 + 2737: BranchIfSmallNeImmediate { + target: 2740, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2738: BranchIfZero { + target: 2740, + value: StatePartIndex(3586), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:311:21 + 2739: Copy { + dest: StatePartIndex(3234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:308:13 + 2740: BranchIfSmallNeImmediate { + target: 2743, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2741: BranchIfZero { + target: 2743, + value: StatePartIndex(3761), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:311:21 + 2742: Copy { + dest: StatePartIndex(3234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:286:13 + 2743: Copy { + dest: StatePartIndex(3242), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(3234), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:33:9 + 2744: BranchIfZero { + target: 2746, + value: StatePartIndex(3242), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:34:13 + 2745: Copy { + dest: StatePartIndex(3568), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(3241), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: ready_valid.rs:30:27 + 2746: AndBigWithSmallImmediate { + dest: StatePartIndex(248), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3568), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 2747: Copy { + dest: StatePartIndex(3569), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(3568), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 2748: SliceInt { + dest: StatePartIndex(3570), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3569), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 2749: CastBigToArrayIndex { + dest: StatePartIndex(249), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3570), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, // at: unit_free_regs_tracker.rs:102:9 - 791: BranchIfSmallNeImmediate { - target: 793, - lhs: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + 2750: BranchIfSmallNeImmediate { + target: 2752, + lhs: StatePartIndex(248), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, rhs: 0x1, }, // at: unit_free_regs_tracker.rs:103:13 - 792: WriteIndexed { - dest: StatePartIndex(359) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(47) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, - src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + 2751: WriteIndexed { + dest: StatePartIndex(3261) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(249) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, }, - // at: unit_free_regs_tracker.rs:27:25 - 793: BranchIfSmallZero { - target: 828, - value: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 794: BranchIfSmallNonZero { - target: 812, - value: StatePartIndex(28), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 795: Copy { - dest: StatePartIndex(343), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, - src: StatePartIndex(359), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool }, - }, - 796: Copy { - dest: StatePartIndex(344), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, - src: StatePartIndex(360), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", ty: Bool }, - }, - 797: Copy { - dest: StatePartIndex(345), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, - src: StatePartIndex(361), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", ty: Bool }, - }, - 798: Copy { - dest: StatePartIndex(346), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, - src: StatePartIndex(362), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", ty: Bool }, - }, - 799: Copy { - dest: StatePartIndex(347), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, - src: StatePartIndex(363), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", ty: Bool }, - }, - 800: Copy { - dest: StatePartIndex(348), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, - src: StatePartIndex(364), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", ty: Bool }, - }, - 801: Copy { - dest: StatePartIndex(349), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, - src: StatePartIndex(365), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", ty: Bool }, - }, - 802: Copy { - dest: StatePartIndex(350), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, - src: StatePartIndex(366), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", ty: Bool }, - }, - 803: Copy { - dest: StatePartIndex(351), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, - src: StatePartIndex(367), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", ty: Bool }, - }, - 804: Copy { - dest: StatePartIndex(352), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, - src: StatePartIndex(368), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", ty: Bool }, - }, - 805: Copy { - dest: StatePartIndex(353), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, - src: StatePartIndex(369), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", ty: Bool }, - }, - 806: Copy { - dest: StatePartIndex(354), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, - src: StatePartIndex(370), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", ty: Bool }, - }, - 807: Copy { - dest: StatePartIndex(355), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, - src: StatePartIndex(371), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", ty: Bool }, - }, - 808: Copy { - dest: StatePartIndex(356), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, - src: StatePartIndex(372), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", ty: Bool }, - }, - 809: Copy { - dest: StatePartIndex(357), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, - src: StatePartIndex(373), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", ty: Bool }, - }, - 810: Copy { - dest: StatePartIndex(358), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, - src: StatePartIndex(374), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", ty: Bool }, - }, - 811: Branch { - target: 828, - }, - 812: Copy { - dest: StatePartIndex(343), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, - src: StatePartIndex(375), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, - }, - 813: Copy { - dest: StatePartIndex(344), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, - src: StatePartIndex(376), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, - }, - 814: Copy { - dest: StatePartIndex(345), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, - src: StatePartIndex(377), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, - }, - 815: Copy { - dest: StatePartIndex(346), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, - src: StatePartIndex(378), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, - }, - 816: Copy { - dest: StatePartIndex(347), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, - src: StatePartIndex(379), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, - }, - 817: Copy { - dest: StatePartIndex(348), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, - src: StatePartIndex(380), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, - }, - 818: Copy { - dest: StatePartIndex(349), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, - src: StatePartIndex(381), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, - }, - 819: Copy { - dest: StatePartIndex(350), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, - src: StatePartIndex(382), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, - }, - 820: Copy { - dest: StatePartIndex(351), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, - src: StatePartIndex(383), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, - }, - 821: Copy { - dest: StatePartIndex(352), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, - src: StatePartIndex(384), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, - }, - 822: Copy { - dest: StatePartIndex(353), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, - src: StatePartIndex(385), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, - }, - 823: Copy { - dest: StatePartIndex(354), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, - src: StatePartIndex(386), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, - }, - 824: Copy { - dest: StatePartIndex(355), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, - src: StatePartIndex(387), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, - }, - 825: Copy { - dest: StatePartIndex(356), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, - src: StatePartIndex(388), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, - }, - 826: Copy { - dest: StatePartIndex(357), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, - src: StatePartIndex(389), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, - }, - 827: Copy { - dest: StatePartIndex(358), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, - src: StatePartIndex(390), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, - }, - 828: XorSmallImmediate { - dest: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + // at: reg_alloc.rs:308:13 + 2752: BranchIfSmallNeImmediate { + target: 2756, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, rhs: 0x1, }, - // at: reg_alloc.rs:41:1 - 829: Return, + // at: reg_alloc.rs:310:17 + 2753: BranchIfZero { + target: 2756, + value: StatePartIndex(3586), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:325:21 + 2754: BranchIfSmallNeImmediate { + target: 2756, + lhs: StatePartIndex(251), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:331:25 + 2755: Copy { + dest: StatePartIndex(761), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(3760), // (0x3) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:43:1 + 2756: CmpEq { + dest: StatePartIndex(4390), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(1867), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:308:13 + 2757: BranchIfSmallNeImmediate { + target: 2760, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2758: BranchIfZero { + target: 2760, + value: StatePartIndex(4390), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:311:21 + 2759: Copy { + dest: StatePartIndex(4063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:308:13 + 2760: BranchIfSmallNeImmediate { + target: 2763, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2761: BranchIfZero { + target: 2763, + value: StatePartIndex(4550), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:311:21 + 2762: Copy { + dest: StatePartIndex(4063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:286:13 + 2763: Copy { + dest: StatePartIndex(4071), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(4063), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:33:9 + 2764: BranchIfZero { + target: 2766, + value: StatePartIndex(4071), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:34:13 + 2765: Copy { + dest: StatePartIndex(4374), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(4070), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: ready_valid.rs:30:27 + 2766: AndBigWithSmallImmediate { + dest: StatePartIndex(299), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4374), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 2767: Copy { + dest: StatePartIndex(4375), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(4374), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 2768: SliceInt { + dest: StatePartIndex(4376), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4375), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 2769: CastBigToArrayIndex { + dest: StatePartIndex(300), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4376), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:102:9 + 2770: BranchIfSmallNeImmediate { + target: 2772, + lhs: StatePartIndex(299), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:103:13 + 2771: WriteIndexed { + dest: StatePartIndex(4090) /* (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(300) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:308:13 + 2772: BranchIfSmallNeImmediate { + target: 2776, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 2773: BranchIfZero { + target: 2776, + value: StatePartIndex(4390), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:325:21 + 2774: BranchIfSmallNeImmediate { + target: 2776, + lhs: StatePartIndex(302), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:331:25 + 2775: Copy { + dest: StatePartIndex(761), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(4549), // (0x5) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:77:32 + 2776: AndBigWithSmallImmediate { + dest: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(761), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2777: Copy { + dest: StatePartIndex(766), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(761), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops_out_reg[0]", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 2778: SliceInt { + dest: StatePartIndex(767), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(766), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 2779: SliceInt { + dest: StatePartIndex(768), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(767), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 2780: SliceInt { + dest: StatePartIndex(769), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(768), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 2781: Copy { + dest: StatePartIndex(765), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(769), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 2782: SliceInt { + dest: StatePartIndex(771), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(767), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 2783: SliceInt { + dest: StatePartIndex(772), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(771), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 2784: Copy { + dest: StatePartIndex(770), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(772), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 2785: Copy { + dest: StatePartIndex(763), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(765), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 2786: Copy { + dest: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(770), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 2787: Copy { + dest: StatePartIndex(1550), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(118), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 2788: Copy { + dest: StatePartIndex(1551), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 2789: Copy { + dest: StatePartIndex(1552), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1557), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 2790: Copy { + dest: StatePartIndex(1553), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1558), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 2791: Copy { + dest: StatePartIndex(1554), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1559), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 2792: Copy { + dest: StatePartIndex(1555), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1583), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2793: Copy { + dest: StatePartIndex(1556), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1584), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2794: Copy { + dest: StatePartIndex(1543), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1550), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2795: Copy { + dest: StatePartIndex(1544), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1551), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 2796: Copy { + dest: StatePartIndex(1545), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1552), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 2797: Copy { + dest: StatePartIndex(1546), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1553), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 2798: Copy { + dest: StatePartIndex(1547), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1554), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 2799: Copy { + dest: StatePartIndex(1548), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1555), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2800: Copy { + dest: StatePartIndex(1549), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1556), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2801: Copy { + dest: StatePartIndex(1534), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(1542), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2802: Copy { + dest: StatePartIndex(1535), // (0x0) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1543), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 2803: Copy { + dest: StatePartIndex(1536), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1544), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 2804: Copy { + dest: StatePartIndex(1537), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1545), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 2805: Copy { + dest: StatePartIndex(1538), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1546), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 2806: Copy { + dest: StatePartIndex(1539), // (0x4) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1547), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 2807: Copy { + dest: StatePartIndex(1540), // (0x1234) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1548), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 2808: Copy { + dest: StatePartIndex(1541), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1549), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 2809: Shl { + dest: StatePartIndex(1585), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1536), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 2810: Or { + dest: StatePartIndex(1586), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1535), // (0x0) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(1585), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 2811: Shl { + dest: StatePartIndex(1587), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1538), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 2812: Or { + dest: StatePartIndex(1588), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1537), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1587), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 2813: Shl { + dest: StatePartIndex(1589), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1539), // (0x4) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 2814: Or { + dest: StatePartIndex(1590), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1588), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1589), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 2815: Shl { + dest: StatePartIndex(1591), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1590), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 2816: Or { + dest: StatePartIndex(1592), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1586), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(1591), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + }, + 2817: Shl { + dest: StatePartIndex(1593), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1540), // (0x1234) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 2818: Or { + dest: StatePartIndex(1594), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1592), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(1593), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + }, + 2819: CastToUInt { + dest: StatePartIndex(1595), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1541), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2820: Shl { + dest: StatePartIndex(1596), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1595), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 2821: Or { + dest: StatePartIndex(1597), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1594), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1596), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2822: Or { + dest: StatePartIndex(1599), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1597), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(1598), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2823: Shl { + dest: StatePartIndex(1600), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1599), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 2824: Or { + dest: StatePartIndex(1601), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1534), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1600), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + 2825: CastToUInt { + dest: StatePartIndex(1602), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1601), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 2826: Copy { + dest: StatePartIndex(1603), // (0x1234100000) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1602), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:504:1 + 2827: BranchIfSmallNeImmediate { + target: 2829, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x0, + }, + 2828: Copy { + dest: StatePartIndex(1502), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1603), // (0x1234100000) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + // at: reg_alloc.rs:43:1 + 2829: Copy { + dest: StatePartIndex(1717), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(174), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2830: Copy { + dest: StatePartIndex(1718), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 2831: Copy { + dest: StatePartIndex(1719), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1724), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 2832: Copy { + dest: StatePartIndex(1720), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1725), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 2833: Copy { + dest: StatePartIndex(1721), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1726), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 2834: Copy { + dest: StatePartIndex(1722), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1749), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 2835: Copy { + dest: StatePartIndex(1723), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1750), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 2836: Copy { + dest: StatePartIndex(1709), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(1542), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2837: Copy { + dest: StatePartIndex(1710), // (0x0) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1717), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 2838: Copy { + dest: StatePartIndex(1711), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + src: StatePartIndex(1718), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 2839: Copy { + dest: StatePartIndex(1712), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + src: StatePartIndex(1719), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 2840: Copy { + dest: StatePartIndex(1713), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + src: StatePartIndex(1720), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 2841: Copy { + dest: StatePartIndex(1714), // (0x4) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + src: StatePartIndex(1721), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 2842: Copy { + dest: StatePartIndex(1715), // (0x1234) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + src: StatePartIndex(1722), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 2843: Copy { + dest: StatePartIndex(1716), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1723), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 2844: Shl { + dest: StatePartIndex(1751), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1711), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 2845: Or { + dest: StatePartIndex(1752), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1710), // (0x0) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(1751), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 2846: Shl { + dest: StatePartIndex(1753), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1713), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 2847: Or { + dest: StatePartIndex(1754), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1712), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1753), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 2848: Shl { + dest: StatePartIndex(1755), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1714), // (0x4) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 2849: Or { + dest: StatePartIndex(1756), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1754), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1755), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 2850: Shl { + dest: StatePartIndex(1757), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1756), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 2851: Or { + dest: StatePartIndex(1758), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1752), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(1757), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + }, + 2852: Shl { + dest: StatePartIndex(1759), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1715), // (0x1234) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 2853: Or { + dest: StatePartIndex(1760), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1758), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(1759), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + }, + 2854: CastToUInt { + dest: StatePartIndex(1761), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1716), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 2855: Shl { + dest: StatePartIndex(1762), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1761), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 2856: Or { + dest: StatePartIndex(1763), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1760), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1762), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2857: Or { + dest: StatePartIndex(1765), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1763), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(1764), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 2858: Shl { + dest: StatePartIndex(1766), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1765), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 2859: Or { + dest: StatePartIndex(1767), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1709), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1766), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + 2860: CastToUInt { + dest: StatePartIndex(1768), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1767), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 2861: Copy { + dest: StatePartIndex(1769), // (0x1234100000) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1768), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:539:1 + 2862: BranchIfSmallNeImmediate { + target: 2864, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x0, + }, + 2863: Copy { + dest: StatePartIndex(1685), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1769), // (0x1234100000) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + // at: reg_alloc.rs:43:1 + 2864: Copy { + dest: StatePartIndex(1928), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2865: Copy { + dest: StatePartIndex(1929), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(763), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 2866: Copy { + dest: StatePartIndex(1930), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 2867: Shl { + dest: StatePartIndex(1931), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1930), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2868: Or { + dest: StatePartIndex(1932), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1929), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1931), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2869: Shl { + dest: StatePartIndex(1933), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1932), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2870: Or { + dest: StatePartIndex(1934), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(1928), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1933), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2871: CastToUInt { + dest: StatePartIndex(1935), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1934), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2872: Copy { + dest: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1935), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:159:9 + 2873: BranchIfSmallNeImmediate { + target: 2882, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2874: BranchIfSmallNeImmediate { + target: 2882, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2875: BranchIfSmallNeImmediate { + target: 2882, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2876: BranchIfSmallNeImmediate { + target: 2882, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:181:29 + 2877: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1174), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2878: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1174), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2879: Copy { + dest: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1184), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2880: Copy { + dest: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1184), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2881: Copy { + dest: StatePartIndex(850), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(1187), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2882: CmpLe { + dest: StatePartIndex(862), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(850), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", ty: UInt<8> }, + }, + 2883: CmpLt { + dest: StatePartIndex(863), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(850), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2884: And { + dest: StatePartIndex(864), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(862), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(863), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2885: BranchIfZero { + target: 2887, + value: StatePartIndex(864), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2886: Copy { + dest: StatePartIndex(442), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 2887: IsNonZeroDestIsSmall { + dest: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(442), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2888: SubU { + dest: StatePartIndex(865), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(850), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2889: CastToUInt { + dest: StatePartIndex(866), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(865), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 2890: BranchIfZero { + target: 2892, + value: StatePartIndex(864), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2891: Copy { + dest: StatePartIndex(441), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.addr", ty: UInt<8> }, + src: StatePartIndex(866), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 2892: CastBigToArrayIndex { + dest: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(441), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.addr", ty: UInt<8> }, + }, + 2893: BranchIfSmallZero { + target: 2897, + value: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2894: MemoryReadUInt { + dest: StatePartIndex(444), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 2895: MemoryReadUInt { + dest: StatePartIndex(445), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 2896: Branch { + target: 2899, + }, + 2897: Const { + dest: StatePartIndex(444), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2898: Const { + dest: StatePartIndex(445), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2899: Copy { + dest: StatePartIndex(867), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2900: Copy { + dest: StatePartIndex(868), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(444), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2901: Copy { + dest: StatePartIndex(869), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(445), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2902: Shl { + dest: StatePartIndex(870), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(869), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2903: Or { + dest: StatePartIndex(871), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(868), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(870), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2904: Shl { + dest: StatePartIndex(872), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(871), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2905: Or { + dest: StatePartIndex(873), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(867), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(872), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2906: CastToUInt { + dest: StatePartIndex(874), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(873), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2907: Copy { + dest: StatePartIndex(875), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(874), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2908: BranchIfZero { + target: 2910, + value: StatePartIndex(864), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2909: Copy { + dest: StatePartIndex(851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(875), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 2910: AndBigWithSmallImmediate { + dest: StatePartIndex(112), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 2911: Copy { + dest: StatePartIndex(855), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(851), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 2912: SliceInt { + dest: StatePartIndex(856), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(855), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 2913: SliceInt { + dest: StatePartIndex(857), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(856), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 2914: SliceInt { + dest: StatePartIndex(858), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(857), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 2915: Copy { + dest: StatePartIndex(854), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(858), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 2916: SliceInt { + dest: StatePartIndex(860), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(856), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 2917: SliceInt { + dest: StatePartIndex(861), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(860), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 2918: Copy { + dest: StatePartIndex(859), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(861), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 2919: Copy { + dest: StatePartIndex(852), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(854), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 2920: Copy { + dest: StatePartIndex(853), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(859), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:159:9 + 2921: BranchIfSmallNeImmediate { + target: 2926, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2922: BranchIfSmallNeImmediate { + target: 2926, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2923: BranchIfSmallNeImmediate { + target: 2926, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2924: BranchIfSmallNeImmediate { + target: 2926, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:182:29 + 2925: Copy { + dest: StatePartIndex(930), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", ty: UInt<8> }, + src: StatePartIndex(1187), // (0x4) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2926: CmpLe { + dest: StatePartIndex(942), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(930), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", ty: UInt<8> }, + }, + 2927: CmpLt { + dest: StatePartIndex(943), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(930), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2928: And { + dest: StatePartIndex(944), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(942), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(943), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2929: BranchIfZero { + target: 2931, + value: StatePartIndex(944), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2930: Copy { + dest: StatePartIndex(472), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 2931: IsNonZeroDestIsSmall { + dest: StatePartIndex(75), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(472), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2932: SubU { + dest: StatePartIndex(945), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(930), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2933: CastToUInt { + dest: StatePartIndex(946), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(945), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 2934: BranchIfZero { + target: 2936, + value: StatePartIndex(944), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2935: Copy { + dest: StatePartIndex(471), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.addr", ty: UInt<1> }, + src: StatePartIndex(946), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 2936: CastBigToArrayIndex { + dest: StatePartIndex(76), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(471), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.addr", ty: UInt<1> }, + }, + 2937: BranchIfSmallZero { + target: 2941, + value: StatePartIndex(75), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 2938: MemoryReadUInt { + dest: StatePartIndex(474), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(76), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 2939: MemoryReadUInt { + dest: StatePartIndex(475), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(76), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 2940: Branch { + target: 2943, + }, + 2941: Const { + dest: StatePartIndex(474), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 2942: Const { + dest: StatePartIndex(475), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 2943: Copy { + dest: StatePartIndex(947), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 2944: Copy { + dest: StatePartIndex(948), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(474), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_num.adj_value", ty: UInt<2> }, + }, + 2945: Copy { + dest: StatePartIndex(949), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(475), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r2.data.unit_out_reg.value", ty: UInt<4> }, + }, + 2946: Shl { + dest: StatePartIndex(950), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(949), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2947: Or { + dest: StatePartIndex(951), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(948), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(950), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 2948: Shl { + dest: StatePartIndex(952), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(951), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 2949: Or { + dest: StatePartIndex(953), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(947), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(952), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 2950: CastToUInt { + dest: StatePartIndex(954), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(953), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 2951: Copy { + dest: StatePartIndex(955), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(954), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 2952: BranchIfZero { + target: 2954, + value: StatePartIndex(944), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 2953: Copy { + dest: StatePartIndex(931), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(955), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 2954: AndBigWithSmallImmediate { + dest: StatePartIndex(115), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(931), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 2955: BranchIfSmallNeImmediate { + target: 2959, + lhs: StatePartIndex(112), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 2956: BranchIfSmallNeImmediate { + target: 2959, + lhs: StatePartIndex(115), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 2957: Copy { + dest: StatePartIndex(1185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 2958: Copy { + dest: StatePartIndex(1186), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 2959: Copy { + dest: StatePartIndex(935), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(931), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 2960: SliceInt { + dest: StatePartIndex(936), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(935), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 2961: SliceInt { + dest: StatePartIndex(937), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(936), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 2962: SliceInt { + dest: StatePartIndex(938), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(937), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 2963: Copy { + dest: StatePartIndex(934), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(938), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 2964: SliceInt { + dest: StatePartIndex(940), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(936), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 2965: SliceInt { + dest: StatePartIndex(941), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(940), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 2966: Copy { + dest: StatePartIndex(939), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(941), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 2967: Copy { + dest: StatePartIndex(932), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(934), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 2968: Copy { + dest: StatePartIndex(933), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(939), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 2969: BranchIfSmallNeImmediate { + target: 2973, + lhs: StatePartIndex(112), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 2970: BranchIfSmallNeImmediate { + target: 2973, + lhs: StatePartIndex(115), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 2971: Copy { + dest: StatePartIndex(1185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(932), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 2972: Copy { + dest: StatePartIndex(1186), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(933), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 2973: BranchIfSmallNeImmediate { + target: 2976, + lhs: StatePartIndex(112), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 2974: Copy { + dest: StatePartIndex(1185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(852), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 2975: Copy { + dest: StatePartIndex(1186), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(853), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 2976: Shl { + dest: StatePartIndex(1238), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1186), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 2977: Or { + dest: StatePartIndex(1239), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1185), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_2.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1238), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:159:9 + 2978: BranchIfSmallNeImmediate { + target: 2990, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 2979: BranchIfSmallNeImmediate { + target: 2990, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 2980: BranchIfSmallNeImmediate { + target: 2990, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 2981: BranchIfSmallNeImmediate { + target: 2986, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 2982: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1287), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2983: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1287), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2984: Copy { + dest: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1290), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2985: Copy { + dest: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1290), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: instruction.rs:477:1 + 2986: BranchIfSmallNeImmediate { + target: 2990, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + // at: reg_alloc.rs:181:29 + 2987: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1400), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 2988: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1400), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:181:29 + 2989: Copy { + dest: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1403), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 2990: CmpLe { + dest: StatePartIndex(836), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + }, + 2991: CmpLt { + dest: StatePartIndex(837), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 2992: And { + dest: StatePartIndex(838), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(836), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(837), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 2993: BranchIfZero { + target: 2995, + value: StatePartIndex(838), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 2994: Copy { + dest: StatePartIndex(437), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 2995: IsNonZeroDestIsSmall { + dest: StatePartIndex(40), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(437), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 2996: SubU { + dest: StatePartIndex(839), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(824), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 2997: CastToUInt { + dest: StatePartIndex(840), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(839), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 2998: BranchIfZero { + target: 3000, + value: StatePartIndex(838), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 2999: Copy { + dest: StatePartIndex(436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.addr", ty: UInt<8> }, + src: StatePartIndex(840), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 3000: CastBigToArrayIndex { + dest: StatePartIndex(41), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(436), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.addr", ty: UInt<8> }, + }, + 3001: BranchIfSmallZero { + target: 3005, + value: StatePartIndex(40), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 3002: MemoryReadUInt { + dest: StatePartIndex(439), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(41), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 3003: MemoryReadUInt { + dest: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(41), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 3004: Branch { + target: 3007, + }, + 3005: Const { + dest: StatePartIndex(439), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 3006: Const { + dest: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 3007: Copy { + dest: StatePartIndex(841), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3008: Copy { + dest: StatePartIndex(842), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(439), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + }, + 3009: Copy { + dest: StatePartIndex(843), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + }, + 3010: Shl { + dest: StatePartIndex(844), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(843), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3011: Or { + dest: StatePartIndex(845), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(842), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(844), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3012: Shl { + dest: StatePartIndex(846), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(845), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 3013: Or { + dest: StatePartIndex(847), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(841), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(846), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 3014: CastToUInt { + dest: StatePartIndex(848), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(847), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 3015: Copy { + dest: StatePartIndex(849), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(848), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 3016: BranchIfZero { + target: 3018, + value: StatePartIndex(838), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 3017: Copy { + dest: StatePartIndex(825), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(849), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 3018: AndBigWithSmallImmediate { + dest: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(825), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3019: Copy { + dest: StatePartIndex(829), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(825), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 3020: SliceInt { + dest: StatePartIndex(830), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(829), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 3021: SliceInt { + dest: StatePartIndex(831), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(830), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 3022: SliceInt { + dest: StatePartIndex(832), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(831), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 3023: Copy { + dest: StatePartIndex(828), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(832), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3024: SliceInt { + dest: StatePartIndex(834), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(830), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 3025: SliceInt { + dest: StatePartIndex(835), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(834), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3026: Copy { + dest: StatePartIndex(833), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(835), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3027: Copy { + dest: StatePartIndex(826), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(828), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 3028: Copy { + dest: StatePartIndex(827), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(833), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:159:9 + 3029: BranchIfSmallNeImmediate { + target: 3034, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 3030: BranchIfSmallNeImmediate { + target: 3034, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 3031: BranchIfSmallNeImmediate { + target: 3034, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + // at: instruction.rs:477:1 + 3032: BranchIfSmallNeImmediate { + target: 3034, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + // at: reg_alloc.rs:182:29 + 3033: Copy { + dest: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + src: StatePartIndex(1403), // (0x3) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 3034: CmpLe { + dest: StatePartIndex(916), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + }, + 3035: CmpLt { + dest: StatePartIndex(917), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 3036: And { + dest: StatePartIndex(918), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(916), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(917), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 3037: BranchIfZero { + target: 3039, + value: StatePartIndex(918), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 3038: Copy { + dest: StatePartIndex(467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 3039: IsNonZeroDestIsSmall { + dest: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(467), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 3040: SubU { + dest: StatePartIndex(919), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(904), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 3041: CastToUInt { + dest: StatePartIndex(920), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(919), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 3042: BranchIfZero { + target: 3044, + value: StatePartIndex(918), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 3043: Copy { + dest: StatePartIndex(466), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.addr", ty: UInt<1> }, + src: StatePartIndex(920), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 3044: CastBigToArrayIndex { + dest: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(466), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.addr", ty: UInt<1> }, + }, + 3045: BranchIfSmallZero { + target: 3049, + value: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 3046: MemoryReadUInt { + dest: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 3047: MemoryReadUInt { + dest: StatePartIndex(470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 3048: Branch { + target: 3051, + }, + 3049: Const { + dest: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 3050: Const { + dest: StatePartIndex(470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 3051: Copy { + dest: StatePartIndex(921), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3052: Copy { + dest: StatePartIndex(922), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_num.adj_value", ty: UInt<2> }, + }, + 3053: Copy { + dest: StatePartIndex(923), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(470), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r1.data.unit_out_reg.value", ty: UInt<4> }, + }, + 3054: Shl { + dest: StatePartIndex(924), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(923), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3055: Or { + dest: StatePartIndex(925), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(922), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(924), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3056: Shl { + dest: StatePartIndex(926), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(925), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 3057: Or { + dest: StatePartIndex(927), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(921), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(926), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 3058: CastToUInt { + dest: StatePartIndex(928), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(927), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 3059: Copy { + dest: StatePartIndex(929), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(928), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 3060: BranchIfZero { + target: 3062, + value: StatePartIndex(918), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 3061: Copy { + dest: StatePartIndex(905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(929), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 3062: AndBigWithSmallImmediate { + dest: StatePartIndex(114), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 3063: BranchIfSmallNeImmediate { + target: 3071, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3064: BranchIfSmallNeImmediate { + target: 3071, + lhs: StatePartIndex(114), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 3065: Copy { + dest: StatePartIndex(1182), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3066: Copy { + dest: StatePartIndex(1183), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3067: Copy { + dest: StatePartIndex(1288), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3068: Copy { + dest: StatePartIndex(1289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3069: Copy { + dest: StatePartIndex(1401), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3070: Copy { + dest: StatePartIndex(1402), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3071: Copy { + dest: StatePartIndex(909), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(905), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 3072: SliceInt { + dest: StatePartIndex(910), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(909), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 3073: SliceInt { + dest: StatePartIndex(911), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(910), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 3074: SliceInt { + dest: StatePartIndex(912), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(911), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 3075: Copy { + dest: StatePartIndex(908), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(912), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3076: SliceInt { + dest: StatePartIndex(914), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(910), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 3077: SliceInt { + dest: StatePartIndex(915), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(914), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3078: Copy { + dest: StatePartIndex(913), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(915), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3079: Copy { + dest: StatePartIndex(906), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(908), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 3080: Copy { + dest: StatePartIndex(907), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(913), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3081: BranchIfSmallNeImmediate { + target: 3085, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3082: BranchIfSmallNeImmediate { + target: 3085, + lhs: StatePartIndex(114), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3083: Copy { + dest: StatePartIndex(1182), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(906), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3084: Copy { + dest: StatePartIndex(1183), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(907), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3085: BranchIfSmallNeImmediate { + target: 3088, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3086: Copy { + dest: StatePartIndex(1182), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(826), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3087: Copy { + dest: StatePartIndex(1183), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(827), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3088: Shl { + dest: StatePartIndex(1236), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1183), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3089: Or { + dest: StatePartIndex(1237), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1182), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1236), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 3090: BranchIfSmallNeImmediate { + target: 3094, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3091: BranchIfSmallNeImmediate { + target: 3094, + lhs: StatePartIndex(114), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3092: Copy { + dest: StatePartIndex(1288), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(906), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3093: Copy { + dest: StatePartIndex(1289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(907), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3094: BranchIfSmallNeImmediate { + target: 3097, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3095: Copy { + dest: StatePartIndex(1288), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(826), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3096: Copy { + dest: StatePartIndex(1289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(827), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3097: Shl { + dest: StatePartIndex(1338), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1289), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3098: Or { + dest: StatePartIndex(1339), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1288), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1338), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 3099: BranchIfSmallNeImmediate { + target: 3103, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3100: BranchIfSmallNeImmediate { + target: 3103, + lhs: StatePartIndex(114), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3101: Copy { + dest: StatePartIndex(1401), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(906), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3102: Copy { + dest: StatePartIndex(1402), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(907), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3103: BranchIfSmallNeImmediate { + target: 3106, + lhs: StatePartIndex(111), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3104: Copy { + dest: StatePartIndex(1401), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(826), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3105: Copy { + dest: StatePartIndex(1402), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(827), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3106: Shl { + dest: StatePartIndex(1445), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1402), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3107: Or { + dest: StatePartIndex(1446), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1401), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1445), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:159:9 + 3108: BranchIfSmallNeImmediate { + target: 3117, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 3109: BranchIfSmallNeImmediate { + target: 3117, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 3110: BranchIfSmallNeImmediate { + target: 3114, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + // at: instruction.rs:504:1 + 3111: BranchIfSmallNeImmediate { + target: 3114, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 3112: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1606), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:182:29 + 3113: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1606), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: unit.rs:127:1 + 3114: BranchIfSmallNeImmediate { + target: 3117, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + // at: instruction.rs:539:1 + 3115: BranchIfSmallNeImmediate { + target: 3117, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:181:29 + 3116: Copy { + dest: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1772), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 3117: CmpLe { + dest: StatePartIndex(808), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + }, + 3118: CmpLt { + dest: StatePartIndex(810), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + }, + 3119: And { + dest: StatePartIndex(811), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(808), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(810), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 3120: BranchIfZero { + target: 3122, + value: StatePartIndex(811), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 3121: Copy { + dest: StatePartIndex(432), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 3122: IsNonZeroDestIsSmall { + dest: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(432), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 3123: SubU { + dest: StatePartIndex(812), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(790), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(807), // (0x1) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 3124: CastToUInt { + dest: StatePartIndex(813), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(812), // (0x1ffffffff) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 8, + }, + // at: reg_alloc.rs:114:17 + 3125: BranchIfZero { + target: 3127, + value: StatePartIndex(811), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 3126: Copy { + dest: StatePartIndex(431), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.addr", ty: UInt<8> }, + src: StatePartIndex(813), // (0xff) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: reg_alloc.rs:60:39 + 3127: CastBigToArrayIndex { + dest: StatePartIndex(36), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(431), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.addr", ty: UInt<8> }, + }, + 3128: BranchIfSmallZero { + target: 3132, + value: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 3129: MemoryReadUInt { + dest: StatePartIndex(434), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(36), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 0, + width: 2, + }, + 3130: MemoryReadUInt { + dest: StatePartIndex(435), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + // data: [ + // // len = 0xfd + // [0x0]: 0x00, + // [0x1]: 0x00, + // [0x2]: 0x00, + // [0x3]: 0x00, + // [0x4]: 0x00, + // [0x5]: 0x00, + // [0x6]: 0x00, + // [0x7]: 0x00, + // [0x8]: 0x00, + // [0x9]: 0x00, + // [0xa]: 0x00, + // [0xb]: 0x00, + // [0xc]: 0x00, + // [0xd]: 0x00, + // [0xe]: 0x00, + // [0xf]: 0x00, + // [0x10]: 0x00, + // [0x11]: 0x00, + // [0x12]: 0x00, + // [0x13]: 0x00, + // [0x14]: 0x00, + // [0x15]: 0x00, + // [0x16]: 0x00, + // [0x17]: 0x00, + // [0x18]: 0x00, + // [0x19]: 0x00, + // [0x1a]: 0x00, + // [0x1b]: 0x00, + // [0x1c]: 0x00, + // [0x1d]: 0x00, + // [0x1e]: 0x00, + // [0x1f]: 0x00, + // [0x20]: 0x00, + // [0x21]: 0x00, + // [0x22]: 0x00, + // [0x23]: 0x00, + // [0x24]: 0x00, + // [0x25]: 0x00, + // [0x26]: 0x00, + // [0x27]: 0x00, + // [0x28]: 0x00, + // [0x29]: 0x00, + // [0x2a]: 0x00, + // [0x2b]: 0x00, + // [0x2c]: 0x00, + // [0x2d]: 0x00, + // [0x2e]: 0x00, + // [0x2f]: 0x00, + // [0x30]: 0x00, + // [0x31]: 0x00, + // [0x32]: 0x00, + // [0x33]: 0x00, + // [0x34]: 0x00, + // [0x35]: 0x00, + // [0x36]: 0x00, + // [0x37]: 0x00, + // [0x38]: 0x00, + // [0x39]: 0x00, + // [0x3a]: 0x00, + // [0x3b]: 0x00, + // [0x3c]: 0x00, + // [0x3d]: 0x00, + // [0x3e]: 0x00, + // [0x3f]: 0x00, + // [0x40]: 0x00, + // [0x41]: 0x00, + // [0x42]: 0x00, + // [0x43]: 0x00, + // [0x44]: 0x00, + // [0x45]: 0x00, + // [0x46]: 0x00, + // [0x47]: 0x00, + // [0x48]: 0x00, + // [0x49]: 0x00, + // [0x4a]: 0x00, + // [0x4b]: 0x00, + // [0x4c]: 0x00, + // [0x4d]: 0x00, + // [0x4e]: 0x00, + // [0x4f]: 0x00, + // [0x50]: 0x00, + // [0x51]: 0x00, + // [0x52]: 0x00, + // [0x53]: 0x00, + // [0x54]: 0x00, + // [0x55]: 0x00, + // [0x56]: 0x00, + // [0x57]: 0x00, + // [0x58]: 0x00, + // [0x59]: 0x00, + // [0x5a]: 0x00, + // [0x5b]: 0x00, + // [0x5c]: 0x00, + // [0x5d]: 0x00, + // [0x5e]: 0x00, + // [0x5f]: 0x00, + // [0x60]: 0x00, + // [0x61]: 0x00, + // [0x62]: 0x00, + // [0x63]: 0x00, + // [0x64]: 0x00, + // [0x65]: 0x00, + // [0x66]: 0x00, + // [0x67]: 0x00, + // [0x68]: 0x00, + // [0x69]: 0x00, + // [0x6a]: 0x00, + // [0x6b]: 0x00, + // [0x6c]: 0x00, + // [0x6d]: 0x00, + // [0x6e]: 0x00, + // [0x6f]: 0x00, + // [0x70]: 0x00, + // [0x71]: 0x00, + // [0x72]: 0x00, + // [0x73]: 0x00, + // [0x74]: 0x00, + // [0x75]: 0x00, + // [0x76]: 0x00, + // [0x77]: 0x00, + // [0x78]: 0x00, + // [0x79]: 0x00, + // [0x7a]: 0x00, + // [0x7b]: 0x00, + // [0x7c]: 0x00, + // [0x7d]: 0x00, + // [0x7e]: 0x00, + // [0x7f]: 0x00, + // [0x80]: 0x00, + // [0x81]: 0x00, + // [0x82]: 0x00, + // [0x83]: 0x00, + // [0x84]: 0x00, + // [0x85]: 0x00, + // [0x86]: 0x00, + // [0x87]: 0x00, + // [0x88]: 0x00, + // [0x89]: 0x00, + // [0x8a]: 0x00, + // [0x8b]: 0x00, + // [0x8c]: 0x00, + // [0x8d]: 0x00, + // [0x8e]: 0x00, + // [0x8f]: 0x00, + // [0x90]: 0x00, + // [0x91]: 0x00, + // [0x92]: 0x00, + // [0x93]: 0x00, + // [0x94]: 0x00, + // [0x95]: 0x00, + // [0x96]: 0x00, + // [0x97]: 0x00, + // [0x98]: 0x00, + // [0x99]: 0x00, + // [0x9a]: 0x00, + // [0x9b]: 0x00, + // [0x9c]: 0x00, + // [0x9d]: 0x00, + // [0x9e]: 0x00, + // [0x9f]: 0x00, + // [0xa0]: 0x00, + // [0xa1]: 0x00, + // [0xa2]: 0x00, + // [0xa3]: 0x00, + // [0xa4]: 0x00, + // [0xa5]: 0x00, + // [0xa6]: 0x00, + // [0xa7]: 0x00, + // [0xa8]: 0x00, + // [0xa9]: 0x00, + // [0xaa]: 0x00, + // [0xab]: 0x00, + // [0xac]: 0x00, + // [0xad]: 0x00, + // [0xae]: 0x00, + // [0xaf]: 0x00, + // [0xb0]: 0x00, + // [0xb1]: 0x00, + // [0xb2]: 0x00, + // [0xb3]: 0x00, + // [0xb4]: 0x00, + // [0xb5]: 0x00, + // [0xb6]: 0x00, + // [0xb7]: 0x00, + // [0xb8]: 0x00, + // [0xb9]: 0x00, + // [0xba]: 0x00, + // [0xbb]: 0x00, + // [0xbc]: 0x00, + // [0xbd]: 0x00, + // [0xbe]: 0x00, + // [0xbf]: 0x00, + // [0xc0]: 0x00, + // [0xc1]: 0x00, + // [0xc2]: 0x00, + // [0xc3]: 0x00, + // [0xc4]: 0x00, + // [0xc5]: 0x00, + // [0xc6]: 0x00, + // [0xc7]: 0x00, + // [0xc8]: 0x00, + // [0xc9]: 0x00, + // [0xca]: 0x00, + // [0xcb]: 0x00, + // [0xcc]: 0x00, + // [0xcd]: 0x00, + // [0xce]: 0x00, + // [0xcf]: 0x00, + // [0xd0]: 0x00, + // [0xd1]: 0x00, + // [0xd2]: 0x00, + // [0xd3]: 0x00, + // [0xd4]: 0x00, + // [0xd5]: 0x00, + // [0xd6]: 0x00, + // [0xd7]: 0x00, + // [0xd8]: 0x00, + // [0xd9]: 0x00, + // [0xda]: 0x00, + // [0xdb]: 0x00, + // [0xdc]: 0x00, + // [0xdd]: 0x00, + // [0xde]: 0x00, + // [0xdf]: 0x00, + // [0xe0]: 0x00, + // [0xe1]: 0x00, + // [0xe2]: 0x00, + // [0xe3]: 0x00, + // [0xe4]: 0x00, + // [0xe5]: 0x00, + // [0xe6]: 0x00, + // [0xe7]: 0x00, + // [0xe8]: 0x00, + // [0xe9]: 0x00, + // [0xea]: 0x00, + // [0xeb]: 0x00, + // [0xec]: 0x00, + // [0xed]: 0x00, + // [0xee]: 0x00, + // [0xef]: 0x00, + // [0xf0]: 0x00, + // [0xf1]: 0x00, + // [0xf2]: 0x00, + // [0xf3]: 0x00, + // [0xf4]: 0x00, + // [0xf5]: 0x00, + // [0xf6]: 0x00, + // [0xf7]: 0x00, + // [0xf8]: 0x00, + // [0xf9]: 0x00, + // [0xfa]: 0x00, + // [0xfb]: 0x00, + // [0xfc]: 0x00, + // ], + // }) (), + addr: StatePartIndex(36), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> }, + stride: 6, + start: 2, + width: 4, + }, + 3131: Branch { + target: 3134, + }, + 3132: Const { + dest: StatePartIndex(434), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 3133: Const { + dest: StatePartIndex(435), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 3134: Copy { + dest: StatePartIndex(814), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3135: Copy { + dest: StatePartIndex(815), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(434), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + }, + 3136: Copy { + dest: StatePartIndex(816), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(435), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + }, + 3137: Shl { + dest: StatePartIndex(818), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(816), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3138: Or { + dest: StatePartIndex(819), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(815), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(818), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3139: Shl { + dest: StatePartIndex(820), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(819), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 3140: Or { + dest: StatePartIndex(821), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(814), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(820), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 3141: CastToUInt { + dest: StatePartIndex(822), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(821), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 3142: Copy { + dest: StatePartIndex(823), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(822), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 3143: BranchIfZero { + target: 3145, + value: StatePartIndex(811), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 3144: Copy { + dest: StatePartIndex(791), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(823), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 3145: AndBigWithSmallImmediate { + dest: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(791), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3146: Copy { + dest: StatePartIndex(795), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(791), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 3147: SliceInt { + dest: StatePartIndex(796), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(795), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 3148: SliceInt { + dest: StatePartIndex(797), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(796), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 3149: SliceInt { + dest: StatePartIndex(798), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(797), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 3150: Copy { + dest: StatePartIndex(794), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(798), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3151: SliceInt { + dest: StatePartIndex(800), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(796), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 3152: SliceInt { + dest: StatePartIndex(801), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(800), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3153: Copy { + dest: StatePartIndex(799), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(801), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3154: Copy { + dest: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(794), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 3155: Copy { + dest: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(799), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:159:9 + 3156: BranchIfSmallNeImmediate { + target: 3161, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 3157: BranchIfSmallNeImmediate { + target: 3161, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit.rs:127:1 + 3158: BranchIfSmallNeImmediate { + target: 3161, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + // at: instruction.rs:539:1 + 3159: BranchIfSmallNeImmediate { + target: 3161, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:182:29 + 3160: Copy { + dest: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + src: StatePartIndex(1772), // (0x2) SlotDebugData { name: ".value", ty: UInt<8> }, + }, + // at: reg_alloc.rs:43:1 + 3161: CmpLe { + dest: StatePartIndex(889), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + rhs: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + }, + 3162: CmpLt { + dest: StatePartIndex(891), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(890), // (0x100) SlotDebugData { name: "", ty: UInt<32> }, + }, + 3163: And { + dest: StatePartIndex(892), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(889), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(891), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:114:17 + 3164: BranchIfZero { + target: 3166, + value: StatePartIndex(892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:116:21 + 3165: Copy { + dest: StatePartIndex(462), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.en", ty: Bool }, + src: StatePartIndex(783), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 3166: IsNonZeroDestIsSmall { + dest: StatePartIndex(65), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(462), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.en", ty: Bool }, + }, + // at: reg_alloc.rs:43:1 + 3167: SubU { + dest: StatePartIndex(893), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + lhs: StatePartIndex(877), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.addr.value", ty: UInt<8> }, + rhs: StatePartIndex(809), // (0xfe) SlotDebugData { name: "", ty: UInt<32> }, + dest_width: 33, + }, + 3168: CastToUInt { + dest: StatePartIndex(894), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(893), // (0x1ffffff02) SlotDebugData { name: "", ty: UInt<33> }, + dest_width: 1, + }, + // at: reg_alloc.rs:114:17 + 3169: BranchIfZero { + target: 3171, + value: StatePartIndex(892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:115:21 + 3170: Copy { + dest: StatePartIndex(461), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(894), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:65:40 + 3171: CastBigToArrayIndex { + dest: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(461), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.addr", ty: UInt<1> }, + }, + 3172: BranchIfSmallZero { + target: 3176, + value: StatePartIndex(65), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 3173: MemoryReadUInt { + dest: StatePartIndex(464), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 0, + width: 2, + }, + 3174: MemoryReadUInt { + dest: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x00, + // [0x1]: 0x00, + // ], + // }) (), + addr: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 6, + start: 2, + width: 4, + }, + 3175: Branch { + target: 3178, + }, + 3176: Const { + dest: StatePartIndex(464), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + value: 0x0, + }, + 3177: Const { + dest: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + value: 0x0, + }, + // at: reg_alloc.rs:43:1 + 3178: Copy { + dest: StatePartIndex(895), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3179: Copy { + dest: StatePartIndex(896), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(464), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_num.adj_value", ty: UInt<2> }, + }, + 3180: Copy { + dest: StatePartIndex(897), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(465), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_mem::r0.data.unit_out_reg.value", ty: UInt<4> }, + }, + 3181: Shl { + dest: StatePartIndex(898), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(897), // (0x0) SlotDebugData { name: ".1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3182: Or { + dest: StatePartIndex(899), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(896), // (0x0) SlotDebugData { name: ".1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(898), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3183: Shl { + dest: StatePartIndex(900), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(899), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + rhs: 1, + }, + 3184: Or { + dest: StatePartIndex(901), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + lhs: StatePartIndex(895), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(900), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + }, + 3185: CastToUInt { + dest: StatePartIndex(902), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(901), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + dest_width: 7, + }, + 3186: Copy { + dest: StatePartIndex(903), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(902), // (0x1) SlotDebugData { name: "", ty: UInt<7> }, + }, + // at: reg_alloc.rs:114:17 + 3187: BranchIfZero { + target: 3189, + value: StatePartIndex(892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:117:21 + 3188: Copy { + dest: StatePartIndex(878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(903), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 3189: AndBigWithSmallImmediate { + dest: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 3190: BranchIfSmallNeImmediate { + target: 3202, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3191: BranchIfSmallNeImmediate { + target: 3202, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 3192: Copy { + dest: StatePartIndex(1172), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3193: Copy { + dest: StatePartIndex(1173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3194: Copy { + dest: StatePartIndex(1285), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3195: Copy { + dest: StatePartIndex(1286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3196: Copy { + dest: StatePartIndex(1398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3197: Copy { + dest: StatePartIndex(1399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3198: Copy { + dest: StatePartIndex(1604), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3199: Copy { + dest: StatePartIndex(1605), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3200: Copy { + dest: StatePartIndex(1770), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3201: Copy { + dest: StatePartIndex(1771), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3202: Copy { + dest: StatePartIndex(882), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(878), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_0_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 3203: SliceInt { + dest: StatePartIndex(883), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(882), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 3204: SliceInt { + dest: StatePartIndex(884), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(883), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 3205: SliceInt { + dest: StatePartIndex(885), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(884), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 3206: Copy { + dest: StatePartIndex(881), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(885), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3207: SliceInt { + dest: StatePartIndex(887), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(883), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 3208: SliceInt { + dest: StatePartIndex(888), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(887), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3209: Copy { + dest: StatePartIndex(886), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(888), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3210: Copy { + dest: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(881), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 3211: Copy { + dest: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(886), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3212: BranchIfSmallNeImmediate { + target: 3216, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3213: BranchIfSmallNeImmediate { + target: 3216, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3214: Copy { + dest: StatePartIndex(1172), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3215: Copy { + dest: StatePartIndex(1173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3216: BranchIfSmallNeImmediate { + target: 3219, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3217: Copy { + dest: StatePartIndex(1172), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3218: Copy { + dest: StatePartIndex(1173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3219: Shl { + dest: StatePartIndex(1234), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1173), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3220: Or { + dest: StatePartIndex(1235), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1172), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1234), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3221: Copy { + dest: StatePartIndex(1231), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1235), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3222: Copy { + dest: StatePartIndex(1232), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1237), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3223: Copy { + dest: StatePartIndex(1233), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1239), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3224: Copy { + dest: StatePartIndex(1228), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1231), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3225: Copy { + dest: StatePartIndex(1229), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1232), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3226: Copy { + dest: StatePartIndex(1230), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1233), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3227: Copy { + dest: StatePartIndex(1221), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(21), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3228: Copy { + dest: StatePartIndex(1222), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3229: Copy { + dest: StatePartIndex(1223), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1228), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3230: Copy { + dest: StatePartIndex(1224), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1229), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3231: Copy { + dest: StatePartIndex(1225), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1230), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3232: Copy { + dest: StatePartIndex(1226), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1249), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3233: Copy { + dest: StatePartIndex(1227), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1250), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3234: Copy { + dest: StatePartIndex(1213), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1221), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3235: Copy { + dest: StatePartIndex(1214), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1222), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3236: Copy { + dest: StatePartIndex(1215), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1223), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3237: Copy { + dest: StatePartIndex(1216), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1224), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3238: Copy { + dest: StatePartIndex(1217), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1225), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3239: Copy { + dest: StatePartIndex(1218), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1226), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3240: Copy { + dest: StatePartIndex(1219), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1227), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3241: Copy { + dest: StatePartIndex(1220), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3242: Copy { + dest: StatePartIndex(1201), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1213), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3243: Copy { + dest: StatePartIndex(1202), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1214), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3244: Copy { + dest: StatePartIndex(1203), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1215), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3245: Copy { + dest: StatePartIndex(1204), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1216), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3246: Copy { + dest: StatePartIndex(1205), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1217), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3247: Copy { + dest: StatePartIndex(1206), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1218), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3248: Copy { + dest: StatePartIndex(1207), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1219), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3249: Copy { + dest: StatePartIndex(1208), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1220), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3250: Copy { + dest: StatePartIndex(1209), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(32), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 3251: Copy { + dest: StatePartIndex(1210), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(33), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 3252: Copy { + dest: StatePartIndex(1211), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 3253: Copy { + dest: StatePartIndex(1212), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 3254: Copy { + dest: StatePartIndex(1188), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3255: Copy { + dest: StatePartIndex(1189), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1201), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3256: Copy { + dest: StatePartIndex(1190), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1202), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 3257: Copy { + dest: StatePartIndex(1191), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1203), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 3258: Copy { + dest: StatePartIndex(1192), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1204), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 3259: Copy { + dest: StatePartIndex(1193), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1205), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 3260: Copy { + dest: StatePartIndex(1194), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1206), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 3261: Copy { + dest: StatePartIndex(1195), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1207), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 3262: Copy { + dest: StatePartIndex(1196), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1208), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3263: Copy { + dest: StatePartIndex(1197), // (0x1) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + src: StatePartIndex(1209), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 3264: Copy { + dest: StatePartIndex(1198), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + src: StatePartIndex(1210), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 3265: Copy { + dest: StatePartIndex(1199), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + src: StatePartIndex(1211), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 3266: Copy { + dest: StatePartIndex(1200), // (0x1) SlotDebugData { name: ".1.add_pc", ty: Bool }, + src: StatePartIndex(1212), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 3267: Shl { + dest: StatePartIndex(1251), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1190), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 3268: Or { + dest: StatePartIndex(1252), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1189), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(1251), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3269: Shl { + dest: StatePartIndex(1253), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1192), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 3270: Or { + dest: StatePartIndex(1254), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1191), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1253), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 3271: Shl { + dest: StatePartIndex(1255), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1193), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 3272: Or { + dest: StatePartIndex(1256), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1254), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1255), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 3273: Shl { + dest: StatePartIndex(1257), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1256), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 3274: Or { + dest: StatePartIndex(1258), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1252), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(1257), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + }, + 3275: Shl { + dest: StatePartIndex(1259), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1194), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 3276: Or { + dest: StatePartIndex(1260), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1258), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(1259), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + }, + 3277: CastToUInt { + dest: StatePartIndex(1261), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1195), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 3278: Shl { + dest: StatePartIndex(1262), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1261), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 3279: Or { + dest: StatePartIndex(1263), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1260), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(1262), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3280: Or { + dest: StatePartIndex(1265), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1263), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1264), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3281: Copy { + dest: StatePartIndex(1266), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1196), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3282: Shl { + dest: StatePartIndex(1267), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1266), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 3283: Or { + dest: StatePartIndex(1268), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1265), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1267), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 3284: Copy { + dest: StatePartIndex(1269), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1197), // (0x1) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + }, + 3285: Shl { + dest: StatePartIndex(1270), // (0x8000000000000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1269), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 51, + }, + 3286: Or { + dest: StatePartIndex(1271), // (0x800048d000000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1268), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(1270), // (0x8000000000000) SlotDebugData { name: "", ty: UInt<52> }, + }, + 3287: Copy { + dest: StatePartIndex(1272), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1198), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + }, + 3288: Shl { + dest: StatePartIndex(1273), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(1272), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 52, + }, + 3289: Or { + dest: StatePartIndex(1274), // (0x1800048d000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(1271), // (0x800048d000000) SlotDebugData { name: "", ty: UInt<52> }, + rhs: StatePartIndex(1273), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + }, + 3290: Copy { + dest: StatePartIndex(1275), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1199), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + }, + 3291: Shl { + dest: StatePartIndex(1276), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(1275), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 53, + }, + 3292: Or { + dest: StatePartIndex(1277), // (0x3800048d000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(1274), // (0x1800048d000000) SlotDebugData { name: "", ty: UInt<53> }, + rhs: StatePartIndex(1276), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + }, + 3293: Copy { + dest: StatePartIndex(1278), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1200), // (0x1) SlotDebugData { name: ".1.add_pc", ty: Bool }, + }, + 3294: Shl { + dest: StatePartIndex(1279), // (0x40000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1278), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 54, + }, + 3295: Or { + dest: StatePartIndex(1280), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1277), // (0x3800048d000000) SlotDebugData { name: "", ty: UInt<54> }, + rhs: StatePartIndex(1279), // (0x40000000000000) SlotDebugData { name: "", ty: UInt<55> }, + }, + 3296: Shl { + dest: StatePartIndex(1281), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1280), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 3297: Or { + dest: StatePartIndex(1282), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1188), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1281), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 3298: CastToUInt { + dest: StatePartIndex(1283), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(1282), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 3299: Copy { + dest: StatePartIndex(1284), // (0x1e0001234000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1283), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: instruction.rs:477:1 + 3300: BranchIfSmallNeImmediate { + target: 3302, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 3301: Copy { + dest: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1284), // (0x1e0001234000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + // at: reg_alloc.rs:184:29 + 3302: BranchIfSmallNeImmediate { + target: 3306, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3303: BranchIfSmallNeImmediate { + target: 3306, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3304: Copy { + dest: StatePartIndex(1285), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3305: Copy { + dest: StatePartIndex(1286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3306: BranchIfSmallNeImmediate { + target: 3309, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3307: Copy { + dest: StatePartIndex(1285), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3308: Copy { + dest: StatePartIndex(1286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3309: Shl { + dest: StatePartIndex(1336), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3310: Or { + dest: StatePartIndex(1337), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1285), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1336), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3311: Copy { + dest: StatePartIndex(1334), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1337), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3312: Copy { + dest: StatePartIndex(1335), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1339), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3313: Copy { + dest: StatePartIndex(1331), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1334), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3314: Copy { + dest: StatePartIndex(1332), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1335), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3315: Copy { + dest: StatePartIndex(1333), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1361), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3316: Copy { + dest: StatePartIndex(1324), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(21), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3317: Copy { + dest: StatePartIndex(1325), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3318: Copy { + dest: StatePartIndex(1326), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1331), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3319: Copy { + dest: StatePartIndex(1327), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1332), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3320: Copy { + dest: StatePartIndex(1328), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1333), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3321: Copy { + dest: StatePartIndex(1329), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1362), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3322: Copy { + dest: StatePartIndex(1330), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1363), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3323: Copy { + dest: StatePartIndex(1316), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1324), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3324: Copy { + dest: StatePartIndex(1317), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1325), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3325: Copy { + dest: StatePartIndex(1318), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1326), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3326: Copy { + dest: StatePartIndex(1319), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1327), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3327: Copy { + dest: StatePartIndex(1320), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1328), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3328: Copy { + dest: StatePartIndex(1321), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1329), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3329: Copy { + dest: StatePartIndex(1322), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1330), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3330: Copy { + dest: StatePartIndex(1323), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3331: Copy { + dest: StatePartIndex(1304), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1316), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3332: Copy { + dest: StatePartIndex(1305), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1317), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3333: Copy { + dest: StatePartIndex(1306), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1318), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3334: Copy { + dest: StatePartIndex(1307), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1319), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3335: Copy { + dest: StatePartIndex(1308), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1320), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3336: Copy { + dest: StatePartIndex(1309), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1321), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3337: Copy { + dest: StatePartIndex(1310), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1322), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3338: Copy { + dest: StatePartIndex(1311), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1323), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3339: Copy { + dest: StatePartIndex(1312), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(32), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 3340: Copy { + dest: StatePartIndex(1313), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(33), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 3341: Copy { + dest: StatePartIndex(1314), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 3342: Copy { + dest: StatePartIndex(1315), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 3343: Copy { + dest: StatePartIndex(1291), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3344: Copy { + dest: StatePartIndex(1292), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1304), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3345: Copy { + dest: StatePartIndex(1293), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1305), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 3346: Copy { + dest: StatePartIndex(1294), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1306), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 3347: Copy { + dest: StatePartIndex(1295), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1307), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 3348: Copy { + dest: StatePartIndex(1296), // (0x4) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1308), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 3349: Copy { + dest: StatePartIndex(1297), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1309), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 3350: Copy { + dest: StatePartIndex(1298), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1310), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 3351: Copy { + dest: StatePartIndex(1299), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1311), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3352: Copy { + dest: StatePartIndex(1300), // (0x1) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + src: StatePartIndex(1312), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 3353: Copy { + dest: StatePartIndex(1301), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + src: StatePartIndex(1313), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 3354: Copy { + dest: StatePartIndex(1302), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + src: StatePartIndex(1314), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 3355: Copy { + dest: StatePartIndex(1303), // (0x1) SlotDebugData { name: ".1.add_pc", ty: Bool }, + src: StatePartIndex(1315), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 3356: Shl { + dest: StatePartIndex(1364), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1293), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 3357: Or { + dest: StatePartIndex(1365), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1292), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(1364), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3358: Shl { + dest: StatePartIndex(1366), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1295), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 3359: Or { + dest: StatePartIndex(1367), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1294), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1366), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 3360: Shl { + dest: StatePartIndex(1368), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1296), // (0x4) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 3361: Or { + dest: StatePartIndex(1369), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1367), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1368), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 3362: Shl { + dest: StatePartIndex(1370), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1369), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 3363: Or { + dest: StatePartIndex(1371), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1365), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(1370), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + }, + 3364: Shl { + dest: StatePartIndex(1372), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1297), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 3365: Or { + dest: StatePartIndex(1373), // (0x48d040000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1371), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(1372), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + }, + 3366: CastToUInt { + dest: StatePartIndex(1374), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1298), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 3367: Shl { + dest: StatePartIndex(1375), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1374), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 3368: Or { + dest: StatePartIndex(1376), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1373), // (0x48d040000) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(1375), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3369: Or { + dest: StatePartIndex(1378), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1376), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1377), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3370: Copy { + dest: StatePartIndex(1379), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1299), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3371: Shl { + dest: StatePartIndex(1380), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1379), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 3372: Or { + dest: StatePartIndex(1381), // (0x48d040000) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1378), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1380), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 3373: Copy { + dest: StatePartIndex(1382), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1300), // (0x1) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + }, + 3374: Shl { + dest: StatePartIndex(1383), // (0x8000000000000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1382), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 51, + }, + 3375: Or { + dest: StatePartIndex(1384), // (0x800048d040000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1381), // (0x48d040000) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(1383), // (0x8000000000000) SlotDebugData { name: "", ty: UInt<52> }, + }, + 3376: Copy { + dest: StatePartIndex(1385), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1301), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + }, + 3377: Shl { + dest: StatePartIndex(1386), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(1385), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 52, + }, + 3378: Or { + dest: StatePartIndex(1387), // (0x1800048d040000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(1384), // (0x800048d040000) SlotDebugData { name: "", ty: UInt<52> }, + rhs: StatePartIndex(1386), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + }, + 3379: Copy { + dest: StatePartIndex(1388), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1302), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + }, + 3380: Shl { + dest: StatePartIndex(1389), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(1388), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 53, + }, + 3381: Or { + dest: StatePartIndex(1390), // (0x3800048d040000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(1387), // (0x1800048d040000) SlotDebugData { name: "", ty: UInt<53> }, + rhs: StatePartIndex(1389), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + }, + 3382: Copy { + dest: StatePartIndex(1391), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1303), // (0x1) SlotDebugData { name: ".1.add_pc", ty: Bool }, + }, + 3383: Shl { + dest: StatePartIndex(1392), // (0x40000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1391), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 54, + }, + 3384: Or { + dest: StatePartIndex(1393), // (0x7800048d040000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1390), // (0x3800048d040000) SlotDebugData { name: "", ty: UInt<54> }, + rhs: StatePartIndex(1392), // (0x40000000000000) SlotDebugData { name: "", ty: UInt<55> }, + }, + 3385: Shl { + dest: StatePartIndex(1394), // (0x1e0001234100000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1393), // (0x7800048d040000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 3386: Or { + dest: StatePartIndex(1395), // (0x1e0001234100001) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1291), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1394), // (0x1e0001234100000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 3387: CastToUInt { + dest: StatePartIndex(1396), // (0x1e0001234100001) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(1395), // (0x1e0001234100001) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 3388: Copy { + dest: StatePartIndex(1397), // (0x1e0001234100001) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1396), // (0x1e0001234100001) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: instruction.rs:477:1 + 3389: BranchIfSmallNeImmediate { + target: 3391, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 3390: Copy { + dest: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1397), // (0x1e0001234100001) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + // at: reg_alloc.rs:184:29 + 3391: BranchIfSmallNeImmediate { + target: 3395, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3392: BranchIfSmallNeImmediate { + target: 3395, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3393: Copy { + dest: StatePartIndex(1398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3394: Copy { + dest: StatePartIndex(1399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3395: BranchIfSmallNeImmediate { + target: 3398, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3396: Copy { + dest: StatePartIndex(1398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3397: Copy { + dest: StatePartIndex(1399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3398: Shl { + dest: StatePartIndex(1443), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1399), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3399: Or { + dest: StatePartIndex(1444), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1443), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3400: Copy { + dest: StatePartIndex(1441), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1444), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3401: Copy { + dest: StatePartIndex(1442), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1446), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3402: Copy { + dest: StatePartIndex(1438), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1441), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3403: Copy { + dest: StatePartIndex(1439), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1442), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3404: Copy { + dest: StatePartIndex(1440), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1468), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3405: Copy { + dest: StatePartIndex(1431), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(103), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3406: Copy { + dest: StatePartIndex(1432), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3407: Copy { + dest: StatePartIndex(1433), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1438), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3408: Copy { + dest: StatePartIndex(1434), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1439), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3409: Copy { + dest: StatePartIndex(1435), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1440), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3410: Copy { + dest: StatePartIndex(1436), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1469), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3411: Copy { + dest: StatePartIndex(1437), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1470), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3412: Copy { + dest: StatePartIndex(1423), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1431), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3413: Copy { + dest: StatePartIndex(1424), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1432), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3414: Copy { + dest: StatePartIndex(1425), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1433), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3415: Copy { + dest: StatePartIndex(1426), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1434), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3416: Copy { + dest: StatePartIndex(1427), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1435), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3417: Copy { + dest: StatePartIndex(1428), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1436), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3418: Copy { + dest: StatePartIndex(1429), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1437), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3419: Copy { + dest: StatePartIndex(1430), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(113), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3420: Copy { + dest: StatePartIndex(1414), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1423), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3421: Copy { + dest: StatePartIndex(1415), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1424), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3422: Copy { + dest: StatePartIndex(1416), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1425), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3423: Copy { + dest: StatePartIndex(1417), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1426), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3424: Copy { + dest: StatePartIndex(1418), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1427), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3425: Copy { + dest: StatePartIndex(1419), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1428), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3426: Copy { + dest: StatePartIndex(1420), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1429), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3427: Copy { + dest: StatePartIndex(1421), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1430), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3428: Copy { + dest: StatePartIndex(1422), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(114), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + }, + 3429: Copy { + dest: StatePartIndex(1404), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3430: Copy { + dest: StatePartIndex(1405), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1414), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 3431: Copy { + dest: StatePartIndex(1406), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1415), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 3432: Copy { + dest: StatePartIndex(1407), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1416), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 3433: Copy { + dest: StatePartIndex(1408), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1417), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 3434: Copy { + dest: StatePartIndex(1409), // (0x4) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1418), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 3435: Copy { + dest: StatePartIndex(1410), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1419), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 3436: Copy { + dest: StatePartIndex(1411), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1420), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 3437: Copy { + dest: StatePartIndex(1412), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1421), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3438: Copy { + dest: StatePartIndex(1413), // (0xf) SlotDebugData { name: ".1.lut", ty: UInt<4> }, + src: StatePartIndex(1422), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + }, + 3439: Shl { + dest: StatePartIndex(1471), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1406), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 3440: Or { + dest: StatePartIndex(1472), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(1405), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(1471), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3441: Shl { + dest: StatePartIndex(1473), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1408), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 3442: Or { + dest: StatePartIndex(1474), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1407), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1473), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 3443: Shl { + dest: StatePartIndex(1475), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1409), // (0x4) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 3444: Or { + dest: StatePartIndex(1476), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1474), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1475), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 3445: Shl { + dest: StatePartIndex(1477), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1476), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 3446: Or { + dest: StatePartIndex(1478), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(1472), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(1477), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + }, + 3447: Shl { + dest: StatePartIndex(1479), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1410), // (0x1234) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 3448: Or { + dest: StatePartIndex(1480), // (0x48d040000) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(1478), // (0x40000) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(1479), // (0x48d000000) SlotDebugData { name: "", ty: UInt<47> }, + }, + 3449: CastToUInt { + dest: StatePartIndex(1481), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1411), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 3450: Shl { + dest: StatePartIndex(1482), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1481), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 3451: Or { + dest: StatePartIndex(1483), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1480), // (0x48d040000) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(1482), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3452: Or { + dest: StatePartIndex(1485), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1483), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1484), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3453: Copy { + dest: StatePartIndex(1486), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1412), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3454: Shl { + dest: StatePartIndex(1487), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1486), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 3455: Or { + dest: StatePartIndex(1488), // (0x48d040000) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(1485), // (0x48d040000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1487), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 3456: Shl { + dest: StatePartIndex(1489), // (0x78000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1413), // (0xf) SlotDebugData { name: ".1.lut", ty: UInt<4> }, + rhs: 51, + }, + 3457: Or { + dest: StatePartIndex(1490), // (0x7800048d040000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(1488), // (0x48d040000) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(1489), // (0x78000000000000) SlotDebugData { name: "", ty: UInt<55> }, + }, + 3458: Shl { + dest: StatePartIndex(1491), // (0x1e0001234100000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1490), // (0x7800048d040000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 3459: Or { + dest: StatePartIndex(1492), // (0x1e0001234100002) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(1404), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1491), // (0x1e0001234100000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 3460: CastToUInt { + dest: StatePartIndex(1493), // (0x1e0001234100002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(1492), // (0x1e0001234100002) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 3461: Copy { + dest: StatePartIndex(1494), // (0x1e0001234100002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1493), // (0x1e0001234100002) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: instruction.rs:477:1 + 3462: BranchIfSmallNeImmediate { + target: 3464, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 3463: Copy { + dest: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1494), // (0x1e0001234100002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3464: AndBigWithSmallImmediate { + dest: StatePartIndex(131), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3465: Copy { + dest: StatePartIndex(1134), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3466: SliceInt { + dest: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(1134), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 3467: SliceInt { + dest: StatePartIndex(1136), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 3468: SliceInt { + dest: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(1136), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 3469: SliceInt { + dest: StatePartIndex(1138), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 3470: SliceInt { + dest: StatePartIndex(1140), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 3471: SliceInt { + dest: StatePartIndex(1141), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1140), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3472: Copy { + dest: StatePartIndex(1139), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1141), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3473: SliceInt { + dest: StatePartIndex(1145), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 3474: SliceInt { + dest: StatePartIndex(1146), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1145), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3475: SliceInt { + dest: StatePartIndex(1147), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1145), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3476: SliceInt { + dest: StatePartIndex(1148), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1145), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3477: Copy { + dest: StatePartIndex(1142), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1146), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3478: Copy { + dest: StatePartIndex(1143), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1147), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3479: Copy { + dest: StatePartIndex(1144), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1148), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3480: SliceInt { + dest: StatePartIndex(1149), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 3481: SliceInt { + dest: StatePartIndex(1150), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1137), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 3482: CastToSInt { + dest: StatePartIndex(1151), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1150), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3483: Copy { + dest: StatePartIndex(1127), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1138), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 3484: Copy { + dest: StatePartIndex(1128), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1139), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3485: Copy { + dest: StatePartIndex(1129), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1142), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3486: Copy { + dest: StatePartIndex(1130), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1143), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3487: Copy { + dest: StatePartIndex(1131), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1144), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3488: Copy { + dest: StatePartIndex(1132), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1149), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3489: Copy { + dest: StatePartIndex(1133), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1151), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3490: SliceInt { + dest: StatePartIndex(1152), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1136), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 3491: Copy { + dest: StatePartIndex(1153), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1152), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 3492: Copy { + dest: StatePartIndex(1119), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1127), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3493: Copy { + dest: StatePartIndex(1120), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1128), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3494: Copy { + dest: StatePartIndex(1121), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1129), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3495: Copy { + dest: StatePartIndex(1122), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1130), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3496: Copy { + dest: StatePartIndex(1123), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1131), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3497: Copy { + dest: StatePartIndex(1124), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1132), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3498: Copy { + dest: StatePartIndex(1125), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1133), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3499: Copy { + dest: StatePartIndex(1126), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1153), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3500: SliceInt { + dest: StatePartIndex(1154), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 3501: Copy { + dest: StatePartIndex(1155), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1154), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3502: SliceInt { + dest: StatePartIndex(1156), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 3503: Copy { + dest: StatePartIndex(1157), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1156), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3504: SliceInt { + dest: StatePartIndex(1158), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 3505: Copy { + dest: StatePartIndex(1159), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1158), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3506: SliceInt { + dest: StatePartIndex(1160), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 3507: Copy { + dest: StatePartIndex(1161), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1160), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3508: Copy { + dest: StatePartIndex(1107), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1119), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3509: Copy { + dest: StatePartIndex(1108), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1120), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3510: Copy { + dest: StatePartIndex(1109), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1121), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3511: Copy { + dest: StatePartIndex(1110), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1122), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3512: Copy { + dest: StatePartIndex(1111), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1123), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3513: Copy { + dest: StatePartIndex(1112), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1124), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3514: Copy { + dest: StatePartIndex(1113), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1125), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3515: Copy { + dest: StatePartIndex(1114), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1126), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3516: Copy { + dest: StatePartIndex(1115), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(1155), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3517: Copy { + dest: StatePartIndex(1116), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(1157), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3518: Copy { + dest: StatePartIndex(1117), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(1159), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3519: Copy { + dest: StatePartIndex(1118), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(1161), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: instruction.rs:477:1 + 3520: AndBigWithSmallImmediate { + dest: StatePartIndex(132), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(1114), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3521: SliceInt { + dest: StatePartIndex(1171), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1135), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 3522: Copy { + dest: StatePartIndex(1162), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1119), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3523: Copy { + dest: StatePartIndex(1163), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1120), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3524: Copy { + dest: StatePartIndex(1164), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1121), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3525: Copy { + dest: StatePartIndex(1165), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1122), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3526: Copy { + dest: StatePartIndex(1166), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1123), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3527: Copy { + dest: StatePartIndex(1167), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1124), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3528: Copy { + dest: StatePartIndex(1168), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1125), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3529: Copy { + dest: StatePartIndex(1169), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1126), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3530: Copy { + dest: StatePartIndex(1170), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(1171), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: instruction.rs:477:1 + 3531: AndBigWithSmallImmediate { + dest: StatePartIndex(133), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(1169), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3532: Copy { + dest: StatePartIndex(1495), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3533: Copy { + dest: StatePartIndex(1496), // (0x1e0001234000000) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(1106), // (0x1e0001234000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3534: Copy { + dest: StatePartIndex(1497), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(1496), // (0x1e0001234000000) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3535: Shl { + dest: StatePartIndex(1498), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + lhs: StatePartIndex(1497), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 2, + }, + 3536: Or { + dest: StatePartIndex(1499), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + lhs: StatePartIndex(1495), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1498), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + }, + 3537: CastToUInt { + dest: StatePartIndex(1500), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(1499), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + dest_width: 59, + }, + 3538: Copy { + dest: StatePartIndex(1501), // (0x7800048d0000000) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1500), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: unit.rs:127:1 + 3539: BranchIfSmallNeImmediate { + target: 3541, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 3540: Copy { + dest: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1501), // (0x7800048d0000000) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + // at: reg_alloc.rs:184:29 + 3541: BranchIfSmallNeImmediate { + target: 3545, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3542: BranchIfSmallNeImmediate { + target: 3545, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3543: Copy { + dest: StatePartIndex(1604), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3544: Copy { + dest: StatePartIndex(1605), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3545: BranchIfSmallNeImmediate { + target: 3548, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3546: Copy { + dest: StatePartIndex(1604), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3547: Copy { + dest: StatePartIndex(1605), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3548: Shl { + dest: StatePartIndex(1633), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1605), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3549: Or { + dest: StatePartIndex(1634), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1604), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1633), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3550: Copy { + dest: StatePartIndex(1632), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1634), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3551: Copy { + dest: StatePartIndex(1629), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1632), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3552: Copy { + dest: StatePartIndex(1630), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3553: Copy { + dest: StatePartIndex(1631), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1656), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3554: Copy { + dest: StatePartIndex(1622), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(118), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 3555: Copy { + dest: StatePartIndex(1623), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3556: Copy { + dest: StatePartIndex(1624), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1629), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3557: Copy { + dest: StatePartIndex(1625), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1630), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3558: Copy { + dest: StatePartIndex(1626), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1631), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3559: Copy { + dest: StatePartIndex(1627), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1657), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3560: Copy { + dest: StatePartIndex(1628), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1658), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3561: Copy { + dest: StatePartIndex(1615), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1622), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 3562: Copy { + dest: StatePartIndex(1616), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1623), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3563: Copy { + dest: StatePartIndex(1617), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1624), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3564: Copy { + dest: StatePartIndex(1618), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1625), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3565: Copy { + dest: StatePartIndex(1619), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1626), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3566: Copy { + dest: StatePartIndex(1620), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1627), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3567: Copy { + dest: StatePartIndex(1621), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1628), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3568: Copy { + dest: StatePartIndex(1607), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3569: Copy { + dest: StatePartIndex(1608), // (0x0) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1615), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 3570: Copy { + dest: StatePartIndex(1609), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1616), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3571: Copy { + dest: StatePartIndex(1610), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1617), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3572: Copy { + dest: StatePartIndex(1611), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1618), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3573: Copy { + dest: StatePartIndex(1612), // (0x4) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1619), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3574: Copy { + dest: StatePartIndex(1613), // (0x1234) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1620), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3575: Copy { + dest: StatePartIndex(1614), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1621), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3576: Shl { + dest: StatePartIndex(1659), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1609), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 3577: Or { + dest: StatePartIndex(1660), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1608), // (0x0) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(1659), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 3578: Shl { + dest: StatePartIndex(1661), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1611), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 3579: Or { + dest: StatePartIndex(1662), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1610), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1661), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 3580: Shl { + dest: StatePartIndex(1663), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1612), // (0x4) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 3581: Or { + dest: StatePartIndex(1664), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1662), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1663), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 3582: Shl { + dest: StatePartIndex(1665), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1664), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 3583: Or { + dest: StatePartIndex(1666), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1660), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(1665), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + }, + 3584: Shl { + dest: StatePartIndex(1667), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1613), // (0x1234) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 3585: Or { + dest: StatePartIndex(1668), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1666), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(1667), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3586: CastToUInt { + dest: StatePartIndex(1669), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1614), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 3587: Shl { + dest: StatePartIndex(1670), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1669), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 3588: Or { + dest: StatePartIndex(1671), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1668), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1670), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 3589: Or { + dest: StatePartIndex(1673), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1671), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(1672), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 3590: Shl { + dest: StatePartIndex(1674), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1673), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 3591: Or { + dest: StatePartIndex(1675), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1607), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1674), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + 3592: CastToUInt { + dest: StatePartIndex(1676), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1675), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 3593: Copy { + dest: StatePartIndex(1677), // (0x1234100001) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1676), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:504:1 + 3594: BranchIfSmallNeImmediate { + target: 3596, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 3595: Copy { + dest: StatePartIndex(1502), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1677), // (0x1234100001) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 3596: AndBigWithSmallImmediate { + dest: StatePartIndex(134), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(1502), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3597: Copy { + dest: StatePartIndex(1517), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1502), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 3598: SliceInt { + dest: StatePartIndex(1518), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1517), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 3599: SliceInt { + dest: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1518), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 3600: SliceInt { + dest: StatePartIndex(1520), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 3601: SliceInt { + dest: StatePartIndex(1522), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 3602: SliceInt { + dest: StatePartIndex(1523), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1522), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3603: Copy { + dest: StatePartIndex(1521), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1523), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3604: SliceInt { + dest: StatePartIndex(1527), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 3605: SliceInt { + dest: StatePartIndex(1528), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1527), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3606: SliceInt { + dest: StatePartIndex(1529), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1527), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3607: SliceInt { + dest: StatePartIndex(1530), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1527), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3608: Copy { + dest: StatePartIndex(1524), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1528), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3609: Copy { + dest: StatePartIndex(1525), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1529), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3610: Copy { + dest: StatePartIndex(1526), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1530), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3611: SliceInt { + dest: StatePartIndex(1531), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 3612: SliceInt { + dest: StatePartIndex(1532), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1519), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 3613: CastToSInt { + dest: StatePartIndex(1533), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1532), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3614: Copy { + dest: StatePartIndex(1510), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1520), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3615: Copy { + dest: StatePartIndex(1511), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1521), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3616: Copy { + dest: StatePartIndex(1512), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1524), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3617: Copy { + dest: StatePartIndex(1513), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1525), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3618: Copy { + dest: StatePartIndex(1514), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1526), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3619: Copy { + dest: StatePartIndex(1515), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1531), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3620: Copy { + dest: StatePartIndex(1516), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1533), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3621: Copy { + dest: StatePartIndex(1503), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1510), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 3622: Copy { + dest: StatePartIndex(1504), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1511), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3623: Copy { + dest: StatePartIndex(1505), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1512), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3624: Copy { + dest: StatePartIndex(1506), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1513), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3625: Copy { + dest: StatePartIndex(1507), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1514), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3626: Copy { + dest: StatePartIndex(1508), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1515), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3627: Copy { + dest: StatePartIndex(1509), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1516), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3628: Copy { + dest: StatePartIndex(1678), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3629: Copy { + dest: StatePartIndex(1679), // (0x1234100000) SlotDebugData { name: ".1", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1502), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 3630: Copy { + dest: StatePartIndex(1680), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1679), // (0x1234100000) SlotDebugData { name: ".1", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 3631: Shl { + dest: StatePartIndex(1681), // (0x48d0400000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1680), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + rhs: 2, + }, + 3632: Or { + dest: StatePartIndex(1682), // (0x48d0400001) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1678), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1681), // (0x48d0400000) SlotDebugData { name: "", ty: UInt<52> }, + }, + 3633: CastToUInt { + dest: StatePartIndex(1683), // (0x48d0400001) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(1682), // (0x48d0400001) SlotDebugData { name: "", ty: UInt<52> }, + dest_width: 59, + }, + 3634: Copy { + dest: StatePartIndex(1684), // (0x48d0400001) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1683), // (0x48d0400001) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: unit.rs:127:1 + 3635: BranchIfSmallNeImmediate { + target: 3637, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 3636: Copy { + dest: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1684), // (0x48d0400001) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + // at: reg_alloc.rs:184:29 + 3637: BranchIfSmallNeImmediate { + target: 3641, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 3638: BranchIfSmallNeImmediate { + target: 3641, + lhs: StatePartIndex(113), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 3639: Copy { + dest: StatePartIndex(1770), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(879), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3640: Copy { + dest: StatePartIndex(1771), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(880), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 3641: BranchIfSmallNeImmediate { + target: 3644, + lhs: StatePartIndex(110), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 3642: Copy { + dest: StatePartIndex(1770), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(792), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 3643: Copy { + dest: StatePartIndex(1771), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(793), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 3644: Shl { + dest: StatePartIndex(1792), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1771), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 3645: Or { + dest: StatePartIndex(1793), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(1770), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_0_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(1792), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3646: Copy { + dest: StatePartIndex(1791), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1793), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3647: Copy { + dest: StatePartIndex(1788), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1791), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3648: Copy { + dest: StatePartIndex(1789), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3649: Copy { + dest: StatePartIndex(1790), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1815), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3650: Copy { + dest: StatePartIndex(1781), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(174), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 3651: Copy { + dest: StatePartIndex(1782), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(764), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 3652: Copy { + dest: StatePartIndex(1783), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1788), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3653: Copy { + dest: StatePartIndex(1784), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1789), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3654: Copy { + dest: StatePartIndex(1785), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1790), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3655: Copy { + dest: StatePartIndex(1786), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1816), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3656: Copy { + dest: StatePartIndex(1787), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1817), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3657: Copy { + dest: StatePartIndex(1773), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3658: Copy { + dest: StatePartIndex(1774), // (0x0) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1781), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 3659: Copy { + dest: StatePartIndex(1775), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + src: StatePartIndex(1782), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3660: Copy { + dest: StatePartIndex(1776), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + src: StatePartIndex(1783), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3661: Copy { + dest: StatePartIndex(1777), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + src: StatePartIndex(1784), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3662: Copy { + dest: StatePartIndex(1778), // (0x4) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + src: StatePartIndex(1785), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3663: Copy { + dest: StatePartIndex(1779), // (0x1234) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + src: StatePartIndex(1786), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3664: Copy { + dest: StatePartIndex(1780), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1787), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3665: Shl { + dest: StatePartIndex(1818), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1775), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 3666: Or { + dest: StatePartIndex(1819), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(1774), // (0x0) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(1818), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 3667: Shl { + dest: StatePartIndex(1820), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1777), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 3668: Or { + dest: StatePartIndex(1821), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(1776), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(1820), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 3669: Shl { + dest: StatePartIndex(1822), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1778), // (0x4) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 3670: Or { + dest: StatePartIndex(1823), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(1821), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(1822), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + }, + 3671: Shl { + dest: StatePartIndex(1824), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1823), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 3672: Or { + dest: StatePartIndex(1825), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(1819), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(1824), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + }, + 3673: Shl { + dest: StatePartIndex(1826), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1779), // (0x1234) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 3674: Or { + dest: StatePartIndex(1827), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(1825), // (0x80000) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(1826), // (0x91a000000) SlotDebugData { name: "", ty: UInt<48> }, + }, + 3675: CastToUInt { + dest: StatePartIndex(1828), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1780), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 3676: Shl { + dest: StatePartIndex(1829), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1828), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 3677: Or { + dest: StatePartIndex(1830), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1827), // (0x91a080000) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(1829), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 3678: Or { + dest: StatePartIndex(1832), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(1830), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(1831), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 3679: Shl { + dest: StatePartIndex(1833), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1832), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 3680: Or { + dest: StatePartIndex(1834), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(1773), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1833), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + }, + 3681: CastToUInt { + dest: StatePartIndex(1835), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1834), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 3682: Copy { + dest: StatePartIndex(1836), // (0x1234100001) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1835), // (0x1234100001) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:539:1 + 3683: BranchIfSmallNeImmediate { + target: 3685, + lhs: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 3684: Copy { + dest: StatePartIndex(1685), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1836), // (0x1234100001) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 3685: AndBigWithSmallImmediate { + dest: StatePartIndex(135), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(1685), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3686: Copy { + dest: StatePartIndex(1693), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1685), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 3687: SliceInt { + dest: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1693), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 3688: SliceInt { + dest: StatePartIndex(1695), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 3689: SliceInt { + dest: StatePartIndex(1697), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 3690: SliceInt { + dest: StatePartIndex(1698), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1697), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3691: Copy { + dest: StatePartIndex(1696), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1698), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3692: SliceInt { + dest: StatePartIndex(1702), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 3693: SliceInt { + dest: StatePartIndex(1703), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1702), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3694: SliceInt { + dest: StatePartIndex(1704), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1702), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3695: SliceInt { + dest: StatePartIndex(1705), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1702), // (0x4000) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3696: Copy { + dest: StatePartIndex(1699), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1703), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3697: Copy { + dest: StatePartIndex(1700), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1704), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3698: Copy { + dest: StatePartIndex(1701), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1705), // (0x4) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3699: SliceInt { + dest: StatePartIndex(1706), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 3700: SliceInt { + dest: StatePartIndex(1707), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1694), // (0x91a080000) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 3701: CastToSInt { + dest: StatePartIndex(1708), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1707), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3702: Copy { + dest: StatePartIndex(1686), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1695), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3703: Copy { + dest: StatePartIndex(1687), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1696), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3704: Copy { + dest: StatePartIndex(1688), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1699), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3705: Copy { + dest: StatePartIndex(1689), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1700), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3706: Copy { + dest: StatePartIndex(1690), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1701), // (0x4) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3707: Copy { + dest: StatePartIndex(1691), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1706), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3708: Copy { + dest: StatePartIndex(1692), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1708), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3709: Copy { + dest: StatePartIndex(1837), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 3710: Copy { + dest: StatePartIndex(1838), // (0x1234100000) SlotDebugData { name: ".1", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1685), // (0x1234100000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 3711: Copy { + dest: StatePartIndex(1839), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1838), // (0x1234100000) SlotDebugData { name: ".1", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 3712: Shl { + dest: StatePartIndex(1840), // (0x48d0400000) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1839), // (0x1234100000) SlotDebugData { name: "", ty: UInt<50> }, + rhs: 2, + }, + 3713: Or { + dest: StatePartIndex(1841), // (0x48d0400002) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(1837), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(1840), // (0x48d0400000) SlotDebugData { name: "", ty: UInt<52> }, + }, + 3714: CastToUInt { + dest: StatePartIndex(1842), // (0x48d0400002) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(1841), // (0x48d0400002) SlotDebugData { name: "", ty: UInt<52> }, + dest_width: 59, + }, + 3715: Copy { + dest: StatePartIndex(1843), // (0x48d0400002) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1842), // (0x48d0400002) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: unit.rs:127:1 + 3716: BranchIfSmallNeImmediate { + target: 3718, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 3717: Copy { + dest: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(1843), // (0x48d0400002) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 3718: AndBigWithSmallImmediate { + dest: StatePartIndex(125), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3719: Copy { + dest: StatePartIndex(981), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 3720: SliceInt { + dest: StatePartIndex(982), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(981), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 57, + }, + 3721: Copy { + dest: StatePartIndex(983), // (0x1e0001234000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(982), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 3722: AndBigWithSmallImmediate { + dest: StatePartIndex(126), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(983), // (0x1e0001234000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3723: Copy { + dest: StatePartIndex(1011), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(983), // (0x1e0001234000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3724: SliceInt { + dest: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(1011), // (0x1e0001234000000) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 3725: SliceInt { + dest: StatePartIndex(1013), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 3726: SliceInt { + dest: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(1013), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 3727: SliceInt { + dest: StatePartIndex(1015), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 3728: SliceInt { + dest: StatePartIndex(1017), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 3729: SliceInt { + dest: StatePartIndex(1018), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1017), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3730: Copy { + dest: StatePartIndex(1016), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1018), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3731: SliceInt { + dest: StatePartIndex(1022), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 3732: SliceInt { + dest: StatePartIndex(1023), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1022), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3733: SliceInt { + dest: StatePartIndex(1024), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1022), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3734: SliceInt { + dest: StatePartIndex(1025), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1022), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3735: Copy { + dest: StatePartIndex(1019), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1023), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3736: Copy { + dest: StatePartIndex(1020), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1024), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3737: Copy { + dest: StatePartIndex(1021), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1025), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3738: SliceInt { + dest: StatePartIndex(1026), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 3739: SliceInt { + dest: StatePartIndex(1027), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1014), // (0x48d000000) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 3740: CastToSInt { + dest: StatePartIndex(1028), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1027), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3741: Copy { + dest: StatePartIndex(1004), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1015), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 3742: Copy { + dest: StatePartIndex(1005), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1016), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3743: Copy { + dest: StatePartIndex(1006), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1019), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3744: Copy { + dest: StatePartIndex(1007), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1020), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3745: Copy { + dest: StatePartIndex(1008), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1021), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3746: Copy { + dest: StatePartIndex(1009), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1026), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3747: Copy { + dest: StatePartIndex(1010), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1028), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3748: SliceInt { + dest: StatePartIndex(1029), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(1013), // (0x48d000000) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 3749: Copy { + dest: StatePartIndex(1030), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1029), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 3750: Copy { + dest: StatePartIndex(996), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(1004), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3751: Copy { + dest: StatePartIndex(997), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1005), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3752: Copy { + dest: StatePartIndex(998), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1006), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3753: Copy { + dest: StatePartIndex(999), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1007), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3754: Copy { + dest: StatePartIndex(1000), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1008), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3755: Copy { + dest: StatePartIndex(1001), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1009), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3756: Copy { + dest: StatePartIndex(1002), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1010), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3757: Copy { + dest: StatePartIndex(1003), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1030), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3758: SliceInt { + dest: StatePartIndex(1031), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 3759: Copy { + dest: StatePartIndex(1032), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1031), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3760: SliceInt { + dest: StatePartIndex(1033), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 3761: Copy { + dest: StatePartIndex(1034), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1033), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3762: SliceInt { + dest: StatePartIndex(1035), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 3763: Copy { + dest: StatePartIndex(1036), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1035), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3764: SliceInt { + dest: StatePartIndex(1037), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 3765: Copy { + dest: StatePartIndex(1038), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1037), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3766: Copy { + dest: StatePartIndex(984), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(996), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3767: Copy { + dest: StatePartIndex(985), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(997), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3768: Copy { + dest: StatePartIndex(986), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(998), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3769: Copy { + dest: StatePartIndex(987), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(999), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3770: Copy { + dest: StatePartIndex(988), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1000), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3771: Copy { + dest: StatePartIndex(989), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1001), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3772: Copy { + dest: StatePartIndex(990), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1002), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3773: Copy { + dest: StatePartIndex(991), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1003), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3774: Copy { + dest: StatePartIndex(992), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(1032), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3775: Copy { + dest: StatePartIndex(993), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(1034), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3776: Copy { + dest: StatePartIndex(994), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(1036), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 3777: Copy { + dest: StatePartIndex(995), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(1038), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 3778: AndBigWithSmallImmediate { + dest: StatePartIndex(127), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(991), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3779: SliceInt { + dest: StatePartIndex(1048), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1012), // (0x7800048d000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 3780: Copy { + dest: StatePartIndex(1039), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(996), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3781: Copy { + dest: StatePartIndex(1040), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(997), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3782: Copy { + dest: StatePartIndex(1041), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(998), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3783: Copy { + dest: StatePartIndex(1042), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(999), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3784: Copy { + dest: StatePartIndex(1043), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1000), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3785: Copy { + dest: StatePartIndex(1044), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1001), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3786: Copy { + dest: StatePartIndex(1045), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1002), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3787: Copy { + dest: StatePartIndex(1046), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(1003), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3788: Copy { + dest: StatePartIndex(1047), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(1048), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 3789: AndBigWithSmallImmediate { + dest: StatePartIndex(128), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(1046), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3790: SliceInt { + dest: StatePartIndex(1049), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(981), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 50, + }, + 3791: Copy { + dest: StatePartIndex(1050), // (0x1234000000) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(1049), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: unit.rs:127:1 + 3792: AndBigWithSmallImmediate { + dest: StatePartIndex(129), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(1050), // (0x1234000000) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3793: Copy { + dest: StatePartIndex(1065), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1050), // (0x1234000000) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 3794: SliceInt { + dest: StatePartIndex(1066), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1065), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 3795: SliceInt { + dest: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1066), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 3796: SliceInt { + dest: StatePartIndex(1068), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 3797: SliceInt { + dest: StatePartIndex(1070), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 3798: SliceInt { + dest: StatePartIndex(1071), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1070), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3799: Copy { + dest: StatePartIndex(1069), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1071), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3800: SliceInt { + dest: StatePartIndex(1075), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 3801: SliceInt { + dest: StatePartIndex(1076), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1075), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3802: SliceInt { + dest: StatePartIndex(1077), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1075), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3803: SliceInt { + dest: StatePartIndex(1078), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1075), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3804: Copy { + dest: StatePartIndex(1072), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1076), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3805: Copy { + dest: StatePartIndex(1073), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1077), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3806: Copy { + dest: StatePartIndex(1074), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1078), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3807: SliceInt { + dest: StatePartIndex(1079), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 3808: SliceInt { + dest: StatePartIndex(1080), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1067), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 3809: CastToSInt { + dest: StatePartIndex(1081), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1080), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3810: Copy { + dest: StatePartIndex(1058), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1068), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3811: Copy { + dest: StatePartIndex(1059), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1069), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3812: Copy { + dest: StatePartIndex(1060), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1072), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3813: Copy { + dest: StatePartIndex(1061), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1073), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3814: Copy { + dest: StatePartIndex(1062), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1074), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3815: Copy { + dest: StatePartIndex(1063), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1079), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3816: Copy { + dest: StatePartIndex(1064), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1081), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3817: Copy { + dest: StatePartIndex(1051), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1058), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 3818: Copy { + dest: StatePartIndex(1052), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(1059), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3819: Copy { + dest: StatePartIndex(1053), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(1060), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3820: Copy { + dest: StatePartIndex(1054), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(1061), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3821: Copy { + dest: StatePartIndex(1055), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(1062), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3822: Copy { + dest: StatePartIndex(1056), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(1063), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3823: Copy { + dest: StatePartIndex(1057), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(1064), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3824: Copy { + dest: StatePartIndex(1082), // (0x1234000000) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(1049), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: unit.rs:127:1 + 3825: AndBigWithSmallImmediate { + dest: StatePartIndex(130), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(1082), // (0x1234000000) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3826: Copy { + dest: StatePartIndex(1090), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(1082), // (0x1234000000) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 3827: SliceInt { + dest: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(1090), // (0x1234000000) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 3828: SliceInt { + dest: StatePartIndex(1092), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 3829: SliceInt { + dest: StatePartIndex(1094), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 3830: SliceInt { + dest: StatePartIndex(1095), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1094), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3831: Copy { + dest: StatePartIndex(1093), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1095), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3832: SliceInt { + dest: StatePartIndex(1099), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 3833: SliceInt { + dest: StatePartIndex(1100), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1099), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3834: SliceInt { + dest: StatePartIndex(1101), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1099), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3835: SliceInt { + dest: StatePartIndex(1102), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1099), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3836: Copy { + dest: StatePartIndex(1096), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(1100), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3837: Copy { + dest: StatePartIndex(1097), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1101), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3838: Copy { + dest: StatePartIndex(1098), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(1102), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3839: SliceInt { + dest: StatePartIndex(1103), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 3840: SliceInt { + dest: StatePartIndex(1104), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(1091), // (0x91a000000) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 3841: CastToSInt { + dest: StatePartIndex(1105), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(1104), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3842: Copy { + dest: StatePartIndex(1083), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(1092), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3843: Copy { + dest: StatePartIndex(1084), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(1093), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3844: Copy { + dest: StatePartIndex(1085), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(1096), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3845: Copy { + dest: StatePartIndex(1086), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(1097), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3846: Copy { + dest: StatePartIndex(1087), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(1098), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3847: Copy { + dest: StatePartIndex(1088), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(1103), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3848: Copy { + dest: StatePartIndex(1089), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(1105), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3849: Copy { + dest: StatePartIndex(1844), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3850: Copy { + dest: StatePartIndex(1845), // (0x7800048d0000000) SlotDebugData { name: ".1", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(980), // (0x7800048d0000000) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 3851: Copy { + dest: StatePartIndex(1846), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(1845), // (0x7800048d0000000) SlotDebugData { name: ".1", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 3852: Shl { + dest: StatePartIndex(1847), // (0xf000091a0000000) SlotDebugData { name: "", ty: UInt<60> }, + lhs: StatePartIndex(1846), // (0x7800048d0000000) SlotDebugData { name: "", ty: UInt<59> }, + rhs: 1, + }, + 3853: Or { + dest: StatePartIndex(1848), // (0xf000091a0000001) SlotDebugData { name: "", ty: UInt<60> }, + lhs: StatePartIndex(1844), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(1847), // (0xf000091a0000000) SlotDebugData { name: "", ty: UInt<60> }, + }, + 3854: CastToUInt { + dest: StatePartIndex(1849), // (0xf000091a0000001) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(1848), // (0xf000091a0000001) SlotDebugData { name: "", ty: UInt<60> }, + dest_width: 60, + }, + 3855: Copy { + dest: StatePartIndex(1850), // (0xf000091a0000001) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(1849), // (0xf000091a0000001) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:159:9 + 3856: BranchIfSmallNeImmediate { + target: 3859, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 3857: BranchIfSmallNeImmediate { + target: 3859, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:167:17 + 3858: Copy { + dest: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[0]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(1850), // (0xf000091a0000001) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + // at: reg_alloc.rs:75:24 + 3859: AndBigWithSmallImmediate { + dest: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[0]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:314:25 + 3860: BranchIfSmallNeImmediate { + target: 3863, + lhs: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + 3861: Copy { + dest: StatePartIndex(3587), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 3862: Copy { + dest: StatePartIndex(4391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 3863: Copy { + dest: StatePartIndex(505), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[0]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + 3864: SliceInt { + dest: StatePartIndex(506), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(505), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 3865: Copy { + dest: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(506), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: reg_alloc.rs:75:24 + 3866: AndBigWithSmallImmediate { + dest: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3867: Copy { + dest: StatePartIndex(508), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 3868: SliceInt { + dest: StatePartIndex(509), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(508), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 57, + }, + 3869: Copy { + dest: StatePartIndex(510), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(509), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:75:24 + 3870: AndBigWithSmallImmediate { + dest: StatePartIndex(96), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(510), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3871: Copy { + dest: StatePartIndex(538), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(510), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3872: SliceInt { + dest: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(538), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 3873: SliceInt { + dest: StatePartIndex(540), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 3874: SliceInt { + dest: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(540), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 3875: SliceInt { + dest: StatePartIndex(542), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 3876: SliceInt { + dest: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 3877: SliceInt { + dest: StatePartIndex(545), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3878: Copy { + dest: StatePartIndex(543), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(545), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3879: SliceInt { + dest: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 3880: SliceInt { + dest: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3881: SliceInt { + dest: StatePartIndex(551), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3882: SliceInt { + dest: StatePartIndex(552), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(549), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3883: Copy { + dest: StatePartIndex(546), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(550), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3884: Copy { + dest: StatePartIndex(547), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(551), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3885: Copy { + dest: StatePartIndex(548), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(552), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3886: SliceInt { + dest: StatePartIndex(553), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 3887: SliceInt { + dest: StatePartIndex(554), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(541), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 3888: CastToSInt { + dest: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(554), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3889: Copy { + dest: StatePartIndex(531), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(542), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 3890: Copy { + dest: StatePartIndex(532), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(543), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3891: Copy { + dest: StatePartIndex(533), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(546), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3892: Copy { + dest: StatePartIndex(534), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(547), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3893: Copy { + dest: StatePartIndex(535), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(548), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3894: Copy { + dest: StatePartIndex(536), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(553), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3895: Copy { + dest: StatePartIndex(537), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3896: SliceInt { + dest: StatePartIndex(556), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(540), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 3897: Copy { + dest: StatePartIndex(557), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(556), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 3898: Copy { + dest: StatePartIndex(523), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(531), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3899: Copy { + dest: StatePartIndex(524), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(532), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3900: Copy { + dest: StatePartIndex(525), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(533), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3901: Copy { + dest: StatePartIndex(526), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(534), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3902: Copy { + dest: StatePartIndex(527), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(535), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3903: Copy { + dest: StatePartIndex(528), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(536), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3904: Copy { + dest: StatePartIndex(529), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(537), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3905: Copy { + dest: StatePartIndex(530), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(557), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3906: SliceInt { + dest: StatePartIndex(558), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 3907: Copy { + dest: StatePartIndex(559), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(558), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3908: SliceInt { + dest: StatePartIndex(560), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 3909: Copy { + dest: StatePartIndex(561), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(560), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3910: SliceInt { + dest: StatePartIndex(562), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 3911: Copy { + dest: StatePartIndex(563), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(562), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3912: SliceInt { + dest: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 3913: Copy { + dest: StatePartIndex(565), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3914: Copy { + dest: StatePartIndex(511), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(523), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3915: Copy { + dest: StatePartIndex(512), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(524), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3916: Copy { + dest: StatePartIndex(513), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(525), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3917: Copy { + dest: StatePartIndex(514), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(526), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3918: Copy { + dest: StatePartIndex(515), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(527), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3919: Copy { + dest: StatePartIndex(516), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(528), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3920: Copy { + dest: StatePartIndex(517), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(529), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3921: Copy { + dest: StatePartIndex(518), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(530), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3922: Copy { + dest: StatePartIndex(519), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(559), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 3923: Copy { + dest: StatePartIndex(520), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(561), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 3924: Copy { + dest: StatePartIndex(521), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(563), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 3925: Copy { + dest: StatePartIndex(522), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(565), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:75:24 + 3926: AndBigWithSmallImmediate { + dest: StatePartIndex(97), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(518), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3927: SliceInt { + dest: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(539), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 3928: Copy { + dest: StatePartIndex(566), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(523), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3929: Copy { + dest: StatePartIndex(567), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(524), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3930: Copy { + dest: StatePartIndex(568), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(525), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3931: Copy { + dest: StatePartIndex(569), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(526), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3932: Copy { + dest: StatePartIndex(570), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(527), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 3933: Copy { + dest: StatePartIndex(571), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(528), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 3934: Copy { + dest: StatePartIndex(572), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(529), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 3935: Copy { + dest: StatePartIndex(573), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(530), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3936: Copy { + dest: StatePartIndex(574), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:75:24 + 3937: AndBigWithSmallImmediate { + dest: StatePartIndex(98), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(573), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 3938: Copy { + dest: StatePartIndex(3725), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3939: Copy { + dest: StatePartIndex(3726), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(510), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3940: Copy { + dest: StatePartIndex(3727), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3726), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3941: Shl { + dest: StatePartIndex(3728), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3727), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 3942: Or { + dest: StatePartIndex(3729), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3725), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3728), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 3943: CastToUInt { + dest: StatePartIndex(3730), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3729), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 3944: Copy { + dest: StatePartIndex(3731), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3730), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: unit.rs:127:1 + 3945: BranchIfSmallNeImmediate { + target: 3947, + lhs: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 3946: Copy { + dest: StatePartIndex(3656), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3731), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 3947: AndBigWithSmallImmediate { + dest: StatePartIndex(256), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3656), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 3948: Copy { + dest: StatePartIndex(3657), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3656), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 3949: SliceInt { + dest: StatePartIndex(3658), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3657), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 3950: Copy { + dest: StatePartIndex(3659), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3658), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 3951: AndBigWithSmallImmediate { + dest: StatePartIndex(257), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3659), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 3952: Copy { + dest: StatePartIndex(3687), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3659), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 3953: SliceInt { + dest: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3687), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 3954: SliceInt { + dest: StatePartIndex(3689), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 3955: SliceInt { + dest: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3689), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 3956: SliceInt { + dest: StatePartIndex(3691), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 3957: SliceInt { + dest: StatePartIndex(3693), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 3958: SliceInt { + dest: StatePartIndex(3694), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3693), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 3959: Copy { + dest: StatePartIndex(3692), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3694), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 3960: SliceInt { + dest: StatePartIndex(3698), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 3961: SliceInt { + dest: StatePartIndex(3699), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3698), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 3962: SliceInt { + dest: StatePartIndex(3700), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3698), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 3963: SliceInt { + dest: StatePartIndex(3701), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3698), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 3964: Copy { + dest: StatePartIndex(3695), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3699), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3965: Copy { + dest: StatePartIndex(3696), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3700), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3966: Copy { + dest: StatePartIndex(3697), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3701), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 3967: SliceInt { + dest: StatePartIndex(3702), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 3968: SliceInt { + dest: StatePartIndex(3703), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3690), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 3969: CastToSInt { + dest: StatePartIndex(3704), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3703), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 3970: Copy { + dest: StatePartIndex(3680), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3691), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 3971: Copy { + dest: StatePartIndex(3681), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3692), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 3972: Copy { + dest: StatePartIndex(3682), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3695), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 3973: Copy { + dest: StatePartIndex(3683), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3696), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 3974: Copy { + dest: StatePartIndex(3684), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3697), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 3975: Copy { + dest: StatePartIndex(3685), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3702), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 3976: Copy { + dest: StatePartIndex(3686), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3704), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 3977: SliceInt { + dest: StatePartIndex(3705), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3689), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 3978: Copy { + dest: StatePartIndex(3706), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3705), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 3979: Copy { + dest: StatePartIndex(3672), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3680), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 3980: Copy { + dest: StatePartIndex(3673), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3681), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 3981: Copy { + dest: StatePartIndex(3674), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3682), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 3982: Copy { + dest: StatePartIndex(3675), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3683), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 3983: Copy { + dest: StatePartIndex(3676), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3684), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 3984: Copy { + dest: StatePartIndex(3677), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3685), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 3985: Copy { + dest: StatePartIndex(3678), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3686), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 3986: Copy { + dest: StatePartIndex(3679), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3706), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 3987: SliceInt { + dest: StatePartIndex(3707), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 3988: Copy { + dest: StatePartIndex(3708), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3707), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3989: SliceInt { + dest: StatePartIndex(3709), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 3990: Copy { + dest: StatePartIndex(3710), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3709), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3991: SliceInt { + dest: StatePartIndex(3711), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 3992: Copy { + dest: StatePartIndex(3712), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3711), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3993: SliceInt { + dest: StatePartIndex(3713), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 3994: Copy { + dest: StatePartIndex(3714), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3713), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3995: Copy { + dest: StatePartIndex(3660), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3672), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 3996: Copy { + dest: StatePartIndex(3661), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3673), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 3997: Copy { + dest: StatePartIndex(3662), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3674), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 3998: Copy { + dest: StatePartIndex(3663), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3675), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 3999: Copy { + dest: StatePartIndex(3664), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3676), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4000: Copy { + dest: StatePartIndex(3665), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3677), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4001: Copy { + dest: StatePartIndex(3666), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3678), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4002: Copy { + dest: StatePartIndex(3667), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3679), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4003: Copy { + dest: StatePartIndex(3668), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3708), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4004: Copy { + dest: StatePartIndex(3669), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3710), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4005: Copy { + dest: StatePartIndex(3670), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3712), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4006: Copy { + dest: StatePartIndex(3671), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3714), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 4007: AndBigWithSmallImmediate { + dest: StatePartIndex(258), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3667), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4008: SliceInt { + dest: StatePartIndex(3724), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3688), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 4009: Copy { + dest: StatePartIndex(3715), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3672), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4010: Copy { + dest: StatePartIndex(3716), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3673), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4011: Copy { + dest: StatePartIndex(3717), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3674), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4012: Copy { + dest: StatePartIndex(3718), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3675), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4013: Copy { + dest: StatePartIndex(3719), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3676), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4014: Copy { + dest: StatePartIndex(3720), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3677), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4015: Copy { + dest: StatePartIndex(3721), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3678), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4016: Copy { + dest: StatePartIndex(3722), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3679), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4017: Copy { + dest: StatePartIndex(3723), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3724), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 4018: AndBigWithSmallImmediate { + dest: StatePartIndex(259), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3722), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:314:25 + 4019: BranchIfSmallNeImmediate { + target: 4021, + lhs: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 4020: Copy { + dest: StatePartIndex(3587), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3656), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4021: AndBigWithSmallImmediate { + dest: StatePartIndex(252), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3587), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:308:13 + 4022: BranchIfSmallNeImmediate { + target: 4026, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 4023: BranchIfZero { + target: 4026, + value: StatePartIndex(3586), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 4024: BranchIfSmallNeImmediate { + target: 4026, + lhs: StatePartIndex(252), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:318:25 + 4025: Copy { + dest: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3740), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 4026: Copy { + dest: StatePartIndex(3588), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3587), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4027: SliceInt { + dest: StatePartIndex(3589), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3588), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 4028: Copy { + dest: StatePartIndex(3590), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3589), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:314:25 + 4029: AndBigWithSmallImmediate { + dest: StatePartIndex(253), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3590), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 4030: Copy { + dest: StatePartIndex(3618), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3590), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4031: SliceInt { + dest: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3618), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 4032: SliceInt { + dest: StatePartIndex(3620), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 4033: SliceInt { + dest: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3620), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 4034: SliceInt { + dest: StatePartIndex(3622), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 4035: SliceInt { + dest: StatePartIndex(3624), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 4036: SliceInt { + dest: StatePartIndex(3625), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3624), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4037: Copy { + dest: StatePartIndex(3623), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3625), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4038: SliceInt { + dest: StatePartIndex(3629), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 4039: SliceInt { + dest: StatePartIndex(3630), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3629), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4040: SliceInt { + dest: StatePartIndex(3631), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3629), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4041: SliceInt { + dest: StatePartIndex(3632), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3629), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4042: Copy { + dest: StatePartIndex(3626), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3630), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4043: Copy { + dest: StatePartIndex(3627), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3631), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4044: Copy { + dest: StatePartIndex(3628), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3632), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4045: SliceInt { + dest: StatePartIndex(3633), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 4046: SliceInt { + dest: StatePartIndex(3634), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3621), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 4047: CastToSInt { + dest: StatePartIndex(3635), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3634), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4048: Copy { + dest: StatePartIndex(3611), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3622), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 4049: Copy { + dest: StatePartIndex(3612), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3623), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4050: Copy { + dest: StatePartIndex(3613), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3626), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4051: Copy { + dest: StatePartIndex(3614), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3627), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4052: Copy { + dest: StatePartIndex(3615), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3628), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4053: Copy { + dest: StatePartIndex(3616), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3633), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4054: Copy { + dest: StatePartIndex(3617), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3635), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4055: SliceInt { + dest: StatePartIndex(3636), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3620), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 4056: Copy { + dest: StatePartIndex(3637), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3636), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 4057: Copy { + dest: StatePartIndex(3603), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3611), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4058: Copy { + dest: StatePartIndex(3604), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3612), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4059: Copy { + dest: StatePartIndex(3605), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3613), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4060: Copy { + dest: StatePartIndex(3606), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3614), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4061: Copy { + dest: StatePartIndex(3607), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3615), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4062: Copy { + dest: StatePartIndex(3608), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3616), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4063: Copy { + dest: StatePartIndex(3609), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3617), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4064: Copy { + dest: StatePartIndex(3610), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3637), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4065: SliceInt { + dest: StatePartIndex(3638), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 4066: Copy { + dest: StatePartIndex(3639), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3638), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4067: SliceInt { + dest: StatePartIndex(3640), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 4068: Copy { + dest: StatePartIndex(3641), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3640), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4069: SliceInt { + dest: StatePartIndex(3642), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 4070: Copy { + dest: StatePartIndex(3643), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3642), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4071: SliceInt { + dest: StatePartIndex(3644), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 4072: Copy { + dest: StatePartIndex(3645), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3644), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4073: Copy { + dest: StatePartIndex(3591), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3603), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4074: Copy { + dest: StatePartIndex(3592), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3604), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4075: Copy { + dest: StatePartIndex(3593), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3605), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4076: Copy { + dest: StatePartIndex(3594), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3606), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4077: Copy { + dest: StatePartIndex(3595), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3607), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4078: Copy { + dest: StatePartIndex(3596), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3608), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4079: Copy { + dest: StatePartIndex(3597), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3609), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4080: Copy { + dest: StatePartIndex(3598), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3610), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4081: Copy { + dest: StatePartIndex(3599), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3639), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4082: Copy { + dest: StatePartIndex(3600), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3641), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4083: Copy { + dest: StatePartIndex(3601), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3643), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4084: Copy { + dest: StatePartIndex(3602), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3645), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:314:25 + 4085: AndBigWithSmallImmediate { + dest: StatePartIndex(254), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3598), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4086: SliceInt { + dest: StatePartIndex(3655), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3619), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 4087: Copy { + dest: StatePartIndex(3646), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3603), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4088: Copy { + dest: StatePartIndex(3647), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3604), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4089: Copy { + dest: StatePartIndex(3648), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3605), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4090: Copy { + dest: StatePartIndex(3649), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3606), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4091: Copy { + dest: StatePartIndex(3650), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3607), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4092: Copy { + dest: StatePartIndex(3651), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3608), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4093: Copy { + dest: StatePartIndex(3652), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3609), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4094: Copy { + dest: StatePartIndex(3653), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3610), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4095: Copy { + dest: StatePartIndex(3654), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3655), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:314:25 + 4096: AndBigWithSmallImmediate { + dest: StatePartIndex(255), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3653), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4097: Copy { + dest: StatePartIndex(3741), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4098: Copy { + dest: StatePartIndex(3742), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3590), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4099: Copy { + dest: StatePartIndex(3743), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3742), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4100: Shl { + dest: StatePartIndex(3744), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3743), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 4101: Or { + dest: StatePartIndex(3745), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3741), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3744), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 4102: CastToUInt { + dest: StatePartIndex(3746), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3745), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 4103: Copy { + dest: StatePartIndex(3747), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3746), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: reg_alloc.rs:308:13 + 4104: BranchIfSmallNeImmediate { + target: 4108, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 4105: BranchIfZero { + target: 4108, + value: StatePartIndex(3586), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 4106: BranchIfSmallNeImmediate { + target: 4108, + lhs: StatePartIndex(252), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:316:25 + 4107: Copy { + dest: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3747), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: unit.rs:127:1 + 4108: BranchIfSmallNeImmediate { + target: 4110, + lhs: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 4109: Copy { + dest: StatePartIndex(4460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3731), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4110: AndBigWithSmallImmediate { + dest: StatePartIndex(307), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4111: Copy { + dest: StatePartIndex(4461), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4112: SliceInt { + dest: StatePartIndex(4462), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4461), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 4113: Copy { + dest: StatePartIndex(4463), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4462), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 4114: AndBigWithSmallImmediate { + dest: StatePartIndex(308), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(4463), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 4115: Copy { + dest: StatePartIndex(4491), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4463), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4116: SliceInt { + dest: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(4491), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 4117: SliceInt { + dest: StatePartIndex(4493), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 4118: SliceInt { + dest: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(4493), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 4119: SliceInt { + dest: StatePartIndex(4495), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 4120: SliceInt { + dest: StatePartIndex(4497), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 4121: SliceInt { + dest: StatePartIndex(4498), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4497), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4122: Copy { + dest: StatePartIndex(4496), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4498), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4123: SliceInt { + dest: StatePartIndex(4502), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 4124: SliceInt { + dest: StatePartIndex(4503), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4502), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4125: SliceInt { + dest: StatePartIndex(4504), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4502), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4126: SliceInt { + dest: StatePartIndex(4505), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4502), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4127: Copy { + dest: StatePartIndex(4499), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(4503), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4128: Copy { + dest: StatePartIndex(4500), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(4504), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4129: Copy { + dest: StatePartIndex(4501), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(4505), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4130: SliceInt { + dest: StatePartIndex(4506), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 4131: SliceInt { + dest: StatePartIndex(4507), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4494), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 4132: CastToSInt { + dest: StatePartIndex(4508), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(4507), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4133: Copy { + dest: StatePartIndex(4484), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4495), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 4134: Copy { + dest: StatePartIndex(4485), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(4496), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4135: Copy { + dest: StatePartIndex(4486), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(4499), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4136: Copy { + dest: StatePartIndex(4487), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(4500), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4137: Copy { + dest: StatePartIndex(4488), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(4501), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4138: Copy { + dest: StatePartIndex(4489), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(4506), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4139: Copy { + dest: StatePartIndex(4490), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(4508), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4140: SliceInt { + dest: StatePartIndex(4509), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4493), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 4141: Copy { + dest: StatePartIndex(4510), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4509), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 4142: Copy { + dest: StatePartIndex(4476), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4484), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4143: Copy { + dest: StatePartIndex(4477), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4485), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4144: Copy { + dest: StatePartIndex(4478), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4486), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4145: Copy { + dest: StatePartIndex(4479), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4487), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4146: Copy { + dest: StatePartIndex(4480), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4488), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4147: Copy { + dest: StatePartIndex(4481), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4489), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4148: Copy { + dest: StatePartIndex(4482), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4490), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4149: Copy { + dest: StatePartIndex(4483), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4510), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4150: SliceInt { + dest: StatePartIndex(4511), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 4151: Copy { + dest: StatePartIndex(4512), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4511), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4152: SliceInt { + dest: StatePartIndex(4513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 4153: Copy { + dest: StatePartIndex(4514), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4154: SliceInt { + dest: StatePartIndex(4515), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 4155: Copy { + dest: StatePartIndex(4516), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4515), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4156: SliceInt { + dest: StatePartIndex(4517), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 4157: Copy { + dest: StatePartIndex(4518), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4517), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4158: Copy { + dest: StatePartIndex(4464), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4476), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4159: Copy { + dest: StatePartIndex(4465), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4477), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4160: Copy { + dest: StatePartIndex(4466), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4478), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4161: Copy { + dest: StatePartIndex(4467), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4479), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4162: Copy { + dest: StatePartIndex(4468), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4480), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4163: Copy { + dest: StatePartIndex(4469), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4481), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4164: Copy { + dest: StatePartIndex(4470), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4482), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4165: Copy { + dest: StatePartIndex(4471), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4483), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4166: Copy { + dest: StatePartIndex(4472), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(4512), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4167: Copy { + dest: StatePartIndex(4473), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(4514), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4168: Copy { + dest: StatePartIndex(4474), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(4516), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4169: Copy { + dest: StatePartIndex(4475), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(4518), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 4170: AndBigWithSmallImmediate { + dest: StatePartIndex(309), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4471), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4171: SliceInt { + dest: StatePartIndex(4528), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4492), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 4172: Copy { + dest: StatePartIndex(4519), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4476), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4173: Copy { + dest: StatePartIndex(4520), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4477), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4174: Copy { + dest: StatePartIndex(4521), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4478), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4175: Copy { + dest: StatePartIndex(4522), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4479), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4176: Copy { + dest: StatePartIndex(4523), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4480), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4177: Copy { + dest: StatePartIndex(4524), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4481), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4178: Copy { + dest: StatePartIndex(4525), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4482), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4179: Copy { + dest: StatePartIndex(4526), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4483), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4180: Copy { + dest: StatePartIndex(4527), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(4528), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 4181: AndBigWithSmallImmediate { + dest: StatePartIndex(310), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4526), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:314:25 + 4182: BranchIfSmallNeImmediate { + target: 4184, + lhs: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 4183: Copy { + dest: StatePartIndex(4391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4460), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4184: AndBigWithSmallImmediate { + dest: StatePartIndex(303), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:308:13 + 4185: BranchIfSmallNeImmediate { + target: 4189, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 4186: BranchIfZero { + target: 4189, + value: StatePartIndex(4390), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 4187: BranchIfSmallNeImmediate { + target: 4189, + lhs: StatePartIndex(303), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:318:25 + 4188: Copy { + dest: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3740), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 4189: Copy { + dest: StatePartIndex(4392), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 4190: SliceInt { + dest: StatePartIndex(4393), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4392), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 4191: Copy { + dest: StatePartIndex(4394), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4393), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:314:25 + 4192: AndBigWithSmallImmediate { + dest: StatePartIndex(304), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(4394), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 4193: Copy { + dest: StatePartIndex(4422), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4394), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4194: SliceInt { + dest: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(4422), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 4195: SliceInt { + dest: StatePartIndex(4424), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 4196: SliceInt { + dest: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(4424), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 4197: SliceInt { + dest: StatePartIndex(4426), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 4198: SliceInt { + dest: StatePartIndex(4428), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 4199: SliceInt { + dest: StatePartIndex(4429), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4428), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4200: Copy { + dest: StatePartIndex(4427), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4429), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4201: SliceInt { + dest: StatePartIndex(4433), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 4202: SliceInt { + dest: StatePartIndex(4434), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4433), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4203: SliceInt { + dest: StatePartIndex(4435), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4433), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4204: SliceInt { + dest: StatePartIndex(4436), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4433), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4205: Copy { + dest: StatePartIndex(4430), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(4434), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4206: Copy { + dest: StatePartIndex(4431), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(4435), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4207: Copy { + dest: StatePartIndex(4432), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(4436), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4208: SliceInt { + dest: StatePartIndex(4437), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 4209: SliceInt { + dest: StatePartIndex(4438), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4425), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 4210: CastToSInt { + dest: StatePartIndex(4439), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(4438), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4211: Copy { + dest: StatePartIndex(4415), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4426), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 4212: Copy { + dest: StatePartIndex(4416), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(4427), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4213: Copy { + dest: StatePartIndex(4417), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(4430), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4214: Copy { + dest: StatePartIndex(4418), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(4431), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4215: Copy { + dest: StatePartIndex(4419), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(4432), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4216: Copy { + dest: StatePartIndex(4420), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(4437), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4217: Copy { + dest: StatePartIndex(4421), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(4439), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4218: SliceInt { + dest: StatePartIndex(4440), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4424), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 4219: Copy { + dest: StatePartIndex(4441), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4440), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 4220: Copy { + dest: StatePartIndex(4407), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4415), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4221: Copy { + dest: StatePartIndex(4408), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4416), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4222: Copy { + dest: StatePartIndex(4409), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4417), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4223: Copy { + dest: StatePartIndex(4410), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4418), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4224: Copy { + dest: StatePartIndex(4411), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4419), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4225: Copy { + dest: StatePartIndex(4412), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4420), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4226: Copy { + dest: StatePartIndex(4413), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4421), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4227: Copy { + dest: StatePartIndex(4414), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4441), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4228: SliceInt { + dest: StatePartIndex(4442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 4229: Copy { + dest: StatePartIndex(4443), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4230: SliceInt { + dest: StatePartIndex(4444), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 4231: Copy { + dest: StatePartIndex(4445), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4444), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4232: SliceInt { + dest: StatePartIndex(4446), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 4233: Copy { + dest: StatePartIndex(4447), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4446), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4234: SliceInt { + dest: StatePartIndex(4448), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 4235: Copy { + dest: StatePartIndex(4449), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4448), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4236: Copy { + dest: StatePartIndex(4395), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4407), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4237: Copy { + dest: StatePartIndex(4396), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4408), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4238: Copy { + dest: StatePartIndex(4397), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4409), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4239: Copy { + dest: StatePartIndex(4398), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4410), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4240: Copy { + dest: StatePartIndex(4399), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4411), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4241: Copy { + dest: StatePartIndex(4400), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4412), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4242: Copy { + dest: StatePartIndex(4401), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4413), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4243: Copy { + dest: StatePartIndex(4402), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4414), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4244: Copy { + dest: StatePartIndex(4403), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(4443), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4245: Copy { + dest: StatePartIndex(4404), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(4445), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4246: Copy { + dest: StatePartIndex(4405), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(4447), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 4247: Copy { + dest: StatePartIndex(4406), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(4449), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:314:25 + 4248: AndBigWithSmallImmediate { + dest: StatePartIndex(305), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4402), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4249: SliceInt { + dest: StatePartIndex(4459), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4423), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 4250: Copy { + dest: StatePartIndex(4450), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4407), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4251: Copy { + dest: StatePartIndex(4451), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4408), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4252: Copy { + dest: StatePartIndex(4452), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4409), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4253: Copy { + dest: StatePartIndex(4453), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4410), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4254: Copy { + dest: StatePartIndex(4454), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4411), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4255: Copy { + dest: StatePartIndex(4455), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4412), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4256: Copy { + dest: StatePartIndex(4456), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4413), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4257: Copy { + dest: StatePartIndex(4457), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4414), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4258: Copy { + dest: StatePartIndex(4458), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(4459), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:314:25 + 4259: AndBigWithSmallImmediate { + dest: StatePartIndex(306), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4457), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 4260: Copy { + dest: StatePartIndex(4529), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4261: Copy { + dest: StatePartIndex(4530), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4394), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4262: Copy { + dest: StatePartIndex(4531), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4530), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4263: Shl { + dest: StatePartIndex(4532), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(4531), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 4264: Or { + dest: StatePartIndex(4533), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(4529), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(4532), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 4265: CastToUInt { + dest: StatePartIndex(4534), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4533), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 4266: Copy { + dest: StatePartIndex(4535), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4534), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: reg_alloc.rs:308:13 + 4267: BranchIfSmallNeImmediate { + target: 4271, + lhs: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 4268: BranchIfZero { + target: 4271, + value: StatePartIndex(4390), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 4269: BranchIfSmallNeImmediate { + target: 4271, + lhs: StatePartIndex(303), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:316:25 + 4270: Copy { + dest: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4535), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 4271: SliceInt { + dest: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(508), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 50, + }, + 4272: Copy { + dest: StatePartIndex(577), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: reg_alloc.rs:75:24 + 4273: AndBigWithSmallImmediate { + dest: StatePartIndex(99), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(577), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4274: Copy { + dest: StatePartIndex(592), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(577), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 4275: SliceInt { + dest: StatePartIndex(593), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(592), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 4276: SliceInt { + dest: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(593), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 4277: SliceInt { + dest: StatePartIndex(595), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 4278: SliceInt { + dest: StatePartIndex(597), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 4279: SliceInt { + dest: StatePartIndex(598), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(597), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4280: Copy { + dest: StatePartIndex(596), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(598), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4281: SliceInt { + dest: StatePartIndex(602), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 4282: SliceInt { + dest: StatePartIndex(603), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(602), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4283: SliceInt { + dest: StatePartIndex(604), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(602), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4284: SliceInt { + dest: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(602), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4285: Copy { + dest: StatePartIndex(599), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(603), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4286: Copy { + dest: StatePartIndex(600), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(604), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4287: Copy { + dest: StatePartIndex(601), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(605), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4288: SliceInt { + dest: StatePartIndex(606), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 4289: SliceInt { + dest: StatePartIndex(607), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(594), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 4290: CastToSInt { + dest: StatePartIndex(608), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(607), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4291: Copy { + dest: StatePartIndex(585), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(595), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4292: Copy { + dest: StatePartIndex(586), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(596), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4293: Copy { + dest: StatePartIndex(587), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(599), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4294: Copy { + dest: StatePartIndex(588), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(600), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4295: Copy { + dest: StatePartIndex(589), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(601), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4296: Copy { + dest: StatePartIndex(590), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(606), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4297: Copy { + dest: StatePartIndex(591), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(608), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4298: Copy { + dest: StatePartIndex(578), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(585), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 4299: Copy { + dest: StatePartIndex(579), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(586), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4300: Copy { + dest: StatePartIndex(580), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(587), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4301: Copy { + dest: StatePartIndex(581), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(588), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4302: Copy { + dest: StatePartIndex(582), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(589), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4303: Copy { + dest: StatePartIndex(583), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(590), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4304: Copy { + dest: StatePartIndex(584), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(591), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4305: Copy { + dest: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(576), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: reg_alloc.rs:75:24 + 4306: AndBigWithSmallImmediate { + dest: StatePartIndex(100), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4307: Copy { + dest: StatePartIndex(617), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(609), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 4308: SliceInt { + dest: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(617), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 4309: SliceInt { + dest: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 4310: SliceInt { + dest: StatePartIndex(621), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 4311: SliceInt { + dest: StatePartIndex(622), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(621), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4312: Copy { + dest: StatePartIndex(620), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(622), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4313: SliceInt { + dest: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 4314: SliceInt { + dest: StatePartIndex(627), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4315: SliceInt { + dest: StatePartIndex(628), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4316: SliceInt { + dest: StatePartIndex(629), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4317: Copy { + dest: StatePartIndex(623), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(627), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4318: Copy { + dest: StatePartIndex(624), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(628), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4319: Copy { + dest: StatePartIndex(625), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(629), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4320: SliceInt { + dest: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 4321: SliceInt { + dest: StatePartIndex(631), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(618), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 4322: CastToSInt { + dest: StatePartIndex(632), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(631), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4323: Copy { + dest: StatePartIndex(610), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4324: Copy { + dest: StatePartIndex(611), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(620), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4325: Copy { + dest: StatePartIndex(612), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(623), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4326: Copy { + dest: StatePartIndex(613), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(624), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4327: Copy { + dest: StatePartIndex(614), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(625), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4328: Copy { + dest: StatePartIndex(615), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4329: Copy { + dest: StatePartIndex(616), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(632), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: reg_alloc.rs:114:17 + 4330: BranchIfZero { + target: 4341, + value: StatePartIndex(1892), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4331: BranchIfSmallNeImmediate { + target: 4341, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4332: BranchIfSmallNeImmediate { + target: 4341, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4333: BranchIfZero { + target: 4335, + value: StatePartIndex(1927), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4334: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4335: BranchIfZero { + target: 4337, + value: StatePartIndex(1937), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4336: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4337: BranchIfZero { + target: 4339, + value: StatePartIndex(1938), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4338: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4339: BranchIfZero { + target: 4341, + value: StatePartIndex(1939), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4340: Copy { + dest: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4341: AndBigWithSmallImmediate { + dest: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4342: Copy { + dest: StatePartIndex(1883), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1879), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4343: SliceInt { + dest: StatePartIndex(1884), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1883), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4344: SliceInt { + dest: StatePartIndex(1885), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1884), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4345: SliceInt { + dest: StatePartIndex(1886), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1885), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4346: Copy { + dest: StatePartIndex(1882), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(1886), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4347: SliceInt { + dest: StatePartIndex(1888), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1884), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4348: SliceInt { + dest: StatePartIndex(1889), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1888), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4349: Copy { + dest: StatePartIndex(1887), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1889), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4350: Copy { + dest: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1882), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4351: Copy { + dest: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1887), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:114:17 + 4352: BranchIfZero { + target: 4363, + value: StatePartIndex(1954), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4353: BranchIfSmallNeImmediate { + target: 4363, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4354: BranchIfSmallNeImmediate { + target: 4363, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4355: BranchIfZero { + target: 4357, + value: StatePartIndex(1984), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4356: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4357: BranchIfZero { + target: 4359, + value: StatePartIndex(1985), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4358: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4359: BranchIfZero { + target: 4361, + value: StatePartIndex(1986), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4360: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4361: BranchIfZero { + target: 4363, + value: StatePartIndex(1987), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4362: Copy { + dest: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4363: AndBigWithSmallImmediate { + dest: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4364: Copy { + dest: StatePartIndex(1945), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1941), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4365: SliceInt { + dest: StatePartIndex(1946), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1945), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4366: SliceInt { + dest: StatePartIndex(1947), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1946), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4367: SliceInt { + dest: StatePartIndex(1948), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1947), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4368: Copy { + dest: StatePartIndex(1944), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(1948), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4369: SliceInt { + dest: StatePartIndex(1950), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1946), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4370: SliceInt { + dest: StatePartIndex(1951), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1950), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4371: Copy { + dest: StatePartIndex(1949), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1951), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4372: Copy { + dest: StatePartIndex(1942), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1944), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4373: Copy { + dest: StatePartIndex(1943), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1949), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:114:17 + 4374: BranchIfZero { + target: 4385, + value: StatePartIndex(2002), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4375: BranchIfSmallNeImmediate { + target: 4385, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4376: BranchIfSmallNeImmediate { + target: 4385, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4377: BranchIfZero { + target: 4379, + value: StatePartIndex(2032), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4378: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4379: BranchIfZero { + target: 4381, + value: StatePartIndex(2033), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4380: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4381: BranchIfZero { + target: 4383, + value: StatePartIndex(2034), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4382: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4383: BranchIfZero { + target: 4385, + value: StatePartIndex(2035), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4384: Copy { + dest: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4385: AndBigWithSmallImmediate { + dest: StatePartIndex(157), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4386: Copy { + dest: StatePartIndex(1993), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(1989), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_normal_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4387: SliceInt { + dest: StatePartIndex(1994), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(1993), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4388: SliceInt { + dest: StatePartIndex(1995), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1994), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4389: SliceInt { + dest: StatePartIndex(1996), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(1995), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4390: Copy { + dest: StatePartIndex(1992), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(1996), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4391: SliceInt { + dest: StatePartIndex(1998), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1994), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4392: SliceInt { + dest: StatePartIndex(1999), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(1998), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4393: Copy { + dest: StatePartIndex(1997), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(1999), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4394: Copy { + dest: StatePartIndex(1990), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1992), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4395: Copy { + dest: StatePartIndex(1991), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1997), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:114:17 + 4396: BranchIfZero { + target: 4407, + value: StatePartIndex(2050), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4397: BranchIfSmallNeImmediate { + target: 4407, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4398: BranchIfSmallNeImmediate { + target: 4407, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4399: BranchIfZero { + target: 4401, + value: StatePartIndex(2080), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4400: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4401: BranchIfZero { + target: 4403, + value: StatePartIndex(2081), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4402: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4403: BranchIfZero { + target: 4405, + value: StatePartIndex(2082), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4404: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4405: BranchIfZero { + target: 4407, + value: StatePartIndex(2083), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4406: Copy { + dest: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4407: AndBigWithSmallImmediate { + dest: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 4408: BranchIfSmallNeImmediate { + target: 4420, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4409: BranchIfSmallNeImmediate { + target: 4420, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 4410: Copy { + dest: StatePartIndex(2391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4411: Copy { + dest: StatePartIndex(2392), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4412: Copy { + dest: StatePartIndex(2496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4413: Copy { + dest: StatePartIndex(2497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4414: Copy { + dest: StatePartIndex(2609), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4415: Copy { + dest: StatePartIndex(2610), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4416: Copy { + dest: StatePartIndex(2813), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4417: Copy { + dest: StatePartIndex(2814), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4418: Copy { + dest: StatePartIndex(2979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4419: Copy { + dest: StatePartIndex(2980), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4420: Copy { + dest: StatePartIndex(2041), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2037), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_0.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4421: SliceInt { + dest: StatePartIndex(2042), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2041), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4422: SliceInt { + dest: StatePartIndex(2043), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2042), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4423: SliceInt { + dest: StatePartIndex(2044), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2043), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4424: Copy { + dest: StatePartIndex(2040), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(2044), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4425: SliceInt { + dest: StatePartIndex(2046), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2042), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4426: SliceInt { + dest: StatePartIndex(2047), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2046), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4427: Copy { + dest: StatePartIndex(2045), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2047), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4428: Copy { + dest: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2040), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4429: Copy { + dest: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2045), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4430: BranchIfSmallNeImmediate { + target: 4434, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4431: BranchIfSmallNeImmediate { + target: 4434, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4432: Copy { + dest: StatePartIndex(2391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4433: Copy { + dest: StatePartIndex(2392), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4434: BranchIfSmallNeImmediate { + target: 4437, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4435: Copy { + dest: StatePartIndex(2391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4436: Copy { + dest: StatePartIndex(2392), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4437: Shl { + dest: StatePartIndex(2446), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2392), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4438: Or { + dest: StatePartIndex(2447), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2446), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 4439: BranchIfSmallNeImmediate { + target: 4443, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4440: BranchIfSmallNeImmediate { + target: 4443, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4441: Copy { + dest: StatePartIndex(2496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4442: Copy { + dest: StatePartIndex(2497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4443: BranchIfSmallNeImmediate { + target: 4446, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4444: Copy { + dest: StatePartIndex(2496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4445: Copy { + dest: StatePartIndex(2497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4446: Shl { + dest: StatePartIndex(2547), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2497), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4447: Or { + dest: StatePartIndex(2548), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2547), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 4448: BranchIfSmallNeImmediate { + target: 4452, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4449: BranchIfSmallNeImmediate { + target: 4452, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4450: Copy { + dest: StatePartIndex(2609), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4451: Copy { + dest: StatePartIndex(2610), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4452: BranchIfSmallNeImmediate { + target: 4455, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4453: Copy { + dest: StatePartIndex(2609), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4454: Copy { + dest: StatePartIndex(2610), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4455: Shl { + dest: StatePartIndex(2654), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2610), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4456: Or { + dest: StatePartIndex(2655), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2609), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2654), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 4457: BranchIfSmallNeImmediate { + target: 4461, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4458: BranchIfSmallNeImmediate { + target: 4461, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4459: Copy { + dest: StatePartIndex(2813), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4460: Copy { + dest: StatePartIndex(2814), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4461: BranchIfSmallNeImmediate { + target: 4464, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4462: Copy { + dest: StatePartIndex(2813), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4463: Copy { + dest: StatePartIndex(2814), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4464: Shl { + dest: StatePartIndex(2842), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2814), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4465: Or { + dest: StatePartIndex(2843), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2813), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2842), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4466: Copy { + dest: StatePartIndex(2841), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2843), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4467: Copy { + dest: StatePartIndex(2838), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2841), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4468: Copy { + dest: StatePartIndex(2839), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4469: Copy { + dest: StatePartIndex(2840), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2865), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4470: Copy { + dest: StatePartIndex(2831), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(328), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 4471: Copy { + dest: StatePartIndex(2832), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4472: Copy { + dest: StatePartIndex(2833), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2838), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4473: Copy { + dest: StatePartIndex(2834), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2839), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4474: Copy { + dest: StatePartIndex(2835), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2840), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4475: Copy { + dest: StatePartIndex(2836), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2866), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4476: Copy { + dest: StatePartIndex(2837), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2867), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4477: Copy { + dest: StatePartIndex(2824), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2831), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 4478: Copy { + dest: StatePartIndex(2825), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2832), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4479: Copy { + dest: StatePartIndex(2826), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2833), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4480: Copy { + dest: StatePartIndex(2827), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2834), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4481: Copy { + dest: StatePartIndex(2828), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2835), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4482: Copy { + dest: StatePartIndex(2829), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2836), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4483: Copy { + dest: StatePartIndex(2830), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2837), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4484: Copy { + dest: StatePartIndex(2816), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4485: Copy { + dest: StatePartIndex(2817), // (0x1) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2824), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + }, + 4486: Copy { + dest: StatePartIndex(2818), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2825), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4487: Copy { + dest: StatePartIndex(2819), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2826), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4488: Copy { + dest: StatePartIndex(2820), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2827), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4489: Copy { + dest: StatePartIndex(2821), // (0x0) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2828), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4490: Copy { + dest: StatePartIndex(2822), // (0x0) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2829), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4491: Copy { + dest: StatePartIndex(2823), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2830), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4492: Shl { + dest: StatePartIndex(2868), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2818), // (0x0) SlotDebugData { name: ".1.common.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 4493: Or { + dest: StatePartIndex(2869), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2817), // (0x1) SlotDebugData { name: ".1.common.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(2868), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 4494: Shl { + dest: StatePartIndex(2870), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2820), // (0x0) SlotDebugData { name: ".1.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 4495: Or { + dest: StatePartIndex(2871), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2819), // (0x0) SlotDebugData { name: ".1.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2870), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 4496: Shl { + dest: StatePartIndex(2872), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2821), // (0x0) SlotDebugData { name: ".1.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 4497: Or { + dest: StatePartIndex(2873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2871), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2872), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 4498: Shl { + dest: StatePartIndex(2874), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 4499: Or { + dest: StatePartIndex(2875), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(2869), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(2874), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + }, + 4500: Shl { + dest: StatePartIndex(2876), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2822), // (0x0) SlotDebugData { name: ".1.common.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 4501: Or { + dest: StatePartIndex(2877), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2875), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(2876), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4502: CastToUInt { + dest: StatePartIndex(2878), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2823), // (0x0) SlotDebugData { name: ".1.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 4503: Shl { + dest: StatePartIndex(2879), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2878), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 4504: Or { + dest: StatePartIndex(2880), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2877), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2879), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 4505: Or { + dest: StatePartIndex(2882), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(2880), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(2881), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 4506: Shl { + dest: StatePartIndex(2883), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2882), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 4507: Or { + dest: StatePartIndex(2884), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2816), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(2883), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + 4508: CastToUInt { + dest: StatePartIndex(2885), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2884), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 4509: Copy { + dest: StatePartIndex(2886), // (0x3) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2885), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:504:1 + 4510: BranchIfSmallNeImmediate { + target: 4512, + lhs: StatePartIndex(24), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + rhs: 0x1, + }, + 4511: Copy { + dest: StatePartIndex(2713), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2886), // (0x3) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 4512: AndBigWithSmallImmediate { + dest: StatePartIndex(211), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(2713), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4513: Copy { + dest: StatePartIndex(2728), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2713), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 4514: SliceInt { + dest: StatePartIndex(2729), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2728), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 4515: SliceInt { + dest: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2729), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 4516: SliceInt { + dest: StatePartIndex(2731), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 4517: SliceInt { + dest: StatePartIndex(2733), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 4518: SliceInt { + dest: StatePartIndex(2734), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2733), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4519: Copy { + dest: StatePartIndex(2732), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2734), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4520: SliceInt { + dest: StatePartIndex(2738), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 4521: SliceInt { + dest: StatePartIndex(2739), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2738), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4522: SliceInt { + dest: StatePartIndex(2740), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2738), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4523: SliceInt { + dest: StatePartIndex(2741), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2738), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4524: Copy { + dest: StatePartIndex(2735), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2739), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4525: Copy { + dest: StatePartIndex(2736), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2740), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4526: Copy { + dest: StatePartIndex(2737), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2741), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4527: SliceInt { + dest: StatePartIndex(2742), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 4528: SliceInt { + dest: StatePartIndex(2743), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2730), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 4529: CastToSInt { + dest: StatePartIndex(2744), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2743), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4530: Copy { + dest: StatePartIndex(2721), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2731), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4531: Copy { + dest: StatePartIndex(2722), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2732), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4532: Copy { + dest: StatePartIndex(2723), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2735), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4533: Copy { + dest: StatePartIndex(2724), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2736), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4534: Copy { + dest: StatePartIndex(2725), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2737), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4535: Copy { + dest: StatePartIndex(2726), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2742), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4536: Copy { + dest: StatePartIndex(2727), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2744), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4537: Copy { + dest: StatePartIndex(2714), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2721), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 4538: Copy { + dest: StatePartIndex(2715), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2722), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4539: Copy { + dest: StatePartIndex(2716), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2723), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4540: Copy { + dest: StatePartIndex(2717), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2724), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4541: Copy { + dest: StatePartIndex(2718), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2725), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4542: Copy { + dest: StatePartIndex(2719), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2726), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4543: Copy { + dest: StatePartIndex(2720), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2727), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4544: Copy { + dest: StatePartIndex(2887), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4545: Copy { + dest: StatePartIndex(2888), // (0x2) SlotDebugData { name: ".1", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2713), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 4546: Copy { + dest: StatePartIndex(2889), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2888), // (0x2) SlotDebugData { name: ".1", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 4547: Shl { + dest: StatePartIndex(2890), // (0x8) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2889), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + rhs: 2, + }, + 4548: Or { + dest: StatePartIndex(2891), // (0x9) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2887), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(2890), // (0x8) SlotDebugData { name: "", ty: UInt<52> }, + }, + 4549: CastToUInt { + dest: StatePartIndex(2892), // (0x9) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(2891), // (0x9) SlotDebugData { name: "", ty: UInt<52> }, + dest_width: 59, + }, + 4550: Copy { + dest: StatePartIndex(2893), // (0x9) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(2892), // (0x9) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: reg_alloc.rs:184:29 + 4551: BranchIfSmallNeImmediate { + target: 4555, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4552: BranchIfSmallNeImmediate { + target: 4555, + lhs: StatePartIndex(166), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4553: Copy { + dest: StatePartIndex(2979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2038), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4554: Copy { + dest: StatePartIndex(2980), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2039), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4555: BranchIfSmallNeImmediate { + target: 4558, + lhs: StatePartIndex(139), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4556: Copy { + dest: StatePartIndex(2979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1880), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4557: Copy { + dest: StatePartIndex(2980), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1881), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4558: Shl { + dest: StatePartIndex(3001), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2980), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4559: Or { + dest: StatePartIndex(3002), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2979), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_0.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(3001), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4560: Copy { + dest: StatePartIndex(3000), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3002), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4561: Copy { + dest: StatePartIndex(2997), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3000), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4562: Copy { + dest: StatePartIndex(2998), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(1560), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4563: Copy { + dest: StatePartIndex(2999), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3024), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4564: Copy { + dest: StatePartIndex(2990), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(384), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 4565: Copy { + dest: StatePartIndex(2991), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4566: Copy { + dest: StatePartIndex(2992), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2997), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4567: Copy { + dest: StatePartIndex(2993), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2998), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4568: Copy { + dest: StatePartIndex(2994), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2999), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4569: Copy { + dest: StatePartIndex(2995), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3025), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4570: Copy { + dest: StatePartIndex(2996), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3026), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4571: Copy { + dest: StatePartIndex(2982), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4572: Copy { + dest: StatePartIndex(2983), // (0x1) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2990), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 4573: Copy { + dest: StatePartIndex(2984), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + src: StatePartIndex(2991), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4574: Copy { + dest: StatePartIndex(2985), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + src: StatePartIndex(2992), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4575: Copy { + dest: StatePartIndex(2986), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + src: StatePartIndex(2993), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4576: Copy { + dest: StatePartIndex(2987), // (0x0) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + src: StatePartIndex(2994), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4577: Copy { + dest: StatePartIndex(2988), // (0x0) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + src: StatePartIndex(2995), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4578: Copy { + dest: StatePartIndex(2989), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2996), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4579: Shl { + dest: StatePartIndex(3027), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2984), // (0x0) SlotDebugData { name: ".1.dest.value", ty: UInt<4> }, + rhs: 1, + }, + 4580: Or { + dest: StatePartIndex(3028), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(2983), // (0x1) SlotDebugData { name: ".1.prefix_pad", ty: UInt<1> }, + rhs: StatePartIndex(3027), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 4581: Shl { + dest: StatePartIndex(3029), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2986), // (0x0) SlotDebugData { name: ".1.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 4582: Or { + dest: StatePartIndex(3030), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2985), // (0x0) SlotDebugData { name: ".1.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(3029), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 4583: Shl { + dest: StatePartIndex(3031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2987), // (0x0) SlotDebugData { name: ".1.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 4584: Or { + dest: StatePartIndex(3032), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(3030), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(3031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 4585: Shl { + dest: StatePartIndex(3033), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(3032), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 5, + }, + 4586: Or { + dest: StatePartIndex(3034), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + lhs: StatePartIndex(3028), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + rhs: StatePartIndex(3033), // (0x0) SlotDebugData { name: "", ty: UInt<23> }, + }, + 4587: Shl { + dest: StatePartIndex(3035), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2988), // (0x0) SlotDebugData { name: ".1.imm_low", ty: UInt<25> }, + rhs: 23, + }, + 4588: Or { + dest: StatePartIndex(3036), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(3034), // (0x1) SlotDebugData { name: "", ty: UInt<23> }, + rhs: StatePartIndex(3035), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4589: CastToUInt { + dest: StatePartIndex(3037), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2989), // (0x0) SlotDebugData { name: ".1.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 4590: Shl { + dest: StatePartIndex(3038), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(3037), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 48, + }, + 4591: Or { + dest: StatePartIndex(3039), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(3036), // (0x1) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(3038), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 4592: Or { + dest: StatePartIndex(3041), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + lhs: StatePartIndex(3039), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: StatePartIndex(3040), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + }, + 4593: Shl { + dest: StatePartIndex(3042), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(3041), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + rhs: 1, + }, + 4594: Or { + dest: StatePartIndex(3043), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + lhs: StatePartIndex(2982), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3042), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + 4595: CastToUInt { + dest: StatePartIndex(3044), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(3043), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + dest_width: 50, + }, + 4596: Copy { + dest: StatePartIndex(3045), // (0x3) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(3044), // (0x3) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: instruction.rs:539:1 + 4597: BranchIfSmallNeImmediate { + target: 4599, + lhs: StatePartIndex(27), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + rhs: 0x1, + }, + 4598: Copy { + dest: StatePartIndex(2894), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(3045), // (0x3) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 4599: AndBigWithSmallImmediate { + dest: StatePartIndex(212), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(2894), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 4600: Copy { + dest: StatePartIndex(2902), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2894), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 4601: SliceInt { + dest: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2902), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 4602: SliceInt { + dest: StatePartIndex(2904), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 4603: SliceInt { + dest: StatePartIndex(2906), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 4604: SliceInt { + dest: StatePartIndex(2907), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2906), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4605: Copy { + dest: StatePartIndex(2905), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2907), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4606: SliceInt { + dest: StatePartIndex(2911), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 4607: SliceInt { + dest: StatePartIndex(2912), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2911), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4608: SliceInt { + dest: StatePartIndex(2913), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2911), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4609: SliceInt { + dest: StatePartIndex(2914), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2911), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4610: Copy { + dest: StatePartIndex(2908), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2912), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4611: Copy { + dest: StatePartIndex(2909), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2913), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4612: Copy { + dest: StatePartIndex(2910), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2914), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4613: SliceInt { + dest: StatePartIndex(2915), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 4614: SliceInt { + dest: StatePartIndex(2916), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2903), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 4615: CastToSInt { + dest: StatePartIndex(2917), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2916), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4616: Copy { + dest: StatePartIndex(2895), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2904), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4617: Copy { + dest: StatePartIndex(2896), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2905), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4618: Copy { + dest: StatePartIndex(2897), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2908), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4619: Copy { + dest: StatePartIndex(2898), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2909), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4620: Copy { + dest: StatePartIndex(2899), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2910), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4621: Copy { + dest: StatePartIndex(2900), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2915), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4622: Copy { + dest: StatePartIndex(2901), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2917), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4623: Copy { + dest: StatePartIndex(3046), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4624: Copy { + dest: StatePartIndex(3047), // (0x2) SlotDebugData { name: ".1", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(2894), // (0x2) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 4625: Copy { + dest: StatePartIndex(3048), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(3047), // (0x2) SlotDebugData { name: ".1", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 4626: Shl { + dest: StatePartIndex(3049), // (0x8) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(3048), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + rhs: 2, + }, + 4627: Or { + dest: StatePartIndex(3050), // (0xa) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(3046), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(3049), // (0x8) SlotDebugData { name: "", ty: UInt<52> }, + }, + 4628: CastToUInt { + dest: StatePartIndex(3051), // (0xa) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(3050), // (0xa) SlotDebugData { name: "", ty: UInt<52> }, + dest_width: 59, + }, + 4629: Copy { + dest: StatePartIndex(3052), // (0xa) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(3051), // (0xa) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: reg_alloc.rs:114:17 + 4630: BranchIfZero { + target: 4641, + value: StatePartIndex(2098), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4631: BranchIfSmallNeImmediate { + target: 4641, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4632: BranchIfSmallNeImmediate { + target: 4641, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4633: BranchIfZero { + target: 4635, + value: StatePartIndex(2128), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4634: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4635: BranchIfZero { + target: 4637, + value: StatePartIndex(2129), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4636: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4637: BranchIfZero { + target: 4639, + value: StatePartIndex(2130), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4638: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4639: BranchIfZero { + target: 4641, + value: StatePartIndex(2131), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4640: Copy { + dest: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4641: AndBigWithSmallImmediate { + dest: StatePartIndex(175), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 4642: BranchIfSmallNeImmediate { + target: 4650, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4643: BranchIfSmallNeImmediate { + target: 4650, + lhs: StatePartIndex(175), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 4644: Copy { + dest: StatePartIndex(2394), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4645: Copy { + dest: StatePartIndex(2395), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4646: Copy { + dest: StatePartIndex(2499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4647: Copy { + dest: StatePartIndex(2500), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4648: Copy { + dest: StatePartIndex(2612), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4649: Copy { + dest: StatePartIndex(2613), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4650: Copy { + dest: StatePartIndex(2089), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2085), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_1.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4651: SliceInt { + dest: StatePartIndex(2090), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2089), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4652: SliceInt { + dest: StatePartIndex(2091), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2090), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4653: SliceInt { + dest: StatePartIndex(2092), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2091), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4654: Copy { + dest: StatePartIndex(2088), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(2092), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4655: SliceInt { + dest: StatePartIndex(2094), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2090), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4656: SliceInt { + dest: StatePartIndex(2095), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2094), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4657: Copy { + dest: StatePartIndex(2093), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2095), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4658: Copy { + dest: StatePartIndex(2086), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2088), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4659: Copy { + dest: StatePartIndex(2087), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2093), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4660: BranchIfSmallNeImmediate { + target: 4664, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4661: BranchIfSmallNeImmediate { + target: 4664, + lhs: StatePartIndex(175), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4662: Copy { + dest: StatePartIndex(2394), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2086), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4663: Copy { + dest: StatePartIndex(2395), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2087), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4664: BranchIfSmallNeImmediate { + target: 4667, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4665: Copy { + dest: StatePartIndex(2394), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1942), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4666: Copy { + dest: StatePartIndex(2395), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1943), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4667: Shl { + dest: StatePartIndex(2448), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2395), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4668: Or { + dest: StatePartIndex(2449), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2394), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2448), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + // at: reg_alloc.rs:184:29 + 4669: BranchIfSmallNeImmediate { + target: 4673, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4670: BranchIfSmallNeImmediate { + target: 4673, + lhs: StatePartIndex(175), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4671: Copy { + dest: StatePartIndex(2499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2086), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4672: Copy { + dest: StatePartIndex(2500), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2087), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4673: BranchIfSmallNeImmediate { + target: 4676, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4674: Copy { + dest: StatePartIndex(2499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1942), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4675: Copy { + dest: StatePartIndex(2500), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1943), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4676: Shl { + dest: StatePartIndex(2549), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2500), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4677: Or { + dest: StatePartIndex(2550), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2499), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2549), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4678: Copy { + dest: StatePartIndex(2545), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2548), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4679: Copy { + dest: StatePartIndex(2546), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2550), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4680: Copy { + dest: StatePartIndex(2542), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2545), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4681: Copy { + dest: StatePartIndex(2543), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2546), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4682: Copy { + dest: StatePartIndex(2544), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2572), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4683: Copy { + dest: StatePartIndex(2535), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(231), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4684: Copy { + dest: StatePartIndex(2536), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4685: Copy { + dest: StatePartIndex(2537), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2542), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4686: Copy { + dest: StatePartIndex(2538), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2543), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4687: Copy { + dest: StatePartIndex(2539), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2544), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4688: Copy { + dest: StatePartIndex(2540), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2573), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4689: Copy { + dest: StatePartIndex(2541), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2574), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4690: Copy { + dest: StatePartIndex(2527), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2535), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4691: Copy { + dest: StatePartIndex(2528), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2536), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4692: Copy { + dest: StatePartIndex(2529), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2537), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4693: Copy { + dest: StatePartIndex(2530), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2538), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4694: Copy { + dest: StatePartIndex(2531), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2539), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4695: Copy { + dest: StatePartIndex(2532), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2540), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4696: Copy { + dest: StatePartIndex(2533), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2541), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4697: Copy { + dest: StatePartIndex(2534), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(241), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4698: Copy { + dest: StatePartIndex(2515), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2527), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4699: Copy { + dest: StatePartIndex(2516), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2528), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4700: Copy { + dest: StatePartIndex(2517), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2529), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4701: Copy { + dest: StatePartIndex(2518), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2530), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4702: Copy { + dest: StatePartIndex(2519), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2531), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4703: Copy { + dest: StatePartIndex(2520), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2532), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4704: Copy { + dest: StatePartIndex(2521), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2533), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4705: Copy { + dest: StatePartIndex(2522), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2534), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4706: Copy { + dest: StatePartIndex(2523), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(242), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 4707: Copy { + dest: StatePartIndex(2524), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(243), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 4708: Copy { + dest: StatePartIndex(2525), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(244), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 4709: Copy { + dest: StatePartIndex(2526), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(245), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 4710: Copy { + dest: StatePartIndex(2502), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(958), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4711: Copy { + dest: StatePartIndex(2503), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2515), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4712: Copy { + dest: StatePartIndex(2504), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2516), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 4713: Copy { + dest: StatePartIndex(2505), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2517), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 4714: Copy { + dest: StatePartIndex(2506), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2518), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 4715: Copy { + dest: StatePartIndex(2507), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2519), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 4716: Copy { + dest: StatePartIndex(2508), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2520), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 4717: Copy { + dest: StatePartIndex(2509), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2521), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 4718: Copy { + dest: StatePartIndex(2510), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2522), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4719: Copy { + dest: StatePartIndex(2511), // (0x0) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + src: StatePartIndex(2523), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 4720: Copy { + dest: StatePartIndex(2512), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + src: StatePartIndex(2524), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 4721: Copy { + dest: StatePartIndex(2513), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + src: StatePartIndex(2525), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 4722: Copy { + dest: StatePartIndex(2514), // (0x0) SlotDebugData { name: ".1.add_pc", ty: Bool }, + src: StatePartIndex(2526), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 4723: Shl { + dest: StatePartIndex(2575), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2504), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 4724: Or { + dest: StatePartIndex(2576), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2503), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(2575), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4725: Shl { + dest: StatePartIndex(2577), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2506), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 4726: Or { + dest: StatePartIndex(2578), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2505), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2577), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 4727: Shl { + dest: StatePartIndex(2579), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2507), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 4728: Or { + dest: StatePartIndex(2580), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2578), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2579), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 4729: Shl { + dest: StatePartIndex(2581), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2580), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 4730: Or { + dest: StatePartIndex(2582), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2576), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(2581), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + }, + 4731: Shl { + dest: StatePartIndex(2583), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2508), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 4732: Or { + dest: StatePartIndex(2584), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2582), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(2583), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + }, + 4733: CastToUInt { + dest: StatePartIndex(2585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2509), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 4734: Shl { + dest: StatePartIndex(2586), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2585), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 4735: Or { + dest: StatePartIndex(2587), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2584), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(2586), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4736: Or { + dest: StatePartIndex(2589), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2587), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2588), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4737: Copy { + dest: StatePartIndex(2590), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(2510), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4738: Shl { + dest: StatePartIndex(2591), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2590), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 4739: Or { + dest: StatePartIndex(2592), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2589), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2591), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 4740: Copy { + dest: StatePartIndex(2593), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2511), // (0x0) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + }, + 4741: Shl { + dest: StatePartIndex(2594), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2593), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 51, + }, + 4742: Or { + dest: StatePartIndex(2595), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2592), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(2594), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + }, + 4743: Copy { + dest: StatePartIndex(2596), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2512), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + }, + 4744: Shl { + dest: StatePartIndex(2597), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(2596), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 52, + }, + 4745: Or { + dest: StatePartIndex(2598), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(2595), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + rhs: StatePartIndex(2597), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + }, + 4746: Copy { + dest: StatePartIndex(2599), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2513), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + }, + 4747: Shl { + dest: StatePartIndex(2600), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(2599), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 53, + }, + 4748: Or { + dest: StatePartIndex(2601), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(2598), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + rhs: StatePartIndex(2600), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + }, + 4749: Copy { + dest: StatePartIndex(2602), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2514), // (0x0) SlotDebugData { name: ".1.add_pc", ty: Bool }, + }, + 4750: Shl { + dest: StatePartIndex(2603), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2602), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 54, + }, + 4751: Or { + dest: StatePartIndex(2604), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2601), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<54> }, + rhs: StatePartIndex(2603), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + }, + 4752: Shl { + dest: StatePartIndex(2605), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2604), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 4753: Or { + dest: StatePartIndex(2606), // (0xc0000000000001) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2502), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(2605), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 4754: CastToUInt { + dest: StatePartIndex(2607), // (0xc0000000000001) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2606), // (0xc0000000000001) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 4755: Copy { + dest: StatePartIndex(2608), // (0xc0000000000001) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2607), // (0xc0000000000001) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:184:29 + 4756: BranchIfSmallNeImmediate { + target: 4760, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4757: BranchIfSmallNeImmediate { + target: 4760, + lhs: StatePartIndex(175), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4758: Copy { + dest: StatePartIndex(2612), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2086), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4759: Copy { + dest: StatePartIndex(2613), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2087), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4760: BranchIfSmallNeImmediate { + target: 4763, + lhs: StatePartIndex(148), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4761: Copy { + dest: StatePartIndex(2612), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1942), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4762: Copy { + dest: StatePartIndex(2613), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1943), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4763: Shl { + dest: StatePartIndex(2656), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2613), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4764: Or { + dest: StatePartIndex(2657), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2612), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_1.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2656), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4765: Copy { + dest: StatePartIndex(2652), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2655), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4766: Copy { + dest: StatePartIndex(2653), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2657), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4767: Copy { + dest: StatePartIndex(2649), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2652), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4768: Copy { + dest: StatePartIndex(2650), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2653), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4769: Copy { + dest: StatePartIndex(2651), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2679), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4770: Copy { + dest: StatePartIndex(2642), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(313), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4771: Copy { + dest: StatePartIndex(2643), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4772: Copy { + dest: StatePartIndex(2644), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2649), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4773: Copy { + dest: StatePartIndex(2645), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2650), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4774: Copy { + dest: StatePartIndex(2646), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2651), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4775: Copy { + dest: StatePartIndex(2647), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2680), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4776: Copy { + dest: StatePartIndex(2648), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2681), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4777: Copy { + dest: StatePartIndex(2634), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2642), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4778: Copy { + dest: StatePartIndex(2635), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2643), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4779: Copy { + dest: StatePartIndex(2636), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2644), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4780: Copy { + dest: StatePartIndex(2637), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2645), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4781: Copy { + dest: StatePartIndex(2638), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2646), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4782: Copy { + dest: StatePartIndex(2639), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2647), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4783: Copy { + dest: StatePartIndex(2640), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2648), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4784: Copy { + dest: StatePartIndex(2641), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(323), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4785: Copy { + dest: StatePartIndex(2625), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2634), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4786: Copy { + dest: StatePartIndex(2626), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2635), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4787: Copy { + dest: StatePartIndex(2627), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2636), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4788: Copy { + dest: StatePartIndex(2628), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2637), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4789: Copy { + dest: StatePartIndex(2629), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2638), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4790: Copy { + dest: StatePartIndex(2630), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2639), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4791: Copy { + dest: StatePartIndex(2631), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2640), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4792: Copy { + dest: StatePartIndex(2632), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2641), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4793: Copy { + dest: StatePartIndex(2633), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(324), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + }, + 4794: Copy { + dest: StatePartIndex(2615), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(960), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4795: Copy { + dest: StatePartIndex(2616), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2625), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4796: Copy { + dest: StatePartIndex(2617), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2626), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 4797: Copy { + dest: StatePartIndex(2618), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2627), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 4798: Copy { + dest: StatePartIndex(2619), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2628), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 4799: Copy { + dest: StatePartIndex(2620), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2629), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 4800: Copy { + dest: StatePartIndex(2621), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2630), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 4801: Copy { + dest: StatePartIndex(2622), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2631), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 4802: Copy { + dest: StatePartIndex(2623), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2632), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4803: Copy { + dest: StatePartIndex(2624), // (0x6) SlotDebugData { name: ".1.lut", ty: UInt<4> }, + src: StatePartIndex(2633), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + }, + 4804: Shl { + dest: StatePartIndex(2682), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2617), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 4805: Or { + dest: StatePartIndex(2683), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2616), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(2682), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4806: Shl { + dest: StatePartIndex(2684), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2619), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 4807: Or { + dest: StatePartIndex(2685), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2618), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2684), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 4808: Shl { + dest: StatePartIndex(2686), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2620), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 4809: Or { + dest: StatePartIndex(2687), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2685), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2686), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 4810: Shl { + dest: StatePartIndex(2688), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2687), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 4811: Or { + dest: StatePartIndex(2689), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2683), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(2688), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + }, + 4812: Shl { + dest: StatePartIndex(2690), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2621), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 4813: Or { + dest: StatePartIndex(2691), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2689), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(2690), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + }, + 4814: CastToUInt { + dest: StatePartIndex(2692), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2622), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 4815: Shl { + dest: StatePartIndex(2693), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2692), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 4816: Or { + dest: StatePartIndex(2694), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2691), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(2693), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4817: Or { + dest: StatePartIndex(2696), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2694), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2695), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4818: Copy { + dest: StatePartIndex(2697), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(2623), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4819: Shl { + dest: StatePartIndex(2698), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2697), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 4820: Or { + dest: StatePartIndex(2699), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2696), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2698), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 4821: Shl { + dest: StatePartIndex(2700), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2624), // (0x6) SlotDebugData { name: ".1.lut", ty: UInt<4> }, + rhs: 51, + }, + 4822: Or { + dest: StatePartIndex(2701), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2699), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(2700), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + }, + 4823: Shl { + dest: StatePartIndex(2702), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2701), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 4824: Or { + dest: StatePartIndex(2703), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2615), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(2702), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 4825: CastToUInt { + dest: StatePartIndex(2704), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2703), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 4826: Copy { + dest: StatePartIndex(2705), // (0xc0000000000002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2704), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:114:17 + 4827: BranchIfZero { + target: 4838, + value: StatePartIndex(2146), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:120:25 + 4828: BranchIfSmallNeImmediate { + target: 4838, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:29 + 4829: BranchIfSmallNeImmediate { + target: 4838, + lhs: StatePartIndex(108), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:130:37 + 4830: BranchIfZero { + target: 4832, + value: StatePartIndex(2176), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4831: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4832: BranchIfZero { + target: 4834, + value: StatePartIndex(2177), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4833: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4834: BranchIfZero { + target: 4836, + value: StatePartIndex(2178), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4835: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:130:37 + 4836: BranchIfZero { + target: 4838, + value: StatePartIndex(2179), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:131:41 + 4837: Copy { + dest: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + src: StatePartIndex(1936), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + // at: reg_alloc.rs:108:21 + 4838: AndBigWithSmallImmediate { + dest: StatePartIndex(184), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:184:29 + 4839: BranchIfSmallNeImmediate { + target: 4843, + lhs: StatePartIndex(157), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4840: BranchIfSmallNeImmediate { + target: 4843, + lhs: StatePartIndex(184), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:191:33 + 4841: Copy { + dest: StatePartIndex(2397), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1175), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4842: Copy { + dest: StatePartIndex(2398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1176), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4843: Copy { + dest: StatePartIndex(2137), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + src: StatePartIndex(2133), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::rename_table_special_1_src_2.data", ty: Enum {HdlNone, HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}})} }, + }, + 4844: SliceInt { + dest: StatePartIndex(2138), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2137), // (0x0) SlotDebugData { name: "", ty: UInt<7> }, + start: 1, + len: 6, + }, + 4845: SliceInt { + dest: StatePartIndex(2139), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2138), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 0, + len: 2, + }, + 4846: SliceInt { + dest: StatePartIndex(2140), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(2139), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 0, + len: 2, + }, + 4847: Copy { + dest: StatePartIndex(2136), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + src: StatePartIndex(2140), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4848: SliceInt { + dest: StatePartIndex(2142), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2138), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + start: 2, + len: 4, + }, + 4849: SliceInt { + dest: StatePartIndex(2143), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2142), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4850: Copy { + dest: StatePartIndex(2141), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2143), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4851: Copy { + dest: StatePartIndex(2134), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2136), // (0x0) SlotDebugData { name: ".adj_value", ty: UInt<2> }, + }, + 4852: Copy { + dest: StatePartIndex(2135), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2141), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4853: BranchIfSmallNeImmediate { + target: 4857, + lhs: StatePartIndex(157), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:186:36 + 4854: BranchIfSmallNeImmediate { + target: 4857, + lhs: StatePartIndex(184), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:189:33 + 4855: Copy { + dest: StatePartIndex(2397), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(2134), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4856: Copy { + dest: StatePartIndex(2398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(2135), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:184:29 + 4857: BranchIfSmallNeImmediate { + target: 4860, + lhs: StatePartIndex(157), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:185:33 + 4858: Copy { + dest: StatePartIndex(2397), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_num.adj_value", ty: UInt<2> }, + src: StatePartIndex(1990), // (0x0) SlotDebugData { name: ".unit_num.adj_value", ty: UInt<2> }, + }, + 4859: Copy { + dest: StatePartIndex(2398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_out_reg.value", ty: UInt<4> }, + src: StatePartIndex(1991), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + // at: reg_alloc.rs:43:1 + 4860: Shl { + dest: StatePartIndex(2450), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2398), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_out_reg.value", ty: UInt<4> }, + rhs: 2, + }, + 4861: Or { + dest: StatePartIndex(2451), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(2397), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_src_reg_1_2.unit_num.adj_value", ty: UInt<2> }, + rhs: StatePartIndex(2450), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4862: Copy { + dest: StatePartIndex(2443), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2447), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4863: Copy { + dest: StatePartIndex(2444), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2449), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4864: Copy { + dest: StatePartIndex(2445), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2451), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4865: Copy { + dest: StatePartIndex(2440), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2443), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4866: Copy { + dest: StatePartIndex(2441), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2444), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4867: Copy { + dest: StatePartIndex(2442), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2445), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4868: Copy { + dest: StatePartIndex(2433), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(231), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4869: Copy { + dest: StatePartIndex(2434), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(774), // (0x0) SlotDebugData { name: ".unit_out_reg.value", ty: UInt<4> }, + }, + 4870: Copy { + dest: StatePartIndex(2435), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2440), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4871: Copy { + dest: StatePartIndex(2436), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2441), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4872: Copy { + dest: StatePartIndex(2437), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2442), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4873: Copy { + dest: StatePartIndex(2438), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2460), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4874: Copy { + dest: StatePartIndex(2439), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2461), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4875: Copy { + dest: StatePartIndex(2425), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2433), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4876: Copy { + dest: StatePartIndex(2426), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2434), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4877: Copy { + dest: StatePartIndex(2427), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2435), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4878: Copy { + dest: StatePartIndex(2428), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2436), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4879: Copy { + dest: StatePartIndex(2429), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2437), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4880: Copy { + dest: StatePartIndex(2430), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2438), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4881: Copy { + dest: StatePartIndex(2431), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2439), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4882: Copy { + dest: StatePartIndex(2432), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(241), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4883: Copy { + dest: StatePartIndex(2413), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2425), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4884: Copy { + dest: StatePartIndex(2414), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2426), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4885: Copy { + dest: StatePartIndex(2415), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2427), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4886: Copy { + dest: StatePartIndex(2416), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2428), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4887: Copy { + dest: StatePartIndex(2417), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2429), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4888: Copy { + dest: StatePartIndex(2418), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2430), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4889: Copy { + dest: StatePartIndex(2419), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2431), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4890: Copy { + dest: StatePartIndex(2420), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2432), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4891: Copy { + dest: StatePartIndex(2421), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(242), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 4892: Copy { + dest: StatePartIndex(2422), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(243), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 4893: Copy { + dest: StatePartIndex(2423), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(244), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 4894: Copy { + dest: StatePartIndex(2424), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(245), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 4895: Copy { + dest: StatePartIndex(2400), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 4896: Copy { + dest: StatePartIndex(2401), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2413), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + }, + 4897: Copy { + dest: StatePartIndex(2402), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2414), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + }, + 4898: Copy { + dest: StatePartIndex(2403), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2415), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + }, + 4899: Copy { + dest: StatePartIndex(2404), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2416), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + }, + 4900: Copy { + dest: StatePartIndex(2405), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2417), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + }, + 4901: Copy { + dest: StatePartIndex(2406), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2418), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + }, + 4902: Copy { + dest: StatePartIndex(2407), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2419), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + }, + 4903: Copy { + dest: StatePartIndex(2408), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2420), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4904: Copy { + dest: StatePartIndex(2409), // (0x0) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + src: StatePartIndex(2421), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + }, + 4905: Copy { + dest: StatePartIndex(2410), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + src: StatePartIndex(2422), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + }, + 4906: Copy { + dest: StatePartIndex(2411), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + src: StatePartIndex(2423), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + }, + 4907: Copy { + dest: StatePartIndex(2412), // (0x0) SlotDebugData { name: ".1.add_pc", ty: Bool }, + src: StatePartIndex(2424), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + }, + 4908: Shl { + dest: StatePartIndex(2462), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2402), // (0x0) SlotDebugData { name: ".1.alu_common.common.dest.value", ty: UInt<4> }, + rhs: 0, + }, + 4909: Or { + dest: StatePartIndex(2463), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(2401), // (0x0) SlotDebugData { name: ".1.alu_common.common.prefix_pad", ty: UInt<0> }, + rhs: StatePartIndex(2462), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4910: Shl { + dest: StatePartIndex(2464), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2404), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[1]", ty: UInt<6> }, + rhs: 6, + }, + 4911: Or { + dest: StatePartIndex(2465), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + lhs: StatePartIndex(2403), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[0]", ty: UInt<6> }, + rhs: StatePartIndex(2464), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + }, + 4912: Shl { + dest: StatePartIndex(2466), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2405), // (0x0) SlotDebugData { name: ".1.alu_common.common.src[2]", ty: UInt<6> }, + rhs: 12, + }, + 4913: Or { + dest: StatePartIndex(2467), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + lhs: StatePartIndex(2465), // (0x0) SlotDebugData { name: "", ty: UInt<12> }, + rhs: StatePartIndex(2466), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + }, + 4914: Shl { + dest: StatePartIndex(2468), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2467), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + rhs: 4, + }, + 4915: Or { + dest: StatePartIndex(2469), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + lhs: StatePartIndex(2463), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(2468), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + }, + 4916: Shl { + dest: StatePartIndex(2470), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2406), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_low", ty: UInt<25> }, + rhs: 22, + }, + 4917: Or { + dest: StatePartIndex(2471), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + lhs: StatePartIndex(2469), // (0x0) SlotDebugData { name: "", ty: UInt<22> }, + rhs: StatePartIndex(2470), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + }, + 4918: CastToUInt { + dest: StatePartIndex(2472), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2407), // (0x0) SlotDebugData { name: ".1.alu_common.common.imm_sign", ty: SInt<1> }, + dest_width: 1, + }, + 4919: Shl { + dest: StatePartIndex(2473), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2472), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 47, + }, + 4920: Or { + dest: StatePartIndex(2474), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2471), // (0x0) SlotDebugData { name: "", ty: UInt<47> }, + rhs: StatePartIndex(2473), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4921: Or { + dest: StatePartIndex(2476), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + lhs: StatePartIndex(2474), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2475), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + }, + 4922: Copy { + dest: StatePartIndex(2477), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(2408), // (0x0) SlotDebugData { name: ".1.alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4923: Shl { + dest: StatePartIndex(2478), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2477), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: 48, + }, + 4924: Or { + dest: StatePartIndex(2479), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + lhs: StatePartIndex(2476), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + rhs: StatePartIndex(2478), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + }, + 4925: Copy { + dest: StatePartIndex(2480), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2409), // (0x0) SlotDebugData { name: ".1.invert_src0", ty: Bool }, + }, + 4926: Shl { + dest: StatePartIndex(2481), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2480), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 51, + }, + 4927: Or { + dest: StatePartIndex(2482), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + lhs: StatePartIndex(2479), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + rhs: StatePartIndex(2481), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + }, + 4928: Copy { + dest: StatePartIndex(2483), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2410), // (0x1) SlotDebugData { name: ".1.invert_carry_in", ty: Bool }, + }, + 4929: Shl { + dest: StatePartIndex(2484), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(2483), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 52, + }, + 4930: Or { + dest: StatePartIndex(2485), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + lhs: StatePartIndex(2482), // (0x0) SlotDebugData { name: "", ty: UInt<52> }, + rhs: StatePartIndex(2484), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + }, + 4931: Copy { + dest: StatePartIndex(2486), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2411), // (0x1) SlotDebugData { name: ".1.invert_carry_out", ty: Bool }, + }, + 4932: Shl { + dest: StatePartIndex(2487), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(2486), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 53, + }, + 4933: Or { + dest: StatePartIndex(2488), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<54> }, + lhs: StatePartIndex(2485), // (0x10000000000000) SlotDebugData { name: "", ty: UInt<53> }, + rhs: StatePartIndex(2487), // (0x20000000000000) SlotDebugData { name: "", ty: UInt<54> }, + }, + 4934: Copy { + dest: StatePartIndex(2489), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2412), // (0x0) SlotDebugData { name: ".1.add_pc", ty: Bool }, + }, + 4935: Shl { + dest: StatePartIndex(2490), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2489), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 54, + }, + 4936: Or { + dest: StatePartIndex(2491), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + lhs: StatePartIndex(2488), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<54> }, + rhs: StatePartIndex(2490), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + }, + 4937: Shl { + dest: StatePartIndex(2492), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2491), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + rhs: 2, + }, + 4938: Or { + dest: StatePartIndex(2493), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + lhs: StatePartIndex(2400), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(2492), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + 4939: CastToUInt { + dest: StatePartIndex(2494), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2493), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + dest_width: 57, + }, + 4940: Copy { + dest: StatePartIndex(2495), // (0xc0000000000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2494), // (0xc0000000000000) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: instruction.rs:477:1 + 4941: BranchIfSmallNeImmediate { + target: 4943, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x0, + }, + 4942: Copy { + dest: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2495), // (0xc0000000000000) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4943: BranchIfSmallNeImmediate { + target: 4945, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x1, + }, + 4944: Copy { + dest: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2608), // (0xc0000000000001) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4945: BranchIfSmallNeImmediate { + target: 4947, + lhs: StatePartIndex(17), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + rhs: 0x2, + }, + 4946: Copy { + dest: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2705), // (0xc0000000000002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4947: AndBigWithSmallImmediate { + dest: StatePartIndex(208), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 4948: Copy { + dest: StatePartIndex(2353), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 4949: SliceInt { + dest: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(2353), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 4950: SliceInt { + dest: StatePartIndex(2355), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 4951: SliceInt { + dest: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(2355), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 4952: SliceInt { + dest: StatePartIndex(2357), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 4953: SliceInt { + dest: StatePartIndex(2359), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 4954: SliceInt { + dest: StatePartIndex(2360), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2359), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 4955: Copy { + dest: StatePartIndex(2358), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2360), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 4956: SliceInt { + dest: StatePartIndex(2364), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 4957: SliceInt { + dest: StatePartIndex(2365), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2364), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 4958: SliceInt { + dest: StatePartIndex(2366), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2364), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 4959: SliceInt { + dest: StatePartIndex(2367), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2364), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 4960: Copy { + dest: StatePartIndex(2361), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2365), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4961: Copy { + dest: StatePartIndex(2362), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2366), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4962: Copy { + dest: StatePartIndex(2363), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2367), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 4963: SliceInt { + dest: StatePartIndex(2368), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 4964: SliceInt { + dest: StatePartIndex(2369), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2356), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 4965: CastToSInt { + dest: StatePartIndex(2370), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2369), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 4966: Copy { + dest: StatePartIndex(2346), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2357), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 4967: Copy { + dest: StatePartIndex(2347), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2358), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 4968: Copy { + dest: StatePartIndex(2348), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2361), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 4969: Copy { + dest: StatePartIndex(2349), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2362), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 4970: Copy { + dest: StatePartIndex(2350), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2363), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 4971: Copy { + dest: StatePartIndex(2351), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2368), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 4972: Copy { + dest: StatePartIndex(2352), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2370), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 4973: SliceInt { + dest: StatePartIndex(2371), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(2355), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 4974: Copy { + dest: StatePartIndex(2372), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2371), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 4975: Copy { + dest: StatePartIndex(2338), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2346), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 4976: Copy { + dest: StatePartIndex(2339), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2347), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 4977: Copy { + dest: StatePartIndex(2340), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2348), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 4978: Copy { + dest: StatePartIndex(2341), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2349), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 4979: Copy { + dest: StatePartIndex(2342), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2350), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 4980: Copy { + dest: StatePartIndex(2343), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2351), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 4981: Copy { + dest: StatePartIndex(2344), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2352), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 4982: Copy { + dest: StatePartIndex(2345), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2372), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4983: SliceInt { + dest: StatePartIndex(2373), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 4984: Copy { + dest: StatePartIndex(2374), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2373), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4985: SliceInt { + dest: StatePartIndex(2375), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 4986: Copy { + dest: StatePartIndex(2376), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2375), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4987: SliceInt { + dest: StatePartIndex(2377), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 4988: Copy { + dest: StatePartIndex(2378), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2377), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4989: SliceInt { + dest: StatePartIndex(2379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 4990: Copy { + dest: StatePartIndex(2380), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2379), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 4991: Copy { + dest: StatePartIndex(2326), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2338), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 4992: Copy { + dest: StatePartIndex(2327), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2339), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 4993: Copy { + dest: StatePartIndex(2328), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2340), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 4994: Copy { + dest: StatePartIndex(2329), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2341), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 4995: Copy { + dest: StatePartIndex(2330), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2342), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 4996: Copy { + dest: StatePartIndex(2331), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2343), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 4997: Copy { + dest: StatePartIndex(2332), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2344), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 4998: Copy { + dest: StatePartIndex(2333), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2345), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 4999: Copy { + dest: StatePartIndex(2334), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(2374), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5000: Copy { + dest: StatePartIndex(2335), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(2376), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 5001: Copy { + dest: StatePartIndex(2336), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(2378), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 5002: Copy { + dest: StatePartIndex(2337), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(2380), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: instruction.rs:477:1 + 5003: AndBigWithSmallImmediate { + dest: StatePartIndex(209), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(2333), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5004: SliceInt { + dest: StatePartIndex(2390), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2354), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5005: Copy { + dest: StatePartIndex(2381), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2338), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5006: Copy { + dest: StatePartIndex(2382), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2339), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5007: Copy { + dest: StatePartIndex(2383), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2340), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5008: Copy { + dest: StatePartIndex(2384), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2341), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5009: Copy { + dest: StatePartIndex(2385), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2342), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5010: Copy { + dest: StatePartIndex(2386), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2343), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5011: Copy { + dest: StatePartIndex(2387), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2344), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5012: Copy { + dest: StatePartIndex(2388), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2345), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5013: Copy { + dest: StatePartIndex(2389), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(2390), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: instruction.rs:477:1 + 5014: AndBigWithSmallImmediate { + dest: StatePartIndex(210), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(2388), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5015: Copy { + dest: StatePartIndex(2706), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(491), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 5016: Copy { + dest: StatePartIndex(2707), // (0xc0000000000002) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2325), // (0xc0000000000002) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5017: Copy { + dest: StatePartIndex(2708), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2707), // (0xc0000000000002) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5018: Shl { + dest: StatePartIndex(2709), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + lhs: StatePartIndex(2708), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 2, + }, + 5019: Or { + dest: StatePartIndex(2710), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + lhs: StatePartIndex(2706), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(2709), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + }, + 5020: CastToUInt { + dest: StatePartIndex(2711), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(2710), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + dest_width: 59, + }, + 5021: Copy { + dest: StatePartIndex(2712), // (0x300000000000008) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(2711), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: unit.rs:127:1 + 5022: BranchIfSmallNeImmediate { + target: 5024, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 5023: Copy { + dest: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(2712), // (0x300000000000008) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5024: BranchIfSmallNeImmediate { + target: 5026, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 5025: Copy { + dest: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(2893), // (0x9) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5026: BranchIfSmallNeImmediate { + target: 5028, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 5027: Copy { + dest: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(3052), // (0xa) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5028: AndBigWithSmallImmediate { + dest: StatePartIndex(202), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5029: Copy { + dest: StatePartIndex(2200), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5030: SliceInt { + dest: StatePartIndex(2201), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2200), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 57, + }, + 5031: Copy { + dest: StatePartIndex(2202), // (0xc0000000000002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(2201), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 5032: AndBigWithSmallImmediate { + dest: StatePartIndex(203), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(2202), // (0xc0000000000002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5033: Copy { + dest: StatePartIndex(2230), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(2202), // (0xc0000000000002) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5034: SliceInt { + dest: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(2230), // (0xc0000000000002) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5035: SliceInt { + dest: StatePartIndex(2232), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5036: SliceInt { + dest: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(2232), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5037: SliceInt { + dest: StatePartIndex(2234), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5038: SliceInt { + dest: StatePartIndex(2236), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5039: SliceInt { + dest: StatePartIndex(2237), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2236), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5040: Copy { + dest: StatePartIndex(2235), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2237), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5041: SliceInt { + dest: StatePartIndex(2241), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5042: SliceInt { + dest: StatePartIndex(2242), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2241), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5043: SliceInt { + dest: StatePartIndex(2243), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2241), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5044: SliceInt { + dest: StatePartIndex(2244), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2241), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5045: Copy { + dest: StatePartIndex(2238), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2242), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5046: Copy { + dest: StatePartIndex(2239), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2243), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5047: Copy { + dest: StatePartIndex(2240), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2244), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5048: SliceInt { + dest: StatePartIndex(2245), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5049: SliceInt { + dest: StatePartIndex(2246), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2233), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5050: CastToSInt { + dest: StatePartIndex(2247), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2246), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5051: Copy { + dest: StatePartIndex(2223), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2234), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5052: Copy { + dest: StatePartIndex(2224), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2235), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5053: Copy { + dest: StatePartIndex(2225), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2238), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5054: Copy { + dest: StatePartIndex(2226), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2239), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5055: Copy { + dest: StatePartIndex(2227), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2240), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5056: Copy { + dest: StatePartIndex(2228), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2245), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5057: Copy { + dest: StatePartIndex(2229), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2247), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5058: SliceInt { + dest: StatePartIndex(2248), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(2232), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5059: Copy { + dest: StatePartIndex(2249), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2248), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5060: Copy { + dest: StatePartIndex(2215), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2223), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5061: Copy { + dest: StatePartIndex(2216), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2224), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5062: Copy { + dest: StatePartIndex(2217), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2225), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5063: Copy { + dest: StatePartIndex(2218), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2226), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5064: Copy { + dest: StatePartIndex(2219), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2227), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5065: Copy { + dest: StatePartIndex(2220), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2228), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5066: Copy { + dest: StatePartIndex(2221), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2229), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5067: Copy { + dest: StatePartIndex(2222), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2249), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5068: SliceInt { + dest: StatePartIndex(2250), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5069: Copy { + dest: StatePartIndex(2251), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2250), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5070: SliceInt { + dest: StatePartIndex(2252), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5071: Copy { + dest: StatePartIndex(2253), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2252), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5072: SliceInt { + dest: StatePartIndex(2254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5073: Copy { + dest: StatePartIndex(2255), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5074: SliceInt { + dest: StatePartIndex(2256), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5075: Copy { + dest: StatePartIndex(2257), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2256), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5076: Copy { + dest: StatePartIndex(2203), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2215), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5077: Copy { + dest: StatePartIndex(2204), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2216), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5078: Copy { + dest: StatePartIndex(2205), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2217), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5079: Copy { + dest: StatePartIndex(2206), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2218), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5080: Copy { + dest: StatePartIndex(2207), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2219), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5081: Copy { + dest: StatePartIndex(2208), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2220), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5082: Copy { + dest: StatePartIndex(2209), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2221), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5083: Copy { + dest: StatePartIndex(2210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2222), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5084: Copy { + dest: StatePartIndex(2211), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(2251), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5085: Copy { + dest: StatePartIndex(2212), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(2253), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 5086: Copy { + dest: StatePartIndex(2213), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(2255), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 5087: Copy { + dest: StatePartIndex(2214), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(2257), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 5088: AndBigWithSmallImmediate { + dest: StatePartIndex(204), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(2210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5089: SliceInt { + dest: StatePartIndex(2267), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2231), // (0x30000000000000) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5090: Copy { + dest: StatePartIndex(2258), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(2215), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5091: Copy { + dest: StatePartIndex(2259), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2216), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5092: Copy { + dest: StatePartIndex(2260), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2217), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5093: Copy { + dest: StatePartIndex(2261), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2218), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5094: Copy { + dest: StatePartIndex(2262), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2219), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5095: Copy { + dest: StatePartIndex(2263), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2220), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5096: Copy { + dest: StatePartIndex(2264), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2221), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5097: Copy { + dest: StatePartIndex(2265), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(2222), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5098: Copy { + dest: StatePartIndex(2266), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(2267), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 5099: AndBigWithSmallImmediate { + dest: StatePartIndex(205), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(2265), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5100: SliceInt { + dest: StatePartIndex(2268), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2200), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 50, + }, + 5101: Copy { + dest: StatePartIndex(2269), // (0x2) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(2268), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: unit.rs:127:1 + 5102: AndBigWithSmallImmediate { + dest: StatePartIndex(206), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(2269), // (0x2) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5103: Copy { + dest: StatePartIndex(2284), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2269), // (0x2) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 5104: SliceInt { + dest: StatePartIndex(2285), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2284), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 5105: SliceInt { + dest: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2285), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 5106: SliceInt { + dest: StatePartIndex(2287), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 5107: SliceInt { + dest: StatePartIndex(2289), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 5108: SliceInt { + dest: StatePartIndex(2290), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2289), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5109: Copy { + dest: StatePartIndex(2288), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2290), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5110: SliceInt { + dest: StatePartIndex(2294), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 5111: SliceInt { + dest: StatePartIndex(2295), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2294), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5112: SliceInt { + dest: StatePartIndex(2296), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2294), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5113: SliceInt { + dest: StatePartIndex(2297), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2294), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5114: Copy { + dest: StatePartIndex(2291), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2295), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5115: Copy { + dest: StatePartIndex(2292), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2296), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5116: Copy { + dest: StatePartIndex(2293), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2297), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5117: SliceInt { + dest: StatePartIndex(2298), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 5118: SliceInt { + dest: StatePartIndex(2299), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2286), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 5119: CastToSInt { + dest: StatePartIndex(2300), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2299), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5120: Copy { + dest: StatePartIndex(2277), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2287), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5121: Copy { + dest: StatePartIndex(2278), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2288), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5122: Copy { + dest: StatePartIndex(2279), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2291), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5123: Copy { + dest: StatePartIndex(2280), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2292), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5124: Copy { + dest: StatePartIndex(2281), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2293), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5125: Copy { + dest: StatePartIndex(2282), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2298), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5126: Copy { + dest: StatePartIndex(2283), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2300), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5127: Copy { + dest: StatePartIndex(2270), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2277), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 5128: Copy { + dest: StatePartIndex(2271), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(2278), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5129: Copy { + dest: StatePartIndex(2272), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(2279), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5130: Copy { + dest: StatePartIndex(2273), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(2280), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5131: Copy { + dest: StatePartIndex(2274), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(2281), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5132: Copy { + dest: StatePartIndex(2275), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(2282), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5133: Copy { + dest: StatePartIndex(2276), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(2283), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5134: Copy { + dest: StatePartIndex(2301), // (0x2) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(2268), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: unit.rs:127:1 + 5135: AndBigWithSmallImmediate { + dest: StatePartIndex(207), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(2301), // (0x2) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5136: Copy { + dest: StatePartIndex(2309), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(2301), // (0x2) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 5137: SliceInt { + dest: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(2309), // (0x2) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 5138: SliceInt { + dest: StatePartIndex(2311), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 5139: SliceInt { + dest: StatePartIndex(2313), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 5140: SliceInt { + dest: StatePartIndex(2314), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(2313), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5141: Copy { + dest: StatePartIndex(2312), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(2314), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5142: SliceInt { + dest: StatePartIndex(2318), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 5143: SliceInt { + dest: StatePartIndex(2319), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2318), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5144: SliceInt { + dest: StatePartIndex(2320), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2318), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5145: SliceInt { + dest: StatePartIndex(2321), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(2318), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5146: Copy { + dest: StatePartIndex(2315), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(2319), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5147: Copy { + dest: StatePartIndex(2316), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(2320), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5148: Copy { + dest: StatePartIndex(2317), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(2321), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5149: SliceInt { + dest: StatePartIndex(2322), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 5150: SliceInt { + dest: StatePartIndex(2323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(2310), // (0x1) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 5151: CastToSInt { + dest: StatePartIndex(2324), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(2323), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5152: Copy { + dest: StatePartIndex(2302), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(2311), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5153: Copy { + dest: StatePartIndex(2303), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(2312), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5154: Copy { + dest: StatePartIndex(2304), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(2315), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5155: Copy { + dest: StatePartIndex(2305), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(2316), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5156: Copy { + dest: StatePartIndex(2306), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(2317), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5157: Copy { + dest: StatePartIndex(2307), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(2322), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5158: Copy { + dest: StatePartIndex(2308), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(2324), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5159: Copy { + dest: StatePartIndex(3053), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5160: Copy { + dest: StatePartIndex(3054), // (0x300000000000008) SlotDebugData { name: ".1", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(2199), // (0x300000000000008) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::mapped_regs", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5161: Copy { + dest: StatePartIndex(3055), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(3054), // (0x300000000000008) SlotDebugData { name: ".1", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5162: Shl { + dest: StatePartIndex(3056), // (0x600000000000010) SlotDebugData { name: "", ty: UInt<60> }, + lhs: StatePartIndex(3055), // (0x300000000000008) SlotDebugData { name: "", ty: UInt<59> }, + rhs: 1, + }, + 5163: Or { + dest: StatePartIndex(3057), // (0x600000000000011) SlotDebugData { name: "", ty: UInt<60> }, + lhs: StatePartIndex(3053), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3056), // (0x600000000000010) SlotDebugData { name: "", ty: UInt<60> }, + }, + 5164: CastToUInt { + dest: StatePartIndex(3058), // (0x600000000000011) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(3057), // (0x600000000000011) SlotDebugData { name: "", ty: UInt<60> }, + dest_width: 60, + }, + 5165: Copy { + dest: StatePartIndex(3059), // (0x600000000000011) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(3058), // (0x600000000000011) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:159:9 + 5166: BranchIfSmallNeImmediate { + target: 5169, + lhs: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:165:13 + 5167: BranchIfSmallNeImmediate { + target: 5169, + lhs: StatePartIndex(109), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:167:17 + 5168: Copy { + dest: StatePartIndex(504), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[1]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + src: StatePartIndex(3059), // (0x600000000000011) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + // at: reg_alloc.rs:75:24 + 5169: AndBigWithSmallImmediate { + dest: StatePartIndex(101), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(504), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[1]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:314:25 + 5170: BranchIfSmallNeImmediate { + target: 5173, + lhs: StatePartIndex(101), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + 5171: Copy { + dest: StatePartIndex(3762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5172: Copy { + dest: StatePartIndex(4551), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3584), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 5173: Copy { + dest: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(504), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::renamed_mops[1]", ty: Enum {HdlNone, HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})} }, + }, + 5174: SliceInt { + dest: StatePartIndex(634), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 5175: Copy { + dest: StatePartIndex(635), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(634), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + }, + // at: reg_alloc.rs:75:24 + 5176: AndBigWithSmallImmediate { + dest: StatePartIndex(102), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(635), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5177: Copy { + dest: StatePartIndex(636), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(635), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 5178: SliceInt { + dest: StatePartIndex(637), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(636), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 57, + }, + 5179: Copy { + dest: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(637), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:75:24 + 5180: AndBigWithSmallImmediate { + dest: StatePartIndex(103), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5181: Copy { + dest: StatePartIndex(666), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5182: SliceInt { + dest: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(666), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5183: SliceInt { + dest: StatePartIndex(668), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5184: SliceInt { + dest: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(668), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5185: SliceInt { + dest: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5186: SliceInt { + dest: StatePartIndex(672), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5187: SliceInt { + dest: StatePartIndex(673), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(672), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5188: Copy { + dest: StatePartIndex(671), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(673), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5189: SliceInt { + dest: StatePartIndex(677), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5190: SliceInt { + dest: StatePartIndex(678), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(677), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5191: SliceInt { + dest: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(677), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5192: SliceInt { + dest: StatePartIndex(680), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(677), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5193: Copy { + dest: StatePartIndex(674), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(678), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5194: Copy { + dest: StatePartIndex(675), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5195: Copy { + dest: StatePartIndex(676), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(680), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5196: SliceInt { + dest: StatePartIndex(681), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5197: SliceInt { + dest: StatePartIndex(682), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5198: CastToSInt { + dest: StatePartIndex(683), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(682), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5199: Copy { + dest: StatePartIndex(659), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5200: Copy { + dest: StatePartIndex(660), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(671), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5201: Copy { + dest: StatePartIndex(661), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(674), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5202: Copy { + dest: StatePartIndex(662), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(675), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5203: Copy { + dest: StatePartIndex(663), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(676), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5204: Copy { + dest: StatePartIndex(664), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(681), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5205: Copy { + dest: StatePartIndex(665), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(683), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5206: SliceInt { + dest: StatePartIndex(684), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(668), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5207: Copy { + dest: StatePartIndex(685), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(684), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5208: Copy { + dest: StatePartIndex(651), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(659), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5209: Copy { + dest: StatePartIndex(652), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(660), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5210: Copy { + dest: StatePartIndex(653), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(661), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5211: Copy { + dest: StatePartIndex(654), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(662), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5212: Copy { + dest: StatePartIndex(655), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(663), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5213: Copy { + dest: StatePartIndex(656), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(664), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5214: Copy { + dest: StatePartIndex(657), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(665), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5215: Copy { + dest: StatePartIndex(658), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(685), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5216: SliceInt { + dest: StatePartIndex(686), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5217: Copy { + dest: StatePartIndex(687), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(686), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5218: SliceInt { + dest: StatePartIndex(688), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5219: Copy { + dest: StatePartIndex(689), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(688), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5220: SliceInt { + dest: StatePartIndex(690), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5221: Copy { + dest: StatePartIndex(691), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(690), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5222: SliceInt { + dest: StatePartIndex(692), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5223: Copy { + dest: StatePartIndex(693), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(692), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5224: Copy { + dest: StatePartIndex(639), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(651), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5225: Copy { + dest: StatePartIndex(640), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(652), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5226: Copy { + dest: StatePartIndex(641), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(653), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5227: Copy { + dest: StatePartIndex(642), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(654), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5228: Copy { + dest: StatePartIndex(643), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(655), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5229: Copy { + dest: StatePartIndex(644), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(656), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5230: Copy { + dest: StatePartIndex(645), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(657), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5231: Copy { + dest: StatePartIndex(646), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(658), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5232: Copy { + dest: StatePartIndex(647), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(687), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5233: Copy { + dest: StatePartIndex(648), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(689), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5234: Copy { + dest: StatePartIndex(649), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(691), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5235: Copy { + dest: StatePartIndex(650), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(693), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:75:24 + 5236: AndBigWithSmallImmediate { + dest: StatePartIndex(104), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(646), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5237: SliceInt { + dest: StatePartIndex(703), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(667), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5238: Copy { + dest: StatePartIndex(694), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(651), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5239: Copy { + dest: StatePartIndex(695), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(652), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5240: Copy { + dest: StatePartIndex(696), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(653), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5241: Copy { + dest: StatePartIndex(697), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(654), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5242: Copy { + dest: StatePartIndex(698), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(655), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5243: Copy { + dest: StatePartIndex(699), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(656), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5244: Copy { + dest: StatePartIndex(700), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(657), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5245: Copy { + dest: StatePartIndex(701), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(658), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5246: Copy { + dest: StatePartIndex(702), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(703), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:75:24 + 5247: AndBigWithSmallImmediate { + dest: StatePartIndex(105), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(701), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5248: Copy { + dest: StatePartIndex(3900), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5249: Copy { + dest: StatePartIndex(3901), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5250: Copy { + dest: StatePartIndex(3902), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3901), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5251: Shl { + dest: StatePartIndex(3903), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3902), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 5252: Or { + dest: StatePartIndex(3904), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3900), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3903), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 5253: CastToUInt { + dest: StatePartIndex(3905), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3904), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 5254: Copy { + dest: StatePartIndex(3906), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3905), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: unit.rs:127:1 + 5255: BranchIfSmallNeImmediate { + target: 5257, + lhs: StatePartIndex(102), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 5256: Copy { + dest: StatePartIndex(3831), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3906), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5257: AndBigWithSmallImmediate { + dest: StatePartIndex(264), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3831), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5258: Copy { + dest: StatePartIndex(3832), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3831), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5259: SliceInt { + dest: StatePartIndex(3833), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3832), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5260: Copy { + dest: StatePartIndex(3834), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3833), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 5261: AndBigWithSmallImmediate { + dest: StatePartIndex(265), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3834), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5262: Copy { + dest: StatePartIndex(3862), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3834), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5263: SliceInt { + dest: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3862), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5264: SliceInt { + dest: StatePartIndex(3864), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5265: SliceInt { + dest: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3864), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5266: SliceInt { + dest: StatePartIndex(3866), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5267: SliceInt { + dest: StatePartIndex(3868), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5268: SliceInt { + dest: StatePartIndex(3869), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3868), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5269: Copy { + dest: StatePartIndex(3867), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3869), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5270: SliceInt { + dest: StatePartIndex(3873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5271: SliceInt { + dest: StatePartIndex(3874), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5272: SliceInt { + dest: StatePartIndex(3875), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5273: SliceInt { + dest: StatePartIndex(3876), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3873), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5274: Copy { + dest: StatePartIndex(3870), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3874), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5275: Copy { + dest: StatePartIndex(3871), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3875), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5276: Copy { + dest: StatePartIndex(3872), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3876), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5277: SliceInt { + dest: StatePartIndex(3877), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5278: SliceInt { + dest: StatePartIndex(3878), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3865), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5279: CastToSInt { + dest: StatePartIndex(3879), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3878), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5280: Copy { + dest: StatePartIndex(3855), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3866), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5281: Copy { + dest: StatePartIndex(3856), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3867), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5282: Copy { + dest: StatePartIndex(3857), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3870), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5283: Copy { + dest: StatePartIndex(3858), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3871), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5284: Copy { + dest: StatePartIndex(3859), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3872), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5285: Copy { + dest: StatePartIndex(3860), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3877), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5286: Copy { + dest: StatePartIndex(3861), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3879), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5287: SliceInt { + dest: StatePartIndex(3880), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3864), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5288: Copy { + dest: StatePartIndex(3881), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3880), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5289: Copy { + dest: StatePartIndex(3847), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3855), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5290: Copy { + dest: StatePartIndex(3848), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3856), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5291: Copy { + dest: StatePartIndex(3849), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3857), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5292: Copy { + dest: StatePartIndex(3850), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3858), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5293: Copy { + dest: StatePartIndex(3851), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3859), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5294: Copy { + dest: StatePartIndex(3852), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3860), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5295: Copy { + dest: StatePartIndex(3853), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3861), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5296: Copy { + dest: StatePartIndex(3854), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3881), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5297: SliceInt { + dest: StatePartIndex(3882), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5298: Copy { + dest: StatePartIndex(3883), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3882), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5299: SliceInt { + dest: StatePartIndex(3884), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5300: Copy { + dest: StatePartIndex(3885), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3884), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5301: SliceInt { + dest: StatePartIndex(3886), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5302: Copy { + dest: StatePartIndex(3887), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3886), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5303: SliceInt { + dest: StatePartIndex(3888), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5304: Copy { + dest: StatePartIndex(3889), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3888), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5305: Copy { + dest: StatePartIndex(3835), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3847), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5306: Copy { + dest: StatePartIndex(3836), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3848), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5307: Copy { + dest: StatePartIndex(3837), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3849), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5308: Copy { + dest: StatePartIndex(3838), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3850), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5309: Copy { + dest: StatePartIndex(3839), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3851), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5310: Copy { + dest: StatePartIndex(3840), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3852), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5311: Copy { + dest: StatePartIndex(3841), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3853), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5312: Copy { + dest: StatePartIndex(3842), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3854), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5313: Copy { + dest: StatePartIndex(3843), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3883), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5314: Copy { + dest: StatePartIndex(3844), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3885), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5315: Copy { + dest: StatePartIndex(3845), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3887), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5316: Copy { + dest: StatePartIndex(3846), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3889), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 5317: AndBigWithSmallImmediate { + dest: StatePartIndex(266), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3842), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5318: SliceInt { + dest: StatePartIndex(3899), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3863), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5319: Copy { + dest: StatePartIndex(3890), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3847), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5320: Copy { + dest: StatePartIndex(3891), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3848), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5321: Copy { + dest: StatePartIndex(3892), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3849), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5322: Copy { + dest: StatePartIndex(3893), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3850), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5323: Copy { + dest: StatePartIndex(3894), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3851), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5324: Copy { + dest: StatePartIndex(3895), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3852), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5325: Copy { + dest: StatePartIndex(3896), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3853), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5326: Copy { + dest: StatePartIndex(3897), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3854), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5327: Copy { + dest: StatePartIndex(3898), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3899), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 5328: AndBigWithSmallImmediate { + dest: StatePartIndex(267), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3897), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:314:25 + 5329: BranchIfSmallNeImmediate { + target: 5331, + lhs: StatePartIndex(101), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 5330: Copy { + dest: StatePartIndex(3762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3831), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5331: AndBigWithSmallImmediate { + dest: StatePartIndex(260), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:308:13 + 5332: BranchIfSmallNeImmediate { + target: 5336, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 5333: BranchIfZero { + target: 5336, + value: StatePartIndex(3761), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 5334: BranchIfSmallNeImmediate { + target: 5336, + lhs: StatePartIndex(260), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:318:25 + 5335: Copy { + dest: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3740), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 5336: Copy { + dest: StatePartIndex(3763), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3762), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5337: SliceInt { + dest: StatePartIndex(3764), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3763), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5338: Copy { + dest: StatePartIndex(3765), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3764), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:314:25 + 5339: AndBigWithSmallImmediate { + dest: StatePartIndex(261), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3765), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5340: Copy { + dest: StatePartIndex(3793), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3765), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5341: SliceInt { + dest: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3793), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5342: SliceInt { + dest: StatePartIndex(3795), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5343: SliceInt { + dest: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3795), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5344: SliceInt { + dest: StatePartIndex(3797), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5345: SliceInt { + dest: StatePartIndex(3799), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5346: SliceInt { + dest: StatePartIndex(3800), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3799), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5347: Copy { + dest: StatePartIndex(3798), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3800), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5348: SliceInt { + dest: StatePartIndex(3804), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5349: SliceInt { + dest: StatePartIndex(3805), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3804), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5350: SliceInt { + dest: StatePartIndex(3806), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3804), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5351: SliceInt { + dest: StatePartIndex(3807), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3804), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5352: Copy { + dest: StatePartIndex(3801), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3805), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5353: Copy { + dest: StatePartIndex(3802), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3806), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5354: Copy { + dest: StatePartIndex(3803), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3807), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5355: SliceInt { + dest: StatePartIndex(3808), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5356: SliceInt { + dest: StatePartIndex(3809), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3796), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5357: CastToSInt { + dest: StatePartIndex(3810), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3809), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5358: Copy { + dest: StatePartIndex(3786), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3797), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5359: Copy { + dest: StatePartIndex(3787), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3798), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5360: Copy { + dest: StatePartIndex(3788), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3801), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5361: Copy { + dest: StatePartIndex(3789), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3802), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5362: Copy { + dest: StatePartIndex(3790), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3803), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5363: Copy { + dest: StatePartIndex(3791), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3808), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5364: Copy { + dest: StatePartIndex(3792), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3810), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5365: SliceInt { + dest: StatePartIndex(3811), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3795), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5366: Copy { + dest: StatePartIndex(3812), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3811), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5367: Copy { + dest: StatePartIndex(3778), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3786), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5368: Copy { + dest: StatePartIndex(3779), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3787), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5369: Copy { + dest: StatePartIndex(3780), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3788), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5370: Copy { + dest: StatePartIndex(3781), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3789), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5371: Copy { + dest: StatePartIndex(3782), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3790), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5372: Copy { + dest: StatePartIndex(3783), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3791), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5373: Copy { + dest: StatePartIndex(3784), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3792), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5374: Copy { + dest: StatePartIndex(3785), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3812), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5375: SliceInt { + dest: StatePartIndex(3813), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5376: Copy { + dest: StatePartIndex(3814), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3813), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5377: SliceInt { + dest: StatePartIndex(3815), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5378: Copy { + dest: StatePartIndex(3816), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3815), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5379: SliceInt { + dest: StatePartIndex(3817), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5380: Copy { + dest: StatePartIndex(3818), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3817), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5381: SliceInt { + dest: StatePartIndex(3819), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5382: Copy { + dest: StatePartIndex(3820), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3819), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5383: Copy { + dest: StatePartIndex(3766), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3778), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5384: Copy { + dest: StatePartIndex(3767), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3779), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5385: Copy { + dest: StatePartIndex(3768), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3780), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5386: Copy { + dest: StatePartIndex(3769), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3781), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5387: Copy { + dest: StatePartIndex(3770), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3782), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5388: Copy { + dest: StatePartIndex(3771), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3783), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5389: Copy { + dest: StatePartIndex(3772), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3784), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5390: Copy { + dest: StatePartIndex(3773), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3785), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5391: Copy { + dest: StatePartIndex(3774), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3814), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5392: Copy { + dest: StatePartIndex(3775), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3816), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5393: Copy { + dest: StatePartIndex(3776), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3818), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5394: Copy { + dest: StatePartIndex(3777), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3820), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:314:25 + 5395: AndBigWithSmallImmediate { + dest: StatePartIndex(262), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3773), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5396: SliceInt { + dest: StatePartIndex(3830), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3794), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5397: Copy { + dest: StatePartIndex(3821), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3778), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5398: Copy { + dest: StatePartIndex(3822), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3779), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5399: Copy { + dest: StatePartIndex(3823), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3780), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5400: Copy { + dest: StatePartIndex(3824), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3781), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5401: Copy { + dest: StatePartIndex(3825), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3782), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5402: Copy { + dest: StatePartIndex(3826), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3783), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5403: Copy { + dest: StatePartIndex(3827), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3784), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5404: Copy { + dest: StatePartIndex(3828), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3785), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5405: Copy { + dest: StatePartIndex(3829), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3830), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:314:25 + 5406: AndBigWithSmallImmediate { + dest: StatePartIndex(263), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3828), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5407: Copy { + dest: StatePartIndex(3907), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5408: Copy { + dest: StatePartIndex(3908), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3765), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5409: Copy { + dest: StatePartIndex(3909), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3908), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5410: Shl { + dest: StatePartIndex(3910), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3909), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 5411: Or { + dest: StatePartIndex(3911), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(3907), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(3910), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 5412: CastToUInt { + dest: StatePartIndex(3912), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3911), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 5413: Copy { + dest: StatePartIndex(3913), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3912), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: reg_alloc.rs:308:13 + 5414: BranchIfSmallNeImmediate { + target: 5418, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 5415: BranchIfZero { + target: 5418, + value: StatePartIndex(3761), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 5416: BranchIfSmallNeImmediate { + target: 5418, + lhs: StatePartIndex(260), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:316:25 + 5417: Copy { + dest: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3913), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:271:13 + 5418: Copy { + dest: StatePartIndex(3091), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: alu_branch.rs:21:11 + 5419: AndBigWithSmallImmediate { + dest: StatePartIndex(217), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3091), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: alu_branch.rs:15:1 + 5420: Copy { + dest: StatePartIndex(3093), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3091), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5421: SliceInt { + dest: StatePartIndex(3094), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3093), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5422: Copy { + dest: StatePartIndex(3095), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3094), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: alu_branch.rs:21:11 + 5423: AndBigWithSmallImmediate { + dest: StatePartIndex(218), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3095), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: alu_branch.rs:15:1 + 5424: Copy { + dest: StatePartIndex(3123), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3095), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5425: SliceInt { + dest: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3123), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5426: SliceInt { + dest: StatePartIndex(3125), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5427: SliceInt { + dest: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3125), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5428: SliceInt { + dest: StatePartIndex(3127), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5429: SliceInt { + dest: StatePartIndex(3129), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5430: SliceInt { + dest: StatePartIndex(3130), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3129), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5431: Copy { + dest: StatePartIndex(3128), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3130), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5432: SliceInt { + dest: StatePartIndex(3134), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5433: SliceInt { + dest: StatePartIndex(3135), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3134), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5434: SliceInt { + dest: StatePartIndex(3136), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3134), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5435: SliceInt { + dest: StatePartIndex(3137), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3134), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5436: Copy { + dest: StatePartIndex(3131), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3135), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5437: Copy { + dest: StatePartIndex(3132), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3136), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5438: Copy { + dest: StatePartIndex(3133), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3137), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5439: SliceInt { + dest: StatePartIndex(3138), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5440: SliceInt { + dest: StatePartIndex(3139), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3126), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5441: CastToSInt { + dest: StatePartIndex(3140), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3139), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5442: Copy { + dest: StatePartIndex(3116), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3127), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5443: Copy { + dest: StatePartIndex(3117), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3128), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5444: Copy { + dest: StatePartIndex(3118), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3131), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5445: Copy { + dest: StatePartIndex(3119), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3132), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5446: Copy { + dest: StatePartIndex(3120), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3133), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5447: Copy { + dest: StatePartIndex(3121), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3138), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5448: Copy { + dest: StatePartIndex(3122), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3140), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5449: SliceInt { + dest: StatePartIndex(3141), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3125), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5450: Copy { + dest: StatePartIndex(3142), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3141), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5451: Copy { + dest: StatePartIndex(3108), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3116), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5452: Copy { + dest: StatePartIndex(3109), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3117), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5453: Copy { + dest: StatePartIndex(3110), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3118), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5454: Copy { + dest: StatePartIndex(3111), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3119), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5455: Copy { + dest: StatePartIndex(3112), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3120), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5456: Copy { + dest: StatePartIndex(3113), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3121), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5457: Copy { + dest: StatePartIndex(3114), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3122), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5458: Copy { + dest: StatePartIndex(3115), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3142), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5459: SliceInt { + dest: StatePartIndex(3143), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5460: Copy { + dest: StatePartIndex(3144), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3143), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5461: SliceInt { + dest: StatePartIndex(3145), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5462: Copy { + dest: StatePartIndex(3146), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3145), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5463: SliceInt { + dest: StatePartIndex(3147), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5464: Copy { + dest: StatePartIndex(3148), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3147), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5465: SliceInt { + dest: StatePartIndex(3149), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5466: Copy { + dest: StatePartIndex(3150), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3149), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5467: Copy { + dest: StatePartIndex(3096), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3108), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5468: Copy { + dest: StatePartIndex(3097), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3109), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5469: Copy { + dest: StatePartIndex(3098), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3110), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5470: Copy { + dest: StatePartIndex(3099), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3111), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5471: Copy { + dest: StatePartIndex(3100), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3112), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5472: Copy { + dest: StatePartIndex(3101), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3113), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5473: Copy { + dest: StatePartIndex(3102), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3114), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5474: Copy { + dest: StatePartIndex(3103), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3115), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5475: Copy { + dest: StatePartIndex(3104), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3144), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5476: Copy { + dest: StatePartIndex(3105), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3146), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5477: Copy { + dest: StatePartIndex(3106), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3148), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5478: Copy { + dest: StatePartIndex(3107), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3150), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: alu_branch.rs:21:11 + 5479: AndBigWithSmallImmediate { + dest: StatePartIndex(219), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3103), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: alu_branch.rs:15:1 + 5480: SliceInt { + dest: StatePartIndex(3160), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3124), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5481: Copy { + dest: StatePartIndex(3151), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3108), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5482: Copy { + dest: StatePartIndex(3152), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3109), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5483: Copy { + dest: StatePartIndex(3153), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3110), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5484: Copy { + dest: StatePartIndex(3154), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3111), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5485: Copy { + dest: StatePartIndex(3155), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3112), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5486: Copy { + dest: StatePartIndex(3156), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3113), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5487: Copy { + dest: StatePartIndex(3157), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3114), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5488: Copy { + dest: StatePartIndex(3158), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3115), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5489: Copy { + dest: StatePartIndex(3159), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3160), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: alu_branch.rs:21:11 + 5490: AndBigWithSmallImmediate { + dest: StatePartIndex(220), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3158), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:271:13 + 5491: AndBigWithSmallImmediate { + dest: StatePartIndex(221), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5492: Copy { + dest: StatePartIndex(3161), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3087), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5493: SliceInt { + dest: StatePartIndex(3162), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3161), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5494: Copy { + dest: StatePartIndex(3163), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3162), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:271:13 + 5495: AndBigWithSmallImmediate { + dest: StatePartIndex(222), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3163), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5496: Copy { + dest: StatePartIndex(3191), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3163), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5497: SliceInt { + dest: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3191), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5498: SliceInt { + dest: StatePartIndex(3193), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5499: SliceInt { + dest: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3193), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5500: SliceInt { + dest: StatePartIndex(3195), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5501: SliceInt { + dest: StatePartIndex(3197), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5502: SliceInt { + dest: StatePartIndex(3198), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3197), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5503: Copy { + dest: StatePartIndex(3196), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3198), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5504: SliceInt { + dest: StatePartIndex(3202), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5505: SliceInt { + dest: StatePartIndex(3203), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3202), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5506: SliceInt { + dest: StatePartIndex(3204), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3202), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5507: SliceInt { + dest: StatePartIndex(3205), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3202), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5508: Copy { + dest: StatePartIndex(3199), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3203), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5509: Copy { + dest: StatePartIndex(3200), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3204), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5510: Copy { + dest: StatePartIndex(3201), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3205), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5511: SliceInt { + dest: StatePartIndex(3206), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5512: SliceInt { + dest: StatePartIndex(3207), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3194), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5513: CastToSInt { + dest: StatePartIndex(3208), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3207), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5514: Copy { + dest: StatePartIndex(3184), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3195), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5515: Copy { + dest: StatePartIndex(3185), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3196), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5516: Copy { + dest: StatePartIndex(3186), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3199), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5517: Copy { + dest: StatePartIndex(3187), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3200), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5518: Copy { + dest: StatePartIndex(3188), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3201), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5519: Copy { + dest: StatePartIndex(3189), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3206), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5520: Copy { + dest: StatePartIndex(3190), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3208), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5521: SliceInt { + dest: StatePartIndex(3209), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3193), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5522: Copy { + dest: StatePartIndex(3210), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3209), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5523: Copy { + dest: StatePartIndex(3176), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3184), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5524: Copy { + dest: StatePartIndex(3177), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3185), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5525: Copy { + dest: StatePartIndex(3178), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3186), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5526: Copy { + dest: StatePartIndex(3179), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3187), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5527: Copy { + dest: StatePartIndex(3180), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3188), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5528: Copy { + dest: StatePartIndex(3181), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3189), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5529: Copy { + dest: StatePartIndex(3182), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3190), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5530: Copy { + dest: StatePartIndex(3183), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3210), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5531: SliceInt { + dest: StatePartIndex(3211), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5532: Copy { + dest: StatePartIndex(3212), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3211), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5533: SliceInt { + dest: StatePartIndex(3213), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5534: Copy { + dest: StatePartIndex(3214), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3213), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5535: SliceInt { + dest: StatePartIndex(3215), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5536: Copy { + dest: StatePartIndex(3216), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3215), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5537: SliceInt { + dest: StatePartIndex(3217), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5538: Copy { + dest: StatePartIndex(3218), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3217), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5539: Copy { + dest: StatePartIndex(3164), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3176), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5540: Copy { + dest: StatePartIndex(3165), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3177), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5541: Copy { + dest: StatePartIndex(3166), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3178), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5542: Copy { + dest: StatePartIndex(3167), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3179), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5543: Copy { + dest: StatePartIndex(3168), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3180), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5544: Copy { + dest: StatePartIndex(3169), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3181), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5545: Copy { + dest: StatePartIndex(3170), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3182), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5546: Copy { + dest: StatePartIndex(3171), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3183), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5547: Copy { + dest: StatePartIndex(3172), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3212), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5548: Copy { + dest: StatePartIndex(3173), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3214), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5549: Copy { + dest: StatePartIndex(3174), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3216), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5550: Copy { + dest: StatePartIndex(3175), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3218), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:271:13 + 5551: AndBigWithSmallImmediate { + dest: StatePartIndex(223), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3171), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5552: SliceInt { + dest: StatePartIndex(3228), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3192), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5553: Copy { + dest: StatePartIndex(3219), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3176), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5554: Copy { + dest: StatePartIndex(3220), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3177), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5555: Copy { + dest: StatePartIndex(3221), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3178), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5556: Copy { + dest: StatePartIndex(3222), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3179), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5557: Copy { + dest: StatePartIndex(3223), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3180), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5558: Copy { + dest: StatePartIndex(3224), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3181), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5559: Copy { + dest: StatePartIndex(3225), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3182), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5560: Copy { + dest: StatePartIndex(3226), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3183), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5561: Copy { + dest: StatePartIndex(3227), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3228), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:271:13 + 5562: AndBigWithSmallImmediate { + dest: StatePartIndex(224), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3226), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: unit.rs:127:1 + 5563: BranchIfSmallNeImmediate { + target: 5565, + lhs: StatePartIndex(102), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 5564: Copy { + dest: StatePartIndex(4620), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3906), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5565: AndBigWithSmallImmediate { + dest: StatePartIndex(315), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4620), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5566: Copy { + dest: StatePartIndex(4621), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4620), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5567: SliceInt { + dest: StatePartIndex(4622), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4621), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5568: Copy { + dest: StatePartIndex(4623), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4622), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: unit.rs:127:1 + 5569: AndBigWithSmallImmediate { + dest: StatePartIndex(316), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(4623), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5570: Copy { + dest: StatePartIndex(4651), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4623), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5571: SliceInt { + dest: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(4651), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5572: SliceInt { + dest: StatePartIndex(4653), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5573: SliceInt { + dest: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(4653), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5574: SliceInt { + dest: StatePartIndex(4655), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5575: SliceInt { + dest: StatePartIndex(4657), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5576: SliceInt { + dest: StatePartIndex(4658), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4657), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5577: Copy { + dest: StatePartIndex(4656), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4658), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5578: SliceInt { + dest: StatePartIndex(4662), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5579: SliceInt { + dest: StatePartIndex(4663), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4662), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5580: SliceInt { + dest: StatePartIndex(4664), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4662), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5581: SliceInt { + dest: StatePartIndex(4665), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4662), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5582: Copy { + dest: StatePartIndex(4659), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(4663), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5583: Copy { + dest: StatePartIndex(4660), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(4664), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5584: Copy { + dest: StatePartIndex(4661), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(4665), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5585: SliceInt { + dest: StatePartIndex(4666), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5586: SliceInt { + dest: StatePartIndex(4667), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4654), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5587: CastToSInt { + dest: StatePartIndex(4668), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(4667), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5588: Copy { + dest: StatePartIndex(4644), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4655), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5589: Copy { + dest: StatePartIndex(4645), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(4656), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5590: Copy { + dest: StatePartIndex(4646), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(4659), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5591: Copy { + dest: StatePartIndex(4647), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(4660), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5592: Copy { + dest: StatePartIndex(4648), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(4661), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5593: Copy { + dest: StatePartIndex(4649), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(4666), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5594: Copy { + dest: StatePartIndex(4650), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(4668), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5595: SliceInt { + dest: StatePartIndex(4669), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4653), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5596: Copy { + dest: StatePartIndex(4670), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4669), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5597: Copy { + dest: StatePartIndex(4636), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4644), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5598: Copy { + dest: StatePartIndex(4637), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4645), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5599: Copy { + dest: StatePartIndex(4638), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4646), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5600: Copy { + dest: StatePartIndex(4639), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4647), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5601: Copy { + dest: StatePartIndex(4640), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4648), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5602: Copy { + dest: StatePartIndex(4641), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4649), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5603: Copy { + dest: StatePartIndex(4642), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4650), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5604: Copy { + dest: StatePartIndex(4643), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4670), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5605: SliceInt { + dest: StatePartIndex(4671), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5606: Copy { + dest: StatePartIndex(4672), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4671), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5607: SliceInt { + dest: StatePartIndex(4673), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5608: Copy { + dest: StatePartIndex(4674), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4673), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5609: SliceInt { + dest: StatePartIndex(4675), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5610: Copy { + dest: StatePartIndex(4676), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4675), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5611: SliceInt { + dest: StatePartIndex(4677), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5612: Copy { + dest: StatePartIndex(4678), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4677), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5613: Copy { + dest: StatePartIndex(4624), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4636), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5614: Copy { + dest: StatePartIndex(4625), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4637), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5615: Copy { + dest: StatePartIndex(4626), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4638), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5616: Copy { + dest: StatePartIndex(4627), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4639), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5617: Copy { + dest: StatePartIndex(4628), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4640), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5618: Copy { + dest: StatePartIndex(4629), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4641), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5619: Copy { + dest: StatePartIndex(4630), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4642), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5620: Copy { + dest: StatePartIndex(4631), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4643), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5621: Copy { + dest: StatePartIndex(4632), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(4672), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5622: Copy { + dest: StatePartIndex(4633), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(4674), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5623: Copy { + dest: StatePartIndex(4634), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(4676), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5624: Copy { + dest: StatePartIndex(4635), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(4678), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit.rs:127:1 + 5625: AndBigWithSmallImmediate { + dest: StatePartIndex(317), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4631), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5626: SliceInt { + dest: StatePartIndex(4688), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4652), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5627: Copy { + dest: StatePartIndex(4679), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4636), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5628: Copy { + dest: StatePartIndex(4680), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4637), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5629: Copy { + dest: StatePartIndex(4681), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4638), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5630: Copy { + dest: StatePartIndex(4682), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4639), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5631: Copy { + dest: StatePartIndex(4683), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4640), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5632: Copy { + dest: StatePartIndex(4684), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4641), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5633: Copy { + dest: StatePartIndex(4685), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4642), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5634: Copy { + dest: StatePartIndex(4686), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4643), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5635: Copy { + dest: StatePartIndex(4687), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(4688), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit.rs:127:1 + 5636: AndBigWithSmallImmediate { + dest: StatePartIndex(318), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4686), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:314:25 + 5637: BranchIfSmallNeImmediate { + target: 5639, + lhs: StatePartIndex(101), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 5638: Copy { + dest: StatePartIndex(4551), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4620), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::alu_branch_mop", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5639: AndBigWithSmallImmediate { + dest: StatePartIndex(311), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4551), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:308:13 + 5640: BranchIfSmallNeImmediate { + target: 5644, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 5641: BranchIfZero { + target: 5644, + value: StatePartIndex(4550), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 5642: BranchIfSmallNeImmediate { + target: 5644, + lhs: StatePartIndex(311), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: reg_alloc.rs:318:25 + 5643: Copy { + dest: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3740), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:43:1 + 5644: Copy { + dest: StatePartIndex(4552), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4551), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::and_then_out", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5645: SliceInt { + dest: StatePartIndex(4553), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4552), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5646: Copy { + dest: StatePartIndex(4554), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4553), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:314:25 + 5647: AndBigWithSmallImmediate { + dest: StatePartIndex(312), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(4554), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5648: Copy { + dest: StatePartIndex(4582), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4554), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5649: SliceInt { + dest: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(4582), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5650: SliceInt { + dest: StatePartIndex(4584), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5651: SliceInt { + dest: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(4584), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5652: SliceInt { + dest: StatePartIndex(4586), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5653: SliceInt { + dest: StatePartIndex(4588), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5654: SliceInt { + dest: StatePartIndex(4589), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4588), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5655: Copy { + dest: StatePartIndex(4587), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4589), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5656: SliceInt { + dest: StatePartIndex(4593), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5657: SliceInt { + dest: StatePartIndex(4594), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4593), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5658: SliceInt { + dest: StatePartIndex(4595), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4593), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5659: SliceInt { + dest: StatePartIndex(4596), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4593), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5660: Copy { + dest: StatePartIndex(4590), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(4594), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5661: Copy { + dest: StatePartIndex(4591), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(4595), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5662: Copy { + dest: StatePartIndex(4592), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(4596), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5663: SliceInt { + dest: StatePartIndex(4597), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5664: SliceInt { + dest: StatePartIndex(4598), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4585), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5665: CastToSInt { + dest: StatePartIndex(4599), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(4598), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5666: Copy { + dest: StatePartIndex(4575), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4586), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5667: Copy { + dest: StatePartIndex(4576), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(4587), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5668: Copy { + dest: StatePartIndex(4577), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(4590), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5669: Copy { + dest: StatePartIndex(4578), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(4591), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5670: Copy { + dest: StatePartIndex(4579), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(4592), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5671: Copy { + dest: StatePartIndex(4580), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(4597), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5672: Copy { + dest: StatePartIndex(4581), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(4599), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5673: SliceInt { + dest: StatePartIndex(4600), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4584), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5674: Copy { + dest: StatePartIndex(4601), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4600), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5675: Copy { + dest: StatePartIndex(4567), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4575), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5676: Copy { + dest: StatePartIndex(4568), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4576), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5677: Copy { + dest: StatePartIndex(4569), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4577), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5678: Copy { + dest: StatePartIndex(4570), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4578), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5679: Copy { + dest: StatePartIndex(4571), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4579), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5680: Copy { + dest: StatePartIndex(4572), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4580), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5681: Copy { + dest: StatePartIndex(4573), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4581), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5682: Copy { + dest: StatePartIndex(4574), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4601), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5683: SliceInt { + dest: StatePartIndex(4602), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5684: Copy { + dest: StatePartIndex(4603), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4602), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5685: SliceInt { + dest: StatePartIndex(4604), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5686: Copy { + dest: StatePartIndex(4605), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4604), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5687: SliceInt { + dest: StatePartIndex(4606), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5688: Copy { + dest: StatePartIndex(4607), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4606), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5689: SliceInt { + dest: StatePartIndex(4608), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5690: Copy { + dest: StatePartIndex(4609), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4608), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5691: Copy { + dest: StatePartIndex(4555), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4567), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5692: Copy { + dest: StatePartIndex(4556), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4568), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5693: Copy { + dest: StatePartIndex(4557), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4569), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5694: Copy { + dest: StatePartIndex(4558), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4570), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5695: Copy { + dest: StatePartIndex(4559), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4571), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5696: Copy { + dest: StatePartIndex(4560), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4572), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5697: Copy { + dest: StatePartIndex(4561), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4573), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5698: Copy { + dest: StatePartIndex(4562), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4574), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5699: Copy { + dest: StatePartIndex(4563), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(4603), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5700: Copy { + dest: StatePartIndex(4564), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(4605), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5701: Copy { + dest: StatePartIndex(4565), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(4607), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5702: Copy { + dest: StatePartIndex(4566), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(4609), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:314:25 + 5703: AndBigWithSmallImmediate { + dest: StatePartIndex(313), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4562), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5704: SliceInt { + dest: StatePartIndex(4619), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4583), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5705: Copy { + dest: StatePartIndex(4610), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4567), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5706: Copy { + dest: StatePartIndex(4611), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4568), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5707: Copy { + dest: StatePartIndex(4612), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4569), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5708: Copy { + dest: StatePartIndex(4613), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4570), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5709: Copy { + dest: StatePartIndex(4614), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4571), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5710: Copy { + dest: StatePartIndex(4615), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4572), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5711: Copy { + dest: StatePartIndex(4616), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4573), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5712: Copy { + dest: StatePartIndex(4617), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4574), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5713: Copy { + dest: StatePartIndex(4618), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(4619), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:314:25 + 5714: AndBigWithSmallImmediate { + dest: StatePartIndex(314), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4617), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5715: Copy { + dest: StatePartIndex(4689), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(817), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5716: Copy { + dest: StatePartIndex(4690), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(4554), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5717: Copy { + dest: StatePartIndex(4691), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(4690), // (0x0) SlotDebugData { name: ".1", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5718: Shl { + dest: StatePartIndex(4692), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(4691), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + rhs: 1, + }, + 5719: Or { + dest: StatePartIndex(4693), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + lhs: StatePartIndex(4689), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(4692), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + }, + 5720: CastToUInt { + dest: StatePartIndex(4694), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(4693), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + dest_width: 58, + }, + 5721: Copy { + dest: StatePartIndex(4695), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4694), // (0x1) SlotDebugData { name: "", ty: UInt<58> }, + }, + // at: reg_alloc.rs:308:13 + 5722: BranchIfSmallNeImmediate { + target: 5726, + lhs: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:310:17 + 5723: BranchIfZero { + target: 5726, + value: StatePartIndex(4550), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:313:21 + 5724: BranchIfSmallNeImmediate { + target: 5726, + lhs: StatePartIndex(311), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:316:25 + 5725: Copy { + dest: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(4695), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: reg_alloc.rs:271:13 + 5726: Copy { + dest: StatePartIndex(3920), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + src: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + // at: alu_branch.rs:21:11 + 5727: AndBigWithSmallImmediate { + dest: StatePartIndex(268), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3920), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: alu_branch.rs:15:1 + 5728: Copy { + dest: StatePartIndex(3922), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3920), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1: alu_branch).alu_branch::input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5729: SliceInt { + dest: StatePartIndex(3923), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3922), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5730: Copy { + dest: StatePartIndex(3924), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3923), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: alu_branch.rs:21:11 + 5731: AndBigWithSmallImmediate { + dest: StatePartIndex(269), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3924), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: alu_branch.rs:15:1 + 5732: Copy { + dest: StatePartIndex(3952), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3924), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5733: SliceInt { + dest: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(3952), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5734: SliceInt { + dest: StatePartIndex(3954), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5735: SliceInt { + dest: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(3954), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5736: SliceInt { + dest: StatePartIndex(3956), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5737: SliceInt { + dest: StatePartIndex(3958), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5738: SliceInt { + dest: StatePartIndex(3959), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3958), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5739: Copy { + dest: StatePartIndex(3957), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(3959), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5740: SliceInt { + dest: StatePartIndex(3963), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5741: SliceInt { + dest: StatePartIndex(3964), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3963), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5742: SliceInt { + dest: StatePartIndex(3965), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3963), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5743: SliceInt { + dest: StatePartIndex(3966), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(3963), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5744: Copy { + dest: StatePartIndex(3960), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(3964), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5745: Copy { + dest: StatePartIndex(3961), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(3965), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5746: Copy { + dest: StatePartIndex(3962), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(3966), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5747: SliceInt { + dest: StatePartIndex(3967), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5748: SliceInt { + dest: StatePartIndex(3968), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3955), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5749: CastToSInt { + dest: StatePartIndex(3969), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(3968), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5750: Copy { + dest: StatePartIndex(3945), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3956), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5751: Copy { + dest: StatePartIndex(3946), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(3957), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5752: Copy { + dest: StatePartIndex(3947), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(3960), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5753: Copy { + dest: StatePartIndex(3948), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(3961), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5754: Copy { + dest: StatePartIndex(3949), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(3962), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5755: Copy { + dest: StatePartIndex(3950), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(3967), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5756: Copy { + dest: StatePartIndex(3951), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(3969), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5757: SliceInt { + dest: StatePartIndex(3970), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(3954), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5758: Copy { + dest: StatePartIndex(3971), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3970), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5759: Copy { + dest: StatePartIndex(3937), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3945), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5760: Copy { + dest: StatePartIndex(3938), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3946), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5761: Copy { + dest: StatePartIndex(3939), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3947), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5762: Copy { + dest: StatePartIndex(3940), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3948), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5763: Copy { + dest: StatePartIndex(3941), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3949), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5764: Copy { + dest: StatePartIndex(3942), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3950), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5765: Copy { + dest: StatePartIndex(3943), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3951), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5766: Copy { + dest: StatePartIndex(3944), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3971), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5767: SliceInt { + dest: StatePartIndex(3972), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5768: Copy { + dest: StatePartIndex(3973), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3972), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5769: SliceInt { + dest: StatePartIndex(3974), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5770: Copy { + dest: StatePartIndex(3975), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3974), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5771: SliceInt { + dest: StatePartIndex(3976), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5772: Copy { + dest: StatePartIndex(3977), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3976), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5773: SliceInt { + dest: StatePartIndex(3978), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5774: Copy { + dest: StatePartIndex(3979), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(3978), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5775: Copy { + dest: StatePartIndex(3925), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3937), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5776: Copy { + dest: StatePartIndex(3926), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3938), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5777: Copy { + dest: StatePartIndex(3927), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3939), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5778: Copy { + dest: StatePartIndex(3928), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3940), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5779: Copy { + dest: StatePartIndex(3929), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3941), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5780: Copy { + dest: StatePartIndex(3930), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3942), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5781: Copy { + dest: StatePartIndex(3931), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3943), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5782: Copy { + dest: StatePartIndex(3932), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3944), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5783: Copy { + dest: StatePartIndex(3933), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(3973), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5784: Copy { + dest: StatePartIndex(3934), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(3975), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5785: Copy { + dest: StatePartIndex(3935), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(3977), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5786: Copy { + dest: StatePartIndex(3936), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(3979), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: alu_branch.rs:21:11 + 5787: AndBigWithSmallImmediate { + dest: StatePartIndex(270), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3932), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: alu_branch.rs:15:1 + 5788: SliceInt { + dest: StatePartIndex(3989), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(3953), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5789: Copy { + dest: StatePartIndex(3980), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(3937), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5790: Copy { + dest: StatePartIndex(3981), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(3938), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5791: Copy { + dest: StatePartIndex(3982), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(3939), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5792: Copy { + dest: StatePartIndex(3983), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(3940), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5793: Copy { + dest: StatePartIndex(3984), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(3941), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5794: Copy { + dest: StatePartIndex(3985), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(3942), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5795: Copy { + dest: StatePartIndex(3986), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(3943), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5796: Copy { + dest: StatePartIndex(3987), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(3944), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5797: Copy { + dest: StatePartIndex(3988), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(3989), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: alu_branch.rs:21:11 + 5798: AndBigWithSmallImmediate { + dest: StatePartIndex(271), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(3987), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:271:13 + 5799: AndBigWithSmallImmediate { + dest: StatePartIndex(272), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5800: Copy { + dest: StatePartIndex(3990), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(3916), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_1.input.data", ty: Enum {HdlNone, HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})})} }, + }, + 5801: SliceInt { + dest: StatePartIndex(3991), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3990), // (0x0) SlotDebugData { name: "", ty: UInt<58> }, + start: 1, + len: 57, + }, + 5802: Copy { + dest: StatePartIndex(3992), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(3991), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + }, + // at: reg_alloc.rs:271:13 + 5803: AndBigWithSmallImmediate { + dest: StatePartIndex(273), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(3992), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:43:1 + 5804: Copy { + dest: StatePartIndex(4020), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + src: StatePartIndex(3992), // (0x0) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 5805: SliceInt { + dest: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + src: StatePartIndex(4020), // (0x0) SlotDebugData { name: "", ty: UInt<57> }, + start: 2, + len: 55, + }, + 5806: SliceInt { + dest: StatePartIndex(4022), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 0, + len: 51, + }, + 5807: SliceInt { + dest: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + src: StatePartIndex(4022), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 0, + len: 48, + }, + 5808: SliceInt { + dest: StatePartIndex(4024), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 0, + }, + 5809: SliceInt { + dest: StatePartIndex(4026), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 0, + len: 4, + }, + 5810: SliceInt { + dest: StatePartIndex(4027), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4026), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5811: Copy { + dest: StatePartIndex(4025), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(4027), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5812: SliceInt { + dest: StatePartIndex(4031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 4, + len: 18, + }, + 5813: SliceInt { + dest: StatePartIndex(4032), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5814: SliceInt { + dest: StatePartIndex(4033), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5815: SliceInt { + dest: StatePartIndex(4034), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(4031), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5816: Copy { + dest: StatePartIndex(4028), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(4032), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5817: Copy { + dest: StatePartIndex(4029), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(4033), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5818: Copy { + dest: StatePartIndex(4030), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(4034), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5819: SliceInt { + dest: StatePartIndex(4035), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 22, + len: 25, + }, + 5820: SliceInt { + dest: StatePartIndex(4036), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4023), // (0x0) SlotDebugData { name: "", ty: UInt<48> }, + start: 47, + len: 1, + }, + 5821: CastToSInt { + dest: StatePartIndex(4037), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(4036), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5822: Copy { + dest: StatePartIndex(4013), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4024), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 5823: Copy { + dest: StatePartIndex(4014), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(4025), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5824: Copy { + dest: StatePartIndex(4015), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(4028), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5825: Copy { + dest: StatePartIndex(4016), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(4029), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5826: Copy { + dest: StatePartIndex(4017), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(4030), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5827: Copy { + dest: StatePartIndex(4018), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(4035), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5828: Copy { + dest: StatePartIndex(4019), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(4037), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5829: SliceInt { + dest: StatePartIndex(4038), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(4022), // (0x0) SlotDebugData { name: "", ty: UInt<51> }, + start: 48, + len: 3, + }, + 5830: Copy { + dest: StatePartIndex(4039), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4038), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 5831: Copy { + dest: StatePartIndex(4005), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4013), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 5832: Copy { + dest: StatePartIndex(4006), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4014), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5833: Copy { + dest: StatePartIndex(4007), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4015), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5834: Copy { + dest: StatePartIndex(4008), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4016), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5835: Copy { + dest: StatePartIndex(4009), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4017), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5836: Copy { + dest: StatePartIndex(4010), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4018), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5837: Copy { + dest: StatePartIndex(4011), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4019), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5838: Copy { + dest: StatePartIndex(4012), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4039), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5839: SliceInt { + dest: StatePartIndex(4040), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 1, + }, + 5840: Copy { + dest: StatePartIndex(4041), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4040), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5841: SliceInt { + dest: StatePartIndex(4042), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 52, + len: 1, + }, + 5842: Copy { + dest: StatePartIndex(4043), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4042), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5843: SliceInt { + dest: StatePartIndex(4044), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 53, + len: 1, + }, + 5844: Copy { + dest: StatePartIndex(4045), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4044), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5845: SliceInt { + dest: StatePartIndex(4046), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 54, + len: 1, + }, + 5846: Copy { + dest: StatePartIndex(4047), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(4046), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5847: Copy { + dest: StatePartIndex(3993), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4005), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5848: Copy { + dest: StatePartIndex(3994), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4006), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5849: Copy { + dest: StatePartIndex(3995), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4007), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5850: Copy { + dest: StatePartIndex(3996), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4008), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5851: Copy { + dest: StatePartIndex(3997), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4009), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5852: Copy { + dest: StatePartIndex(3998), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4010), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5853: Copy { + dest: StatePartIndex(3999), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4011), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5854: Copy { + dest: StatePartIndex(4000), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4012), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5855: Copy { + dest: StatePartIndex(4001), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(4041), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5856: Copy { + dest: StatePartIndex(4002), // (0x0) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(4043), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5857: Copy { + dest: StatePartIndex(4003), // (0x0) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(4045), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 5858: Copy { + dest: StatePartIndex(4004), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(4047), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:271:13 + 5859: AndBigWithSmallImmediate { + dest: StatePartIndex(274), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4000), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5860: SliceInt { + dest: StatePartIndex(4057), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(4021), // (0x0) SlotDebugData { name: "", ty: UInt<55> }, + start: 51, + len: 4, + }, + 5861: Copy { + dest: StatePartIndex(4048), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(4005), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 5862: Copy { + dest: StatePartIndex(4049), // (0x0) SlotDebugData { name: ".alu_common.common.dest.value", ty: UInt<4> }, + src: StatePartIndex(4006), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + }, + 5863: Copy { + dest: StatePartIndex(4050), // (0x0) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<6> }, + src: StatePartIndex(4007), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + }, + 5864: Copy { + dest: StatePartIndex(4051), // (0x0) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<6> }, + src: StatePartIndex(4008), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + }, + 5865: Copy { + dest: StatePartIndex(4052), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<6> }, + src: StatePartIndex(4009), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + }, + 5866: Copy { + dest: StatePartIndex(4053), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(4010), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 5867: Copy { + dest: StatePartIndex(4054), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(4011), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 5868: Copy { + dest: StatePartIndex(4055), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(4012), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 5869: Copy { + dest: StatePartIndex(4056), // (0x0) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(4057), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:271:13 + 5870: AndBigWithSmallImmediate { + dest: StatePartIndex(275), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(4055), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:43:1 + 5871: SliceInt { + dest: StatePartIndex(704), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(636), // (0x0) SlotDebugData { name: "", ty: UInt<59> }, + start: 2, + len: 50, + }, + 5872: Copy { + dest: StatePartIndex(705), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(704), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: reg_alloc.rs:75:24 + 5873: AndBigWithSmallImmediate { + dest: StatePartIndex(106), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(705), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5874: Copy { + dest: StatePartIndex(720), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(705), // (0x0) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 5875: SliceInt { + dest: StatePartIndex(721), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(720), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 5876: SliceInt { + dest: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(721), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 49, + }, + 5877: SliceInt { + dest: StatePartIndex(723), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 5878: SliceInt { + dest: StatePartIndex(725), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 5879: SliceInt { + dest: StatePartIndex(726), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(725), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5880: Copy { + dest: StatePartIndex(724), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(726), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5881: SliceInt { + dest: StatePartIndex(730), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 5882: SliceInt { + dest: StatePartIndex(731), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(730), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5883: SliceInt { + dest: StatePartIndex(732), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(730), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5884: SliceInt { + dest: StatePartIndex(733), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(730), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5885: Copy { + dest: StatePartIndex(727), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(731), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5886: Copy { + dest: StatePartIndex(728), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(732), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5887: Copy { + dest: StatePartIndex(729), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(733), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5888: SliceInt { + dest: StatePartIndex(734), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 5889: SliceInt { + dest: StatePartIndex(735), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(722), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 5890: CastToSInt { + dest: StatePartIndex(736), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(735), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5891: Copy { + dest: StatePartIndex(713), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(723), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5892: Copy { + dest: StatePartIndex(714), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(724), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5893: Copy { + dest: StatePartIndex(715), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(727), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5894: Copy { + dest: StatePartIndex(716), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(728), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5895: Copy { + dest: StatePartIndex(717), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(729), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5896: Copy { + dest: StatePartIndex(718), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(734), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5897: Copy { + dest: StatePartIndex(719), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(736), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 5898: Copy { + dest: StatePartIndex(706), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(713), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 5899: Copy { + dest: StatePartIndex(707), // (0x0) SlotDebugData { name: ".common.dest.value", ty: UInt<4> }, + src: StatePartIndex(714), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + }, + 5900: Copy { + dest: StatePartIndex(708), // (0x0) SlotDebugData { name: ".common.src[0]", ty: UInt<6> }, + src: StatePartIndex(715), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + }, + 5901: Copy { + dest: StatePartIndex(709), // (0x0) SlotDebugData { name: ".common.src[1]", ty: UInt<6> }, + src: StatePartIndex(716), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + }, + 5902: Copy { + dest: StatePartIndex(710), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<6> }, + src: StatePartIndex(717), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + }, + 5903: Copy { + dest: StatePartIndex(711), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(718), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 5904: Copy { + dest: StatePartIndex(712), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(719), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 5905: Copy { + dest: StatePartIndex(737), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(704), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + }, + // at: reg_alloc.rs:75:24 + 5906: AndBigWithSmallImmediate { + dest: StatePartIndex(107), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(737), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 5907: Copy { + dest: StatePartIndex(745), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + src: StatePartIndex(737), // (0x0) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 5908: SliceInt { + dest: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + src: StatePartIndex(745), // (0x0) SlotDebugData { name: "", ty: UInt<50> }, + start: 1, + len: 49, + }, + 5909: SliceInt { + dest: StatePartIndex(747), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 0, + len: 1, + }, + 5910: SliceInt { + dest: StatePartIndex(749), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 1, + len: 4, + }, + 5911: SliceInt { + dest: StatePartIndex(750), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(749), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 4, + }, + 5912: Copy { + dest: StatePartIndex(748), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + src: StatePartIndex(750), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 5913: SliceInt { + dest: StatePartIndex(754), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + src: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 5, + len: 18, + }, + 5914: SliceInt { + dest: StatePartIndex(755), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(754), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 0, + len: 6, + }, + 5915: SliceInt { + dest: StatePartIndex(756), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(754), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 6, + len: 6, + }, + 5916: SliceInt { + dest: StatePartIndex(757), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(754), // (0x0) SlotDebugData { name: "", ty: UInt<18> }, + start: 12, + len: 6, + }, + 5917: Copy { + dest: StatePartIndex(751), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + src: StatePartIndex(755), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5918: Copy { + dest: StatePartIndex(752), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + src: StatePartIndex(756), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5919: Copy { + dest: StatePartIndex(753), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + src: StatePartIndex(757), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + }, + 5920: SliceInt { + dest: StatePartIndex(758), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 23, + len: 25, + }, + 5921: SliceInt { + dest: StatePartIndex(759), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(746), // (0x0) SlotDebugData { name: "", ty: UInt<49> }, + start: 48, + len: 1, + }, + 5922: CastToSInt { + dest: StatePartIndex(760), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(759), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 5923: Copy { + dest: StatePartIndex(738), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(747), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5924: Copy { + dest: StatePartIndex(739), // (0x0) SlotDebugData { name: ".dest.value", ty: UInt<4> }, + src: StatePartIndex(748), // (0x0) SlotDebugData { name: ".value", ty: UInt<4> }, + }, + 5925: Copy { + dest: StatePartIndex(740), // (0x0) SlotDebugData { name: ".src[0]", ty: UInt<6> }, + src: StatePartIndex(751), // (0x0) SlotDebugData { name: "[0]", ty: UInt<6> }, + }, + 5926: Copy { + dest: StatePartIndex(741), // (0x0) SlotDebugData { name: ".src[1]", ty: UInt<6> }, + src: StatePartIndex(752), // (0x0) SlotDebugData { name: "[1]", ty: UInt<6> }, + }, + 5927: Copy { + dest: StatePartIndex(742), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<6> }, + src: StatePartIndex(753), // (0x0) SlotDebugData { name: "[2]", ty: UInt<6> }, + }, + 5928: Copy { + dest: StatePartIndex(743), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(758), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 5929: Copy { + dest: StatePartIndex(744), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(760), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: unit_free_regs_tracker.rs:27:25 + 5930: BranchIfSmallZero { + target: 5965, + value: StatePartIndex(228), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 5931: BranchIfSmallNonZero { + target: 5949, + value: StatePartIndex(230), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 5932: Copy { + dest: StatePartIndex(3245), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(3261), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool }, + }, + 5933: Copy { + dest: StatePartIndex(3246), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(3262), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", ty: Bool }, + }, + 5934: Copy { + dest: StatePartIndex(3247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(3263), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", ty: Bool }, + }, + 5935: Copy { + dest: StatePartIndex(3248), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(3264), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", ty: Bool }, + }, + 5936: Copy { + dest: StatePartIndex(3249), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(3265), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", ty: Bool }, + }, + 5937: Copy { + dest: StatePartIndex(3250), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(3266), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", ty: Bool }, + }, + 5938: Copy { + dest: StatePartIndex(3251), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(3267), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", ty: Bool }, + }, + 5939: Copy { + dest: StatePartIndex(3252), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(3268), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", ty: Bool }, + }, + 5940: Copy { + dest: StatePartIndex(3253), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(3269), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", ty: Bool }, + }, + 5941: Copy { + dest: StatePartIndex(3254), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(3270), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", ty: Bool }, + }, + 5942: Copy { + dest: StatePartIndex(3255), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(3271), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", ty: Bool }, + }, + 5943: Copy { + dest: StatePartIndex(3256), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(3272), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", ty: Bool }, + }, + 5944: Copy { + dest: StatePartIndex(3257), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(3273), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", ty: Bool }, + }, + 5945: Copy { + dest: StatePartIndex(3258), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(3274), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", ty: Bool }, + }, + 5946: Copy { + dest: StatePartIndex(3259), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(3275), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", ty: Bool }, + }, + 5947: Copy { + dest: StatePartIndex(3260), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(3276), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", ty: Bool }, + }, + 5948: Branch { + target: 5965, + }, + 5949: Copy { + dest: StatePartIndex(3245), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(3277), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 5950: Copy { + dest: StatePartIndex(3246), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(3278), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 5951: Copy { + dest: StatePartIndex(3247), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(3279), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + }, + 5952: Copy { + dest: StatePartIndex(3248), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(3280), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + }, + 5953: Copy { + dest: StatePartIndex(3249), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(3281), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + }, + 5954: Copy { + dest: StatePartIndex(3250), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(3282), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + }, + 5955: Copy { + dest: StatePartIndex(3251), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(3283), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + }, + 5956: Copy { + dest: StatePartIndex(3252), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(3284), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + }, + 5957: Copy { + dest: StatePartIndex(3253), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(3285), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, + }, + 5958: Copy { + dest: StatePartIndex(3254), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(3286), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, + }, + 5959: Copy { + dest: StatePartIndex(3255), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(3287), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, + }, + 5960: Copy { + dest: StatePartIndex(3256), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(3288), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, + }, + 5961: Copy { + dest: StatePartIndex(3257), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(3289), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, + }, + 5962: Copy { + dest: StatePartIndex(3258), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(3290), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, + }, + 5963: Copy { + dest: StatePartIndex(3259), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(3291), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, + }, + 5964: Copy { + dest: StatePartIndex(3260), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(3292), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, + }, + 5965: BranchIfSmallZero { + target: 6000, + value: StatePartIndex(279), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 5966: BranchIfSmallNonZero { + target: 5984, + value: StatePartIndex(281), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 5967: Copy { + dest: StatePartIndex(4074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(4090), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool }, + }, + 5968: Copy { + dest: StatePartIndex(4075), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(4091), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", ty: Bool }, + }, + 5969: Copy { + dest: StatePartIndex(4076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(4092), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", ty: Bool }, + }, + 5970: Copy { + dest: StatePartIndex(4077), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(4093), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", ty: Bool }, + }, + 5971: Copy { + dest: StatePartIndex(4078), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(4094), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", ty: Bool }, + }, + 5972: Copy { + dest: StatePartIndex(4079), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(4095), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", ty: Bool }, + }, + 5973: Copy { + dest: StatePartIndex(4080), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(4096), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", ty: Bool }, + }, + 5974: Copy { + dest: StatePartIndex(4081), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(4097), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", ty: Bool }, + }, + 5975: Copy { + dest: StatePartIndex(4082), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(4098), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", ty: Bool }, + }, + 5976: Copy { + dest: StatePartIndex(4083), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(4099), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", ty: Bool }, + }, + 5977: Copy { + dest: StatePartIndex(4084), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(4100), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", ty: Bool }, + }, + 5978: Copy { + dest: StatePartIndex(4085), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(4101), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", ty: Bool }, + }, + 5979: Copy { + dest: StatePartIndex(4086), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(4102), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", ty: Bool }, + }, + 5980: Copy { + dest: StatePartIndex(4087), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(4103), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", ty: Bool }, + }, + 5981: Copy { + dest: StatePartIndex(4088), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(4104), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", ty: Bool }, + }, + 5982: Copy { + dest: StatePartIndex(4089), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(4105), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", ty: Bool }, + }, + 5983: Branch { + target: 6000, + }, + 5984: Copy { + dest: StatePartIndex(4074), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(3277), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 5985: Copy { + dest: StatePartIndex(4075), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(3278), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 5986: Copy { + dest: StatePartIndex(4076), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(3279), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + }, + 5987: Copy { + dest: StatePartIndex(4077), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(3280), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + }, + 5988: Copy { + dest: StatePartIndex(4078), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(3281), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + }, + 5989: Copy { + dest: StatePartIndex(4079), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(3282), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + }, + 5990: Copy { + dest: StatePartIndex(4080), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(3283), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + }, + 5991: Copy { + dest: StatePartIndex(4081), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(3284), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + }, + 5992: Copy { + dest: StatePartIndex(4082), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(3285), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, + }, + 5993: Copy { + dest: StatePartIndex(4083), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(3286), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, + }, + 5994: Copy { + dest: StatePartIndex(4084), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(3287), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, + }, + 5995: Copy { + dest: StatePartIndex(4085), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(3288), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, + }, + 5996: Copy { + dest: StatePartIndex(4086), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(3289), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, + }, + 5997: Copy { + dest: StatePartIndex(4087), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(3290), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, + }, + 5998: Copy { + dest: StatePartIndex(4088), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(3291), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, + }, + 5999: Copy { + dest: StatePartIndex(4089), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_1_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(3292), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 6000: BranchIfSmallZero { + target: 6001, + value: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6001: BranchIfSmallZero { + target: 6002, + value: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6002: BranchIfSmallZero { + target: 6003, + value: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6003: BranchIfSmallZero { + target: 6004, + value: StatePartIndex(48), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6004: BranchIfSmallZero { + target: 6005, + value: StatePartIndex(53), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6005: BranchIfSmallZero { + target: 6006, + value: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:40 + 6006: BranchIfSmallZero { + target: 6007, + value: StatePartIndex(63), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6007: BranchIfSmallZero { + target: 6008, + value: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6008: BranchIfSmallZero { + target: 6009, + value: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6009: BranchIfSmallZero { + target: 6010, + value: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6010: BranchIfSmallZero { + target: 6011, + value: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 6011: BranchIfSmallZero { + target: 6012, + value: StatePartIndex(88), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:60:39 + 6012: XorSmallImmediate { + dest: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6013: XorSmallImmediate { + dest: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6014: XorSmallImmediate { + dest: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(44), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6015: XorSmallImmediate { + dest: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(49), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6016: XorSmallImmediate { + dest: StatePartIndex(52), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(54), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6017: XorSmallImmediate { + dest: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(59), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: reg_alloc.rs:65:40 + 6018: XorSmallImmediate { + dest: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(64), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6019: XorSmallImmediate { + dest: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(69), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6020: XorSmallImmediate { + dest: StatePartIndex(72), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(74), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6021: XorSmallImmediate { + dest: StatePartIndex(77), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(79), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6022: XorSmallImmediate { + dest: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6023: XorSmallImmediate { + dest: StatePartIndex(87), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:27:25 + 6024: XorSmallImmediate { + dest: StatePartIndex(227), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(229), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 6025: XorSmallImmediate { + dest: StatePartIndex(278), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(280), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: reg_alloc.rs:43:1 + 6026: Return, ], .. }, - pc: 829, + pc: 6026, memory_write_log: [], memories: StatePart { - value: [], + value: [ + MemoryData { + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + data: [ + // len = 0xfd + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + [0x4]: 0x00, + [0x5]: 0x00, + [0x6]: 0x00, + [0x7]: 0x00, + [0x8]: 0x00, + [0x9]: 0x00, + [0xa]: 0x00, + [0xb]: 0x00, + [0xc]: 0x00, + [0xd]: 0x00, + [0xe]: 0x00, + [0xf]: 0x00, + [0x10]: 0x00, + [0x11]: 0x00, + [0x12]: 0x00, + [0x13]: 0x00, + [0x14]: 0x00, + [0x15]: 0x00, + [0x16]: 0x00, + [0x17]: 0x00, + [0x18]: 0x00, + [0x19]: 0x00, + [0x1a]: 0x00, + [0x1b]: 0x00, + [0x1c]: 0x00, + [0x1d]: 0x00, + [0x1e]: 0x00, + [0x1f]: 0x00, + [0x20]: 0x00, + [0x21]: 0x00, + [0x22]: 0x00, + [0x23]: 0x00, + [0x24]: 0x00, + [0x25]: 0x00, + [0x26]: 0x00, + [0x27]: 0x00, + [0x28]: 0x00, + [0x29]: 0x00, + [0x2a]: 0x00, + [0x2b]: 0x00, + [0x2c]: 0x00, + [0x2d]: 0x00, + [0x2e]: 0x00, + [0x2f]: 0x00, + [0x30]: 0x00, + [0x31]: 0x00, + [0x32]: 0x00, + [0x33]: 0x00, + [0x34]: 0x00, + [0x35]: 0x00, + [0x36]: 0x00, + [0x37]: 0x00, + [0x38]: 0x00, + [0x39]: 0x00, + [0x3a]: 0x00, + [0x3b]: 0x00, + [0x3c]: 0x00, + [0x3d]: 0x00, + [0x3e]: 0x00, + [0x3f]: 0x00, + [0x40]: 0x00, + [0x41]: 0x00, + [0x42]: 0x00, + [0x43]: 0x00, + [0x44]: 0x00, + [0x45]: 0x00, + [0x46]: 0x00, + [0x47]: 0x00, + [0x48]: 0x00, + [0x49]: 0x00, + [0x4a]: 0x00, + [0x4b]: 0x00, + [0x4c]: 0x00, + [0x4d]: 0x00, + [0x4e]: 0x00, + [0x4f]: 0x00, + [0x50]: 0x00, + [0x51]: 0x00, + [0x52]: 0x00, + [0x53]: 0x00, + [0x54]: 0x00, + [0x55]: 0x00, + [0x56]: 0x00, + [0x57]: 0x00, + [0x58]: 0x00, + [0x59]: 0x00, + [0x5a]: 0x00, + [0x5b]: 0x00, + [0x5c]: 0x00, + [0x5d]: 0x00, + [0x5e]: 0x00, + [0x5f]: 0x00, + [0x60]: 0x00, + [0x61]: 0x00, + [0x62]: 0x00, + [0x63]: 0x00, + [0x64]: 0x00, + [0x65]: 0x00, + [0x66]: 0x00, + [0x67]: 0x00, + [0x68]: 0x00, + [0x69]: 0x00, + [0x6a]: 0x00, + [0x6b]: 0x00, + [0x6c]: 0x00, + [0x6d]: 0x00, + [0x6e]: 0x00, + [0x6f]: 0x00, + [0x70]: 0x00, + [0x71]: 0x00, + [0x72]: 0x00, + [0x73]: 0x00, + [0x74]: 0x00, + [0x75]: 0x00, + [0x76]: 0x00, + [0x77]: 0x00, + [0x78]: 0x00, + [0x79]: 0x00, + [0x7a]: 0x00, + [0x7b]: 0x00, + [0x7c]: 0x00, + [0x7d]: 0x00, + [0x7e]: 0x00, + [0x7f]: 0x00, + [0x80]: 0x00, + [0x81]: 0x00, + [0x82]: 0x00, + [0x83]: 0x00, + [0x84]: 0x00, + [0x85]: 0x00, + [0x86]: 0x00, + [0x87]: 0x00, + [0x88]: 0x00, + [0x89]: 0x00, + [0x8a]: 0x00, + [0x8b]: 0x00, + [0x8c]: 0x00, + [0x8d]: 0x00, + [0x8e]: 0x00, + [0x8f]: 0x00, + [0x90]: 0x00, + [0x91]: 0x00, + [0x92]: 0x00, + [0x93]: 0x00, + [0x94]: 0x00, + [0x95]: 0x00, + [0x96]: 0x00, + [0x97]: 0x00, + [0x98]: 0x00, + [0x99]: 0x00, + [0x9a]: 0x00, + [0x9b]: 0x00, + [0x9c]: 0x00, + [0x9d]: 0x00, + [0x9e]: 0x00, + [0x9f]: 0x00, + [0xa0]: 0x00, + [0xa1]: 0x00, + [0xa2]: 0x00, + [0xa3]: 0x00, + [0xa4]: 0x00, + [0xa5]: 0x00, + [0xa6]: 0x00, + [0xa7]: 0x00, + [0xa8]: 0x00, + [0xa9]: 0x00, + [0xaa]: 0x00, + [0xab]: 0x00, + [0xac]: 0x00, + [0xad]: 0x00, + [0xae]: 0x00, + [0xaf]: 0x00, + [0xb0]: 0x00, + [0xb1]: 0x00, + [0xb2]: 0x00, + [0xb3]: 0x00, + [0xb4]: 0x00, + [0xb5]: 0x00, + [0xb6]: 0x00, + [0xb7]: 0x00, + [0xb8]: 0x00, + [0xb9]: 0x00, + [0xba]: 0x00, + [0xbb]: 0x00, + [0xbc]: 0x00, + [0xbd]: 0x00, + [0xbe]: 0x00, + [0xbf]: 0x00, + [0xc0]: 0x00, + [0xc1]: 0x00, + [0xc2]: 0x00, + [0xc3]: 0x00, + [0xc4]: 0x00, + [0xc5]: 0x00, + [0xc6]: 0x00, + [0xc7]: 0x00, + [0xc8]: 0x00, + [0xc9]: 0x00, + [0xca]: 0x00, + [0xcb]: 0x00, + [0xcc]: 0x00, + [0xcd]: 0x00, + [0xce]: 0x00, + [0xcf]: 0x00, + [0xd0]: 0x00, + [0xd1]: 0x00, + [0xd2]: 0x00, + [0xd3]: 0x00, + [0xd4]: 0x00, + [0xd5]: 0x00, + [0xd6]: 0x00, + [0xd7]: 0x00, + [0xd8]: 0x00, + [0xd9]: 0x00, + [0xda]: 0x00, + [0xdb]: 0x00, + [0xdc]: 0x00, + [0xdd]: 0x00, + [0xde]: 0x00, + [0xdf]: 0x00, + [0xe0]: 0x00, + [0xe1]: 0x00, + [0xe2]: 0x00, + [0xe3]: 0x00, + [0xe4]: 0x00, + [0xe5]: 0x00, + [0xe6]: 0x00, + [0xe7]: 0x00, + [0xe8]: 0x00, + [0xe9]: 0x00, + [0xea]: 0x00, + [0xeb]: 0x00, + [0xec]: 0x00, + [0xed]: 0x00, + [0xee]: 0x00, + [0xef]: 0x00, + [0xf0]: 0x00, + [0xf1]: 0x00, + [0xf2]: 0x00, + [0xf3]: 0x00, + [0xf4]: 0x00, + [0xf5]: 0x00, + [0xf6]: 0x00, + [0xf7]: 0x00, + [0xf8]: 0x00, + [0xf9]: 0x00, + [0xfa]: 0x00, + [0xfb]: 0x00, + [0xfc]: 0x00, + ], + }, + MemoryData { + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], }, small_slots: StatePart { value: [ 1, 0, 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 0, + 0, + 1, 0, 0, 0, 0, 1, 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 2, + 0, + 0, + 0, + 0, 2, 0, 0, @@ -7350,6 +55545,9 @@ Simulation { 0, 0, 0, + 0, + 0, + 0, 1, 0, 0, @@ -7373,33 +55571,103 @@ Simulation { 0, 0, 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, ], }, big_slots: StatePart { value: [ 0, 0, - 9673693953822641059020833, + 9905862608714384444439396385, 1, - 9681294011740541725728849, + 9913645068022314727150452817, 1, 0, 1, - 553402642445125034000, + 566684305863808035848208, 1, 4096, - 9673693953822641059020833, - 4836846976911320529510416, - 553402642445125034000, - 553402642445125034000, + 9905862608714384444439396385, + 4952931304357192222219698192, + 566684305863808035848208, + 566684305863808035848208, 1, 1, 4096, - 553402642445125034000, - 138350660611281258500, - 138350660611281258500, + 566684305863808035848208, + 141671076465952008962052, + 141671076465952008962052, 0, 1, + 0, + 1, + 0, 2, 3, 4, @@ -7412,6 +55680,9 @@ Simulation { 1, 0, 1, + 0, + 1, + 0, 2, 3, 4, @@ -7420,17 +55691,40 @@ Simulation { 0, 0, 1, + 0, + 1, + 0, 2, 3, 4, 4660, 0, - 138350660611281258500, - 34587665152820314625, - 20014614905345, - 20014614905345, + 141671076465952008962052, + 35417769116488002240513, + 20494965663137793, + 20494965663137793, 0, 1, + 0, + 1, + 0, + 1, + 0, + 1, + 65537, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, 2, 3, 4, @@ -7453,6 +55747,9 @@ Simulation { 1, 0, 1, + 0, + 1, + 0, 2, 3, 4, @@ -7461,10 +55758,13 @@ Simulation { 0, 15, 15, - 80058459621380, - 80058459621380, + 81979862652551172, + 81979862652551172, 0, 1, + 0, + 1, + 0, 2, 3, 4, @@ -7472,16 +55772,39 @@ Simulation { 0, 0, 1, + 0, + 1, + 0, 2, 3, 4, 4660, 0, - 80058459621380, - 40029229810690, - 40029229810690, + 81979862652551172, + 40989931326275586, + 40989931326275586, 0, 1, + 0, + 1, + 0, + 1, + 0, + 1, + 65537, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, 2, 3, 4, @@ -7492,18 +55815,41 @@ Simulation { 4660, 0, 0, - 80058459621380, + 81979862652551172, 0, 1, + 0, + 1, + 0, 2, 3, 4, 4660, 0, - 80058459621380, - 40029229810690, + 81979862652551172, + 40989931326275586, 0, 1, + 0, + 1, + 0, + 1, + 0, + 1, + 65537, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, 2, 3, 4, @@ -7514,21 +55860,24 @@ Simulation { 4660, 0, 0, - 221360928884518826024, + 226673591177747279904808, 0, 4100, - 9681294011740541725728849, - 4840647005870270862864424, - 221360928884518826024, - 221360928884518826024, + 9913645068022314727150452817, + 4956822534011157363575226408, + 226673591177747279904808, + 226673591177747279904808, 0, 0, 4100, - 221360928884518826024, - 55340232221129706506, - 55340232221129706506, + 226673591177747279904808, + 56668397794436819976202, + 56668397794436819976202, 0, 2, + 0, + 0, + 1, 3, 4, 0, @@ -7541,6 +55890,9 @@ Simulation { 0, 0, 2, + 0, + 0, + 1, 3, 4, 0, @@ -7549,17 +55901,40 @@ Simulation { 0, 0, 2, + 0, + 0, + 1, 3, 4, 0, 0, 0, - 55340232221129706506, - 13835058055282426626, - 262914, - 262914, + 56668397794436819976202, + 14167099448609204994050, + 269352962, + 269352962, 0, 2, + 0, + 0, + 1, + 2, + 0, + 2, + 131074, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 1, 3, 4, 0, @@ -7582,6 +55957,9 @@ Simulation { 0, 0, 2, + 0, + 0, + 1, 3, 4, 0, @@ -7590,10 +55968,13 @@ Simulation { 0, 6, 6, - 1051658, - 1051658, + 1077411850, + 1077411850, 1, 2, + 0, + 0, + 1, 3, 4, 0, @@ -7601,16 +55982,39 @@ Simulation { 0, 1, 2, + 0, + 0, + 1, 3, 4, 0, 0, 0, - 1051658, - 525829, - 525829, + 1077411850, + 538705925, + 538705925, 1, 2, + 0, + 0, + 1, + 2, + 0, + 2, + 131074, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 1, 3, 4, 0, @@ -7621,18 +56025,41 @@ Simulation { 0, 0, 0, - 1051658, + 1077411850, 1, 2, + 0, + 0, + 1, 3, 4, 0, 0, 0, - 1051658, - 525829, + 1077411850, + 538705925, 1, 2, + 0, + 0, + 1, + 2, + 0, + 2, + 131074, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 1, 3, 4, 0, @@ -7648,6 +56075,344 @@ Simulation { 0, 0, 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 0, 0, 0, @@ -7665,8 +56430,1486 @@ Simulation { 0, 0, 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 254, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 1, + 0, + 0, + 0, 1, 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 256, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 2, + 2, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 540432268011765760, + 540432268011765760, + 135108067002941440, + 135108067002941440, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 135108067002941440, + 33777016750735360, + 19545456640, + 19545456640, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 15, + 15, + 78181826560, + 78181826560, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 78181826560, + 39090913280, + 39090913280, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 78181826560, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 78181826560, + 39090913280, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 135108067002941440, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 135108067002941440, + 33777016750735360, + 19545456640, + 19545456640, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 15, + 15, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 0, + 0, + 0, + 4660, + 0, + 0, + 4660, + 4660, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 19545456640, + 19545456640, + 0, + 0, + 19545456640, + 0, + 19545456640, + 0, + 0, + 19545456640, + 1, + 2251799813685248, + 2251819359141888, + 1, + 4503599627370496, + 6755418986512384, + 1, + 9007199254740992, + 15762618241253376, + 1, + 18014398509481984, + 33777016750735360, + 135108067002941440, + 135108067002941440, + 135108067002941440, + 135108067002941440, + 0, + 0, + 2, + 0, + 0, + 3, + 1, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 262144, + 262144, + 19545456640, + 19545718784, + 0, + 0, + 19545718784, + 0, + 19545718784, + 0, + 0, + 19545718784, + 1, + 2251799813685248, + 2251819359404032, + 1, + 4503599627370496, + 6755418986774528, + 1, + 9007199254740992, + 15762618241515520, + 1, + 18014398509481984, + 33777016750997504, + 135108067003990016, + 135108067003990017, + 135108067003990017, + 135108067003990017, + 0, + 0, + 2, + 0, + 0, + 3, + 2, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 15, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 15, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 262144, + 262144, + 19545456640, + 19545718784, + 0, + 0, + 19545718784, + 0, + 19545718784, + 0, + 0, + 19545718784, + 33776997205278720, + 33777016750997504, + 135108067003990016, + 135108067003990018, + 135108067003990018, + 135108067003990018, + 0, + 135108067002941440, + 135108067002941440, + 540432268011765760, + 540432268011765760, + 540432268011765760, + 540432268011765760, + 78182875136, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 78182875136, + 39091437568, + 39091437568, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 16384, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 0, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 524288, + 524288, + 39090913280, + 39091437568, + 0, + 0, + 39091437568, + 0, + 39091437568, + 78182875136, + 78182875136, + 78182875136, + 78182875136, + 0, + 0, + 2, + 1, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 0, + 0, + 0, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 524288, + 524288, + 39090913280, + 39091437568, + 0, + 0, + 39091437568, + 0, + 39091437568, + 78182875136, + 78182875137, + 78182875137, + 78182875137, + 1, + 78182875136, + 78182875136, + 312731500544, + 312731500545, + 312731500545, + 312731500545, + 78182875136, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 78182875136, + 39091437568, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 16384, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 524288, + 524288, + 39090913280, + 39091437568, + 0, + 0, + 39091437568, + 0, + 39091437568, + 78182875136, + 78182875136, + 78182875136, + 78182875136, + 0, + 0, + 2, + 1, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 4, + 0, + 0, + 0, + 4660, + 4, + 0, + 4660, + 4, + 0, + 4, + 4, + 134217728, + 134222388, + 0, + 0, + 134222388, + 134222388, + 134222388, + 4660, + 4, + 4, + 4, + 0, + 0, + 4, + 4660, + 0, + 0, + 0, + 0, + 0, + 16384, + 16384, + 524288, + 524288, + 39090913280, + 39091437568, + 0, + 0, + 39091437568, + 0, + 39091437568, + 78182875136, + 78182875137, + 78182875137, + 78182875137, + 2, + 78182875136, + 78182875136, + 312731500544, + 312731500546, + 312731500546, + 312731500546, + 1, + 540432268011765760, + 540432268011765760, + 1080864536023531520, + 1080864536023531521, + 1080864536023531521, + 1080864536023531521, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 2, + 3, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 254, + 254, + 0, + 255, + 255, + 255, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934591, + 255, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 8589934338, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 254, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 1, + 2, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 2, + 0, + 0, + 1, + 216172782113783816, + 216172782113783816, + 54043195528445954, + 54043195528445954, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 54043195528445954, + 13510798882111488, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 6, + 6, 2, 2, 1, @@ -7676,16 +57919,474 @@ Simulation { 0, 0, 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 54043195528445954, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 54043195528445954, + 13510798882111488, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 6, + 6, + 0, + 0, + 3, + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 4503599627370496, + 4503599627370496, + 1, + 9007199254740992, + 13510798882111488, + 0, + 0, + 13510798882111488, + 54043195528445952, + 54043195528445952, + 54043195528445952, + 54043195528445952, + 0, + 0, + 3, + 0, + 0, + 4, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 4503599627370496, + 4503599627370496, + 1, + 9007199254740992, + 13510798882111488, + 0, + 0, + 13510798882111488, + 54043195528445952, + 54043195528445953, + 54043195528445953, + 54043195528445953, + 0, + 0, + 3, + 0, + 0, + 4, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 6, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 6, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 13510798882111488, + 13510798882111488, + 54043195528445952, + 54043195528445954, + 54043195528445954, + 54043195528445954, + 0, + 54043195528445954, + 54043195528445954, + 216172782113783816, + 216172782113783816, + 216172782113783816, + 216172782113783816, + 2, + 1, + 0, + 0, + 0, 0, 0, 0, 1, 0, + 0, + 0, + 0, + 0, + 0, + 2, + 1, + 1, 1, 0, - 1, - 1, - 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 0, 1, 0, @@ -7697,12 +58398,478 @@ Simulation { 1, 0, 0, + 0, + 0, + 0, + 0, 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 2, + 2, + 2, + 2, + 0, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 2, + 3, + 3, + 3, + 1, + 2, + 2, + 8, + 9, + 9, + 9, + 2, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 2, + 2, + 2, + 2, + 0, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 2, + 3, + 3, + 3, + 2, + 2, + 2, + 8, + 10, + 10, + 10, + 1, + 216172782113783816, + 216172782113783816, + 432345564227567632, + 432345564227567633, + 432345564227567633, + 432345564227567633, + 0, + 0, + 0, + 0, + 1, + 0, + 0, 1, 1, 1, 0, + 0, + 0, 1, + 1, + 1, + 2, + 3, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 0, 1, 0, @@ -7793,8 +58960,6 @@ Simulation { 0, 0, 0, - 0, - 1, 1, 1, 0, @@ -8060,6 +59225,1117 @@ Simulation { 0, 0, 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 2, + 3, + 3, + 3, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 1, + 0, + 1, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 1, + 0, + 1, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 7, + 0, + 0, + 3, + 0, + 3, + 7, + 7, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 1, + 0, + 1, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 1, + 0, + 1, + 3, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 7, + 0, + 0, + 3, + 0, + 3, + 7, + 7, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 15, + 0, + 0, + 7, + 0, + 7, + 15, + 15, + 0, + 0, + 0, + 0, + 0, + 1, + 15, + 30, + 31, + 31, + 31, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 2, + 0, + 2, + 0, + 2, + 2, + 0, + 0, + 2, + 4, + 5, + 5, + 5, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, 1, 1, ], @@ -8252,8 +60528,8 @@ Simulation { layout: CompiledTypeLayout { ty: Bundle { /* offset = 0 */ - decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, - #[hdl(flip)] /* offset = 272 */ + decoded_insns: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 292 */ fetch_decode_special_op: Bundle { /* offset = 0 */ data: Enum { @@ -8277,7 +60553,7 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8288,7 +60564,7 @@ Simulation { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8318,7 +60594,7 @@ Simulation { big_slots: StatePartIndex(0), }, ty: CompiledTypeLayout { - ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + ty: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, layout: TypeLayout { small_slots: StatePartLayout { len: 0, @@ -8332,7 +60608,7 @@ Simulation { name: "[0].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8343,7 +60619,7 @@ Simulation { name: "[1].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8360,9 +60636,9 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, layout: TypeLayout { @@ -8378,7 +60654,7 @@ Simulation { name: ".data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8399,7 +60675,7 @@ Simulation { ty: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -8414,7 +60690,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -8579,7 +60855,7 @@ Simulation { }, }.fetch_decode_interface.decoded_insns: CompiledValue { layout: CompiledTypeLayout { - ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + ty: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, layout: TypeLayout { small_slots: StatePartLayout { len: 0, @@ -8593,7 +60869,7 @@ Simulation { name: "[0].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8604,7 +60880,7 @@ Simulation { name: "[1].data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8621,9 +60897,9 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, layout: TypeLayout { @@ -8639,7 +60915,7 @@ Simulation { name: ".data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8660,7 +60936,7 @@ Simulation { ty: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -8675,7 +60951,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -8735,9 +61011,9 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, layout: TypeLayout { @@ -8753,7 +61029,7 @@ Simulation { name: ".data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8774,7 +61050,7 @@ Simulation { ty: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -8789,7 +61065,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -8845,7 +61121,7 @@ Simulation { layout: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -8860,7 +61136,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -8921,9 +61197,9 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, layout: TypeLayout { @@ -8939,7 +61215,7 @@ Simulation { name: ".data", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, SlotDebugData { @@ -8960,7 +61236,7 @@ Simulation { ty: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -8975,7 +61251,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -9031,7 +61307,7 @@ Simulation { layout: CompiledTypeLayout { ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, layout: TypeLayout { small_slots: StatePartLayout { @@ -9046,7 +61322,7 @@ Simulation { name: "", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, ], @@ -9337,7 +61613,7 @@ Simulation { name: "$tag", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, flow: Source, }, @@ -9346,14 +61622,14 @@ Simulation { name: "HdlSome", fields: [ TraceEnumWithFields { - name: "uop", + name: "mop", discriminant: TraceEnumDiscriminant { location: TraceScalarId(3), name: "$tag", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, flow: Source, }, @@ -9364,9 +61640,9 @@ Simulation { location: TraceScalarId(4), name: "$tag", ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, flow: Source, }, @@ -9386,29 +61662,131 @@ Simulation { ty: UInt<0>, flow: Source, }, - TraceUInt { - location: TraceScalarId(6), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(7), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(8), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(9), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(7), + location: TraceScalarId(10), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(8), + location: TraceScalarId(11), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(9), + location: TraceScalarId(12), name: "[2]", ty: UInt<8>, flow: Source, @@ -9418,13 +61796,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(10), + location: TraceScalarId(13), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(11), + location: TraceScalarId(14), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -9440,20 +61818,25 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, flow: Source, }, TraceFieldlessEnum { - location: TraceScalarId(12), + location: TraceScalarId(15), name: "output_integer_mode", ty: Enum { Full64, @@ -9474,17 +61857,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9499,22 +61887,22 @@ Simulation { flow: Source, }, TraceBool { - location: TraceScalarId(13), + location: TraceScalarId(16), name: "invert_src0", flow: Source, }, TraceBool { - location: TraceScalarId(14), + location: TraceScalarId(17), name: "invert_carry_in", flow: Source, }, TraceBool { - location: TraceScalarId(15), + location: TraceScalarId(18), name: "invert_carry_out", flow: Source, }, TraceBool { - location: TraceScalarId(16), + location: TraceScalarId(19), name: "add_pc", flow: Source, }, @@ -9527,17 +61915,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9549,13 +61942,13 @@ Simulation { SignExt8, }, }, - /* offset = 61 */ + /* offset = 71 */ invert_src0: Bool, - /* offset = 62 */ + /* offset = 72 */ invert_carry_in: Bool, - /* offset = 63 */ + /* offset = 73 */ invert_carry_out: Bool, - /* offset = 64 */ + /* offset = 74 */ add_pc: Bool, }, flow: Source, @@ -9570,34 +61963,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(17), + location: TraceScalarId(20), name: "prefix_pad", ty: UInt<0>, flow: Source, }, - TraceUInt { - location: TraceScalarId(18), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(21), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(22), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(23), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(24), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(19), + location: TraceScalarId(25), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(20), + location: TraceScalarId(26), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(21), + location: TraceScalarId(27), name: "[2]", ty: UInt<8>, flow: Source, @@ -9607,13 +62102,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(22), + location: TraceScalarId(28), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(23), + location: TraceScalarId(29), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -9629,20 +62124,25 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, flow: Source, }, TraceFieldlessEnum { - location: TraceScalarId(24), + location: TraceScalarId(30), name: "output_integer_mode", ty: Enum { Full64, @@ -9663,17 +62163,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9688,22 +62193,22 @@ Simulation { flow: Source, }, TraceBool { - location: TraceScalarId(25), + location: TraceScalarId(31), name: "invert_src0", flow: Source, }, TraceBool { - location: TraceScalarId(26), + location: TraceScalarId(32), name: "invert_carry_in", flow: Source, }, TraceBool { - location: TraceScalarId(27), + location: TraceScalarId(33), name: "invert_carry_out", flow: Source, }, TraceBool { - location: TraceScalarId(28), + location: TraceScalarId(34), name: "add_pc", flow: Source, }, @@ -9716,17 +62221,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9738,13 +62248,13 @@ Simulation { SignExt8, }, }, - /* offset = 61 */ + /* offset = 71 */ invert_src0: Bool, - /* offset = 62 */ + /* offset = 72 */ invert_carry_in: Bool, - /* offset = 63 */ + /* offset = 73 */ invert_carry_out: Bool, - /* offset = 64 */ + /* offset = 74 */ add_pc: Bool, }, flow: Source, @@ -9759,34 +62269,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(29), + location: TraceScalarId(35), name: "prefix_pad", ty: UInt<0>, flow: Source, }, - TraceUInt { - location: TraceScalarId(30), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(36), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(37), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(38), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(39), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(31), + location: TraceScalarId(40), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(32), + location: TraceScalarId(41), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(33), + location: TraceScalarId(42), name: "[2]", ty: UInt<8>, flow: Source, @@ -9796,13 +62408,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(34), + location: TraceScalarId(43), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(35), + location: TraceScalarId(44), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -9818,20 +62430,25 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, flow: Source, }, TraceFieldlessEnum { - location: TraceScalarId(36), + location: TraceScalarId(45), name: "output_integer_mode", ty: Enum { Full64, @@ -9852,17 +62469,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9877,7 +62499,7 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(37), + location: TraceScalarId(46), name: "lut", ty: UInt<4>, flow: Source, @@ -9891,17 +62513,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -9913,27 +62540,27 @@ Simulation { SignExt8, }, }, - /* offset = 61 */ + /* offset = 71 */ lut: UInt<4>, }, flow: Source, }, ], ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, flow: Source, }, TraceEnumWithFields { name: "L2RegisterFile", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(38), + location: TraceScalarId(47), name: "$tag", ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, flow: Source, }, @@ -9945,34 +62572,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(39), + location: TraceScalarId(48), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(40), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(49), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(50), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(51), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(52), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(41), + location: TraceScalarId(53), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(42), + location: TraceScalarId(54), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(43), + location: TraceScalarId(55), name: "[2]", ty: UInt<8>, flow: Source, @@ -9982,13 +62711,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(44), + location: TraceScalarId(56), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(45), + location: TraceScalarId(57), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -10004,14 +62733,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -10023,14 +62757,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, }, @@ -10043,34 +62782,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(46), + location: TraceScalarId(58), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(47), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(59), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(60), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(61), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(62), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(48), + location: TraceScalarId(63), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(49), + location: TraceScalarId(64), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(50), + location: TraceScalarId(65), name: "[2]", ty: UInt<8>, flow: Source, @@ -10080,13 +62921,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(51), + location: TraceScalarId(66), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(52), + location: TraceScalarId(67), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -10102,14 +62943,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -10121,14 +62967,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, }, @@ -10136,19 +62987,19 @@ Simulation { }, ], ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, flow: Source, }, TraceEnumWithFields { name: "LoadStore", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(53), + location: TraceScalarId(68), name: "$tag", ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, flow: Source, }, @@ -10157,34 +63008,136 @@ Simulation { name: "Load", fields: [ TraceUInt { - location: TraceScalarId(54), + location: TraceScalarId(69), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(55), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(70), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(71), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(72), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(73), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(56), + location: TraceScalarId(74), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(57), + location: TraceScalarId(75), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(58), + location: TraceScalarId(76), name: "[2]", ty: UInt<8>, flow: Source, @@ -10194,13 +63147,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(59), + location: TraceScalarId(77), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(60), + location: TraceScalarId(78), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -10216,14 +63169,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -10232,34 +63190,136 @@ Simulation { name: "Store", fields: [ TraceUInt { - location: TraceScalarId(61), + location: TraceScalarId(79), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(62), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(80), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(81), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(82), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(83), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(63), + location: TraceScalarId(84), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(64), + location: TraceScalarId(85), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(65), + location: TraceScalarId(86), name: "[2]", ty: UInt<8>, flow: Source, @@ -10269,13 +63329,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(66), + location: TraceScalarId(87), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(67), + location: TraceScalarId(88), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -10291,40 +63351,45 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, }, ], ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, flow: Source, }, ], ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, flow: Source, }, TraceBool { - location: TraceScalarId(68), + location: TraceScalarId(89), name: "is_unrelated_pc", flow: Source, }, TraceUInt { - location: TraceScalarId(69), + location: TraceScalarId(90), name: "pc", ty: UInt<64>, flow: Source, @@ -10332,14 +63397,14 @@ Simulation { ], ty: Bundle { /* offset = 0 */ - uop: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + mop: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, - /* offset = 69 */ + /* offset = 79 */ is_unrelated_pc: Bool, - /* offset = 70 */ + /* offset = 80 */ pc: UInt<64>, }, flow: Source, @@ -10347,12 +63412,12 @@ Simulation { ], ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, flow: Source, }, TraceBool { - location: TraceScalarId(70), + location: TraceScalarId(91), name: "ready", flow: Sink, }, @@ -10361,9 +63426,9 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, flow: Source, @@ -10374,11 +63439,11 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(71), + location: TraceScalarId(92), name: "$tag", ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, flow: Source, }, @@ -10387,14 +63452,14 @@ Simulation { name: "HdlSome", fields: [ TraceEnumWithFields { - name: "uop", + name: "mop", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(72), + location: TraceScalarId(93), name: "$tag", ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, flow: Source, }, @@ -10402,12 +63467,12 @@ Simulation { TraceEnumWithFields { name: "AluBranch", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(73), + location: TraceScalarId(94), name: "$tag", ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, flow: Source, }, @@ -10422,393 +63487,117 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(74), + location: TraceScalarId(95), name: "prefix_pad", ty: UInt<0>, flow: Source, }, - TraceUInt { - location: TraceScalarId(75), - name: "dest", - ty: UInt<8>, - flow: Source, - }, - TraceArray { - name: "src", - elements: [ - TraceUInt { - location: TraceScalarId(76), - name: "[0]", - ty: UInt<8>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(77), - name: "[1]", - ty: UInt<8>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(78), - name: "[2]", - ty: UInt<8>, - flow: Source, - }, - ], - ty: Array, 3>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(79), - name: "imm_low", - ty: UInt<25>, - flow: Source, - }, - TraceSInt { - location: TraceScalarId(80), - name: "imm_sign", - ty: SInt<1>, - flow: Source, - }, TraceBundle { - name: "_phantom", - fields: [], - ty: Bundle {}, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - flow: Source, - }, - TraceFieldlessEnum { - location: TraceScalarId(81), - name: "output_integer_mode", - ty: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - common: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - /* offset = 58 */ - output_integer_mode: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - }, - flow: Source, - }, - TraceBool { - location: TraceScalarId(82), - name: "invert_src0", - flow: Source, - }, - TraceBool { - location: TraceScalarId(83), - name: "invert_carry_in", - flow: Source, - }, - TraceBool { - location: TraceScalarId(84), - name: "invert_carry_out", - flow: Source, - }, - TraceBool { - location: TraceScalarId(85), - name: "add_pc", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - alu_common: Bundle { - /* offset = 0 */ - common: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - /* offset = 58 */ - output_integer_mode: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - }, - /* offset = 61 */ - invert_src0: Bool, - /* offset = 62 */ - invert_carry_in: Bool, - /* offset = 63 */ - invert_carry_out: Bool, - /* offset = 64 */ - add_pc: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "AddSubI", - fields: [ - TraceBundle { - name: "alu_common", - fields: [ - TraceBundle { - name: "common", - fields: [ - TraceUInt { - location: TraceScalarId(86), - name: "prefix_pad", - ty: UInt<0>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(87), name: "dest", - ty: UInt<8>, - flow: Source, - }, - TraceArray { - name: "src", - elements: [ - TraceUInt { - location: TraceScalarId(88), - name: "[0]", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(96), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(97), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, flow: Source, }, - TraceUInt { - location: TraceScalarId(89), - name: "[1]", - ty: UInt<8>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(90), - name: "[2]", - ty: UInt<8>, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(98), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(99), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, flow: Source, }, ], - ty: Array, 3>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(91), - name: "imm_low", - ty: UInt<25>, - flow: Source, - }, - TraceSInt { - location: TraceScalarId(92), - name: "imm_sign", - ty: SInt<1>, - flow: Source, - }, - TraceBundle { - name: "_phantom", - fields: [], - ty: Bundle {}, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - flow: Source, - }, - TraceFieldlessEnum { - location: TraceScalarId(93), - name: "output_integer_mode", - ty: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - common: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - /* offset = 58 */ - output_integer_mode: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - }, - flow: Source, - }, - TraceBool { - location: TraceScalarId(94), - name: "invert_src0", - flow: Source, - }, - TraceBool { - location: TraceScalarId(95), - name: "invert_carry_in", - flow: Source, - }, - TraceBool { - location: TraceScalarId(96), - name: "invert_carry_out", - flow: Source, - }, - TraceBool { - location: TraceScalarId(97), - name: "add_pc", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - alu_common: Bundle { - /* offset = 0 */ - common: Bundle { - /* offset = 0 */ - prefix_pad: UInt<0>, - /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ - src: Array, 3>, - /* offset = 32 */ - imm_low: UInt<25>, - /* offset = 57 */ - imm_sign: SInt<1>, - /* offset = 58 */ - _phantom: Bundle {}, - }, - /* offset = 58 */ - output_integer_mode: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - }, - /* offset = 61 */ - invert_src0: Bool, - /* offset = 62 */ - invert_carry_in: Bool, - /* offset = 63 */ - invert_carry_out: Bool, - /* offset = 64 */ - add_pc: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "Logical", - fields: [ - TraceBundle { - name: "alu_common", - fields: [ - TraceBundle { - name: "common", - fields: [ - TraceUInt { - location: TraceScalarId(98), - name: "prefix_pad", - ty: UInt<0>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(99), - name: "dest", - ty: UInt<8>, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { @@ -10859,14 +63648,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, flow: Source, @@ -10893,17 +63687,634 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(106), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(107), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(108), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(109), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + /* offset = 68 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 71 */ + invert_src0: Bool, + /* offset = 72 */ + invert_carry_in: Bool, + /* offset = 73 */ + invert_carry_out: Bool, + /* offset = 74 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(110), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(111), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(112), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(113), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(114), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(115), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(116), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(117), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(118), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(119), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(120), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + /* offset = 68 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(121), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(122), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(123), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(124), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + /* offset = 68 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 71 */ + invert_src0: Bool, + /* offset = 72 */ + invert_carry_in: Bool, + /* offset = 73 */ + invert_carry_out: Bool, + /* offset = 74 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(125), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(126), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(127), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(128), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(129), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(130), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(131), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(132), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(133), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(134), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(135), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ + src: Array, 3>, + /* offset = 42 */ + imm_low: UInt<25>, + /* offset = 67 */ + imm_sign: SInt<1>, + /* offset = 68 */ + _phantom: Bundle {}, + }, + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -10918,7 +64329,7 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(106), + location: TraceScalarId(136), name: "lut", ty: UInt<4>, flow: Source, @@ -10932,17 +64343,22 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<0>, /* offset = 0 */ - dest: UInt<8>, - /* offset = 8 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 18 */ src: Array, 3>, - /* offset = 32 */ + /* offset = 42 */ imm_low: UInt<25>, - /* offset = 57 */ + /* offset = 67 */ imm_sign: SInt<1>, - /* offset = 58 */ + /* offset = 68 */ _phantom: Bundle {}, }, - /* offset = 58 */ + /* offset = 68 */ output_integer_mode: Enum { Full64, DupLow32, @@ -10954,27 +64370,27 @@ Simulation { SignExt8, }, }, - /* offset = 61 */ + /* offset = 71 */ lut: UInt<4>, }, flow: Source, }, ], ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, flow: Source, }, TraceEnumWithFields { name: "L2RegisterFile", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(107), + location: TraceScalarId(137), name: "$tag", ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, flow: Source, }, @@ -10986,34 +64402,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(108), + location: TraceScalarId(138), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(109), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(139), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(140), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(141), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(142), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(110), + location: TraceScalarId(143), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(111), + location: TraceScalarId(144), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(112), + location: TraceScalarId(145), name: "[2]", ty: UInt<8>, flow: Source, @@ -11023,13 +64541,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(113), + location: TraceScalarId(146), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(114), + location: TraceScalarId(147), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -11045,14 +64563,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -11064,14 +64587,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, }, @@ -11084,34 +64612,136 @@ Simulation { name: "common", fields: [ TraceUInt { - location: TraceScalarId(115), + location: TraceScalarId(148), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(116), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(149), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(150), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(151), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(152), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(117), + location: TraceScalarId(153), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(118), + location: TraceScalarId(154), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(119), + location: TraceScalarId(155), name: "[2]", ty: UInt<8>, flow: Source, @@ -11121,13 +64751,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(120), + location: TraceScalarId(156), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(121), + location: TraceScalarId(157), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -11143,14 +64773,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -11162,14 +64797,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, }, @@ -11177,19 +64817,19 @@ Simulation { }, ], ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, flow: Source, }, TraceEnumWithFields { name: "LoadStore", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(122), + location: TraceScalarId(158), name: "$tag", ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, flow: Source, }, @@ -11198,34 +64838,136 @@ Simulation { name: "Load", fields: [ TraceUInt { - location: TraceScalarId(123), + location: TraceScalarId(159), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(124), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(160), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(161), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(162), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(163), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(125), + location: TraceScalarId(164), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(126), + location: TraceScalarId(165), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(127), + location: TraceScalarId(166), name: "[2]", ty: UInt<8>, flow: Source, @@ -11235,13 +64977,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(128), + location: TraceScalarId(167), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(129), + location: TraceScalarId(168), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -11257,14 +64999,19 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, @@ -11273,34 +65020,136 @@ Simulation { name: "Store", fields: [ TraceUInt { - location: TraceScalarId(130), + location: TraceScalarId(169), name: "prefix_pad", ty: UInt<1>, flow: Source, }, - TraceUInt { - location: TraceScalarId(131), + TraceBundle { name: "dest", - ty: UInt<8>, + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(170), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(171), + name: "value", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Source, + }, + ], + ty: Array}, 2>, + flow: Source, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(172), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(173), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, flow: Source, }, TraceArray { name: "src", elements: [ TraceUInt { - location: TraceScalarId(132), + location: TraceScalarId(174), name: "[0]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(133), + location: TraceScalarId(175), name: "[1]", ty: UInt<8>, flow: Source, }, TraceUInt { - location: TraceScalarId(134), + location: TraceScalarId(176), name: "[2]", ty: UInt<8>, flow: Source, @@ -11310,13 +65159,13 @@ Simulation { flow: Source, }, TraceUInt { - location: TraceScalarId(135), + location: TraceScalarId(177), name: "imm_low", ty: UInt<25>, flow: Source, }, TraceSInt { - location: TraceScalarId(136), + location: TraceScalarId(178), name: "imm_sign", ty: SInt<1>, flow: Source, @@ -11332,40 +65181,45 @@ Simulation { /* offset = 0 */ prefix_pad: UInt<1>, /* offset = 1 */ - dest: UInt<8>, - /* offset = 9 */ + dest: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + /* offset = 19 */ src: Array, 3>, - /* offset = 33 */ + /* offset = 43 */ imm_low: UInt<25>, - /* offset = 58 */ + /* offset = 68 */ imm_sign: SInt<1>, - /* offset = 59 */ + /* offset = 69 */ _phantom: Bundle {}, }, flow: Source, }, ], ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), }, flow: Source, }, ], ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, flow: Source, }, TraceBool { - location: TraceScalarId(137), + location: TraceScalarId(179), name: "is_unrelated_pc", flow: Source, }, TraceUInt { - location: TraceScalarId(138), + location: TraceScalarId(180), name: "pc", ty: UInt<64>, flow: Source, @@ -11373,14 +65227,14 @@ Simulation { ], ty: Bundle { /* offset = 0 */ - uop: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + mop: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, - /* offset = 69 */ + /* offset = 79 */ is_unrelated_pc: Bool, - /* offset = 70 */ + /* offset = 80 */ pc: UInt<64>, }, flow: Source, @@ -11388,12 +65242,12 @@ Simulation { ], ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, flow: Source, }, TraceBool { - location: TraceScalarId(139), + location: TraceScalarId(181), name: "ready", flow: Sink, }, @@ -11402,15 +65256,15 @@ Simulation { /* offset = 0 */ data: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, - #[hdl(flip)] /* offset = 135 */ + #[hdl(flip)] /* offset = 145 */ ready: Bool, }, flow: Source, }, ], - ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + ty: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, flow: Source, }, TraceBundle { @@ -11419,7 +65273,7 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(140), + location: TraceScalarId(182), name: "$tag", ty: Enum { HdlNone, @@ -11431,7 +65285,7 @@ Simulation { TraceEnumWithFields { name: "HdlSome", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(141), + location: TraceScalarId(183), name: "$tag", ty: Enum { Trap(Bundle {}), @@ -11461,7 +65315,7 @@ Simulation { flow: Sink, }, TraceBool { - location: TraceScalarId(142), + location: TraceScalarId(184), name: "ready", flow: Source, }, @@ -11480,8 +65334,8 @@ Simulation { ], ty: Bundle { /* offset = 0 */ - decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, - #[hdl(flip)] /* offset = 272 */ + decoded_insns: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 292 */ fetch_decode_special_op: Bundle { /* offset = 0 */ data: Enum { @@ -11496,8 +65350,8 @@ Simulation { }, ty: Bundle { /* offset = 0 */ - decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, - #[hdl(flip)] /* offset = 272 */ + decoded_insns: Array, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 292 */ fetch_decode_special_op: Bundle { /* offset = 0 */ data: Enum { @@ -11510,6 +65364,1550 @@ Simulation { }, flow: Source, }, + TraceMem { + id: TraceMemoryId(0), + name: "rename_table_normal_mem", + stride: 6, + element_type: TraceBundle { + name: "rename_table_normal_mem", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 253, + stride: 6, + start: 0, + len: 2, + }, + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 253, + stride: 6, + start: 2, + len: 4, + }, + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(185), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(186), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(187), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(188), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(189), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r1", + bundle: TraceBundle { + name: "r1", + fields: [ + TraceUInt { + location: TraceScalarId(190), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(191), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(192), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(193), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(194), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r2", + bundle: TraceBundle { + name: "r2", + fields: [ + TraceUInt { + location: TraceScalarId(195), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(196), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(197), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(198), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(199), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r3", + bundle: TraceBundle { + name: "r3", + fields: [ + TraceUInt { + location: TraceScalarId(200), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(201), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(202), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(203), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(204), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r4", + bundle: TraceBundle { + name: "r4", + fields: [ + TraceUInt { + location: TraceScalarId(205), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(206), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(207), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(208), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(209), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r5", + bundle: TraceBundle { + name: "r5", + fields: [ + TraceUInt { + location: TraceScalarId(210), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(211), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(212), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(213), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(214), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + ], + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + }, + TraceMem { + id: TraceMemoryId(1), + name: "rename_table_special_mem", + stride: 6, + element_type: TraceBundle { + name: "rename_table_special_mem", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 2, + stride: 6, + start: 0, + len: 2, + }, + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 2, + stride: 6, + start: 2, + len: 4, + }, + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(215), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(216), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(217), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(218), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(219), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r1", + bundle: TraceBundle { + name: "r1", + fields: [ + TraceUInt { + location: TraceScalarId(220), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(221), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(222), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(223), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(224), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r2", + bundle: TraceBundle { + name: "r2", + fields: [ + TraceUInt { + location: TraceScalarId(225), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(226), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(227), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(228), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(229), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r3", + bundle: TraceBundle { + name: "r3", + fields: [ + TraceUInt { + location: TraceScalarId(230), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(231), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(232), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(233), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(234), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r4", + bundle: TraceBundle { + name: "r4", + fields: [ + TraceUInt { + location: TraceScalarId(235), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(236), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(237), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(238), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(239), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r5", + bundle: TraceBundle { + name: "r5", + fields: [ + TraceUInt { + location: TraceScalarId(240), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(241), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(242), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(243), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(244), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + ], + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + }, TraceWire { name: "available_units", child: TraceArray { @@ -11519,80 +66917,2341 @@ Simulation { name: "[0]", elements: [ TraceBool { - location: TraceScalarId(143), + location: TraceScalarId(245), name: "[0]", flow: Duplex, }, + TraceBool { + location: TraceScalarId(246), + name: "[1]", + flow: Duplex, + }, ], - ty: Array, + ty: Array, flow: Duplex, }, TraceArray { name: "[1]", elements: [ TraceBool { - location: TraceScalarId(144), + location: TraceScalarId(247), name: "[0]", flow: Duplex, }, + TraceBool { + location: TraceScalarId(248), + name: "[1]", + flow: Duplex, + }, ], - ty: Array, + ty: Array, flow: Duplex, }, ], - ty: Array, 2>, + ty: Array, 2>, flow: Duplex, }, - ty: Array, 2>, + ty: Array, 2>, }, TraceWire { - name: "selected_unit_nums", + name: "selected_unit_indexes", child: TraceArray { - name: "selected_unit_nums", + name: "selected_unit_indexes", elements: [ TraceEnumWithFields { name: "[0]", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(145), + location: TraceScalarId(249), name: "$tag", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(UInt<2>), }, flow: Duplex, }, non_empty_fields: [ - TraceBundle { + TraceUInt { + location: TraceScalarId(250), name: "HdlSome", - fields: [ - TraceUInt { - location: TraceScalarId(146), - name: "value", - ty: UInt<1>, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - value: UInt<1>, - }, + ty: UInt<2>, flow: Source, }, ], ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(UInt<2>), }, flow: Duplex, }, TraceEnumWithFields { name: "[1]", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(147), + location: TraceScalarId(251), name: "$tag", ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(252), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ], + ty: Array)}, 2>, + flow: Duplex, + }, + ty: Array)}, 2>, + }, + TraceWire { + name: "renamed_mops", + child: TraceArray { + name: "renamed_mops", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(253), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(254), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(255), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(256), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(257), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(258), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(259), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(260), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(261), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(262), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(263), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(264), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(265), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(266), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(267), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(268), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(269), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(270), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(271), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(272), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(273), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(274), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(275), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(276), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(277), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(278), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(279), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(280), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(281), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(282), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(283), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(284), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(285), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(286), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(287), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(288), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(289), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(290), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(291), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(292), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(293), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(294), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(295), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(296), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(297), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(298), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(299), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(300), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(301), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(302), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(303), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(304), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(305), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(306), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(307), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(308), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(309), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(310), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(311), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(312), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(313), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(314), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(315), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(316), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(317), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(318), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(319), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(320), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(321), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(322), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(323), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(324), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(325), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(326), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(327), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(328), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(329), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(330), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(331), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(332), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(333), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(334), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(335), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(336), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(337), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(338), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(339), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(340), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(341), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(342), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(343), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(344), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(345), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(346), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(347), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(348), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(349), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(350), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(351), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(352), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(353), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(354), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(355), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(356), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(357), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(358), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(359), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(360), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(361), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(362), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(363), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(364), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(365), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(366), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(367), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(368), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(369), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(370), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(371), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(372), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(373), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(374), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(375), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(376), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(377), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(378), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(379), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(380), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(381), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(382), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(383), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(384), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + flow: Duplex, + }, + ], + ty: Array, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})}, 2>, + flow: Duplex, + }, + ty: Array, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})})}, 2>, + }, + TraceWire { + name: "renamed_mops_out_reg", + child: TraceArray { + name: "renamed_mops_out_reg", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(385), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), }, flow: Duplex, }, @@ -11600,36 +69259,847 @@ Simulation { TraceBundle { name: "HdlSome", fields: [ - TraceUInt { - location: TraceScalarId(148), - name: "value", - ty: UInt<1>, + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(386), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(387), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, flow: Source, }, ], ty: Bundle { /* offset = 0 */ - value: UInt<1>, + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, }, flow: Source, }, ], ty: Enum { HdlNone, - HdlSome(Bundle {value: UInt<1>}), + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(388), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(389), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(390), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), }, flow: Duplex, }, ], - ty: Array})}, 2>, + ty: Array}, unit_out_reg: Bundle {value: UInt<4>}})}, 2>, flow: Duplex, }, - ty: Array})}, 2>, + ty: Array}, unit_out_reg: Bundle {value: UInt<4>}})}, 2>, + }, + TraceWire { + name: "rename_table_normal_0_src_0", + child: TraceBundle { + name: "rename_table_normal_0_src_0", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(391), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(392), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(393), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(394), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "rename_table_normal_0_src_1", + child: TraceBundle { + name: "rename_table_normal_0_src_1", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(395), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(396), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(397), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(398), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "rename_table_normal_0_src_2", + child: TraceBundle { + name: "rename_table_normal_0_src_2", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(399), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(400), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(401), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(402), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "rename_table_special_0_src_0", + child: TraceBundle { + name: "rename_table_special_0_src_0", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(403), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(404), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(405), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(406), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "rename_table_special_0_src_1", + child: TraceBundle { + name: "rename_table_special_0_src_1", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(407), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(408), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(409), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(410), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "rename_table_special_0_src_2", + child: TraceBundle { + name: "rename_table_special_0_src_2", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(411), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(412), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(413), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(414), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, }, TraceWire { name: "unit_kind", child: TraceFieldlessEnum { - location: TraceScalarId(149), + location: TraceScalarId(415), name: "unit_kind", ty: Enum { AluBranch, @@ -11650,85 +70120,7171 @@ Simulation { name: "available_units_for_kind", elements: [ TraceBool { - location: TraceScalarId(150), + location: TraceScalarId(416), name: "[0]", flow: Duplex, }, + TraceBool { + location: TraceScalarId(417), + name: "[1]", + flow: Duplex, + }, ], - ty: Array, + ty: Array, flow: Duplex, }, - ty: Array, + ty: Array, }, TraceWire { - name: "selected_unit_leaf_0_0", - child: TraceEnumWithFields { - name: "selected_unit_leaf_0_0", - discriminant: TraceEnumDiscriminant { - location: TraceScalarId(151), - name: "$tag", - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - flow: Duplex, - }, - non_empty_fields: [ - TraceBundle { - name: "HdlSome", - fields: [ - TraceUInt { - location: TraceScalarId(152), - name: "value", - ty: UInt<1>, - flow: Source, + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(418), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(419), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, }, ], - ty: Bundle { - /* offset = 0 */ - value: UInt<1>, - }, - flow: Source, + ty: Array}, 2>, + flow: Duplex, }, - ], - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - flow: Duplex, - }, - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - TraceWire { - name: "unit_num_0_0", - child: TraceBundle { - name: "unit_num_0_0", - fields: [ - TraceUInt { - location: TraceScalarId(153), - name: "value", - ty: UInt<1>, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(420), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(421), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, flow: Duplex, }, ], ty: Bundle { /* offset = 0 */ - value: UInt<1>, + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, }, flow: Duplex, }, ty: Bundle { /* offset = 0 */ - value: UInt<1>, + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(422), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(423), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(424), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(425), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(426), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(427), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(428), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(429), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(430), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(431), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(432), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(433), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(434), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(435), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(436), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(437), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(438), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(439), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(440), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(441), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(442), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(443), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(444), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(445), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(446), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(447), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(448), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(449), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(450), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(451), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(452), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(453), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(454), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(455), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(456), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(457), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(458), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(459), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(460), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(461), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(462), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(463), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(464), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(465), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(466), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(467), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(468), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(469), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(470), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(471), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(472), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(473), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(474), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(475), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(476), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(477), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(478), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(479), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(480), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(481), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(482), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(483), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(484), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(485), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(486), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(487), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(488), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(489), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(490), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(491), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(492), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(493), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(494), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(495), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(496), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(497), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(498), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Duplex, + }, + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(499), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(500), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(501), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(502), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(503), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(504), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(505), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(506), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(507), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(508), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(509), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(510), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(511), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(512), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(513), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(514), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(515), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(516), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(517), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(518), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(519), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(520), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(521), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(522), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(523), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(524), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(525), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(526), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(527), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(528), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(529), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(530), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(531), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(532), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Duplex, + }, + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + TraceWire { + name: "renamed_src_reg_0_0", + child: TraceBundle { + name: "renamed_src_reg_0_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(533), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(534), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_1", + child: TraceBundle { + name: "renamed_src_reg_0_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(535), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(536), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_2", + child: TraceBundle { + name: "renamed_src_reg_0_2", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(537), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(538), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_0", + child: TraceBundle { + name: "renamed_src_reg_0_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(539), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(540), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_1", + child: TraceBundle { + name: "renamed_src_reg_0_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(541), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(542), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_0", + child: TraceBundle { + name: "renamed_src_reg_0_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(543), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(544), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_0_1", + child: TraceBundle { + name: "renamed_src_reg_0_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(545), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(546), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(547), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(548), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(549), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(550), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(551), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(552), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(553), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(554), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(555), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(556), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(557), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(558), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(559), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(560), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(561), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Duplex, + }, + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + TraceWire { + name: "renamed_src_reg_0_0", + child: TraceBundle { + name: "renamed_src_reg_0_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(562), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(563), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(564), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(565), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(566), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(567), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(568), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(569), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(570), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(571), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(572), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(573), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(574), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(575), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(576), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(577), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(578), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Duplex, + }, + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + TraceWire { + name: "renamed_src_reg_0_0", + child: TraceBundle { + name: "renamed_src_reg_0_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(579), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(580), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "selected_unit_index_leaf_0_0", + child: TraceEnumWithFields { + name: "selected_unit_index_leaf_0_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(581), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(582), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + TraceWire { + name: "unit_index_0_0", + child: TraceUInt { + location: TraceScalarId(583), + name: "unit_index_0_0", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceWire { + name: "selected_unit_index_leaf_0_1", + child: TraceEnumWithFields { + name: "selected_unit_index_leaf_0_1", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(584), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(585), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + TraceWire { + name: "unit_index_0_1", + child: TraceUInt { + location: TraceScalarId(586), + name: "unit_index_0_1", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceWire { + name: "selected_unit_index_node_0_0", + child: TraceEnumWithFields { + name: "selected_unit_index_node_0_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(587), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(588), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + TraceWire { + name: "rename_table_normal_1_src_0", + child: TraceBundle { + name: "rename_table_normal_1_src_0", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(589), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(590), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(591), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(592), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(593), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(594), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(595), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(596), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(597), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(598), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(599), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(600), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(601), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(602), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(603), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(604), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(605), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(606), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(607), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(608), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(609), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(610), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "rename_table_normal_1_src_1", + child: TraceBundle { + name: "rename_table_normal_1_src_1", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(611), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(612), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(613), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(614), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(615), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(616), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(617), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(618), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(619), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(620), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(621), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(622), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(623), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(624), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(625), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(626), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(627), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(628), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(629), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(630), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(631), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(632), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "rename_table_normal_1_src_2", + child: TraceBundle { + name: "rename_table_normal_1_src_2", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(633), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(634), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(635), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(636), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(637), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(638), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(639), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(640), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(641), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(642), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(643), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(644), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(645), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(646), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(647), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(648), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(649), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(650), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(651), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(652), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(653), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(654), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "rename_table_special_1_src_0", + child: TraceBundle { + name: "rename_table_special_1_src_0", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(655), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(656), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(657), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(658), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(659), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(660), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(661), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(662), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(663), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(664), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(665), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(666), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(667), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(668), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(669), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(670), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(671), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(672), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(673), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(674), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(675), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(676), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "rename_table_special_1_src_1", + child: TraceBundle { + name: "rename_table_special_1_src_1", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(677), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(678), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(679), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(680), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(681), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(682), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(683), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(684), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(685), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(686), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(687), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(688), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(689), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(690), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(691), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(692), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(693), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(694), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(695), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(696), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(697), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(698), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "rename_table_special_1_src_2", + child: TraceBundle { + name: "rename_table_special_1_src_2", + fields: [ + TraceBundle { + name: "addr", + fields: [ + TraceUInt { + location: TraceScalarId(699), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(700), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(701), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(702), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + addr: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + #[hdl(flip)] /* offset = 8 */ + data: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(703), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(704), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(705), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(706), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(707), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(708), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(709), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(710), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(711), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(712), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(713), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(714), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(715), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(716), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(717), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(718), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(719), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + }, + TraceWire { + name: "flag_reg", + child: TraceBundle { + name: "flag_reg", + fields: [ + TraceUInt { + location: TraceScalarId(720), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, }, }, TraceWire { name: "unit_kind", child: TraceFieldlessEnum { - location: TraceScalarId(154), + location: TraceScalarId(721), name: "unit_kind", ty: Enum { AluBranch, @@ -11749,79 +77305,3373 @@ Simulation { name: "available_units_for_kind", elements: [ TraceBool { - location: TraceScalarId(155), + location: TraceScalarId(722), name: "[0]", flow: Duplex, }, + TraceBool { + location: TraceScalarId(723), + name: "[1]", + flow: Duplex, + }, ], - ty: Array, + ty: Array, flow: Duplex, }, - ty: Array, + ty: Array, }, TraceWire { - name: "selected_unit_leaf_1_0", - child: TraceEnumWithFields { - name: "selected_unit_leaf_1_0", - discriminant: TraceEnumDiscriminant { - location: TraceScalarId(156), - name: "$tag", - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - flow: Duplex, - }, - non_empty_fields: [ - TraceBundle { - name: "HdlSome", - fields: [ - TraceUInt { - location: TraceScalarId(157), - name: "value", - ty: UInt<1>, - flow: Source, + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(724), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(725), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, }, ], - ty: Bundle { - /* offset = 0 */ - value: UInt<1>, - }, - flow: Source, + ty: Array}, 2>, + flow: Duplex, }, - ], - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - flow: Duplex, - }, - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - TraceWire { - name: "unit_num_1_0", - child: TraceBundle { - name: "unit_num_1_0", - fields: [ - TraceUInt { - location: TraceScalarId(158), - name: "value", - ty: UInt<1>, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(726), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(727), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, flow: Duplex, }, ], ty: Bundle { /* offset = 0 */ - value: UInt<1>, + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, }, flow: Duplex, }, ty: Bundle { /* offset = 0 */ - value: UInt<1>, + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(728), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(729), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(730), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(731), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(732), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(733), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(734), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(735), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "dest_reg", + child: TraceBundle { + name: "dest_reg", + fields: [ + TraceArray { + name: "normal_regs", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(736), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(737), + name: "value", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<8>, + }, + flow: Duplex, + }, + ], + ty: Array}, 2>, + flow: Duplex, + }, + TraceArray { + name: "flag_regs", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(738), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(739), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + normal_regs: Array}, 2>, + /* offset = 16 */ + flag_regs: Array, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(740), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(741), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(742), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(743), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(744), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(745), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(746), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(747), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(748), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(749), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(750), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(751), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(752), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(753), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(754), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(755), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(756), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(757), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(758), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(759), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(760), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(761), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(762), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(763), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(764), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(765), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(766), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(767), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(768), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(769), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(770), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(771), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(772), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(773), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(774), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(775), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(776), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(777), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(778), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(779), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(780), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(781), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(782), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(783), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(784), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(785), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(786), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(787), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(788), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(789), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(790), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(791), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(792), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(793), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(794), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(795), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(796), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(797), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(798), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(799), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(800), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(801), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(802), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(803), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(804), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Duplex, + }, + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(805), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(806), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(807), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(808), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(809), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(810), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(811), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(812), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(813), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(814), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(815), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(816), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(817), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(818), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(819), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(820), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(821), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(822), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(823), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(824), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(825), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(826), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(827), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(828), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(829), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(830), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(831), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(832), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(833), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(834), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(835), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(836), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(837), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(838), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Duplex, + }, + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + TraceWire { + name: "renamed_src_reg_1_0", + child: TraceBundle { + name: "renamed_src_reg_1_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(839), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(840), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_1", + child: TraceBundle { + name: "renamed_src_reg_1_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(841), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(842), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_2", + child: TraceBundle { + name: "renamed_src_reg_1_2", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(843), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(844), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_0", + child: TraceBundle { + name: "renamed_src_reg_1_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(845), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(846), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_1", + child: TraceBundle { + name: "renamed_src_reg_1_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(847), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(848), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_0", + child: TraceBundle { + name: "renamed_src_reg_1_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(849), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(850), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "renamed_src_reg_1_1", + child: TraceBundle { + name: "renamed_src_reg_1_1", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(851), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(852), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(853), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(854), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(855), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(856), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(857), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(858), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(859), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(860), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(861), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(862), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(863), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(864), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(865), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(866), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(867), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Duplex, + }, + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + TraceWire { + name: "renamed_src_reg_1_0", + child: TraceBundle { + name: "renamed_src_reg_1_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(868), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(869), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "mapped_regs", + child: TraceEnumWithFields { + name: "mapped_regs", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(870), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(871), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(872), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(873), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(874), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(875), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(876), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(877), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(878), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(879), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(880), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(881), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(882), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(883), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(884), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 5 */ + src: Array, 3>, + /* offset = 23 */ + imm_low: UInt<25>, + /* offset = 48 */ + imm_sign: SInt<1>, + /* offset = 49 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Duplex, + }, + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + TraceWire { + name: "renamed_src_reg_1_0", + child: TraceBundle { + name: "renamed_src_reg_1_0", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(885), + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(886), + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + TraceWire { + name: "selected_unit_index_leaf_1_0", + child: TraceEnumWithFields { + name: "selected_unit_index_leaf_1_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(887), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(888), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + TraceWire { + name: "unit_index_1_0", + child: TraceUInt { + location: TraceScalarId(889), + name: "unit_index_1_0", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceWire { + name: "selected_unit_index_leaf_1_1", + child: TraceEnumWithFields { + name: "selected_unit_index_leaf_1_1", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(890), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(891), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + TraceWire { + name: "unit_index_1_1", + child: TraceUInt { + location: TraceScalarId(892), + name: "unit_index_1_1", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceWire { + name: "selected_unit_index_node_1_0", + child: TraceEnumWithFields { + name: "selected_unit_index_node_1_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(893), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(894), + name: "HdlSome", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<2>), }, }, TraceInstance { @@ -11833,12 +80683,12 @@ Simulation { name: "cd", fields: [ TraceClock { - location: TraceScalarId(161), + location: TraceScalarId(933), name: "clk", flow: Sink, }, TraceSyncReset { - location: TraceScalarId(162), + location: TraceScalarId(934), name: "rst", flow: Sink, }, @@ -11851,6 +80701,670 @@ Simulation { }, flow: Sink, }, + TraceBundle { + name: "input", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(935), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(936), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(937), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(938), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(939), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(940), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(941), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(942), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(943), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(944), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(945), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(946), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(947), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(948), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(949), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(950), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(951), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(952), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(953), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(954), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(955), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(956), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(957), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(958), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(959), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(960), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(961), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(962), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(963), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(964), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(965), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(966), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(967), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(968), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(969), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(970), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Sink, + }, ], ty: Bundle { #[hdl(flip)] /* offset = 0 */ @@ -11860,6 +81374,16 @@ Simulation { /* offset = 1 */ rst: SyncReset, }, + #[hdl(flip)] /* offset = 2 */ + input: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, }, flow: Source, }, @@ -11872,12 +81396,12 @@ Simulation { name: "cd", fields: [ TraceClock { - location: TraceScalarId(159), + location: TraceScalarId(895), name: "clk", flow: Source, }, TraceSyncReset { - location: TraceScalarId(160), + location: TraceScalarId(896), name: "rst", flow: Source, }, @@ -11898,6 +81422,683 @@ Simulation { }, flow: Source, }, + TraceModuleIO { + name: "input", + child: TraceBundle { + name: "input", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(897), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(898), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(899), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(900), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(901), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(902), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(903), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(904), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(905), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(906), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(907), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(908), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(909), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(910), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(911), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(912), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(913), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(914), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(915), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(916), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(917), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(918), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(919), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(920), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(921), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(922), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(923), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(924), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(925), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(926), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(927), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(928), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(929), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(930), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(931), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(932), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Source, + }, ], }, ty: Bundle { @@ -11908,6 +82109,16 @@ Simulation { /* offset = 1 */ rst: SyncReset, }, + #[hdl(flip)] /* offset = 2 */ + input: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, }, }, TraceInstance { @@ -11919,12 +82130,12 @@ Simulation { name: "cd", fields: [ TraceClock { - location: TraceScalarId(236), + location: TraceScalarId(1044), name: "clk", flow: Sink, }, TraceSyncReset { - location: TraceScalarId(237), + location: TraceScalarId(1045), name: "rst", flow: Sink, }, @@ -11946,7 +82157,7 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(238), + location: TraceScalarId(1046), name: "$tag", ty: Enum { HdlNone, @@ -11956,7 +82167,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(239), + location: TraceScalarId(1047), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -11969,7 +82180,7 @@ Simulation { flow: Sink, }, TraceBool { - location: TraceScalarId(240), + location: TraceScalarId(1048), name: "ready", flow: Source, }, @@ -11998,7 +82209,7 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(241), + location: TraceScalarId(1049), name: "$tag", ty: Enum { HdlNone, @@ -12008,7 +82219,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(242), + location: TraceScalarId(1050), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -12021,7 +82232,7 @@ Simulation { flow: Source, }, TraceBool { - location: TraceScalarId(243), + location: TraceScalarId(1051), name: "ready", flow: Sink, }, @@ -12066,12 +82277,12 @@ Simulation { name: "cd", fields: [ TraceClock { - location: TraceScalarId(163), + location: TraceScalarId(971), name: "clk", flow: Source, }, TraceSyncReset { - location: TraceScalarId(164), + location: TraceScalarId(972), name: "rst", flow: Source, }, @@ -12103,7 +82314,7 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(165), + location: TraceScalarId(973), name: "$tag", ty: Enum { HdlNone, @@ -12113,7 +82324,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(166), + location: TraceScalarId(974), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -12126,7 +82337,7 @@ Simulation { flow: Source, }, TraceBool { - location: TraceScalarId(167), + location: TraceScalarId(975), name: "ready", flow: Sink, }, @@ -12160,7 +82371,7 @@ Simulation { TraceEnumWithFields { name: "data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(168), + location: TraceScalarId(976), name: "$tag", ty: Enum { HdlNone, @@ -12170,7 +82381,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(169), + location: TraceScalarId(977), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -12183,7 +82394,7 @@ Simulation { flow: Sink, }, TraceBool { - location: TraceScalarId(170), + location: TraceScalarId(978), name: "ready", flow: Source, }, @@ -12212,82 +82423,82 @@ Simulation { name: "allocated_reg", elements: [ TraceBool { - location: TraceScalarId(171), + location: TraceScalarId(979), name: "[0]", flow: Duplex, }, TraceBool { - location: TraceScalarId(172), + location: TraceScalarId(980), name: "[1]", flow: Duplex, }, TraceBool { - location: TraceScalarId(173), + location: TraceScalarId(981), name: "[2]", flow: Duplex, }, TraceBool { - location: TraceScalarId(174), + location: TraceScalarId(982), name: "[3]", flow: Duplex, }, TraceBool { - location: TraceScalarId(175), + location: TraceScalarId(983), name: "[4]", flow: Duplex, }, TraceBool { - location: TraceScalarId(176), + location: TraceScalarId(984), name: "[5]", flow: Duplex, }, TraceBool { - location: TraceScalarId(177), + location: TraceScalarId(985), name: "[6]", flow: Duplex, }, TraceBool { - location: TraceScalarId(178), + location: TraceScalarId(986), name: "[7]", flow: Duplex, }, TraceBool { - location: TraceScalarId(179), + location: TraceScalarId(987), name: "[8]", flow: Duplex, }, TraceBool { - location: TraceScalarId(180), + location: TraceScalarId(988), name: "[9]", flow: Duplex, }, TraceBool { - location: TraceScalarId(181), + location: TraceScalarId(989), name: "[10]", flow: Duplex, }, TraceBool { - location: TraceScalarId(182), + location: TraceScalarId(990), name: "[11]", flow: Duplex, }, TraceBool { - location: TraceScalarId(183), + location: TraceScalarId(991), name: "[12]", flow: Duplex, }, TraceBool { - location: TraceScalarId(184), + location: TraceScalarId(992), name: "[13]", flow: Duplex, }, TraceBool { - location: TraceScalarId(185), + location: TraceScalarId(993), name: "[14]", flow: Duplex, }, TraceBool { - location: TraceScalarId(186), + location: TraceScalarId(994), name: "[15]", flow: Duplex, }, @@ -12302,7 +82513,7 @@ Simulation { child: TraceEnumWithFields { name: "firing_data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(187), + location: TraceScalarId(995), name: "$tag", ty: Enum { HdlNone, @@ -12312,7 +82523,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(188), + location: TraceScalarId(996), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -12332,7 +82543,7 @@ Simulation { TraceWire { name: "reduced_count_0_2", child: TraceUInt { - location: TraceScalarId(189), + location: TraceScalarId(997), name: "reduced_count_0_2", ty: UInt<1>, flow: Duplex, @@ -12342,7 +82553,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_0_2", child: TraceBool { - location: TraceScalarId(190), + location: TraceScalarId(998), name: "reduced_count_overflowed_0_2", flow: Duplex, }, @@ -12354,7 +82565,7 @@ Simulation { name: "reduced_alloc_nums_0_2", elements: [ TraceUInt { - location: TraceScalarId(191), + location: TraceScalarId(999), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12368,7 +82579,7 @@ Simulation { TraceWire { name: "reduced_count_2_4", child: TraceUInt { - location: TraceScalarId(192), + location: TraceScalarId(1000), name: "reduced_count_2_4", ty: UInt<1>, flow: Duplex, @@ -12378,7 +82589,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_2_4", child: TraceBool { - location: TraceScalarId(193), + location: TraceScalarId(1001), name: "reduced_count_overflowed_2_4", flow: Duplex, }, @@ -12390,7 +82601,7 @@ Simulation { name: "reduced_alloc_nums_2_4", elements: [ TraceUInt { - location: TraceScalarId(194), + location: TraceScalarId(1002), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12404,7 +82615,7 @@ Simulation { TraceWire { name: "reduced_count_0_4", child: TraceUInt { - location: TraceScalarId(195), + location: TraceScalarId(1003), name: "reduced_count_0_4", ty: UInt<1>, flow: Duplex, @@ -12414,7 +82625,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_0_4", child: TraceBool { - location: TraceScalarId(196), + location: TraceScalarId(1004), name: "reduced_count_overflowed_0_4", flow: Duplex, }, @@ -12426,7 +82637,7 @@ Simulation { name: "reduced_alloc_nums_0_4", elements: [ TraceUInt { - location: TraceScalarId(197), + location: TraceScalarId(1005), name: "[0]", ty: UInt<2>, flow: Duplex, @@ -12440,7 +82651,7 @@ Simulation { TraceWire { name: "reduced_count_4_6", child: TraceUInt { - location: TraceScalarId(198), + location: TraceScalarId(1006), name: "reduced_count_4_6", ty: UInt<1>, flow: Duplex, @@ -12450,7 +82661,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_4_6", child: TraceBool { - location: TraceScalarId(199), + location: TraceScalarId(1007), name: "reduced_count_overflowed_4_6", flow: Duplex, }, @@ -12462,7 +82673,7 @@ Simulation { name: "reduced_alloc_nums_4_6", elements: [ TraceUInt { - location: TraceScalarId(200), + location: TraceScalarId(1008), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12476,7 +82687,7 @@ Simulation { TraceWire { name: "reduced_count_6_8", child: TraceUInt { - location: TraceScalarId(201), + location: TraceScalarId(1009), name: "reduced_count_6_8", ty: UInt<1>, flow: Duplex, @@ -12486,7 +82697,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_6_8", child: TraceBool { - location: TraceScalarId(202), + location: TraceScalarId(1010), name: "reduced_count_overflowed_6_8", flow: Duplex, }, @@ -12498,7 +82709,7 @@ Simulation { name: "reduced_alloc_nums_6_8", elements: [ TraceUInt { - location: TraceScalarId(203), + location: TraceScalarId(1011), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12512,7 +82723,7 @@ Simulation { TraceWire { name: "reduced_count_4_8", child: TraceUInt { - location: TraceScalarId(204), + location: TraceScalarId(1012), name: "reduced_count_4_8", ty: UInt<1>, flow: Duplex, @@ -12522,7 +82733,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_4_8", child: TraceBool { - location: TraceScalarId(205), + location: TraceScalarId(1013), name: "reduced_count_overflowed_4_8", flow: Duplex, }, @@ -12534,7 +82745,7 @@ Simulation { name: "reduced_alloc_nums_4_8", elements: [ TraceUInt { - location: TraceScalarId(206), + location: TraceScalarId(1014), name: "[0]", ty: UInt<2>, flow: Duplex, @@ -12548,7 +82759,7 @@ Simulation { TraceWire { name: "reduced_count_0_8", child: TraceUInt { - location: TraceScalarId(207), + location: TraceScalarId(1015), name: "reduced_count_0_8", ty: UInt<1>, flow: Duplex, @@ -12558,7 +82769,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_0_8", child: TraceBool { - location: TraceScalarId(208), + location: TraceScalarId(1016), name: "reduced_count_overflowed_0_8", flow: Duplex, }, @@ -12570,7 +82781,7 @@ Simulation { name: "reduced_alloc_nums_0_8", elements: [ TraceUInt { - location: TraceScalarId(209), + location: TraceScalarId(1017), name: "[0]", ty: UInt<3>, flow: Duplex, @@ -12584,7 +82795,7 @@ Simulation { TraceWire { name: "reduced_count_8_10", child: TraceUInt { - location: TraceScalarId(210), + location: TraceScalarId(1018), name: "reduced_count_8_10", ty: UInt<1>, flow: Duplex, @@ -12594,7 +82805,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_8_10", child: TraceBool { - location: TraceScalarId(211), + location: TraceScalarId(1019), name: "reduced_count_overflowed_8_10", flow: Duplex, }, @@ -12606,7 +82817,7 @@ Simulation { name: "reduced_alloc_nums_8_10", elements: [ TraceUInt { - location: TraceScalarId(212), + location: TraceScalarId(1020), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12620,7 +82831,7 @@ Simulation { TraceWire { name: "reduced_count_10_12", child: TraceUInt { - location: TraceScalarId(213), + location: TraceScalarId(1021), name: "reduced_count_10_12", ty: UInt<1>, flow: Duplex, @@ -12630,7 +82841,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_10_12", child: TraceBool { - location: TraceScalarId(214), + location: TraceScalarId(1022), name: "reduced_count_overflowed_10_12", flow: Duplex, }, @@ -12642,7 +82853,7 @@ Simulation { name: "reduced_alloc_nums_10_12", elements: [ TraceUInt { - location: TraceScalarId(215), + location: TraceScalarId(1023), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12656,7 +82867,7 @@ Simulation { TraceWire { name: "reduced_count_8_12", child: TraceUInt { - location: TraceScalarId(216), + location: TraceScalarId(1024), name: "reduced_count_8_12", ty: UInt<1>, flow: Duplex, @@ -12666,7 +82877,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_8_12", child: TraceBool { - location: TraceScalarId(217), + location: TraceScalarId(1025), name: "reduced_count_overflowed_8_12", flow: Duplex, }, @@ -12678,7 +82889,7 @@ Simulation { name: "reduced_alloc_nums_8_12", elements: [ TraceUInt { - location: TraceScalarId(218), + location: TraceScalarId(1026), name: "[0]", ty: UInt<2>, flow: Duplex, @@ -12692,7 +82903,7 @@ Simulation { TraceWire { name: "reduced_count_12_14", child: TraceUInt { - location: TraceScalarId(219), + location: TraceScalarId(1027), name: "reduced_count_12_14", ty: UInt<1>, flow: Duplex, @@ -12702,7 +82913,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_12_14", child: TraceBool { - location: TraceScalarId(220), + location: TraceScalarId(1028), name: "reduced_count_overflowed_12_14", flow: Duplex, }, @@ -12714,7 +82925,7 @@ Simulation { name: "reduced_alloc_nums_12_14", elements: [ TraceUInt { - location: TraceScalarId(221), + location: TraceScalarId(1029), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12728,7 +82939,7 @@ Simulation { TraceWire { name: "reduced_count_14_16", child: TraceUInt { - location: TraceScalarId(222), + location: TraceScalarId(1030), name: "reduced_count_14_16", ty: UInt<1>, flow: Duplex, @@ -12738,7 +82949,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_14_16", child: TraceBool { - location: TraceScalarId(223), + location: TraceScalarId(1031), name: "reduced_count_overflowed_14_16", flow: Duplex, }, @@ -12750,7 +82961,7 @@ Simulation { name: "reduced_alloc_nums_14_16", elements: [ TraceUInt { - location: TraceScalarId(224), + location: TraceScalarId(1032), name: "[0]", ty: UInt<1>, flow: Duplex, @@ -12764,7 +82975,7 @@ Simulation { TraceWire { name: "reduced_count_12_16", child: TraceUInt { - location: TraceScalarId(225), + location: TraceScalarId(1033), name: "reduced_count_12_16", ty: UInt<1>, flow: Duplex, @@ -12774,7 +82985,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_12_16", child: TraceBool { - location: TraceScalarId(226), + location: TraceScalarId(1034), name: "reduced_count_overflowed_12_16", flow: Duplex, }, @@ -12786,7 +82997,7 @@ Simulation { name: "reduced_alloc_nums_12_16", elements: [ TraceUInt { - location: TraceScalarId(227), + location: TraceScalarId(1035), name: "[0]", ty: UInt<2>, flow: Duplex, @@ -12800,7 +83011,7 @@ Simulation { TraceWire { name: "reduced_count_8_16", child: TraceUInt { - location: TraceScalarId(228), + location: TraceScalarId(1036), name: "reduced_count_8_16", ty: UInt<1>, flow: Duplex, @@ -12810,7 +83021,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_8_16", child: TraceBool { - location: TraceScalarId(229), + location: TraceScalarId(1037), name: "reduced_count_overflowed_8_16", flow: Duplex, }, @@ -12822,7 +83033,7 @@ Simulation { name: "reduced_alloc_nums_8_16", elements: [ TraceUInt { - location: TraceScalarId(230), + location: TraceScalarId(1038), name: "[0]", ty: UInt<3>, flow: Duplex, @@ -12836,7 +83047,7 @@ Simulation { TraceWire { name: "reduced_count_0_16", child: TraceUInt { - location: TraceScalarId(231), + location: TraceScalarId(1039), name: "reduced_count_0_16", ty: UInt<1>, flow: Duplex, @@ -12846,7 +83057,7 @@ Simulation { TraceWire { name: "reduced_count_overflowed_0_16", child: TraceBool { - location: TraceScalarId(232), + location: TraceScalarId(1040), name: "reduced_count_overflowed_0_16", flow: Duplex, }, @@ -12858,7 +83069,7 @@ Simulation { name: "reduced_alloc_nums_0_16", elements: [ TraceUInt { - location: TraceScalarId(233), + location: TraceScalarId(1041), name: "[0]", ty: UInt<4>, flow: Duplex, @@ -12874,7 +83085,7 @@ Simulation { child: TraceEnumWithFields { name: "firing_data", discriminant: TraceEnumDiscriminant { - location: TraceScalarId(234), + location: TraceScalarId(1042), name: "$tag", ty: Enum { HdlNone, @@ -12884,7 +83095,7 @@ Simulation { }, non_empty_fields: [ TraceUInt { - location: TraceScalarId(235), + location: TraceScalarId(1043), name: "HdlSome", ty: UInt<4>, flow: Source, @@ -12917,6 +83128,7668 @@ Simulation { alloc_out: Array)}, #[hdl(flip)] ready: Bool}, 1>, }, }, + TraceWire { + name: "and_then_out", + child: TraceEnumWithFields { + name: "and_then_out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1052), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1053), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1054), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1055), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1056), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1057), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1058), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1059), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1060), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1061), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1062), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1063), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1064), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1065), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1066), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1067), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1068), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1069), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1070), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1071), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1072), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1073), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1074), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1075), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1076), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1077), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1078), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1079), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1080), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1081), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1082), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1083), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1084), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1085), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1086), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "alu_branch_mop", + child: TraceEnumWithFields { + name: "alu_branch_mop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1087), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1088), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1089), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1090), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1091), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1092), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1093), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1094), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1095), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1096), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1097), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1098), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1099), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1100), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1101), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1102), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1103), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1104), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1105), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1106), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1107), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1108), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1109), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1110), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1111), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1112), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1113), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1114), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1115), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1116), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1117), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1118), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1119), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1120), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1121), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "and_then_out", + child: TraceEnumWithFields { + name: "and_then_out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1122), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1123), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1124), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1125), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1126), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1127), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1128), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1129), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1130), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1131), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1132), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1133), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1134), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1135), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1136), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1137), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1138), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1139), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1140), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1141), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1142), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1143), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1144), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1145), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1146), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1147), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1148), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1149), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1150), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1151), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1152), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1153), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1154), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1155), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1156), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "alu_branch_mop", + child: TraceEnumWithFields { + name: "alu_branch_mop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1157), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1158), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1159), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1160), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1161), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1162), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1163), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1164), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1165), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1166), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1167), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1168), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1169), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1170), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1171), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1172), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1173), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1174), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1175), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1176), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1177), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1178), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1179), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1180), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1181), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1182), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1183), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1184), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1185), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1186), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1187), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1188), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1189), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1190), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1191), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceInstance { + name: "unit_1", + instance_io: TraceBundle { + name: "unit_1", + fields: [ + TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(1230), + name: "clk", + flow: Sink, + }, + TraceSyncReset { + location: TraceScalarId(1231), + name: "rst", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Sink, + }, + TraceBundle { + name: "input", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1232), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1233), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1234), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1235), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1236), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1237), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1238), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1239), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1240), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1241), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1242), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1243), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1244), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1245), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1246), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1247), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1248), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1249), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1250), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1251), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1252), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1253), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1254), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1255), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1256), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1257), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1258), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1259), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1260), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1261), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1262), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1263), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1264), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1265), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1266), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(1267), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + input: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + }, + flow: Source, + }, + module: TraceModule { + name: "alu_branch", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(1192), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1193), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "input", + child: TraceBundle { + name: "input", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1194), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1195), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1196), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1197), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1198), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1199), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1200), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1201), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1202), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1203), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1204), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1205), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1206), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1207), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1208), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1209), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1210), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1211), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1212), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1213), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1214), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1215), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1216), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1217), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1218), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1219), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1220), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1221), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1222), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1223), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1224), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1225), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1226), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1227), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1228), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1229), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + flow: Source, + }, + ], + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + input: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + #[hdl(flip)] /* offset = 58 */ + ready: Bool, + }, + }, + }, + TraceInstance { + name: "unit_1_free_regs_tracker", + instance_io: TraceBundle { + name: "unit_1_free_regs_tracker", + fields: [ + TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(1341), + name: "clk", + flow: Sink, + }, + TraceSyncReset { + location: TraceScalarId(1342), + name: "rst", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Sink, + }, + TraceArray { + name: "free_in", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1343), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1344), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(1345), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + TraceArray { + name: "alloc_out", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1346), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1347), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1348), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Source, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + free_in: Array)}, #[hdl(flip)] ready: Bool}, 1>, + /* offset = 8 */ + alloc_out: Array)}, #[hdl(flip)] ready: Bool}, 1>, + }, + flow: Source, + }, + module: TraceModule { + name: "unit_free_regs_tracker", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(1268), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1269), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "free_in", + child: TraceArray { + name: "free_in", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1270), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1271), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1272), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Source, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + TraceModuleIO { + name: "alloc_out", + child: TraceArray { + name: "alloc_out", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1273), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1274), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(1275), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + TraceReg { + name: "allocated_reg", + child: TraceArray { + name: "allocated_reg", + elements: [ + TraceBool { + location: TraceScalarId(1276), + name: "[0]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1277), + name: "[1]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1278), + name: "[2]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1279), + name: "[3]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1280), + name: "[4]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1281), + name: "[5]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1282), + name: "[6]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1283), + name: "[7]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1284), + name: "[8]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1285), + name: "[9]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1286), + name: "[10]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1287), + name: "[11]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1288), + name: "[12]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1289), + name: "[13]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1290), + name: "[14]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(1291), + name: "[15]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ty: Array, + }, + TraceWire { + name: "firing_data", + child: TraceEnumWithFields { + name: "firing_data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1292), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1293), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + TraceWire { + name: "reduced_count_0_2", + child: TraceUInt { + location: TraceScalarId(1294), + name: "reduced_count_0_2", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_2", + child: TraceBool { + location: TraceScalarId(1295), + name: "reduced_count_overflowed_0_2", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_2", + child: TraceArray { + name: "reduced_alloc_nums_0_2", + elements: [ + TraceUInt { + location: TraceScalarId(1296), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_2_4", + child: TraceUInt { + location: TraceScalarId(1297), + name: "reduced_count_2_4", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_2_4", + child: TraceBool { + location: TraceScalarId(1298), + name: "reduced_count_overflowed_2_4", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_2_4", + child: TraceArray { + name: "reduced_alloc_nums_2_4", + elements: [ + TraceUInt { + location: TraceScalarId(1299), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_4", + child: TraceUInt { + location: TraceScalarId(1300), + name: "reduced_count_0_4", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_4", + child: TraceBool { + location: TraceScalarId(1301), + name: "reduced_count_overflowed_0_4", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_4", + child: TraceArray { + name: "reduced_alloc_nums_0_4", + elements: [ + TraceUInt { + location: TraceScalarId(1302), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_4_6", + child: TraceUInt { + location: TraceScalarId(1303), + name: "reduced_count_4_6", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_4_6", + child: TraceBool { + location: TraceScalarId(1304), + name: "reduced_count_overflowed_4_6", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_4_6", + child: TraceArray { + name: "reduced_alloc_nums_4_6", + elements: [ + TraceUInt { + location: TraceScalarId(1305), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_6_8", + child: TraceUInt { + location: TraceScalarId(1306), + name: "reduced_count_6_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_6_8", + child: TraceBool { + location: TraceScalarId(1307), + name: "reduced_count_overflowed_6_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_6_8", + child: TraceArray { + name: "reduced_alloc_nums_6_8", + elements: [ + TraceUInt { + location: TraceScalarId(1308), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_4_8", + child: TraceUInt { + location: TraceScalarId(1309), + name: "reduced_count_4_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_4_8", + child: TraceBool { + location: TraceScalarId(1310), + name: "reduced_count_overflowed_4_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_4_8", + child: TraceArray { + name: "reduced_alloc_nums_4_8", + elements: [ + TraceUInt { + location: TraceScalarId(1311), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_8", + child: TraceUInt { + location: TraceScalarId(1312), + name: "reduced_count_0_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_8", + child: TraceBool { + location: TraceScalarId(1313), + name: "reduced_count_overflowed_0_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_8", + child: TraceArray { + name: "reduced_alloc_nums_0_8", + elements: [ + TraceUInt { + location: TraceScalarId(1314), + name: "[0]", + ty: UInt<3>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_10", + child: TraceUInt { + location: TraceScalarId(1315), + name: "reduced_count_8_10", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_10", + child: TraceBool { + location: TraceScalarId(1316), + name: "reduced_count_overflowed_8_10", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_10", + child: TraceArray { + name: "reduced_alloc_nums_8_10", + elements: [ + TraceUInt { + location: TraceScalarId(1317), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_10_12", + child: TraceUInt { + location: TraceScalarId(1318), + name: "reduced_count_10_12", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_10_12", + child: TraceBool { + location: TraceScalarId(1319), + name: "reduced_count_overflowed_10_12", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_10_12", + child: TraceArray { + name: "reduced_alloc_nums_10_12", + elements: [ + TraceUInt { + location: TraceScalarId(1320), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_12", + child: TraceUInt { + location: TraceScalarId(1321), + name: "reduced_count_8_12", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_12", + child: TraceBool { + location: TraceScalarId(1322), + name: "reduced_count_overflowed_8_12", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_12", + child: TraceArray { + name: "reduced_alloc_nums_8_12", + elements: [ + TraceUInt { + location: TraceScalarId(1323), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_12_14", + child: TraceUInt { + location: TraceScalarId(1324), + name: "reduced_count_12_14", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_12_14", + child: TraceBool { + location: TraceScalarId(1325), + name: "reduced_count_overflowed_12_14", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_12_14", + child: TraceArray { + name: "reduced_alloc_nums_12_14", + elements: [ + TraceUInt { + location: TraceScalarId(1326), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_14_16", + child: TraceUInt { + location: TraceScalarId(1327), + name: "reduced_count_14_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_14_16", + child: TraceBool { + location: TraceScalarId(1328), + name: "reduced_count_overflowed_14_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_14_16", + child: TraceArray { + name: "reduced_alloc_nums_14_16", + elements: [ + TraceUInt { + location: TraceScalarId(1329), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_12_16", + child: TraceUInt { + location: TraceScalarId(1330), + name: "reduced_count_12_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_12_16", + child: TraceBool { + location: TraceScalarId(1331), + name: "reduced_count_overflowed_12_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_12_16", + child: TraceArray { + name: "reduced_alloc_nums_12_16", + elements: [ + TraceUInt { + location: TraceScalarId(1332), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_16", + child: TraceUInt { + location: TraceScalarId(1333), + name: "reduced_count_8_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_16", + child: TraceBool { + location: TraceScalarId(1334), + name: "reduced_count_overflowed_8_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_16", + child: TraceArray { + name: "reduced_alloc_nums_8_16", + elements: [ + TraceUInt { + location: TraceScalarId(1335), + name: "[0]", + ty: UInt<3>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_16", + child: TraceUInt { + location: TraceScalarId(1336), + name: "reduced_count_0_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_16", + child: TraceBool { + location: TraceScalarId(1337), + name: "reduced_count_overflowed_0_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_16", + child: TraceArray { + name: "reduced_alloc_nums_0_16", + elements: [ + TraceUInt { + location: TraceScalarId(1338), + name: "[0]", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "firing_data", + child: TraceEnumWithFields { + name: "firing_data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1339), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(1340), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + ], + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + free_in: Array)}, #[hdl(flip)] ready: Bool}, 1>, + /* offset = 8 */ + alloc_out: Array)}, #[hdl(flip)] ready: Bool}, 1>, + }, + }, + TraceWire { + name: "and_then_out", + child: TraceEnumWithFields { + name: "and_then_out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1349), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1350), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1351), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1352), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1353), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1354), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1355), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1356), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1357), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1358), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1359), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1360), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1361), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1362), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1363), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1364), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1365), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1366), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1367), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1368), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1369), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1370), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1371), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1372), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1373), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1374), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1375), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1376), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1377), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1378), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1379), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1380), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1381), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1382), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1383), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "alu_branch_mop", + child: TraceEnumWithFields { + name: "alu_branch_mop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1384), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1385), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1386), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1387), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1388), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1389), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1390), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1391), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1392), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1393), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1394), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1395), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1396), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1397), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1398), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1399), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1400), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1401), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1402), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1403), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1404), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1405), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1406), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1407), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1408), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1409), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1410), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1411), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1412), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1413), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1414), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1415), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1416), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1417), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1418), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "and_then_out", + child: TraceEnumWithFields { + name: "and_then_out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1419), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1420), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1421), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1422), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1423), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1424), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1425), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1426), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1427), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1428), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1429), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1430), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1431), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1432), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1433), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1434), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1435), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1436), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1437), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1438), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1439), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1440), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1441), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1442), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1443), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1444), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1445), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1446), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1447), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1448), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1449), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1450), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1451), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1452), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1453), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + TraceWire { + name: "alu_branch_mop", + child: TraceEnumWithFields { + name: "alu_branch_mop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1454), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(1455), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1456), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1457), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1458), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1459), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1460), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1461), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1462), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1463), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1464), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1465), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1466), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1467), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1468), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1469), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1470), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1471), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1472), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1473), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1474), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1475), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1476), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1477), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1478), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(1479), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + invert_src0: Bool, + /* offset = 52 */ + invert_carry_in: Bool, + /* offset = 53 */ + invert_carry_out: Bool, + /* offset = 54 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(1480), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceBundle { + name: "dest", + fields: [ + TraceUInt { + location: TraceScalarId(1481), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(1482), + name: "[0]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1483), + name: "[1]", + ty: UInt<6>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1484), + name: "[2]", + ty: UInt<6>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1485), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(1486), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(1487), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(1488), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + /* offset = 4 */ + src: Array, 3>, + /* offset = 22 */ + imm_low: UInt<25>, + /* offset = 47 */ + imm_sign: SInt<1>, + /* offset = 48 */ + _phantom: Bundle {}, + }, + /* offset = 48 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 51 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, ], }, traces: [ @@ -12942,7 +90815,7 @@ Simulation { index: StatePartIndex(0), ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, state: 0x1, @@ -12953,9 +90826,9 @@ Simulation { kind: EnumDiscriminant { index: StatePartIndex(1), ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, state: 0x0, @@ -12966,9 +90839,9 @@ Simulation { kind: EnumDiscriminant { index: StatePartIndex(2), ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), }, }, state: 0x0, @@ -12998,49 +90871,82 @@ Simulation { index: StatePartIndex(23), ty: UInt<8>, }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(8), + kind: EnumDiscriminant { + index: StatePartIndex(3), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: EnumDiscriminant { + index: StatePartIndex(4), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigUInt { + index: StatePartIndex(26), + ty: UInt<8>, + }, state: 0x02, last_state: 0x02, }, SimTrace { - id: TraceScalarId(8), + id: TraceScalarId(11), kind: BigUInt { - index: StatePartIndex(24), + index: StatePartIndex(27), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(9), + id: TraceScalarId(12), kind: BigUInt { - index: StatePartIndex(25), + index: StatePartIndex(28), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, SimTrace { - id: TraceScalarId(10), + id: TraceScalarId(13), kind: BigUInt { - index: StatePartIndex(26), + index: StatePartIndex(29), ty: UInt<25>, }, state: 0x0001234, last_state: 0x0001234, }, SimTrace { - id: TraceScalarId(11), + id: TraceScalarId(14), kind: BigSInt { - index: StatePartIndex(27), + index: StatePartIndex(30), ty: SInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(12), + id: TraceScalarId(15), kind: EnumDiscriminant { - index: StatePartIndex(3), + index: StatePartIndex(5), ty: Enum { Full64, DupLow32, @@ -13055,30 +90961,6 @@ Simulation { state: 0x0, last_state: 0x0, }, - SimTrace { - id: TraceScalarId(13), - kind: BigBool { - index: StatePartIndex(29), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(14), - kind: BigBool { - index: StatePartIndex(30), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(15), - kind: BigBool { - index: StatePartIndex(31), - }, - state: 0x1, - last_state: 0x1, - }, SimTrace { id: TraceScalarId(16), kind: BigBool { @@ -13089,6 +90971,30 @@ Simulation { }, SimTrace { id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigBool { + index: StatePartIndex(35), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), kind: BigUInt { index: StatePartIndex(21), ty: UInt<0>, @@ -13097,7 +91003,7 @@ Simulation { last_state: 0x0, }, SimTrace { - id: TraceScalarId(18), + id: TraceScalarId(21), kind: BigUInt { index: StatePartIndex(22), ty: UInt<8>, @@ -13106,63 +91012,33 @@ Simulation { last_state: 0x01, }, SimTrace { - id: TraceScalarId(19), + id: TraceScalarId(22), kind: BigUInt { index: StatePartIndex(23), ty: UInt<8>, }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(20), - kind: BigUInt { - index: StatePartIndex(24), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(21), - kind: BigUInt { - index: StatePartIndex(25), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, - SimTrace { - id: TraceScalarId(22), - kind: BigUInt { - index: StatePartIndex(26), - ty: UInt<25>, - }, - state: 0x0001234, - last_state: 0x0001234, + state: 0x00, + last_state: 0x00, }, SimTrace { id: TraceScalarId(23), - kind: BigSInt { - index: StatePartIndex(27), - ty: SInt<1>, + kind: EnumDiscriminant { + index: StatePartIndex(3), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, - state: 0x0, - last_state: 0x0, + state: 0x1, + last_state: 0x1, }, SimTrace { id: TraceScalarId(24), kind: EnumDiscriminant { - index: StatePartIndex(3), + index: StatePartIndex(4), ty: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, + HdlNone, + HdlSome(Bundle {}), }, }, state: 0x0, @@ -13170,103 +91046,53 @@ Simulation { }, SimTrace { id: TraceScalarId(25), - kind: BigBool { - index: StatePartIndex(29), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(26), - kind: BigBool { - index: StatePartIndex(30), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(27), - kind: BigBool { - index: StatePartIndex(31), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(28), - kind: BigBool { - index: StatePartIndex(32), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(29), kind: BigUInt { - index: StatePartIndex(74), - ty: UInt<0>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(30), - kind: BigUInt { - index: StatePartIndex(75), - ty: UInt<8>, - }, - state: 0x01, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(31), - kind: BigUInt { - index: StatePartIndex(76), + index: StatePartIndex(26), ty: UInt<8>, }, state: 0x02, last_state: 0x02, }, SimTrace { - id: TraceScalarId(32), + id: TraceScalarId(26), kind: BigUInt { - index: StatePartIndex(77), + index: StatePartIndex(27), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(33), + id: TraceScalarId(27), kind: BigUInt { - index: StatePartIndex(78), + index: StatePartIndex(28), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, SimTrace { - id: TraceScalarId(34), + id: TraceScalarId(28), kind: BigUInt { - index: StatePartIndex(79), + index: StatePartIndex(29), ty: UInt<25>, }, state: 0x0001234, last_state: 0x0001234, }, SimTrace { - id: TraceScalarId(35), + id: TraceScalarId(29), kind: BigSInt { - index: StatePartIndex(80), + index: StatePartIndex(30), ty: SInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(36), + id: TraceScalarId(30), kind: EnumDiscriminant { - index: StatePartIndex(4), + index: StatePartIndex(5), ty: Enum { Full64, DupLow32, @@ -13282,31 +91108,84 @@ Simulation { last_state: 0x0, }, SimTrace { - id: TraceScalarId(37), - kind: BigUInt { - index: StatePartIndex(82), - ty: UInt<4>, + id: TraceScalarId(31), + kind: BigBool { + index: StatePartIndex(32), }, - state: 0xf, - last_state: 0xf, + state: 0x1, + last_state: 0x1, }, SimTrace { - id: TraceScalarId(38), - kind: EnumDiscriminant { - index: StatePartIndex(5), - ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - }, + id: TraceScalarId(32), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(33), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(34), + kind: BigBool { + index: StatePartIndex(35), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(35), + kind: BigUInt { + index: StatePartIndex(103), + ty: UInt<0>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(39), + id: TraceScalarId(36), kind: BigUInt { - index: StatePartIndex(86), - ty: UInt<1>, + index: StatePartIndex(104), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(37), + kind: BigUInt { + index: StatePartIndex(105), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(38), + kind: EnumDiscriminant { + index: StatePartIndex(6), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(39), + kind: EnumDiscriminant { + index: StatePartIndex(7), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, state: 0x0, last_state: 0x0, @@ -13314,217 +91193,238 @@ Simulation { SimTrace { id: TraceScalarId(40), kind: BigUInt { - index: StatePartIndex(87), - ty: UInt<8>, - }, - state: 0x01, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(41), - kind: BigUInt { - index: StatePartIndex(88), + index: StatePartIndex(108), ty: UInt<8>, }, state: 0x02, last_state: 0x02, }, SimTrace { - id: TraceScalarId(42), + id: TraceScalarId(41), kind: BigUInt { - index: StatePartIndex(89), + index: StatePartIndex(109), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(43), + id: TraceScalarId(42), kind: BigUInt { - index: StatePartIndex(90), + index: StatePartIndex(110), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, SimTrace { - id: TraceScalarId(44), + id: TraceScalarId(43), kind: BigUInt { - index: StatePartIndex(91), + index: StatePartIndex(111), ty: UInt<25>, }, state: 0x0001234, last_state: 0x0001234, }, SimTrace { - id: TraceScalarId(45), + id: TraceScalarId(44), kind: BigSInt { - index: StatePartIndex(92), + index: StatePartIndex(112), ty: SInt<1>, }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(45), + kind: EnumDiscriminant { + index: StatePartIndex(8), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, SimTrace { id: TraceScalarId(46), kind: BigUInt { - index: StatePartIndex(86), - ty: UInt<1>, + index: StatePartIndex(114), + ty: UInt<4>, }, - state: 0x0, - last_state: 0x0, + state: 0xf, + last_state: 0xf, }, SimTrace { id: TraceScalarId(47), - kind: BigUInt { - index: StatePartIndex(87), - ty: UInt<8>, - }, - state: 0x01, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(48), - kind: BigUInt { - index: StatePartIndex(88), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(49), - kind: BigUInt { - index: StatePartIndex(89), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(50), - kind: BigUInt { - index: StatePartIndex(90), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, - SimTrace { - id: TraceScalarId(51), - kind: BigUInt { - index: StatePartIndex(91), - ty: UInt<25>, - }, - state: 0x0001234, - last_state: 0x0001234, - }, - SimTrace { - id: TraceScalarId(52), - kind: BigSInt { - index: StatePartIndex(92), - ty: SInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(53), kind: EnumDiscriminant { - index: StatePartIndex(6), + index: StatePartIndex(9), ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), }, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(54), + id: TraceScalarId(48), kind: BigUInt { - index: StatePartIndex(116), + index: StatePartIndex(118), ty: UInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(55), + id: TraceScalarId(49), kind: BigUInt { - index: StatePartIndex(117), + index: StatePartIndex(119), ty: UInt<8>, }, state: 0x01, last_state: 0x01, }, SimTrace { - id: TraceScalarId(56), + id: TraceScalarId(50), kind: BigUInt { - index: StatePartIndex(118), + index: StatePartIndex(120), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(51), + kind: EnumDiscriminant { + index: StatePartIndex(10), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(52), + kind: EnumDiscriminant { + index: StatePartIndex(11), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(53), + kind: BigUInt { + index: StatePartIndex(123), ty: UInt<8>, }, state: 0x02, last_state: 0x02, }, SimTrace { - id: TraceScalarId(57), + id: TraceScalarId(54), kind: BigUInt { - index: StatePartIndex(119), + index: StatePartIndex(124), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(58), + id: TraceScalarId(55), kind: BigUInt { - index: StatePartIndex(120), + index: StatePartIndex(125), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, SimTrace { - id: TraceScalarId(59), + id: TraceScalarId(56), kind: BigUInt { - index: StatePartIndex(121), + index: StatePartIndex(126), ty: UInt<25>, }, state: 0x0001234, last_state: 0x0001234, }, SimTrace { - id: TraceScalarId(60), + id: TraceScalarId(57), kind: BigSInt { - index: StatePartIndex(122), + index: StatePartIndex(127), ty: SInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(61), + id: TraceScalarId(58), kind: BigUInt { - index: StatePartIndex(116), + index: StatePartIndex(118), ty: UInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(62), + id: TraceScalarId(59), kind: BigUInt { - index: StatePartIndex(117), + index: StatePartIndex(119), ty: UInt<8>, }, state: 0x01, last_state: 0x01, }, + SimTrace { + id: TraceScalarId(60), + kind: BigUInt { + index: StatePartIndex(120), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(61), + kind: EnumDiscriminant { + index: StatePartIndex(10), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(62), + kind: EnumDiscriminant { + index: StatePartIndex(11), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, SimTrace { id: TraceScalarId(63), kind: BigUInt { - index: StatePartIndex(118), + index: StatePartIndex(123), ty: UInt<8>, }, state: 0x02, @@ -13533,7 +91433,7 @@ Simulation { SimTrace { id: TraceScalarId(64), kind: BigUInt { - index: StatePartIndex(119), + index: StatePartIndex(124), ty: UInt<8>, }, state: 0x03, @@ -13542,7 +91442,7 @@ Simulation { SimTrace { id: TraceScalarId(65), kind: BigUInt { - index: StatePartIndex(120), + index: StatePartIndex(125), ty: UInt<8>, }, state: 0x04, @@ -13551,7 +91451,7 @@ Simulation { SimTrace { id: TraceScalarId(66), kind: BigUInt { - index: StatePartIndex(121), + index: StatePartIndex(126), ty: UInt<25>, }, state: 0x0001234, @@ -13560,7 +91460,7 @@ Simulation { SimTrace { id: TraceScalarId(67), kind: BigSInt { - index: StatePartIndex(122), + index: StatePartIndex(127), ty: SInt<1>, }, state: 0x0, @@ -13568,6 +91468,210 @@ Simulation { }, SimTrace { id: TraceScalarId(68), + kind: EnumDiscriminant { + index: StatePartIndex(12), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(69), + kind: BigUInt { + index: StatePartIndex(174), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(70), + kind: BigUInt { + index: StatePartIndex(175), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(71), + kind: BigUInt { + index: StatePartIndex(176), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(72), + kind: EnumDiscriminant { + index: StatePartIndex(13), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(73), + kind: EnumDiscriminant { + index: StatePartIndex(14), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(74), + kind: BigUInt { + index: StatePartIndex(179), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(75), + kind: BigUInt { + index: StatePartIndex(180), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(76), + kind: BigUInt { + index: StatePartIndex(181), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(77), + kind: BigUInt { + index: StatePartIndex(182), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(78), + kind: BigSInt { + index: StatePartIndex(183), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(79), + kind: BigUInt { + index: StatePartIndex(174), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(80), + kind: BigUInt { + index: StatePartIndex(175), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(81), + kind: BigUInt { + index: StatePartIndex(176), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(82), + kind: EnumDiscriminant { + index: StatePartIndex(13), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(83), + kind: EnumDiscriminant { + index: StatePartIndex(14), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(84), + kind: BigUInt { + index: StatePartIndex(179), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(85), + kind: BigUInt { + index: StatePartIndex(180), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(86), + kind: BigUInt { + index: StatePartIndex(181), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(87), + kind: BigUInt { + index: StatePartIndex(182), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(88), + kind: BigSInt { + index: StatePartIndex(183), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(89), kind: BigBool { index: StatePartIndex(9), }, @@ -13575,7 +91679,7 @@ Simulation { last_state: 0x1, }, SimTrace { - id: TraceScalarId(69), + id: TraceScalarId(90), kind: BigUInt { index: StatePartIndex(10), ty: UInt<64>, @@ -13584,7 +91688,7 @@ Simulation { last_state: 0x0000000000001000, }, SimTrace { - id: TraceScalarId(70), + id: TraceScalarId(91), kind: BigBool { index: StatePartIndex(3), }, @@ -13592,232 +91696,25 @@ Simulation { last_state: 0x1, }, SimTrace { - id: TraceScalarId(71), + id: TraceScalarId(92), kind: EnumDiscriminant { - index: StatePartIndex(7), + index: StatePartIndex(15), ty: Enum { HdlNone, - HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + HdlSome(Bundle {mop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), }, }, state: 0x1, last_state: 0x1, }, - SimTrace { - id: TraceScalarId(72), - kind: EnumDiscriminant { - index: StatePartIndex(8), - ty: Enum { - AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), - L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), - LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(73), - kind: EnumDiscriminant { - index: StatePartIndex(9), - ty: Enum { - AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), - Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), - }, - }, - state: 0x2, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(74), - kind: BigUInt { - index: StatePartIndex(150), - ty: UInt<0>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(75), - kind: BigUInt { - index: StatePartIndex(151), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(76), - kind: BigUInt { - index: StatePartIndex(152), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(77), - kind: BigUInt { - index: StatePartIndex(153), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, - SimTrace { - id: TraceScalarId(78), - kind: BigUInt { - index: StatePartIndex(154), - ty: UInt<8>, - }, - state: 0x00, - last_state: 0x00, - }, - SimTrace { - id: TraceScalarId(79), - kind: BigUInt { - index: StatePartIndex(155), - ty: UInt<25>, - }, - state: 0x0000000, - last_state: 0x0000000, - }, - SimTrace { - id: TraceScalarId(80), - kind: BigSInt { - index: StatePartIndex(156), - ty: SInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(81), - kind: EnumDiscriminant { - index: StatePartIndex(10), - ty: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(82), - kind: BigBool { - index: StatePartIndex(158), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(83), - kind: BigBool { - index: StatePartIndex(159), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(84), - kind: BigBool { - index: StatePartIndex(160), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(85), - kind: BigBool { - index: StatePartIndex(161), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(86), - kind: BigUInt { - index: StatePartIndex(150), - ty: UInt<0>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(87), - kind: BigUInt { - index: StatePartIndex(151), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(88), - kind: BigUInt { - index: StatePartIndex(152), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(89), - kind: BigUInt { - index: StatePartIndex(153), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, - SimTrace { - id: TraceScalarId(90), - kind: BigUInt { - index: StatePartIndex(154), - ty: UInt<8>, - }, - state: 0x00, - last_state: 0x00, - }, - SimTrace { - id: TraceScalarId(91), - kind: BigUInt { - index: StatePartIndex(155), - ty: UInt<25>, - }, - state: 0x0000000, - last_state: 0x0000000, - }, - SimTrace { - id: TraceScalarId(92), - kind: BigSInt { - index: StatePartIndex(156), - ty: SInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, SimTrace { id: TraceScalarId(93), kind: EnumDiscriminant { - index: StatePartIndex(10), + index: StatePartIndex(16), ty: Enum { - Full64, - DupLow32, - ZeroExt32, - SignExt32, - ZeroExt16, - SignExt16, - ZeroExt8, - SignExt8, + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), }, }, state: 0x0, @@ -13825,58 +91722,72 @@ Simulation { }, SimTrace { id: TraceScalarId(94), - kind: BigBool { - index: StatePartIndex(158), + kind: EnumDiscriminant { + index: StatePartIndex(17), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, }, - state: 0x0, - last_state: 0x0, + state: 0x2, + last_state: 0x2, }, SimTrace { id: TraceScalarId(95), - kind: BigBool { - index: StatePartIndex(159), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(96), - kind: BigBool { - index: StatePartIndex(160), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(97), - kind: BigBool { - index: StatePartIndex(161), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(98), kind: BigUInt { - index: StatePartIndex(203), + index: StatePartIndex(231), ty: UInt<0>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(99), + id: TraceScalarId(96), kind: BigUInt { - index: StatePartIndex(204), + index: StatePartIndex(232), ty: UInt<8>, }, state: 0x02, last_state: 0x02, }, + SimTrace { + id: TraceScalarId(97), + kind: BigUInt { + index: StatePartIndex(233), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(98), + kind: EnumDiscriminant { + index: StatePartIndex(18), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(99), + kind: EnumDiscriminant { + index: StatePartIndex(19), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(100), kind: BigUInt { - index: StatePartIndex(205), + index: StatePartIndex(236), ty: UInt<8>, }, state: 0x03, @@ -13885,7 +91796,7 @@ Simulation { SimTrace { id: TraceScalarId(101), kind: BigUInt { - index: StatePartIndex(206), + index: StatePartIndex(237), ty: UInt<8>, }, state: 0x04, @@ -13894,7 +91805,7 @@ Simulation { SimTrace { id: TraceScalarId(102), kind: BigUInt { - index: StatePartIndex(207), + index: StatePartIndex(238), ty: UInt<8>, }, state: 0x00, @@ -13903,7 +91814,7 @@ Simulation { SimTrace { id: TraceScalarId(103), kind: BigUInt { - index: StatePartIndex(208), + index: StatePartIndex(239), ty: UInt<25>, }, state: 0x0000000, @@ -13912,7 +91823,7 @@ Simulation { SimTrace { id: TraceScalarId(104), kind: BigSInt { - index: StatePartIndex(209), + index: StatePartIndex(240), ty: SInt<1>, }, state: 0x0, @@ -13921,7 +91832,7 @@ Simulation { SimTrace { id: TraceScalarId(105), kind: EnumDiscriminant { - index: StatePartIndex(11), + index: StatePartIndex(20), ty: Enum { Full64, DupLow32, @@ -13938,65 +91849,58 @@ Simulation { }, SimTrace { id: TraceScalarId(106), - kind: BigUInt { - index: StatePartIndex(211), - ty: UInt<4>, - }, - state: 0x6, - last_state: 0x6, - }, - SimTrace { - id: TraceScalarId(107), - kind: EnumDiscriminant { - index: StatePartIndex(12), - ty: Enum { - ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), - }, + kind: BigBool { + index: StatePartIndex(242), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(107), + kind: BigBool { + index: StatePartIndex(243), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(108), - kind: BigUInt { - index: StatePartIndex(215), - ty: UInt<1>, + kind: BigBool { + index: StatePartIndex(244), }, state: 0x1, last_state: 0x1, }, SimTrace { id: TraceScalarId(109), + kind: BigBool { + index: StatePartIndex(245), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(110), kind: BigUInt { - index: StatePartIndex(216), + index: StatePartIndex(231), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(111), + kind: BigUInt { + index: StatePartIndex(232), ty: UInt<8>, }, state: 0x02, last_state: 0x02, }, - SimTrace { - id: TraceScalarId(110), - kind: BigUInt { - index: StatePartIndex(217), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(111), - kind: BigUInt { - index: StatePartIndex(218), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, SimTrace { id: TraceScalarId(112), kind: BigUInt { - index: StatePartIndex(219), + index: StatePartIndex(233), ty: UInt<8>, }, state: 0x00, @@ -14004,137 +91908,145 @@ Simulation { }, SimTrace { id: TraceScalarId(113), - kind: BigUInt { - index: StatePartIndex(220), - ty: UInt<25>, - }, - state: 0x0000000, - last_state: 0x0000000, - }, - SimTrace { - id: TraceScalarId(114), - kind: BigSInt { - index: StatePartIndex(221), - ty: SInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(115), - kind: BigUInt { - index: StatePartIndex(215), - ty: UInt<1>, - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(116), - kind: BigUInt { - index: StatePartIndex(216), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(117), - kind: BigUInt { - index: StatePartIndex(217), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - SimTrace { - id: TraceScalarId(118), - kind: BigUInt { - index: StatePartIndex(218), - ty: UInt<8>, - }, - state: 0x04, - last_state: 0x04, - }, - SimTrace { - id: TraceScalarId(119), - kind: BigUInt { - index: StatePartIndex(219), - ty: UInt<8>, - }, - state: 0x00, - last_state: 0x00, - }, - SimTrace { - id: TraceScalarId(120), - kind: BigUInt { - index: StatePartIndex(220), - ty: UInt<25>, - }, - state: 0x0000000, - last_state: 0x0000000, - }, - SimTrace { - id: TraceScalarId(121), - kind: BigSInt { - index: StatePartIndex(221), - ty: SInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(122), kind: EnumDiscriminant { - index: StatePartIndex(13), + index: StatePartIndex(18), ty: Enum { - Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), - Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + HdlNone, + HdlSome(Bundle {}), }, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(123), - kind: BigUInt { - index: StatePartIndex(245), - ty: UInt<1>, + id: TraceScalarId(114), + kind: EnumDiscriminant { + index: StatePartIndex(19), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, state: 0x1, last_state: 0x1, }, SimTrace { - id: TraceScalarId(124), + id: TraceScalarId(115), kind: BigUInt { - index: StatePartIndex(246), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(125), - kind: BigUInt { - index: StatePartIndex(247), + index: StatePartIndex(236), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(126), + id: TraceScalarId(116), kind: BigUInt { - index: StatePartIndex(248), + index: StatePartIndex(237), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, + SimTrace { + id: TraceScalarId(117), + kind: BigUInt { + index: StatePartIndex(238), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(118), + kind: BigUInt { + index: StatePartIndex(239), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(119), + kind: BigSInt { + index: StatePartIndex(240), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(120), + kind: EnumDiscriminant { + index: StatePartIndex(20), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(121), + kind: BigBool { + index: StatePartIndex(242), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(122), + kind: BigBool { + index: StatePartIndex(243), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(123), + kind: BigBool { + index: StatePartIndex(244), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(124), + kind: BigBool { + index: StatePartIndex(245), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(125), + kind: BigUInt { + index: StatePartIndex(313), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(126), + kind: BigUInt { + index: StatePartIndex(314), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, SimTrace { id: TraceScalarId(127), kind: BigUInt { - index: StatePartIndex(249), + index: StatePartIndex(315), ty: UInt<8>, }, state: 0x00, @@ -14142,89 +92054,108 @@ Simulation { }, SimTrace { id: TraceScalarId(128), - kind: BigUInt { - index: StatePartIndex(250), - ty: UInt<25>, - }, - state: 0x0000000, - last_state: 0x0000000, - }, - SimTrace { - id: TraceScalarId(129), - kind: BigSInt { - index: StatePartIndex(251), - ty: SInt<1>, + kind: EnumDiscriminant { + index: StatePartIndex(21), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(130), - kind: BigUInt { - index: StatePartIndex(245), - ty: UInt<1>, + id: TraceScalarId(129), + kind: EnumDiscriminant { + index: StatePartIndex(22), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, }, state: 0x1, last_state: 0x1, }, SimTrace { - id: TraceScalarId(131), + id: TraceScalarId(130), kind: BigUInt { - index: StatePartIndex(246), - ty: UInt<8>, - }, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(132), - kind: BigUInt { - index: StatePartIndex(247), + index: StatePartIndex(318), ty: UInt<8>, }, state: 0x03, last_state: 0x03, }, SimTrace { - id: TraceScalarId(133), + id: TraceScalarId(131), kind: BigUInt { - index: StatePartIndex(248), + index: StatePartIndex(319), ty: UInt<8>, }, state: 0x04, last_state: 0x04, }, SimTrace { - id: TraceScalarId(134), + id: TraceScalarId(132), kind: BigUInt { - index: StatePartIndex(249), + index: StatePartIndex(320), ty: UInt<8>, }, state: 0x00, last_state: 0x00, }, SimTrace { - id: TraceScalarId(135), + id: TraceScalarId(133), kind: BigUInt { - index: StatePartIndex(250), + index: StatePartIndex(321), ty: UInt<25>, }, state: 0x0000000, last_state: 0x0000000, }, SimTrace { - id: TraceScalarId(136), + id: TraceScalarId(134), kind: BigSInt { - index: StatePartIndex(251), + index: StatePartIndex(322), ty: SInt<1>, }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(135), + kind: EnumDiscriminant { + index: StatePartIndex(23), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(136), + kind: BigUInt { + index: StatePartIndex(324), + ty: UInt<4>, + }, + state: 0x6, + last_state: 0x6, + }, SimTrace { id: TraceScalarId(137), - kind: BigBool { - index: StatePartIndex(138), + kind: EnumDiscriminant { + index: StatePartIndex(24), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, }, state: 0x0, last_state: 0x0, @@ -14232,14 +92163,418 @@ Simulation { SimTrace { id: TraceScalarId(138), kind: BigUInt { - index: StatePartIndex(139), + index: StatePartIndex(328), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(139), + kind: BigUInt { + index: StatePartIndex(329), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(140), + kind: BigUInt { + index: StatePartIndex(330), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(141), + kind: EnumDiscriminant { + index: StatePartIndex(25), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(142), + kind: EnumDiscriminant { + index: StatePartIndex(26), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(143), + kind: BigUInt { + index: StatePartIndex(333), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(144), + kind: BigUInt { + index: StatePartIndex(334), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(145), + kind: BigUInt { + index: StatePartIndex(335), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(146), + kind: BigUInt { + index: StatePartIndex(336), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(147), + kind: BigSInt { + index: StatePartIndex(337), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(148), + kind: BigUInt { + index: StatePartIndex(328), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(149), + kind: BigUInt { + index: StatePartIndex(329), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(150), + kind: BigUInt { + index: StatePartIndex(330), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(151), + kind: EnumDiscriminant { + index: StatePartIndex(25), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(152), + kind: EnumDiscriminant { + index: StatePartIndex(26), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(153), + kind: BigUInt { + index: StatePartIndex(333), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(154), + kind: BigUInt { + index: StatePartIndex(334), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(155), + kind: BigUInt { + index: StatePartIndex(335), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(156), + kind: BigUInt { + index: StatePartIndex(336), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(157), + kind: BigSInt { + index: StatePartIndex(337), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(158), + kind: EnumDiscriminant { + index: StatePartIndex(27), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {normal_regs: Array}, 2>, flag_regs: Array}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(159), + kind: BigUInt { + index: StatePartIndex(384), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(160), + kind: BigUInt { + index: StatePartIndex(385), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(161), + kind: BigUInt { + index: StatePartIndex(386), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(162), + kind: EnumDiscriminant { + index: StatePartIndex(28), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(163), + kind: EnumDiscriminant { + index: StatePartIndex(29), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(164), + kind: BigUInt { + index: StatePartIndex(389), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(165), + kind: BigUInt { + index: StatePartIndex(390), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(166), + kind: BigUInt { + index: StatePartIndex(391), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(167), + kind: BigUInt { + index: StatePartIndex(392), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(168), + kind: BigSInt { + index: StatePartIndex(393), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(169), + kind: BigUInt { + index: StatePartIndex(384), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(170), + kind: BigUInt { + index: StatePartIndex(385), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(171), + kind: BigUInt { + index: StatePartIndex(386), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(172), + kind: EnumDiscriminant { + index: StatePartIndex(28), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(173), + kind: EnumDiscriminant { + index: StatePartIndex(29), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(174), + kind: BigUInt { + index: StatePartIndex(389), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(175), + kind: BigUInt { + index: StatePartIndex(390), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(176), + kind: BigUInt { + index: StatePartIndex(391), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(177), + kind: BigUInt { + index: StatePartIndex(392), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(178), + kind: BigSInt { + index: StatePartIndex(393), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(179), + kind: BigBool { + index: StatePartIndex(219), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(180), + kind: BigUInt { + index: StatePartIndex(220), ty: UInt<64>, }, state: 0x0000000000001004, last_state: 0x0000000000001004, }, SimTrace { - id: TraceScalarId(139), + id: TraceScalarId(181), kind: BigBool { index: StatePartIndex(5), }, @@ -14247,9 +92582,9 @@ Simulation { last_state: 0x1, }, SimTrace { - id: TraceScalarId(140), + id: TraceScalarId(182), kind: EnumDiscriminant { - index: StatePartIndex(14), + index: StatePartIndex(30), ty: Enum { HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), @@ -14259,9 +92594,9 @@ Simulation { last_state: 0x0, }, SimTrace { - id: TraceScalarId(141), + id: TraceScalarId(183), kind: EnumDiscriminant { - index: StatePartIndex(15), + index: StatePartIndex(31), ty: Enum { Trap(Bundle {}), ICacheFlush, @@ -14271,424 +92606,43 @@ Simulation { last_state: 0x0, }, SimTrace { - id: TraceScalarId(142), + id: TraceScalarId(184), kind: BigBool { index: StatePartIndex(7), }, state: 0x1, last_state: 0x1, }, - SimTrace { - id: TraceScalarId(143), - kind: BigBool { - index: StatePartIndex(271), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(144), - kind: BigBool { - index: StatePartIndex(272), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(145), - kind: EnumDiscriminant { - index: StatePartIndex(16), - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(146), - kind: BigUInt { - index: StatePartIndex(275), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(147), - kind: EnumDiscriminant { - index: StatePartIndex(17), - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(148), - kind: BigUInt { - index: StatePartIndex(279), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(149), - kind: EnumDiscriminant { - index: StatePartIndex(18), - ty: Enum { - AluBranch, - L2RegisterFile, - LoadStore, - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(150), - kind: BigBool { - index: StatePartIndex(292), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(151), - kind: EnumDiscriminant { - index: StatePartIndex(19), - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(152), - kind: BigUInt { - index: StatePartIndex(294), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(153), - kind: BigUInt { - index: StatePartIndex(299), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(154), - kind: EnumDiscriminant { - index: StatePartIndex(20), - ty: Enum { - AluBranch, - L2RegisterFile, - LoadStore, - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(155), - kind: BigBool { - index: StatePartIndex(310), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(156), - kind: EnumDiscriminant { - index: StatePartIndex(21), - ty: Enum { - HdlNone, - HdlSome(Bundle {value: UInt<1>}), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(157), - kind: BigUInt { - index: StatePartIndex(312), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(158), - kind: BigUInt { - index: StatePartIndex(316), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(159), - kind: BigClock { - index: StatePartIndex(325), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(160), - kind: BigSyncReset { - index: StatePartIndex(326), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(161), - kind: BigClock { - index: StatePartIndex(323), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(162), - kind: BigSyncReset { - index: StatePartIndex(324), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(163), - kind: BigClock { - index: StatePartIndex(333), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(164), - kind: BigSyncReset { - index: StatePartIndex(334), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(165), - kind: EnumDiscriminant { - index: StatePartIndex(23), - ty: Enum { - HdlNone, - HdlSome(UInt<4>), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(166), - kind: BigUInt { - index: StatePartIndex(338), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(167), - kind: BigBool { - index: StatePartIndex(336), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(168), - kind: EnumDiscriminant { - index: StatePartIndex(24), - ty: Enum { - HdlNone, - HdlSome(UInt<4>), - }, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(169), - kind: BigUInt { - index: StatePartIndex(342), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(170), - kind: BigBool { - index: StatePartIndex(340), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(171), - kind: BigBool { - index: StatePartIndex(343), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(172), - kind: BigBool { - index: StatePartIndex(344), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(173), - kind: BigBool { - index: StatePartIndex(345), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(174), - kind: BigBool { - index: StatePartIndex(346), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(175), - kind: BigBool { - index: StatePartIndex(347), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(176), - kind: BigBool { - index: StatePartIndex(348), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(177), - kind: BigBool { - index: StatePartIndex(349), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(178), - kind: BigBool { - index: StatePartIndex(350), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(179), - kind: BigBool { - index: StatePartIndex(351), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(180), - kind: BigBool { - index: StatePartIndex(352), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(181), - kind: BigBool { - index: StatePartIndex(353), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(182), - kind: BigBool { - index: StatePartIndex(354), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(183), - kind: BigBool { - index: StatePartIndex(355), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(184), - kind: BigBool { - index: StatePartIndex(356), - }, - state: 0x1, - last_state: 0x1, - }, SimTrace { id: TraceScalarId(185), - kind: BigBool { - index: StatePartIndex(357), + kind: BigUInt { + index: StatePartIndex(431), + ty: UInt<8>, }, - state: 0x1, - last_state: 0x1, + state: 0x00, + last_state: 0x00, }, SimTrace { id: TraceScalarId(186), kind: BigBool { - index: StatePartIndex(358), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(187), - kind: EnumDiscriminant { - index: StatePartIndex(29), - ty: Enum { - HdlNone, - HdlSome(UInt<4>), - }, + index: StatePartIndex(432), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(187), + kind: BigClock { + index: StatePartIndex(433), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(188), kind: BigUInt { - index: StatePartIndex(393), - ty: UInt<4>, + index: StatePartIndex(434), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, @@ -14696,94 +92650,94 @@ Simulation { SimTrace { id: TraceScalarId(189), kind: BigUInt { - index: StatePartIndex(396), - ty: UInt<1>, + index: StatePartIndex(435), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(190), + kind: BigUInt { + index: StatePartIndex(436), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(191), kind: BigBool { - index: StatePartIndex(405), + index: StatePartIndex(437), }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(191), - kind: BigUInt { - index: StatePartIndex(409), - ty: UInt<1>, + id: TraceScalarId(192), + kind: BigClock { + index: StatePartIndex(438), }, state: 0x1, last_state: 0x1, }, - SimTrace { - id: TraceScalarId(192), - kind: BigUInt { - index: StatePartIndex(420), - ty: UInt<1>, - }, - state: 0x0, - last_state: 0x0, - }, SimTrace { id: TraceScalarId(193), - kind: BigBool { - index: StatePartIndex(429), + kind: BigUInt { + index: StatePartIndex(439), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(194), - kind: BigUInt { - index: StatePartIndex(433), - ty: UInt<1>, - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(195), kind: BigUInt { index: StatePartIndex(440), - ty: UInt<1>, + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(195), + kind: BigUInt { + index: StatePartIndex(441), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, SimTrace { id: TraceScalarId(196), kind: BigBool { - index: StatePartIndex(443), + index: StatePartIndex(442), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(197), - kind: BigUInt { - index: StatePartIndex(447), - ty: UInt<2>, + kind: BigClock { + index: StatePartIndex(443), }, - state: 0x3, - last_state: 0x3, + state: 0x1, + last_state: 0x1, }, SimTrace { id: TraceScalarId(198), kind: BigUInt { - index: StatePartIndex(456), - ty: UInt<1>, + index: StatePartIndex(444), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(199), - kind: BigBool { - index: StatePartIndex(465), + kind: BigUInt { + index: StatePartIndex(445), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, @@ -14791,77 +92745,76 @@ Simulation { SimTrace { id: TraceScalarId(200), kind: BigUInt { - index: StatePartIndex(469), - ty: UInt<1>, + index: StatePartIndex(446), + ty: UInt<8>, }, - state: 0x1, - last_state: 0x1, + state: 0x00, + last_state: 0x00, }, SimTrace { id: TraceScalarId(201), - kind: BigUInt { - index: StatePartIndex(476), - ty: UInt<1>, + kind: BigBool { + index: StatePartIndex(447), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(202), - kind: BigBool { - index: StatePartIndex(485), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(203), - kind: BigUInt { - index: StatePartIndex(489), - ty: UInt<1>, + kind: BigClock { + index: StatePartIndex(448), }, state: 0x1, last_state: 0x1, }, + SimTrace { + id: TraceScalarId(203), + kind: BigUInt { + index: StatePartIndex(449), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, SimTrace { id: TraceScalarId(204), kind: BigUInt { - index: StatePartIndex(496), - ty: UInt<1>, + index: StatePartIndex(450), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(205), - kind: BigBool { - index: StatePartIndex(499), + kind: BigUInt { + index: StatePartIndex(451), + ty: UInt<8>, }, - state: 0x0, - last_state: 0x0, + state: 0x00, + last_state: 0x00, }, SimTrace { id: TraceScalarId(206), - kind: BigUInt { - index: StatePartIndex(503), - ty: UInt<2>, - }, - state: 0x3, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(207), - kind: BigUInt { - index: StatePartIndex(511), - ty: UInt<1>, + kind: BigBool { + index: StatePartIndex(452), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(207), + kind: BigClock { + index: StatePartIndex(453), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(208), - kind: BigBool { - index: StatePartIndex(514), + kind: BigUInt { + index: StatePartIndex(454), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, @@ -14869,34 +92822,33 @@ Simulation { SimTrace { id: TraceScalarId(209), kind: BigUInt { - index: StatePartIndex(518), - ty: UInt<3>, - }, - state: 0x7, - last_state: 0x7, - }, - SimTrace { - id: TraceScalarId(210), - kind: BigUInt { - index: StatePartIndex(527), - ty: UInt<1>, + index: StatePartIndex(455), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(210), + kind: BigUInt { + index: StatePartIndex(456), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, SimTrace { id: TraceScalarId(211), kind: BigBool { - index: StatePartIndex(536), + index: StatePartIndex(457), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(212), - kind: BigUInt { - index: StatePartIndex(540), - ty: UInt<1>, + kind: BigClock { + index: StatePartIndex(458), }, state: 0x1, last_state: 0x1, @@ -14904,16 +92856,17 @@ Simulation { SimTrace { id: TraceScalarId(213), kind: BigUInt { - index: StatePartIndex(547), - ty: UInt<1>, + index: StatePartIndex(459), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(214), - kind: BigBool { - index: StatePartIndex(556), + kind: BigUInt { + index: StatePartIndex(460), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, @@ -14921,77 +92874,76 @@ Simulation { SimTrace { id: TraceScalarId(215), kind: BigUInt { - index: StatePartIndex(560), + index: StatePartIndex(461), ty: UInt<1>, }, - state: 0x1, - last_state: 0x1, + state: 0x0, + last_state: 0x0, }, SimTrace { id: TraceScalarId(216), - kind: BigUInt { - index: StatePartIndex(567), - ty: UInt<1>, + kind: BigBool { + index: StatePartIndex(462), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(217), - kind: BigBool { - index: StatePartIndex(570), + kind: BigClock { + index: StatePartIndex(463), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(218), + kind: BigUInt { + index: StatePartIndex(464), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, - SimTrace { - id: TraceScalarId(218), - kind: BigUInt { - index: StatePartIndex(574), - ty: UInt<2>, - }, - state: 0x3, - last_state: 0x3, - }, SimTrace { id: TraceScalarId(219), kind: BigUInt { - index: StatePartIndex(582), - ty: UInt<1>, + index: StatePartIndex(465), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(220), - kind: BigBool { - index: StatePartIndex(591), + kind: BigUInt { + index: StatePartIndex(466), + ty: UInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(221), - kind: BigUInt { - index: StatePartIndex(595), - ty: UInt<1>, - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(222), - kind: BigUInt { - index: StatePartIndex(602), - ty: UInt<1>, + kind: BigBool { + index: StatePartIndex(467), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(222), + kind: BigClock { + index: StatePartIndex(468), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(223), - kind: BigBool { - index: StatePartIndex(611), + kind: BigUInt { + index: StatePartIndex(469), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, @@ -14999,16 +92951,16 @@ Simulation { SimTrace { id: TraceScalarId(224), kind: BigUInt { - index: StatePartIndex(615), - ty: UInt<1>, + index: StatePartIndex(470), + ty: UInt<4>, }, - state: 0x1, - last_state: 0x1, + state: 0x0, + last_state: 0x0, }, SimTrace { id: TraceScalarId(225), kind: BigUInt { - index: StatePartIndex(622), + index: StatePartIndex(471), ty: UInt<1>, }, state: 0x0, @@ -15017,33 +92969,33 @@ Simulation { SimTrace { id: TraceScalarId(226), kind: BigBool { - index: StatePartIndex(625), + index: StatePartIndex(472), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(227), - kind: BigUInt { - index: StatePartIndex(629), - ty: UInt<2>, + kind: BigClock { + index: StatePartIndex(473), }, - state: 0x3, - last_state: 0x3, + state: 0x1, + last_state: 0x1, }, SimTrace { id: TraceScalarId(228), kind: BigUInt { - index: StatePartIndex(637), - ty: UInt<1>, + index: StatePartIndex(474), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(229), - kind: BigBool { - index: StatePartIndex(640), + kind: BigUInt { + index: StatePartIndex(475), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, @@ -15051,46 +93003,42 @@ Simulation { SimTrace { id: TraceScalarId(230), kind: BigUInt { - index: StatePartIndex(644), - ty: UInt<3>, - }, - state: 0x7, - last_state: 0x7, - }, - SimTrace { - id: TraceScalarId(231), - kind: BigUInt { - index: StatePartIndex(652), + index: StatePartIndex(476), ty: UInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(232), + id: TraceScalarId(231), kind: BigBool { - index: StatePartIndex(655), + index: StatePartIndex(477), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(232), + kind: BigClock { + index: StatePartIndex(478), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(233), kind: BigUInt { - index: StatePartIndex(659), - ty: UInt<4>, + index: StatePartIndex(479), + ty: UInt<2>, }, - state: 0xf, - last_state: 0xf, + state: 0x0, + last_state: 0x0, }, SimTrace { id: TraceScalarId(234), - kind: EnumDiscriminant { - index: StatePartIndex(46), - ty: Enum { - HdlNone, - HdlSome(UInt<4>), - }, + kind: BigUInt { + index: StatePartIndex(480), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, @@ -15098,36 +93046,33 @@ Simulation { SimTrace { id: TraceScalarId(235), kind: BigUInt { - index: StatePartIndex(670), - ty: UInt<4>, + index: StatePartIndex(481), + ty: UInt<1>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(236), - kind: BigClock { - index: StatePartIndex(327), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(237), - kind: BigSyncReset { - index: StatePartIndex(328), + kind: BigBool { + index: StatePartIndex(482), }, state: 0x0, last_state: 0x0, }, + SimTrace { + id: TraceScalarId(237), + kind: BigClock { + index: StatePartIndex(483), + }, + state: 0x1, + last_state: 0x1, + }, SimTrace { id: TraceScalarId(238), - kind: EnumDiscriminant { - index: StatePartIndex(48), - ty: Enum { - HdlNone, - HdlSome(UInt<4>), - }, + kind: BigUInt { + index: StatePartIndex(484), + ty: UInt<2>, }, state: 0x0, last_state: 0x0, @@ -15135,7 +93080,7 @@ Simulation { SimTrace { id: TraceScalarId(239), kind: BigUInt { - index: StatePartIndex(680), + index: StatePartIndex(485), ty: UInt<4>, }, state: 0x0, @@ -15143,16 +93088,7101 @@ Simulation { }, SimTrace { id: TraceScalarId(240), + kind: BigUInt { + index: StatePartIndex(486), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(241), kind: BigBool { - index: StatePartIndex(330), + index: StatePartIndex(487), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(242), + kind: BigClock { + index: StatePartIndex(488), }, state: 0x1, last_state: 0x1, }, SimTrace { - id: TraceScalarId(241), + id: TraceScalarId(243), + kind: BigUInt { + index: StatePartIndex(489), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(244), + kind: BigUInt { + index: StatePartIndex(490), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(245), + kind: BigBool { + index: StatePartIndex(493), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(246), + kind: BigBool { + index: StatePartIndex(494), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(247), + kind: BigBool { + index: StatePartIndex(495), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(248), + kind: BigBool { + index: StatePartIndex(496), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(249), kind: EnumDiscriminant { - index: StatePartIndex(49), + index: StatePartIndex(92), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(250), + kind: BigUInt { + index: StatePartIndex(500), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(251), + kind: EnumDiscriminant { + index: StatePartIndex(93), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(252), + kind: BigUInt { + index: StatePartIndex(502), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(253), + kind: EnumDiscriminant { + index: StatePartIndex(94), + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(254), + kind: EnumDiscriminant { + index: StatePartIndex(95), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(255), + kind: EnumDiscriminant { + index: StatePartIndex(96), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(256), + kind: BigUInt { + index: StatePartIndex(511), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(257), + kind: BigUInt { + index: StatePartIndex(512), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(258), + kind: BigUInt { + index: StatePartIndex(513), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(259), + kind: BigUInt { + index: StatePartIndex(514), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(260), + kind: BigUInt { + index: StatePartIndex(515), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(261), + kind: BigUInt { + index: StatePartIndex(516), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(262), + kind: BigSInt { + index: StatePartIndex(517), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(263), + kind: EnumDiscriminant { + index: StatePartIndex(97), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(264), + kind: BigBool { + index: StatePartIndex(519), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(265), + kind: BigBool { + index: StatePartIndex(520), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(266), + kind: BigBool { + index: StatePartIndex(521), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(267), + kind: BigBool { + index: StatePartIndex(522), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(268), + kind: BigUInt { + index: StatePartIndex(511), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(269), + kind: BigUInt { + index: StatePartIndex(512), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(270), + kind: BigUInt { + index: StatePartIndex(513), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(271), + kind: BigUInt { + index: StatePartIndex(514), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(272), + kind: BigUInt { + index: StatePartIndex(515), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(273), + kind: BigUInt { + index: StatePartIndex(516), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(274), + kind: BigSInt { + index: StatePartIndex(517), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(275), + kind: EnumDiscriminant { + index: StatePartIndex(97), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(276), + kind: BigBool { + index: StatePartIndex(519), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(277), + kind: BigBool { + index: StatePartIndex(520), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(278), + kind: BigBool { + index: StatePartIndex(521), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(279), + kind: BigBool { + index: StatePartIndex(522), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(280), + kind: BigUInt { + index: StatePartIndex(566), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(281), + kind: BigUInt { + index: StatePartIndex(567), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(282), + kind: BigUInt { + index: StatePartIndex(568), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(283), + kind: BigUInt { + index: StatePartIndex(569), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(284), + kind: BigUInt { + index: StatePartIndex(570), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(285), + kind: BigUInt { + index: StatePartIndex(571), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(286), + kind: BigSInt { + index: StatePartIndex(572), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(287), + kind: EnumDiscriminant { + index: StatePartIndex(98), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(288), + kind: BigUInt { + index: StatePartIndex(574), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(289), + kind: EnumDiscriminant { + index: StatePartIndex(99), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(290), + kind: BigUInt { + index: StatePartIndex(578), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(291), + kind: BigUInt { + index: StatePartIndex(579), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(292), + kind: BigUInt { + index: StatePartIndex(580), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(293), + kind: BigUInt { + index: StatePartIndex(581), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(294), + kind: BigUInt { + index: StatePartIndex(582), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(295), + kind: BigUInt { + index: StatePartIndex(583), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(296), + kind: BigSInt { + index: StatePartIndex(584), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(297), + kind: BigUInt { + index: StatePartIndex(578), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(298), + kind: BigUInt { + index: StatePartIndex(579), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(299), + kind: BigUInt { + index: StatePartIndex(580), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(300), + kind: BigUInt { + index: StatePartIndex(581), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(301), + kind: BigUInt { + index: StatePartIndex(582), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(302), + kind: BigUInt { + index: StatePartIndex(583), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(303), + kind: BigSInt { + index: StatePartIndex(584), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(304), + kind: EnumDiscriminant { + index: StatePartIndex(100), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(305), + kind: BigUInt { + index: StatePartIndex(610), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(306), + kind: BigUInt { + index: StatePartIndex(611), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(307), + kind: BigUInt { + index: StatePartIndex(612), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(308), + kind: BigUInt { + index: StatePartIndex(613), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(309), + kind: BigUInt { + index: StatePartIndex(614), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(310), + kind: BigUInt { + index: StatePartIndex(615), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(311), + kind: BigSInt { + index: StatePartIndex(616), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(312), + kind: BigUInt { + index: StatePartIndex(610), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(313), + kind: BigUInt { + index: StatePartIndex(611), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(314), + kind: BigUInt { + index: StatePartIndex(612), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(315), + kind: BigUInt { + index: StatePartIndex(613), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(316), + kind: BigUInt { + index: StatePartIndex(614), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(317), + kind: BigUInt { + index: StatePartIndex(615), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(318), + kind: BigSInt { + index: StatePartIndex(616), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(319), + kind: EnumDiscriminant { + index: StatePartIndex(101), + ty: Enum { + HdlNone, + HdlSome(Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(320), + kind: EnumDiscriminant { + index: StatePartIndex(102), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(321), + kind: EnumDiscriminant { + index: StatePartIndex(103), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(322), + kind: BigUInt { + index: StatePartIndex(639), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(323), + kind: BigUInt { + index: StatePartIndex(640), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(324), + kind: BigUInt { + index: StatePartIndex(641), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(325), + kind: BigUInt { + index: StatePartIndex(642), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(326), + kind: BigUInt { + index: StatePartIndex(643), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(327), + kind: BigUInt { + index: StatePartIndex(644), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(328), + kind: BigSInt { + index: StatePartIndex(645), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(329), + kind: EnumDiscriminant { + index: StatePartIndex(104), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(330), + kind: BigBool { + index: StatePartIndex(647), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(331), + kind: BigBool { + index: StatePartIndex(648), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(332), + kind: BigBool { + index: StatePartIndex(649), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(333), + kind: BigBool { + index: StatePartIndex(650), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(334), + kind: BigUInt { + index: StatePartIndex(639), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(335), + kind: BigUInt { + index: StatePartIndex(640), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(336), + kind: BigUInt { + index: StatePartIndex(641), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(337), + kind: BigUInt { + index: StatePartIndex(642), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(338), + kind: BigUInt { + index: StatePartIndex(643), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(339), + kind: BigUInt { + index: StatePartIndex(644), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(340), + kind: BigSInt { + index: StatePartIndex(645), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(341), + kind: EnumDiscriminant { + index: StatePartIndex(104), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(342), + kind: BigBool { + index: StatePartIndex(647), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(343), + kind: BigBool { + index: StatePartIndex(648), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(344), + kind: BigBool { + index: StatePartIndex(649), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(345), + kind: BigBool { + index: StatePartIndex(650), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(346), + kind: BigUInt { + index: StatePartIndex(694), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(347), + kind: BigUInt { + index: StatePartIndex(695), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(348), + kind: BigUInt { + index: StatePartIndex(696), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(349), + kind: BigUInt { + index: StatePartIndex(697), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(350), + kind: BigUInt { + index: StatePartIndex(698), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(351), + kind: BigUInt { + index: StatePartIndex(699), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(352), + kind: BigSInt { + index: StatePartIndex(700), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(353), + kind: EnumDiscriminant { + index: StatePartIndex(105), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(354), + kind: BigUInt { + index: StatePartIndex(702), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(355), + kind: EnumDiscriminant { + index: StatePartIndex(106), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(356), + kind: BigUInt { + index: StatePartIndex(706), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(357), + kind: BigUInt { + index: StatePartIndex(707), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(358), + kind: BigUInt { + index: StatePartIndex(708), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(359), + kind: BigUInt { + index: StatePartIndex(709), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(360), + kind: BigUInt { + index: StatePartIndex(710), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(361), + kind: BigUInt { + index: StatePartIndex(711), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(362), + kind: BigSInt { + index: StatePartIndex(712), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(363), + kind: BigUInt { + index: StatePartIndex(706), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(364), + kind: BigUInt { + index: StatePartIndex(707), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(365), + kind: BigUInt { + index: StatePartIndex(708), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(366), + kind: BigUInt { + index: StatePartIndex(709), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(367), + kind: BigUInt { + index: StatePartIndex(710), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(368), + kind: BigUInt { + index: StatePartIndex(711), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(369), + kind: BigSInt { + index: StatePartIndex(712), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(370), + kind: EnumDiscriminant { + index: StatePartIndex(107), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(371), + kind: BigUInt { + index: StatePartIndex(738), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(372), + kind: BigUInt { + index: StatePartIndex(739), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(373), + kind: BigUInt { + index: StatePartIndex(740), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(374), + kind: BigUInt { + index: StatePartIndex(741), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(375), + kind: BigUInt { + index: StatePartIndex(742), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(376), + kind: BigUInt { + index: StatePartIndex(743), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(377), + kind: BigSInt { + index: StatePartIndex(744), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(378), + kind: BigUInt { + index: StatePartIndex(738), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(379), + kind: BigUInt { + index: StatePartIndex(739), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(380), + kind: BigUInt { + index: StatePartIndex(740), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(381), + kind: BigUInt { + index: StatePartIndex(741), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(382), + kind: BigUInt { + index: StatePartIndex(742), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(383), + kind: BigUInt { + index: StatePartIndex(743), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(384), + kind: BigSInt { + index: StatePartIndex(744), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(385), + kind: EnumDiscriminant { + index: StatePartIndex(108), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(386), + kind: BigUInt { + index: StatePartIndex(763), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(387), + kind: BigUInt { + index: StatePartIndex(764), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(388), + kind: EnumDiscriminant { + index: StatePartIndex(109), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(389), + kind: BigUInt { + index: StatePartIndex(773), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(390), + kind: BigUInt { + index: StatePartIndex(774), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(391), + kind: BigUInt { + index: StatePartIndex(790), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(392), + kind: EnumDiscriminant { + index: StatePartIndex(110), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(393), + kind: BigUInt { + index: StatePartIndex(792), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(394), + kind: BigUInt { + index: StatePartIndex(793), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(395), + kind: BigUInt { + index: StatePartIndex(824), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(396), + kind: EnumDiscriminant { + index: StatePartIndex(111), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(397), + kind: BigUInt { + index: StatePartIndex(826), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(398), + kind: BigUInt { + index: StatePartIndex(827), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(399), + kind: BigUInt { + index: StatePartIndex(850), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(400), + kind: EnumDiscriminant { + index: StatePartIndex(112), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(401), + kind: BigUInt { + index: StatePartIndex(852), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(402), + kind: BigUInt { + index: StatePartIndex(853), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(403), + kind: BigUInt { + index: StatePartIndex(877), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(404), + kind: EnumDiscriminant { + index: StatePartIndex(113), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(405), + kind: BigUInt { + index: StatePartIndex(879), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(406), + kind: BigUInt { + index: StatePartIndex(880), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(407), + kind: BigUInt { + index: StatePartIndex(904), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(408), + kind: EnumDiscriminant { + index: StatePartIndex(114), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(409), + kind: BigUInt { + index: StatePartIndex(906), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(410), + kind: BigUInt { + index: StatePartIndex(907), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(411), + kind: BigUInt { + index: StatePartIndex(930), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(412), + kind: EnumDiscriminant { + index: StatePartIndex(115), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(413), + kind: BigUInt { + index: StatePartIndex(932), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(414), + kind: BigUInt { + index: StatePartIndex(933), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(415), + kind: EnumDiscriminant { + index: StatePartIndex(116), + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(416), + kind: BigBool { + index: StatePartIndex(962), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(417), + kind: BigBool { + index: StatePartIndex(963), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(418), + kind: BigUInt { + index: StatePartIndex(964), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(419), + kind: BigUInt { + index: StatePartIndex(965), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(420), + kind: EnumDiscriminant { + index: StatePartIndex(117), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(421), + kind: EnumDiscriminant { + index: StatePartIndex(118), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(422), + kind: BigUInt { + index: StatePartIndex(968), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(423), + kind: BigUInt { + index: StatePartIndex(969), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(424), + kind: EnumDiscriminant { + index: StatePartIndex(119), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(425), + kind: EnumDiscriminant { + index: StatePartIndex(120), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(426), + kind: BigUInt { + index: StatePartIndex(972), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(427), + kind: BigUInt { + index: StatePartIndex(973), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(428), + kind: EnumDiscriminant { + index: StatePartIndex(121), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(429), + kind: EnumDiscriminant { + index: StatePartIndex(122), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(430), + kind: BigUInt { + index: StatePartIndex(976), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(431), + kind: BigUInt { + index: StatePartIndex(977), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(432), + kind: EnumDiscriminant { + index: StatePartIndex(123), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(433), + kind: EnumDiscriminant { + index: StatePartIndex(124), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(434), + kind: EnumDiscriminant { + index: StatePartIndex(125), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(435), + kind: EnumDiscriminant { + index: StatePartIndex(126), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(436), + kind: BigUInt { + index: StatePartIndex(984), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(437), + kind: BigUInt { + index: StatePartIndex(985), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(438), + kind: BigUInt { + index: StatePartIndex(986), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(439), + kind: BigUInt { + index: StatePartIndex(987), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(440), + kind: BigUInt { + index: StatePartIndex(988), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(441), + kind: BigUInt { + index: StatePartIndex(989), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(442), + kind: BigSInt { + index: StatePartIndex(990), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(443), + kind: EnumDiscriminant { + index: StatePartIndex(127), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(444), + kind: BigBool { + index: StatePartIndex(992), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(445), + kind: BigBool { + index: StatePartIndex(993), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(446), + kind: BigBool { + index: StatePartIndex(994), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(447), + kind: BigBool { + index: StatePartIndex(995), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(448), + kind: BigUInt { + index: StatePartIndex(984), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(449), + kind: BigUInt { + index: StatePartIndex(985), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(450), + kind: BigUInt { + index: StatePartIndex(986), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(451), + kind: BigUInt { + index: StatePartIndex(987), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(452), + kind: BigUInt { + index: StatePartIndex(988), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(453), + kind: BigUInt { + index: StatePartIndex(989), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(454), + kind: BigSInt { + index: StatePartIndex(990), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(455), + kind: EnumDiscriminant { + index: StatePartIndex(127), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(456), + kind: BigBool { + index: StatePartIndex(992), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(457), + kind: BigBool { + index: StatePartIndex(993), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(458), + kind: BigBool { + index: StatePartIndex(994), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(459), + kind: BigBool { + index: StatePartIndex(995), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(460), + kind: BigUInt { + index: StatePartIndex(1039), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(461), + kind: BigUInt { + index: StatePartIndex(1040), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(462), + kind: BigUInt { + index: StatePartIndex(1041), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(463), + kind: BigUInt { + index: StatePartIndex(1042), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(464), + kind: BigUInt { + index: StatePartIndex(1043), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(465), + kind: BigUInt { + index: StatePartIndex(1044), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(466), + kind: BigSInt { + index: StatePartIndex(1045), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(467), + kind: EnumDiscriminant { + index: StatePartIndex(128), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(468), + kind: BigUInt { + index: StatePartIndex(1047), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(469), + kind: EnumDiscriminant { + index: StatePartIndex(129), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(470), + kind: BigUInt { + index: StatePartIndex(1051), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(471), + kind: BigUInt { + index: StatePartIndex(1052), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(472), + kind: BigUInt { + index: StatePartIndex(1053), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(473), + kind: BigUInt { + index: StatePartIndex(1054), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(474), + kind: BigUInt { + index: StatePartIndex(1055), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(475), + kind: BigUInt { + index: StatePartIndex(1056), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(476), + kind: BigSInt { + index: StatePartIndex(1057), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(477), + kind: BigUInt { + index: StatePartIndex(1051), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(478), + kind: BigUInt { + index: StatePartIndex(1052), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(479), + kind: BigUInt { + index: StatePartIndex(1053), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(480), + kind: BigUInt { + index: StatePartIndex(1054), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(481), + kind: BigUInt { + index: StatePartIndex(1055), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(482), + kind: BigUInt { + index: StatePartIndex(1056), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(483), + kind: BigSInt { + index: StatePartIndex(1057), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(484), + kind: EnumDiscriminant { + index: StatePartIndex(130), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(485), + kind: BigUInt { + index: StatePartIndex(1083), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(486), + kind: BigUInt { + index: StatePartIndex(1084), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(487), + kind: BigUInt { + index: StatePartIndex(1085), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(488), + kind: BigUInt { + index: StatePartIndex(1086), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(489), + kind: BigUInt { + index: StatePartIndex(1087), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(490), + kind: BigUInt { + index: StatePartIndex(1088), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(491), + kind: BigSInt { + index: StatePartIndex(1089), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(492), + kind: BigUInt { + index: StatePartIndex(1083), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(493), + kind: BigUInt { + index: StatePartIndex(1084), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(494), + kind: BigUInt { + index: StatePartIndex(1085), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(495), + kind: BigUInt { + index: StatePartIndex(1086), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(496), + kind: BigUInt { + index: StatePartIndex(1087), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(497), + kind: BigUInt { + index: StatePartIndex(1088), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(498), + kind: BigSInt { + index: StatePartIndex(1089), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(499), + kind: EnumDiscriminant { + index: StatePartIndex(131), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(500), + kind: BigUInt { + index: StatePartIndex(1107), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(501), + kind: BigUInt { + index: StatePartIndex(1108), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(502), + kind: BigUInt { + index: StatePartIndex(1109), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(503), + kind: BigUInt { + index: StatePartIndex(1110), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(504), + kind: BigUInt { + index: StatePartIndex(1111), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(505), + kind: BigUInt { + index: StatePartIndex(1112), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(506), + kind: BigSInt { + index: StatePartIndex(1113), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(507), + kind: EnumDiscriminant { + index: StatePartIndex(132), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(508), + kind: BigBool { + index: StatePartIndex(1115), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(509), + kind: BigBool { + index: StatePartIndex(1116), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(510), + kind: BigBool { + index: StatePartIndex(1117), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(511), + kind: BigBool { + index: StatePartIndex(1118), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(512), + kind: BigUInt { + index: StatePartIndex(1107), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(513), + kind: BigUInt { + index: StatePartIndex(1108), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(514), + kind: BigUInt { + index: StatePartIndex(1109), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(515), + kind: BigUInt { + index: StatePartIndex(1110), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(516), + kind: BigUInt { + index: StatePartIndex(1111), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(517), + kind: BigUInt { + index: StatePartIndex(1112), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(518), + kind: BigSInt { + index: StatePartIndex(1113), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(519), + kind: EnumDiscriminant { + index: StatePartIndex(132), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(520), + kind: BigBool { + index: StatePartIndex(1115), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(521), + kind: BigBool { + index: StatePartIndex(1116), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(522), + kind: BigBool { + index: StatePartIndex(1117), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(523), + kind: BigBool { + index: StatePartIndex(1118), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(524), + kind: BigUInt { + index: StatePartIndex(1162), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(525), + kind: BigUInt { + index: StatePartIndex(1163), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(526), + kind: BigUInt { + index: StatePartIndex(1164), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(527), + kind: BigUInt { + index: StatePartIndex(1165), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(528), + kind: BigUInt { + index: StatePartIndex(1166), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(529), + kind: BigUInt { + index: StatePartIndex(1167), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(530), + kind: BigSInt { + index: StatePartIndex(1168), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(531), + kind: EnumDiscriminant { + index: StatePartIndex(133), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(532), + kind: BigUInt { + index: StatePartIndex(1170), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(533), + kind: BigUInt { + index: StatePartIndex(1172), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(534), + kind: BigUInt { + index: StatePartIndex(1173), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(535), + kind: BigUInt { + index: StatePartIndex(1182), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(536), + kind: BigUInt { + index: StatePartIndex(1183), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(537), + kind: BigUInt { + index: StatePartIndex(1185), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(538), + kind: BigUInt { + index: StatePartIndex(1186), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(539), + kind: BigUInt { + index: StatePartIndex(1285), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(540), + kind: BigUInt { + index: StatePartIndex(1286), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(541), + kind: BigUInt { + index: StatePartIndex(1288), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(542), + kind: BigUInt { + index: StatePartIndex(1289), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(543), + kind: BigUInt { + index: StatePartIndex(1398), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(544), + kind: BigUInt { + index: StatePartIndex(1399), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(545), + kind: BigUInt { + index: StatePartIndex(1401), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(546), + kind: BigUInt { + index: StatePartIndex(1402), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(547), + kind: EnumDiscriminant { + index: StatePartIndex(134), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(548), + kind: BigUInt { + index: StatePartIndex(1503), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(549), + kind: BigUInt { + index: StatePartIndex(1504), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(550), + kind: BigUInt { + index: StatePartIndex(1505), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(551), + kind: BigUInt { + index: StatePartIndex(1506), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(552), + kind: BigUInt { + index: StatePartIndex(1507), + ty: UInt<6>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(553), + kind: BigUInt { + index: StatePartIndex(1508), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(554), + kind: BigSInt { + index: StatePartIndex(1509), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(555), + kind: BigUInt { + index: StatePartIndex(1503), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(556), + kind: BigUInt { + index: StatePartIndex(1504), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(557), + kind: BigUInt { + index: StatePartIndex(1505), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(558), + kind: BigUInt { + index: StatePartIndex(1506), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(559), + kind: BigUInt { + index: StatePartIndex(1507), + ty: UInt<6>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(560), + kind: BigUInt { + index: StatePartIndex(1508), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(561), + kind: BigSInt { + index: StatePartIndex(1509), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(562), + kind: BigUInt { + index: StatePartIndex(1604), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(563), + kind: BigUInt { + index: StatePartIndex(1605), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(564), + kind: EnumDiscriminant { + index: StatePartIndex(135), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(565), + kind: BigUInt { + index: StatePartIndex(1686), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(566), + kind: BigUInt { + index: StatePartIndex(1687), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(567), + kind: BigUInt { + index: StatePartIndex(1688), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(568), + kind: BigUInt { + index: StatePartIndex(1689), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(569), + kind: BigUInt { + index: StatePartIndex(1690), + ty: UInt<6>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(570), + kind: BigUInt { + index: StatePartIndex(1691), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(571), + kind: BigSInt { + index: StatePartIndex(1692), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(572), + kind: BigUInt { + index: StatePartIndex(1686), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(573), + kind: BigUInt { + index: StatePartIndex(1687), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(574), + kind: BigUInt { + index: StatePartIndex(1688), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(575), + kind: BigUInt { + index: StatePartIndex(1689), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(576), + kind: BigUInt { + index: StatePartIndex(1690), + ty: UInt<6>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(577), + kind: BigUInt { + index: StatePartIndex(1691), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(578), + kind: BigSInt { + index: StatePartIndex(1692), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(579), + kind: BigUInt { + index: StatePartIndex(1770), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(580), + kind: BigUInt { + index: StatePartIndex(1771), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(581), + kind: EnumDiscriminant { + index: StatePartIndex(136), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(582), + kind: BigUInt { + index: StatePartIndex(1853), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(583), + kind: BigUInt { + index: StatePartIndex(1856), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(584), + kind: EnumDiscriminant { + index: StatePartIndex(137), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(585), + kind: BigUInt { + index: StatePartIndex(1865), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(586), + kind: BigUInt { + index: StatePartIndex(1866), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(587), + kind: EnumDiscriminant { + index: StatePartIndex(138), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(588), + kind: BigUInt { + index: StatePartIndex(1877), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(589), + kind: BigUInt { + index: StatePartIndex(1878), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(590), + kind: EnumDiscriminant { + index: StatePartIndex(139), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(591), + kind: BigUInt { + index: StatePartIndex(1880), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(592), + kind: BigUInt { + index: StatePartIndex(1881), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(593), + kind: BigUInt { + index: StatePartIndex(1904), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(594), + kind: BigUInt { + index: StatePartIndex(1905), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(595), + kind: EnumDiscriminant { + index: StatePartIndex(140), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(596), + kind: EnumDiscriminant { + index: StatePartIndex(141), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(597), + kind: BigUInt { + index: StatePartIndex(1908), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(598), + kind: BigUInt { + index: StatePartIndex(1909), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(599), + kind: EnumDiscriminant { + index: StatePartIndex(142), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(600), + kind: EnumDiscriminant { + index: StatePartIndex(143), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(601), + kind: BigUInt { + index: StatePartIndex(1912), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(602), + kind: BigUInt { + index: StatePartIndex(1913), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(603), + kind: EnumDiscriminant { + index: StatePartIndex(144), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(604), + kind: EnumDiscriminant { + index: StatePartIndex(145), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(605), + kind: BigUInt { + index: StatePartIndex(1916), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(606), + kind: BigUInt { + index: StatePartIndex(1917), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(607), + kind: EnumDiscriminant { + index: StatePartIndex(146), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(608), + kind: EnumDiscriminant { + index: StatePartIndex(147), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(609), + kind: BigUInt { + index: StatePartIndex(1920), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(610), + kind: BigUInt { + index: StatePartIndex(1923), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(611), + kind: BigUInt { + index: StatePartIndex(1940), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(612), + kind: EnumDiscriminant { + index: StatePartIndex(148), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(613), + kind: BigUInt { + index: StatePartIndex(1942), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(614), + kind: BigUInt { + index: StatePartIndex(1943), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(615), + kind: BigUInt { + index: StatePartIndex(1966), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(616), + kind: BigUInt { + index: StatePartIndex(1967), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(617), + kind: EnumDiscriminant { + index: StatePartIndex(149), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(618), + kind: EnumDiscriminant { + index: StatePartIndex(150), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(619), + kind: BigUInt { + index: StatePartIndex(1970), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(620), + kind: BigUInt { + index: StatePartIndex(1971), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(621), + kind: EnumDiscriminant { + index: StatePartIndex(151), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(622), + kind: EnumDiscriminant { + index: StatePartIndex(152), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(623), + kind: BigUInt { + index: StatePartIndex(1974), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(624), + kind: BigUInt { + index: StatePartIndex(1975), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(625), + kind: EnumDiscriminant { + index: StatePartIndex(153), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(626), + kind: EnumDiscriminant { + index: StatePartIndex(154), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(627), + kind: BigUInt { + index: StatePartIndex(1978), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(628), + kind: BigUInt { + index: StatePartIndex(1979), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(629), + kind: EnumDiscriminant { + index: StatePartIndex(155), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(630), + kind: EnumDiscriminant { + index: StatePartIndex(156), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(631), + kind: BigUInt { + index: StatePartIndex(1982), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(632), + kind: BigUInt { + index: StatePartIndex(1983), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(633), + kind: BigUInt { + index: StatePartIndex(1988), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(634), + kind: EnumDiscriminant { + index: StatePartIndex(157), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(635), + kind: BigUInt { + index: StatePartIndex(1990), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(636), + kind: BigUInt { + index: StatePartIndex(1991), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(637), + kind: BigUInt { + index: StatePartIndex(2014), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(638), + kind: BigUInt { + index: StatePartIndex(2015), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(639), + kind: EnumDiscriminant { + index: StatePartIndex(158), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(640), + kind: EnumDiscriminant { + index: StatePartIndex(159), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(641), + kind: BigUInt { + index: StatePartIndex(2018), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(642), + kind: BigUInt { + index: StatePartIndex(2019), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(643), + kind: EnumDiscriminant { + index: StatePartIndex(160), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(644), + kind: EnumDiscriminant { + index: StatePartIndex(161), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(645), + kind: BigUInt { + index: StatePartIndex(2022), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(646), + kind: BigUInt { + index: StatePartIndex(2023), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(647), + kind: EnumDiscriminant { + index: StatePartIndex(162), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(648), + kind: EnumDiscriminant { + index: StatePartIndex(163), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(649), + kind: BigUInt { + index: StatePartIndex(2026), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(650), + kind: BigUInt { + index: StatePartIndex(2027), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(651), + kind: EnumDiscriminant { + index: StatePartIndex(164), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(652), + kind: EnumDiscriminant { + index: StatePartIndex(165), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(653), + kind: BigUInt { + index: StatePartIndex(2030), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(654), + kind: BigUInt { + index: StatePartIndex(2031), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(655), + kind: BigUInt { + index: StatePartIndex(2036), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(656), + kind: EnumDiscriminant { + index: StatePartIndex(166), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(657), + kind: BigUInt { + index: StatePartIndex(2038), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(658), + kind: BigUInt { + index: StatePartIndex(2039), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(659), + kind: BigUInt { + index: StatePartIndex(2062), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(660), + kind: BigUInt { + index: StatePartIndex(2063), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(661), + kind: EnumDiscriminant { + index: StatePartIndex(167), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(662), + kind: EnumDiscriminant { + index: StatePartIndex(168), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(663), + kind: BigUInt { + index: StatePartIndex(2066), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(664), + kind: BigUInt { + index: StatePartIndex(2067), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(665), + kind: EnumDiscriminant { + index: StatePartIndex(169), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(666), + kind: EnumDiscriminant { + index: StatePartIndex(170), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(667), + kind: BigUInt { + index: StatePartIndex(2070), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(668), + kind: BigUInt { + index: StatePartIndex(2071), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(669), + kind: EnumDiscriminant { + index: StatePartIndex(171), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(670), + kind: EnumDiscriminant { + index: StatePartIndex(172), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(671), + kind: BigUInt { + index: StatePartIndex(2074), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(672), + kind: BigUInt { + index: StatePartIndex(2075), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(673), + kind: EnumDiscriminant { + index: StatePartIndex(173), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(674), + kind: EnumDiscriminant { + index: StatePartIndex(174), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(675), + kind: BigUInt { + index: StatePartIndex(2078), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(676), + kind: BigUInt { + index: StatePartIndex(2079), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(677), + kind: BigUInt { + index: StatePartIndex(2084), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(678), + kind: EnumDiscriminant { + index: StatePartIndex(175), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(679), + kind: BigUInt { + index: StatePartIndex(2086), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(680), + kind: BigUInt { + index: StatePartIndex(2087), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(681), + kind: BigUInt { + index: StatePartIndex(2110), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(682), + kind: BigUInt { + index: StatePartIndex(2111), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(683), + kind: EnumDiscriminant { + index: StatePartIndex(176), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(684), + kind: EnumDiscriminant { + index: StatePartIndex(177), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(685), + kind: BigUInt { + index: StatePartIndex(2114), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(686), + kind: BigUInt { + index: StatePartIndex(2115), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(687), + kind: EnumDiscriminant { + index: StatePartIndex(178), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(688), + kind: EnumDiscriminant { + index: StatePartIndex(179), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(689), + kind: BigUInt { + index: StatePartIndex(2118), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(690), + kind: BigUInt { + index: StatePartIndex(2119), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(691), + kind: EnumDiscriminant { + index: StatePartIndex(180), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(692), + kind: EnumDiscriminant { + index: StatePartIndex(181), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(693), + kind: BigUInt { + index: StatePartIndex(2122), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(694), + kind: BigUInt { + index: StatePartIndex(2123), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(695), + kind: EnumDiscriminant { + index: StatePartIndex(182), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(696), + kind: EnumDiscriminant { + index: StatePartIndex(183), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(697), + kind: BigUInt { + index: StatePartIndex(2126), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(698), + kind: BigUInt { + index: StatePartIndex(2127), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(699), + kind: BigUInt { + index: StatePartIndex(2132), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(700), + kind: EnumDiscriminant { + index: StatePartIndex(184), + ty: Enum { + HdlNone, + HdlSome(Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(701), + kind: BigUInt { + index: StatePartIndex(2134), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(702), + kind: BigUInt { + index: StatePartIndex(2135), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(703), + kind: BigUInt { + index: StatePartIndex(2158), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(704), + kind: BigUInt { + index: StatePartIndex(2159), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(705), + kind: EnumDiscriminant { + index: StatePartIndex(185), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(706), + kind: EnumDiscriminant { + index: StatePartIndex(186), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(707), + kind: BigUInt { + index: StatePartIndex(2162), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(708), + kind: BigUInt { + index: StatePartIndex(2163), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(709), + kind: EnumDiscriminant { + index: StatePartIndex(187), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(710), + kind: EnumDiscriminant { + index: StatePartIndex(188), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(711), + kind: BigUInt { + index: StatePartIndex(2166), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(712), + kind: BigUInt { + index: StatePartIndex(2167), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(713), + kind: EnumDiscriminant { + index: StatePartIndex(189), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(714), + kind: EnumDiscriminant { + index: StatePartIndex(190), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(715), + kind: BigUInt { + index: StatePartIndex(2170), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(716), + kind: BigUInt { + index: StatePartIndex(2171), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(717), + kind: EnumDiscriminant { + index: StatePartIndex(191), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(718), + kind: EnumDiscriminant { + index: StatePartIndex(192), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(719), + kind: BigUInt { + index: StatePartIndex(2174), + ty: UInt<8>, + }, + state: 0xfe, + last_state: 0xfe, + }, + SimTrace { + id: TraceScalarId(720), + kind: BigUInt { + index: StatePartIndex(2175), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(721), + kind: EnumDiscriminant { + index: StatePartIndex(193), + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(722), + kind: BigBool { + index: StatePartIndex(2181), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(723), + kind: BigBool { + index: StatePartIndex(2182), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(724), + kind: BigUInt { + index: StatePartIndex(2183), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(725), + kind: BigUInt { + index: StatePartIndex(2184), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(726), + kind: EnumDiscriminant { + index: StatePartIndex(194), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(727), + kind: EnumDiscriminant { + index: StatePartIndex(195), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(728), + kind: BigUInt { + index: StatePartIndex(2187), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(729), + kind: BigUInt { + index: StatePartIndex(2188), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(730), + kind: EnumDiscriminant { + index: StatePartIndex(196), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(731), + kind: EnumDiscriminant { + index: StatePartIndex(197), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(732), + kind: BigUInt { + index: StatePartIndex(2191), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(733), + kind: BigUInt { + index: StatePartIndex(2192), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(734), + kind: EnumDiscriminant { + index: StatePartIndex(198), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(735), + kind: EnumDiscriminant { + index: StatePartIndex(199), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(736), + kind: BigUInt { + index: StatePartIndex(2195), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(737), + kind: BigUInt { + index: StatePartIndex(2196), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(738), + kind: EnumDiscriminant { + index: StatePartIndex(200), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(739), + kind: EnumDiscriminant { + index: StatePartIndex(201), + ty: Enum { + HdlNone, + HdlSome(Bundle {}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(740), + kind: EnumDiscriminant { + index: StatePartIndex(202), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(741), + kind: EnumDiscriminant { + index: StatePartIndex(203), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(742), + kind: BigUInt { + index: StatePartIndex(2203), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(743), + kind: BigUInt { + index: StatePartIndex(2204), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(744), + kind: BigUInt { + index: StatePartIndex(2205), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(745), + kind: BigUInt { + index: StatePartIndex(2206), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(746), + kind: BigUInt { + index: StatePartIndex(2207), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(747), + kind: BigUInt { + index: StatePartIndex(2208), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(748), + kind: BigSInt { + index: StatePartIndex(2209), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(749), + kind: EnumDiscriminant { + index: StatePartIndex(204), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(750), + kind: BigBool { + index: StatePartIndex(2211), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(751), + kind: BigBool { + index: StatePartIndex(2212), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(752), + kind: BigBool { + index: StatePartIndex(2213), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(753), + kind: BigBool { + index: StatePartIndex(2214), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(754), + kind: BigUInt { + index: StatePartIndex(2203), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(755), + kind: BigUInt { + index: StatePartIndex(2204), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(756), + kind: BigUInt { + index: StatePartIndex(2205), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(757), + kind: BigUInt { + index: StatePartIndex(2206), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(758), + kind: BigUInt { + index: StatePartIndex(2207), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(759), + kind: BigUInt { + index: StatePartIndex(2208), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(760), + kind: BigSInt { + index: StatePartIndex(2209), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(761), + kind: EnumDiscriminant { + index: StatePartIndex(204), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(762), + kind: BigBool { + index: StatePartIndex(2211), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(763), + kind: BigBool { + index: StatePartIndex(2212), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(764), + kind: BigBool { + index: StatePartIndex(2213), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(765), + kind: BigBool { + index: StatePartIndex(2214), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(766), + kind: BigUInt { + index: StatePartIndex(2258), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(767), + kind: BigUInt { + index: StatePartIndex(2259), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(768), + kind: BigUInt { + index: StatePartIndex(2260), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(769), + kind: BigUInt { + index: StatePartIndex(2261), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(770), + kind: BigUInt { + index: StatePartIndex(2262), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(771), + kind: BigUInt { + index: StatePartIndex(2263), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(772), + kind: BigSInt { + index: StatePartIndex(2264), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(773), + kind: EnumDiscriminant { + index: StatePartIndex(205), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(774), + kind: BigUInt { + index: StatePartIndex(2266), + ty: UInt<4>, + }, + state: 0x6, + last_state: 0x6, + }, + SimTrace { + id: TraceScalarId(775), + kind: EnumDiscriminant { + index: StatePartIndex(206), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(776), + kind: BigUInt { + index: StatePartIndex(2270), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(777), + kind: BigUInt { + index: StatePartIndex(2271), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(778), + kind: BigUInt { + index: StatePartIndex(2272), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(779), + kind: BigUInt { + index: StatePartIndex(2273), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(780), + kind: BigUInt { + index: StatePartIndex(2274), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(781), + kind: BigUInt { + index: StatePartIndex(2275), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(782), + kind: BigSInt { + index: StatePartIndex(2276), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(783), + kind: BigUInt { + index: StatePartIndex(2270), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(784), + kind: BigUInt { + index: StatePartIndex(2271), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(785), + kind: BigUInt { + index: StatePartIndex(2272), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(786), + kind: BigUInt { + index: StatePartIndex(2273), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(787), + kind: BigUInt { + index: StatePartIndex(2274), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(788), + kind: BigUInt { + index: StatePartIndex(2275), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(789), + kind: BigSInt { + index: StatePartIndex(2276), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(790), + kind: EnumDiscriminant { + index: StatePartIndex(207), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(791), + kind: BigUInt { + index: StatePartIndex(2302), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(792), + kind: BigUInt { + index: StatePartIndex(2303), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(793), + kind: BigUInt { + index: StatePartIndex(2304), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(794), + kind: BigUInt { + index: StatePartIndex(2305), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(795), + kind: BigUInt { + index: StatePartIndex(2306), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(796), + kind: BigUInt { + index: StatePartIndex(2307), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(797), + kind: BigSInt { + index: StatePartIndex(2308), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(798), + kind: BigUInt { + index: StatePartIndex(2302), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(799), + kind: BigUInt { + index: StatePartIndex(2303), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(800), + kind: BigUInt { + index: StatePartIndex(2304), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(801), + kind: BigUInt { + index: StatePartIndex(2305), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(802), + kind: BigUInt { + index: StatePartIndex(2306), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(803), + kind: BigUInt { + index: StatePartIndex(2307), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(804), + kind: BigSInt { + index: StatePartIndex(2308), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(805), + kind: EnumDiscriminant { + index: StatePartIndex(208), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(806), + kind: BigUInt { + index: StatePartIndex(2326), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(807), + kind: BigUInt { + index: StatePartIndex(2327), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(808), + kind: BigUInt { + index: StatePartIndex(2328), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(809), + kind: BigUInt { + index: StatePartIndex(2329), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(810), + kind: BigUInt { + index: StatePartIndex(2330), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(811), + kind: BigUInt { + index: StatePartIndex(2331), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(812), + kind: BigSInt { + index: StatePartIndex(2332), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(813), + kind: EnumDiscriminant { + index: StatePartIndex(209), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(814), + kind: BigBool { + index: StatePartIndex(2334), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(815), + kind: BigBool { + index: StatePartIndex(2335), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(816), + kind: BigBool { + index: StatePartIndex(2336), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(817), + kind: BigBool { + index: StatePartIndex(2337), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(818), + kind: BigUInt { + index: StatePartIndex(2326), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(819), + kind: BigUInt { + index: StatePartIndex(2327), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(820), + kind: BigUInt { + index: StatePartIndex(2328), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(821), + kind: BigUInt { + index: StatePartIndex(2329), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(822), + kind: BigUInt { + index: StatePartIndex(2330), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(823), + kind: BigUInt { + index: StatePartIndex(2331), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(824), + kind: BigSInt { + index: StatePartIndex(2332), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(825), + kind: EnumDiscriminant { + index: StatePartIndex(209), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(826), + kind: BigBool { + index: StatePartIndex(2334), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(827), + kind: BigBool { + index: StatePartIndex(2335), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(828), + kind: BigBool { + index: StatePartIndex(2336), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(829), + kind: BigBool { + index: StatePartIndex(2337), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(830), + kind: BigUInt { + index: StatePartIndex(2381), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(831), + kind: BigUInt { + index: StatePartIndex(2382), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(832), + kind: BigUInt { + index: StatePartIndex(2383), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(833), + kind: BigUInt { + index: StatePartIndex(2384), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(834), + kind: BigUInt { + index: StatePartIndex(2385), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(835), + kind: BigUInt { + index: StatePartIndex(2386), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(836), + kind: BigSInt { + index: StatePartIndex(2387), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(837), + kind: EnumDiscriminant { + index: StatePartIndex(210), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(838), + kind: BigUInt { + index: StatePartIndex(2389), + ty: UInt<4>, + }, + state: 0x6, + last_state: 0x6, + }, + SimTrace { + id: TraceScalarId(839), + kind: BigUInt { + index: StatePartIndex(2391), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(840), + kind: BigUInt { + index: StatePartIndex(2392), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(841), + kind: BigUInt { + index: StatePartIndex(2394), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(842), + kind: BigUInt { + index: StatePartIndex(2395), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(843), + kind: BigUInt { + index: StatePartIndex(2397), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(844), + kind: BigUInt { + index: StatePartIndex(2398), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(845), + kind: BigUInt { + index: StatePartIndex(2496), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(846), + kind: BigUInt { + index: StatePartIndex(2497), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(847), + kind: BigUInt { + index: StatePartIndex(2499), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(848), + kind: BigUInt { + index: StatePartIndex(2500), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(849), + kind: BigUInt { + index: StatePartIndex(2609), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(850), + kind: BigUInt { + index: StatePartIndex(2610), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(851), + kind: BigUInt { + index: StatePartIndex(2612), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(852), + kind: BigUInt { + index: StatePartIndex(2613), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(853), + kind: EnumDiscriminant { + index: StatePartIndex(211), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(854), + kind: BigUInt { + index: StatePartIndex(2714), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(855), + kind: BigUInt { + index: StatePartIndex(2715), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(856), + kind: BigUInt { + index: StatePartIndex(2716), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(857), + kind: BigUInt { + index: StatePartIndex(2717), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(858), + kind: BigUInt { + index: StatePartIndex(2718), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(859), + kind: BigUInt { + index: StatePartIndex(2719), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(860), + kind: BigSInt { + index: StatePartIndex(2720), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(861), + kind: BigUInt { + index: StatePartIndex(2714), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(862), + kind: BigUInt { + index: StatePartIndex(2715), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(863), + kind: BigUInt { + index: StatePartIndex(2716), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(864), + kind: BigUInt { + index: StatePartIndex(2717), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(865), + kind: BigUInt { + index: StatePartIndex(2718), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(866), + kind: BigUInt { + index: StatePartIndex(2719), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(867), + kind: BigSInt { + index: StatePartIndex(2720), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(868), + kind: BigUInt { + index: StatePartIndex(2813), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(869), + kind: BigUInt { + index: StatePartIndex(2814), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(870), + kind: EnumDiscriminant { + index: StatePartIndex(212), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(871), + kind: BigUInt { + index: StatePartIndex(2895), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(872), + kind: BigUInt { + index: StatePartIndex(2896), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(873), + kind: BigUInt { + index: StatePartIndex(2897), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(874), + kind: BigUInt { + index: StatePartIndex(2898), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(875), + kind: BigUInt { + index: StatePartIndex(2899), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(876), + kind: BigUInt { + index: StatePartIndex(2900), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(877), + kind: BigSInt { + index: StatePartIndex(2901), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(878), + kind: BigUInt { + index: StatePartIndex(2895), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(879), + kind: BigUInt { + index: StatePartIndex(2896), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(880), + kind: BigUInt { + index: StatePartIndex(2897), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(881), + kind: BigUInt { + index: StatePartIndex(2898), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(882), + kind: BigUInt { + index: StatePartIndex(2899), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(883), + kind: BigUInt { + index: StatePartIndex(2900), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(884), + kind: BigSInt { + index: StatePartIndex(2901), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(885), + kind: BigUInt { + index: StatePartIndex(2979), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(886), + kind: BigUInt { + index: StatePartIndex(2980), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(887), + kind: EnumDiscriminant { + index: StatePartIndex(213), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(888), + kind: BigUInt { + index: StatePartIndex(3062), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(889), + kind: BigUInt { + index: StatePartIndex(3063), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(890), + kind: EnumDiscriminant { + index: StatePartIndex(214), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(891), + kind: BigUInt { + index: StatePartIndex(3072), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(892), + kind: BigUInt { + index: StatePartIndex(3073), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(893), + kind: EnumDiscriminant { + index: StatePartIndex(215), + ty: Enum { + HdlNone, + HdlSome(UInt<2>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(894), + kind: BigUInt { + index: StatePartIndex(3082), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(895), + kind: BigClock { + index: StatePartIndex(3089), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(896), + kind: BigSyncReset { + index: StatePartIndex(3090), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(897), + kind: EnumDiscriminant { + index: StatePartIndex(217), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(898), + kind: EnumDiscriminant { + index: StatePartIndex(218), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(899), + kind: BigUInt { + index: StatePartIndex(3096), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(900), + kind: BigUInt { + index: StatePartIndex(3097), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(901), + kind: BigUInt { + index: StatePartIndex(3098), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(902), + kind: BigUInt { + index: StatePartIndex(3099), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(903), + kind: BigUInt { + index: StatePartIndex(3100), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(904), + kind: BigUInt { + index: StatePartIndex(3101), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(905), + kind: BigSInt { + index: StatePartIndex(3102), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(906), + kind: EnumDiscriminant { + index: StatePartIndex(219), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(907), + kind: BigBool { + index: StatePartIndex(3104), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(908), + kind: BigBool { + index: StatePartIndex(3105), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(909), + kind: BigBool { + index: StatePartIndex(3106), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(910), + kind: BigBool { + index: StatePartIndex(3107), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(911), + kind: BigUInt { + index: StatePartIndex(3096), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(912), + kind: BigUInt { + index: StatePartIndex(3097), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(913), + kind: BigUInt { + index: StatePartIndex(3098), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(914), + kind: BigUInt { + index: StatePartIndex(3099), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(915), + kind: BigUInt { + index: StatePartIndex(3100), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(916), + kind: BigUInt { + index: StatePartIndex(3101), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(917), + kind: BigSInt { + index: StatePartIndex(3102), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(918), + kind: EnumDiscriminant { + index: StatePartIndex(219), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(919), + kind: BigBool { + index: StatePartIndex(3104), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(920), + kind: BigBool { + index: StatePartIndex(3105), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(921), + kind: BigBool { + index: StatePartIndex(3106), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(922), + kind: BigBool { + index: StatePartIndex(3107), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(923), + kind: BigUInt { + index: StatePartIndex(3151), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(924), + kind: BigUInt { + index: StatePartIndex(3152), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(925), + kind: BigUInt { + index: StatePartIndex(3153), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(926), + kind: BigUInt { + index: StatePartIndex(3154), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(927), + kind: BigUInt { + index: StatePartIndex(3155), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(928), + kind: BigUInt { + index: StatePartIndex(3156), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(929), + kind: BigSInt { + index: StatePartIndex(3157), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(930), + kind: EnumDiscriminant { + index: StatePartIndex(220), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(931), + kind: BigUInt { + index: StatePartIndex(3159), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(932), + kind: BigBool { + index: StatePartIndex(3092), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(933), + kind: BigClock { + index: StatePartIndex(3085), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(934), + kind: BigSyncReset { + index: StatePartIndex(3086), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(935), + kind: EnumDiscriminant { + index: StatePartIndex(221), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(936), + kind: EnumDiscriminant { + index: StatePartIndex(222), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(937), + kind: BigUInt { + index: StatePartIndex(3164), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(938), + kind: BigUInt { + index: StatePartIndex(3165), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(939), + kind: BigUInt { + index: StatePartIndex(3166), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(940), + kind: BigUInt { + index: StatePartIndex(3167), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(941), + kind: BigUInt { + index: StatePartIndex(3168), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(942), + kind: BigUInt { + index: StatePartIndex(3169), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(943), + kind: BigSInt { + index: StatePartIndex(3170), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(944), + kind: EnumDiscriminant { + index: StatePartIndex(223), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(945), + kind: BigBool { + index: StatePartIndex(3172), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(946), + kind: BigBool { + index: StatePartIndex(3173), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(947), + kind: BigBool { + index: StatePartIndex(3174), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(948), + kind: BigBool { + index: StatePartIndex(3175), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(949), + kind: BigUInt { + index: StatePartIndex(3164), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(950), + kind: BigUInt { + index: StatePartIndex(3165), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(951), + kind: BigUInt { + index: StatePartIndex(3166), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(952), + kind: BigUInt { + index: StatePartIndex(3167), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(953), + kind: BigUInt { + index: StatePartIndex(3168), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(954), + kind: BigUInt { + index: StatePartIndex(3169), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(955), + kind: BigSInt { + index: StatePartIndex(3170), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(956), + kind: EnumDiscriminant { + index: StatePartIndex(223), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(957), + kind: BigBool { + index: StatePartIndex(3172), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(958), + kind: BigBool { + index: StatePartIndex(3173), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(959), + kind: BigBool { + index: StatePartIndex(3174), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(960), + kind: BigBool { + index: StatePartIndex(3175), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(961), + kind: BigUInt { + index: StatePartIndex(3219), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(962), + kind: BigUInt { + index: StatePartIndex(3220), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(963), + kind: BigUInt { + index: StatePartIndex(3221), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(964), + kind: BigUInt { + index: StatePartIndex(3222), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(965), + kind: BigUInt { + index: StatePartIndex(3223), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(966), + kind: BigUInt { + index: StatePartIndex(3224), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(967), + kind: BigSInt { + index: StatePartIndex(3225), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(968), + kind: EnumDiscriminant { + index: StatePartIndex(224), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(969), + kind: BigUInt { + index: StatePartIndex(3227), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(970), + kind: BigBool { + index: StatePartIndex(3088), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(971), + kind: BigClock { + index: StatePartIndex(3235), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(972), + kind: BigSyncReset { + index: StatePartIndex(3236), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(973), + kind: EnumDiscriminant { + index: StatePartIndex(225), ty: Enum { HdlNone, HdlSome(UInt<4>), @@ -15162,24 +100192,6398 @@ Simulation { last_state: 0x0, }, SimTrace { - id: TraceScalarId(242), + id: TraceScalarId(974), kind: BigUInt { - index: StatePartIndex(682), + index: StatePartIndex(3240), ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, SimTrace { - id: TraceScalarId(243), + id: TraceScalarId(975), kind: BigBool { - index: StatePartIndex(332), + index: StatePartIndex(3238), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(976), + kind: EnumDiscriminant { + index: StatePartIndex(226), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(977), + kind: BigUInt { + index: StatePartIndex(3244), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(978), + kind: BigBool { + index: StatePartIndex(3242), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(979), + kind: BigBool { + index: StatePartIndex(3245), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(980), + kind: BigBool { + index: StatePartIndex(3246), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(981), + kind: BigBool { + index: StatePartIndex(3247), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(982), + kind: BigBool { + index: StatePartIndex(3248), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(983), + kind: BigBool { + index: StatePartIndex(3249), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(984), + kind: BigBool { + index: StatePartIndex(3250), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(985), + kind: BigBool { + index: StatePartIndex(3251), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(986), + kind: BigBool { + index: StatePartIndex(3252), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(987), + kind: BigBool { + index: StatePartIndex(3253), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(988), + kind: BigBool { + index: StatePartIndex(3254), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(989), + kind: BigBool { + index: StatePartIndex(3255), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(990), + kind: BigBool { + index: StatePartIndex(3256), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(991), + kind: BigBool { + index: StatePartIndex(3257), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(992), + kind: BigBool { + index: StatePartIndex(3258), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(993), + kind: BigBool { + index: StatePartIndex(3259), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(994), + kind: BigBool { + index: StatePartIndex(3260), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(995), + kind: EnumDiscriminant { + index: StatePartIndex(231), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(996), + kind: BigUInt { + index: StatePartIndex(3295), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(997), + kind: BigUInt { + index: StatePartIndex(3298), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(998), + kind: BigBool { + index: StatePartIndex(3307), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(999), + kind: BigUInt { + index: StatePartIndex(3311), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1000), + kind: BigUInt { + index: StatePartIndex(3320), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1001), + kind: BigBool { + index: StatePartIndex(3329), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1002), + kind: BigUInt { + index: StatePartIndex(3333), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1003), + kind: BigUInt { + index: StatePartIndex(3340), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1004), + kind: BigBool { + index: StatePartIndex(3343), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1005), + kind: BigUInt { + index: StatePartIndex(3347), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1006), + kind: BigUInt { + index: StatePartIndex(3356), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1007), + kind: BigBool { + index: StatePartIndex(3365), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1008), + kind: BigUInt { + index: StatePartIndex(3369), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1009), + kind: BigUInt { + index: StatePartIndex(3376), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1010), + kind: BigBool { + index: StatePartIndex(3385), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1011), + kind: BigUInt { + index: StatePartIndex(3389), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1012), + kind: BigUInt { + index: StatePartIndex(3396), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1013), + kind: BigBool { + index: StatePartIndex(3399), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1014), + kind: BigUInt { + index: StatePartIndex(3403), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1015), + kind: BigUInt { + index: StatePartIndex(3411), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1016), + kind: BigBool { + index: StatePartIndex(3414), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1017), + kind: BigUInt { + index: StatePartIndex(3418), + ty: UInt<3>, + }, + state: 0x7, + last_state: 0x7, + }, + SimTrace { + id: TraceScalarId(1018), + kind: BigUInt { + index: StatePartIndex(3427), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1019), + kind: BigBool { + index: StatePartIndex(3436), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1020), + kind: BigUInt { + index: StatePartIndex(3440), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1021), + kind: BigUInt { + index: StatePartIndex(3447), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1022), + kind: BigBool { + index: StatePartIndex(3456), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1023), + kind: BigUInt { + index: StatePartIndex(3460), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1024), + kind: BigUInt { + index: StatePartIndex(3467), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1025), + kind: BigBool { + index: StatePartIndex(3470), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1026), + kind: BigUInt { + index: StatePartIndex(3474), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1027), + kind: BigUInt { + index: StatePartIndex(3482), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1028), + kind: BigBool { + index: StatePartIndex(3491), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1029), + kind: BigUInt { + index: StatePartIndex(3495), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1030), + kind: BigUInt { + index: StatePartIndex(3502), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1031), + kind: BigBool { + index: StatePartIndex(3511), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1032), + kind: BigUInt { + index: StatePartIndex(3515), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1033), + kind: BigUInt { + index: StatePartIndex(3522), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1034), + kind: BigBool { + index: StatePartIndex(3525), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1035), + kind: BigUInt { + index: StatePartIndex(3529), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1036), + kind: BigUInt { + index: StatePartIndex(3537), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1037), + kind: BigBool { + index: StatePartIndex(3540), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1038), + kind: BigUInt { + index: StatePartIndex(3544), + ty: UInt<3>, + }, + state: 0x7, + last_state: 0x7, + }, + SimTrace { + id: TraceScalarId(1039), + kind: BigUInt { + index: StatePartIndex(3552), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1040), + kind: BigBool { + index: StatePartIndex(3555), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1041), + kind: BigUInt { + index: StatePartIndex(3559), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(1042), + kind: EnumDiscriminant { + index: StatePartIndex(248), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1043), + kind: BigUInt { + index: StatePartIndex(3570), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1044), + kind: BigClock { + index: StatePartIndex(3229), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1045), + kind: BigSyncReset { + index: StatePartIndex(3230), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1046), + kind: EnumDiscriminant { + index: StatePartIndex(250), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1047), + kind: BigUInt { + index: StatePartIndex(3580), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1048), + kind: BigBool { + index: StatePartIndex(3232), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1049), + kind: EnumDiscriminant { + index: StatePartIndex(251), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1050), + kind: BigUInt { + index: StatePartIndex(3582), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1051), + kind: BigBool { + index: StatePartIndex(3234), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1052), + kind: EnumDiscriminant { + index: StatePartIndex(252), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1053), + kind: EnumDiscriminant { + index: StatePartIndex(253), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1054), + kind: BigUInt { + index: StatePartIndex(3591), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1055), + kind: BigUInt { + index: StatePartIndex(3592), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1056), + kind: BigUInt { + index: StatePartIndex(3593), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1057), + kind: BigUInt { + index: StatePartIndex(3594), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1058), + kind: BigUInt { + index: StatePartIndex(3595), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1059), + kind: BigUInt { + index: StatePartIndex(3596), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1060), + kind: BigSInt { + index: StatePartIndex(3597), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1061), + kind: EnumDiscriminant { + index: StatePartIndex(254), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1062), + kind: BigBool { + index: StatePartIndex(3599), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1063), + kind: BigBool { + index: StatePartIndex(3600), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1064), + kind: BigBool { + index: StatePartIndex(3601), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1065), + kind: BigBool { + index: StatePartIndex(3602), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1066), + kind: BigUInt { + index: StatePartIndex(3591), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1067), + kind: BigUInt { + index: StatePartIndex(3592), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1068), + kind: BigUInt { + index: StatePartIndex(3593), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1069), + kind: BigUInt { + index: StatePartIndex(3594), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1070), + kind: BigUInt { + index: StatePartIndex(3595), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1071), + kind: BigUInt { + index: StatePartIndex(3596), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1072), + kind: BigSInt { + index: StatePartIndex(3597), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1073), + kind: EnumDiscriminant { + index: StatePartIndex(254), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1074), + kind: BigBool { + index: StatePartIndex(3599), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1075), + kind: BigBool { + index: StatePartIndex(3600), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1076), + kind: BigBool { + index: StatePartIndex(3601), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1077), + kind: BigBool { + index: StatePartIndex(3602), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1078), + kind: BigUInt { + index: StatePartIndex(3646), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1079), + kind: BigUInt { + index: StatePartIndex(3647), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1080), + kind: BigUInt { + index: StatePartIndex(3648), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1081), + kind: BigUInt { + index: StatePartIndex(3649), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1082), + kind: BigUInt { + index: StatePartIndex(3650), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1083), + kind: BigUInt { + index: StatePartIndex(3651), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1084), + kind: BigSInt { + index: StatePartIndex(3652), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1085), + kind: EnumDiscriminant { + index: StatePartIndex(255), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1086), + kind: BigUInt { + index: StatePartIndex(3654), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1087), + kind: EnumDiscriminant { + index: StatePartIndex(256), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1088), + kind: EnumDiscriminant { + index: StatePartIndex(257), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1089), + kind: BigUInt { + index: StatePartIndex(3660), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1090), + kind: BigUInt { + index: StatePartIndex(3661), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1091), + kind: BigUInt { + index: StatePartIndex(3662), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1092), + kind: BigUInt { + index: StatePartIndex(3663), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1093), + kind: BigUInt { + index: StatePartIndex(3664), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1094), + kind: BigUInt { + index: StatePartIndex(3665), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1095), + kind: BigSInt { + index: StatePartIndex(3666), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1096), + kind: EnumDiscriminant { + index: StatePartIndex(258), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1097), + kind: BigBool { + index: StatePartIndex(3668), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1098), + kind: BigBool { + index: StatePartIndex(3669), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1099), + kind: BigBool { + index: StatePartIndex(3670), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1100), + kind: BigBool { + index: StatePartIndex(3671), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1101), + kind: BigUInt { + index: StatePartIndex(3660), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1102), + kind: BigUInt { + index: StatePartIndex(3661), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1103), + kind: BigUInt { + index: StatePartIndex(3662), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1104), + kind: BigUInt { + index: StatePartIndex(3663), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1105), + kind: BigUInt { + index: StatePartIndex(3664), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1106), + kind: BigUInt { + index: StatePartIndex(3665), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1107), + kind: BigSInt { + index: StatePartIndex(3666), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1108), + kind: EnumDiscriminant { + index: StatePartIndex(258), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1109), + kind: BigBool { + index: StatePartIndex(3668), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1110), + kind: BigBool { + index: StatePartIndex(3669), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1111), + kind: BigBool { + index: StatePartIndex(3670), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1112), + kind: BigBool { + index: StatePartIndex(3671), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1113), + kind: BigUInt { + index: StatePartIndex(3715), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1114), + kind: BigUInt { + index: StatePartIndex(3716), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1115), + kind: BigUInt { + index: StatePartIndex(3717), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1116), + kind: BigUInt { + index: StatePartIndex(3718), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1117), + kind: BigUInt { + index: StatePartIndex(3719), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1118), + kind: BigUInt { + index: StatePartIndex(3720), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1119), + kind: BigSInt { + index: StatePartIndex(3721), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1120), + kind: EnumDiscriminant { + index: StatePartIndex(259), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1121), + kind: BigUInt { + index: StatePartIndex(3723), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1122), + kind: EnumDiscriminant { + index: StatePartIndex(260), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1123), + kind: EnumDiscriminant { + index: StatePartIndex(261), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1124), + kind: BigUInt { + index: StatePartIndex(3766), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1125), + kind: BigUInt { + index: StatePartIndex(3767), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1126), + kind: BigUInt { + index: StatePartIndex(3768), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1127), + kind: BigUInt { + index: StatePartIndex(3769), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1128), + kind: BigUInt { + index: StatePartIndex(3770), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1129), + kind: BigUInt { + index: StatePartIndex(3771), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1130), + kind: BigSInt { + index: StatePartIndex(3772), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1131), + kind: EnumDiscriminant { + index: StatePartIndex(262), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1132), + kind: BigBool { + index: StatePartIndex(3774), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1133), + kind: BigBool { + index: StatePartIndex(3775), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1134), + kind: BigBool { + index: StatePartIndex(3776), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1135), + kind: BigBool { + index: StatePartIndex(3777), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1136), + kind: BigUInt { + index: StatePartIndex(3766), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1137), + kind: BigUInt { + index: StatePartIndex(3767), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1138), + kind: BigUInt { + index: StatePartIndex(3768), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1139), + kind: BigUInt { + index: StatePartIndex(3769), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1140), + kind: BigUInt { + index: StatePartIndex(3770), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1141), + kind: BigUInt { + index: StatePartIndex(3771), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1142), + kind: BigSInt { + index: StatePartIndex(3772), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1143), + kind: EnumDiscriminant { + index: StatePartIndex(262), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1144), + kind: BigBool { + index: StatePartIndex(3774), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1145), + kind: BigBool { + index: StatePartIndex(3775), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1146), + kind: BigBool { + index: StatePartIndex(3776), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1147), + kind: BigBool { + index: StatePartIndex(3777), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1148), + kind: BigUInt { + index: StatePartIndex(3821), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1149), + kind: BigUInt { + index: StatePartIndex(3822), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1150), + kind: BigUInt { + index: StatePartIndex(3823), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1151), + kind: BigUInt { + index: StatePartIndex(3824), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1152), + kind: BigUInt { + index: StatePartIndex(3825), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1153), + kind: BigUInt { + index: StatePartIndex(3826), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1154), + kind: BigSInt { + index: StatePartIndex(3827), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1155), + kind: EnumDiscriminant { + index: StatePartIndex(263), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1156), + kind: BigUInt { + index: StatePartIndex(3829), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1157), + kind: EnumDiscriminant { + index: StatePartIndex(264), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1158), + kind: EnumDiscriminant { + index: StatePartIndex(265), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1159), + kind: BigUInt { + index: StatePartIndex(3835), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1160), + kind: BigUInt { + index: StatePartIndex(3836), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1161), + kind: BigUInt { + index: StatePartIndex(3837), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1162), + kind: BigUInt { + index: StatePartIndex(3838), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1163), + kind: BigUInt { + index: StatePartIndex(3839), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1164), + kind: BigUInt { + index: StatePartIndex(3840), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1165), + kind: BigSInt { + index: StatePartIndex(3841), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1166), + kind: EnumDiscriminant { + index: StatePartIndex(266), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1167), + kind: BigBool { + index: StatePartIndex(3843), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1168), + kind: BigBool { + index: StatePartIndex(3844), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1169), + kind: BigBool { + index: StatePartIndex(3845), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1170), + kind: BigBool { + index: StatePartIndex(3846), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1171), + kind: BigUInt { + index: StatePartIndex(3835), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1172), + kind: BigUInt { + index: StatePartIndex(3836), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1173), + kind: BigUInt { + index: StatePartIndex(3837), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1174), + kind: BigUInt { + index: StatePartIndex(3838), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1175), + kind: BigUInt { + index: StatePartIndex(3839), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1176), + kind: BigUInt { + index: StatePartIndex(3840), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1177), + kind: BigSInt { + index: StatePartIndex(3841), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1178), + kind: EnumDiscriminant { + index: StatePartIndex(266), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1179), + kind: BigBool { + index: StatePartIndex(3843), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1180), + kind: BigBool { + index: StatePartIndex(3844), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1181), + kind: BigBool { + index: StatePartIndex(3845), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1182), + kind: BigBool { + index: StatePartIndex(3846), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1183), + kind: BigUInt { + index: StatePartIndex(3890), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1184), + kind: BigUInt { + index: StatePartIndex(3891), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1185), + kind: BigUInt { + index: StatePartIndex(3892), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1186), + kind: BigUInt { + index: StatePartIndex(3893), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1187), + kind: BigUInt { + index: StatePartIndex(3894), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1188), + kind: BigUInt { + index: StatePartIndex(3895), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1189), + kind: BigSInt { + index: StatePartIndex(3896), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1190), + kind: EnumDiscriminant { + index: StatePartIndex(267), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1191), + kind: BigUInt { + index: StatePartIndex(3898), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1192), + kind: BigClock { + index: StatePartIndex(3918), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1193), + kind: BigSyncReset { + index: StatePartIndex(3919), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1194), + kind: EnumDiscriminant { + index: StatePartIndex(268), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1195), + kind: EnumDiscriminant { + index: StatePartIndex(269), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1196), + kind: BigUInt { + index: StatePartIndex(3925), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1197), + kind: BigUInt { + index: StatePartIndex(3926), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1198), + kind: BigUInt { + index: StatePartIndex(3927), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1199), + kind: BigUInt { + index: StatePartIndex(3928), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1200), + kind: BigUInt { + index: StatePartIndex(3929), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1201), + kind: BigUInt { + index: StatePartIndex(3930), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1202), + kind: BigSInt { + index: StatePartIndex(3931), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1203), + kind: EnumDiscriminant { + index: StatePartIndex(270), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1204), + kind: BigBool { + index: StatePartIndex(3933), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1205), + kind: BigBool { + index: StatePartIndex(3934), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1206), + kind: BigBool { + index: StatePartIndex(3935), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1207), + kind: BigBool { + index: StatePartIndex(3936), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1208), + kind: BigUInt { + index: StatePartIndex(3925), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1209), + kind: BigUInt { + index: StatePartIndex(3926), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1210), + kind: BigUInt { + index: StatePartIndex(3927), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1211), + kind: BigUInt { + index: StatePartIndex(3928), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1212), + kind: BigUInt { + index: StatePartIndex(3929), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1213), + kind: BigUInt { + index: StatePartIndex(3930), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1214), + kind: BigSInt { + index: StatePartIndex(3931), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1215), + kind: EnumDiscriminant { + index: StatePartIndex(270), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1216), + kind: BigBool { + index: StatePartIndex(3933), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1217), + kind: BigBool { + index: StatePartIndex(3934), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1218), + kind: BigBool { + index: StatePartIndex(3935), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1219), + kind: BigBool { + index: StatePartIndex(3936), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1220), + kind: BigUInt { + index: StatePartIndex(3980), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1221), + kind: BigUInt { + index: StatePartIndex(3981), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1222), + kind: BigUInt { + index: StatePartIndex(3982), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1223), + kind: BigUInt { + index: StatePartIndex(3983), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1224), + kind: BigUInt { + index: StatePartIndex(3984), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1225), + kind: BigUInt { + index: StatePartIndex(3985), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1226), + kind: BigSInt { + index: StatePartIndex(3986), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1227), + kind: EnumDiscriminant { + index: StatePartIndex(271), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1228), + kind: BigUInt { + index: StatePartIndex(3988), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1229), + kind: BigBool { + index: StatePartIndex(3921), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1230), + kind: BigClock { + index: StatePartIndex(3914), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1231), + kind: BigSyncReset { + index: StatePartIndex(3915), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1232), + kind: EnumDiscriminant { + index: StatePartIndex(272), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1233), + kind: EnumDiscriminant { + index: StatePartIndex(273), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1234), + kind: BigUInt { + index: StatePartIndex(3993), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1235), + kind: BigUInt { + index: StatePartIndex(3994), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1236), + kind: BigUInt { + index: StatePartIndex(3995), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1237), + kind: BigUInt { + index: StatePartIndex(3996), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1238), + kind: BigUInt { + index: StatePartIndex(3997), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1239), + kind: BigUInt { + index: StatePartIndex(3998), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1240), + kind: BigSInt { + index: StatePartIndex(3999), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1241), + kind: EnumDiscriminant { + index: StatePartIndex(274), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1242), + kind: BigBool { + index: StatePartIndex(4001), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1243), + kind: BigBool { + index: StatePartIndex(4002), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1244), + kind: BigBool { + index: StatePartIndex(4003), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1245), + kind: BigBool { + index: StatePartIndex(4004), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1246), + kind: BigUInt { + index: StatePartIndex(3993), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1247), + kind: BigUInt { + index: StatePartIndex(3994), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1248), + kind: BigUInt { + index: StatePartIndex(3995), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1249), + kind: BigUInt { + index: StatePartIndex(3996), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1250), + kind: BigUInt { + index: StatePartIndex(3997), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1251), + kind: BigUInt { + index: StatePartIndex(3998), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1252), + kind: BigSInt { + index: StatePartIndex(3999), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1253), + kind: EnumDiscriminant { + index: StatePartIndex(274), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1254), + kind: BigBool { + index: StatePartIndex(4001), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1255), + kind: BigBool { + index: StatePartIndex(4002), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1256), + kind: BigBool { + index: StatePartIndex(4003), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1257), + kind: BigBool { + index: StatePartIndex(4004), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1258), + kind: BigUInt { + index: StatePartIndex(4048), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1259), + kind: BigUInt { + index: StatePartIndex(4049), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1260), + kind: BigUInt { + index: StatePartIndex(4050), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1261), + kind: BigUInt { + index: StatePartIndex(4051), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1262), + kind: BigUInt { + index: StatePartIndex(4052), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1263), + kind: BigUInt { + index: StatePartIndex(4053), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1264), + kind: BigSInt { + index: StatePartIndex(4054), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1265), + kind: EnumDiscriminant { + index: StatePartIndex(275), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1266), + kind: BigUInt { + index: StatePartIndex(4056), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1267), + kind: BigBool { + index: StatePartIndex(3917), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1268), + kind: BigClock { + index: StatePartIndex(4064), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1269), + kind: BigSyncReset { + index: StatePartIndex(4065), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1270), + kind: EnumDiscriminant { + index: StatePartIndex(276), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1271), + kind: BigUInt { + index: StatePartIndex(4069), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1272), + kind: BigBool { + index: StatePartIndex(4067), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1273), + kind: EnumDiscriminant { + index: StatePartIndex(277), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1274), + kind: BigUInt { + index: StatePartIndex(4073), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1275), + kind: BigBool { + index: StatePartIndex(4071), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1276), + kind: BigBool { + index: StatePartIndex(4074), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1277), + kind: BigBool { + index: StatePartIndex(4075), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1278), + kind: BigBool { + index: StatePartIndex(4076), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1279), + kind: BigBool { + index: StatePartIndex(4077), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1280), + kind: BigBool { + index: StatePartIndex(4078), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1281), + kind: BigBool { + index: StatePartIndex(4079), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1282), + kind: BigBool { + index: StatePartIndex(4080), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1283), + kind: BigBool { + index: StatePartIndex(4081), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1284), + kind: BigBool { + index: StatePartIndex(4082), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1285), + kind: BigBool { + index: StatePartIndex(4083), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1286), + kind: BigBool { + index: StatePartIndex(4084), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1287), + kind: BigBool { + index: StatePartIndex(4085), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1288), + kind: BigBool { + index: StatePartIndex(4086), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1289), + kind: BigBool { + index: StatePartIndex(4087), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1290), + kind: BigBool { + index: StatePartIndex(4088), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1291), + kind: BigBool { + index: StatePartIndex(4089), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1292), + kind: EnumDiscriminant { + index: StatePartIndex(282), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1293), + kind: BigUInt { + index: StatePartIndex(4108), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1294), + kind: BigUInt { + index: StatePartIndex(4109), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1295), + kind: BigBool { + index: StatePartIndex(4118), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1296), + kind: BigUInt { + index: StatePartIndex(4122), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1297), + kind: BigUInt { + index: StatePartIndex(4129), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1298), + kind: BigBool { + index: StatePartIndex(4138), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1299), + kind: BigUInt { + index: StatePartIndex(4142), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1300), + kind: BigUInt { + index: StatePartIndex(4149), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1301), + kind: BigBool { + index: StatePartIndex(4152), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1302), + kind: BigUInt { + index: StatePartIndex(4156), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1303), + kind: BigUInt { + index: StatePartIndex(4164), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1304), + kind: BigBool { + index: StatePartIndex(4173), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1305), + kind: BigUInt { + index: StatePartIndex(4177), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1306), + kind: BigUInt { + index: StatePartIndex(4184), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1307), + kind: BigBool { + index: StatePartIndex(4193), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1308), + kind: BigUInt { + index: StatePartIndex(4197), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1309), + kind: BigUInt { + index: StatePartIndex(4204), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1310), + kind: BigBool { + index: StatePartIndex(4207), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1311), + kind: BigUInt { + index: StatePartIndex(4211), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1312), + kind: BigUInt { + index: StatePartIndex(4219), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1313), + kind: BigBool { + index: StatePartIndex(4222), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1314), + kind: BigUInt { + index: StatePartIndex(4226), + ty: UInt<3>, + }, + state: 0x7, + last_state: 0x7, + }, + SimTrace { + id: TraceScalarId(1315), + kind: BigUInt { + index: StatePartIndex(4234), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1316), + kind: BigBool { + index: StatePartIndex(4243), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1317), + kind: BigUInt { + index: StatePartIndex(4247), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1318), + kind: BigUInt { + index: StatePartIndex(4254), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1319), + kind: BigBool { + index: StatePartIndex(4263), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1320), + kind: BigUInt { + index: StatePartIndex(4267), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1321), + kind: BigUInt { + index: StatePartIndex(4274), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1322), + kind: BigBool { + index: StatePartIndex(4277), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1323), + kind: BigUInt { + index: StatePartIndex(4281), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1324), + kind: BigUInt { + index: StatePartIndex(4289), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1325), + kind: BigBool { + index: StatePartIndex(4298), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1326), + kind: BigUInt { + index: StatePartIndex(4302), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1327), + kind: BigUInt { + index: StatePartIndex(4309), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1328), + kind: BigBool { + index: StatePartIndex(4318), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1329), + kind: BigUInt { + index: StatePartIndex(4322), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1330), + kind: BigUInt { + index: StatePartIndex(4329), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1331), + kind: BigBool { + index: StatePartIndex(4332), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1332), + kind: BigUInt { + index: StatePartIndex(4336), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1333), + kind: BigUInt { + index: StatePartIndex(4344), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1334), + kind: BigBool { + index: StatePartIndex(4347), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1335), + kind: BigUInt { + index: StatePartIndex(4351), + ty: UInt<3>, + }, + state: 0x7, + last_state: 0x7, + }, + SimTrace { + id: TraceScalarId(1336), + kind: BigUInt { + index: StatePartIndex(4359), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1337), + kind: BigBool { + index: StatePartIndex(4362), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1338), + kind: BigUInt { + index: StatePartIndex(4366), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(1339), + kind: EnumDiscriminant { + index: StatePartIndex(299), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1340), + kind: BigUInt { + index: StatePartIndex(4376), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1341), + kind: BigClock { + index: StatePartIndex(4058), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1342), + kind: BigSyncReset { + index: StatePartIndex(4059), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1343), + kind: EnumDiscriminant { + index: StatePartIndex(301), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1344), + kind: BigUInt { + index: StatePartIndex(4386), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1345), + kind: BigBool { + index: StatePartIndex(4061), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1346), + kind: EnumDiscriminant { + index: StatePartIndex(302), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1347), + kind: BigUInt { + index: StatePartIndex(4388), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1348), + kind: BigBool { + index: StatePartIndex(4063), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1349), + kind: EnumDiscriminant { + index: StatePartIndex(303), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1350), + kind: EnumDiscriminant { + index: StatePartIndex(304), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1351), + kind: BigUInt { + index: StatePartIndex(4395), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1352), + kind: BigUInt { + index: StatePartIndex(4396), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1353), + kind: BigUInt { + index: StatePartIndex(4397), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1354), + kind: BigUInt { + index: StatePartIndex(4398), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1355), + kind: BigUInt { + index: StatePartIndex(4399), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1356), + kind: BigUInt { + index: StatePartIndex(4400), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1357), + kind: BigSInt { + index: StatePartIndex(4401), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1358), + kind: EnumDiscriminant { + index: StatePartIndex(305), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1359), + kind: BigBool { + index: StatePartIndex(4403), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1360), + kind: BigBool { + index: StatePartIndex(4404), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1361), + kind: BigBool { + index: StatePartIndex(4405), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1362), + kind: BigBool { + index: StatePartIndex(4406), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1363), + kind: BigUInt { + index: StatePartIndex(4395), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1364), + kind: BigUInt { + index: StatePartIndex(4396), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1365), + kind: BigUInt { + index: StatePartIndex(4397), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1366), + kind: BigUInt { + index: StatePartIndex(4398), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1367), + kind: BigUInt { + index: StatePartIndex(4399), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1368), + kind: BigUInt { + index: StatePartIndex(4400), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1369), + kind: BigSInt { + index: StatePartIndex(4401), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1370), + kind: EnumDiscriminant { + index: StatePartIndex(305), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1371), + kind: BigBool { + index: StatePartIndex(4403), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1372), + kind: BigBool { + index: StatePartIndex(4404), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1373), + kind: BigBool { + index: StatePartIndex(4405), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1374), + kind: BigBool { + index: StatePartIndex(4406), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1375), + kind: BigUInt { + index: StatePartIndex(4450), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1376), + kind: BigUInt { + index: StatePartIndex(4451), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1377), + kind: BigUInt { + index: StatePartIndex(4452), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1378), + kind: BigUInt { + index: StatePartIndex(4453), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1379), + kind: BigUInt { + index: StatePartIndex(4454), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1380), + kind: BigUInt { + index: StatePartIndex(4455), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1381), + kind: BigSInt { + index: StatePartIndex(4456), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1382), + kind: EnumDiscriminant { + index: StatePartIndex(306), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1383), + kind: BigUInt { + index: StatePartIndex(4458), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1384), + kind: EnumDiscriminant { + index: StatePartIndex(307), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1385), + kind: EnumDiscriminant { + index: StatePartIndex(308), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1386), + kind: BigUInt { + index: StatePartIndex(4464), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1387), + kind: BigUInt { + index: StatePartIndex(4465), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1388), + kind: BigUInt { + index: StatePartIndex(4466), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1389), + kind: BigUInt { + index: StatePartIndex(4467), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1390), + kind: BigUInt { + index: StatePartIndex(4468), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1391), + kind: BigUInt { + index: StatePartIndex(4469), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1392), + kind: BigSInt { + index: StatePartIndex(4470), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1393), + kind: EnumDiscriminant { + index: StatePartIndex(309), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1394), + kind: BigBool { + index: StatePartIndex(4472), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1395), + kind: BigBool { + index: StatePartIndex(4473), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1396), + kind: BigBool { + index: StatePartIndex(4474), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1397), + kind: BigBool { + index: StatePartIndex(4475), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1398), + kind: BigUInt { + index: StatePartIndex(4464), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1399), + kind: BigUInt { + index: StatePartIndex(4465), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1400), + kind: BigUInt { + index: StatePartIndex(4466), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1401), + kind: BigUInt { + index: StatePartIndex(4467), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1402), + kind: BigUInt { + index: StatePartIndex(4468), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1403), + kind: BigUInt { + index: StatePartIndex(4469), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1404), + kind: BigSInt { + index: StatePartIndex(4470), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1405), + kind: EnumDiscriminant { + index: StatePartIndex(309), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1406), + kind: BigBool { + index: StatePartIndex(4472), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1407), + kind: BigBool { + index: StatePartIndex(4473), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1408), + kind: BigBool { + index: StatePartIndex(4474), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1409), + kind: BigBool { + index: StatePartIndex(4475), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1410), + kind: BigUInt { + index: StatePartIndex(4519), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1411), + kind: BigUInt { + index: StatePartIndex(4520), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1412), + kind: BigUInt { + index: StatePartIndex(4521), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1413), + kind: BigUInt { + index: StatePartIndex(4522), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1414), + kind: BigUInt { + index: StatePartIndex(4523), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1415), + kind: BigUInt { + index: StatePartIndex(4524), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1416), + kind: BigSInt { + index: StatePartIndex(4525), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1417), + kind: EnumDiscriminant { + index: StatePartIndex(310), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1418), + kind: BigUInt { + index: StatePartIndex(4527), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1419), + kind: EnumDiscriminant { + index: StatePartIndex(311), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1420), + kind: EnumDiscriminant { + index: StatePartIndex(312), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1421), + kind: BigUInt { + index: StatePartIndex(4555), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1422), + kind: BigUInt { + index: StatePartIndex(4556), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1423), + kind: BigUInt { + index: StatePartIndex(4557), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1424), + kind: BigUInt { + index: StatePartIndex(4558), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1425), + kind: BigUInt { + index: StatePartIndex(4559), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1426), + kind: BigUInt { + index: StatePartIndex(4560), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1427), + kind: BigSInt { + index: StatePartIndex(4561), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1428), + kind: EnumDiscriminant { + index: StatePartIndex(313), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1429), + kind: BigBool { + index: StatePartIndex(4563), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1430), + kind: BigBool { + index: StatePartIndex(4564), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1431), + kind: BigBool { + index: StatePartIndex(4565), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1432), + kind: BigBool { + index: StatePartIndex(4566), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1433), + kind: BigUInt { + index: StatePartIndex(4555), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1434), + kind: BigUInt { + index: StatePartIndex(4556), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1435), + kind: BigUInt { + index: StatePartIndex(4557), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1436), + kind: BigUInt { + index: StatePartIndex(4558), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1437), + kind: BigUInt { + index: StatePartIndex(4559), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1438), + kind: BigUInt { + index: StatePartIndex(4560), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1439), + kind: BigSInt { + index: StatePartIndex(4561), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1440), + kind: EnumDiscriminant { + index: StatePartIndex(313), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1441), + kind: BigBool { + index: StatePartIndex(4563), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1442), + kind: BigBool { + index: StatePartIndex(4564), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1443), + kind: BigBool { + index: StatePartIndex(4565), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1444), + kind: BigBool { + index: StatePartIndex(4566), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1445), + kind: BigUInt { + index: StatePartIndex(4610), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1446), + kind: BigUInt { + index: StatePartIndex(4611), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1447), + kind: BigUInt { + index: StatePartIndex(4612), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1448), + kind: BigUInt { + index: StatePartIndex(4613), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1449), + kind: BigUInt { + index: StatePartIndex(4614), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1450), + kind: BigUInt { + index: StatePartIndex(4615), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1451), + kind: BigSInt { + index: StatePartIndex(4616), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1452), + kind: EnumDiscriminant { + index: StatePartIndex(314), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1453), + kind: BigUInt { + index: StatePartIndex(4618), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1454), + kind: EnumDiscriminant { + index: StatePartIndex(315), + ty: Enum { + HdlNone, + HdlSome(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1455), + kind: EnumDiscriminant { + index: StatePartIndex(316), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: Bundle {value: UInt<4>}, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1456), + kind: BigUInt { + index: StatePartIndex(4624), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1457), + kind: BigUInt { + index: StatePartIndex(4625), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1458), + kind: BigUInt { + index: StatePartIndex(4626), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1459), + kind: BigUInt { + index: StatePartIndex(4627), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1460), + kind: BigUInt { + index: StatePartIndex(4628), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1461), + kind: BigUInt { + index: StatePartIndex(4629), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1462), + kind: BigSInt { + index: StatePartIndex(4630), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1463), + kind: EnumDiscriminant { + index: StatePartIndex(317), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1464), + kind: BigBool { + index: StatePartIndex(4632), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1465), + kind: BigBool { + index: StatePartIndex(4633), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1466), + kind: BigBool { + index: StatePartIndex(4634), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1467), + kind: BigBool { + index: StatePartIndex(4635), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1468), + kind: BigUInt { + index: StatePartIndex(4624), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1469), + kind: BigUInt { + index: StatePartIndex(4625), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1470), + kind: BigUInt { + index: StatePartIndex(4626), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1471), + kind: BigUInt { + index: StatePartIndex(4627), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1472), + kind: BigUInt { + index: StatePartIndex(4628), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1473), + kind: BigUInt { + index: StatePartIndex(4629), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1474), + kind: BigSInt { + index: StatePartIndex(4630), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1475), + kind: EnumDiscriminant { + index: StatePartIndex(317), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1476), + kind: BigBool { + index: StatePartIndex(4632), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1477), + kind: BigBool { + index: StatePartIndex(4633), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1478), + kind: BigBool { + index: StatePartIndex(4634), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1479), + kind: BigBool { + index: StatePartIndex(4635), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1480), + kind: BigUInt { + index: StatePartIndex(4679), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1481), + kind: BigUInt { + index: StatePartIndex(4680), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1482), + kind: BigUInt { + index: StatePartIndex(4681), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1483), + kind: BigUInt { + index: StatePartIndex(4682), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1484), + kind: BigUInt { + index: StatePartIndex(4683), + ty: UInt<6>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(1485), + kind: BigUInt { + index: StatePartIndex(4684), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(1486), + kind: BigSInt { + index: StatePartIndex(4685), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1487), + kind: EnumDiscriminant { + index: StatePartIndex(318), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1488), + kind: BigUInt { + index: StatePartIndex(4687), + ty: UInt<4>, }, state: 0x0, last_state: 0x0, }, ], - trace_memories: {}, + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "rename_table_normal_mem", + stride: 6, + element_type: TraceBundle { + name: "rename_table_normal_mem", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 253, + stride: 6, + start: 0, + len: 2, + }, + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 253, + stride: 6, + start: 2, + len: 4, + }, + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(185), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(186), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(187), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(188), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(189), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r1", + bundle: TraceBundle { + name: "r1", + fields: [ + TraceUInt { + location: TraceScalarId(190), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(191), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(192), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(193), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(194), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r2", + bundle: TraceBundle { + name: "r2", + fields: [ + TraceUInt { + location: TraceScalarId(195), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(196), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(197), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(198), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(199), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r3", + bundle: TraceBundle { + name: "r3", + fields: [ + TraceUInt { + location: TraceScalarId(200), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(201), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(202), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(203), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(204), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r4", + bundle: TraceBundle { + name: "r4", + fields: [ + TraceUInt { + location: TraceScalarId(205), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(206), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(207), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(208), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(209), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r5", + bundle: TraceBundle { + name: "r5", + fields: [ + TraceUInt { + location: TraceScalarId(210), + name: "addr", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(211), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(212), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(213), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(214), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<8>, + /* offset = 8 */ + en: Bool, + /* offset = 9 */ + clk: Clock, + #[hdl(flip)] /* offset = 10 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + ], + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 253>, + }, + StatePartIndex(1): TraceMem { + id: TraceMemoryId(1), + name: "rename_table_special_mem", + stride: 6, + element_type: TraceBundle { + name: "rename_table_special_mem", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 2, + stride: 6, + start: 0, + len: 2, + }, + name: "adj_value", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Duplex, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 2, + stride: 6, + start: 2, + len: 4, + }, + name: "value", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(215), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(216), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(217), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(218), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(219), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r1", + bundle: TraceBundle { + name: "r1", + fields: [ + TraceUInt { + location: TraceScalarId(220), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(221), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(222), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(223), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(224), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r2", + bundle: TraceBundle { + name: "r2", + fields: [ + TraceUInt { + location: TraceScalarId(225), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(226), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(227), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(228), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(229), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r3", + bundle: TraceBundle { + name: "r3", + fields: [ + TraceUInt { + location: TraceScalarId(230), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(231), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(232), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(233), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(234), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r4", + bundle: TraceBundle { + name: "r4", + fields: [ + TraceUInt { + location: TraceScalarId(235), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(236), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(237), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(238), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(239), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + TraceMemPort { + name: "r5", + bundle: TraceBundle { + name: "r5", + fields: [ + TraceUInt { + location: TraceScalarId(240), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(241), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(242), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceBundle { + name: "unit_num", + fields: [ + TraceUInt { + location: TraceScalarId(243), + name: "adj_value", + ty: UInt<2>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + flow: Source, + }, + TraceBundle { + name: "unit_out_reg", + fields: [ + TraceUInt { + location: TraceScalarId(244), + name: "value", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: Bundle { + /* offset = 0 */ + unit_num: Bundle { + /* offset = 0 */ + adj_value: UInt<2>, + }, + /* offset = 2 */ + unit_out_reg: Bundle { + /* offset = 0 */ + value: UInt<4>, + }, + }, + }, + }, + ], + array_type: Array}, unit_out_reg: Bundle {value: UInt<4>}}, 2>, + }, + }, trace_writers: [ Running( VcdWriter { @@ -15191,7 +106595,20 @@ Simulation { ], instant: 20 μs, clocks_triggered: [ - StatePartIndex(26), + StatePartIndex(33), + StatePartIndex(38), + StatePartIndex(43), + StatePartIndex(48), + StatePartIndex(53), + StatePartIndex(58), + StatePartIndex(63), + StatePartIndex(68), + StatePartIndex(73), + StatePartIndex(78), + StatePartIndex(83), + StatePartIndex(88), + StatePartIndex(228), + StatePartIndex(279), ], .. } \ No newline at end of file diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd index ba1dbe8..97da171 100644 --- a/crates/cpu/tests/expected/reg_alloc.vcd +++ b/crates/cpu/tests/expected/reg_alloc.vcd @@ -10,7 +10,7 @@ $scope struct \[0] $end $scope struct data $end $var string 1 # \$tag $end $scope struct HdlSome $end -$scope struct uop $end +$scope struct mop $end $var string 1 $ \$tag $end $scope struct AluBranch $end $var string 1 % \$tag $end @@ -18,117 +18,192 @@ $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end $var string 0 & prefix_pad $end -$var wire 8 ' dest $end -$scope struct src $end -$var wire 8 ( \[0] $end -$var wire 8 ) \[1] $end -$var wire 8 * \[2] $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 ' value $end $upscope $end -$var wire 25 + imm_low $end -$var wire 1 , imm_sign $end +$scope struct \[1] $end +$var wire 8 ( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 ) \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 * \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 + \[0] $end +$var wire 8 , \[1] $end +$var wire 8 - \[2] $end +$upscope $end +$var wire 25 . imm_low $end +$var wire 1 / imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 - output_integer_mode $end +$var string 1 0 output_integer_mode $end $upscope $end -$var wire 1 . invert_src0 $end -$var wire 1 / invert_carry_in $end -$var wire 1 0 invert_carry_out $end -$var wire 1 1 add_pc $end +$var wire 1 1 invert_src0 $end +$var wire 1 2 invert_carry_in $end +$var wire 1 3 invert_carry_out $end +$var wire 1 4 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 2 prefix_pad $end -$var wire 8 3 dest $end -$scope struct src $end -$var wire 8 4 \[0] $end -$var wire 8 5 \[1] $end -$var wire 8 6 \[2] $end +$var string 0 5 prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 6 value $end $upscope $end -$var wire 25 7 imm_low $end -$var wire 1 8 imm_sign $end +$scope struct \[1] $end +$var wire 8 7 value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 8 \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 9 \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 : \[0] $end +$var wire 8 ; \[1] $end +$var wire 8 < \[2] $end +$upscope $end +$var wire 25 = imm_low $end +$var wire 1 > imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 9 output_integer_mode $end +$var string 1 ? output_integer_mode $end $upscope $end -$var wire 1 : invert_src0 $end -$var wire 1 ; invert_carry_in $end -$var wire 1 < invert_carry_out $end -$var wire 1 = add_pc $end +$var wire 1 @ invert_src0 $end +$var wire 1 A invert_carry_in $end +$var wire 1 B invert_carry_out $end +$var wire 1 C add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 > prefix_pad $end -$var wire 8 ? dest $end -$scope struct src $end -$var wire 8 @ \[0] $end -$var wire 8 A \[1] $end -$var wire 8 B \[2] $end +$var string 0 D prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 E value $end $upscope $end -$var wire 25 C imm_low $end -$var wire 1 D imm_sign $end +$scope struct \[1] $end +$var wire 8 F value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 G \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 H \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 I \[0] $end +$var wire 8 J \[1] $end +$var wire 8 K \[2] $end +$upscope $end +$var wire 25 L imm_low $end +$var wire 1 M imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 E output_integer_mode $end +$var string 1 N output_integer_mode $end $upscope $end -$var wire 4 F lut $end +$var wire 4 O lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 G \$tag $end +$var string 1 P \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 H prefix_pad $end -$var wire 8 I dest $end -$scope struct src $end -$var wire 8 J \[0] $end -$var wire 8 K \[1] $end -$var wire 8 L \[2] $end +$var wire 1 Q prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 R value $end $upscope $end -$var wire 25 M imm_low $end -$var wire 1 N imm_sign $end +$scope struct \[1] $end +$var wire 8 S value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 T \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 U \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 V \[0] $end +$var wire 8 W \[1] $end +$var wire 8 X \[2] $end +$upscope $end +$var wire 25 Y imm_low $end +$var wire 1 Z imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 O prefix_pad $end -$var wire 8 P dest $end -$scope struct src $end -$var wire 8 Q \[0] $end -$var wire 8 R \[1] $end -$var wire 8 S \[2] $end +$var wire 1 [ prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 \ value $end $upscope $end -$var wire 25 T imm_low $end -$var wire 1 U imm_sign $end -$scope struct _phantom $end +$scope struct \[1] $end +$var wire 8 ] value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 ^ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 _ \$tag $end +$scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end -$scope struct LoadStore $end -$var string 1 V \$tag $end -$scope struct Load $end -$var wire 1 W prefix_pad $end -$var wire 8 X dest $end -$scope struct src $end -$var wire 8 Y \[0] $end -$var wire 8 Z \[1] $end -$var wire 8 [ \[2] $end -$upscope $end -$var wire 25 \ imm_low $end -$var wire 1 ] imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$scope struct Store $end -$var wire 1 ^ prefix_pad $end -$var wire 8 _ dest $end $scope struct src $end $var wire 8 ` \[0] $end $var wire 8 a \[1] $end @@ -141,69 +216,118 @@ $upscope $end $upscope $end $upscope $end $upscope $end -$var wire 1 e is_unrelated_pc $end -$var wire 64 f pc $end +$scope struct LoadStore $end +$var string 1 e \$tag $end +$scope struct Load $end +$var wire 1 f prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 g value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 h value $end $upscope $end $upscope $end -$var wire 1 g ready $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 i \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 j \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 k \[0] $end +$var wire 8 l \[1] $end +$var wire 8 m \[2] $end +$upscope $end +$var wire 25 n imm_low $end +$var wire 1 o imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 p prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 q value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 r value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 s \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 t \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 u \[0] $end +$var wire 8 v \[1] $end +$var wire 8 w \[2] $end +$upscope $end +$var wire 25 x imm_low $end +$var wire 1 y imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 z is_unrelated_pc $end +$var wire 64 { pc $end +$upscope $end +$upscope $end +$var wire 1 | ready $end $upscope $end $scope struct \[1] $end $scope struct data $end -$var string 1 h \$tag $end +$var string 1 } \$tag $end $scope struct HdlSome $end -$scope struct uop $end -$var string 1 i \$tag $end +$scope struct mop $end +$var string 1 ~ \$tag $end $scope struct AluBranch $end -$var string 1 j \$tag $end +$var string 1 !" \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 k prefix_pad $end -$var wire 8 l dest $end -$scope struct src $end -$var wire 8 m \[0] $end -$var wire 8 n \[1] $end -$var wire 8 o \[2] $end +$var string 0 "" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 #" value $end $upscope $end -$var wire 25 p imm_low $end -$var wire 1 q imm_sign $end -$scope struct _phantom $end +$scope struct \[1] $end +$var wire 8 $" value $end $upscope $end $upscope $end -$var string 1 r output_integer_mode $end -$upscope $end -$var wire 1 s invert_src0 $end -$var wire 1 t invert_carry_in $end -$var wire 1 u invert_carry_out $end -$var wire 1 v add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 w prefix_pad $end -$var wire 8 x dest $end -$scope struct src $end -$var wire 8 y \[0] $end -$var wire 8 z \[1] $end -$var wire 8 { \[2] $end -$upscope $end -$var wire 25 | imm_low $end -$var wire 1 } imm_sign $end -$scope struct _phantom $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 %" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 &" \$tag $end +$scope struct HdlSome $end $upscope $end $upscope $end -$var string 1 ~ output_integer_mode $end $upscope $end -$var wire 1 !" invert_src0 $end -$var wire 1 "" invert_carry_in $end -$var wire 1 #" invert_carry_out $end -$var wire 1 $" add_pc $end $upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 %" prefix_pad $end -$var wire 8 &" dest $end $scope struct src $end $var wire 8 '" \[0] $end $var wire 8 (" \[1] $end @@ -216,303 +340,6752 @@ $upscope $end $upscope $end $var string 1 ," output_integer_mode $end $upscope $end -$var wire 4 -" lut $end +$var wire 1 -" invert_src0 $end +$var wire 1 ." invert_carry_in $end +$var wire 1 /" invert_carry_out $end +$var wire 1 0" add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 1" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 2" value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 3" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 4" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 5" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 6" \[0] $end +$var wire 8 7" \[1] $end +$var wire 8 8" \[2] $end +$upscope $end +$var wire 25 9" imm_low $end +$var wire 1 :" imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ;" output_integer_mode $end +$upscope $end +$var wire 1 <" invert_src0 $end +$var wire 1 =" invert_carry_in $end +$var wire 1 >" invert_carry_out $end +$var wire 1 ?" add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 @" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 A" value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 B" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 C" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 D" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 E" \[0] $end +$var wire 8 F" \[1] $end +$var wire 8 G" \[2] $end +$upscope $end +$var wire 25 H" imm_low $end +$var wire 1 I" imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 J" output_integer_mode $end +$upscope $end +$var wire 4 K" lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 ." \$tag $end +$var string 1 L" \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 /" prefix_pad $end -$var wire 8 0" dest $end -$scope struct src $end -$var wire 8 1" \[0] $end -$var wire 8 2" \[1] $end -$var wire 8 3" \[2] $end +$var wire 1 M" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 N" value $end $upscope $end -$var wire 25 4" imm_low $end -$var wire 1 5" imm_sign $end +$scope struct \[1] $end +$var wire 8 O" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 P" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Q" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 R" \[0] $end +$var wire 8 S" \[1] $end +$var wire 8 T" \[2] $end +$upscope $end +$var wire 25 U" imm_low $end +$var wire 1 V" imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 6" prefix_pad $end -$var wire 8 7" dest $end -$scope struct src $end -$var wire 8 8" \[0] $end -$var wire 8 9" \[1] $end -$var wire 8 :" \[2] $end +$var wire 1 W" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 X" value $end $upscope $end -$var wire 25 ;" imm_low $end -$var wire 1 <" imm_sign $end +$scope struct \[1] $end +$var wire 8 Y" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 Z" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 [" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 \" \[0] $end +$var wire 8 ]" \[1] $end +$var wire 8 ^" \[2] $end +$upscope $end +$var wire 25 _" imm_low $end +$var wire 1 `" imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct LoadStore $end -$var string 1 =" \$tag $end +$var string 1 a" \$tag $end $scope struct Load $end -$var wire 1 >" prefix_pad $end -$var wire 8 ?" dest $end -$scope struct src $end -$var wire 8 @" \[0] $end -$var wire 8 A" \[1] $end -$var wire 8 B" \[2] $end +$var wire 1 b" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 c" value $end $upscope $end -$var wire 25 C" imm_low $end -$var wire 1 D" imm_sign $end +$scope struct \[1] $end +$var wire 8 d" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 e" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 f" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 g" \[0] $end +$var wire 8 h" \[1] $end +$var wire 8 i" \[2] $end +$upscope $end +$var wire 25 j" imm_low $end +$var wire 1 k" imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 E" prefix_pad $end -$var wire 8 F" dest $end -$scope struct src $end -$var wire 8 G" \[0] $end -$var wire 8 H" \[1] $end -$var wire 8 I" \[2] $end +$var wire 1 l" prefix_pad $end +$scope struct dest $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 m" value $end $upscope $end -$var wire 25 J" imm_low $end -$var wire 1 K" imm_sign $end +$scope struct \[1] $end +$var wire 8 n" value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 o" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 p" \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct src $end +$var wire 8 q" \[0] $end +$var wire 8 r" \[1] $end +$var wire 8 s" \[2] $end +$upscope $end +$var wire 25 t" imm_low $end +$var wire 1 u" imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end -$var wire 1 L" is_unrelated_pc $end -$var wire 64 M" pc $end +$var wire 1 v" is_unrelated_pc $end +$var wire 64 w" pc $end $upscope $end $upscope $end -$var wire 1 N" ready $end +$var wire 1 x" ready $end $upscope $end $upscope $end $scope struct fetch_decode_special_op $end $scope struct data $end -$var string 1 O" \$tag $end +$var string 1 y" \$tag $end $scope struct HdlSome $end -$var string 1 P" \$tag $end +$var string 1 z" \$tag $end $scope struct Trap $end $upscope $end $upscope $end $upscope $end -$var wire 1 Q" ready $end +$var wire 1 {" ready $end +$upscope $end +$upscope $end +$scope struct rename_table_normal_mem $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 p0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 S3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 q0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 T3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 r0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 U3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 s0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 V3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 t0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 W3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 u0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 X3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 v0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Y3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 w0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Z3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 x0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 [3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 y0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 \3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 z0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ]3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 {0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ^3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 |0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 _3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 }0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 `3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ~0 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 a3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 !1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 b3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[16] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 "1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 c3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[17] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 #1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 d3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[18] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 $1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 e3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[19] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 %1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 f3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[20] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 &1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 g3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[21] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 '1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 h3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[22] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 (1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 i3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[23] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 )1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 j3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[24] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 *1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 k3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[25] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 +1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 l3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[26] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ,1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 m3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[27] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 -1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 n3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[28] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 .1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 o3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[29] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 /1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 p3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[30] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 01 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 q3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[31] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 11 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 r3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[32] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 21 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 s3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[33] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 31 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 t3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[34] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 41 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 u3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[35] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 51 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 v3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[36] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 61 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 w3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[37] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 71 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 x3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[38] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 81 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 y3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[39] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 91 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 z3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[40] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 :1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 {3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[41] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ;1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 |3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[42] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 <1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 }3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[43] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 =1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ~3 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[44] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 >1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 !4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[45] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ?1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 "4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[46] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 @1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 #4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[47] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 A1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 $4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[48] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 B1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 %4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[49] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 C1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 &4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[50] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 D1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 '4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[51] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 E1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 (4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[52] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 F1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 )4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[53] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 G1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 *4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[54] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 H1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 +4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[55] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 I1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ,4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[56] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 J1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 -4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[57] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 K1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 .4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[58] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 L1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 /4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[59] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 M1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 04 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[60] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 N1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 14 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[61] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 O1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 24 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[62] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 P1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 34 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[63] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Q1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 44 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[64] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 R1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 54 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[65] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 S1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 64 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[66] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 T1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 74 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[67] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 U1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 84 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[68] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 V1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 94 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[69] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 W1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 :4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[70] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 X1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ;4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[71] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Y1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 <4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[72] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Z1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 =4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[73] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 [1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 >4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[74] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 \1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ?4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[75] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ]1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 @4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[76] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ^1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 A4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[77] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 _1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 B4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[78] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 `1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 C4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[79] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 a1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 D4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[80] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 b1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 E4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[81] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 c1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 F4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[82] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 d1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 G4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[83] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 e1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 H4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[84] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 f1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 I4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[85] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 g1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 J4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[86] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 h1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 K4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[87] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 i1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 L4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[88] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 j1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 M4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[89] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 k1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 N4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[90] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 l1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 O4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[91] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 m1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 P4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[92] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 n1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Q4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[93] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 o1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 R4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[94] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 p1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 S4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[95] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 q1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 T4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[96] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 r1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 U4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[97] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 s1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 V4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[98] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 t1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 W4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[99] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 u1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 X4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[100] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 v1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Y4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[101] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 w1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Z4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[102] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 x1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 [4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[103] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 y1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 \4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[104] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 z1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ]4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[105] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 {1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ^4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[106] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 |1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 _4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[107] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 }1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 `4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[108] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ~1 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 a4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[109] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 !2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 b4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[110] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 "2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 c4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[111] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 #2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 d4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[112] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 $2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 e4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[113] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 %2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 f4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[114] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 &2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 g4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[115] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 '2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 h4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[116] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 (2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 i4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[117] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 )2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 j4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[118] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 *2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 k4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[119] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 +2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 l4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[120] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ,2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 m4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[121] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 -2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 n4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[122] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 .2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 o4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[123] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 /2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 p4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[124] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 02 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 q4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[125] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 12 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 r4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[126] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 22 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 s4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[127] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 32 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 t4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[128] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 42 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 u4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[129] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 52 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 v4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[130] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 62 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 w4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[131] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 72 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 x4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[132] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 82 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 y4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[133] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 92 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 z4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[134] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 :2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 {4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[135] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ;2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 |4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[136] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 <2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 }4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[137] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 =2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ~4 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[138] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 >2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 !5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[139] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ?2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 "5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[140] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 @2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 #5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[141] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 A2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 $5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[142] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 B2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 %5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[143] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 C2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 &5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[144] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 D2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 '5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[145] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 E2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 (5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[146] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 F2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 )5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[147] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 G2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 *5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[148] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 H2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 +5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[149] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 I2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ,5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[150] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 J2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 -5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[151] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 K2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 .5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[152] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 L2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 /5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[153] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 M2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 05 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[154] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 N2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 15 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[155] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 O2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 25 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[156] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 P2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 35 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[157] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Q2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 45 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[158] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 R2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 55 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[159] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 S2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 65 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[160] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 T2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 75 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[161] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 U2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 85 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[162] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 V2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 95 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[163] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 W2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 :5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[164] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 X2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ;5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[165] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Y2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 <5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[166] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Z2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 =5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[167] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 [2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 >5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[168] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 \2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ?5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[169] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ]2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 @5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[170] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ^2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 A5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[171] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 _2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 B5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[172] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 `2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 C5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[173] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 a2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 D5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[174] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 b2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 E5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[175] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 c2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 F5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[176] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 d2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 G5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[177] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 e2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 H5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[178] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 f2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 I5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[179] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 g2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 J5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[180] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 h2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 K5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[181] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 i2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 L5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[182] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 j2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 M5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[183] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 k2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 N5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[184] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 l2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 O5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[185] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 m2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 P5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[186] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 n2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Q5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[187] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 o2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 R5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[188] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 p2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 S5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[189] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 q2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 T5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[190] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 r2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 U5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[191] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 s2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 V5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[192] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 t2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 W5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[193] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 u2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 X5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[194] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 v2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Y5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[195] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 w2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 Z5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[196] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 x2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 [5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[197] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 y2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 \5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[198] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 z2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ]5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[199] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 {2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ^5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[200] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 |2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 _5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[201] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 }2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 `5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[202] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ~2 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 a5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[203] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 !3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 b5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[204] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 "3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 c5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[205] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 #3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 d5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[206] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 $3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 e5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[207] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 %3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 f5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[208] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 &3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 g5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[209] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 '3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 h5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[210] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 (3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 i5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[211] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 )3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 j5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[212] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 *3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 k5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[213] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 +3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 l5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[214] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ,3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 m5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[215] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 -3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 n5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[216] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 .3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 o5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[217] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 /3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 p5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[218] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 03 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 q5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[219] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 13 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 r5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[220] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 23 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 s5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[221] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 33 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 t5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[222] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 43 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 u5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[223] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 53 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 v5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[224] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 63 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 w5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[225] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 73 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 x5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[226] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 83 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 y5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[227] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 93 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 z5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[228] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 :3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 {5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[229] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ;3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 |5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[230] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 <3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 }5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[231] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 =3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ~5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[232] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 >3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 !6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[233] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 ?3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 "6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[234] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 @3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 #6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[235] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 A3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 $6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[236] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 B3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 %6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[237] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 C3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 &6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[238] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 D3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 '6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[239] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 E3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 (6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[240] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 F3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 )6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[241] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 G3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 *6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[242] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 H3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 +6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[243] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 I3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 ,6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[244] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 J3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 -6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[245] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 K3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 .6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[246] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 L3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 /6 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[247] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 M3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 06 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[248] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 N3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 16 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[249] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 O3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 26 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[250] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 P3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 36 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[251] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 Q3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 46 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[252] $end +$scope struct rename_table_normal_mem $end +$scope struct unit_num $end +$var reg 2 R3 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 56 value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 8 |" addr $end +$var wire 1 }" en $end +$var wire 1 ~" clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 !# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 "# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r1 $end +$var wire 8 ## addr $end +$var wire 1 $# en $end +$var wire 1 %# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 &# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 '# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r2 $end +$var wire 8 (# addr $end +$var wire 1 )# en $end +$var wire 1 *# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 +# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ,# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r3 $end +$var wire 8 -# addr $end +$var wire 1 .# en $end +$var wire 1 /# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 0# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 1# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r4 $end +$var wire 8 2# addr $end +$var wire 1 3# en $end +$var wire 1 4# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 5# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 6# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r5 $end +$var wire 8 7# addr $end +$var wire 1 8# en $end +$var wire 1 9# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 :# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ;# value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_special_mem $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct rename_table_special_mem $end +$scope struct unit_num $end +$var reg 2 66 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 86 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct rename_table_special_mem $end +$scope struct unit_num $end +$var reg 2 76 adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var reg 4 96 value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 <# addr $end +$var wire 1 =# en $end +$var wire 1 ># clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 ?# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 @# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r1 $end +$var wire 1 A# addr $end +$var wire 1 B# en $end +$var wire 1 C# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 D# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 E# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r2 $end +$var wire 1 F# addr $end +$var wire 1 G# en $end +$var wire 1 H# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 I# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 J# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r3 $end +$var wire 1 K# addr $end +$var wire 1 L# en $end +$var wire 1 M# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 N# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 O# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r4 $end +$var wire 1 P# addr $end +$var wire 1 Q# en $end +$var wire 1 R# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 S# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 T# value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r5 $end +$var wire 1 U# addr $end +$var wire 1 V# en $end +$var wire 1 W# clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 X# adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 Y# value $end +$upscope $end +$upscope $end $upscope $end $upscope $end $scope struct available_units $end $scope struct \[0] $end -$var wire 1 R" \[0] $end +$var wire 1 Z# \[0] $end +$var wire 1 [# \[1] $end $upscope $end $scope struct \[1] $end -$var wire 1 S" \[0] $end +$var wire 1 \# \[0] $end +$var wire 1 ]# \[1] $end $upscope $end $upscope $end -$scope struct selected_unit_nums $end +$scope struct selected_unit_indexes $end $scope struct \[0] $end -$var string 1 T" \$tag $end +$var string 1 ^# \$tag $end +$var wire 2 _# HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 `# \$tag $end +$var wire 2 a# HdlSome $end +$upscope $end +$upscope $end +$scope struct renamed_mops $end +$scope struct \[0] $end +$var string 1 b# \$tag $end $scope struct HdlSome $end -$var wire 1 U" value $end +$var string 1 c# \$tag $end +$scope struct AluBranch $end +$var string 1 d# \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 e# prefix_pad $end +$scope struct dest $end +$var wire 4 f# value $end +$upscope $end +$scope struct src $end +$var wire 6 g# \[0] $end +$var wire 6 h# \[1] $end +$var wire 6 i# \[2] $end +$upscope $end +$var wire 25 j# imm_low $end +$var wire 1 k# imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 l# output_integer_mode $end +$upscope $end +$var wire 1 m# invert_src0 $end +$var wire 1 n# invert_carry_in $end +$var wire 1 o# invert_carry_out $end +$var wire 1 p# add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 q# prefix_pad $end +$scope struct dest $end +$var wire 4 r# value $end +$upscope $end +$scope struct src $end +$var wire 6 s# \[0] $end +$var wire 6 t# \[1] $end +$var wire 6 u# \[2] $end +$upscope $end +$var wire 25 v# imm_low $end +$var wire 1 w# imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 x# output_integer_mode $end +$upscope $end +$var wire 1 y# invert_src0 $end +$var wire 1 z# invert_carry_in $end +$var wire 1 {# invert_carry_out $end +$var wire 1 |# add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }# prefix_pad $end +$scope struct dest $end +$var wire 4 ~# value $end +$upscope $end +$scope struct src $end +$var wire 6 !$ \[0] $end +$var wire 6 "$ \[1] $end +$var wire 6 #$ \[2] $end +$upscope $end +$var wire 25 $$ imm_low $end +$var wire 1 %$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &$ output_integer_mode $end +$upscope $end +$var wire 4 '$ lut $end +$upscope $end +$upscope $end +$scope struct L2RegisterFile $end +$var string 1 ($ \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 )$ prefix_pad $end +$scope struct dest $end +$var wire 4 *$ value $end +$upscope $end +$scope struct src $end +$var wire 6 +$ \[0] $end +$var wire 6 ,$ \[1] $end +$var wire 6 -$ \[2] $end +$upscope $end +$var wire 25 .$ imm_low $end +$var wire 1 /$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 0$ prefix_pad $end +$scope struct dest $end +$var wire 4 1$ value $end +$upscope $end +$scope struct src $end +$var wire 6 2$ \[0] $end +$var wire 6 3$ \[1] $end +$var wire 6 4$ \[2] $end +$upscope $end +$var wire 25 5$ imm_low $end +$var wire 1 6$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct LoadStore $end +$var string 1 7$ \$tag $end +$scope struct Load $end +$var wire 1 8$ prefix_pad $end +$scope struct dest $end +$var wire 4 9$ value $end +$upscope $end +$scope struct src $end +$var wire 6 :$ \[0] $end +$var wire 6 ;$ \[1] $end +$var wire 6 <$ \[2] $end +$upscope $end +$var wire 25 =$ imm_low $end +$var wire 1 >$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 ?$ prefix_pad $end +$scope struct dest $end +$var wire 4 @$ value $end +$upscope $end +$scope struct src $end +$var wire 6 A$ \[0] $end +$var wire 6 B$ \[1] $end +$var wire 6 C$ \[2] $end +$upscope $end +$var wire 25 D$ imm_low $end +$var wire 1 E$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 V" \$tag $end +$var string 1 F$ \$tag $end $scope struct HdlSome $end -$var wire 1 W" value $end +$var string 1 G$ \$tag $end +$scope struct AluBranch $end +$var string 1 H$ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 I$ prefix_pad $end +$scope struct dest $end +$var wire 4 J$ value $end +$upscope $end +$scope struct src $end +$var wire 6 K$ \[0] $end +$var wire 6 L$ \[1] $end +$var wire 6 M$ \[2] $end +$upscope $end +$var wire 25 N$ imm_low $end +$var wire 1 O$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 P$ output_integer_mode $end +$upscope $end +$var wire 1 Q$ invert_src0 $end +$var wire 1 R$ invert_carry_in $end +$var wire 1 S$ invert_carry_out $end +$var wire 1 T$ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 U$ prefix_pad $end +$scope struct dest $end +$var wire 4 V$ value $end +$upscope $end +$scope struct src $end +$var wire 6 W$ \[0] $end +$var wire 6 X$ \[1] $end +$var wire 6 Y$ \[2] $end +$upscope $end +$var wire 25 Z$ imm_low $end +$var wire 1 [$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 \$ output_integer_mode $end +$upscope $end +$var wire 1 ]$ invert_src0 $end +$var wire 1 ^$ invert_carry_in $end +$var wire 1 _$ invert_carry_out $end +$var wire 1 `$ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 a$ prefix_pad $end +$scope struct dest $end +$var wire 4 b$ value $end +$upscope $end +$scope struct src $end +$var wire 6 c$ \[0] $end +$var wire 6 d$ \[1] $end +$var wire 6 e$ \[2] $end +$upscope $end +$var wire 25 f$ imm_low $end +$var wire 1 g$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 h$ output_integer_mode $end +$upscope $end +$var wire 4 i$ lut $end +$upscope $end +$upscope $end +$scope struct L2RegisterFile $end +$var string 1 j$ \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 k$ prefix_pad $end +$scope struct dest $end +$var wire 4 l$ value $end +$upscope $end +$scope struct src $end +$var wire 6 m$ \[0] $end +$var wire 6 n$ \[1] $end +$var wire 6 o$ \[2] $end +$upscope $end +$var wire 25 p$ imm_low $end +$var wire 1 q$ imm_sign $end +$scope struct _phantom $end $upscope $end $upscope $end $upscope $end -$var string 1 X" unit_kind $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 r$ prefix_pad $end +$scope struct dest $end +$var wire 4 s$ value $end +$upscope $end +$scope struct src $end +$var wire 6 t$ \[0] $end +$var wire 6 u$ \[1] $end +$var wire 6 v$ \[2] $end +$upscope $end +$var wire 25 w$ imm_low $end +$var wire 1 x$ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct LoadStore $end +$var string 1 y$ \$tag $end +$scope struct Load $end +$var wire 1 z$ prefix_pad $end +$scope struct dest $end +$var wire 4 {$ value $end +$upscope $end +$scope struct src $end +$var wire 6 |$ \[0] $end +$var wire 6 }$ \[1] $end +$var wire 6 ~$ \[2] $end +$upscope $end +$var wire 25 !% imm_low $end +$var wire 1 "% imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 #% prefix_pad $end +$scope struct dest $end +$var wire 4 $% value $end +$upscope $end +$scope struct src $end +$var wire 6 %% \[0] $end +$var wire 6 &% \[1] $end +$var wire 6 '% \[2] $end +$upscope $end +$var wire 25 (% imm_low $end +$var wire 1 )% imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct renamed_mops_out_reg $end +$scope struct \[0] $end +$var string 1 *% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 +% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ,% value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 -% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 .% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 /% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_normal_0_src_0 $end +$scope struct addr $end +$var wire 8 0% value $end +$upscope $end +$scope struct data $end +$var string 1 1% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 2% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 3% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_normal_0_src_1 $end +$scope struct addr $end +$var wire 8 4% value $end +$upscope $end +$scope struct data $end +$var string 1 5% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 6% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 7% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_normal_0_src_2 $end +$scope struct addr $end +$var wire 8 8% value $end +$upscope $end +$scope struct data $end +$var string 1 9% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 :% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ;% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_special_0_src_0 $end +$scope struct addr $end +$var wire 8 <% value $end +$upscope $end +$scope struct data $end +$var string 1 =% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 >% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ?% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_special_0_src_1 $end +$scope struct addr $end +$var wire 8 @% value $end +$upscope $end +$scope struct data $end +$var string 1 A% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 B% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 C% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_special_0_src_2 $end +$scope struct addr $end +$var wire 8 D% value $end +$upscope $end +$scope struct data $end +$var string 1 E% \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 F% adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 G% value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 H% unit_kind $end $scope struct available_units_for_kind $end -$var wire 1 Y" \[0] $end +$var wire 1 I% \[0] $end +$var wire 1 J% \[1] $end $upscope $end -$scope struct selected_unit_leaf_0_0 $end -$var string 1 Z" \$tag $end +$scope struct dest_reg $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 K% value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 L% value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 M% \$tag $end $scope struct HdlSome $end -$var wire 1 [" value $end $upscope $end $upscope $end -$scope struct unit_num_0_0 $end -$var wire 1 \" value $end +$scope struct \[1] $end +$var string 1 N% \$tag $end +$scope struct HdlSome $end $upscope $end -$var string 1 ]" unit_kind_2 $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_2 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 O% value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 P% value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 Q% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 R% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_3 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 S% value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 T% value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 U% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 V% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_4 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 W% value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 X% value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 Y% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Z% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mapped_regs $end +$var string 1 [% \$tag $end +$scope struct AluBranch $end +$var string 1 \% \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ]% prefix_pad $end +$scope struct dest $end +$var wire 4 ^% value $end +$upscope $end +$scope struct src $end +$var wire 6 _% \[0] $end +$var wire 6 `% \[1] $end +$var wire 6 a% \[2] $end +$upscope $end +$var wire 25 b% imm_low $end +$var wire 1 c% imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 d% output_integer_mode $end +$upscope $end +$var wire 1 e% invert_src0 $end +$var wire 1 f% invert_carry_in $end +$var wire 1 g% invert_carry_out $end +$var wire 1 h% add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 i% prefix_pad $end +$scope struct dest $end +$var wire 4 j% value $end +$upscope $end +$scope struct src $end +$var wire 6 k% \[0] $end +$var wire 6 l% \[1] $end +$var wire 6 m% \[2] $end +$upscope $end +$var wire 25 n% imm_low $end +$var wire 1 o% imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 p% output_integer_mode $end +$upscope $end +$var wire 1 q% invert_src0 $end +$var wire 1 r% invert_carry_in $end +$var wire 1 s% invert_carry_out $end +$var wire 1 t% add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 u% prefix_pad $end +$scope struct dest $end +$var wire 4 v% value $end +$upscope $end +$scope struct src $end +$var wire 6 w% \[0] $end +$var wire 6 x% \[1] $end +$var wire 6 y% \[2] $end +$upscope $end +$var wire 25 z% imm_low $end +$var wire 1 {% imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 |% output_integer_mode $end +$upscope $end +$var wire 4 }% lut $end +$upscope $end +$upscope $end +$scope struct L2RegisterFile $end +$var string 1 ~% \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 !& prefix_pad $end +$scope struct dest $end +$var wire 4 "& value $end +$upscope $end +$scope struct src $end +$var wire 6 #& \[0] $end +$var wire 6 $& \[1] $end +$var wire 6 %& \[2] $end +$upscope $end +$var wire 25 && imm_low $end +$var wire 1 '& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 (& prefix_pad $end +$scope struct dest $end +$var wire 4 )& value $end +$upscope $end +$scope struct src $end +$var wire 6 *& \[0] $end +$var wire 6 +& \[1] $end +$var wire 6 ,& \[2] $end +$upscope $end +$var wire 25 -& imm_low $end +$var wire 1 .& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct LoadStore $end +$var string 1 /& \$tag $end +$scope struct Load $end +$var wire 1 0& prefix_pad $end +$scope struct dest $end +$var wire 4 1& value $end +$upscope $end +$scope struct src $end +$var wire 6 2& \[0] $end +$var wire 6 3& \[1] $end +$var wire 6 4& \[2] $end +$upscope $end +$var wire 25 5& imm_low $end +$var wire 1 6& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 7& prefix_pad $end +$scope struct dest $end +$var wire 4 8& value $end +$upscope $end +$scope struct src $end +$var wire 6 9& \[0] $end +$var wire 6 :& \[1] $end +$var wire 6 ;& \[2] $end +$upscope $end +$var wire 25 <& imm_low $end +$var wire 1 =& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mapped_regs_2 $end +$var string 1 >& \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ?& prefix_pad $end +$scope struct dest $end +$var wire 4 @& value $end +$upscope $end +$scope struct src $end +$var wire 6 A& \[0] $end +$var wire 6 B& \[1] $end +$var wire 6 C& \[2] $end +$upscope $end +$var wire 25 D& imm_low $end +$var wire 1 E& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 F& output_integer_mode $end +$upscope $end +$var wire 1 G& invert_src0 $end +$var wire 1 H& invert_carry_in $end +$var wire 1 I& invert_carry_out $end +$var wire 1 J& add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 K& prefix_pad $end +$scope struct dest $end +$var wire 4 L& value $end +$upscope $end +$scope struct src $end +$var wire 6 M& \[0] $end +$var wire 6 N& \[1] $end +$var wire 6 O& \[2] $end +$upscope $end +$var wire 25 P& imm_low $end +$var wire 1 Q& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 R& output_integer_mode $end +$upscope $end +$var wire 1 S& invert_src0 $end +$var wire 1 T& invert_carry_in $end +$var wire 1 U& invert_carry_out $end +$var wire 1 V& add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 W& prefix_pad $end +$scope struct dest $end +$var wire 4 X& value $end +$upscope $end +$scope struct src $end +$var wire 6 Y& \[0] $end +$var wire 6 Z& \[1] $end +$var wire 6 [& \[2] $end +$upscope $end +$var wire 25 \& imm_low $end +$var wire 1 ]& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ^& output_integer_mode $end +$upscope $end +$var wire 4 _& lut $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_0 $end +$scope struct unit_num $end +$var wire 2 `& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 a& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_1 $end +$scope struct unit_num $end +$var wire 2 b& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 c& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_2 $end +$scope struct unit_num $end +$var wire 2 d& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 e& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_0_2 $end +$scope struct unit_num $end +$var wire 2 f& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 g& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_1_2 $end +$scope struct unit_num $end +$var wire 2 h& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 i& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_0_3 $end +$scope struct unit_num $end +$var wire 2 j& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 k& value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_1_3 $end +$scope struct unit_num $end +$var wire 2 l& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 m& value $end +$upscope $end +$upscope $end +$scope struct mapped_regs_3 $end +$var string 1 n& \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 o& prefix_pad $end +$scope struct dest $end +$var wire 4 p& value $end +$upscope $end +$scope struct src $end +$var wire 6 q& \[0] $end +$var wire 6 r& \[1] $end +$var wire 6 s& \[2] $end +$upscope $end +$var wire 25 t& imm_low $end +$var wire 1 u& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 v& prefix_pad $end +$scope struct dest $end +$var wire 4 w& value $end +$upscope $end +$scope struct src $end +$var wire 6 x& \[0] $end +$var wire 6 y& \[1] $end +$var wire 6 z& \[2] $end +$upscope $end +$var wire 25 {& imm_low $end +$var wire 1 |& imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_0_4 $end +$scope struct unit_num $end +$var wire 2 }& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 ~& value $end +$upscope $end +$upscope $end +$scope struct mapped_regs_4 $end +$var string 1 !' \$tag $end +$scope struct Load $end +$var wire 1 "' prefix_pad $end +$scope struct dest $end +$var wire 4 #' value $end +$upscope $end +$scope struct src $end +$var wire 6 $' \[0] $end +$var wire 6 %' \[1] $end +$var wire 6 &' \[2] $end +$upscope $end +$var wire 25 '' imm_low $end +$var wire 1 (' imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 )' prefix_pad $end +$scope struct dest $end +$var wire 4 *' value $end +$upscope $end +$scope struct src $end +$var wire 6 +' \[0] $end +$var wire 6 ,' \[1] $end +$var wire 6 -' \[2] $end +$upscope $end +$var wire 25 .' imm_low $end +$var wire 1 /' imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_0_0_5 $end +$scope struct unit_num $end +$var wire 2 0' adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 1' value $end +$upscope $end +$upscope $end +$scope struct selected_unit_index_leaf_0_0 $end +$var string 1 2' \$tag $end +$var wire 2 3' HdlSome $end +$upscope $end +$var wire 2 4' unit_index_0_0 $end +$scope struct selected_unit_index_leaf_0_1 $end +$var string 1 5' \$tag $end +$var wire 2 6' HdlSome $end +$upscope $end +$var wire 2 7' unit_index_0_1 $end +$scope struct selected_unit_index_node_0_0 $end +$var string 1 8' \$tag $end +$var wire 2 9' HdlSome $end +$upscope $end +$scope struct rename_table_normal_1_src_0 $end +$scope struct addr $end +$var wire 8 :' value $end +$upscope $end +$scope struct data $end +$var string 1 ;' \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 <' adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 =' value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_5 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 >' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 ?' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 @' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 A' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_6 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 B' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 C' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 D' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 E' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_7 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 F' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 G' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 H' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 I' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_8 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 J' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 K' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 L' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 M' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg $end +$var wire 8 N' value $end +$upscope $end +$scope struct flag_reg_2 $end +$var wire 8 O' value $end +$upscope $end +$scope struct rename_table_normal_1_src_1 $end +$scope struct addr $end +$var wire 8 P' value $end +$upscope $end +$scope struct data $end +$var string 1 Q' \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 R' adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 S' value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_9 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 T' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 U' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 V' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 W' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_10 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 X' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 Y' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 Z' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 [' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_11 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 \' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 ]' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 ^' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 _' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_12 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 `' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 a' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 b' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 c' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg_3 $end +$var wire 8 d' value $end +$upscope $end +$scope struct flag_reg_4 $end +$var wire 8 e' value $end +$upscope $end +$scope struct rename_table_normal_1_src_2 $end +$scope struct addr $end +$var wire 8 f' value $end +$upscope $end +$scope struct data $end +$var string 1 g' \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 h' adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 i' value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_13 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 j' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 k' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 l' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 m' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_14 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 n' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 o' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 p' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 q' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_15 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 r' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 s' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 t' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 u' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_16 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 v' value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 w' value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 x' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 y' \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg_5 $end +$var wire 8 z' value $end +$upscope $end +$scope struct flag_reg_6 $end +$var wire 8 {' value $end +$upscope $end +$scope struct rename_table_special_1_src_0 $end +$scope struct addr $end +$var wire 8 |' value $end +$upscope $end +$scope struct data $end +$var string 1 }' \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 ~' adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 !( value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_17 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 "( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 #( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 $( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 %( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_18 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 &( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 '( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 (( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 )( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_19 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 *( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 +( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 ,( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 -( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_20 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 .( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 /( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 0( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 1( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg_7 $end +$var wire 8 2( value $end +$upscope $end +$scope struct flag_reg_8 $end +$var wire 8 3( value $end +$upscope $end +$scope struct rename_table_special_1_src_1 $end +$scope struct addr $end +$var wire 8 4( value $end +$upscope $end +$scope struct data $end +$var string 1 5( \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 6( adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 7( value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_21 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 8( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 9( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 :( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ;( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_22 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 <( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 =( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 >( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ?( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_23 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 @( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 A( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 B( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 C( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_24 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 D( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 E( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 F( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 G( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg_9 $end +$var wire 8 H( value $end +$upscope $end +$scope struct flag_reg_10 $end +$var wire 8 I( value $end +$upscope $end +$scope struct rename_table_special_1_src_2 $end +$scope struct addr $end +$var wire 8 J( value $end +$upscope $end +$scope struct data $end +$var string 1 K( \$tag $end +$scope struct HdlSome $end +$scope struct unit_num $end +$var wire 2 L( adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 M( value $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_25 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 N( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 O( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 P( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Q( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_26 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 R( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 S( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 T( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 U( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_27 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 V( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 W( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 X( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Y( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_28 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 Z( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 [( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 \( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ]( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct flag_reg_11 $end +$var wire 8 ^( value $end +$upscope $end +$scope struct flag_reg_12 $end +$var wire 8 _( value $end +$upscope $end +$var string 1 `( unit_kind_2 $end $scope struct available_units_for_kind_2 $end -$var wire 1 ^" \[0] $end +$var wire 1 a( \[0] $end +$var wire 1 b( \[1] $end $upscope $end -$scope struct selected_unit_leaf_1_0 $end -$var string 1 _" \$tag $end +$scope struct dest_reg_29 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 c( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 d( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 e( \$tag $end $scope struct HdlSome $end -$var wire 1 `" value $end $upscope $end $upscope $end -$scope struct unit_num_1_0 $end -$var wire 1 a" value $end +$scope struct \[1] $end +$var string 1 f( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_30 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 g( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 h( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 i( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 j( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_31 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 k( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 l( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 m( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 n( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_32 $end +$scope struct normal_regs $end +$scope struct \[0] $end +$var wire 8 o( value $end +$upscope $end +$scope struct \[1] $end +$var wire 8 p( value $end +$upscope $end +$upscope $end +$scope struct flag_regs $end +$scope struct \[0] $end +$var string 1 q( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 r( \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mapped_regs_5 $end +$var string 1 s( \$tag $end +$scope struct AluBranch $end +$var string 1 t( \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 u( prefix_pad $end +$scope struct dest $end +$var wire 4 v( value $end +$upscope $end +$scope struct src $end +$var wire 6 w( \[0] $end +$var wire 6 x( \[1] $end +$var wire 6 y( \[2] $end +$upscope $end +$var wire 25 z( imm_low $end +$var wire 1 {( imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 |( output_integer_mode $end +$upscope $end +$var wire 1 }( invert_src0 $end +$var wire 1 ~( invert_carry_in $end +$var wire 1 !) invert_carry_out $end +$var wire 1 ") add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 #) prefix_pad $end +$scope struct dest $end +$var wire 4 $) value $end +$upscope $end +$scope struct src $end +$var wire 6 %) \[0] $end +$var wire 6 &) \[1] $end +$var wire 6 ') \[2] $end +$upscope $end +$var wire 25 () imm_low $end +$var wire 1 )) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 *) output_integer_mode $end +$upscope $end +$var wire 1 +) invert_src0 $end +$var wire 1 ,) invert_carry_in $end +$var wire 1 -) invert_carry_out $end +$var wire 1 .) add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 /) prefix_pad $end +$scope struct dest $end +$var wire 4 0) value $end +$upscope $end +$scope struct src $end +$var wire 6 1) \[0] $end +$var wire 6 2) \[1] $end +$var wire 6 3) \[2] $end +$upscope $end +$var wire 25 4) imm_low $end +$var wire 1 5) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 6) output_integer_mode $end +$upscope $end +$var wire 4 7) lut $end +$upscope $end +$upscope $end +$scope struct L2RegisterFile $end +$var string 1 8) \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 9) prefix_pad $end +$scope struct dest $end +$var wire 4 :) value $end +$upscope $end +$scope struct src $end +$var wire 6 ;) \[0] $end +$var wire 6 <) \[1] $end +$var wire 6 =) \[2] $end +$upscope $end +$var wire 25 >) imm_low $end +$var wire 1 ?) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 @) prefix_pad $end +$scope struct dest $end +$var wire 4 A) value $end +$upscope $end +$scope struct src $end +$var wire 6 B) \[0] $end +$var wire 6 C) \[1] $end +$var wire 6 D) \[2] $end +$upscope $end +$var wire 25 E) imm_low $end +$var wire 1 F) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct LoadStore $end +$var string 1 G) \$tag $end +$scope struct Load $end +$var wire 1 H) prefix_pad $end +$scope struct dest $end +$var wire 4 I) value $end +$upscope $end +$scope struct src $end +$var wire 6 J) \[0] $end +$var wire 6 K) \[1] $end +$var wire 6 L) \[2] $end +$upscope $end +$var wire 25 M) imm_low $end +$var wire 1 N) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 O) prefix_pad $end +$scope struct dest $end +$var wire 4 P) value $end +$upscope $end +$scope struct src $end +$var wire 6 Q) \[0] $end +$var wire 6 R) \[1] $end +$var wire 6 S) \[2] $end +$upscope $end +$var wire 25 T) imm_low $end +$var wire 1 U) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mapped_regs_6 $end +$var string 1 V) \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 W) prefix_pad $end +$scope struct dest $end +$var wire 4 X) value $end +$upscope $end +$scope struct src $end +$var wire 6 Y) \[0] $end +$var wire 6 Z) \[1] $end +$var wire 6 [) \[2] $end +$upscope $end +$var wire 25 \) imm_low $end +$var wire 1 ]) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ^) output_integer_mode $end +$upscope $end +$var wire 1 _) invert_src0 $end +$var wire 1 `) invert_carry_in $end +$var wire 1 a) invert_carry_out $end +$var wire 1 b) add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 c) prefix_pad $end +$scope struct dest $end +$var wire 4 d) value $end +$upscope $end +$scope struct src $end +$var wire 6 e) \[0] $end +$var wire 6 f) \[1] $end +$var wire 6 g) \[2] $end +$upscope $end +$var wire 25 h) imm_low $end +$var wire 1 i) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 j) output_integer_mode $end +$upscope $end +$var wire 1 k) invert_src0 $end +$var wire 1 l) invert_carry_in $end +$var wire 1 m) invert_carry_out $end +$var wire 1 n) add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 o) prefix_pad $end +$scope struct dest $end +$var wire 4 p) value $end +$upscope $end +$scope struct src $end +$var wire 6 q) \[0] $end +$var wire 6 r) \[1] $end +$var wire 6 s) \[2] $end +$upscope $end +$var wire 25 t) imm_low $end +$var wire 1 u) imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 v) output_integer_mode $end +$upscope $end +$var wire 4 w) lut $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_0 $end +$scope struct unit_num $end +$var wire 2 x) adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 y) value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_1 $end +$scope struct unit_num $end +$var wire 2 z) adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 {) value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_2 $end +$scope struct unit_num $end +$var wire 2 |) adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 }) value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_0_2 $end +$scope struct unit_num $end +$var wire 2 ~) adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 !* value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_1_2 $end +$scope struct unit_num $end +$var wire 2 "* adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 #* value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_0_3 $end +$scope struct unit_num $end +$var wire 2 $* adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 %* value $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_1_3 $end +$scope struct unit_num $end +$var wire 2 &* adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 '* value $end +$upscope $end +$upscope $end +$scope struct mapped_regs_7 $end +$var string 1 (* \$tag $end +$scope struct ReadL2Reg $end +$scope struct common $end +$var wire 1 )* prefix_pad $end +$scope struct dest $end +$var wire 4 ** value $end +$upscope $end +$scope struct src $end +$var wire 6 +* \[0] $end +$var wire 6 ,* \[1] $end +$var wire 6 -* \[2] $end +$upscope $end +$var wire 25 .* imm_low $end +$var wire 1 /* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct WriteL2Reg $end +$scope struct common $end +$var wire 1 0* prefix_pad $end +$scope struct dest $end +$var wire 4 1* value $end +$upscope $end +$scope struct src $end +$var wire 6 2* \[0] $end +$var wire 6 3* \[1] $end +$var wire 6 4* \[2] $end +$upscope $end +$var wire 25 5* imm_low $end +$var wire 1 6* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_0_4 $end +$scope struct unit_num $end +$var wire 2 7* adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 8* value $end +$upscope $end +$upscope $end +$scope struct mapped_regs_8 $end +$var string 1 9* \$tag $end +$scope struct Load $end +$var wire 1 :* prefix_pad $end +$scope struct dest $end +$var wire 4 ;* value $end +$upscope $end +$scope struct src $end +$var wire 6 <* \[0] $end +$var wire 6 =* \[1] $end +$var wire 6 >* \[2] $end +$upscope $end +$var wire 25 ?* imm_low $end +$var wire 1 @* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct Store $end +$var wire 1 A* prefix_pad $end +$scope struct dest $end +$var wire 4 B* value $end +$upscope $end +$scope struct src $end +$var wire 6 C* \[0] $end +$var wire 6 D* \[1] $end +$var wire 6 E* \[2] $end +$upscope $end +$var wire 25 F* imm_low $end +$var wire 1 G* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$upscope $end +$scope struct renamed_src_reg_1_0_5 $end +$scope struct unit_num $end +$var wire 2 H* adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 I* value $end +$upscope $end +$upscope $end +$scope struct selected_unit_index_leaf_1_0 $end +$var string 1 J* \$tag $end +$var wire 2 K* HdlSome $end +$upscope $end +$var wire 2 L* unit_index_1_0 $end +$scope struct selected_unit_index_leaf_1_1 $end +$var string 1 M* \$tag $end +$var wire 2 N* HdlSome $end +$upscope $end +$var wire 2 O* unit_index_1_1 $end +$scope struct selected_unit_index_node_1_0 $end +$var string 1 P* \$tag $end +$var wire 2 Q* HdlSome $end $upscope $end $scope struct unit_0 $end $scope struct cd $end -$var wire 1 d" clk $end -$var wire 1 e" rst $end +$var wire 1 x* clk $end +$var wire 1 y* rst $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 z* \$tag $end +$scope struct HdlSome $end +$var string 1 {* \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 |* prefix_pad $end +$scope struct dest $end +$var wire 4 }* value $end +$upscope $end +$scope struct src $end +$var wire 6 ~* \[0] $end +$var wire 6 !+ \[1] $end +$var wire 6 "+ \[2] $end +$upscope $end +$var wire 25 #+ imm_low $end +$var wire 1 $+ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 %+ output_integer_mode $end +$upscope $end +$var wire 1 &+ invert_src0 $end +$var wire 1 '+ invert_carry_in $end +$var wire 1 (+ invert_carry_out $end +$var wire 1 )+ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 *+ prefix_pad $end +$scope struct dest $end +$var wire 4 ++ value $end +$upscope $end +$scope struct src $end +$var wire 6 ,+ \[0] $end +$var wire 6 -+ \[1] $end +$var wire 6 .+ \[2] $end +$upscope $end +$var wire 25 /+ imm_low $end +$var wire 1 0+ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 1+ output_integer_mode $end +$upscope $end +$var wire 1 2+ invert_src0 $end +$var wire 1 3+ invert_carry_in $end +$var wire 1 4+ invert_carry_out $end +$var wire 1 5+ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 6+ prefix_pad $end +$scope struct dest $end +$var wire 4 7+ value $end +$upscope $end +$scope struct src $end +$var wire 6 8+ \[0] $end +$var wire 6 9+ \[1] $end +$var wire 6 :+ \[2] $end +$upscope $end +$var wire 25 ;+ imm_low $end +$var wire 1 <+ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 =+ output_integer_mode $end +$upscope $end +$var wire 4 >+ lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 ?+ ready $end $upscope $end $upscope $end $scope module alu_branch $end $scope struct cd $end -$var wire 1 b" clk $end -$var wire 1 c" rst $end +$var wire 1 R* clk $end +$var wire 1 S* rst $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 T* \$tag $end +$scope struct HdlSome $end +$var string 1 U* \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 V* prefix_pad $end +$scope struct dest $end +$var wire 4 W* value $end +$upscope $end +$scope struct src $end +$var wire 6 X* \[0] $end +$var wire 6 Y* \[1] $end +$var wire 6 Z* \[2] $end +$upscope $end +$var wire 25 [* imm_low $end +$var wire 1 \* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ]* output_integer_mode $end +$upscope $end +$var wire 1 ^* invert_src0 $end +$var wire 1 _* invert_carry_in $end +$var wire 1 `* invert_carry_out $end +$var wire 1 a* add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 b* prefix_pad $end +$scope struct dest $end +$var wire 4 c* value $end +$upscope $end +$scope struct src $end +$var wire 6 d* \[0] $end +$var wire 6 e* \[1] $end +$var wire 6 f* \[2] $end +$upscope $end +$var wire 25 g* imm_low $end +$var wire 1 h* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 i* output_integer_mode $end +$upscope $end +$var wire 1 j* invert_src0 $end +$var wire 1 k* invert_carry_in $end +$var wire 1 l* invert_carry_out $end +$var wire 1 m* add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 n* prefix_pad $end +$scope struct dest $end +$var wire 4 o* value $end +$upscope $end +$scope struct src $end +$var wire 6 p* \[0] $end +$var wire 6 q* \[1] $end +$var wire 6 r* \[2] $end +$upscope $end +$var wire 25 s* imm_low $end +$var wire 1 t* imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 u* output_integer_mode $end +$upscope $end +$var wire 4 v* lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 w* ready $end $upscope $end $upscope $end $scope struct unit_0_free_regs_tracker $end $scope struct cd $end -$var wire 1 Q# clk $end -$var wire 1 R# rst $end +$var wire 1 +, clk $end +$var wire 1 ,, rst $end $upscope $end $scope struct free_in $end $scope struct \[0] $end $scope struct data $end -$var string 1 S# \$tag $end -$var wire 4 T# HdlSome $end +$var string 1 -, \$tag $end +$var wire 4 ., HdlSome $end $upscope $end -$var wire 1 U# ready $end +$var wire 1 /, ready $end $upscope $end $upscope $end $scope struct alloc_out $end $scope struct \[0] $end $scope struct data $end -$var string 1 V# \$tag $end -$var wire 4 W# HdlSome $end +$var string 1 0, \$tag $end +$var wire 4 1, HdlSome $end $upscope $end -$var wire 1 X# ready $end +$var wire 1 2, ready $end $upscope $end $upscope $end $upscope $end $scope module unit_free_regs_tracker $end $scope struct cd $end -$var wire 1 f" clk $end -$var wire 1 g" rst $end +$var wire 1 @+ clk $end +$var wire 1 A+ rst $end $upscope $end $scope struct free_in $end $scope struct \[0] $end $scope struct data $end -$var string 1 h" \$tag $end -$var wire 4 i" HdlSome $end +$var string 1 B+ \$tag $end +$var wire 4 C+ HdlSome $end $upscope $end -$var wire 1 j" ready $end +$var wire 1 D+ ready $end $upscope $end $upscope $end $scope struct alloc_out $end $scope struct \[0] $end $scope struct data $end -$var string 1 k" \$tag $end -$var wire 4 l" HdlSome $end +$var string 1 E+ \$tag $end +$var wire 4 F+ HdlSome $end $upscope $end -$var wire 1 m" ready $end +$var wire 1 G+ ready $end $upscope $end $upscope $end $scope struct allocated_reg $end -$var reg 1 n" \[0] $end -$var reg 1 o" \[1] $end -$var reg 1 p" \[2] $end -$var reg 1 q" \[3] $end -$var reg 1 r" \[4] $end -$var reg 1 s" \[5] $end -$var reg 1 t" \[6] $end -$var reg 1 u" \[7] $end -$var reg 1 v" \[8] $end -$var reg 1 w" \[9] $end -$var reg 1 x" \[10] $end -$var reg 1 y" \[11] $end -$var reg 1 z" \[12] $end -$var reg 1 {" \[13] $end -$var reg 1 |" \[14] $end -$var reg 1 }" \[15] $end +$var reg 1 H+ \[0] $end +$var reg 1 I+ \[1] $end +$var reg 1 J+ \[2] $end +$var reg 1 K+ \[3] $end +$var reg 1 L+ \[4] $end +$var reg 1 M+ \[5] $end +$var reg 1 N+ \[6] $end +$var reg 1 O+ \[7] $end +$var reg 1 P+ \[8] $end +$var reg 1 Q+ \[9] $end +$var reg 1 R+ \[10] $end +$var reg 1 S+ \[11] $end +$var reg 1 T+ \[12] $end +$var reg 1 U+ \[13] $end +$var reg 1 V+ \[14] $end +$var reg 1 W+ \[15] $end $upscope $end $scope struct firing_data $end -$var string 1 ~" \$tag $end -$var wire 4 !# HdlSome $end +$var string 1 X+ \$tag $end +$var wire 4 Y+ HdlSome $end $upscope $end -$var wire 1 "# reduced_count_0_2 $end -$var wire 1 ## reduced_count_overflowed_0_2 $end +$var wire 1 Z+ reduced_count_0_2 $end +$var wire 1 [+ reduced_count_overflowed_0_2 $end $scope struct reduced_alloc_nums_0_2 $end -$var wire 1 $# \[0] $end +$var wire 1 \+ \[0] $end $upscope $end -$var wire 1 %# reduced_count_2_4 $end -$var wire 1 &# reduced_count_overflowed_2_4 $end +$var wire 1 ]+ reduced_count_2_4 $end +$var wire 1 ^+ reduced_count_overflowed_2_4 $end $scope struct reduced_alloc_nums_2_4 $end -$var wire 1 '# \[0] $end +$var wire 1 _+ \[0] $end $upscope $end -$var wire 1 (# reduced_count_0_4 $end -$var wire 1 )# reduced_count_overflowed_0_4 $end +$var wire 1 `+ reduced_count_0_4 $end +$var wire 1 a+ reduced_count_overflowed_0_4 $end $scope struct reduced_alloc_nums_0_4 $end -$var wire 2 *# \[0] $end +$var wire 2 b+ \[0] $end $upscope $end -$var wire 1 +# reduced_count_4_6 $end -$var wire 1 ,# reduced_count_overflowed_4_6 $end +$var wire 1 c+ reduced_count_4_6 $end +$var wire 1 d+ reduced_count_overflowed_4_6 $end $scope struct reduced_alloc_nums_4_6 $end -$var wire 1 -# \[0] $end +$var wire 1 e+ \[0] $end $upscope $end -$var wire 1 .# reduced_count_6_8 $end -$var wire 1 /# reduced_count_overflowed_6_8 $end +$var wire 1 f+ reduced_count_6_8 $end +$var wire 1 g+ reduced_count_overflowed_6_8 $end $scope struct reduced_alloc_nums_6_8 $end -$var wire 1 0# \[0] $end +$var wire 1 h+ \[0] $end $upscope $end -$var wire 1 1# reduced_count_4_8 $end -$var wire 1 2# reduced_count_overflowed_4_8 $end +$var wire 1 i+ reduced_count_4_8 $end +$var wire 1 j+ reduced_count_overflowed_4_8 $end $scope struct reduced_alloc_nums_4_8 $end -$var wire 2 3# \[0] $end +$var wire 2 k+ \[0] $end $upscope $end -$var wire 1 4# reduced_count_0_8 $end -$var wire 1 5# reduced_count_overflowed_0_8 $end +$var wire 1 l+ reduced_count_0_8 $end +$var wire 1 m+ reduced_count_overflowed_0_8 $end $scope struct reduced_alloc_nums_0_8 $end -$var wire 3 6# \[0] $end +$var wire 3 n+ \[0] $end $upscope $end -$var wire 1 7# reduced_count_8_10 $end -$var wire 1 8# reduced_count_overflowed_8_10 $end +$var wire 1 o+ reduced_count_8_10 $end +$var wire 1 p+ reduced_count_overflowed_8_10 $end $scope struct reduced_alloc_nums_8_10 $end -$var wire 1 9# \[0] $end +$var wire 1 q+ \[0] $end $upscope $end -$var wire 1 :# reduced_count_10_12 $end -$var wire 1 ;# reduced_count_overflowed_10_12 $end +$var wire 1 r+ reduced_count_10_12 $end +$var wire 1 s+ reduced_count_overflowed_10_12 $end $scope struct reduced_alloc_nums_10_12 $end -$var wire 1 <# \[0] $end +$var wire 1 t+ \[0] $end $upscope $end -$var wire 1 =# reduced_count_8_12 $end -$var wire 1 ># reduced_count_overflowed_8_12 $end +$var wire 1 u+ reduced_count_8_12 $end +$var wire 1 v+ reduced_count_overflowed_8_12 $end $scope struct reduced_alloc_nums_8_12 $end -$var wire 2 ?# \[0] $end +$var wire 2 w+ \[0] $end $upscope $end -$var wire 1 @# reduced_count_12_14 $end -$var wire 1 A# reduced_count_overflowed_12_14 $end +$var wire 1 x+ reduced_count_12_14 $end +$var wire 1 y+ reduced_count_overflowed_12_14 $end $scope struct reduced_alloc_nums_12_14 $end -$var wire 1 B# \[0] $end +$var wire 1 z+ \[0] $end $upscope $end -$var wire 1 C# reduced_count_14_16 $end -$var wire 1 D# reduced_count_overflowed_14_16 $end +$var wire 1 {+ reduced_count_14_16 $end +$var wire 1 |+ reduced_count_overflowed_14_16 $end $scope struct reduced_alloc_nums_14_16 $end -$var wire 1 E# \[0] $end +$var wire 1 }+ \[0] $end $upscope $end -$var wire 1 F# reduced_count_12_16 $end -$var wire 1 G# reduced_count_overflowed_12_16 $end +$var wire 1 ~+ reduced_count_12_16 $end +$var wire 1 !, reduced_count_overflowed_12_16 $end $scope struct reduced_alloc_nums_12_16 $end -$var wire 2 H# \[0] $end +$var wire 2 ", \[0] $end $upscope $end -$var wire 1 I# reduced_count_8_16 $end -$var wire 1 J# reduced_count_overflowed_8_16 $end +$var wire 1 #, reduced_count_8_16 $end +$var wire 1 $, reduced_count_overflowed_8_16 $end $scope struct reduced_alloc_nums_8_16 $end -$var wire 3 K# \[0] $end +$var wire 3 %, \[0] $end $upscope $end -$var wire 1 L# reduced_count_0_16 $end -$var wire 1 M# reduced_count_overflowed_0_16 $end +$var wire 1 &, reduced_count_0_16 $end +$var wire 1 ', reduced_count_overflowed_0_16 $end $scope struct reduced_alloc_nums_0_16 $end -$var wire 4 N# \[0] $end +$var wire 4 (, \[0] $end $upscope $end $scope struct firing_data_2 $end -$var string 1 O# \$tag $end -$var wire 4 P# HdlSome $end +$var string 1 ), \$tag $end +$var wire 4 *, HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out $end +$var string 1 3, \$tag $end +$scope struct HdlSome $end +$var string 1 4, \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 5, prefix_pad $end +$scope struct dest $end +$var wire 4 6, value $end +$upscope $end +$scope struct src $end +$var wire 6 7, \[0] $end +$var wire 6 8, \[1] $end +$var wire 6 9, \[2] $end +$upscope $end +$var wire 25 :, imm_low $end +$var wire 1 ;, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 <, output_integer_mode $end +$upscope $end +$var wire 1 =, invert_src0 $end +$var wire 1 >, invert_carry_in $end +$var wire 1 ?, invert_carry_out $end +$var wire 1 @, add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A, prefix_pad $end +$scope struct dest $end +$var wire 4 B, value $end +$upscope $end +$scope struct src $end +$var wire 6 C, \[0] $end +$var wire 6 D, \[1] $end +$var wire 6 E, \[2] $end +$upscope $end +$var wire 25 F, imm_low $end +$var wire 1 G, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 H, output_integer_mode $end +$upscope $end +$var wire 1 I, invert_src0 $end +$var wire 1 J, invert_carry_in $end +$var wire 1 K, invert_carry_out $end +$var wire 1 L, add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 M, prefix_pad $end +$scope struct dest $end +$var wire 4 N, value $end +$upscope $end +$scope struct src $end +$var wire 6 O, \[0] $end +$var wire 6 P, \[1] $end +$var wire 6 Q, \[2] $end +$upscope $end +$var wire 25 R, imm_low $end +$var wire 1 S, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 T, output_integer_mode $end +$upscope $end +$var wire 4 U, lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop $end +$var string 1 V, \$tag $end +$scope struct HdlSome $end +$var string 1 W, \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 X, prefix_pad $end +$scope struct dest $end +$var wire 4 Y, value $end +$upscope $end +$scope struct src $end +$var wire 6 Z, \[0] $end +$var wire 6 [, \[1] $end +$var wire 6 \, \[2] $end +$upscope $end +$var wire 25 ], imm_low $end +$var wire 1 ^, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 _, output_integer_mode $end +$upscope $end +$var wire 1 `, invert_src0 $end +$var wire 1 a, invert_carry_in $end +$var wire 1 b, invert_carry_out $end +$var wire 1 c, add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 d, prefix_pad $end +$scope struct dest $end +$var wire 4 e, value $end +$upscope $end +$scope struct src $end +$var wire 6 f, \[0] $end +$var wire 6 g, \[1] $end +$var wire 6 h, \[2] $end +$upscope $end +$var wire 25 i, imm_low $end +$var wire 1 j, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 k, output_integer_mode $end +$upscope $end +$var wire 1 l, invert_src0 $end +$var wire 1 m, invert_carry_in $end +$var wire 1 n, invert_carry_out $end +$var wire 1 o, add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 p, prefix_pad $end +$scope struct dest $end +$var wire 4 q, value $end +$upscope $end +$scope struct src $end +$var wire 6 r, \[0] $end +$var wire 6 s, \[1] $end +$var wire 6 t, \[2] $end +$upscope $end +$var wire 25 u, imm_low $end +$var wire 1 v, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 w, output_integer_mode $end +$upscope $end +$var wire 4 x, lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct and_then_out_2 $end +$var string 1 y, \$tag $end +$scope struct HdlSome $end +$var string 1 z, \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 {, prefix_pad $end +$scope struct dest $end +$var wire 4 |, value $end +$upscope $end +$scope struct src $end +$var wire 6 }, \[0] $end +$var wire 6 ~, \[1] $end +$var wire 6 !- \[2] $end +$upscope $end +$var wire 25 "- imm_low $end +$var wire 1 #- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 $- output_integer_mode $end +$upscope $end +$var wire 1 %- invert_src0 $end +$var wire 1 &- invert_carry_in $end +$var wire 1 '- invert_carry_out $end +$var wire 1 (- add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 )- prefix_pad $end +$scope struct dest $end +$var wire 4 *- value $end +$upscope $end +$scope struct src $end +$var wire 6 +- \[0] $end +$var wire 6 ,- \[1] $end +$var wire 6 -- \[2] $end +$upscope $end +$var wire 25 .- imm_low $end +$var wire 1 /- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 0- output_integer_mode $end +$upscope $end +$var wire 1 1- invert_src0 $end +$var wire 1 2- invert_carry_in $end +$var wire 1 3- invert_carry_out $end +$var wire 1 4- add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 5- prefix_pad $end +$scope struct dest $end +$var wire 4 6- value $end +$upscope $end +$scope struct src $end +$var wire 6 7- \[0] $end +$var wire 6 8- \[1] $end +$var wire 6 9- \[2] $end +$upscope $end +$var wire 25 :- imm_low $end +$var wire 1 ;- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 <- output_integer_mode $end +$upscope $end +$var wire 4 =- lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_2 $end +$var string 1 >- \$tag $end +$scope struct HdlSome $end +$var string 1 ?- \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 @- prefix_pad $end +$scope struct dest $end +$var wire 4 A- value $end +$upscope $end +$scope struct src $end +$var wire 6 B- \[0] $end +$var wire 6 C- \[1] $end +$var wire 6 D- \[2] $end +$upscope $end +$var wire 25 E- imm_low $end +$var wire 1 F- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 G- output_integer_mode $end +$upscope $end +$var wire 1 H- invert_src0 $end +$var wire 1 I- invert_carry_in $end +$var wire 1 J- invert_carry_out $end +$var wire 1 K- add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 L- prefix_pad $end +$scope struct dest $end +$var wire 4 M- value $end +$upscope $end +$scope struct src $end +$var wire 6 N- \[0] $end +$var wire 6 O- \[1] $end +$var wire 6 P- \[2] $end +$upscope $end +$var wire 25 Q- imm_low $end +$var wire 1 R- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 S- output_integer_mode $end +$upscope $end +$var wire 1 T- invert_src0 $end +$var wire 1 U- invert_carry_in $end +$var wire 1 V- invert_carry_out $end +$var wire 1 W- add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 X- prefix_pad $end +$scope struct dest $end +$var wire 4 Y- value $end +$upscope $end +$scope struct src $end +$var wire 6 Z- \[0] $end +$var wire 6 [- \[1] $end +$var wire 6 \- \[2] $end +$upscope $end +$var wire 25 ]- imm_low $end +$var wire 1 ^- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 _- output_integer_mode $end +$upscope $end +$var wire 4 `- lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_1 $end +$scope struct cd $end +$var wire 1 ). clk $end +$var wire 1 *. rst $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 +. \$tag $end +$scope struct HdlSome $end +$var string 1 ,. \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 -. prefix_pad $end +$scope struct dest $end +$var wire 4 .. value $end +$upscope $end +$scope struct src $end +$var wire 6 /. \[0] $end +$var wire 6 0. \[1] $end +$var wire 6 1. \[2] $end +$upscope $end +$var wire 25 2. imm_low $end +$var wire 1 3. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 4. output_integer_mode $end +$upscope $end +$var wire 1 5. invert_src0 $end +$var wire 1 6. invert_carry_in $end +$var wire 1 7. invert_carry_out $end +$var wire 1 8. add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 9. prefix_pad $end +$scope struct dest $end +$var wire 4 :. value $end +$upscope $end +$scope struct src $end +$var wire 6 ;. \[0] $end +$var wire 6 <. \[1] $end +$var wire 6 =. \[2] $end +$upscope $end +$var wire 25 >. imm_low $end +$var wire 1 ?. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 @. output_integer_mode $end +$upscope $end +$var wire 1 A. invert_src0 $end +$var wire 1 B. invert_carry_in $end +$var wire 1 C. invert_carry_out $end +$var wire 1 D. add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 E. prefix_pad $end +$scope struct dest $end +$var wire 4 F. value $end +$upscope $end +$scope struct src $end +$var wire 6 G. \[0] $end +$var wire 6 H. \[1] $end +$var wire 6 I. \[2] $end +$upscope $end +$var wire 25 J. imm_low $end +$var wire 1 K. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 L. output_integer_mode $end +$upscope $end +$var wire 4 M. lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 N. ready $end +$upscope $end +$upscope $end +$scope module alu_branch_2 $end +$scope struct cd $end +$var wire 1 a- clk $end +$var wire 1 b- rst $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 c- \$tag $end +$scope struct HdlSome $end +$var string 1 d- \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 e- prefix_pad $end +$scope struct dest $end +$var wire 4 f- value $end +$upscope $end +$scope struct src $end +$var wire 6 g- \[0] $end +$var wire 6 h- \[1] $end +$var wire 6 i- \[2] $end +$upscope $end +$var wire 25 j- imm_low $end +$var wire 1 k- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 l- output_integer_mode $end +$upscope $end +$var wire 1 m- invert_src0 $end +$var wire 1 n- invert_carry_in $end +$var wire 1 o- invert_carry_out $end +$var wire 1 p- add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 q- prefix_pad $end +$scope struct dest $end +$var wire 4 r- value $end +$upscope $end +$scope struct src $end +$var wire 6 s- \[0] $end +$var wire 6 t- \[1] $end +$var wire 6 u- \[2] $end +$upscope $end +$var wire 25 v- imm_low $end +$var wire 1 w- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 x- output_integer_mode $end +$upscope $end +$var wire 1 y- invert_src0 $end +$var wire 1 z- invert_carry_in $end +$var wire 1 {- invert_carry_out $end +$var wire 1 |- add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }- prefix_pad $end +$scope struct dest $end +$var wire 4 ~- value $end +$upscope $end +$scope struct src $end +$var wire 6 !. \[0] $end +$var wire 6 ". \[1] $end +$var wire 6 #. \[2] $end +$upscope $end +$var wire 25 $. imm_low $end +$var wire 1 %. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &. output_integer_mode $end +$upscope $end +$var wire 4 '. lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 (. ready $end +$upscope $end +$upscope $end +$scope struct unit_1_free_regs_tracker $end +$scope struct cd $end +$var wire 1 :/ clk $end +$var wire 1 ;/ rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 / ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 ?/ \$tag $end +$var wire 4 @/ HdlSome $end +$upscope $end +$var wire 1 A/ ready $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_free_regs_tracker_2 $end +$scope struct cd $end +$var wire 1 O. clk $end +$var wire 1 P. rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 Q. \$tag $end +$var wire 4 R. HdlSome $end +$upscope $end +$var wire 1 S. ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 T. \$tag $end +$var wire 4 U. HdlSome $end +$upscope $end +$var wire 1 V. ready $end +$upscope $end +$upscope $end +$scope struct allocated_reg $end +$var reg 1 W. \[0] $end +$var reg 1 X. \[1] $end +$var reg 1 Y. \[2] $end +$var reg 1 Z. \[3] $end +$var reg 1 [. \[4] $end +$var reg 1 \. \[5] $end +$var reg 1 ]. \[6] $end +$var reg 1 ^. \[7] $end +$var reg 1 _. \[8] $end +$var reg 1 `. \[9] $end +$var reg 1 a. \[10] $end +$var reg 1 b. \[11] $end +$var reg 1 c. \[12] $end +$var reg 1 d. \[13] $end +$var reg 1 e. \[14] $end +$var reg 1 f. \[15] $end +$upscope $end +$scope struct firing_data $end +$var string 1 g. \$tag $end +$var wire 4 h. HdlSome $end +$upscope $end +$var wire 1 i. reduced_count_0_2 $end +$var wire 1 j. reduced_count_overflowed_0_2 $end +$scope struct reduced_alloc_nums_0_2 $end +$var wire 1 k. \[0] $end +$upscope $end +$var wire 1 l. reduced_count_2_4 $end +$var wire 1 m. reduced_count_overflowed_2_4 $end +$scope struct reduced_alloc_nums_2_4 $end +$var wire 1 n. \[0] $end +$upscope $end +$var wire 1 o. reduced_count_0_4 $end +$var wire 1 p. reduced_count_overflowed_0_4 $end +$scope struct reduced_alloc_nums_0_4 $end +$var wire 2 q. \[0] $end +$upscope $end +$var wire 1 r. reduced_count_4_6 $end +$var wire 1 s. reduced_count_overflowed_4_6 $end +$scope struct reduced_alloc_nums_4_6 $end +$var wire 1 t. \[0] $end +$upscope $end +$var wire 1 u. reduced_count_6_8 $end +$var wire 1 v. reduced_count_overflowed_6_8 $end +$scope struct reduced_alloc_nums_6_8 $end +$var wire 1 w. \[0] $end +$upscope $end +$var wire 1 x. reduced_count_4_8 $end +$var wire 1 y. reduced_count_overflowed_4_8 $end +$scope struct reduced_alloc_nums_4_8 $end +$var wire 2 z. \[0] $end +$upscope $end +$var wire 1 {. reduced_count_0_8 $end +$var wire 1 |. reduced_count_overflowed_0_8 $end +$scope struct reduced_alloc_nums_0_8 $end +$var wire 3 }. \[0] $end +$upscope $end +$var wire 1 ~. reduced_count_8_10 $end +$var wire 1 !/ reduced_count_overflowed_8_10 $end +$scope struct reduced_alloc_nums_8_10 $end +$var wire 1 "/ \[0] $end +$upscope $end +$var wire 1 #/ reduced_count_10_12 $end +$var wire 1 $/ reduced_count_overflowed_10_12 $end +$scope struct reduced_alloc_nums_10_12 $end +$var wire 1 %/ \[0] $end +$upscope $end +$var wire 1 &/ reduced_count_8_12 $end +$var wire 1 '/ reduced_count_overflowed_8_12 $end +$scope struct reduced_alloc_nums_8_12 $end +$var wire 2 (/ \[0] $end +$upscope $end +$var wire 1 )/ reduced_count_12_14 $end +$var wire 1 */ reduced_count_overflowed_12_14 $end +$scope struct reduced_alloc_nums_12_14 $end +$var wire 1 +/ \[0] $end +$upscope $end +$var wire 1 ,/ reduced_count_14_16 $end +$var wire 1 -/ reduced_count_overflowed_14_16 $end +$scope struct reduced_alloc_nums_14_16 $end +$var wire 1 ./ \[0] $end +$upscope $end +$var wire 1 // reduced_count_12_16 $end +$var wire 1 0/ reduced_count_overflowed_12_16 $end +$scope struct reduced_alloc_nums_12_16 $end +$var wire 2 1/ \[0] $end +$upscope $end +$var wire 1 2/ reduced_count_8_16 $end +$var wire 1 3/ reduced_count_overflowed_8_16 $end +$scope struct reduced_alloc_nums_8_16 $end +$var wire 3 4/ \[0] $end +$upscope $end +$var wire 1 5/ reduced_count_0_16 $end +$var wire 1 6/ reduced_count_overflowed_0_16 $end +$scope struct reduced_alloc_nums_0_16 $end +$var wire 4 7/ \[0] $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 8/ \$tag $end +$var wire 4 9/ HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out_3 $end +$var string 1 B/ \$tag $end +$scope struct HdlSome $end +$var string 1 C/ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 D/ prefix_pad $end +$scope struct dest $end +$var wire 4 E/ value $end +$upscope $end +$scope struct src $end +$var wire 6 F/ \[0] $end +$var wire 6 G/ \[1] $end +$var wire 6 H/ \[2] $end +$upscope $end +$var wire 25 I/ imm_low $end +$var wire 1 J/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 K/ output_integer_mode $end +$upscope $end +$var wire 1 L/ invert_src0 $end +$var wire 1 M/ invert_carry_in $end +$var wire 1 N/ invert_carry_out $end +$var wire 1 O/ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 P/ prefix_pad $end +$scope struct dest $end +$var wire 4 Q/ value $end +$upscope $end +$scope struct src $end +$var wire 6 R/ \[0] $end +$var wire 6 S/ \[1] $end +$var wire 6 T/ \[2] $end +$upscope $end +$var wire 25 U/ imm_low $end +$var wire 1 V/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 W/ output_integer_mode $end +$upscope $end +$var wire 1 X/ invert_src0 $end +$var wire 1 Y/ invert_carry_in $end +$var wire 1 Z/ invert_carry_out $end +$var wire 1 [/ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 \/ prefix_pad $end +$scope struct dest $end +$var wire 4 ]/ value $end +$upscope $end +$scope struct src $end +$var wire 6 ^/ \[0] $end +$var wire 6 _/ \[1] $end +$var wire 6 `/ \[2] $end +$upscope $end +$var wire 25 a/ imm_low $end +$var wire 1 b/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 c/ output_integer_mode $end +$upscope $end +$var wire 4 d/ lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_3 $end +$var string 1 e/ \$tag $end +$scope struct HdlSome $end +$var string 1 f/ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 g/ prefix_pad $end +$scope struct dest $end +$var wire 4 h/ value $end +$upscope $end +$scope struct src $end +$var wire 6 i/ \[0] $end +$var wire 6 j/ \[1] $end +$var wire 6 k/ \[2] $end +$upscope $end +$var wire 25 l/ imm_low $end +$var wire 1 m/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 n/ output_integer_mode $end +$upscope $end +$var wire 1 o/ invert_src0 $end +$var wire 1 p/ invert_carry_in $end +$var wire 1 q/ invert_carry_out $end +$var wire 1 r/ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 s/ prefix_pad $end +$scope struct dest $end +$var wire 4 t/ value $end +$upscope $end +$scope struct src $end +$var wire 6 u/ \[0] $end +$var wire 6 v/ \[1] $end +$var wire 6 w/ \[2] $end +$upscope $end +$var wire 25 x/ imm_low $end +$var wire 1 y/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 z/ output_integer_mode $end +$upscope $end +$var wire 1 {/ invert_src0 $end +$var wire 1 |/ invert_carry_in $end +$var wire 1 }/ invert_carry_out $end +$var wire 1 ~/ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 !0 prefix_pad $end +$scope struct dest $end +$var wire 4 "0 value $end +$upscope $end +$scope struct src $end +$var wire 6 #0 \[0] $end +$var wire 6 $0 \[1] $end +$var wire 6 %0 \[2] $end +$upscope $end +$var wire 25 &0 imm_low $end +$var wire 1 '0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 (0 output_integer_mode $end +$upscope $end +$var wire 4 )0 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct and_then_out_4 $end +$var string 1 *0 \$tag $end +$scope struct HdlSome $end +$var string 1 +0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ,0 prefix_pad $end +$scope struct dest $end +$var wire 4 -0 value $end +$upscope $end +$scope struct src $end +$var wire 6 .0 \[0] $end +$var wire 6 /0 \[1] $end +$var wire 6 00 \[2] $end +$upscope $end +$var wire 25 10 imm_low $end +$var wire 1 20 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 30 output_integer_mode $end +$upscope $end +$var wire 1 40 invert_src0 $end +$var wire 1 50 invert_carry_in $end +$var wire 1 60 invert_carry_out $end +$var wire 1 70 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 80 prefix_pad $end +$scope struct dest $end +$var wire 4 90 value $end +$upscope $end +$scope struct src $end +$var wire 6 :0 \[0] $end +$var wire 6 ;0 \[1] $end +$var wire 6 <0 \[2] $end +$upscope $end +$var wire 25 =0 imm_low $end +$var wire 1 >0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ?0 output_integer_mode $end +$upscope $end +$var wire 1 @0 invert_src0 $end +$var wire 1 A0 invert_carry_in $end +$var wire 1 B0 invert_carry_out $end +$var wire 1 C0 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 D0 prefix_pad $end +$scope struct dest $end +$var wire 4 E0 value $end +$upscope $end +$scope struct src $end +$var wire 6 F0 \[0] $end +$var wire 6 G0 \[1] $end +$var wire 6 H0 \[2] $end +$upscope $end +$var wire 25 I0 imm_low $end +$var wire 1 J0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 K0 output_integer_mode $end +$upscope $end +$var wire 4 L0 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_4 $end +$var string 1 M0 \$tag $end +$scope struct HdlSome $end +$var string 1 N0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 O0 prefix_pad $end +$scope struct dest $end +$var wire 4 P0 value $end +$upscope $end +$scope struct src $end +$var wire 6 Q0 \[0] $end +$var wire 6 R0 \[1] $end +$var wire 6 S0 \[2] $end +$upscope $end +$var wire 25 T0 imm_low $end +$var wire 1 U0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 V0 output_integer_mode $end +$upscope $end +$var wire 1 W0 invert_src0 $end +$var wire 1 X0 invert_carry_in $end +$var wire 1 Y0 invert_carry_out $end +$var wire 1 Z0 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 [0 prefix_pad $end +$scope struct dest $end +$var wire 4 \0 value $end +$upscope $end +$scope struct src $end +$var wire 6 ]0 \[0] $end +$var wire 6 ^0 \[1] $end +$var wire 6 _0 \[2] $end +$upscope $end +$var wire 25 `0 imm_low $end +$var wire 1 a0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 b0 output_integer_mode $end +$upscope $end +$var wire 1 c0 invert_src0 $end +$var wire 1 d0 invert_carry_in $end +$var wire 1 e0 invert_carry_out $end +$var wire 1 f0 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 g0 prefix_pad $end +$scope struct dest $end +$var wire 4 h0 value $end +$upscope $end +$scope struct src $end +$var wire 6 i0 \[0] $end +$var wire 6 j0 \[1] $end +$var wire 6 k0 \[2] $end +$upscope $end +$var wire 25 l0 imm_low $end +$var wire 1 m0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 n0 output_integer_mode $end +$upscope $end +$var wire 4 o0 lut $end +$upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars +b0 p0 +b0 S3 +b0 q0 +b0 T3 +b0 r0 +b0 U3 +b0 s0 +b0 V3 +b0 t0 +b0 W3 +b0 u0 +b0 X3 +b0 v0 +b0 Y3 +b0 w0 +b0 Z3 +b0 x0 +b0 [3 +b0 y0 +b0 \3 +b0 z0 +b0 ]3 +b0 {0 +b0 ^3 +b0 |0 +b0 _3 +b0 }0 +b0 `3 +b0 ~0 +b0 a3 +b0 !1 +b0 b3 +b0 "1 +b0 c3 +b0 #1 +b0 d3 +b0 $1 +b0 e3 +b0 %1 +b0 f3 +b0 &1 +b0 g3 +b0 '1 +b0 h3 +b0 (1 +b0 i3 +b0 )1 +b0 j3 +b0 *1 +b0 k3 +b0 +1 +b0 l3 +b0 ,1 +b0 m3 +b0 -1 +b0 n3 +b0 .1 +b0 o3 +b0 /1 +b0 p3 +b0 01 +b0 q3 +b0 11 +b0 r3 +b0 21 +b0 s3 +b0 31 +b0 t3 +b0 41 +b0 u3 +b0 51 +b0 v3 +b0 61 +b0 w3 +b0 71 +b0 x3 +b0 81 +b0 y3 +b0 91 +b0 z3 +b0 :1 +b0 {3 +b0 ;1 +b0 |3 +b0 <1 +b0 }3 +b0 =1 +b0 ~3 +b0 >1 +b0 !4 +b0 ?1 +b0 "4 +b0 @1 +b0 #4 +b0 A1 +b0 $4 +b0 B1 +b0 %4 +b0 C1 +b0 &4 +b0 D1 +b0 '4 +b0 E1 +b0 (4 +b0 F1 +b0 )4 +b0 G1 +b0 *4 +b0 H1 +b0 +4 +b0 I1 +b0 ,4 +b0 J1 +b0 -4 +b0 K1 +b0 .4 +b0 L1 +b0 /4 +b0 M1 +b0 04 +b0 N1 +b0 14 +b0 O1 +b0 24 +b0 P1 +b0 34 +b0 Q1 +b0 44 +b0 R1 +b0 54 +b0 S1 +b0 64 +b0 T1 +b0 74 +b0 U1 +b0 84 +b0 V1 +b0 94 +b0 W1 +b0 :4 +b0 X1 +b0 ;4 +b0 Y1 +b0 <4 +b0 Z1 +b0 =4 +b0 [1 +b0 >4 +b0 \1 +b0 ?4 +b0 ]1 +b0 @4 +b0 ^1 +b0 A4 +b0 _1 +b0 B4 +b0 `1 +b0 C4 +b0 a1 +b0 D4 +b0 b1 +b0 E4 +b0 c1 +b0 F4 +b0 d1 +b0 G4 +b0 e1 +b0 H4 +b0 f1 +b0 I4 +b0 g1 +b0 J4 +b0 h1 +b0 K4 +b0 i1 +b0 L4 +b0 j1 +b0 M4 +b0 k1 +b0 N4 +b0 l1 +b0 O4 +b0 m1 +b0 P4 +b0 n1 +b0 Q4 +b0 o1 +b0 R4 +b0 p1 +b0 S4 +b0 q1 +b0 T4 +b0 r1 +b0 U4 +b0 s1 +b0 V4 +b0 t1 +b0 W4 +b0 u1 +b0 X4 +b0 v1 +b0 Y4 +b0 w1 +b0 Z4 +b0 x1 +b0 [4 +b0 y1 +b0 \4 +b0 z1 +b0 ]4 +b0 {1 +b0 ^4 +b0 |1 +b0 _4 +b0 }1 +b0 `4 +b0 ~1 +b0 a4 +b0 !2 +b0 b4 +b0 "2 +b0 c4 +b0 #2 +b0 d4 +b0 $2 +b0 e4 +b0 %2 +b0 f4 +b0 &2 +b0 g4 +b0 '2 +b0 h4 +b0 (2 +b0 i4 +b0 )2 +b0 j4 +b0 *2 +b0 k4 +b0 +2 +b0 l4 +b0 ,2 +b0 m4 +b0 -2 +b0 n4 +b0 .2 +b0 o4 +b0 /2 +b0 p4 +b0 02 +b0 q4 +b0 12 +b0 r4 +b0 22 +b0 s4 +b0 32 +b0 t4 +b0 42 +b0 u4 +b0 52 +b0 v4 +b0 62 +b0 w4 +b0 72 +b0 x4 +b0 82 +b0 y4 +b0 92 +b0 z4 +b0 :2 +b0 {4 +b0 ;2 +b0 |4 +b0 <2 +b0 }4 +b0 =2 +b0 ~4 +b0 >2 +b0 !5 +b0 ?2 +b0 "5 +b0 @2 +b0 #5 +b0 A2 +b0 $5 +b0 B2 +b0 %5 +b0 C2 +b0 &5 +b0 D2 +b0 '5 +b0 E2 +b0 (5 +b0 F2 +b0 )5 +b0 G2 +b0 *5 +b0 H2 +b0 +5 +b0 I2 +b0 ,5 +b0 J2 +b0 -5 +b0 K2 +b0 .5 +b0 L2 +b0 /5 +b0 M2 +b0 05 +b0 N2 +b0 15 +b0 O2 +b0 25 +b0 P2 +b0 35 +b0 Q2 +b0 45 +b0 R2 +b0 55 +b0 S2 +b0 65 +b0 T2 +b0 75 +b0 U2 +b0 85 +b0 V2 +b0 95 +b0 W2 +b0 :5 +b0 X2 +b0 ;5 +b0 Y2 +b0 <5 +b0 Z2 +b0 =5 +b0 [2 +b0 >5 +b0 \2 +b0 ?5 +b0 ]2 +b0 @5 +b0 ^2 +b0 A5 +b0 _2 +b0 B5 +b0 `2 +b0 C5 +b0 a2 +b0 D5 +b0 b2 +b0 E5 +b0 c2 +b0 F5 +b0 d2 +b0 G5 +b0 e2 +b0 H5 +b0 f2 +b0 I5 +b0 g2 +b0 J5 +b0 h2 +b0 K5 +b0 i2 +b0 L5 +b0 j2 +b0 M5 +b0 k2 +b0 N5 +b0 l2 +b0 O5 +b0 m2 +b0 P5 +b0 n2 +b0 Q5 +b0 o2 +b0 R5 +b0 p2 +b0 S5 +b0 q2 +b0 T5 +b0 r2 +b0 U5 +b0 s2 +b0 V5 +b0 t2 +b0 W5 +b0 u2 +b0 X5 +b0 v2 +b0 Y5 +b0 w2 +b0 Z5 +b0 x2 +b0 [5 +b0 y2 +b0 \5 +b0 z2 +b0 ]5 +b0 {2 +b0 ^5 +b0 |2 +b0 _5 +b0 }2 +b0 `5 +b0 ~2 +b0 a5 +b0 !3 +b0 b5 +b0 "3 +b0 c5 +b0 #3 +b0 d5 +b0 $3 +b0 e5 +b0 %3 +b0 f5 +b0 &3 +b0 g5 +b0 '3 +b0 h5 +b0 (3 +b0 i5 +b0 )3 +b0 j5 +b0 *3 +b0 k5 +b0 +3 +b0 l5 +b0 ,3 +b0 m5 +b0 -3 +b0 n5 +b0 .3 +b0 o5 +b0 /3 +b0 p5 +b0 03 +b0 q5 +b0 13 +b0 r5 +b0 23 +b0 s5 +b0 33 +b0 t5 +b0 43 +b0 u5 +b0 53 +b0 v5 +b0 63 +b0 w5 +b0 73 +b0 x5 +b0 83 +b0 y5 +b0 93 +b0 z5 +b0 :3 +b0 {5 +b0 ;3 +b0 |5 +b0 <3 +b0 }5 +b0 =3 +b0 ~5 +b0 >3 +b0 !6 +b0 ?3 +b0 "6 +b0 @3 +b0 #6 +b0 A3 +b0 $6 +b0 B3 +b0 %6 +b0 C3 +b0 &6 +b0 D3 +b0 '6 +b0 E3 +b0 (6 +b0 F3 +b0 )6 +b0 G3 +b0 *6 +b0 H3 +b0 +6 +b0 I3 +b0 ,6 +b0 J3 +b0 -6 +b0 K3 +b0 .6 +b0 L3 +b0 /6 +b0 M3 +b0 06 +b0 N3 +b0 16 +b0 O3 +b0 26 +b0 P3 +b0 36 +b0 Q3 +b0 46 +b0 R3 +b0 56 +b0 66 +b0 86 +b0 76 +b0 96 0! 1" sHdlSome\x20(1) # @@ -520,681 +7093,4215 @@ sAluBranch\x20(0) $ sAddSub\x20(0) % s0 & b1 ' -b10 ( -b11 ) -b100 * -b1001000110100 + -0, -sFull64\x20(0) - -1. -1/ -10 +b0 ( +sHdlSome\x20(1) ) +sHdlNone\x20(0) * +b10 + +b11 , +b100 - +b1001000110100 . +0/ +sFull64\x20(0) 0 11 -s0 2 -b1 3 -b10 4 -b11 5 -b100 6 -b1001000110100 7 -08 -sFull64\x20(0) 9 -1: -1; -1< -1= -s0 > -b1 ? -b10 @ -b11 A -b100 B -b1001000110100 C -0D -sFull64\x20(0) E -b1111 F -sReadL2Reg\x20(0) G -0H -b1 I -b10 J -b11 K -b100 L -b1001000110100 M -0N -0O -b1 P -b10 Q -b11 R -b100 S -b1001000110100 T -0U -sLoad\x20(0) V -0W -b1 X -b10 Y -b11 Z -b100 [ -b1001000110100 \ -0] -0^ -b1 _ +12 +13 +14 +s0 5 +b1 6 +b0 7 +sHdlSome\x20(1) 8 +sHdlNone\x20(0) 9 +b10 : +b11 ; +b100 < +b1001000110100 = +0> +sFull64\x20(0) ? +1@ +1A +1B +1C +s0 D +b1 E +b0 F +sHdlSome\x20(1) G +sHdlNone\x20(0) H +b10 I +b11 J +b100 K +b1001000110100 L +0M +sFull64\x20(0) N +b1111 O +sReadL2Reg\x20(0) P +0Q +b1 R +b0 S +sHdlSome\x20(1) T +sHdlNone\x20(0) U +b10 V +b11 W +b100 X +b1001000110100 Y +0Z +0[ +b1 \ +b0 ] +sHdlSome\x20(1) ^ +sHdlNone\x20(0) _ b10 ` b11 a b100 b b1001000110100 c 0d -1e -b1000000000000 f -1g -sHdlSome\x20(1) h -sAluBranch\x20(0) i -sLogical\x20(2) j -s0 k -b10 l -b11 m -b100 n -b0 o -b0 p -0q -sFull64\x20(0) r -0s -1t -1u -0v -s0 w -b10 x -b11 y -b100 z -b0 { -b0 | -0} -sFull64\x20(0) ~ -0!" -1"" -1#" -0$" -s0 %" -b10 &" +sLoad\x20(0) e +0f +b1 g +b0 h +sHdlSome\x20(1) i +sHdlNone\x20(0) j +b10 k +b11 l +b100 m +b1001000110100 n +0o +0p +b1 q +b0 r +sHdlSome\x20(1) s +sHdlNone\x20(0) t +b10 u +b11 v +b100 w +b1001000110100 x +0y +1z +b1000000000000 { +1| +sHdlSome\x20(1) } +sAluBranch\x20(0) ~ +sLogical\x20(2) !" +s0 "" +b10 #" +b0 $" +sHdlNone\x20(0) %" +sHdlSome\x20(1) &" b11 '" b100 (" b0 )" b0 *" 0+" sFull64\x20(0) ," -b110 -" -sReadL2Reg\x20(0) ." +0-" +1." 1/" -b10 0" -b11 1" -b100 2" +00" +s0 1" +b10 2" b0 3" -b0 4" -05" -16" -b10 7" -b11 8" -b100 9" -b0 :" -b0 ;" +sHdlNone\x20(0) 4" +sHdlSome\x20(1) 5" +b11 6" +b100 7" +b0 8" +b0 9" +0:" +sFull64\x20(0) ;" 0<" -sLoad\x20(0) =" +1=" 1>" -b10 ?" -b11 @" -b100 A" +0?" +s0 @" +b10 A" b0 B" -b0 C" -0D" -1E" -b10 F" -b11 G" -b100 H" -b0 I" -b0 J" -0K" -0L" -b1000000000100 M" -1N" -sHdlNone\x20(0) O" -sTrap\x20(0) P" -1Q" -1R" -0S" -sHdlSome\x20(1) T" -0U" -sHdlNone\x20(0) V" -0W" -sAluBranch\x20(0) X" -1Y" -sHdlSome\x20(1) Z" -0[" -0\" -sAluBranch\x20(0) ]" -1^" -sHdlNone\x20(0) _" +sHdlNone\x20(0) C" +sHdlSome\x20(1) D" +b11 E" +b100 F" +b0 G" +b0 H" +0I" +sFull64\x20(0) J" +b110 K" +sReadL2Reg\x20(0) L" +1M" +b10 N" +b0 O" +sHdlNone\x20(0) P" +sHdlSome\x20(1) Q" +b11 R" +b100 S" +b0 T" +b0 U" +0V" +1W" +b10 X" +b0 Y" +sHdlNone\x20(0) Z" +sHdlSome\x20(1) [" +b11 \" +b100 ]" +b0 ^" +b0 _" 0`" -0a" -0b" -1c" -0d" -1e" -0f" -1g" -sHdlNone\x20(0) h" +sLoad\x20(0) a" +1b" +b10 c" +b0 d" +sHdlNone\x20(0) e" +sHdlSome\x20(1) f" +b11 g" +b100 h" b0 i" -1j" -sHdlSome\x20(1) k" -b0 l" -1m" -0n" -0o" -0p" -0q" -0r" -0s" -0t" +b0 j" +0k" +1l" +b10 m" +b0 n" +sHdlNone\x20(0) o" +sHdlSome\x20(1) p" +b11 q" +b100 r" +b0 s" +b0 t" 0u" 0v" -0w" -0x" -0y" -0z" -0{" -0|" -0}" -sHdlNone\x20(0) ~" +b1000000000100 w" +1x" +sHdlNone\x20(0) y" +sTrap\x20(0) z" +1{" +b1 |" +1}" +0~" b0 !# -0"# -1## -0$# +b0 "# +b10 ## +1$# 0%# -1&# -0'# -0(# +b0 &# +b0 '# +b11 (# 1)# -b0 *# -0+# -1,# -0-# -0.# -1/# -00# -01# -12# -b0 3# +0*# +b0 +# +b0 ,# +b10 -# +1.# +0/# +b0 0# +b0 1# +b11 2# +13# 04# -15# +b0 5# b0 6# -07# -18# +b0 7# +08# 09# -0:# -1;# +b0 :# +b0 ;# 0<# 0=# -1># +0># b0 ?# -0@# -1A# +b0 @# +0A# 0B# 0C# -1D# -0E# +b0 D# +b0 E# 0F# -1G# -b0 H# -0I# -1J# -b0 K# +0G# +0H# +b0 I# +b0 J# +0K# 0L# -1M# +0M# b0 N# -sHdlSome\x20(1) O# -b0 P# +b0 O# +0P# 0Q# -1R# -sHdlNone\x20(0) S# +0R# +b0 S# b0 T# -1U# -sHdlSome\x20(1) V# -b0 W# -1X# +0U# +0V# +0W# +b0 X# +b0 Y# +1Z# +1[# +0\# +1]# +sHdlSome\x20(1) ^# +b0 _# +sHdlSome\x20(1) `# +b1 a# +sHdlSome\x20(1) b# +sAluBranch\x20(0) c# +sAddSub\x20(0) d# +s0 e# +b0 f# +b0 g# +b0 h# +b0 i# +b1001000110100 j# +0k# +sFull64\x20(0) l# +1m# +1n# +1o# +1p# +s0 q# +b0 r# +b0 s# +b0 t# +b0 u# +b1001000110100 v# +0w# +sFull64\x20(0) x# +1y# +1z# +1{# +1|# +s0 }# +b0 ~# +b0 !$ +b0 "$ +b0 #$ +b1001000110100 $$ +0%$ +sFull64\x20(0) &$ +b1111 '$ +sReadL2Reg\x20(0) ($ +0)$ +b0 *$ +b0 +$ +b0 ,$ +b0 -$ +b1001000110100 .$ +0/$ +00$ +b0 1$ +b0 2$ +b0 3$ +b0 4$ +b1001000110100 5$ +06$ +sLoad\x20(0) 7$ +08$ +b0 9$ +b0 :$ +b0 ;$ +b0 <$ +b1001000110100 =$ +0>$ +0?$ +b0 @$ +b0 A$ +b0 B$ +b0 C$ +b1001000110100 D$ +0E$ +sHdlSome\x20(1) F$ +sAluBranch\x20(0) G$ +sLogical\x20(2) H$ +s0 I$ +b0 J$ +b0 K$ +b0 L$ +b0 M$ +b0 N$ +0O$ +sFull64\x20(0) P$ +0Q$ +1R$ +1S$ +0T$ +s0 U$ +b0 V$ +b0 W$ +b0 X$ +b0 Y$ +b0 Z$ +0[$ +sFull64\x20(0) \$ +0]$ +1^$ +1_$ +0`$ +s0 a$ +b0 b$ +b0 c$ +b0 d$ +b0 e$ +b0 f$ +0g$ +sFull64\x20(0) h$ +b110 i$ +sReadL2Reg\x20(0) j$ +1k$ +b0 l$ +b0 m$ +b0 n$ +b0 o$ +b0 p$ +0q$ +1r$ +b0 s$ +b0 t$ +b0 u$ +b0 v$ +b0 w$ +0x$ +sLoad\x20(0) y$ +1z$ +b0 {$ +b0 |$ +b0 }$ +b0 ~$ +b0 !% +0"% +1#% +b0 $% +b0 %% +b0 &% +b0 '% +b0 (% +0)% +sHdlSome\x20(1) *% +b1 +% +b0 ,% +sHdlSome\x20(1) -% +b10 .% +b0 /% +b10 0% +sHdlSome\x20(1) 1% +b0 2% +b0 3% +b11 4% +sHdlSome\x20(1) 5% +b0 6% +b0 7% +b100 8% +sHdlSome\x20(1) 9% +b0 :% +b0 ;% +b10 <% +sHdlNone\x20(0) =% +b0 >% +b0 ?% +b11 @% +sHdlNone\x20(0) A% +b0 B% +b0 C% +b100 D% +sHdlNone\x20(0) E% +b0 F% +b0 G% +sAluBranch\x20(0) H% +1I% +1J% +b1 K% +b0 L% +sHdlSome\x20(1) M% +sHdlNone\x20(0) N% +b1 O% +b0 P% +sHdlSome\x20(1) Q% +sHdlNone\x20(0) R% +b1 S% +b0 T% +sHdlSome\x20(1) U% +sHdlNone\x20(0) V% +b1 W% +b0 X% +sHdlSome\x20(1) Y% +sHdlNone\x20(0) Z% +sAluBranch\x20(0) [% +sAddSub\x20(0) \% +s0 ]% +b0 ^% +b0 _% +b0 `% +b0 a% +b1001000110100 b% +0c% +sFull64\x20(0) d% +1e% +1f% +1g% +1h% +s0 i% +b0 j% +b0 k% +b0 l% +b0 m% +b1001000110100 n% +0o% +sFull64\x20(0) p% +1q% +1r% +1s% +1t% +s0 u% +b0 v% +b0 w% +b0 x% +b0 y% +b1001000110100 z% +0{% +sFull64\x20(0) |% +b1111 }% +sReadL2Reg\x20(0) ~% +0!& +b0 "& +b0 #& +b0 $& +b0 %& +b1001000110100 && +0'& +0(& +b0 )& +b0 *& +b0 +& +b0 ,& +b1001000110100 -& +0.& +sLoad\x20(0) /& +00& +b0 1& +b0 2& +b0 3& +b0 4& +b1001000110100 5& +06& +07& +b0 8& +b0 9& +b0 :& +b0 ;& +b1001000110100 <& +0=& +sAddSub\x20(0) >& +s0 ?& +b0 @& +b0 A& +b0 B& +b0 C& +b1001000110100 D& +0E& +sFull64\x20(0) F& +1G& +1H& +1I& +1J& +s0 K& +b0 L& +b0 M& +b0 N& +b0 O& +b1001000110100 P& +0Q& +sFull64\x20(0) R& +1S& +1T& +1U& +1V& +s0 W& +b0 X& +b0 Y& +b0 Z& +b0 [& +b1001000110100 \& +0]& +sFull64\x20(0) ^& +b1111 _& +b0 `& +b0 a& +b0 b& +b0 c& +b0 d& +b0 e& +b0 f& +b0 g& +b0 h& +b0 i& +b0 j& +b0 k& +b0 l& +b0 m& +sReadL2Reg\x20(0) n& +0o& +b0 p& +b0 q& +b0 r& +b100 s& +b1001000110100 t& +0u& +0v& +b0 w& +b0 x& +b0 y& +b100 z& +b1001000110100 {& +0|& +b0 }& +b0 ~& +sLoad\x20(0) !' +0"' +b0 #' +b0 $' +b0 %' +b100 &' +b1001000110100 '' +0(' +0)' +b0 *' +b0 +' +b0 ,' +b100 -' +b1001000110100 .' +0/' +b0 0' +b0 1' +sHdlSome\x20(1) 2' +b0 3' +b0 4' +sHdlSome\x20(1) 5' +b1 6' +b1 7' +sHdlSome\x20(1) 8' +b0 9' +b11 :' +sHdlSome\x20(1) ;' +b0 <' +b0 =' +b1 >' +b0 ?' +sHdlSome\x20(1) @' +sHdlNone\x20(0) A' +b1 B' +b0 C' +sHdlSome\x20(1) D' +sHdlNone\x20(0) E' +b1 F' +b0 G' +sHdlSome\x20(1) H' +sHdlNone\x20(0) I' +b1 J' +b0 K' +sHdlSome\x20(1) L' +sHdlNone\x20(0) M' +b11111110 N' +b0 O' +b100 P' +sHdlSome\x20(1) Q' +b0 R' +b0 S' +b1 T' +b0 U' +sHdlSome\x20(1) V' +sHdlNone\x20(0) W' +b1 X' +b0 Y' +sHdlSome\x20(1) Z' +sHdlNone\x20(0) [' +b1 \' +b0 ]' +sHdlSome\x20(1) ^' +sHdlNone\x20(0) _' +b1 `' +b0 a' +sHdlSome\x20(1) b' +sHdlNone\x20(0) c' +b11111110 d' +b0 e' +b0 f' +sHdlNone\x20(0) g' +b0 h' +b0 i' +b1 j' +b0 k' +sHdlSome\x20(1) l' +sHdlNone\x20(0) m' +b1 n' +b0 o' +sHdlSome\x20(1) p' +sHdlNone\x20(0) q' +b1 r' +b0 s' +sHdlSome\x20(1) t' +sHdlNone\x20(0) u' +b1 v' +b0 w' +sHdlSome\x20(1) x' +sHdlNone\x20(0) y' +b11111110 z' +b0 {' +b11 |' +sHdlNone\x20(0) }' +b0 ~' +b0 !( +b1 "( +b0 #( +sHdlSome\x20(1) $( +sHdlNone\x20(0) %( +b1 &( +b0 '( +sHdlSome\x20(1) (( +sHdlNone\x20(0) )( +b1 *( +b0 +( +sHdlSome\x20(1) ,( +sHdlNone\x20(0) -( +b1 .( +b0 /( +sHdlSome\x20(1) 0( +sHdlNone\x20(0) 1( +b11111110 2( +b0 3( +b100 4( +sHdlNone\x20(0) 5( +b0 6( +b0 7( +b1 8( +b0 9( +sHdlSome\x20(1) :( +sHdlNone\x20(0) ;( +b1 <( +b0 =( +sHdlSome\x20(1) >( +sHdlNone\x20(0) ?( +b1 @( +b0 A( +sHdlSome\x20(1) B( +sHdlNone\x20(0) C( +b1 D( +b0 E( +sHdlSome\x20(1) F( +sHdlNone\x20(0) G( +b11111110 H( +b0 I( +b0 J( +sHdlNone\x20(0) K( +b0 L( +b0 M( +b1 N( +b0 O( +sHdlSome\x20(1) P( +sHdlNone\x20(0) Q( +b1 R( +b0 S( +sHdlSome\x20(1) T( +sHdlNone\x20(0) U( +b1 V( +b0 W( +sHdlSome\x20(1) X( +sHdlNone\x20(0) Y( +b1 Z( +b0 [( +sHdlSome\x20(1) \( +sHdlNone\x20(0) ]( +b11111110 ^( +b0 _( +sAluBranch\x20(0) `( +1a( +1b( +b10 c( +b0 d( +sHdlNone\x20(0) e( +sHdlSome\x20(1) f( +b10 g( +b0 h( +sHdlNone\x20(0) i( +sHdlSome\x20(1) j( +b10 k( +b0 l( +sHdlNone\x20(0) m( +sHdlSome\x20(1) n( +b10 o( +b0 p( +sHdlNone\x20(0) q( +sHdlSome\x20(1) r( +sAluBranch\x20(0) s( +sLogical\x20(2) t( +s0 u( +b0 v( +b0 w( +b0 x( +b0 y( +b0 z( +0{( +sFull64\x20(0) |( +0}( +1~( +1!) +0") +s0 #) +b0 $) +b0 %) +b0 &) +b0 ') +b0 () +0)) +sFull64\x20(0) *) +0+) +1,) +1-) +0.) +s0 /) +b0 0) +b0 1) +b0 2) +b0 3) +b0 4) +05) +sFull64\x20(0) 6) +b110 7) +sReadL2Reg\x20(0) 8) +19) +b0 :) +b0 ;) +b0 <) +b0 =) +b0 >) +0?) +1@) +b0 A) +b0 B) +b0 C) +b0 D) +b0 E) +0F) +sLoad\x20(0) G) +1H) +b0 I) +b0 J) +b0 K) +b0 L) +b0 M) +0N) +1O) +b0 P) +b0 Q) +b0 R) +b0 S) +b0 T) +0U) +sLogical\x20(2) V) +s0 W) +b0 X) +b0 Y) +b0 Z) +b0 [) +b0 \) +0]) +sFull64\x20(0) ^) +0_) +1`) +1a) +0b) +s0 c) +b0 d) +b0 e) +b0 f) +b0 g) +b0 h) +0i) +sFull64\x20(0) j) +0k) +1l) +1m) +0n) +s0 o) +b0 p) +b0 q) +b0 r) +b0 s) +b0 t) +0u) +sFull64\x20(0) v) +b110 w) +b0 x) +b0 y) +b0 z) +b0 {) +b0 |) +b0 }) +b0 ~) +b0 !* +b0 "* +b0 #* +b0 $* +b0 %* +b0 &* +b0 '* +sReadL2Reg\x20(0) (* +1)* +b0 ** +b0 +* +b0 ,* +b0 -* +b0 .* +0/* +10* +b0 1* +b0 2* +b0 3* +b0 4* +b0 5* +06* +b0 7* +b0 8* +sLoad\x20(0) 9* +1:* +b0 ;* +b0 <* +b0 =* +b0 >* +b0 ?* +0@* +1A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +0G* +b0 H* +b0 I* +sHdlNone\x20(0) J* +b0 K* +b0 L* +sHdlSome\x20(1) M* +b1 N* +b1 O* +sHdlSome\x20(1) P* +b1 Q* +0R* +1S* +sHdlSome\x20(1) T* +sAddSub\x20(0) U* +s0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b1001000110100 [* +0\* +sFull64\x20(0) ]* +1^* +1_* +1`* +1a* +s0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b1001000110100 g* +0h* +sFull64\x20(0) i* +1j* +1k* +1l* +1m* +s0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b1001000110100 s* +0t* +sFull64\x20(0) u* +b1111 v* +1w* +0x* +1y* +sHdlSome\x20(1) z* +sAddSub\x20(0) {* +s0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +b1001000110100 #+ +0$+ +sFull64\x20(0) %+ +1&+ +1'+ +1(+ +1)+ +s0 *+ +b0 ++ +b0 ,+ +b0 -+ +b0 .+ +b1001000110100 /+ +00+ +sFull64\x20(0) 1+ +12+ +13+ +14+ +15+ +s0 6+ +b0 7+ +b0 8+ +b0 9+ +b0 :+ +b1001000110100 ;+ +0<+ +sFull64\x20(0) =+ +b1111 >+ +1?+ +0@+ +1A+ +sHdlNone\x20(0) B+ +b0 C+ +1D+ +sHdlSome\x20(1) E+ +b0 F+ +1G+ +0H+ +0I+ +0J+ +0K+ +0L+ +0M+ +0N+ +0O+ +0P+ +0Q+ +0R+ +0S+ +0T+ +0U+ +0V+ +0W+ +sHdlNone\x20(0) X+ +b0 Y+ +0Z+ +1[+ +0\+ +0]+ +1^+ +0_+ +0`+ +1a+ +b0 b+ +0c+ +1d+ +0e+ +0f+ +1g+ +0h+ +0i+ +1j+ +b0 k+ +0l+ +1m+ +b0 n+ +0o+ +1p+ +0q+ +0r+ +1s+ +0t+ +0u+ +1v+ +b0 w+ +0x+ +1y+ +0z+ +0{+ +1|+ +0}+ +0~+ +1!, +b0 ", +0#, +1$, +b0 %, +0&, +1', +b0 (, +sHdlSome\x20(1) ), +b0 *, +0+, +1,, +sHdlNone\x20(0) -, +b0 ., +1/, +sHdlSome\x20(1) 0, +b0 1, +12, +sHdlSome\x20(1) 3, +sAddSub\x20(0) 4, +s0 5, +b0 6, +b0 7, +b0 8, +b0 9, +b1001000110100 :, +0;, +sFull64\x20(0) <, +1=, +1>, +1?, +1@, +s0 A, +b0 B, +b0 C, +b0 D, +b0 E, +b1001000110100 F, +0G, +sFull64\x20(0) H, +1I, +1J, +1K, +1L, +s0 M, +b0 N, +b0 O, +b0 P, +b0 Q, +b1001000110100 R, +0S, +sFull64\x20(0) T, +b1111 U, +sHdlSome\x20(1) V, +sAddSub\x20(0) W, +s0 X, +b0 Y, +b0 Z, +b0 [, +b0 \, +b1001000110100 ], +0^, +sFull64\x20(0) _, +1`, +1a, +1b, +1c, +s0 d, +b0 e, +b0 f, +b0 g, +b0 h, +b1001000110100 i, +0j, +sFull64\x20(0) k, +1l, +1m, +1n, +1o, +s0 p, +b0 q, +b0 r, +b0 s, +b0 t, +b1001000110100 u, +0v, +sFull64\x20(0) w, +b1111 x, +sHdlSome\x20(1) y, +sLogical\x20(2) z, +s0 {, +b0 |, +b0 }, +b0 ~, +b0 !- +b0 "- +0#- +sFull64\x20(0) $- +0%- +1&- +1'- +0(- +s0 )- +b0 *- +b0 +- +b0 ,- +b0 -- +b0 .- +0/- +sFull64\x20(0) 0- +01- +12- +13- +04- +s0 5- +b0 6- +b0 7- +b0 8- +b0 9- +b0 :- +0;- +sFull64\x20(0) <- +b110 =- +sHdlSome\x20(1) >- +sLogical\x20(2) ?- +s0 @- +b0 A- +b0 B- +b0 C- +b0 D- +b0 E- +0F- +sFull64\x20(0) G- +0H- +1I- +1J- +0K- +s0 L- +b0 M- +b0 N- +b0 O- +b0 P- +b0 Q- +0R- +sFull64\x20(0) S- +0T- +1U- +1V- +0W- +s0 X- +b0 Y- +b0 Z- +b0 [- +b0 \- +b0 ]- +0^- +sFull64\x20(0) _- +b110 `- +0a- +1b- +sHdlSome\x20(1) c- +sLogical\x20(2) d- +s0 e- +b0 f- +b0 g- +b0 h- +b0 i- +b0 j- +0k- +sFull64\x20(0) l- +0m- +1n- +1o- +0p- +s0 q- +b0 r- +b0 s- +b0 t- +b0 u- +b0 v- +0w- +sFull64\x20(0) x- +0y- +1z- +1{- +0|- +s0 }- +b0 ~- +b0 !. +b0 ". +b0 #. +b0 $. +0%. +sFull64\x20(0) &. +b110 '. +1(. +0). +1*. +sHdlSome\x20(1) +. +sLogical\x20(2) ,. +s0 -. +b0 .. +b0 /. +b0 0. +b0 1. +b0 2. +03. +sFull64\x20(0) 4. +05. +16. +17. +08. +s0 9. +b0 :. +b0 ;. +b0 <. +b0 =. +b0 >. +0?. +sFull64\x20(0) @. +0A. +1B. +1C. +0D. +s0 E. +b0 F. +b0 G. +b0 H. +b0 I. +b0 J. +0K. +sFull64\x20(0) L. +b110 M. +1N. +0O. +1P. +sHdlNone\x20(0) Q. +b0 R. +1S. +sHdlSome\x20(1) T. +b0 U. +1V. +0W. +0X. +0Y. +0Z. +0[. +0\. +0]. +0^. +0_. +0`. +0a. +0b. +0c. +0d. +0e. +0f. +sHdlNone\x20(0) g. +b0 h. +0i. +1j. +0k. +0l. +1m. +0n. +0o. +1p. +b0 q. +0r. +1s. +0t. +0u. +1v. +0w. +0x. +1y. +b0 z. +0{. +1|. +b0 }. +0~. +1!/ +0"/ +0#/ +1$/ +0%/ +0&/ +1'/ +b0 (/ +0)/ +1*/ +0+/ +0,/ +1-/ +0./ +0// +10/ +b0 1/ +02/ +13/ +b0 4/ +05/ +16/ +b0 7/ +sHdlSome\x20(1) 8/ +b0 9/ +0:/ +1;/ +sHdlNone\x20(0) / +sHdlSome\x20(1) ?/ +b0 @/ +1A/ +sHdlSome\x20(1) B/ +sAddSub\x20(0) C/ +s0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b1001000110100 I/ +0J/ +sFull64\x20(0) K/ +1L/ +1M/ +1N/ +1O/ +s0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b1001000110100 U/ +0V/ +sFull64\x20(0) W/ +1X/ +1Y/ +1Z/ +1[/ +s0 \/ +b0 ]/ +b0 ^/ +b0 _/ +b0 `/ +b1001000110100 a/ +0b/ +sFull64\x20(0) c/ +b1111 d/ +sHdlSome\x20(1) e/ +sAddSub\x20(0) f/ +s0 g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b1001000110100 l/ +0m/ +sFull64\x20(0) n/ +1o/ +1p/ +1q/ +1r/ +s0 s/ +b0 t/ +b0 u/ +b0 v/ +b0 w/ +b1001000110100 x/ +0y/ +sFull64\x20(0) z/ +1{/ +1|/ +1}/ +1~/ +s0 !0 +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b1001000110100 &0 +0'0 +sFull64\x20(0) (0 +b1111 )0 +sHdlSome\x20(1) *0 +sLogical\x20(2) +0 +s0 ,0 +b0 -0 +b0 .0 +b0 /0 +b0 00 +b0 10 +020 +sFull64\x20(0) 30 +040 +150 +160 +070 +s0 80 +b0 90 +b0 :0 +b0 ;0 +b0 <0 +b0 =0 +0>0 +sFull64\x20(0) ?0 +0@0 +1A0 +1B0 +0C0 +s0 D0 +b0 E0 +b0 F0 +b0 G0 +b0 H0 +b0 I0 +0J0 +sFull64\x20(0) K0 +b110 L0 +sHdlSome\x20(1) M0 +sLogical\x20(2) N0 +s0 O0 +b0 P0 +b0 Q0 +b0 R0 +b0 S0 +b0 T0 +0U0 +sFull64\x20(0) V0 +0W0 +1X0 +1Y0 +0Z0 +s0 [0 +b0 \0 +b0 ]0 +b0 ^0 +b0 _0 +b0 `0 +0a0 +sFull64\x20(0) b0 +0c0 +1d0 +1e0 +0f0 +s0 g0 +b0 h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +0m0 +sFull64\x20(0) n0 +b110 o0 $end #500000 1! -1b" -1d" -1f" -1Q# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1+, +1a- +1). +1O. +1:/ #1000000 0! 0" -0b" -0c" -0d" -0e" -0f" -0g" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# 0R# +0W# +0R* +0S* +0x* +0y* +0@+ +0A+ +0+, +0,, +0a- +0b- +0). +0*. +0O. +0P. +0:/ +0;/ #1500000 1! -1b" -1d" -1f" -1n" -1Q# -b1 l" -1"# -0## -1$# -1(# -b1 *# +1~" +1%# +1*# +1/# 14# -b1 6# -1L# -b1 N# -b1 P# -b1 W# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1H+ +1+, +1a- +1). +1O. +1W. +1:/ +b1 f# +b1 r# +b1 ~# +b1 *$ +b1 1$ +b1 9$ +b1 @$ +b1 J$ +b1 V$ +b1 b$ +b1 l$ +b1 s$ +b1 {$ +b1 $% +b1 ,% +b1 /% +b1 ^% +b1 j% +b1 v% +b1 "& +b1 )& +b1 1& +b1 8& +b1 @& +b1 L& +b1 X& +b1 p& +b1 w& +b1 #' +b1 *' +b1 v( +b1 $) +b1 0) +b1 :) +b1 A) +b1 I) +b1 P) +b1 X) +b1 d) +b1 p) +b1 ** +b1 1* +b1 ;* +b1 B* +b1 W* +b1 c* +b1 o* +b1 }* +b1 ++ +b1 7+ +b1 F+ +1Z+ +0[+ +1\+ +1`+ +b1 b+ +1l+ +b1 n+ +1&, +b1 (, +b1 *, +b1 1, +b1 6, +b1 B, +b1 N, +b1 Y, +b1 e, +b1 q, +b1 |, +b1 *- +b1 6- +b1 A- +b1 M- +b1 Y- +b1 f- +b1 r- +b1 ~- +b1 .. +b1 :. +b1 F. +b1 U. +1i. +0j. +1k. +1o. +b1 q. +1{. +b1 }. +15/ +b1 7/ +b1 9/ +b1 @/ +b1 E/ +b1 Q/ +b1 ]/ +b1 h/ +b1 t/ +b1 "0 +b1 -0 +b1 90 +b1 E0 +b1 P0 +b1 \0 +b1 h0 #2000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #2500000 1! -1b" -1d" -1f" -1o" -1Q# -b10 l" -0"# -0(# -b10 *# -04# -b10 6# -0L# -b10 N# -b10 P# -b10 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1I+ +1+, +1a- +1). +1O. +1X. +1:/ +b10 f# +b10 r# +b10 ~# +b10 *$ +b10 1$ +b10 9$ +b10 @$ +b10 J$ +b10 V$ +b10 b$ +b10 l$ +b10 s$ +b10 {$ +b10 $% +b10 ,% +b10 /% +b10 ^% +b10 j% +b10 v% +b10 "& +b10 )& +b10 1& +b10 8& +b10 @& +b10 L& +b10 X& +b10 p& +b10 w& +b10 #' +b10 *' +b10 v( +b10 $) +b10 0) +b10 :) +b10 A) +b10 I) +b10 P) +b10 X) +b10 d) +b10 p) +b10 ** +b10 1* +b10 ;* +b10 B* +b10 W* +b10 c* +b10 o* +b10 }* +b10 ++ +b10 7+ +b10 F+ +0Z+ +0`+ +b10 b+ +0l+ +b10 n+ +0&, +b10 (, +b10 *, +b10 1, +b10 6, +b10 B, +b10 N, +b10 Y, +b10 e, +b10 q, +b10 |, +b10 *- +b10 6- +b10 A- +b10 M- +b10 Y- +b10 f- +b10 r- +b10 ~- +b10 .. +b10 :. +b10 F. +b10 U. +0i. +0o. +b10 q. +0{. +b10 }. +05/ +b10 7/ +b10 9/ +b10 @/ +b10 E/ +b10 Q/ +b10 ]/ +b10 h/ +b10 t/ +b10 "0 +b10 -0 +b10 90 +b10 E0 +b10 P0 +b10 \0 +b10 h0 #3000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #3500000 1! -1b" -1d" -1f" -1p" -1Q# -b11 l" +1~" 1%# -0&# -1'# -1(# -0)# -b11 *# +1*# +1/# 14# -b11 6# -1L# -b11 N# -b11 P# -b11 W# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1J+ +1+, +1a- +1). +1O. +1Y. +1:/ +b11 f# +b11 r# +b11 ~# +b11 *$ +b11 1$ +b11 9$ +b11 @$ +b11 J$ +b11 V$ +b11 b$ +b11 l$ +b11 s$ +b11 {$ +b11 $% +b11 ,% +b11 /% +b11 ^% +b11 j% +b11 v% +b11 "& +b11 )& +b11 1& +b11 8& +b11 @& +b11 L& +b11 X& +b11 p& +b11 w& +b11 #' +b11 *' +b11 v( +b11 $) +b11 0) +b11 :) +b11 A) +b11 I) +b11 P) +b11 X) +b11 d) +b11 p) +b11 ** +b11 1* +b11 ;* +b11 B* +b11 W* +b11 c* +b11 o* +b11 }* +b11 ++ +b11 7+ +b11 F+ +1]+ +0^+ +1_+ +1`+ +0a+ +b11 b+ +1l+ +b11 n+ +1&, +b11 (, +b11 *, +b11 1, +b11 6, +b11 B, +b11 N, +b11 Y, +b11 e, +b11 q, +b11 |, +b11 *- +b11 6- +b11 A- +b11 M- +b11 Y- +b11 f- +b11 r- +b11 ~- +b11 .. +b11 :. +b11 F. +b11 U. +1l. +0m. +1n. +1o. +0p. +b11 q. +1{. +b11 }. +15/ +b11 7/ +b11 9/ +b11 @/ +b11 E/ +b11 Q/ +b11 ]/ +b11 h/ +b11 t/ +b11 "0 +b11 -0 +b11 90 +b11 E0 +b11 P0 +b11 \0 +b11 h0 #4000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #4500000 1! -1b" -1d" -1f" -1q" -1Q# -b100 l" -0%# -0(# -04# -b100 6# -0L# -b100 N# -b100 P# -b100 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1K+ +1+, +1a- +1). +1O. +1Z. +1:/ +b100 f# +b100 r# +b100 ~# +b100 *$ +b100 1$ +b100 9$ +b100 @$ +b100 J$ +b100 V$ +b100 b$ +b100 l$ +b100 s$ +b100 {$ +b100 $% +b100 ,% +b100 /% +b100 ^% +b100 j% +b100 v% +b100 "& +b100 )& +b100 1& +b100 8& +b100 @& +b100 L& +b100 X& +b100 p& +b100 w& +b100 #' +b100 *' +b100 v( +b100 $) +b100 0) +b100 :) +b100 A) +b100 I) +b100 P) +b100 X) +b100 d) +b100 p) +b100 ** +b100 1* +b100 ;* +b100 B* +b100 W* +b100 c* +b100 o* +b100 }* +b100 ++ +b100 7+ +b100 F+ +0]+ +0`+ +0l+ +b100 n+ +0&, +b100 (, +b100 *, +b100 1, +b100 6, +b100 B, +b100 N, +b100 Y, +b100 e, +b100 q, +b100 |, +b100 *- +b100 6- +b100 A- +b100 M- +b100 Y- +b100 f- +b100 r- +b100 ~- +b100 .. +b100 :. +b100 F. +b100 U. +0l. +0o. +0{. +b100 }. +05/ +b100 7/ +b100 9/ +b100 @/ +b100 E/ +b100 Q/ +b100 ]/ +b100 h/ +b100 t/ +b100 "0 +b100 -0 +b100 90 +b100 E0 +b100 P0 +b100 \0 +b100 h0 #5000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #5500000 1! -1b" -1d" -1f" -1r" -1Q# -b101 l" -1+# -0,# -1-# -11# -b1 3# +1~" +1%# +1*# +1/# 14# -b101 6# -1L# -b101 N# -b101 P# -b101 W# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1L+ +1+, +1a- +1). +1O. +1[. +1:/ +b101 f# +b101 r# +b101 ~# +b101 *$ +b101 1$ +b101 9$ +b101 @$ +b101 J$ +b101 V$ +b101 b$ +b101 l$ +b101 s$ +b101 {$ +b101 $% +b101 ,% +b101 /% +b101 ^% +b101 j% +b101 v% +b101 "& +b101 )& +b101 1& +b101 8& +b101 @& +b101 L& +b101 X& +b101 p& +b101 w& +b101 #' +b101 *' +b101 v( +b101 $) +b101 0) +b101 :) +b101 A) +b101 I) +b101 P) +b101 X) +b101 d) +b101 p) +b101 ** +b101 1* +b101 ;* +b101 B* +b101 W* +b101 c* +b101 o* +b101 }* +b101 ++ +b101 7+ +b101 F+ +1c+ +0d+ +1e+ +1i+ +b1 k+ +1l+ +b101 n+ +1&, +b101 (, +b101 *, +b101 1, +b101 6, +b101 B, +b101 N, +b101 Y, +b101 e, +b101 q, +b101 |, +b101 *- +b101 6- +b101 A- +b101 M- +b101 Y- +b101 f- +b101 r- +b101 ~- +b101 .. +b101 :. +b101 F. +b101 U. +1r. +0s. +1t. +1x. +b1 z. +1{. +b101 }. +15/ +b101 7/ +b101 9/ +b101 @/ +b101 E/ +b101 Q/ +b101 ]/ +b101 h/ +b101 t/ +b101 "0 +b101 -0 +b101 90 +b101 E0 +b101 P0 +b101 \0 +b101 h0 #6000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #6500000 1! -1b" -1d" -1f" -1s" -1Q# -b110 l" -0+# -01# -b10 3# -04# -b110 6# -0L# -b110 N# -b110 P# -b110 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1M+ +1+, +1a- +1). +1O. +1\. +1:/ +b110 f# +b110 r# +b110 ~# +b110 *$ +b110 1$ +b110 9$ +b110 @$ +b110 J$ +b110 V$ +b110 b$ +b110 l$ +b110 s$ +b110 {$ +b110 $% +b110 ,% +b110 /% +b110 ^% +b110 j% +b110 v% +b110 "& +b110 )& +b110 1& +b110 8& +b110 @& +b110 L& +b110 X& +b110 p& +b110 w& +b110 #' +b110 *' +b110 v( +b110 $) +b110 0) +b110 :) +b110 A) +b110 I) +b110 P) +b110 X) +b110 d) +b110 p) +b110 ** +b110 1* +b110 ;* +b110 B* +b110 W* +b110 c* +b110 o* +b110 }* +b110 ++ +b110 7+ +b110 F+ +0c+ +0i+ +b10 k+ +0l+ +b110 n+ +0&, +b110 (, +b110 *, +b110 1, +b110 6, +b110 B, +b110 N, +b110 Y, +b110 e, +b110 q, +b110 |, +b110 *- +b110 6- +b110 A- +b110 M- +b110 Y- +b110 f- +b110 r- +b110 ~- +b110 .. +b110 :. +b110 F. +b110 U. +0r. +0x. +b10 z. +0{. +b110 }. +05/ +b110 7/ +b110 9/ +b110 @/ +b110 E/ +b110 Q/ +b110 ]/ +b110 h/ +b110 t/ +b110 "0 +b110 -0 +b110 90 +b110 E0 +b110 P0 +b110 \0 +b110 h0 #7000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #7500000 1! -1b" -1d" -1f" -1t" -1Q# -b111 l" -1.# -0/# -10# -11# -02# -b11 3# +1~" +1%# +1*# +1/# 14# -05# -b111 6# -1L# -b111 N# -b111 P# -b111 W# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1N+ +1+, +1a- +1). +1O. +1]. +1:/ +b111 f# +b111 r# +b111 ~# +b111 *$ +b111 1$ +b111 9$ +b111 @$ +b111 J$ +b111 V$ +b111 b$ +b111 l$ +b111 s$ +b111 {$ +b111 $% +b111 ,% +b111 /% +b111 ^% +b111 j% +b111 v% +b111 "& +b111 )& +b111 1& +b111 8& +b111 @& +b111 L& +b111 X& +b111 p& +b111 w& +b111 #' +b111 *' +b111 v( +b111 $) +b111 0) +b111 :) +b111 A) +b111 I) +b111 P) +b111 X) +b111 d) +b111 p) +b111 ** +b111 1* +b111 ;* +b111 B* +b111 W* +b111 c* +b111 o* +b111 }* +b111 ++ +b111 7+ +b111 F+ +1f+ +0g+ +1h+ +1i+ +0j+ +b11 k+ +1l+ +0m+ +b111 n+ +1&, +b111 (, +b111 *, +b111 1, +b111 6, +b111 B, +b111 N, +b111 Y, +b111 e, +b111 q, +b111 |, +b111 *- +b111 6- +b111 A- +b111 M- +b111 Y- +b111 f- +b111 r- +b111 ~- +b111 .. +b111 :. +b111 F. +b111 U. +1u. +0v. +1w. +1x. +0y. +b11 z. +1{. +0|. +b111 }. +15/ +b111 7/ +b111 9/ +b111 @/ +b111 E/ +b111 Q/ +b111 ]/ +b111 h/ +b111 t/ +b111 "0 +b111 -0 +b111 90 +b111 E0 +b111 P0 +b111 \0 +b111 h0 #8000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #8500000 1! -1b" -1d" -1f" -1u" -1Q# -b1000 l" -0.# -01# -04# -0L# -b1000 N# -b1000 P# -b1000 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1O+ +1+, +1a- +1). +1O. +1^. +1:/ +b1000 f# +b1000 r# +b1000 ~# +b1000 *$ +b1000 1$ +b1000 9$ +b1000 @$ +b1000 J$ +b1000 V$ +b1000 b$ +b1000 l$ +b1000 s$ +b1000 {$ +b1000 $% +b1000 ,% +b1000 /% +b1000 ^% +b1000 j% +b1000 v% +b1000 "& +b1000 )& +b1000 1& +b1000 8& +b1000 @& +b1000 L& +b1000 X& +b1000 p& +b1000 w& +b1000 #' +b1000 *' +b1000 v( +b1000 $) +b1000 0) +b1000 :) +b1000 A) +b1000 I) +b1000 P) +b1000 X) +b1000 d) +b1000 p) +b1000 ** +b1000 1* +b1000 ;* +b1000 B* +b1000 W* +b1000 c* +b1000 o* +b1000 }* +b1000 ++ +b1000 7+ +b1000 F+ +0f+ +0i+ +0l+ +0&, +b1000 (, +b1000 *, +b1000 1, +b1000 6, +b1000 B, +b1000 N, +b1000 Y, +b1000 e, +b1000 q, +b1000 |, +b1000 *- +b1000 6- +b1000 A- +b1000 M- +b1000 Y- +b1000 f- +b1000 r- +b1000 ~- +b1000 .. +b1000 :. +b1000 F. +b1000 U. +0u. +0x. +0{. +05/ +b1000 7/ +b1000 9/ +b1000 @/ +b1000 E/ +b1000 Q/ +b1000 ]/ +b1000 h/ +b1000 t/ +b1000 "0 +b1000 -0 +b1000 90 +b1000 E0 +b1000 P0 +b1000 \0 +b1000 h0 #9000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #9500000 1! -1b" -1d" -1f" -1v" -1Q# -b1001 l" -17# -08# +1~" +1%# +1*# +1/# +14# 19# -1=# -b1 ?# -1I# -b1 K# -1L# -b1001 N# -b1001 P# -b1001 W# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1P+ +1+, +1a- +1). +1O. +1_. +1:/ +b1001 f# +b1001 r# +b1001 ~# +b1001 *$ +b1001 1$ +b1001 9$ +b1001 @$ +b1001 J$ +b1001 V$ +b1001 b$ +b1001 l$ +b1001 s$ +b1001 {$ +b1001 $% +b1001 ,% +b1001 /% +b1001 ^% +b1001 j% +b1001 v% +b1001 "& +b1001 )& +b1001 1& +b1001 8& +b1001 @& +b1001 L& +b1001 X& +b1001 p& +b1001 w& +b1001 #' +b1001 *' +b1001 v( +b1001 $) +b1001 0) +b1001 :) +b1001 A) +b1001 I) +b1001 P) +b1001 X) +b1001 d) +b1001 p) +b1001 ** +b1001 1* +b1001 ;* +b1001 B* +b1001 W* +b1001 c* +b1001 o* +b1001 }* +b1001 ++ +b1001 7+ +b1001 F+ +1o+ +0p+ +1q+ +1u+ +b1 w+ +1#, +b1 %, +1&, +b1001 (, +b1001 *, +b1001 1, +b1001 6, +b1001 B, +b1001 N, +b1001 Y, +b1001 e, +b1001 q, +b1001 |, +b1001 *- +b1001 6- +b1001 A- +b1001 M- +b1001 Y- +b1001 f- +b1001 r- +b1001 ~- +b1001 .. +b1001 :. +b1001 F. +b1001 U. +1~. +0!/ +1"/ +1&/ +b1 (/ +12/ +b1 4/ +15/ +b1001 7/ +b1001 9/ +b1001 @/ +b1001 E/ +b1001 Q/ +b1001 ]/ +b1001 h/ +b1001 t/ +b1001 "0 +b1001 -0 +b1001 90 +b1001 E0 +b1001 P0 +b1001 \0 +b1001 h0 #10000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #10500000 1! -1b" -1d" -1f" -1w" -1Q# -b1010 l" -07# -0=# -b10 ?# -0I# -b10 K# -0L# -b1010 N# -b1010 P# -b1010 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1Q+ +1+, +1a- +1). +1O. +1`. +1:/ +b1010 f# +b1010 r# +b1010 ~# +b1010 *$ +b1010 1$ +b1010 9$ +b1010 @$ +b1010 J$ +b1010 V$ +b1010 b$ +b1010 l$ +b1010 s$ +b1010 {$ +b1010 $% +b1010 ,% +b1010 /% +b1010 ^% +b1010 j% +b1010 v% +b1010 "& +b1010 )& +b1010 1& +b1010 8& +b1010 @& +b1010 L& +b1010 X& +b1010 p& +b1010 w& +b1010 #' +b1010 *' +b1010 v( +b1010 $) +b1010 0) +b1010 :) +b1010 A) +b1010 I) +b1010 P) +b1010 X) +b1010 d) +b1010 p) +b1010 ** +b1010 1* +b1010 ;* +b1010 B* +b1010 W* +b1010 c* +b1010 o* +b1010 }* +b1010 ++ +b1010 7+ +b1010 F+ +0o+ +0u+ +b10 w+ +0#, +b10 %, +0&, +b1010 (, +b1010 *, +b1010 1, +b1010 6, +b1010 B, +b1010 N, +b1010 Y, +b1010 e, +b1010 q, +b1010 |, +b1010 *- +b1010 6- +b1010 A- +b1010 M- +b1010 Y- +b1010 f- +b1010 r- +b1010 ~- +b1010 .. +b1010 :. +b1010 F. +b1010 U. +0~. +0&/ +b10 (/ +02/ +b10 4/ +05/ +b1010 7/ +b1010 9/ +b1010 @/ +b1010 E/ +b1010 Q/ +b1010 ]/ +b1010 h/ +b1010 t/ +b1010 "0 +b1010 -0 +b1010 90 +b1010 E0 +b1010 P0 +b1010 \0 +b1010 h0 #11000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #11500000 1! -1b" -1d" -1f" -1x" -1Q# -b1011 l" -1:# -0;# -1<# -1=# -0># -b11 ?# -1I# -b11 K# -1L# -b1011 N# -b1011 P# -b1011 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1R+ +1+, +1a- +1). +1O. +1a. +1:/ +b1011 f# +b1011 r# +b1011 ~# +b1011 *$ +b1011 1$ +b1011 9$ +b1011 @$ +b1011 J$ +b1011 V$ +b1011 b$ +b1011 l$ +b1011 s$ +b1011 {$ +b1011 $% +b1011 ,% +b1011 /% +b1011 ^% +b1011 j% +b1011 v% +b1011 "& +b1011 )& +b1011 1& +b1011 8& +b1011 @& +b1011 L& +b1011 X& +b1011 p& +b1011 w& +b1011 #' +b1011 *' +b1011 v( +b1011 $) +b1011 0) +b1011 :) +b1011 A) +b1011 I) +b1011 P) +b1011 X) +b1011 d) +b1011 p) +b1011 ** +b1011 1* +b1011 ;* +b1011 B* +b1011 W* +b1011 c* +b1011 o* +b1011 }* +b1011 ++ +b1011 7+ +b1011 F+ +1r+ +0s+ +1t+ +1u+ +0v+ +b11 w+ +1#, +b11 %, +1&, +b1011 (, +b1011 *, +b1011 1, +b1011 6, +b1011 B, +b1011 N, +b1011 Y, +b1011 e, +b1011 q, +b1011 |, +b1011 *- +b1011 6- +b1011 A- +b1011 M- +b1011 Y- +b1011 f- +b1011 r- +b1011 ~- +b1011 .. +b1011 :. +b1011 F. +b1011 U. +1#/ +0$/ +1%/ +1&/ +0'/ +b11 (/ +12/ +b11 4/ +15/ +b1011 7/ +b1011 9/ +b1011 @/ +b1011 E/ +b1011 Q/ +b1011 ]/ +b1011 h/ +b1011 t/ +b1011 "0 +b1011 -0 +b1011 90 +b1011 E0 +b1011 P0 +b1011 \0 +b1011 h0 #12000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #12500000 1! -1b" -1d" -1f" -1y" -1Q# -b1100 l" -0:# -0=# -0I# -b100 K# -0L# -b1100 N# -b1100 P# -b1100 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1S+ +1+, +1a- +1). +1O. +1b. +1:/ +b1100 f# +b1100 r# +b1100 ~# +b1100 *$ +b1100 1$ +b1100 9$ +b1100 @$ +b1100 J$ +b1100 V$ +b1100 b$ +b1100 l$ +b1100 s$ +b1100 {$ +b1100 $% +b1100 ,% +b1100 /% +b1100 ^% +b1100 j% +b1100 v% +b1100 "& +b1100 )& +b1100 1& +b1100 8& +b1100 @& +b1100 L& +b1100 X& +b1100 p& +b1100 w& +b1100 #' +b1100 *' +b1100 v( +b1100 $) +b1100 0) +b1100 :) +b1100 A) +b1100 I) +b1100 P) +b1100 X) +b1100 d) +b1100 p) +b1100 ** +b1100 1* +b1100 ;* +b1100 B* +b1100 W* +b1100 c* +b1100 o* +b1100 }* +b1100 ++ +b1100 7+ +b1100 F+ +0r+ +0u+ +0#, +b100 %, +0&, +b1100 (, +b1100 *, +b1100 1, +b1100 6, +b1100 B, +b1100 N, +b1100 Y, +b1100 e, +b1100 q, +b1100 |, +b1100 *- +b1100 6- +b1100 A- +b1100 M- +b1100 Y- +b1100 f- +b1100 r- +b1100 ~- +b1100 .. +b1100 :. +b1100 F. +b1100 U. +0#/ +0&/ +02/ +b100 4/ +05/ +b1100 7/ +b1100 9/ +b1100 @/ +b1100 E/ +b1100 Q/ +b1100 ]/ +b1100 h/ +b1100 t/ +b1100 "0 +b1100 -0 +b1100 90 +b1100 E0 +b1100 P0 +b1100 \0 +b1100 h0 #13000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #13500000 1! -1b" -1d" -1f" -1z" -1Q# -b1101 l" -1@# -0A# -1B# -1F# -b1 H# -1I# -b101 K# -1L# -b1101 N# -b1101 P# -b1101 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1T+ +1+, +1a- +1). +1O. +1c. +1:/ +b1101 f# +b1101 r# +b1101 ~# +b1101 *$ +b1101 1$ +b1101 9$ +b1101 @$ +b1101 J$ +b1101 V$ +b1101 b$ +b1101 l$ +b1101 s$ +b1101 {$ +b1101 $% +b1101 ,% +b1101 /% +b1101 ^% +b1101 j% +b1101 v% +b1101 "& +b1101 )& +b1101 1& +b1101 8& +b1101 @& +b1101 L& +b1101 X& +b1101 p& +b1101 w& +b1101 #' +b1101 *' +b1101 v( +b1101 $) +b1101 0) +b1101 :) +b1101 A) +b1101 I) +b1101 P) +b1101 X) +b1101 d) +b1101 p) +b1101 ** +b1101 1* +b1101 ;* +b1101 B* +b1101 W* +b1101 c* +b1101 o* +b1101 }* +b1101 ++ +b1101 7+ +b1101 F+ +1x+ +0y+ +1z+ +1~+ +b1 ", +1#, +b101 %, +1&, +b1101 (, +b1101 *, +b1101 1, +b1101 6, +b1101 B, +b1101 N, +b1101 Y, +b1101 e, +b1101 q, +b1101 |, +b1101 *- +b1101 6- +b1101 A- +b1101 M- +b1101 Y- +b1101 f- +b1101 r- +b1101 ~- +b1101 .. +b1101 :. +b1101 F. +b1101 U. +1)/ +0*/ +1+/ +1// +b1 1/ +12/ +b101 4/ +15/ +b1101 7/ +b1101 9/ +b1101 @/ +b1101 E/ +b1101 Q/ +b1101 ]/ +b1101 h/ +b1101 t/ +b1101 "0 +b1101 -0 +b1101 90 +b1101 E0 +b1101 P0 +b1101 \0 +b1101 h0 #14000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #14500000 1! -1b" -1d" -1f" -1{" -1Q# -b1110 l" -0@# -0F# -b10 H# -0I# -b110 K# -0L# -b1110 N# -b1110 P# -b1110 W# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1U+ +1+, +1a- +1). +1O. +1d. +1:/ +b1110 f# +b1110 r# +b1110 ~# +b1110 *$ +b1110 1$ +b1110 9$ +b1110 @$ +b1110 J$ +b1110 V$ +b1110 b$ +b1110 l$ +b1110 s$ +b1110 {$ +b1110 $% +b1110 ,% +b1110 /% +b1110 ^% +b1110 j% +b1110 v% +b1110 "& +b1110 )& +b1110 1& +b1110 8& +b1110 @& +b1110 L& +b1110 X& +b1110 p& +b1110 w& +b1110 #' +b1110 *' +b1110 v( +b1110 $) +b1110 0) +b1110 :) +b1110 A) +b1110 I) +b1110 P) +b1110 X) +b1110 d) +b1110 p) +b1110 ** +b1110 1* +b1110 ;* +b1110 B* +b1110 W* +b1110 c* +b1110 o* +b1110 }* +b1110 ++ +b1110 7+ +b1110 F+ +0x+ +0~+ +b10 ", +0#, +b110 %, +0&, +b1110 (, +b1110 *, +b1110 1, +b1110 6, +b1110 B, +b1110 N, +b1110 Y, +b1110 e, +b1110 q, +b1110 |, +b1110 *- +b1110 6- +b1110 A- +b1110 M- +b1110 Y- +b1110 f- +b1110 r- +b1110 ~- +b1110 .. +b1110 :. +b1110 F. +b1110 U. +0)/ +0// +b10 1/ +02/ +b110 4/ +05/ +b1110 7/ +b1110 9/ +b1110 @/ +b1110 E/ +b1110 Q/ +b1110 ]/ +b1110 h/ +b1110 t/ +b1110 "0 +b1110 -0 +b1110 90 +b1110 E0 +b1110 P0 +b1110 \0 +b1110 h0 #15000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #15500000 1! -1b" -1d" -1f" -1|" -1Q# -b1111 l" +1~" +1%# +1*# +1/# +14# +19# +1># 1C# -0D# -1E# -1F# -0G# -b11 H# -1I# -0J# -b111 K# -1L# -0M# -b1111 N# -b1111 P# -b1111 W# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1V+ +1+, +1a- +1). +1O. +1e. +1:/ +b1111 f# +b1111 r# +b1111 ~# +b1111 *$ +b1111 1$ +b1111 9$ +b1111 @$ +b1111 J$ +b1111 V$ +b1111 b$ +b1111 l$ +b1111 s$ +b1111 {$ +b1111 $% +b1111 ,% +b1111 /% +b1111 ^% +b1111 j% +b1111 v% +b1111 "& +b1111 )& +b1111 1& +b1111 8& +b1111 @& +b1111 L& +b1111 X& +b1111 p& +b1111 w& +b1111 #' +b1111 *' +b1111 v( +b1111 $) +b1111 0) +b1111 :) +b1111 A) +b1111 I) +b1111 P) +b1111 X) +b1111 d) +b1111 p) +b1111 ** +b1111 1* +b1111 ;* +b1111 B* +b1111 W* +b1111 c* +b1111 o* +b1111 }* +b1111 ++ +b1111 7+ +b1111 F+ +1{+ +0|+ +1}+ +1~+ +0!, +b11 ", +1#, +0$, +b111 %, +1&, +0', +b1111 (, +b1111 *, +b1111 1, +b1111 6, +b1111 B, +b1111 N, +b1111 Y, +b1111 e, +b1111 q, +b1111 |, +b1111 *- +b1111 6- +b1111 A- +b1111 M- +b1111 Y- +b1111 f- +b1111 r- +b1111 ~- +b1111 .. +b1111 :. +b1111 F. +b1111 U. +1,/ +0-/ +1./ +1// +00/ +b11 1/ +12/ +03/ +b111 4/ +15/ +06/ +b1111 7/ +b1111 9/ +b1111 @/ +b1111 E/ +b1111 Q/ +b1111 ]/ +b1111 h/ +b1111 t/ +b1111 "0 +b1111 -0 +b1111 90 +b1111 E0 +b1111 P0 +b1111 \0 +b1111 h0 #16000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #16500000 1! -1b" -1d" -1f" -1}" -1Q# -0R" -sHdlNone\x20(0) T" -sHdlNone\x20(0) Z" -sHdlNone\x20(0) k" -b0 l" -0m" -0C# -0F# -0I# -0L# -sHdlNone\x20(0) O# -b0 P# -sHdlNone\x20(0) V# -b0 W# -0X# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1W+ +1+, +1a- +1). +1O. +1f. +1:/ +b0 |" +0}" +b0 ## +0$# +b0 (# +0)# +b0 -# +0.# +b0 2# +03# +0Z# +0[# +0]# +sHdlNone\x20(0) ^# +sHdlNone\x20(0) `# +b0 a# +sHdlNone\x20(0) b# +b0 f# +b0 j# +0m# +0n# +0o# +0p# +b0 r# +b0 v# +0y# +0z# +0{# +0|# +b0 ~# +b0 $$ +b0 '$ +b0 *$ +b0 .$ +b0 1$ +b0 5$ +b0 9$ +b0 =$ +b0 @$ +b0 D$ +sHdlNone\x20(0) F$ +sAddSub\x20(0) H$ +b0 J$ +0R$ +0S$ +b0 V$ +0^$ +0_$ +b0 b$ +b0 i$ +0k$ +b0 l$ +0r$ +b0 s$ +0z$ +b0 {$ +0#% +b0 $% +sHdlNone\x20(0) *% +b0 +% +b0 ,% +sHdlNone\x20(0) -% +b0 .% +b0 /% +b0 0% +sHdlNone\x20(0) 1% +b0 4% +sHdlNone\x20(0) 5% +b0 8% +sHdlNone\x20(0) 9% +b0 <% +b0 @% +b0 D% +b0 ^% +b0 j% +b0 v% +b0 "& +b0 )& +b0 1& +b0 8& +b0 @& +b0 L& +b0 X& +b0 p& +b0 w& +b0 #' +b0 *' +sHdlNone\x20(0) 2' +sHdlNone\x20(0) 5' +b0 6' +sHdlNone\x20(0) 8' +b0 :' +sHdlNone\x20(0) ;' +b0 P' +sHdlNone\x20(0) Q' +b0 |' +b0 4( +b0 v( +b0 $) +b0 0) +b0 :) +b0 A) +b0 I) +b0 P) +b0 X) +b0 d) +b0 p) +b0 ** +b0 1* +b0 ;* +b0 B* +sHdlNone\x20(0) M* +b0 N* +sHdlNone\x20(0) P* +b0 Q* +sHdlNone\x20(0) T* +b0 W* +b0 [* +0^* +0_* +0`* +0a* +b0 c* +b0 g* +0j* +0k* +0l* +0m* +b0 o* +b0 s* +b0 v* +sHdlNone\x20(0) z* +b0 }* +b0 #+ +0&+ +0'+ +0(+ +0)+ +b0 ++ +b0 /+ +02+ +03+ +04+ +05+ +b0 7+ +b0 ;+ +b0 >+ +sHdlNone\x20(0) E+ +b0 F+ +0G+ +0{+ +0~+ +0#, +0&, +sHdlNone\x20(0) ), +b0 *, +sHdlNone\x20(0) 0, +b0 1, +02, +sHdlNone\x20(0) 3, +b0 6, +b0 :, +0=, +0>, +0?, +0@, +b0 B, +b0 F, +0I, +0J, +0K, +0L, +b0 N, +b0 R, +b0 U, +b0 Y, +b0 ], +0`, +0a, +0b, +0c, +b0 e, +b0 i, +0l, +0m, +0n, +0o, +b0 q, +b0 u, +b0 x, +sHdlNone\x20(0) y, +sAddSub\x20(0) z, +b0 |, +0&- +0'- +b0 *- +02- +03- +b0 6- +b0 =- +sAddSub\x20(0) ?- +b0 A- +0I- +0J- +b0 M- +0U- +0V- +b0 Y- +b0 `- +sHdlNone\x20(0) c- +sAddSub\x20(0) d- +b0 f- +0n- +0o- +b0 r- +0z- +0{- +b0 ~- +b0 '. +sHdlNone\x20(0) +. +sAddSub\x20(0) ,. +b0 .. +06. +07. +b0 :. +0B. +0C. +b0 F. +b0 M. +sHdlNone\x20(0) T. +b0 U. +0V. +0,/ +0// +02/ +05/ +sHdlNone\x20(0) 8/ +b0 9/ +sHdlNone\x20(0) ?/ +b0 @/ +0A/ +sHdlNone\x20(0) B/ +b0 E/ +b0 I/ +0L/ +0M/ +0N/ +0O/ +b0 Q/ +b0 U/ +0X/ +0Y/ +0Z/ +0[/ +b0 ]/ +b0 a/ +b0 d/ +b0 h/ +b0 l/ +0o/ +0p/ +0q/ +0r/ +b0 t/ +b0 x/ +0{/ +0|/ +0}/ +0~/ +b0 "0 +b0 &0 +b0 )0 +sHdlNone\x20(0) *0 +sAddSub\x20(0) +0 +b0 -0 +050 +060 +b0 90 +0A0 +0B0 +b0 E0 +b0 L0 +sAddSub\x20(0) N0 +b0 P0 +0X0 +0Y0 +b0 \0 +0d0 +0e0 +b0 h0 +b0 o0 #17000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #17500000 1! -1b" -1d" -1f" -1Q# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1+, +1a- +1). +1O. +1:/ #18000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #18500000 1! -1b" -1d" -1f" -1Q# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1+, +1a- +1). +1O. +1:/ #19000000 0! -0b" -0d" -0f" -0Q# +0~" +0%# +0*# +0/# +04# +09# +0># +0C# +0H# +0M# +0R# +0W# +0R* +0x* +0@+ +0+, +0a- +0). +0O. +0:/ #19500000 1! -1b" -1d" -1f" -1Q# +1~" +1%# +1*# +1/# +14# +19# +1># +1C# +1H# +1M# +1R# +1W# +1R* +1x* +1@+ +1+, +1a- +1). +1O. +1:/ #20000000 diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs index a09bb5d..671afaf 100644 --- a/crates/cpu/tests/reg_alloc.rs +++ b/crates/cpu/tests/reg_alloc.rs @@ -4,8 +4,8 @@ use cpu::{ config::CpuConfig, instruction::{ - AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, OutputIntegerMode, - COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH, + AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, + OutputIntegerMode, COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH, }, reg_alloc::{reg_alloc, FetchedDecodedMOp}, unit::UnitKind, @@ -23,7 +23,7 @@ use std::num::NonZeroUsize; #[test] fn test_reg_alloc() { let _n = SourceLocation::normalize_files_for_tests(); - let mut config = CpuConfig::new(vec![UnitKind::AluBranch]); + let mut config = CpuConfig::new(vec![UnitKind::AluBranch, UnitKind::AluBranch]); config.fetch_width = NonZeroUsize::new(2).unwrap(); let m = reg_alloc(&config); let mut sim = Simulation::new(m); @@ -38,14 +38,24 @@ fn test_reg_alloc() { HdlSome( #[hdl] FetchedDecodedMOp { - uop: MOp.AluBranch(MOp.AluBranch.AddSub( + mop: MOp.AluBranch(MOp.AluBranch.AddSub( #[hdl] AddSubMOp { alu_common: #[hdl] AluCommonMOp { common: CommonMOp::new( 0_hdl_u0, - 1u8, + #[hdl] + MOpDestReg { + normal_regs: #[hdl] + [ + #[hdl] + MOpRegNum { value: 1u8 }, + MOpRegNum::const_zero(), + ], + flag_regs: #[hdl] + [HdlSome(()), HdlNone()], + }, [2u8, 3u8, 4u8], 0x1234.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]), ), @@ -67,14 +77,22 @@ fn test_reg_alloc() { HdlSome( #[hdl] FetchedDecodedMOp { - uop: MOp.AluBranch(MOp.AluBranch.Logical( + mop: MOp.AluBranch(MOp.AluBranch.Logical( #[hdl] LogicalMOp { alu_common: #[hdl] AluCommonMOp { common: CommonMOp::new( 0_hdl_u0, - 2u8, + #[hdl] + MOpDestReg { + normal_regs: [ + #[hdl] + MOpRegNum { value: 2u8 }, + MOpRegNum::const_zero(), + ], + flag_regs: [HdlNone(), HdlSome(())], + }, [3u8, 4u8], SInt[COMMON_MOP_2_IMM_WIDTH].zero(), ), @@ -111,149 +129,2800 @@ fn test_reg_alloc() { "/test/reg_alloc.fir": r"FIRRTL version 3.2.0 circuit reg_alloc: type Ty0 = {clk: Clock, rst: Reset} - type Ty1 = {} - type Ty2 = {prefix_pad: UInt<0>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1} - type Ty3 = {|Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8|} - type Ty4 = {common: Ty2, output_integer_mode: Ty3} - type Ty5 = {alu_common: Ty4, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} - type Ty6 = {alu_common: Ty4, lut: UInt<4>} - type Ty7 = {|AddSub: Ty5, AddSubI: Ty5, Logical: Ty6|} - type Ty8 = {prefix_pad: UInt<1>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1} - type Ty9 = {common: Ty8} - type Ty10 = {|ReadL2Reg: Ty9, WriteL2Reg: Ty9|} - type Ty11 = {|Load: Ty8, Store: Ty8|} - type Ty12 = {|AluBranch: Ty7, L2RegisterFile: Ty10, LoadStore: Ty11|} - type Ty13 = {uop: Ty12, is_unrelated_pc: UInt<1>, pc: UInt<64>} - type Ty14 = {|HdlNone, HdlSome: Ty13|} - type Ty15 = {data: Ty14, flip ready: UInt<1>} - type Ty16 = {|Trap: Ty1, ICacheFlush|} + type Ty1 = {value: UInt<8>} + type Ty2 = {} + type Ty3 = {|HdlNone, HdlSome: Ty2|} + type Ty4 = {normal_regs: Ty1[2], flag_regs: Ty3[2]} + type Ty5 = {prefix_pad: UInt<0>, dest: Ty4, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} + type Ty6 = {|Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8|} + type Ty7 = {common: Ty5, output_integer_mode: Ty6} + type Ty8 = {alu_common: Ty7, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} + type Ty9 = {alu_common: Ty7, lut: UInt<4>} + type Ty10 = {|AddSub: Ty8, AddSubI: Ty8, Logical: Ty9|} + type Ty11 = {prefix_pad: UInt<1>, dest: Ty4, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} + type Ty12 = {common: Ty11} + type Ty13 = {|ReadL2Reg: Ty12, WriteL2Reg: Ty12|} + type Ty14 = {|Load: Ty11, Store: Ty11|} + type Ty15 = {|AluBranch: Ty10, L2RegisterFile: Ty13, LoadStore: Ty14|} + type Ty16 = {mop: Ty15, is_unrelated_pc: UInt<1>, pc: UInt<64>} type Ty17 = {|HdlNone, HdlSome: Ty16|} type Ty18 = {data: Ty17, flip ready: UInt<1>} - type Ty19 = {decoded_insns: Ty15[2], flip fetch_decode_special_op: Ty18} - type Ty20 = {value: UInt<1>} - type Ty21 = {|HdlNone, HdlSome: Ty20|} - type Ty22 = {|AluBranch, L2RegisterFile, LoadStore|} - type Ty23 = {flip cd: Ty0} - type Ty24 = {|HdlNone, HdlSome: UInt<4>|} - type Ty25 = {data: Ty24, flip ready: UInt<1>} - type Ty26 = {flip cd: Ty0, flip free_in: Ty25[1], alloc_out: Ty25[1]} - module reg_alloc: @[reg_alloc.rs 41:1] - input cd: Ty0 @[reg_alloc.rs 45:29] - input fetch_decode_interface: Ty19 @[reg_alloc.rs 48:11] - connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty16|}(HdlNone) @[reg_alloc.rs 50:5] - wire available_units: UInt<1>[1][2] @[reg_alloc.rs 57:9] - wire selected_unit_nums: Ty21[2] @[reg_alloc.rs 59:30] - connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9] - wire _array_literal_expr: UInt<1>[1] + type Ty19 = {|Trap: Ty2, ICacheFlush|} + type Ty20 = {|HdlNone, HdlSome: Ty19|} + type Ty21 = {data: Ty20, flip ready: UInt<1>} + type Ty22 = {decoded_insns: Ty18[2], flip fetch_decode_special_op: Ty21} + type Ty23 = {adj_value: UInt<2>} + type Ty24 = {value: UInt<4>} + type Ty25 = {unit_num: Ty23, unit_out_reg: Ty24} + type Ty26 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty25} + type Ty27 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<2>} + type Ty28 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<4>} + type Ty29 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: Ty25} + type Ty30 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<2>} + type Ty31 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<4>} + type Ty32 = {|HdlNone, HdlSome: UInt<2>|} + type Ty33 = {prefix_pad: UInt<0>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} + type Ty34 = {common: Ty33, output_integer_mode: Ty6} + type Ty35 = {alu_common: Ty34, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} + type Ty36 = {alu_common: Ty34, lut: UInt<4>} + type Ty37 = {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|} + type Ty38 = {prefix_pad: UInt<1>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} + type Ty39 = {common: Ty38} + type Ty40 = {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|} + type Ty41 = {|Load: Ty38, Store: Ty38|} + type Ty42 = {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|} + type Ty43 = {|HdlNone, HdlSome: Ty42|} + type Ty44 = {|HdlNone, HdlSome: Ty25|} + type Ty45 = {addr: Ty1, flip data: Ty44} + type Ty46 = {|AluBranch, L2RegisterFile, LoadStore|} + type Ty47 = {unit_num: UInt<2>, unit_out_reg: UInt<4>} + type Ty48 = {imm_low: UInt<25>, reversed_src: UInt<8>[0], imm_sign: SInt<1>} + type Ty49 = {imm_low: UInt<25>, reversed_src: UInt<0>, imm_sign: UInt<1>} + type Ty50 = {imm_low: UInt<25>, reversed_src: UInt<8>[1], imm_sign: SInt<1>} + type Ty51 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>} + type Ty52 = {|HdlNone, HdlSome: Ty37|} + type Ty53 = {data: Ty52, flip ready: UInt<1>} + type Ty54 = {flip cd: Ty0, flip `input`: Ty53} + type Ty55 = {|HdlNone, HdlSome: UInt<4>|} + type Ty56 = {data: Ty55, flip ready: UInt<1>} + type Ty57 = {flip cd: Ty0, flip free_in: Ty56[1], alloc_out: Ty56[1]} + module reg_alloc: @[reg_alloc.rs 43:1] + input cd: Ty0 @[reg_alloc.rs 47:29] + input fetch_decode_interface: Ty22 @[reg_alloc.rs 50:11] + mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 60:39] + data-type => UInt<2> + depth => 253 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + reader => r1 + reader => r2 + reader => r3 + reader => r4 + reader => r5 + mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 60:39] + data-type => UInt<4> + depth => 253 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + reader => r1 + reader => r2 + reader => r3 + reader => r4 + reader => r5 + mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 65:40] + data-type => UInt<2> + depth => 2 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + reader => r1 + reader => r2 + reader => r3 + reader => r4 + reader => r5 + mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 65:40] + data-type => UInt<4> + depth => 2 + read-latency => 0 + write-latency => 1 + read-under-write => old + reader => r0 + reader => r1 + reader => r2 + reader => r3 + reader => r4 + reader => r5 + wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 102:37] + wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 102:37] + wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 102:37] + wire rename_table_normal_mem_r3: Ty26 @[reg_alloc.rs 102:37] + wire rename_table_normal_mem_r4: Ty26 @[reg_alloc.rs 102:37] + wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r3.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r3.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r4.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r4.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r3.addr, rename_table_normal_mem_r3.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r3.clk, rename_table_normal_mem_r3.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r3.en, rename_table_normal_mem_r3.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r4.addr, rename_table_normal_mem_r4.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r4.clk, rename_table_normal_mem_r4.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r4.en, rename_table_normal_mem_r4.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r3.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r3.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r4.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r4.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r3.addr, rename_table_normal_mem_r3.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r3.clk, rename_table_normal_mem_r3.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r3.en, rename_table_normal_mem_r3.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r4.addr, rename_table_normal_mem_r4.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r4.clk, rename_table_normal_mem_r4.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r4.en, rename_table_normal_mem_r4.en @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 102:37] + connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r0: Ty29 @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r1: Ty29 @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r2: Ty29 @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r3: Ty29 @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r4: Ty29 @[reg_alloc.rs 102:37] + wire rename_table_special_mem_r5: Ty29 @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r3.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r3.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r4.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r4.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r5.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r3.addr, rename_table_special_mem_r3.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r3.clk, rename_table_special_mem_r3.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r3.en, rename_table_special_mem_r3.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r4.addr, rename_table_special_mem_r4.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r4.clk, rename_table_special_mem_r4.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r4.en, rename_table_special_mem_r4.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r5.addr, rename_table_special_mem_r5.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r5.clk, rename_table_special_mem_r5.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_num_adj_value.r5.en, rename_table_special_mem_r5.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r3.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r3.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r4.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r4.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_r5.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r3.addr, rename_table_special_mem_r3.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r3.clk, rename_table_special_mem_r3.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r3.en, rename_table_special_mem_r3.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r4.addr, rename_table_special_mem_r4.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r4.clk, rename_table_special_mem_r4.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r4.en, rename_table_special_mem_r4.en @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r5.addr, rename_table_special_mem_r5.addr @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r5.clk, rename_table_special_mem_r5.clk @[reg_alloc.rs 102:37] + connect rename_table_special_mem_unit_out_reg_value.r5.en, rename_table_special_mem_r5.en @[reg_alloc.rs 102:37] + connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 52:5] + wire available_units: UInt<1>[2][2] @[reg_alloc.rs 70:9] + wire selected_unit_indexes: Ty32[2] @[reg_alloc.rs 73:9] + wire renamed_mops: Ty43[2] @[reg_alloc.rs 75:24] + wire renamed_mops_out_reg: Ty44[2] @[reg_alloc.rs 77:32] + connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 79:9] + wire _array_literal_expr: UInt<1>[2] connect _array_literal_expr[0], UInt<1>(0h0) - connect available_units[0], _array_literal_expr @[reg_alloc.rs 65:9] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 70:9] + connect _array_literal_expr[1], UInt<1>(0h0) + connect available_units[0], _array_literal_expr @[reg_alloc.rs 83:9] + connect renamed_mops[0], {|HdlNone, HdlSome: Ty42|}(HdlNone) @[reg_alloc.rs 87:9] + connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_0_src_0: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr: Ty1 + connect _bundle_literal_expr.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr @[reg_alloc.rs 111:17] + connect rename_table_normal_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r0.addr, sub(rename_table_normal_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r0.data) @[reg_alloc.rs 117:21] + connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_0_src_1: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_1: Ty1 + connect _bundle_literal_expr_1.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_1 @[reg_alloc.rs 111:17] + connect rename_table_normal_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r1.addr, sub(rename_table_normal_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r1.data) @[reg_alloc.rs 117:21] + connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_0_src_2: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_2: Ty1 + connect _bundle_literal_expr_2.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_0_src_2.addr, _bundle_literal_expr_2 @[reg_alloc.rs 111:17] + connect rename_table_normal_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r2.addr, sub(rename_table_normal_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r2.data) @[reg_alloc.rs 117:21] + connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 103:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<8> + connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_0_src_0: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_3: Ty1 + connect _bundle_literal_expr_3.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_3 @[reg_alloc.rs 111:17] + connect rename_table_special_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r0.addr, sub(rename_table_special_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r0.data) @[reg_alloc.rs 117:21] + connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 103:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<8> + connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_0_src_1: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_4: Ty1 + connect _bundle_literal_expr_4.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_0_src_1.addr, _bundle_literal_expr_4 @[reg_alloc.rs 111:17] + connect rename_table_special_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r1.addr, sub(rename_table_special_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r1.data) @[reg_alloc.rs 117:21] + connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 103:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<8> + connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_0_src_2: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_5: Ty1 + connect _bundle_literal_expr_5.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_0_src_2.addr, _bundle_literal_expr_5 @[reg_alloc.rs 111:17] + connect rename_table_special_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r2.addr, sub(rename_table_special_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r2.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 159:9] HdlNone: skip HdlSome(_match_arm_value): - wire unit_kind: Ty22 @[unit.rs 107:1] - match _match_arm_value.uop: @[unit.rs 107:1] + wire unit_kind: Ty46 @[unit.rs 127:1] + match _match_arm_value.mop: @[unit.rs 127:1] AluBranch(_match_arm_value_1): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1] L2RegisterFile(_match_arm_value_2): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 127:1] LoadStore(_match_arm_value_3): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1] - wire available_units_for_kind: UInt<1>[1] @[unit.rs 107:1] - match unit_kind: @[unit.rs 107:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 127:1] + wire available_units_for_kind: UInt<1>[2] @[unit.rs 127:1] + match unit_kind: @[unit.rs 127:1] AluBranch: - connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 107:1] + connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 127:1] + connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 127:1] L2RegisterFile: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1] + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 127:1] LoadStore: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1] - connect available_units[0], available_units_for_kind @[reg_alloc.rs 71:13] - wire selected_unit_leaf_0_0: Ty21 @[reg_alloc.rs 84:25] - connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21] - wire unit_num_0_0: Ty20 @[reg_alloc.rs 90:25] + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units[0], available_units_for_kind @[reg_alloc.rs 160:13] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 165:13] + HdlNone: + skip + HdlSome(_match_arm_value_4): + wire dest_reg: Ty4 @[unit.rs 127:1] + match _match_arm_value.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_5): + wire dest_reg_1: Ty4 @[instruction.rs 477:1] + match _match_arm_value_5: @[instruction.rs 477:1] + AddSub(_match_arm_value_6): + connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_7): + connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_8): + connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg, dest_reg_1 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_9): + wire dest_reg_2: Ty4 @[instruction.rs 504:1] + match _match_arm_value_9: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_10): + connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_11): + connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 504:1] + connect dest_reg, dest_reg_2 @[unit.rs 127:1] + LoadStore(_match_arm_value_12): + wire dest_reg_3: Ty4 @[instruction.rs 539:1] + match _match_arm_value_12: @[instruction.rs 539:1] + Load(_match_arm_value_13): + connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 539:1] + Store(_match_arm_value_14): + connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 539:1] + connect dest_reg, dest_reg_3 @[unit.rs 127:1] + wire mapped_regs: Ty42 @[unit.rs 127:1] + match _match_arm_value.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_15): + wire mapped_regs_1: Ty37 @[instruction.rs 477:1] + match _match_arm_value_15: @[instruction.rs 477:1] + AddSub(_match_arm_value_16): + wire renamed_src_reg_0_0: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_6: Ty1 + connect _bundle_literal_expr_6.value, _match_arm_value_16.alu_common.common.src[0] + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_6 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_7: Ty1 + connect _bundle_literal_expr_7.value, _match_arm_value_16.alu_common.common.src[0] + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_7 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_8: Ty25 + wire _bundle_literal_expr_9: Ty23 + connect _bundle_literal_expr_9.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_8.unit_num, _bundle_literal_expr_9 + wire _bundle_literal_expr_10: Ty24 + connect _bundle_literal_expr_10.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_8.unit_out_reg, _bundle_literal_expr_10 + connect renamed_src_reg_0_0, _bundle_literal_expr_8 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_17): + connect renamed_src_reg_0_0, _match_arm_value_17 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_18): + connect renamed_src_reg_0_0, _match_arm_value_18 @[reg_alloc.rs 185:33] + wire renamed_src_reg_0_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_11: Ty1 + connect _bundle_literal_expr_11.value, _match_arm_value_16.alu_common.common.src[1] + connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_11 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_12: Ty1 + connect _bundle_literal_expr_12.value, _match_arm_value_16.alu_common.common.src[1] + connect rename_table_special_0_src_1.addr, _bundle_literal_expr_12 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_13: Ty25 + wire _bundle_literal_expr_14: Ty23 + connect _bundle_literal_expr_14.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_13.unit_num, _bundle_literal_expr_14 + wire _bundle_literal_expr_15: Ty24 + connect _bundle_literal_expr_15.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_13.unit_out_reg, _bundle_literal_expr_15 + connect renamed_src_reg_0_1, _bundle_literal_expr_13 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_19): + connect renamed_src_reg_0_1, _match_arm_value_19 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_20): + connect renamed_src_reg_0_1, _match_arm_value_20 @[reg_alloc.rs 185:33] + wire renamed_src_reg_0_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_16: Ty1 + connect _bundle_literal_expr_16.value, _match_arm_value_16.alu_common.common.src[2] + connect rename_table_normal_0_src_2.addr, _bundle_literal_expr_16 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_17: Ty1 + connect _bundle_literal_expr_17.value, _match_arm_value_16.alu_common.common.src[2] + connect rename_table_special_0_src_2.addr, _bundle_literal_expr_17 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_2.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_2.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_18: Ty25 + wire _bundle_literal_expr_19: Ty23 + connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19 + wire _bundle_literal_expr_20: Ty24 + connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20 + connect renamed_src_reg_0_2, _bundle_literal_expr_18 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_21): + connect renamed_src_reg_0_2, _match_arm_value_21 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_22): + connect renamed_src_reg_0_2, _match_arm_value_22 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_21: Ty35 + wire _bundle_literal_expr_22: Ty34 + wire _bundle_literal_expr_23: Ty33 + connect _bundle_literal_expr_23.prefix_pad, _match_arm_value_16.alu_common.common.prefix_pad + connect _bundle_literal_expr_23.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_1: UInt<6>[3] + wire _array_literal_expr_2: UInt<6>[3] + wire _cast_bundle_to_bits_expr: Ty47 + connect _cast_bundle_to_bits_expr.unit_num, renamed_src_reg_0_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value + wire _cast_to_bits_expr: UInt<6> + connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) + connect _array_literal_expr_2[0], _cast_to_bits_expr + wire _cast_bundle_to_bits_expr_1: Ty47 + connect _cast_bundle_to_bits_expr_1.unit_num, renamed_src_reg_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_1.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value + wire _cast_to_bits_expr_1: UInt<6> + connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) + connect _array_literal_expr_2[1], _cast_to_bits_expr_1 + wire _cast_bundle_to_bits_expr_2: Ty47 + connect _cast_bundle_to_bits_expr_2.unit_num, renamed_src_reg_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_2.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value + wire _cast_to_bits_expr_2: UInt<6> + connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) + connect _array_literal_expr_2[2], _cast_to_bits_expr_2 + connect _array_literal_expr_1[0], _array_literal_expr_2[0] + wire _array_literal_expr_3: UInt<6>[3] + wire _cast_bundle_to_bits_expr_3: Ty47 + connect _cast_bundle_to_bits_expr_3.unit_num, renamed_src_reg_0_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr_3.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value + wire _cast_to_bits_expr_3: UInt<6> + connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) + connect _array_literal_expr_3[0], _cast_to_bits_expr_3 + wire _cast_bundle_to_bits_expr_4: Ty47 + connect _cast_bundle_to_bits_expr_4.unit_num, renamed_src_reg_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_4.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value + wire _cast_to_bits_expr_4: UInt<6> + connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) + connect _array_literal_expr_3[1], _cast_to_bits_expr_4 + wire _cast_bundle_to_bits_expr_5: Ty47 + connect _cast_bundle_to_bits_expr_5.unit_num, renamed_src_reg_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_5.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value + wire _cast_to_bits_expr_5: UInt<6> + connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) + connect _array_literal_expr_3[2], _cast_to_bits_expr_5 + connect _array_literal_expr_1[1], _array_literal_expr_3[1] + wire _array_literal_expr_4: UInt<6>[3] + wire _cast_bundle_to_bits_expr_6: Ty47 + connect _cast_bundle_to_bits_expr_6.unit_num, renamed_src_reg_0_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr_6.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value + wire _cast_to_bits_expr_6: UInt<6> + connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) + connect _array_literal_expr_4[0], _cast_to_bits_expr_6 + wire _cast_bundle_to_bits_expr_7: Ty47 + connect _cast_bundle_to_bits_expr_7.unit_num, renamed_src_reg_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_7.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value + wire _cast_to_bits_expr_7: UInt<6> + connect _cast_to_bits_expr_7, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num) + connect _array_literal_expr_4[1], _cast_to_bits_expr_7 + wire _cast_bundle_to_bits_expr_8: Ty47 + connect _cast_bundle_to_bits_expr_8.unit_num, renamed_src_reg_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_8.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value + wire _cast_to_bits_expr_8: UInt<6> + connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num) + connect _array_literal_expr_4[2], _cast_to_bits_expr_8 + connect _array_literal_expr_1[2], _array_literal_expr_4[2] + connect _bundle_literal_expr_23.src, _array_literal_expr_1 + wire _bundle_literal_expr_24: Ty48 + connect _bundle_literal_expr_24.imm_low, _match_arm_value_16.alu_common.common.imm_low + wire _array_literal_expr_5: UInt<8>[0] + invalidate _array_literal_expr_5 + connect _bundle_literal_expr_24.reversed_src, _array_literal_expr_5 + connect _bundle_literal_expr_24.imm_sign, _match_arm_value_16.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_9: Ty49 + connect _cast_bundle_to_bits_expr_9.imm_low, _bundle_literal_expr_24.imm_low + connect _cast_bundle_to_bits_expr_9.reversed_src, UInt<0>(0) + connect _cast_bundle_to_bits_expr_9.imm_sign, asUInt(_bundle_literal_expr_24.imm_sign) + wire _cast_to_bits_expr_9: UInt<26> + connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_9.imm_sign, cat(_cast_bundle_to_bits_expr_9.reversed_src, _cast_bundle_to_bits_expr_9.imm_low)) + connect _bundle_literal_expr_23.imm_low, bits(asSInt(_cast_to_bits_expr_9), 24, 0) + wire _bundle_literal_expr_25: Ty48 + connect _bundle_literal_expr_25.imm_low, _match_arm_value_16.alu_common.common.imm_low + wire _array_literal_expr_6: UInt<8>[0] + invalidate _array_literal_expr_6 + connect _bundle_literal_expr_25.reversed_src, _array_literal_expr_6 + connect _bundle_literal_expr_25.imm_sign, _match_arm_value_16.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_10: Ty49 + connect _cast_bundle_to_bits_expr_10.imm_low, _bundle_literal_expr_25.imm_low + connect _cast_bundle_to_bits_expr_10.reversed_src, UInt<0>(0) + connect _cast_bundle_to_bits_expr_10.imm_sign, asUInt(_bundle_literal_expr_25.imm_sign) + wire _cast_to_bits_expr_10: UInt<26> + connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_10.imm_sign, cat(_cast_bundle_to_bits_expr_10.reversed_src, _cast_bundle_to_bits_expr_10.imm_low)) + connect _bundle_literal_expr_23.imm_sign, shr(asSInt(_cast_to_bits_expr_10), 25) + wire _bundle_literal_expr_26: Ty2 + invalidate _bundle_literal_expr_26 + connect _bundle_literal_expr_23._phantom, _bundle_literal_expr_26 + connect _bundle_literal_expr_22.common, _bundle_literal_expr_23 + connect _bundle_literal_expr_22.output_integer_mode, _match_arm_value_16.alu_common.output_integer_mode + connect _bundle_literal_expr_21.alu_common, _bundle_literal_expr_22 + connect _bundle_literal_expr_21.invert_src0, _match_arm_value_16.invert_src0 + connect _bundle_literal_expr_21.invert_carry_in, _match_arm_value_16.invert_carry_in + connect _bundle_literal_expr_21.invert_carry_out, _match_arm_value_16.invert_carry_out + connect _bundle_literal_expr_21.add_pc, _match_arm_value_16.add_pc + connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSub, _bundle_literal_expr_21) @[instruction.rs 477:1] + AddSubI(_match_arm_value_23): + wire renamed_src_reg_0_0_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_27: Ty1 + connect _bundle_literal_expr_27.value, _match_arm_value_23.alu_common.common.src[0] + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_27 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_28: Ty1 + connect _bundle_literal_expr_28.value, _match_arm_value_23.alu_common.common.src[0] + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_28 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_29: Ty25 + wire _bundle_literal_expr_30: Ty23 + connect _bundle_literal_expr_30.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_29.unit_num, _bundle_literal_expr_30 + wire _bundle_literal_expr_31: Ty24 + connect _bundle_literal_expr_31.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_29.unit_out_reg, _bundle_literal_expr_31 + connect renamed_src_reg_0_0_1, _bundle_literal_expr_29 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_24): + connect renamed_src_reg_0_0_1, _match_arm_value_24 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_25): + connect renamed_src_reg_0_0_1, _match_arm_value_25 @[reg_alloc.rs 185:33] + wire renamed_src_reg_0_1_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_32: Ty1 + connect _bundle_literal_expr_32.value, _match_arm_value_23.alu_common.common.src[1] + connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_32 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_33: Ty1 + connect _bundle_literal_expr_33.value, _match_arm_value_23.alu_common.common.src[1] + connect rename_table_special_0_src_1.addr, _bundle_literal_expr_33 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_34: Ty25 + wire _bundle_literal_expr_35: Ty23 + connect _bundle_literal_expr_35.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_34.unit_num, _bundle_literal_expr_35 + wire _bundle_literal_expr_36: Ty24 + connect _bundle_literal_expr_36.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_34.unit_out_reg, _bundle_literal_expr_36 + connect renamed_src_reg_0_1_1, _bundle_literal_expr_34 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_26): + connect renamed_src_reg_0_1_1, _match_arm_value_26 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_27): + connect renamed_src_reg_0_1_1, _match_arm_value_27 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_37: Ty35 + wire _bundle_literal_expr_38: Ty34 + wire _bundle_literal_expr_39: Ty33 + connect _bundle_literal_expr_39.prefix_pad, _match_arm_value_23.alu_common.common.prefix_pad + connect _bundle_literal_expr_39.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_7: UInt<6>[3] + wire _array_literal_expr_8: UInt<6>[2] + wire _cast_bundle_to_bits_expr_11: Ty47 + connect _cast_bundle_to_bits_expr_11.unit_num, renamed_src_reg_0_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_11.unit_out_reg, renamed_src_reg_0_0_1.unit_out_reg.value + wire _cast_to_bits_expr_11: UInt<6> + connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num) + connect _array_literal_expr_8[0], _cast_to_bits_expr_11 + wire _cast_bundle_to_bits_expr_12: Ty47 + connect _cast_bundle_to_bits_expr_12.unit_num, renamed_src_reg_0_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_12.unit_out_reg, renamed_src_reg_0_1_1.unit_out_reg.value + wire _cast_to_bits_expr_12: UInt<6> + connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num) + connect _array_literal_expr_8[1], _cast_to_bits_expr_12 + connect _array_literal_expr_7[0], _array_literal_expr_8[0] + wire _array_literal_expr_9: UInt<6>[2] + wire _cast_bundle_to_bits_expr_13: Ty47 + connect _cast_bundle_to_bits_expr_13.unit_num, renamed_src_reg_0_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_13.unit_out_reg, renamed_src_reg_0_0_1.unit_out_reg.value + wire _cast_to_bits_expr_13: UInt<6> + connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num) + connect _array_literal_expr_9[0], _cast_to_bits_expr_13 + wire _cast_bundle_to_bits_expr_14: Ty47 + connect _cast_bundle_to_bits_expr_14.unit_num, renamed_src_reg_0_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_14.unit_out_reg, renamed_src_reg_0_1_1.unit_out_reg.value + wire _cast_to_bits_expr_14: UInt<6> + connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num) + connect _array_literal_expr_9[1], _cast_to_bits_expr_14 + connect _array_literal_expr_7[1], _array_literal_expr_9[1] + wire _bundle_literal_expr_40: Ty50 + connect _bundle_literal_expr_40.imm_low, _match_arm_value_23.alu_common.common.imm_low + wire _array_literal_expr_10: UInt<8>[1] + connect _array_literal_expr_10[0], _match_arm_value_23.alu_common.common.src[2] + connect _bundle_literal_expr_40.reversed_src, _array_literal_expr_10 + connect _bundle_literal_expr_40.imm_sign, _match_arm_value_23.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_15: Ty51 + connect _cast_bundle_to_bits_expr_15.imm_low, _bundle_literal_expr_40.imm_low + connect _cast_bundle_to_bits_expr_15.reversed_src, _bundle_literal_expr_40.reversed_src[0] + connect _cast_bundle_to_bits_expr_15.imm_sign, asUInt(_bundle_literal_expr_40.imm_sign) + wire _cast_to_bits_expr_15: UInt<34> + connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_15.imm_sign, cat(_cast_bundle_to_bits_expr_15.reversed_src, _cast_bundle_to_bits_expr_15.imm_low)) + wire _cast_bits_to_bundle_expr: Ty50 + wire _cast_bits_to_bundle_expr_flattened: Ty51 + connect _cast_bits_to_bundle_expr_flattened.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 24, 0) + connect _cast_bits_to_bundle_expr.imm_low, _cast_bits_to_bundle_expr_flattened.imm_low + connect _cast_bits_to_bundle_expr_flattened.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 32, 25) + wire _cast_bits_to_array_expr: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened[0], bits(_cast_bits_to_bundle_expr_flattened.reversed_src, 7, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_bundle_expr.reversed_src, _cast_bits_to_array_expr + connect _cast_bits_to_bundle_expr_flattened.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 33, 33) + connect _cast_bits_to_bundle_expr.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened.imm_sign) + connect _array_literal_expr_7[2], tail(_cast_bits_to_bundle_expr.reversed_src[0], 2) + connect _bundle_literal_expr_39.src, _array_literal_expr_7 + wire _bundle_literal_expr_41: Ty50 + connect _bundle_literal_expr_41.imm_low, _match_arm_value_23.alu_common.common.imm_low + wire _array_literal_expr_11: UInt<8>[1] + connect _array_literal_expr_11[0], _match_arm_value_23.alu_common.common.src[2] + connect _bundle_literal_expr_41.reversed_src, _array_literal_expr_11 + connect _bundle_literal_expr_41.imm_sign, _match_arm_value_23.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_16: Ty51 + connect _cast_bundle_to_bits_expr_16.imm_low, _bundle_literal_expr_41.imm_low + connect _cast_bundle_to_bits_expr_16.reversed_src, _bundle_literal_expr_41.reversed_src[0] + connect _cast_bundle_to_bits_expr_16.imm_sign, asUInt(_bundle_literal_expr_41.imm_sign) + wire _cast_to_bits_expr_16: UInt<34> + connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_16.imm_sign, cat(_cast_bundle_to_bits_expr_16.reversed_src, _cast_bundle_to_bits_expr_16.imm_low)) + connect _bundle_literal_expr_39.imm_low, bits(asSInt(_cast_to_bits_expr_16), 24, 0) + wire _bundle_literal_expr_42: Ty50 + connect _bundle_literal_expr_42.imm_low, _match_arm_value_23.alu_common.common.imm_low + wire _array_literal_expr_12: UInt<8>[1] + connect _array_literal_expr_12[0], _match_arm_value_23.alu_common.common.src[2] + connect _bundle_literal_expr_42.reversed_src, _array_literal_expr_12 + connect _bundle_literal_expr_42.imm_sign, _match_arm_value_23.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_17: Ty51 + connect _cast_bundle_to_bits_expr_17.imm_low, _bundle_literal_expr_42.imm_low + connect _cast_bundle_to_bits_expr_17.reversed_src, _bundle_literal_expr_42.reversed_src[0] + connect _cast_bundle_to_bits_expr_17.imm_sign, asUInt(_bundle_literal_expr_42.imm_sign) + wire _cast_to_bits_expr_17: UInt<34> + connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_17.imm_sign, cat(_cast_bundle_to_bits_expr_17.reversed_src, _cast_bundle_to_bits_expr_17.imm_low)) + connect _bundle_literal_expr_39.imm_sign, shr(asSInt(_cast_to_bits_expr_17), 33) + wire _bundle_literal_expr_43: Ty2 + invalidate _bundle_literal_expr_43 + connect _bundle_literal_expr_39._phantom, _bundle_literal_expr_43 + connect _bundle_literal_expr_38.common, _bundle_literal_expr_39 + connect _bundle_literal_expr_38.output_integer_mode, _match_arm_value_23.alu_common.output_integer_mode + connect _bundle_literal_expr_37.alu_common, _bundle_literal_expr_38 + connect _bundle_literal_expr_37.invert_src0, _match_arm_value_23.invert_src0 + connect _bundle_literal_expr_37.invert_carry_in, _match_arm_value_23.invert_carry_in + connect _bundle_literal_expr_37.invert_carry_out, _match_arm_value_23.invert_carry_out + connect _bundle_literal_expr_37.add_pc, _match_arm_value_23.add_pc + connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSubI, _bundle_literal_expr_37) @[instruction.rs 477:1] + Logical(_match_arm_value_28): + wire renamed_src_reg_0_0_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_44: Ty1 + connect _bundle_literal_expr_44.value, _match_arm_value_28.alu_common.common.src[0] + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_44 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_45: Ty1 + connect _bundle_literal_expr_45.value, _match_arm_value_28.alu_common.common.src[0] + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_46: Ty25 + wire _bundle_literal_expr_47: Ty23 + connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47 + wire _bundle_literal_expr_48: Ty24 + connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48 + connect renamed_src_reg_0_0_2, _bundle_literal_expr_46 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_29): + connect renamed_src_reg_0_0_2, _match_arm_value_29 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_30): + connect renamed_src_reg_0_0_2, _match_arm_value_30 @[reg_alloc.rs 185:33] + wire renamed_src_reg_0_1_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_49: Ty1 + connect _bundle_literal_expr_49.value, _match_arm_value_28.alu_common.common.src[1] + connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_49 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_50: Ty1 + connect _bundle_literal_expr_50.value, _match_arm_value_28.alu_common.common.src[1] + connect rename_table_special_0_src_1.addr, _bundle_literal_expr_50 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_51: Ty25 + wire _bundle_literal_expr_52: Ty23 + connect _bundle_literal_expr_52.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_51.unit_num, _bundle_literal_expr_52 + wire _bundle_literal_expr_53: Ty24 + connect _bundle_literal_expr_53.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_51.unit_out_reg, _bundle_literal_expr_53 + connect renamed_src_reg_0_1_2, _bundle_literal_expr_51 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_31): + connect renamed_src_reg_0_1_2, _match_arm_value_31 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_32): + connect renamed_src_reg_0_1_2, _match_arm_value_32 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_54: Ty36 + wire _bundle_literal_expr_55: Ty34 + wire _bundle_literal_expr_56: Ty33 + connect _bundle_literal_expr_56.prefix_pad, _match_arm_value_28.alu_common.common.prefix_pad + connect _bundle_literal_expr_56.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_13: UInt<6>[3] + wire _array_literal_expr_14: UInt<6>[2] + wire _cast_bundle_to_bits_expr_18: Ty47 + connect _cast_bundle_to_bits_expr_18.unit_num, renamed_src_reg_0_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_18.unit_out_reg, renamed_src_reg_0_0_2.unit_out_reg.value + wire _cast_to_bits_expr_18: UInt<6> + connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num) + connect _array_literal_expr_14[0], _cast_to_bits_expr_18 + wire _cast_bundle_to_bits_expr_19: Ty47 + connect _cast_bundle_to_bits_expr_19.unit_num, renamed_src_reg_0_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_19.unit_out_reg, renamed_src_reg_0_1_2.unit_out_reg.value + wire _cast_to_bits_expr_19: UInt<6> + connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num) + connect _array_literal_expr_14[1], _cast_to_bits_expr_19 + connect _array_literal_expr_13[0], _array_literal_expr_14[0] + wire _array_literal_expr_15: UInt<6>[2] + wire _cast_bundle_to_bits_expr_20: Ty47 + connect _cast_bundle_to_bits_expr_20.unit_num, renamed_src_reg_0_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_20.unit_out_reg, renamed_src_reg_0_0_2.unit_out_reg.value + wire _cast_to_bits_expr_20: UInt<6> + connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num) + connect _array_literal_expr_15[0], _cast_to_bits_expr_20 + wire _cast_bundle_to_bits_expr_21: Ty47 + connect _cast_bundle_to_bits_expr_21.unit_num, renamed_src_reg_0_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_21.unit_out_reg, renamed_src_reg_0_1_2.unit_out_reg.value + wire _cast_to_bits_expr_21: UInt<6> + connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num) + connect _array_literal_expr_15[1], _cast_to_bits_expr_21 + connect _array_literal_expr_13[1], _array_literal_expr_15[1] + wire _bundle_literal_expr_57: Ty50 + connect _bundle_literal_expr_57.imm_low, _match_arm_value_28.alu_common.common.imm_low + wire _array_literal_expr_16: UInt<8>[1] + connect _array_literal_expr_16[0], _match_arm_value_28.alu_common.common.src[2] + connect _bundle_literal_expr_57.reversed_src, _array_literal_expr_16 + connect _bundle_literal_expr_57.imm_sign, _match_arm_value_28.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_22: Ty51 + connect _cast_bundle_to_bits_expr_22.imm_low, _bundle_literal_expr_57.imm_low + connect _cast_bundle_to_bits_expr_22.reversed_src, _bundle_literal_expr_57.reversed_src[0] + connect _cast_bundle_to_bits_expr_22.imm_sign, asUInt(_bundle_literal_expr_57.imm_sign) + wire _cast_to_bits_expr_22: UInt<34> + connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_22.imm_sign, cat(_cast_bundle_to_bits_expr_22.reversed_src, _cast_bundle_to_bits_expr_22.imm_low)) + wire _cast_bits_to_bundle_expr_1: Ty50 + wire _cast_bits_to_bundle_expr_flattened_1: Ty51 + connect _cast_bits_to_bundle_expr_flattened_1.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 24, 0) + connect _cast_bits_to_bundle_expr_1.imm_low, _cast_bits_to_bundle_expr_flattened_1.imm_low + connect _cast_bits_to_bundle_expr_flattened_1.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 32, 25) + wire _cast_bits_to_array_expr_1: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_1: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_1[0], bits(_cast_bits_to_bundle_expr_flattened_1.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_bundle_expr_1.reversed_src, _cast_bits_to_array_expr_1 + connect _cast_bits_to_bundle_expr_flattened_1.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 33, 33) + connect _cast_bits_to_bundle_expr_1.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_1.imm_sign) + connect _array_literal_expr_13[2], tail(_cast_bits_to_bundle_expr_1.reversed_src[0], 2) + connect _bundle_literal_expr_56.src, _array_literal_expr_13 + wire _bundle_literal_expr_58: Ty50 + connect _bundle_literal_expr_58.imm_low, _match_arm_value_28.alu_common.common.imm_low + wire _array_literal_expr_17: UInt<8>[1] + connect _array_literal_expr_17[0], _match_arm_value_28.alu_common.common.src[2] + connect _bundle_literal_expr_58.reversed_src, _array_literal_expr_17 + connect _bundle_literal_expr_58.imm_sign, _match_arm_value_28.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_23: Ty51 + connect _cast_bundle_to_bits_expr_23.imm_low, _bundle_literal_expr_58.imm_low + connect _cast_bundle_to_bits_expr_23.reversed_src, _bundle_literal_expr_58.reversed_src[0] + connect _cast_bundle_to_bits_expr_23.imm_sign, asUInt(_bundle_literal_expr_58.imm_sign) + wire _cast_to_bits_expr_23: UInt<34> + connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_23.imm_sign, cat(_cast_bundle_to_bits_expr_23.reversed_src, _cast_bundle_to_bits_expr_23.imm_low)) + connect _bundle_literal_expr_56.imm_low, bits(asSInt(_cast_to_bits_expr_23), 24, 0) + wire _bundle_literal_expr_59: Ty50 + connect _bundle_literal_expr_59.imm_low, _match_arm_value_28.alu_common.common.imm_low + wire _array_literal_expr_18: UInt<8>[1] + connect _array_literal_expr_18[0], _match_arm_value_28.alu_common.common.src[2] + connect _bundle_literal_expr_59.reversed_src, _array_literal_expr_18 + connect _bundle_literal_expr_59.imm_sign, _match_arm_value_28.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_24: Ty51 + connect _cast_bundle_to_bits_expr_24.imm_low, _bundle_literal_expr_59.imm_low + connect _cast_bundle_to_bits_expr_24.reversed_src, _bundle_literal_expr_59.reversed_src[0] + connect _cast_bundle_to_bits_expr_24.imm_sign, asUInt(_bundle_literal_expr_59.imm_sign) + wire _cast_to_bits_expr_24: UInt<34> + connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_24.imm_sign, cat(_cast_bundle_to_bits_expr_24.reversed_src, _cast_bundle_to_bits_expr_24.imm_low)) + connect _bundle_literal_expr_56.imm_sign, shr(asSInt(_cast_to_bits_expr_24), 33) + wire _bundle_literal_expr_60: Ty2 + invalidate _bundle_literal_expr_60 + connect _bundle_literal_expr_56._phantom, _bundle_literal_expr_60 + connect _bundle_literal_expr_55.common, _bundle_literal_expr_56 + connect _bundle_literal_expr_55.output_integer_mode, _match_arm_value_28.alu_common.output_integer_mode + connect _bundle_literal_expr_54.alu_common, _bundle_literal_expr_55 + connect _bundle_literal_expr_54.lut, _match_arm_value_28.lut + connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(Logical, _bundle_literal_expr_54) @[instruction.rs 477:1] + connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(AluBranch, mapped_regs_1) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_33): + wire mapped_regs_2: Ty40 @[instruction.rs 504:1] + match _match_arm_value_33: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_34): + wire _bundle_literal_expr_61: Ty39 + wire _bundle_literal_expr_62: Ty38 + connect _bundle_literal_expr_62.prefix_pad, _match_arm_value_34.common.prefix_pad + connect _bundle_literal_expr_62.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_19: UInt<6>[3] + connect _array_literal_expr_19[0], pad(UInt<0>(0h0), 6) + connect _array_literal_expr_19[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_63: Ty50 + connect _bundle_literal_expr_63.imm_low, _match_arm_value_34.common.imm_low + wire _array_literal_expr_20: UInt<8>[1] + connect _array_literal_expr_20[0], _match_arm_value_34.common.src[2] + connect _bundle_literal_expr_63.reversed_src, _array_literal_expr_20 + connect _bundle_literal_expr_63.imm_sign, _match_arm_value_34.common.imm_sign + wire _cast_bundle_to_bits_expr_25: Ty51 + connect _cast_bundle_to_bits_expr_25.imm_low, _bundle_literal_expr_63.imm_low + connect _cast_bundle_to_bits_expr_25.reversed_src, _bundle_literal_expr_63.reversed_src[0] + connect _cast_bundle_to_bits_expr_25.imm_sign, asUInt(_bundle_literal_expr_63.imm_sign) + wire _cast_to_bits_expr_25: UInt<34> + connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_25.imm_sign, cat(_cast_bundle_to_bits_expr_25.reversed_src, _cast_bundle_to_bits_expr_25.imm_low)) + wire _cast_bits_to_bundle_expr_2: Ty50 + wire _cast_bits_to_bundle_expr_flattened_2: Ty51 + connect _cast_bits_to_bundle_expr_flattened_2.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 24, 0) + connect _cast_bits_to_bundle_expr_2.imm_low, _cast_bits_to_bundle_expr_flattened_2.imm_low + connect _cast_bits_to_bundle_expr_flattened_2.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 32, 25) + wire _cast_bits_to_array_expr_2: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_2: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_2[0], bits(_cast_bits_to_bundle_expr_flattened_2.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_bundle_expr_2.reversed_src, _cast_bits_to_array_expr_2 + connect _cast_bits_to_bundle_expr_flattened_2.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 33, 33) + connect _cast_bits_to_bundle_expr_2.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_2.imm_sign) + connect _array_literal_expr_19[2], tail(_cast_bits_to_bundle_expr_2.reversed_src[0], 2) + connect _bundle_literal_expr_62.src, _array_literal_expr_19 + wire _bundle_literal_expr_64: Ty50 + connect _bundle_literal_expr_64.imm_low, _match_arm_value_34.common.imm_low + wire _array_literal_expr_21: UInt<8>[1] + connect _array_literal_expr_21[0], _match_arm_value_34.common.src[2] + connect _bundle_literal_expr_64.reversed_src, _array_literal_expr_21 + connect _bundle_literal_expr_64.imm_sign, _match_arm_value_34.common.imm_sign + wire _cast_bundle_to_bits_expr_26: Ty51 + connect _cast_bundle_to_bits_expr_26.imm_low, _bundle_literal_expr_64.imm_low + connect _cast_bundle_to_bits_expr_26.reversed_src, _bundle_literal_expr_64.reversed_src[0] + connect _cast_bundle_to_bits_expr_26.imm_sign, asUInt(_bundle_literal_expr_64.imm_sign) + wire _cast_to_bits_expr_26: UInt<34> + connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_26.imm_sign, cat(_cast_bundle_to_bits_expr_26.reversed_src, _cast_bundle_to_bits_expr_26.imm_low)) + connect _bundle_literal_expr_62.imm_low, bits(asSInt(_cast_to_bits_expr_26), 24, 0) + wire _bundle_literal_expr_65: Ty50 + connect _bundle_literal_expr_65.imm_low, _match_arm_value_34.common.imm_low + wire _array_literal_expr_22: UInt<8>[1] + connect _array_literal_expr_22[0], _match_arm_value_34.common.src[2] + connect _bundle_literal_expr_65.reversed_src, _array_literal_expr_22 + connect _bundle_literal_expr_65.imm_sign, _match_arm_value_34.common.imm_sign + wire _cast_bundle_to_bits_expr_27: Ty51 + connect _cast_bundle_to_bits_expr_27.imm_low, _bundle_literal_expr_65.imm_low + connect _cast_bundle_to_bits_expr_27.reversed_src, _bundle_literal_expr_65.reversed_src[0] + connect _cast_bundle_to_bits_expr_27.imm_sign, asUInt(_bundle_literal_expr_65.imm_sign) + wire _cast_to_bits_expr_27: UInt<34> + connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_27.imm_sign, cat(_cast_bundle_to_bits_expr_27.reversed_src, _cast_bundle_to_bits_expr_27.imm_low)) + connect _bundle_literal_expr_62.imm_sign, shr(asSInt(_cast_to_bits_expr_27), 33) + wire _bundle_literal_expr_66: Ty2 + invalidate _bundle_literal_expr_66 + connect _bundle_literal_expr_62._phantom, _bundle_literal_expr_66 + connect _bundle_literal_expr_61.common, _bundle_literal_expr_62 + connect mapped_regs_2, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(ReadL2Reg, _bundle_literal_expr_61) @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_35): + wire renamed_src_reg_0_0_3: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_67: Ty1 + connect _bundle_literal_expr_67.value, _match_arm_value_35.common.src[0] + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_67 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_68: Ty1 + connect _bundle_literal_expr_68.value, _match_arm_value_35.common.src[0] + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_68 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_69: Ty25 + wire _bundle_literal_expr_70: Ty23 + connect _bundle_literal_expr_70.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_69.unit_num, _bundle_literal_expr_70 + wire _bundle_literal_expr_71: Ty24 + connect _bundle_literal_expr_71.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_69.unit_out_reg, _bundle_literal_expr_71 + connect renamed_src_reg_0_0_3, _bundle_literal_expr_69 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_36): + connect renamed_src_reg_0_0_3, _match_arm_value_36 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_37): + connect renamed_src_reg_0_0_3, _match_arm_value_37 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_72: Ty39 + wire _bundle_literal_expr_73: Ty38 + connect _bundle_literal_expr_73.prefix_pad, _match_arm_value_35.common.prefix_pad + connect _bundle_literal_expr_73.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_23: UInt<6>[3] + wire _array_literal_expr_24: UInt<6>[1] + wire _cast_bundle_to_bits_expr_28: Ty47 + connect _cast_bundle_to_bits_expr_28.unit_num, renamed_src_reg_0_0_3.unit_num.adj_value + connect _cast_bundle_to_bits_expr_28.unit_out_reg, renamed_src_reg_0_0_3.unit_out_reg.value + wire _cast_to_bits_expr_28: UInt<6> + connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num) + connect _array_literal_expr_24[0], _cast_to_bits_expr_28 + connect _array_literal_expr_23[0], _array_literal_expr_24[0] + connect _array_literal_expr_23[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_74: Ty50 + connect _bundle_literal_expr_74.imm_low, _match_arm_value_35.common.imm_low + wire _array_literal_expr_25: UInt<8>[1] + connect _array_literal_expr_25[0], _match_arm_value_35.common.src[2] + connect _bundle_literal_expr_74.reversed_src, _array_literal_expr_25 + connect _bundle_literal_expr_74.imm_sign, _match_arm_value_35.common.imm_sign + wire _cast_bundle_to_bits_expr_29: Ty51 + connect _cast_bundle_to_bits_expr_29.imm_low, _bundle_literal_expr_74.imm_low + connect _cast_bundle_to_bits_expr_29.reversed_src, _bundle_literal_expr_74.reversed_src[0] + connect _cast_bundle_to_bits_expr_29.imm_sign, asUInt(_bundle_literal_expr_74.imm_sign) + wire _cast_to_bits_expr_29: UInt<34> + connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_29.imm_sign, cat(_cast_bundle_to_bits_expr_29.reversed_src, _cast_bundle_to_bits_expr_29.imm_low)) + wire _cast_bits_to_bundle_expr_3: Ty50 + wire _cast_bits_to_bundle_expr_flattened_3: Ty51 + connect _cast_bits_to_bundle_expr_flattened_3.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 24, 0) + connect _cast_bits_to_bundle_expr_3.imm_low, _cast_bits_to_bundle_expr_flattened_3.imm_low + connect _cast_bits_to_bundle_expr_flattened_3.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 32, 25) + wire _cast_bits_to_array_expr_3: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_3: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_3[0], bits(_cast_bits_to_bundle_expr_flattened_3.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_bundle_expr_3.reversed_src, _cast_bits_to_array_expr_3 + connect _cast_bits_to_bundle_expr_flattened_3.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 33, 33) + connect _cast_bits_to_bundle_expr_3.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_3.imm_sign) + connect _array_literal_expr_23[2], tail(_cast_bits_to_bundle_expr_3.reversed_src[0], 2) + connect _bundle_literal_expr_73.src, _array_literal_expr_23 + wire _bundle_literal_expr_75: Ty50 + connect _bundle_literal_expr_75.imm_low, _match_arm_value_35.common.imm_low + wire _array_literal_expr_26: UInt<8>[1] + connect _array_literal_expr_26[0], _match_arm_value_35.common.src[2] + connect _bundle_literal_expr_75.reversed_src, _array_literal_expr_26 + connect _bundle_literal_expr_75.imm_sign, _match_arm_value_35.common.imm_sign + wire _cast_bundle_to_bits_expr_30: Ty51 + connect _cast_bundle_to_bits_expr_30.imm_low, _bundle_literal_expr_75.imm_low + connect _cast_bundle_to_bits_expr_30.reversed_src, _bundle_literal_expr_75.reversed_src[0] + connect _cast_bundle_to_bits_expr_30.imm_sign, asUInt(_bundle_literal_expr_75.imm_sign) + wire _cast_to_bits_expr_30: UInt<34> + connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_30.imm_sign, cat(_cast_bundle_to_bits_expr_30.reversed_src, _cast_bundle_to_bits_expr_30.imm_low)) + connect _bundle_literal_expr_73.imm_low, bits(asSInt(_cast_to_bits_expr_30), 24, 0) + wire _bundle_literal_expr_76: Ty50 + connect _bundle_literal_expr_76.imm_low, _match_arm_value_35.common.imm_low + wire _array_literal_expr_27: UInt<8>[1] + connect _array_literal_expr_27[0], _match_arm_value_35.common.src[2] + connect _bundle_literal_expr_76.reversed_src, _array_literal_expr_27 + connect _bundle_literal_expr_76.imm_sign, _match_arm_value_35.common.imm_sign + wire _cast_bundle_to_bits_expr_31: Ty51 + connect _cast_bundle_to_bits_expr_31.imm_low, _bundle_literal_expr_76.imm_low + connect _cast_bundle_to_bits_expr_31.reversed_src, _bundle_literal_expr_76.reversed_src[0] + connect _cast_bundle_to_bits_expr_31.imm_sign, asUInt(_bundle_literal_expr_76.imm_sign) + wire _cast_to_bits_expr_31: UInt<34> + connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_31.imm_sign, cat(_cast_bundle_to_bits_expr_31.reversed_src, _cast_bundle_to_bits_expr_31.imm_low)) + connect _bundle_literal_expr_73.imm_sign, shr(asSInt(_cast_to_bits_expr_31), 33) + wire _bundle_literal_expr_77: Ty2 + invalidate _bundle_literal_expr_77 + connect _bundle_literal_expr_73._phantom, _bundle_literal_expr_77 + connect _bundle_literal_expr_72.common, _bundle_literal_expr_73 + connect mapped_regs_2, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(WriteL2Reg, _bundle_literal_expr_72) @[instruction.rs 504:1] + connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(L2RegisterFile, mapped_regs_2) @[unit.rs 127:1] + LoadStore(_match_arm_value_38): + wire mapped_regs_3: Ty41 @[instruction.rs 539:1] + match _match_arm_value_38: @[instruction.rs 539:1] + Load(_match_arm_value_39): + wire _bundle_literal_expr_78: Ty38 + connect _bundle_literal_expr_78.prefix_pad, _match_arm_value_39.prefix_pad + connect _bundle_literal_expr_78.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_28: UInt<6>[3] + connect _array_literal_expr_28[0], pad(UInt<0>(0h0), 6) + connect _array_literal_expr_28[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_79: Ty50 + connect _bundle_literal_expr_79.imm_low, _match_arm_value_39.imm_low + wire _array_literal_expr_29: UInt<8>[1] + connect _array_literal_expr_29[0], _match_arm_value_39.src[2] + connect _bundle_literal_expr_79.reversed_src, _array_literal_expr_29 + connect _bundle_literal_expr_79.imm_sign, _match_arm_value_39.imm_sign + wire _cast_bundle_to_bits_expr_32: Ty51 + connect _cast_bundle_to_bits_expr_32.imm_low, _bundle_literal_expr_79.imm_low + connect _cast_bundle_to_bits_expr_32.reversed_src, _bundle_literal_expr_79.reversed_src[0] + connect _cast_bundle_to_bits_expr_32.imm_sign, asUInt(_bundle_literal_expr_79.imm_sign) + wire _cast_to_bits_expr_32: UInt<34> + connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_32.imm_sign, cat(_cast_bundle_to_bits_expr_32.reversed_src, _cast_bundle_to_bits_expr_32.imm_low)) + wire _cast_bits_to_bundle_expr_4: Ty50 + wire _cast_bits_to_bundle_expr_flattened_4: Ty51 + connect _cast_bits_to_bundle_expr_flattened_4.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 24, 0) + connect _cast_bits_to_bundle_expr_4.imm_low, _cast_bits_to_bundle_expr_flattened_4.imm_low + connect _cast_bits_to_bundle_expr_flattened_4.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 32, 25) + wire _cast_bits_to_array_expr_4: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_4: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_4[0], bits(_cast_bits_to_bundle_expr_flattened_4.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_bundle_expr_4.reversed_src, _cast_bits_to_array_expr_4 + connect _cast_bits_to_bundle_expr_flattened_4.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 33, 33) + connect _cast_bits_to_bundle_expr_4.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_4.imm_sign) + connect _array_literal_expr_28[2], tail(_cast_bits_to_bundle_expr_4.reversed_src[0], 2) + connect _bundle_literal_expr_78.src, _array_literal_expr_28 + wire _bundle_literal_expr_80: Ty50 + connect _bundle_literal_expr_80.imm_low, _match_arm_value_39.imm_low + wire _array_literal_expr_30: UInt<8>[1] + connect _array_literal_expr_30[0], _match_arm_value_39.src[2] + connect _bundle_literal_expr_80.reversed_src, _array_literal_expr_30 + connect _bundle_literal_expr_80.imm_sign, _match_arm_value_39.imm_sign + wire _cast_bundle_to_bits_expr_33: Ty51 + connect _cast_bundle_to_bits_expr_33.imm_low, _bundle_literal_expr_80.imm_low + connect _cast_bundle_to_bits_expr_33.reversed_src, _bundle_literal_expr_80.reversed_src[0] + connect _cast_bundle_to_bits_expr_33.imm_sign, asUInt(_bundle_literal_expr_80.imm_sign) + wire _cast_to_bits_expr_33: UInt<34> + connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_33.imm_sign, cat(_cast_bundle_to_bits_expr_33.reversed_src, _cast_bundle_to_bits_expr_33.imm_low)) + connect _bundle_literal_expr_78.imm_low, bits(asSInt(_cast_to_bits_expr_33), 24, 0) + wire _bundle_literal_expr_81: Ty50 + connect _bundle_literal_expr_81.imm_low, _match_arm_value_39.imm_low + wire _array_literal_expr_31: UInt<8>[1] + connect _array_literal_expr_31[0], _match_arm_value_39.src[2] + connect _bundle_literal_expr_81.reversed_src, _array_literal_expr_31 + connect _bundle_literal_expr_81.imm_sign, _match_arm_value_39.imm_sign + wire _cast_bundle_to_bits_expr_34: Ty51 + connect _cast_bundle_to_bits_expr_34.imm_low, _bundle_literal_expr_81.imm_low + connect _cast_bundle_to_bits_expr_34.reversed_src, _bundle_literal_expr_81.reversed_src[0] + connect _cast_bundle_to_bits_expr_34.imm_sign, asUInt(_bundle_literal_expr_81.imm_sign) + wire _cast_to_bits_expr_34: UInt<34> + connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_34.imm_sign, cat(_cast_bundle_to_bits_expr_34.reversed_src, _cast_bundle_to_bits_expr_34.imm_low)) + connect _bundle_literal_expr_78.imm_sign, shr(asSInt(_cast_to_bits_expr_34), 33) + wire _bundle_literal_expr_82: Ty2 + invalidate _bundle_literal_expr_82 + connect _bundle_literal_expr_78._phantom, _bundle_literal_expr_82 + connect mapped_regs_3, {|Load: Ty38, Store: Ty38|}(Load, _bundle_literal_expr_78) @[instruction.rs 539:1] + Store(_match_arm_value_40): + wire renamed_src_reg_0_0_4: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_83: Ty1 + connect _bundle_literal_expr_83.value, _match_arm_value_40.src[0] + connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_83 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_84: Ty1 + connect _bundle_literal_expr_84.value, _match_arm_value_40.src[0] + connect rename_table_special_0_src_0.addr, _bundle_literal_expr_84 @[reg_alloc.rs 182:29] + match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_85: Ty25 + wire _bundle_literal_expr_86: Ty23 + connect _bundle_literal_expr_86.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_85.unit_num, _bundle_literal_expr_86 + wire _bundle_literal_expr_87: Ty24 + connect _bundle_literal_expr_87.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_85.unit_out_reg, _bundle_literal_expr_87 + connect renamed_src_reg_0_0_4, _bundle_literal_expr_85 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_41): + connect renamed_src_reg_0_0_4, _match_arm_value_41 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_42): + connect renamed_src_reg_0_0_4, _match_arm_value_42 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_88: Ty38 + connect _bundle_literal_expr_88.prefix_pad, _match_arm_value_40.prefix_pad + connect _bundle_literal_expr_88.dest, _match_arm_value_4.unit_out_reg + wire _array_literal_expr_32: UInt<6>[3] + wire _array_literal_expr_33: UInt<6>[1] + wire _cast_bundle_to_bits_expr_35: Ty47 + connect _cast_bundle_to_bits_expr_35.unit_num, renamed_src_reg_0_0_4.unit_num.adj_value + connect _cast_bundle_to_bits_expr_35.unit_out_reg, renamed_src_reg_0_0_4.unit_out_reg.value + wire _cast_to_bits_expr_35: UInt<6> + connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num) + connect _array_literal_expr_33[0], _cast_to_bits_expr_35 + connect _array_literal_expr_32[0], _array_literal_expr_33[0] + connect _array_literal_expr_32[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_89: Ty50 + connect _bundle_literal_expr_89.imm_low, _match_arm_value_40.imm_low + wire _array_literal_expr_34: UInt<8>[1] + connect _array_literal_expr_34[0], _match_arm_value_40.src[2] + connect _bundle_literal_expr_89.reversed_src, _array_literal_expr_34 + connect _bundle_literal_expr_89.imm_sign, _match_arm_value_40.imm_sign + wire _cast_bundle_to_bits_expr_36: Ty51 + connect _cast_bundle_to_bits_expr_36.imm_low, _bundle_literal_expr_89.imm_low + connect _cast_bundle_to_bits_expr_36.reversed_src, _bundle_literal_expr_89.reversed_src[0] + connect _cast_bundle_to_bits_expr_36.imm_sign, asUInt(_bundle_literal_expr_89.imm_sign) + wire _cast_to_bits_expr_36: UInt<34> + connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_36.imm_sign, cat(_cast_bundle_to_bits_expr_36.reversed_src, _cast_bundle_to_bits_expr_36.imm_low)) + wire _cast_bits_to_bundle_expr_5: Ty50 + wire _cast_bits_to_bundle_expr_flattened_5: Ty51 + connect _cast_bits_to_bundle_expr_flattened_5.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 24, 0) + connect _cast_bits_to_bundle_expr_5.imm_low, _cast_bits_to_bundle_expr_flattened_5.imm_low + connect _cast_bits_to_bundle_expr_flattened_5.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 32, 25) + wire _cast_bits_to_array_expr_5: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_5: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_5[0], bits(_cast_bits_to_bundle_expr_flattened_5.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_bundle_expr_5.reversed_src, _cast_bits_to_array_expr_5 + connect _cast_bits_to_bundle_expr_flattened_5.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 33, 33) + connect _cast_bits_to_bundle_expr_5.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_5.imm_sign) + connect _array_literal_expr_32[2], tail(_cast_bits_to_bundle_expr_5.reversed_src[0], 2) + connect _bundle_literal_expr_88.src, _array_literal_expr_32 + wire _bundle_literal_expr_90: Ty50 + connect _bundle_literal_expr_90.imm_low, _match_arm_value_40.imm_low + wire _array_literal_expr_35: UInt<8>[1] + connect _array_literal_expr_35[0], _match_arm_value_40.src[2] + connect _bundle_literal_expr_90.reversed_src, _array_literal_expr_35 + connect _bundle_literal_expr_90.imm_sign, _match_arm_value_40.imm_sign + wire _cast_bundle_to_bits_expr_37: Ty51 + connect _cast_bundle_to_bits_expr_37.imm_low, _bundle_literal_expr_90.imm_low + connect _cast_bundle_to_bits_expr_37.reversed_src, _bundle_literal_expr_90.reversed_src[0] + connect _cast_bundle_to_bits_expr_37.imm_sign, asUInt(_bundle_literal_expr_90.imm_sign) + wire _cast_to_bits_expr_37: UInt<34> + connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_37.imm_sign, cat(_cast_bundle_to_bits_expr_37.reversed_src, _cast_bundle_to_bits_expr_37.imm_low)) + connect _bundle_literal_expr_88.imm_low, bits(asSInt(_cast_to_bits_expr_37), 24, 0) + wire _bundle_literal_expr_91: Ty50 + connect _bundle_literal_expr_91.imm_low, _match_arm_value_40.imm_low + wire _array_literal_expr_36: UInt<8>[1] + connect _array_literal_expr_36[0], _match_arm_value_40.src[2] + connect _bundle_literal_expr_91.reversed_src, _array_literal_expr_36 + connect _bundle_literal_expr_91.imm_sign, _match_arm_value_40.imm_sign + wire _cast_bundle_to_bits_expr_38: Ty51 + connect _cast_bundle_to_bits_expr_38.imm_low, _bundle_literal_expr_91.imm_low + connect _cast_bundle_to_bits_expr_38.reversed_src, _bundle_literal_expr_91.reversed_src[0] + connect _cast_bundle_to_bits_expr_38.imm_sign, asUInt(_bundle_literal_expr_91.imm_sign) + wire _cast_to_bits_expr_38: UInt<34> + connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_38.imm_sign, cat(_cast_bundle_to_bits_expr_38.reversed_src, _cast_bundle_to_bits_expr_38.imm_low)) + connect _bundle_literal_expr_88.imm_sign, shr(asSInt(_cast_to_bits_expr_38), 33) + wire _bundle_literal_expr_92: Ty2 + invalidate _bundle_literal_expr_92 + connect _bundle_literal_expr_88._phantom, _bundle_literal_expr_92 + connect mapped_regs_3, {|Load: Ty38, Store: Ty38|}(Store, _bundle_literal_expr_88) @[instruction.rs 539:1] + connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(LoadStore, mapped_regs_3) @[unit.rs 127:1] + connect renamed_mops[0], {|HdlNone, HdlSome: Ty42|}(HdlSome, mapped_regs) @[reg_alloc.rs 167:17] + wire selected_unit_index_leaf_0_0: Ty32 @[reg_alloc.rs 209:25] + connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21] + wire unit_index_0_0: UInt<2> @[reg_alloc.rs 218:25] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<64> + connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 221:21] + when available_units[0][0]: @[reg_alloc.rs 223:21] + connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 224:25] + wire selected_unit_index_leaf_0_1: Ty32 @[reg_alloc.rs 209:25] + connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21] + wire unit_index_0_1: UInt<2> @[reg_alloc.rs 218:25] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<64> + connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 221:21] + when available_units[0][1]: @[reg_alloc.rs 223:21] + connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 224:25] + wire selected_unit_index_node_0_0: Ty32 @[reg_alloc.rs 231:25] + connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 235:21] + match selected_unit_index_leaf_0_0: @[reg_alloc.rs 237:21] + HdlNone: + connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 238:25] + HdlSome(_match_arm_value_43): + skip + connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 201:9] + connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 79:9] + wire _array_literal_expr_37: UInt<1>[2] + connect _array_literal_expr_37[0], UInt<1>(0h0) + connect _array_literal_expr_37[1], UInt<1>(0h0) + connect available_units[1], _array_literal_expr_37 @[reg_alloc.rs 83:9] + connect renamed_mops[1], {|HdlNone, HdlSome: Ty42|}(HdlNone) @[reg_alloc.rs 87:9] + connect rename_table_normal_mem_r3.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r3.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r3.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_1_src_0: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_93: Ty1 + connect _bundle_literal_expr_93.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_93 @[reg_alloc.rs 111:17] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r3.addr, sub(rename_table_normal_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r3.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r3.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_44): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_45): + wire dest_reg_4: Ty4 @[unit.rs 127:1] + match _match_arm_value_44.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_46): + wire dest_reg_5: Ty4 @[instruction.rs 477:1] + match _match_arm_value_46: @[instruction.rs 477:1] + AddSub(_match_arm_value_47): + connect dest_reg_5, _match_arm_value_47.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_48): + connect dest_reg_5, _match_arm_value_48.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_49): + connect dest_reg_5, _match_arm_value_49.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_4, dest_reg_5 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_50): + wire dest_reg_6: Ty4 @[instruction.rs 504:1] + match _match_arm_value_50: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_51): + connect dest_reg_6, _match_arm_value_51.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_52): + connect dest_reg_6, _match_arm_value_52.common.dest @[instruction.rs 504:1] + connect dest_reg_4, dest_reg_6 @[unit.rs 127:1] + LoadStore(_match_arm_value_53): + wire dest_reg_7: Ty4 @[instruction.rs 539:1] + match _match_arm_value_53: @[instruction.rs 539:1] + Load(_match_arm_value_54): + connect dest_reg_7, _match_arm_value_54.dest @[instruction.rs 539:1] + Store(_match_arm_value_55): + connect dest_reg_7, _match_arm_value_55.dest @[instruction.rs 539:1] + connect dest_reg_4, dest_reg_7 @[unit.rs 127:1] + wire flag_reg: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_94: Ty1 + connect _bundle_literal_expr_94.value, tail(UInt<32>(0h0), 24) + connect flag_reg, _bundle_literal_expr_94 @[instruction.rs 721:17] + match dest_reg_4.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_56): + wire _bundle_literal_expr_95: Ty1 + connect _bundle_literal_expr_95.value, tail(UInt<32>(0hFE), 24) + connect flag_reg, _bundle_literal_expr_95 @[instruction.rs 725:21] + wire flag_reg_1: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_96: Ty1 + connect _bundle_literal_expr_96.value, tail(UInt<32>(0h0), 24) + connect flag_reg_1, _bundle_literal_expr_96 @[instruction.rs 721:17] + match dest_reg_4.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_57): + wire _bundle_literal_expr_97: Ty1 + connect _bundle_literal_expr_97.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_1, _bundle_literal_expr_97 @[instruction.rs 725:21] + when eq(dest_reg_4.normal_regs[0].value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41] + when eq(dest_reg_4.normal_regs[1].value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41] + when eq(flag_reg.value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41] + when eq(flag_reg_1.value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41] + connect rename_table_normal_mem_r4.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r4.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r4.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_1_src_1: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_98: Ty1 + connect _bundle_literal_expr_98.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_98 @[reg_alloc.rs 111:17] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r4.addr, sub(rename_table_normal_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r4.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r4.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_58): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_59): + wire dest_reg_8: Ty4 @[unit.rs 127:1] + match _match_arm_value_58.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_60): + wire dest_reg_9: Ty4 @[instruction.rs 477:1] + match _match_arm_value_60: @[instruction.rs 477:1] + AddSub(_match_arm_value_61): + connect dest_reg_9, _match_arm_value_61.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_62): + connect dest_reg_9, _match_arm_value_62.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_63): + connect dest_reg_9, _match_arm_value_63.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_8, dest_reg_9 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_64): + wire dest_reg_10: Ty4 @[instruction.rs 504:1] + match _match_arm_value_64: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_65): + connect dest_reg_10, _match_arm_value_65.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_66): + connect dest_reg_10, _match_arm_value_66.common.dest @[instruction.rs 504:1] + connect dest_reg_8, dest_reg_10 @[unit.rs 127:1] + LoadStore(_match_arm_value_67): + wire dest_reg_11: Ty4 @[instruction.rs 539:1] + match _match_arm_value_67: @[instruction.rs 539:1] + Load(_match_arm_value_68): + connect dest_reg_11, _match_arm_value_68.dest @[instruction.rs 539:1] + Store(_match_arm_value_69): + connect dest_reg_11, _match_arm_value_69.dest @[instruction.rs 539:1] + connect dest_reg_8, dest_reg_11 @[unit.rs 127:1] + wire flag_reg_2: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_99: Ty1 + connect _bundle_literal_expr_99.value, tail(UInt<32>(0h0), 24) + connect flag_reg_2, _bundle_literal_expr_99 @[instruction.rs 721:17] + match dest_reg_8.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_70): + wire _bundle_literal_expr_100: Ty1 + connect _bundle_literal_expr_100.value, tail(UInt<32>(0hFE), 24) + connect flag_reg_2, _bundle_literal_expr_100 @[instruction.rs 725:21] + wire flag_reg_3: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_101: Ty1 + connect _bundle_literal_expr_101.value, tail(UInt<32>(0h0), 24) + connect flag_reg_3, _bundle_literal_expr_101 @[instruction.rs 721:17] + match dest_reg_8.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_71): + wire _bundle_literal_expr_102: Ty1 + connect _bundle_literal_expr_102.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_3, _bundle_literal_expr_102 @[instruction.rs 725:21] + when eq(dest_reg_8.normal_regs[0].value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41] + when eq(dest_reg_8.normal_regs[1].value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41] + when eq(flag_reg_2.value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41] + when eq(flag_reg_3.value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41] + connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 103:17] + connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_normal_1_src_2: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_103: Ty1 + connect _bundle_literal_expr_103.value, tail(UInt<32>(0h0), 24) + connect rename_table_normal_1_src_2.addr, _bundle_literal_expr_103 @[reg_alloc.rs 111:17] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_normal_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<8> + ; rhs: UInt<33> + connect rename_table_normal_mem_r5.addr, sub(rename_table_normal_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21] + connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r5.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_72): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_73): + wire dest_reg_12: Ty4 @[unit.rs 127:1] + match _match_arm_value_72.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_74): + wire dest_reg_13: Ty4 @[instruction.rs 477:1] + match _match_arm_value_74: @[instruction.rs 477:1] + AddSub(_match_arm_value_75): + connect dest_reg_13, _match_arm_value_75.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_76): + connect dest_reg_13, _match_arm_value_76.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_77): + connect dest_reg_13, _match_arm_value_77.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_12, dest_reg_13 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_78): + wire dest_reg_14: Ty4 @[instruction.rs 504:1] + match _match_arm_value_78: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_79): + connect dest_reg_14, _match_arm_value_79.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_80): + connect dest_reg_14, _match_arm_value_80.common.dest @[instruction.rs 504:1] + connect dest_reg_12, dest_reg_14 @[unit.rs 127:1] + LoadStore(_match_arm_value_81): + wire dest_reg_15: Ty4 @[instruction.rs 539:1] + match _match_arm_value_81: @[instruction.rs 539:1] + Load(_match_arm_value_82): + connect dest_reg_15, _match_arm_value_82.dest @[instruction.rs 539:1] + Store(_match_arm_value_83): + connect dest_reg_15, _match_arm_value_83.dest @[instruction.rs 539:1] + connect dest_reg_12, dest_reg_15 @[unit.rs 127:1] + wire flag_reg_4: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_104: Ty1 + connect _bundle_literal_expr_104.value, tail(UInt<32>(0h0), 24) + connect flag_reg_4, _bundle_literal_expr_104 @[instruction.rs 721:17] + match dest_reg_12.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_84): + wire _bundle_literal_expr_105: Ty1 + connect _bundle_literal_expr_105.value, tail(UInt<32>(0hFE), 24) + connect flag_reg_4, _bundle_literal_expr_105 @[instruction.rs 725:21] + wire flag_reg_5: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_106: Ty1 + connect _bundle_literal_expr_106.value, tail(UInt<32>(0h0), 24) + connect flag_reg_5, _bundle_literal_expr_106 @[instruction.rs 721:17] + match dest_reg_12.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_85): + wire _bundle_literal_expr_107: Ty1 + connect _bundle_literal_expr_107.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_5, _bundle_literal_expr_107 @[instruction.rs 725:21] + when eq(dest_reg_12.normal_regs[0].value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41] + when eq(dest_reg_12.normal_regs[1].value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41] + when eq(flag_reg_4.value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41] + when eq(flag_reg_5.value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41] + connect rename_table_special_mem_r3.clk, cd.clk @[reg_alloc.rs 103:17] ; connect different types: ; lhs: UInt<1> - ; rhs: UInt<64> - connect unit_num_0_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21] - when available_units[0][0]: @[reg_alloc.rs 95:21] - connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_0_0) @[reg_alloc.rs 96:25] - connect selected_unit_nums[0], selected_unit_leaf_0_0 @[reg_alloc.rs 76:9] - connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9] - wire _array_literal_expr_1: UInt<1>[1] - connect _array_literal_expr_1[0], UInt<1>(0h0) - connect available_units[1], _array_literal_expr_1 @[reg_alloc.rs 65:9] - match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 70:9] - HdlNone: - skip - HdlSome(_match_arm_value_4): - wire unit_kind_1: Ty22 @[unit.rs 107:1] - match _match_arm_value_4.uop: @[unit.rs 107:1] - AluBranch(_match_arm_value_5): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1] - L2RegisterFile(_match_arm_value_6): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1] - LoadStore(_match_arm_value_7): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1] - wire available_units_for_kind_1: UInt<1>[1] @[unit.rs 107:1] - match unit_kind_1: @[unit.rs 107:1] - AluBranch: - connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 107:1] - L2RegisterFile: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1] - LoadStore: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1] - connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 71:13] - wire selected_unit_leaf_1_0: Ty21 @[reg_alloc.rs 84:25] - connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21] - wire unit_num_1_0: Ty20 @[reg_alloc.rs 90:25] + ; rhs: UInt<8> + connect rename_table_special_mem_r3.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r3.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_1_src_0: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_108: Ty1 + connect _bundle_literal_expr_108.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_108 @[reg_alloc.rs 111:17] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r3.addr, sub(rename_table_special_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r3.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r3.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_86): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_87): + wire dest_reg_16: Ty4 @[unit.rs 127:1] + match _match_arm_value_86.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_88): + wire dest_reg_17: Ty4 @[instruction.rs 477:1] + match _match_arm_value_88: @[instruction.rs 477:1] + AddSub(_match_arm_value_89): + connect dest_reg_17, _match_arm_value_89.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_90): + connect dest_reg_17, _match_arm_value_90.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_91): + connect dest_reg_17, _match_arm_value_91.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_16, dest_reg_17 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_92): + wire dest_reg_18: Ty4 @[instruction.rs 504:1] + match _match_arm_value_92: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_93): + connect dest_reg_18, _match_arm_value_93.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_94): + connect dest_reg_18, _match_arm_value_94.common.dest @[instruction.rs 504:1] + connect dest_reg_16, dest_reg_18 @[unit.rs 127:1] + LoadStore(_match_arm_value_95): + wire dest_reg_19: Ty4 @[instruction.rs 539:1] + match _match_arm_value_95: @[instruction.rs 539:1] + Load(_match_arm_value_96): + connect dest_reg_19, _match_arm_value_96.dest @[instruction.rs 539:1] + Store(_match_arm_value_97): + connect dest_reg_19, _match_arm_value_97.dest @[instruction.rs 539:1] + connect dest_reg_16, dest_reg_19 @[unit.rs 127:1] + wire flag_reg_6: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_109: Ty1 + connect _bundle_literal_expr_109.value, tail(UInt<32>(0h0), 24) + connect flag_reg_6, _bundle_literal_expr_109 @[instruction.rs 721:17] + match dest_reg_16.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_98): + wire _bundle_literal_expr_110: Ty1 + connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFE), 24) + connect flag_reg_6, _bundle_literal_expr_110 @[instruction.rs 725:21] + wire flag_reg_7: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_111: Ty1 + connect _bundle_literal_expr_111.value, tail(UInt<32>(0h0), 24) + connect flag_reg_7, _bundle_literal_expr_111 @[instruction.rs 721:17] + match dest_reg_16.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_99): + wire _bundle_literal_expr_112: Ty1 + connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_7, _bundle_literal_expr_112 @[instruction.rs 725:21] + when eq(dest_reg_16.normal_regs[0].value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41] + when eq(dest_reg_16.normal_regs[1].value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41] + when eq(flag_reg_6.value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41] + when eq(flag_reg_7.value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41] + connect rename_table_special_mem_r4.clk, cd.clk @[reg_alloc.rs 103:17] ; connect different types: ; lhs: UInt<1> - ; rhs: UInt<64> - connect unit_num_1_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21] - when available_units[1][0]: @[reg_alloc.rs 95:21] - connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_1_0) @[reg_alloc.rs 96:25] - connect selected_unit_nums[1], selected_unit_leaf_1_0 @[reg_alloc.rs 76:9] - match selected_unit_nums[0]: @[reg_alloc.rs 123:13] + ; rhs: UInt<8> + connect rename_table_special_mem_r4.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r4.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_1_src_1: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_113: Ty1 + connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_1_src_1.addr, _bundle_literal_expr_113 @[reg_alloc.rs 111:17] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r4.addr, sub(rename_table_special_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r4.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r4.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_100): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_101): + wire dest_reg_20: Ty4 @[unit.rs 127:1] + match _match_arm_value_100.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_102): + wire dest_reg_21: Ty4 @[instruction.rs 477:1] + match _match_arm_value_102: @[instruction.rs 477:1] + AddSub(_match_arm_value_103): + connect dest_reg_21, _match_arm_value_103.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_104): + connect dest_reg_21, _match_arm_value_104.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_105): + connect dest_reg_21, _match_arm_value_105.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_20, dest_reg_21 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_106): + wire dest_reg_22: Ty4 @[instruction.rs 504:1] + match _match_arm_value_106: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_107): + connect dest_reg_22, _match_arm_value_107.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_108): + connect dest_reg_22, _match_arm_value_108.common.dest @[instruction.rs 504:1] + connect dest_reg_20, dest_reg_22 @[unit.rs 127:1] + LoadStore(_match_arm_value_109): + wire dest_reg_23: Ty4 @[instruction.rs 539:1] + match _match_arm_value_109: @[instruction.rs 539:1] + Load(_match_arm_value_110): + connect dest_reg_23, _match_arm_value_110.dest @[instruction.rs 539:1] + Store(_match_arm_value_111): + connect dest_reg_23, _match_arm_value_111.dest @[instruction.rs 539:1] + connect dest_reg_20, dest_reg_23 @[unit.rs 127:1] + wire flag_reg_8: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_114: Ty1 + connect _bundle_literal_expr_114.value, tail(UInt<32>(0h0), 24) + connect flag_reg_8, _bundle_literal_expr_114 @[instruction.rs 721:17] + match dest_reg_20.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_112): + wire _bundle_literal_expr_115: Ty1 + connect _bundle_literal_expr_115.value, tail(UInt<32>(0hFE), 24) + connect flag_reg_8, _bundle_literal_expr_115 @[instruction.rs 725:21] + wire flag_reg_9: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_116: Ty1 + connect _bundle_literal_expr_116.value, tail(UInt<32>(0h0), 24) + connect flag_reg_9, _bundle_literal_expr_116 @[instruction.rs 721:17] + match dest_reg_20.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_113): + wire _bundle_literal_expr_117: Ty1 + connect _bundle_literal_expr_117.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_9, _bundle_literal_expr_117 @[instruction.rs 725:21] + when eq(dest_reg_20.normal_regs[0].value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41] + when eq(dest_reg_20.normal_regs[1].value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41] + when eq(flag_reg_8.value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41] + when eq(flag_reg_9.value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41] + connect rename_table_special_mem_r5.clk, cd.clk @[reg_alloc.rs 103:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<8> + connect rename_table_special_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17] + connect rename_table_special_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 105:17] + wire rename_table_special_1_src_2: Ty45 @[reg_alloc.rs 108:21] + wire _bundle_literal_expr_118: Ty1 + connect _bundle_literal_expr_118.value, tail(UInt<32>(0h0), 24) + connect rename_table_special_1_src_2.addr, _bundle_literal_expr_118 @[reg_alloc.rs 111:17] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17] + when and(geq(rename_table_special_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<33> + connect rename_table_special_mem_r5.addr, sub(rename_table_special_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21] + connect rename_table_special_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 116:21] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r5.data) @[reg_alloc.rs 117:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25] + HdlNone: + skip + HdlSome(_match_arm_value_114): + match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29] + HdlNone: + skip + HdlSome(_match_arm_value_115): + wire dest_reg_24: Ty4 @[unit.rs 127:1] + match _match_arm_value_114.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_116): + wire dest_reg_25: Ty4 @[instruction.rs 477:1] + match _match_arm_value_116: @[instruction.rs 477:1] + AddSub(_match_arm_value_117): + connect dest_reg_25, _match_arm_value_117.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_118): + connect dest_reg_25, _match_arm_value_118.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_119): + connect dest_reg_25, _match_arm_value_119.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_24, dest_reg_25 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_120): + wire dest_reg_26: Ty4 @[instruction.rs 504:1] + match _match_arm_value_120: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_121): + connect dest_reg_26, _match_arm_value_121.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_122): + connect dest_reg_26, _match_arm_value_122.common.dest @[instruction.rs 504:1] + connect dest_reg_24, dest_reg_26 @[unit.rs 127:1] + LoadStore(_match_arm_value_123): + wire dest_reg_27: Ty4 @[instruction.rs 539:1] + match _match_arm_value_123: @[instruction.rs 539:1] + Load(_match_arm_value_124): + connect dest_reg_27, _match_arm_value_124.dest @[instruction.rs 539:1] + Store(_match_arm_value_125): + connect dest_reg_27, _match_arm_value_125.dest @[instruction.rs 539:1] + connect dest_reg_24, dest_reg_27 @[unit.rs 127:1] + wire flag_reg_10: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_119: Ty1 + connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24) + connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 721:17] + match dest_reg_24.flag_regs[0]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_126): + wire _bundle_literal_expr_120: Ty1 + connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24) + connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 725:21] + wire flag_reg_11: Ty1 @[instruction.rs 720:32] + wire _bundle_literal_expr_121: Ty1 + connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24) + connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 721:17] + match dest_reg_24.flag_regs[1]: @[instruction.rs 723:17] + HdlNone: + skip + HdlSome(_match_arm_value_127): + wire _bundle_literal_expr_122: Ty1 + connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24) + connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 725:21] + when eq(dest_reg_24.normal_regs[0].value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41] + when eq(dest_reg_24.normal_regs[1].value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41] + when eq(flag_reg_10.value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41] + when eq(flag_reg_11.value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37] + connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41] + match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 159:9] HdlNone: skip - HdlSome(_match_arm_value_8): - connect available_units[1][_match_arm_value_8.value], UInt<1>(0h0) @[reg_alloc.rs 124:17] - inst unit_0 of alu_branch @[reg_alloc.rs 136:13] - connect unit_0.cd, cd @[reg_alloc.rs 138:9] - inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 150:13] - connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 152:9] - wire _uninit_expr: Ty24 + HdlSome(_match_arm_value_128): + wire unit_kind_1: Ty46 @[unit.rs 127:1] + match _match_arm_value_128.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_129): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_130): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 127:1] + LoadStore(_match_arm_value_131): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 127:1] + wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 127:1] + match unit_kind_1: @[unit.rs 127:1] + AluBranch: + connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 127:1] + connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 127:1] + L2RegisterFile: + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 127:1] + LoadStore: + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 160:13] + match renamed_mops_out_reg[1]: @[reg_alloc.rs 165:13] + HdlNone: + skip + HdlSome(_match_arm_value_132): + wire dest_reg_28: Ty4 @[unit.rs 127:1] + match _match_arm_value_128.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_133): + wire dest_reg_29: Ty4 @[instruction.rs 477:1] + match _match_arm_value_133: @[instruction.rs 477:1] + AddSub(_match_arm_value_134): + connect dest_reg_29, _match_arm_value_134.alu_common.common.dest @[instruction.rs 477:1] + AddSubI(_match_arm_value_135): + connect dest_reg_29, _match_arm_value_135.alu_common.common.dest @[instruction.rs 477:1] + Logical(_match_arm_value_136): + connect dest_reg_29, _match_arm_value_136.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_28, dest_reg_29 @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_137): + wire dest_reg_30: Ty4 @[instruction.rs 504:1] + match _match_arm_value_137: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_138): + connect dest_reg_30, _match_arm_value_138.common.dest @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_139): + connect dest_reg_30, _match_arm_value_139.common.dest @[instruction.rs 504:1] + connect dest_reg_28, dest_reg_30 @[unit.rs 127:1] + LoadStore(_match_arm_value_140): + wire dest_reg_31: Ty4 @[instruction.rs 539:1] + match _match_arm_value_140: @[instruction.rs 539:1] + Load(_match_arm_value_141): + connect dest_reg_31, _match_arm_value_141.dest @[instruction.rs 539:1] + Store(_match_arm_value_142): + connect dest_reg_31, _match_arm_value_142.dest @[instruction.rs 539:1] + connect dest_reg_28, dest_reg_31 @[unit.rs 127:1] + wire mapped_regs_4: Ty42 @[unit.rs 127:1] + match _match_arm_value_128.mop: @[unit.rs 127:1] + AluBranch(_match_arm_value_143): + wire mapped_regs_5: Ty37 @[instruction.rs 477:1] + match _match_arm_value_143: @[instruction.rs 477:1] + AddSub(_match_arm_value_144): + wire renamed_src_reg_1_0: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_123: Ty1 + connect _bundle_literal_expr_123.value, _match_arm_value_144.alu_common.common.src[0] + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_123 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_124: Ty1 + connect _bundle_literal_expr_124.value, _match_arm_value_144.alu_common.common.src[0] + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_124 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_125: Ty25 + wire _bundle_literal_expr_126: Ty23 + connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126 + wire _bundle_literal_expr_127: Ty24 + connect _bundle_literal_expr_127.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_125.unit_out_reg, _bundle_literal_expr_127 + connect renamed_src_reg_1_0, _bundle_literal_expr_125 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_145): + connect renamed_src_reg_1_0, _match_arm_value_145 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_146): + connect renamed_src_reg_1_0, _match_arm_value_146 @[reg_alloc.rs 185:33] + wire renamed_src_reg_1_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_128: Ty1 + connect _bundle_literal_expr_128.value, _match_arm_value_144.alu_common.common.src[1] + connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_128 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_129: Ty1 + connect _bundle_literal_expr_129.value, _match_arm_value_144.alu_common.common.src[1] + connect rename_table_special_1_src_1.addr, _bundle_literal_expr_129 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_130: Ty25 + wire _bundle_literal_expr_131: Ty23 + connect _bundle_literal_expr_131.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_130.unit_num, _bundle_literal_expr_131 + wire _bundle_literal_expr_132: Ty24 + connect _bundle_literal_expr_132.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_130.unit_out_reg, _bundle_literal_expr_132 + connect renamed_src_reg_1_1, _bundle_literal_expr_130 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_147): + connect renamed_src_reg_1_1, _match_arm_value_147 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_148): + connect renamed_src_reg_1_1, _match_arm_value_148 @[reg_alloc.rs 185:33] + wire renamed_src_reg_1_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_133: Ty1 + connect _bundle_literal_expr_133.value, _match_arm_value_144.alu_common.common.src[2] + connect rename_table_normal_1_src_2.addr, _bundle_literal_expr_133 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_134: Ty1 + connect _bundle_literal_expr_134.value, _match_arm_value_144.alu_common.common.src[2] + connect rename_table_special_1_src_2.addr, _bundle_literal_expr_134 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_2.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_2.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_135: Ty25 + wire _bundle_literal_expr_136: Ty23 + connect _bundle_literal_expr_136.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_135.unit_num, _bundle_literal_expr_136 + wire _bundle_literal_expr_137: Ty24 + connect _bundle_literal_expr_137.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_135.unit_out_reg, _bundle_literal_expr_137 + connect renamed_src_reg_1_2, _bundle_literal_expr_135 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_149): + connect renamed_src_reg_1_2, _match_arm_value_149 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_150): + connect renamed_src_reg_1_2, _match_arm_value_150 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_138: Ty35 + wire _bundle_literal_expr_139: Ty34 + wire _bundle_literal_expr_140: Ty33 + connect _bundle_literal_expr_140.prefix_pad, _match_arm_value_144.alu_common.common.prefix_pad + connect _bundle_literal_expr_140.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_38: UInt<6>[3] + wire _array_literal_expr_39: UInt<6>[3] + wire _cast_bundle_to_bits_expr_39: Ty47 + connect _cast_bundle_to_bits_expr_39.unit_num, renamed_src_reg_1_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr_39.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value + wire _cast_to_bits_expr_39: UInt<6> + connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num) + connect _array_literal_expr_39[0], _cast_to_bits_expr_39 + wire _cast_bundle_to_bits_expr_40: Ty47 + connect _cast_bundle_to_bits_expr_40.unit_num, renamed_src_reg_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_40.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value + wire _cast_to_bits_expr_40: UInt<6> + connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num) + connect _array_literal_expr_39[1], _cast_to_bits_expr_40 + wire _cast_bundle_to_bits_expr_41: Ty47 + connect _cast_bundle_to_bits_expr_41.unit_num, renamed_src_reg_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_41.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value + wire _cast_to_bits_expr_41: UInt<6> + connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num) + connect _array_literal_expr_39[2], _cast_to_bits_expr_41 + connect _array_literal_expr_38[0], _array_literal_expr_39[0] + wire _array_literal_expr_40: UInt<6>[3] + wire _cast_bundle_to_bits_expr_42: Ty47 + connect _cast_bundle_to_bits_expr_42.unit_num, renamed_src_reg_1_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr_42.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value + wire _cast_to_bits_expr_42: UInt<6> + connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num) + connect _array_literal_expr_40[0], _cast_to_bits_expr_42 + wire _cast_bundle_to_bits_expr_43: Ty47 + connect _cast_bundle_to_bits_expr_43.unit_num, renamed_src_reg_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_43.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value + wire _cast_to_bits_expr_43: UInt<6> + connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num) + connect _array_literal_expr_40[1], _cast_to_bits_expr_43 + wire _cast_bundle_to_bits_expr_44: Ty47 + connect _cast_bundle_to_bits_expr_44.unit_num, renamed_src_reg_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_44.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value + wire _cast_to_bits_expr_44: UInt<6> + connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num) + connect _array_literal_expr_40[2], _cast_to_bits_expr_44 + connect _array_literal_expr_38[1], _array_literal_expr_40[1] + wire _array_literal_expr_41: UInt<6>[3] + wire _cast_bundle_to_bits_expr_45: Ty47 + connect _cast_bundle_to_bits_expr_45.unit_num, renamed_src_reg_1_0.unit_num.adj_value + connect _cast_bundle_to_bits_expr_45.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value + wire _cast_to_bits_expr_45: UInt<6> + connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num) + connect _array_literal_expr_41[0], _cast_to_bits_expr_45 + wire _cast_bundle_to_bits_expr_46: Ty47 + connect _cast_bundle_to_bits_expr_46.unit_num, renamed_src_reg_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_46.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value + wire _cast_to_bits_expr_46: UInt<6> + connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num) + connect _array_literal_expr_41[1], _cast_to_bits_expr_46 + wire _cast_bundle_to_bits_expr_47: Ty47 + connect _cast_bundle_to_bits_expr_47.unit_num, renamed_src_reg_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_47.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value + wire _cast_to_bits_expr_47: UInt<6> + connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num) + connect _array_literal_expr_41[2], _cast_to_bits_expr_47 + connect _array_literal_expr_38[2], _array_literal_expr_41[2] + connect _bundle_literal_expr_140.src, _array_literal_expr_38 + wire _bundle_literal_expr_141: Ty48 + connect _bundle_literal_expr_141.imm_low, _match_arm_value_144.alu_common.common.imm_low + wire _array_literal_expr_42: UInt<8>[0] + invalidate _array_literal_expr_42 + connect _bundle_literal_expr_141.reversed_src, _array_literal_expr_42 + connect _bundle_literal_expr_141.imm_sign, _match_arm_value_144.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_48: Ty49 + connect _cast_bundle_to_bits_expr_48.imm_low, _bundle_literal_expr_141.imm_low + connect _cast_bundle_to_bits_expr_48.reversed_src, UInt<0>(0) + connect _cast_bundle_to_bits_expr_48.imm_sign, asUInt(_bundle_literal_expr_141.imm_sign) + wire _cast_to_bits_expr_48: UInt<26> + connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_48.imm_sign, cat(_cast_bundle_to_bits_expr_48.reversed_src, _cast_bundle_to_bits_expr_48.imm_low)) + connect _bundle_literal_expr_140.imm_low, bits(asSInt(_cast_to_bits_expr_48), 24, 0) + wire _bundle_literal_expr_142: Ty48 + connect _bundle_literal_expr_142.imm_low, _match_arm_value_144.alu_common.common.imm_low + wire _array_literal_expr_43: UInt<8>[0] + invalidate _array_literal_expr_43 + connect _bundle_literal_expr_142.reversed_src, _array_literal_expr_43 + connect _bundle_literal_expr_142.imm_sign, _match_arm_value_144.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_49: Ty49 + connect _cast_bundle_to_bits_expr_49.imm_low, _bundle_literal_expr_142.imm_low + connect _cast_bundle_to_bits_expr_49.reversed_src, UInt<0>(0) + connect _cast_bundle_to_bits_expr_49.imm_sign, asUInt(_bundle_literal_expr_142.imm_sign) + wire _cast_to_bits_expr_49: UInt<26> + connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_49.imm_sign, cat(_cast_bundle_to_bits_expr_49.reversed_src, _cast_bundle_to_bits_expr_49.imm_low)) + connect _bundle_literal_expr_140.imm_sign, shr(asSInt(_cast_to_bits_expr_49), 25) + wire _bundle_literal_expr_143: Ty2 + invalidate _bundle_literal_expr_143 + connect _bundle_literal_expr_140._phantom, _bundle_literal_expr_143 + connect _bundle_literal_expr_139.common, _bundle_literal_expr_140 + connect _bundle_literal_expr_139.output_integer_mode, _match_arm_value_144.alu_common.output_integer_mode + connect _bundle_literal_expr_138.alu_common, _bundle_literal_expr_139 + connect _bundle_literal_expr_138.invert_src0, _match_arm_value_144.invert_src0 + connect _bundle_literal_expr_138.invert_carry_in, _match_arm_value_144.invert_carry_in + connect _bundle_literal_expr_138.invert_carry_out, _match_arm_value_144.invert_carry_out + connect _bundle_literal_expr_138.add_pc, _match_arm_value_144.add_pc + connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSub, _bundle_literal_expr_138) @[instruction.rs 477:1] + AddSubI(_match_arm_value_151): + wire renamed_src_reg_1_0_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_144: Ty1 + connect _bundle_literal_expr_144.value, _match_arm_value_151.alu_common.common.src[0] + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_144 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_145: Ty1 + connect _bundle_literal_expr_145.value, _match_arm_value_151.alu_common.common.src[0] + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_145 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_146: Ty25 + wire _bundle_literal_expr_147: Ty23 + connect _bundle_literal_expr_147.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_146.unit_num, _bundle_literal_expr_147 + wire _bundle_literal_expr_148: Ty24 + connect _bundle_literal_expr_148.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_146.unit_out_reg, _bundle_literal_expr_148 + connect renamed_src_reg_1_0_1, _bundle_literal_expr_146 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_152): + connect renamed_src_reg_1_0_1, _match_arm_value_152 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_153): + connect renamed_src_reg_1_0_1, _match_arm_value_153 @[reg_alloc.rs 185:33] + wire renamed_src_reg_1_1_1: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_149: Ty1 + connect _bundle_literal_expr_149.value, _match_arm_value_151.alu_common.common.src[1] + connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_149 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_150: Ty1 + connect _bundle_literal_expr_150.value, _match_arm_value_151.alu_common.common.src[1] + connect rename_table_special_1_src_1.addr, _bundle_literal_expr_150 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_151: Ty25 + wire _bundle_literal_expr_152: Ty23 + connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152 + wire _bundle_literal_expr_153: Ty24 + connect _bundle_literal_expr_153.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_151.unit_out_reg, _bundle_literal_expr_153 + connect renamed_src_reg_1_1_1, _bundle_literal_expr_151 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_154): + connect renamed_src_reg_1_1_1, _match_arm_value_154 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_155): + connect renamed_src_reg_1_1_1, _match_arm_value_155 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_154: Ty35 + wire _bundle_literal_expr_155: Ty34 + wire _bundle_literal_expr_156: Ty33 + connect _bundle_literal_expr_156.prefix_pad, _match_arm_value_151.alu_common.common.prefix_pad + connect _bundle_literal_expr_156.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_44: UInt<6>[3] + wire _array_literal_expr_45: UInt<6>[2] + wire _cast_bundle_to_bits_expr_50: Ty47 + connect _cast_bundle_to_bits_expr_50.unit_num, renamed_src_reg_1_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_50.unit_out_reg, renamed_src_reg_1_0_1.unit_out_reg.value + wire _cast_to_bits_expr_50: UInt<6> + connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num) + connect _array_literal_expr_45[0], _cast_to_bits_expr_50 + wire _cast_bundle_to_bits_expr_51: Ty47 + connect _cast_bundle_to_bits_expr_51.unit_num, renamed_src_reg_1_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_51.unit_out_reg, renamed_src_reg_1_1_1.unit_out_reg.value + wire _cast_to_bits_expr_51: UInt<6> + connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num) + connect _array_literal_expr_45[1], _cast_to_bits_expr_51 + connect _array_literal_expr_44[0], _array_literal_expr_45[0] + wire _array_literal_expr_46: UInt<6>[2] + wire _cast_bundle_to_bits_expr_52: Ty47 + connect _cast_bundle_to_bits_expr_52.unit_num, renamed_src_reg_1_0_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_52.unit_out_reg, renamed_src_reg_1_0_1.unit_out_reg.value + wire _cast_to_bits_expr_52: UInt<6> + connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num) + connect _array_literal_expr_46[0], _cast_to_bits_expr_52 + wire _cast_bundle_to_bits_expr_53: Ty47 + connect _cast_bundle_to_bits_expr_53.unit_num, renamed_src_reg_1_1_1.unit_num.adj_value + connect _cast_bundle_to_bits_expr_53.unit_out_reg, renamed_src_reg_1_1_1.unit_out_reg.value + wire _cast_to_bits_expr_53: UInt<6> + connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num) + connect _array_literal_expr_46[1], _cast_to_bits_expr_53 + connect _array_literal_expr_44[1], _array_literal_expr_46[1] + wire _bundle_literal_expr_157: Ty50 + connect _bundle_literal_expr_157.imm_low, _match_arm_value_151.alu_common.common.imm_low + wire _array_literal_expr_47: UInt<8>[1] + connect _array_literal_expr_47[0], _match_arm_value_151.alu_common.common.src[2] + connect _bundle_literal_expr_157.reversed_src, _array_literal_expr_47 + connect _bundle_literal_expr_157.imm_sign, _match_arm_value_151.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_54: Ty51 + connect _cast_bundle_to_bits_expr_54.imm_low, _bundle_literal_expr_157.imm_low + connect _cast_bundle_to_bits_expr_54.reversed_src, _bundle_literal_expr_157.reversed_src[0] + connect _cast_bundle_to_bits_expr_54.imm_sign, asUInt(_bundle_literal_expr_157.imm_sign) + wire _cast_to_bits_expr_54: UInt<34> + connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_54.imm_sign, cat(_cast_bundle_to_bits_expr_54.reversed_src, _cast_bundle_to_bits_expr_54.imm_low)) + wire _cast_bits_to_bundle_expr_6: Ty50 + wire _cast_bits_to_bundle_expr_flattened_6: Ty51 + connect _cast_bits_to_bundle_expr_flattened_6.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 24, 0) + connect _cast_bits_to_bundle_expr_6.imm_low, _cast_bits_to_bundle_expr_flattened_6.imm_low + connect _cast_bits_to_bundle_expr_flattened_6.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 32, 25) + wire _cast_bits_to_array_expr_6: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_6: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_6[0], bits(_cast_bits_to_bundle_expr_flattened_6.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_6[0], _cast_bits_to_array_expr_flattened_6[0] + connect _cast_bits_to_bundle_expr_6.reversed_src, _cast_bits_to_array_expr_6 + connect _cast_bits_to_bundle_expr_flattened_6.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 33, 33) + connect _cast_bits_to_bundle_expr_6.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_6.imm_sign) + connect _array_literal_expr_44[2], tail(_cast_bits_to_bundle_expr_6.reversed_src[0], 2) + connect _bundle_literal_expr_156.src, _array_literal_expr_44 + wire _bundle_literal_expr_158: Ty50 + connect _bundle_literal_expr_158.imm_low, _match_arm_value_151.alu_common.common.imm_low + wire _array_literal_expr_48: UInt<8>[1] + connect _array_literal_expr_48[0], _match_arm_value_151.alu_common.common.src[2] + connect _bundle_literal_expr_158.reversed_src, _array_literal_expr_48 + connect _bundle_literal_expr_158.imm_sign, _match_arm_value_151.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_55: Ty51 + connect _cast_bundle_to_bits_expr_55.imm_low, _bundle_literal_expr_158.imm_low + connect _cast_bundle_to_bits_expr_55.reversed_src, _bundle_literal_expr_158.reversed_src[0] + connect _cast_bundle_to_bits_expr_55.imm_sign, asUInt(_bundle_literal_expr_158.imm_sign) + wire _cast_to_bits_expr_55: UInt<34> + connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_55.imm_sign, cat(_cast_bundle_to_bits_expr_55.reversed_src, _cast_bundle_to_bits_expr_55.imm_low)) + connect _bundle_literal_expr_156.imm_low, bits(asSInt(_cast_to_bits_expr_55), 24, 0) + wire _bundle_literal_expr_159: Ty50 + connect _bundle_literal_expr_159.imm_low, _match_arm_value_151.alu_common.common.imm_low + wire _array_literal_expr_49: UInt<8>[1] + connect _array_literal_expr_49[0], _match_arm_value_151.alu_common.common.src[2] + connect _bundle_literal_expr_159.reversed_src, _array_literal_expr_49 + connect _bundle_literal_expr_159.imm_sign, _match_arm_value_151.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_56: Ty51 + connect _cast_bundle_to_bits_expr_56.imm_low, _bundle_literal_expr_159.imm_low + connect _cast_bundle_to_bits_expr_56.reversed_src, _bundle_literal_expr_159.reversed_src[0] + connect _cast_bundle_to_bits_expr_56.imm_sign, asUInt(_bundle_literal_expr_159.imm_sign) + wire _cast_to_bits_expr_56: UInt<34> + connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_56.imm_sign, cat(_cast_bundle_to_bits_expr_56.reversed_src, _cast_bundle_to_bits_expr_56.imm_low)) + connect _bundle_literal_expr_156.imm_sign, shr(asSInt(_cast_to_bits_expr_56), 33) + wire _bundle_literal_expr_160: Ty2 + invalidate _bundle_literal_expr_160 + connect _bundle_literal_expr_156._phantom, _bundle_literal_expr_160 + connect _bundle_literal_expr_155.common, _bundle_literal_expr_156 + connect _bundle_literal_expr_155.output_integer_mode, _match_arm_value_151.alu_common.output_integer_mode + connect _bundle_literal_expr_154.alu_common, _bundle_literal_expr_155 + connect _bundle_literal_expr_154.invert_src0, _match_arm_value_151.invert_src0 + connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_151.invert_carry_in + connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_151.invert_carry_out + connect _bundle_literal_expr_154.add_pc, _match_arm_value_151.add_pc + connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSubI, _bundle_literal_expr_154) @[instruction.rs 477:1] + Logical(_match_arm_value_156): + wire renamed_src_reg_1_0_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_161: Ty1 + connect _bundle_literal_expr_161.value, _match_arm_value_156.alu_common.common.src[0] + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_161 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_162: Ty1 + connect _bundle_literal_expr_162.value, _match_arm_value_156.alu_common.common.src[0] + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_162 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_163: Ty25 + wire _bundle_literal_expr_164: Ty23 + connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164 + wire _bundle_literal_expr_165: Ty24 + connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165 + connect renamed_src_reg_1_0_2, _bundle_literal_expr_163 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_157): + connect renamed_src_reg_1_0_2, _match_arm_value_157 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_158): + connect renamed_src_reg_1_0_2, _match_arm_value_158 @[reg_alloc.rs 185:33] + wire renamed_src_reg_1_1_2: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_166: Ty1 + connect _bundle_literal_expr_166.value, _match_arm_value_156.alu_common.common.src[1] + connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_166 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_167: Ty1 + connect _bundle_literal_expr_167.value, _match_arm_value_156.alu_common.common.src[1] + connect rename_table_special_1_src_1.addr, _bundle_literal_expr_167 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_168: Ty25 + wire _bundle_literal_expr_169: Ty23 + connect _bundle_literal_expr_169.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_168.unit_num, _bundle_literal_expr_169 + wire _bundle_literal_expr_170: Ty24 + connect _bundle_literal_expr_170.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_168.unit_out_reg, _bundle_literal_expr_170 + connect renamed_src_reg_1_1_2, _bundle_literal_expr_168 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_159): + connect renamed_src_reg_1_1_2, _match_arm_value_159 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_160): + connect renamed_src_reg_1_1_2, _match_arm_value_160 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_171: Ty36 + wire _bundle_literal_expr_172: Ty34 + wire _bundle_literal_expr_173: Ty33 + connect _bundle_literal_expr_173.prefix_pad, _match_arm_value_156.alu_common.common.prefix_pad + connect _bundle_literal_expr_173.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_50: UInt<6>[3] + wire _array_literal_expr_51: UInt<6>[2] + wire _cast_bundle_to_bits_expr_57: Ty47 + connect _cast_bundle_to_bits_expr_57.unit_num, renamed_src_reg_1_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_57.unit_out_reg, renamed_src_reg_1_0_2.unit_out_reg.value + wire _cast_to_bits_expr_57: UInt<6> + connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num) + connect _array_literal_expr_51[0], _cast_to_bits_expr_57 + wire _cast_bundle_to_bits_expr_58: Ty47 + connect _cast_bundle_to_bits_expr_58.unit_num, renamed_src_reg_1_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_58.unit_out_reg, renamed_src_reg_1_1_2.unit_out_reg.value + wire _cast_to_bits_expr_58: UInt<6> + connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num) + connect _array_literal_expr_51[1], _cast_to_bits_expr_58 + connect _array_literal_expr_50[0], _array_literal_expr_51[0] + wire _array_literal_expr_52: UInt<6>[2] + wire _cast_bundle_to_bits_expr_59: Ty47 + connect _cast_bundle_to_bits_expr_59.unit_num, renamed_src_reg_1_0_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_59.unit_out_reg, renamed_src_reg_1_0_2.unit_out_reg.value + wire _cast_to_bits_expr_59: UInt<6> + connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num) + connect _array_literal_expr_52[0], _cast_to_bits_expr_59 + wire _cast_bundle_to_bits_expr_60: Ty47 + connect _cast_bundle_to_bits_expr_60.unit_num, renamed_src_reg_1_1_2.unit_num.adj_value + connect _cast_bundle_to_bits_expr_60.unit_out_reg, renamed_src_reg_1_1_2.unit_out_reg.value + wire _cast_to_bits_expr_60: UInt<6> + connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num) + connect _array_literal_expr_52[1], _cast_to_bits_expr_60 + connect _array_literal_expr_50[1], _array_literal_expr_52[1] + wire _bundle_literal_expr_174: Ty50 + connect _bundle_literal_expr_174.imm_low, _match_arm_value_156.alu_common.common.imm_low + wire _array_literal_expr_53: UInt<8>[1] + connect _array_literal_expr_53[0], _match_arm_value_156.alu_common.common.src[2] + connect _bundle_literal_expr_174.reversed_src, _array_literal_expr_53 + connect _bundle_literal_expr_174.imm_sign, _match_arm_value_156.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_61: Ty51 + connect _cast_bundle_to_bits_expr_61.imm_low, _bundle_literal_expr_174.imm_low + connect _cast_bundle_to_bits_expr_61.reversed_src, _bundle_literal_expr_174.reversed_src[0] + connect _cast_bundle_to_bits_expr_61.imm_sign, asUInt(_bundle_literal_expr_174.imm_sign) + wire _cast_to_bits_expr_61: UInt<34> + connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_61.imm_sign, cat(_cast_bundle_to_bits_expr_61.reversed_src, _cast_bundle_to_bits_expr_61.imm_low)) + wire _cast_bits_to_bundle_expr_7: Ty50 + wire _cast_bits_to_bundle_expr_flattened_7: Ty51 + connect _cast_bits_to_bundle_expr_flattened_7.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 24, 0) + connect _cast_bits_to_bundle_expr_7.imm_low, _cast_bits_to_bundle_expr_flattened_7.imm_low + connect _cast_bits_to_bundle_expr_flattened_7.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 32, 25) + wire _cast_bits_to_array_expr_7: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_7: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_7[0], bits(_cast_bits_to_bundle_expr_flattened_7.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_7[0], _cast_bits_to_array_expr_flattened_7[0] + connect _cast_bits_to_bundle_expr_7.reversed_src, _cast_bits_to_array_expr_7 + connect _cast_bits_to_bundle_expr_flattened_7.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 33, 33) + connect _cast_bits_to_bundle_expr_7.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_7.imm_sign) + connect _array_literal_expr_50[2], tail(_cast_bits_to_bundle_expr_7.reversed_src[0], 2) + connect _bundle_literal_expr_173.src, _array_literal_expr_50 + wire _bundle_literal_expr_175: Ty50 + connect _bundle_literal_expr_175.imm_low, _match_arm_value_156.alu_common.common.imm_low + wire _array_literal_expr_54: UInt<8>[1] + connect _array_literal_expr_54[0], _match_arm_value_156.alu_common.common.src[2] + connect _bundle_literal_expr_175.reversed_src, _array_literal_expr_54 + connect _bundle_literal_expr_175.imm_sign, _match_arm_value_156.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_62: Ty51 + connect _cast_bundle_to_bits_expr_62.imm_low, _bundle_literal_expr_175.imm_low + connect _cast_bundle_to_bits_expr_62.reversed_src, _bundle_literal_expr_175.reversed_src[0] + connect _cast_bundle_to_bits_expr_62.imm_sign, asUInt(_bundle_literal_expr_175.imm_sign) + wire _cast_to_bits_expr_62: UInt<34> + connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_62.imm_sign, cat(_cast_bundle_to_bits_expr_62.reversed_src, _cast_bundle_to_bits_expr_62.imm_low)) + connect _bundle_literal_expr_173.imm_low, bits(asSInt(_cast_to_bits_expr_62), 24, 0) + wire _bundle_literal_expr_176: Ty50 + connect _bundle_literal_expr_176.imm_low, _match_arm_value_156.alu_common.common.imm_low + wire _array_literal_expr_55: UInt<8>[1] + connect _array_literal_expr_55[0], _match_arm_value_156.alu_common.common.src[2] + connect _bundle_literal_expr_176.reversed_src, _array_literal_expr_55 + connect _bundle_literal_expr_176.imm_sign, _match_arm_value_156.alu_common.common.imm_sign + wire _cast_bundle_to_bits_expr_63: Ty51 + connect _cast_bundle_to_bits_expr_63.imm_low, _bundle_literal_expr_176.imm_low + connect _cast_bundle_to_bits_expr_63.reversed_src, _bundle_literal_expr_176.reversed_src[0] + connect _cast_bundle_to_bits_expr_63.imm_sign, asUInt(_bundle_literal_expr_176.imm_sign) + wire _cast_to_bits_expr_63: UInt<34> + connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_63.imm_sign, cat(_cast_bundle_to_bits_expr_63.reversed_src, _cast_bundle_to_bits_expr_63.imm_low)) + connect _bundle_literal_expr_173.imm_sign, shr(asSInt(_cast_to_bits_expr_63), 33) + wire _bundle_literal_expr_177: Ty2 + invalidate _bundle_literal_expr_177 + connect _bundle_literal_expr_173._phantom, _bundle_literal_expr_177 + connect _bundle_literal_expr_172.common, _bundle_literal_expr_173 + connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_156.alu_common.output_integer_mode + connect _bundle_literal_expr_171.alu_common, _bundle_literal_expr_172 + connect _bundle_literal_expr_171.lut, _match_arm_value_156.lut + connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(Logical, _bundle_literal_expr_171) @[instruction.rs 477:1] + connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(AluBranch, mapped_regs_5) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_161): + wire mapped_regs_6: Ty40 @[instruction.rs 504:1] + match _match_arm_value_161: @[instruction.rs 504:1] + ReadL2Reg(_match_arm_value_162): + wire _bundle_literal_expr_178: Ty39 + wire _bundle_literal_expr_179: Ty38 + connect _bundle_literal_expr_179.prefix_pad, _match_arm_value_162.common.prefix_pad + connect _bundle_literal_expr_179.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_56: UInt<6>[3] + connect _array_literal_expr_56[0], pad(UInt<0>(0h0), 6) + connect _array_literal_expr_56[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_180: Ty50 + connect _bundle_literal_expr_180.imm_low, _match_arm_value_162.common.imm_low + wire _array_literal_expr_57: UInt<8>[1] + connect _array_literal_expr_57[0], _match_arm_value_162.common.src[2] + connect _bundle_literal_expr_180.reversed_src, _array_literal_expr_57 + connect _bundle_literal_expr_180.imm_sign, _match_arm_value_162.common.imm_sign + wire _cast_bundle_to_bits_expr_64: Ty51 + connect _cast_bundle_to_bits_expr_64.imm_low, _bundle_literal_expr_180.imm_low + connect _cast_bundle_to_bits_expr_64.reversed_src, _bundle_literal_expr_180.reversed_src[0] + connect _cast_bundle_to_bits_expr_64.imm_sign, asUInt(_bundle_literal_expr_180.imm_sign) + wire _cast_to_bits_expr_64: UInt<34> + connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_64.imm_sign, cat(_cast_bundle_to_bits_expr_64.reversed_src, _cast_bundle_to_bits_expr_64.imm_low)) + wire _cast_bits_to_bundle_expr_8: Ty50 + wire _cast_bits_to_bundle_expr_flattened_8: Ty51 + connect _cast_bits_to_bundle_expr_flattened_8.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 24, 0) + connect _cast_bits_to_bundle_expr_8.imm_low, _cast_bits_to_bundle_expr_flattened_8.imm_low + connect _cast_bits_to_bundle_expr_flattened_8.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 32, 25) + wire _cast_bits_to_array_expr_8: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_8: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_8[0], bits(_cast_bits_to_bundle_expr_flattened_8.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_8[0], _cast_bits_to_array_expr_flattened_8[0] + connect _cast_bits_to_bundle_expr_8.reversed_src, _cast_bits_to_array_expr_8 + connect _cast_bits_to_bundle_expr_flattened_8.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 33, 33) + connect _cast_bits_to_bundle_expr_8.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_8.imm_sign) + connect _array_literal_expr_56[2], tail(_cast_bits_to_bundle_expr_8.reversed_src[0], 2) + connect _bundle_literal_expr_179.src, _array_literal_expr_56 + wire _bundle_literal_expr_181: Ty50 + connect _bundle_literal_expr_181.imm_low, _match_arm_value_162.common.imm_low + wire _array_literal_expr_58: UInt<8>[1] + connect _array_literal_expr_58[0], _match_arm_value_162.common.src[2] + connect _bundle_literal_expr_181.reversed_src, _array_literal_expr_58 + connect _bundle_literal_expr_181.imm_sign, _match_arm_value_162.common.imm_sign + wire _cast_bundle_to_bits_expr_65: Ty51 + connect _cast_bundle_to_bits_expr_65.imm_low, _bundle_literal_expr_181.imm_low + connect _cast_bundle_to_bits_expr_65.reversed_src, _bundle_literal_expr_181.reversed_src[0] + connect _cast_bundle_to_bits_expr_65.imm_sign, asUInt(_bundle_literal_expr_181.imm_sign) + wire _cast_to_bits_expr_65: UInt<34> + connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_65.imm_sign, cat(_cast_bundle_to_bits_expr_65.reversed_src, _cast_bundle_to_bits_expr_65.imm_low)) + connect _bundle_literal_expr_179.imm_low, bits(asSInt(_cast_to_bits_expr_65), 24, 0) + wire _bundle_literal_expr_182: Ty50 + connect _bundle_literal_expr_182.imm_low, _match_arm_value_162.common.imm_low + wire _array_literal_expr_59: UInt<8>[1] + connect _array_literal_expr_59[0], _match_arm_value_162.common.src[2] + connect _bundle_literal_expr_182.reversed_src, _array_literal_expr_59 + connect _bundle_literal_expr_182.imm_sign, _match_arm_value_162.common.imm_sign + wire _cast_bundle_to_bits_expr_66: Ty51 + connect _cast_bundle_to_bits_expr_66.imm_low, _bundle_literal_expr_182.imm_low + connect _cast_bundle_to_bits_expr_66.reversed_src, _bundle_literal_expr_182.reversed_src[0] + connect _cast_bundle_to_bits_expr_66.imm_sign, asUInt(_bundle_literal_expr_182.imm_sign) + wire _cast_to_bits_expr_66: UInt<34> + connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_66.imm_sign, cat(_cast_bundle_to_bits_expr_66.reversed_src, _cast_bundle_to_bits_expr_66.imm_low)) + connect _bundle_literal_expr_179.imm_sign, shr(asSInt(_cast_to_bits_expr_66), 33) + wire _bundle_literal_expr_183: Ty2 + invalidate _bundle_literal_expr_183 + connect _bundle_literal_expr_179._phantom, _bundle_literal_expr_183 + connect _bundle_literal_expr_178.common, _bundle_literal_expr_179 + connect mapped_regs_6, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 504:1] + WriteL2Reg(_match_arm_value_163): + wire renamed_src_reg_1_0_3: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_184: Ty1 + connect _bundle_literal_expr_184.value, _match_arm_value_163.common.src[0] + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_185: Ty1 + connect _bundle_literal_expr_185.value, _match_arm_value_163.common.src[0] + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_185 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_186: Ty25 + wire _bundle_literal_expr_187: Ty23 + connect _bundle_literal_expr_187.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_186.unit_num, _bundle_literal_expr_187 + wire _bundle_literal_expr_188: Ty24 + connect _bundle_literal_expr_188.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_186.unit_out_reg, _bundle_literal_expr_188 + connect renamed_src_reg_1_0_3, _bundle_literal_expr_186 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_164): + connect renamed_src_reg_1_0_3, _match_arm_value_164 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_165): + connect renamed_src_reg_1_0_3, _match_arm_value_165 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_189: Ty39 + wire _bundle_literal_expr_190: Ty38 + connect _bundle_literal_expr_190.prefix_pad, _match_arm_value_163.common.prefix_pad + connect _bundle_literal_expr_190.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_60: UInt<6>[3] + wire _array_literal_expr_61: UInt<6>[1] + wire _cast_bundle_to_bits_expr_67: Ty47 + connect _cast_bundle_to_bits_expr_67.unit_num, renamed_src_reg_1_0_3.unit_num.adj_value + connect _cast_bundle_to_bits_expr_67.unit_out_reg, renamed_src_reg_1_0_3.unit_out_reg.value + wire _cast_to_bits_expr_67: UInt<6> + connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num) + connect _array_literal_expr_61[0], _cast_to_bits_expr_67 + connect _array_literal_expr_60[0], _array_literal_expr_61[0] + connect _array_literal_expr_60[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_191: Ty50 + connect _bundle_literal_expr_191.imm_low, _match_arm_value_163.common.imm_low + wire _array_literal_expr_62: UInt<8>[1] + connect _array_literal_expr_62[0], _match_arm_value_163.common.src[2] + connect _bundle_literal_expr_191.reversed_src, _array_literal_expr_62 + connect _bundle_literal_expr_191.imm_sign, _match_arm_value_163.common.imm_sign + wire _cast_bundle_to_bits_expr_68: Ty51 + connect _cast_bundle_to_bits_expr_68.imm_low, _bundle_literal_expr_191.imm_low + connect _cast_bundle_to_bits_expr_68.reversed_src, _bundle_literal_expr_191.reversed_src[0] + connect _cast_bundle_to_bits_expr_68.imm_sign, asUInt(_bundle_literal_expr_191.imm_sign) + wire _cast_to_bits_expr_68: UInt<34> + connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_68.imm_sign, cat(_cast_bundle_to_bits_expr_68.reversed_src, _cast_bundle_to_bits_expr_68.imm_low)) + wire _cast_bits_to_bundle_expr_9: Ty50 + wire _cast_bits_to_bundle_expr_flattened_9: Ty51 + connect _cast_bits_to_bundle_expr_flattened_9.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 24, 0) + connect _cast_bits_to_bundle_expr_9.imm_low, _cast_bits_to_bundle_expr_flattened_9.imm_low + connect _cast_bits_to_bundle_expr_flattened_9.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 32, 25) + wire _cast_bits_to_array_expr_9: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_9: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_9[0], bits(_cast_bits_to_bundle_expr_flattened_9.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_9[0], _cast_bits_to_array_expr_flattened_9[0] + connect _cast_bits_to_bundle_expr_9.reversed_src, _cast_bits_to_array_expr_9 + connect _cast_bits_to_bundle_expr_flattened_9.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 33, 33) + connect _cast_bits_to_bundle_expr_9.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_9.imm_sign) + connect _array_literal_expr_60[2], tail(_cast_bits_to_bundle_expr_9.reversed_src[0], 2) + connect _bundle_literal_expr_190.src, _array_literal_expr_60 + wire _bundle_literal_expr_192: Ty50 + connect _bundle_literal_expr_192.imm_low, _match_arm_value_163.common.imm_low + wire _array_literal_expr_63: UInt<8>[1] + connect _array_literal_expr_63[0], _match_arm_value_163.common.src[2] + connect _bundle_literal_expr_192.reversed_src, _array_literal_expr_63 + connect _bundle_literal_expr_192.imm_sign, _match_arm_value_163.common.imm_sign + wire _cast_bundle_to_bits_expr_69: Ty51 + connect _cast_bundle_to_bits_expr_69.imm_low, _bundle_literal_expr_192.imm_low + connect _cast_bundle_to_bits_expr_69.reversed_src, _bundle_literal_expr_192.reversed_src[0] + connect _cast_bundle_to_bits_expr_69.imm_sign, asUInt(_bundle_literal_expr_192.imm_sign) + wire _cast_to_bits_expr_69: UInt<34> + connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_69.imm_sign, cat(_cast_bundle_to_bits_expr_69.reversed_src, _cast_bundle_to_bits_expr_69.imm_low)) + connect _bundle_literal_expr_190.imm_low, bits(asSInt(_cast_to_bits_expr_69), 24, 0) + wire _bundle_literal_expr_193: Ty50 + connect _bundle_literal_expr_193.imm_low, _match_arm_value_163.common.imm_low + wire _array_literal_expr_64: UInt<8>[1] + connect _array_literal_expr_64[0], _match_arm_value_163.common.src[2] + connect _bundle_literal_expr_193.reversed_src, _array_literal_expr_64 + connect _bundle_literal_expr_193.imm_sign, _match_arm_value_163.common.imm_sign + wire _cast_bundle_to_bits_expr_70: Ty51 + connect _cast_bundle_to_bits_expr_70.imm_low, _bundle_literal_expr_193.imm_low + connect _cast_bundle_to_bits_expr_70.reversed_src, _bundle_literal_expr_193.reversed_src[0] + connect _cast_bundle_to_bits_expr_70.imm_sign, asUInt(_bundle_literal_expr_193.imm_sign) + wire _cast_to_bits_expr_70: UInt<34> + connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_70.imm_sign, cat(_cast_bundle_to_bits_expr_70.reversed_src, _cast_bundle_to_bits_expr_70.imm_low)) + connect _bundle_literal_expr_190.imm_sign, shr(asSInt(_cast_to_bits_expr_70), 33) + wire _bundle_literal_expr_194: Ty2 + invalidate _bundle_literal_expr_194 + connect _bundle_literal_expr_190._phantom, _bundle_literal_expr_194 + connect _bundle_literal_expr_189.common, _bundle_literal_expr_190 + connect mapped_regs_6, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(WriteL2Reg, _bundle_literal_expr_189) @[instruction.rs 504:1] + connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(L2RegisterFile, mapped_regs_6) @[unit.rs 127:1] + LoadStore(_match_arm_value_166): + wire mapped_regs_7: Ty41 @[instruction.rs 539:1] + match _match_arm_value_166: @[instruction.rs 539:1] + Load(_match_arm_value_167): + wire _bundle_literal_expr_195: Ty38 + connect _bundle_literal_expr_195.prefix_pad, _match_arm_value_167.prefix_pad + connect _bundle_literal_expr_195.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_65: UInt<6>[3] + connect _array_literal_expr_65[0], pad(UInt<0>(0h0), 6) + connect _array_literal_expr_65[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_196: Ty50 + connect _bundle_literal_expr_196.imm_low, _match_arm_value_167.imm_low + wire _array_literal_expr_66: UInt<8>[1] + connect _array_literal_expr_66[0], _match_arm_value_167.src[2] + connect _bundle_literal_expr_196.reversed_src, _array_literal_expr_66 + connect _bundle_literal_expr_196.imm_sign, _match_arm_value_167.imm_sign + wire _cast_bundle_to_bits_expr_71: Ty51 + connect _cast_bundle_to_bits_expr_71.imm_low, _bundle_literal_expr_196.imm_low + connect _cast_bundle_to_bits_expr_71.reversed_src, _bundle_literal_expr_196.reversed_src[0] + connect _cast_bundle_to_bits_expr_71.imm_sign, asUInt(_bundle_literal_expr_196.imm_sign) + wire _cast_to_bits_expr_71: UInt<34> + connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_71.imm_sign, cat(_cast_bundle_to_bits_expr_71.reversed_src, _cast_bundle_to_bits_expr_71.imm_low)) + wire _cast_bits_to_bundle_expr_10: Ty50 + wire _cast_bits_to_bundle_expr_flattened_10: Ty51 + connect _cast_bits_to_bundle_expr_flattened_10.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 24, 0) + connect _cast_bits_to_bundle_expr_10.imm_low, _cast_bits_to_bundle_expr_flattened_10.imm_low + connect _cast_bits_to_bundle_expr_flattened_10.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 32, 25) + wire _cast_bits_to_array_expr_10: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_10: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_10[0], bits(_cast_bits_to_bundle_expr_flattened_10.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_10[0], _cast_bits_to_array_expr_flattened_10[0] + connect _cast_bits_to_bundle_expr_10.reversed_src, _cast_bits_to_array_expr_10 + connect _cast_bits_to_bundle_expr_flattened_10.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 33, 33) + connect _cast_bits_to_bundle_expr_10.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_10.imm_sign) + connect _array_literal_expr_65[2], tail(_cast_bits_to_bundle_expr_10.reversed_src[0], 2) + connect _bundle_literal_expr_195.src, _array_literal_expr_65 + wire _bundle_literal_expr_197: Ty50 + connect _bundle_literal_expr_197.imm_low, _match_arm_value_167.imm_low + wire _array_literal_expr_67: UInt<8>[1] + connect _array_literal_expr_67[0], _match_arm_value_167.src[2] + connect _bundle_literal_expr_197.reversed_src, _array_literal_expr_67 + connect _bundle_literal_expr_197.imm_sign, _match_arm_value_167.imm_sign + wire _cast_bundle_to_bits_expr_72: Ty51 + connect _cast_bundle_to_bits_expr_72.imm_low, _bundle_literal_expr_197.imm_low + connect _cast_bundle_to_bits_expr_72.reversed_src, _bundle_literal_expr_197.reversed_src[0] + connect _cast_bundle_to_bits_expr_72.imm_sign, asUInt(_bundle_literal_expr_197.imm_sign) + wire _cast_to_bits_expr_72: UInt<34> + connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_72.imm_sign, cat(_cast_bundle_to_bits_expr_72.reversed_src, _cast_bundle_to_bits_expr_72.imm_low)) + connect _bundle_literal_expr_195.imm_low, bits(asSInt(_cast_to_bits_expr_72), 24, 0) + wire _bundle_literal_expr_198: Ty50 + connect _bundle_literal_expr_198.imm_low, _match_arm_value_167.imm_low + wire _array_literal_expr_68: UInt<8>[1] + connect _array_literal_expr_68[0], _match_arm_value_167.src[2] + connect _bundle_literal_expr_198.reversed_src, _array_literal_expr_68 + connect _bundle_literal_expr_198.imm_sign, _match_arm_value_167.imm_sign + wire _cast_bundle_to_bits_expr_73: Ty51 + connect _cast_bundle_to_bits_expr_73.imm_low, _bundle_literal_expr_198.imm_low + connect _cast_bundle_to_bits_expr_73.reversed_src, _bundle_literal_expr_198.reversed_src[0] + connect _cast_bundle_to_bits_expr_73.imm_sign, asUInt(_bundle_literal_expr_198.imm_sign) + wire _cast_to_bits_expr_73: UInt<34> + connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_73.imm_sign, cat(_cast_bundle_to_bits_expr_73.reversed_src, _cast_bundle_to_bits_expr_73.imm_low)) + connect _bundle_literal_expr_195.imm_sign, shr(asSInt(_cast_to_bits_expr_73), 33) + wire _bundle_literal_expr_199: Ty2 + invalidate _bundle_literal_expr_199 + connect _bundle_literal_expr_195._phantom, _bundle_literal_expr_199 + connect mapped_regs_7, {|Load: Ty38, Store: Ty38|}(Load, _bundle_literal_expr_195) @[instruction.rs 539:1] + Store(_match_arm_value_168): + wire renamed_src_reg_1_0_4: Ty25 @[reg_alloc.rs 178:33] + wire _bundle_literal_expr_200: Ty1 + connect _bundle_literal_expr_200.value, _match_arm_value_168.src[0] + connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_200 @[reg_alloc.rs 181:29] + wire _bundle_literal_expr_201: Ty1 + connect _bundle_literal_expr_201.value, _match_arm_value_168.src[0] + connect rename_table_special_1_src_0.addr, _bundle_literal_expr_201 @[reg_alloc.rs 182:29] + match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29] + HdlNone: + match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36] + HdlNone: + wire _bundle_literal_expr_202: Ty25 + wire _bundle_literal_expr_203: Ty23 + connect _bundle_literal_expr_203.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_202.unit_num, _bundle_literal_expr_203 + wire _bundle_literal_expr_204: Ty24 + connect _bundle_literal_expr_204.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_202.unit_out_reg, _bundle_literal_expr_204 + connect renamed_src_reg_1_0_4, _bundle_literal_expr_202 @[reg_alloc.rs 191:33] + HdlSome(_match_arm_value_169): + connect renamed_src_reg_1_0_4, _match_arm_value_169 @[reg_alloc.rs 189:33] + HdlSome(_match_arm_value_170): + connect renamed_src_reg_1_0_4, _match_arm_value_170 @[reg_alloc.rs 185:33] + wire _bundle_literal_expr_205: Ty38 + connect _bundle_literal_expr_205.prefix_pad, _match_arm_value_168.prefix_pad + connect _bundle_literal_expr_205.dest, _match_arm_value_132.unit_out_reg + wire _array_literal_expr_69: UInt<6>[3] + wire _array_literal_expr_70: UInt<6>[1] + wire _cast_bundle_to_bits_expr_74: Ty47 + connect _cast_bundle_to_bits_expr_74.unit_num, renamed_src_reg_1_0_4.unit_num.adj_value + connect _cast_bundle_to_bits_expr_74.unit_out_reg, renamed_src_reg_1_0_4.unit_out_reg.value + wire _cast_to_bits_expr_74: UInt<6> + connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num) + connect _array_literal_expr_70[0], _cast_to_bits_expr_74 + connect _array_literal_expr_69[0], _array_literal_expr_70[0] + connect _array_literal_expr_69[1], pad(UInt<0>(0h0), 6) + wire _bundle_literal_expr_206: Ty50 + connect _bundle_literal_expr_206.imm_low, _match_arm_value_168.imm_low + wire _array_literal_expr_71: UInt<8>[1] + connect _array_literal_expr_71[0], _match_arm_value_168.src[2] + connect _bundle_literal_expr_206.reversed_src, _array_literal_expr_71 + connect _bundle_literal_expr_206.imm_sign, _match_arm_value_168.imm_sign + wire _cast_bundle_to_bits_expr_75: Ty51 + connect _cast_bundle_to_bits_expr_75.imm_low, _bundle_literal_expr_206.imm_low + connect _cast_bundle_to_bits_expr_75.reversed_src, _bundle_literal_expr_206.reversed_src[0] + connect _cast_bundle_to_bits_expr_75.imm_sign, asUInt(_bundle_literal_expr_206.imm_sign) + wire _cast_to_bits_expr_75: UInt<34> + connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_75.imm_sign, cat(_cast_bundle_to_bits_expr_75.reversed_src, _cast_bundle_to_bits_expr_75.imm_low)) + wire _cast_bits_to_bundle_expr_11: Ty50 + wire _cast_bits_to_bundle_expr_flattened_11: Ty51 + connect _cast_bits_to_bundle_expr_flattened_11.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 24, 0) + connect _cast_bits_to_bundle_expr_11.imm_low, _cast_bits_to_bundle_expr_flattened_11.imm_low + connect _cast_bits_to_bundle_expr_flattened_11.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 32, 25) + wire _cast_bits_to_array_expr_11: UInt<8>[1] + wire _cast_bits_to_array_expr_flattened_11: UInt<8>[1] + connect _cast_bits_to_array_expr_flattened_11[0], bits(_cast_bits_to_bundle_expr_flattened_11.reversed_src, 7, 0) + connect _cast_bits_to_array_expr_11[0], _cast_bits_to_array_expr_flattened_11[0] + connect _cast_bits_to_bundle_expr_11.reversed_src, _cast_bits_to_array_expr_11 + connect _cast_bits_to_bundle_expr_flattened_11.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 33, 33) + connect _cast_bits_to_bundle_expr_11.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_11.imm_sign) + connect _array_literal_expr_69[2], tail(_cast_bits_to_bundle_expr_11.reversed_src[0], 2) + connect _bundle_literal_expr_205.src, _array_literal_expr_69 + wire _bundle_literal_expr_207: Ty50 + connect _bundle_literal_expr_207.imm_low, _match_arm_value_168.imm_low + wire _array_literal_expr_72: UInt<8>[1] + connect _array_literal_expr_72[0], _match_arm_value_168.src[2] + connect _bundle_literal_expr_207.reversed_src, _array_literal_expr_72 + connect _bundle_literal_expr_207.imm_sign, _match_arm_value_168.imm_sign + wire _cast_bundle_to_bits_expr_76: Ty51 + connect _cast_bundle_to_bits_expr_76.imm_low, _bundle_literal_expr_207.imm_low + connect _cast_bundle_to_bits_expr_76.reversed_src, _bundle_literal_expr_207.reversed_src[0] + connect _cast_bundle_to_bits_expr_76.imm_sign, asUInt(_bundle_literal_expr_207.imm_sign) + wire _cast_to_bits_expr_76: UInt<34> + connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_76.imm_sign, cat(_cast_bundle_to_bits_expr_76.reversed_src, _cast_bundle_to_bits_expr_76.imm_low)) + connect _bundle_literal_expr_205.imm_low, bits(asSInt(_cast_to_bits_expr_76), 24, 0) + wire _bundle_literal_expr_208: Ty50 + connect _bundle_literal_expr_208.imm_low, _match_arm_value_168.imm_low + wire _array_literal_expr_73: UInt<8>[1] + connect _array_literal_expr_73[0], _match_arm_value_168.src[2] + connect _bundle_literal_expr_208.reversed_src, _array_literal_expr_73 + connect _bundle_literal_expr_208.imm_sign, _match_arm_value_168.imm_sign + wire _cast_bundle_to_bits_expr_77: Ty51 + connect _cast_bundle_to_bits_expr_77.imm_low, _bundle_literal_expr_208.imm_low + connect _cast_bundle_to_bits_expr_77.reversed_src, _bundle_literal_expr_208.reversed_src[0] + connect _cast_bundle_to_bits_expr_77.imm_sign, asUInt(_bundle_literal_expr_208.imm_sign) + wire _cast_to_bits_expr_77: UInt<34> + connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_77.imm_sign, cat(_cast_bundle_to_bits_expr_77.reversed_src, _cast_bundle_to_bits_expr_77.imm_low)) + connect _bundle_literal_expr_205.imm_sign, shr(asSInt(_cast_to_bits_expr_77), 33) + wire _bundle_literal_expr_209: Ty2 + invalidate _bundle_literal_expr_209 + connect _bundle_literal_expr_205._phantom, _bundle_literal_expr_209 + connect mapped_regs_7, {|Load: Ty38, Store: Ty38|}(Store, _bundle_literal_expr_205) @[instruction.rs 539:1] + connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(LoadStore, mapped_regs_7) @[unit.rs 127:1] + connect renamed_mops[1], {|HdlNone, HdlSome: Ty42|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 167:17] + wire selected_unit_index_leaf_1_0: Ty32 @[reg_alloc.rs 209:25] + connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21] + wire unit_index_1_0: UInt<2> @[reg_alloc.rs 218:25] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<64> + connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 221:21] + when available_units[1][0]: @[reg_alloc.rs 223:21] + connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 224:25] + wire selected_unit_index_leaf_1_1: Ty32 @[reg_alloc.rs 209:25] + connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21] + wire unit_index_1_1: UInt<2> @[reg_alloc.rs 218:25] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<64> + connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 221:21] + when available_units[1][1]: @[reg_alloc.rs 223:21] + connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 224:25] + wire selected_unit_index_node_1_0: Ty32 @[reg_alloc.rs 231:25] + connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 235:21] + match selected_unit_index_leaf_1_0: @[reg_alloc.rs 237:21] + HdlNone: + connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 238:25] + HdlSome(_match_arm_value_171): + skip + connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 201:9] + match selected_unit_indexes[0]: @[reg_alloc.rs 251:13] + HdlNone: + skip + HdlSome(_match_arm_value_172): + connect available_units[1][_match_arm_value_172], UInt<1>(0h0) @[reg_alloc.rs 252:17] + wire _array_literal_expr_74: Ty44[2] + connect _array_literal_expr_74[0], {|HdlNone, HdlSome: Ty25|}(HdlNone) + connect _array_literal_expr_74[1], {|HdlNone, HdlSome: Ty25|}(HdlNone) + connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 259:5] + inst unit_0 of alu_branch @[reg_alloc.rs 271:13] + connect unit_0.cd, cd @[reg_alloc.rs 273:9] + inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 286:13] + connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 288:9] + wire _uninit_expr: Ty55 invalidate _uninit_expr - connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 154:9] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 158:9] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 161:13] + connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 290:9] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 294:9] + connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 295:9] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13] HdlNone: - connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 163:17] - HdlSome(_match_arm_value_9): + connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 300:17] + HdlSome(_match_arm_value_173): skip - match selected_unit_nums[0]: @[reg_alloc.rs 166:13] + when not(unit_0.`input`.ready): @[reg_alloc.rs 303:13] + connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 305:17] + match selected_unit_indexes[0]: @[reg_alloc.rs 308:13] HdlNone: skip - HdlSome(_match_arm_value_10): - when eq(_match_arm_value_10.value, UInt<64>(0h0)): @[reg_alloc.rs 168:17] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 169:21] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 161:13] + HdlSome(_match_arm_value_174): + when eq(_match_arm_value_174, UInt<64>(0h0)): @[reg_alloc.rs 310:17] + wire and_then_out: Ty52 @[reg_alloc.rs 314:25] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21] + match renamed_mops[0]: @[reg_alloc.rs 314:25] + HdlNone: + connect and_then_out, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25] + HdlSome(_match_arm_value_175): + wire alu_branch_mop: Ty52 @[unit.rs 127:1] + connect alu_branch_mop, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1] + match _match_arm_value_175: @[unit.rs 127:1] + AluBranch(_match_arm_value_176): + connect alu_branch_mop, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_176) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_177): + skip + LoadStore(_match_arm_value_178): + skip + connect and_then_out, alu_branch_mop @[reg_alloc.rs 314:25] + match and_then_out: @[reg_alloc.rs 313:21] + HdlNone: + wire _uninit_expr_1: Ty37 + invalidate _uninit_expr_1 + connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_1) @[reg_alloc.rs 318:25] + HdlSome(_match_arm_value_179): + connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_179) @[reg_alloc.rs 316:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21] + HdlNone: + skip + HdlSome(_match_arm_value_180): + wire _bundle_literal_expr_210: Ty25 + wire _bundle_literal_expr_211: Ty23 + connect _bundle_literal_expr_211.adj_value, tail(UInt<64>(0h1), 62) + connect _bundle_literal_expr_210.unit_num, _bundle_literal_expr_211 + wire _bundle_literal_expr_212: Ty24 + connect _bundle_literal_expr_212.value, _match_arm_value_180 + connect _bundle_literal_expr_210.unit_out_reg, _bundle_literal_expr_212 + connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_210) @[reg_alloc.rs 331:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13] HdlNone: - connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 163:17] - HdlSome(_match_arm_value_11): + connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 300:17] + HdlSome(_match_arm_value_181): skip - match selected_unit_nums[1]: @[reg_alloc.rs 166:13] + when not(unit_0.`input`.ready): @[reg_alloc.rs 303:13] + connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 305:17] + match selected_unit_indexes[1]: @[reg_alloc.rs 308:13] HdlNone: skip - HdlSome(_match_arm_value_12): - when eq(_match_arm_value_12.value, UInt<64>(0h0)): @[reg_alloc.rs 168:17] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 169:21] + HdlSome(_match_arm_value_182): + when eq(_match_arm_value_182, UInt<64>(0h0)): @[reg_alloc.rs 310:17] + wire and_then_out_1: Ty52 @[reg_alloc.rs 314:25] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21] + match renamed_mops[1]: @[reg_alloc.rs 314:25] + HdlNone: + connect and_then_out_1, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25] + HdlSome(_match_arm_value_183): + wire alu_branch_mop_1: Ty52 @[unit.rs 127:1] + connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1] + match _match_arm_value_183: @[unit.rs 127:1] + AluBranch(_match_arm_value_184): + connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_184) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_185): + skip + LoadStore(_match_arm_value_186): + skip + connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 314:25] + match and_then_out_1: @[reg_alloc.rs 313:21] + HdlNone: + wire _uninit_expr_2: Ty37 + invalidate _uninit_expr_2 + connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_2) @[reg_alloc.rs 318:25] + HdlSome(_match_arm_value_187): + connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_187) @[reg_alloc.rs 316:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21] + HdlNone: + skip + HdlSome(_match_arm_value_188): + wire _bundle_literal_expr_213: Ty25 + wire _bundle_literal_expr_214: Ty23 + connect _bundle_literal_expr_214.adj_value, tail(UInt<64>(0h1), 62) + connect _bundle_literal_expr_213.unit_num, _bundle_literal_expr_214 + wire _bundle_literal_expr_215: Ty24 + connect _bundle_literal_expr_215.value, _match_arm_value_188 + connect _bundle_literal_expr_213.unit_out_reg, _bundle_literal_expr_215 + connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_213) @[reg_alloc.rs 331:25] + inst unit_1 of alu_branch_1 @[reg_alloc.rs 271:13] + connect unit_1.cd, cd @[reg_alloc.rs 273:9] + inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 286:13] + connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 288:9] + wire _uninit_expr_3: Ty55 + invalidate _uninit_expr_3 + connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_3 @[reg_alloc.rs 290:9] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 294:9] + connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 295:9] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13] + HdlNone: + connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 300:17] + HdlSome(_match_arm_value_189): + skip + when not(unit_1.`input`.ready): @[reg_alloc.rs 303:13] + connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 305:17] + match selected_unit_indexes[0]: @[reg_alloc.rs 308:13] + HdlNone: + skip + HdlSome(_match_arm_value_190): + when eq(_match_arm_value_190, UInt<64>(0h1)): @[reg_alloc.rs 310:17] + wire and_then_out_2: Ty52 @[reg_alloc.rs 314:25] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21] + match renamed_mops[0]: @[reg_alloc.rs 314:25] + HdlNone: + connect and_then_out_2, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25] + HdlSome(_match_arm_value_191): + wire alu_branch_mop_2: Ty52 @[unit.rs 127:1] + connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1] + match _match_arm_value_191: @[unit.rs 127:1] + AluBranch(_match_arm_value_192): + connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_192) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_193): + skip + LoadStore(_match_arm_value_194): + skip + connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 314:25] + match and_then_out_2: @[reg_alloc.rs 313:21] + HdlNone: + wire _uninit_expr_4: Ty37 + invalidate _uninit_expr_4 + connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_4) @[reg_alloc.rs 318:25] + HdlSome(_match_arm_value_195): + connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_195) @[reg_alloc.rs 316:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21] + HdlNone: + skip + HdlSome(_match_arm_value_196): + wire _bundle_literal_expr_216: Ty25 + wire _bundle_literal_expr_217: Ty23 + connect _bundle_literal_expr_217.adj_value, tail(UInt<64>(0h2), 62) + connect _bundle_literal_expr_216.unit_num, _bundle_literal_expr_217 + wire _bundle_literal_expr_218: Ty24 + connect _bundle_literal_expr_218.value, _match_arm_value_196 + connect _bundle_literal_expr_216.unit_out_reg, _bundle_literal_expr_218 + connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_216) @[reg_alloc.rs 331:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13] + HdlNone: + connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 300:17] + HdlSome(_match_arm_value_197): + skip + when not(unit_1.`input`.ready): @[reg_alloc.rs 303:13] + connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 305:17] + match selected_unit_indexes[1]: @[reg_alloc.rs 308:13] + HdlNone: + skip + HdlSome(_match_arm_value_198): + when eq(_match_arm_value_198, UInt<64>(0h1)): @[reg_alloc.rs 310:17] + wire and_then_out_3: Ty52 @[reg_alloc.rs 314:25] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21] + match renamed_mops[1]: @[reg_alloc.rs 314:25] + HdlNone: + connect and_then_out_3, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25] + HdlSome(_match_arm_value_199): + wire alu_branch_mop_3: Ty52 @[unit.rs 127:1] + connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1] + match _match_arm_value_199: @[unit.rs 127:1] + AluBranch(_match_arm_value_200): + connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_200) @[unit.rs 127:1] + L2RegisterFile(_match_arm_value_201): + skip + LoadStore(_match_arm_value_202): + skip + connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 314:25] + match and_then_out_3: @[reg_alloc.rs 313:21] + HdlNone: + wire _uninit_expr_5: Ty37 + invalidate _uninit_expr_5 + connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_5) @[reg_alloc.rs 318:25] + HdlSome(_match_arm_value_203): + connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_203) @[reg_alloc.rs 316:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21] + HdlNone: + skip + HdlSome(_match_arm_value_204): + wire _bundle_literal_expr_219: Ty25 + wire _bundle_literal_expr_220: Ty23 + connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h2), 62) + connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220 + wire _bundle_literal_expr_221: Ty24 + connect _bundle_literal_expr_221.value, _match_arm_value_204 + connect _bundle_literal_expr_219.unit_out_reg, _bundle_literal_expr_221 + connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_219) @[reg_alloc.rs 331:25] module alu_branch: @[alu_branch.rs 15:1] input cd: Ty0 @[alu_branch.rs 18:29] + input `input`: Ty53 @[alu_branch.rs 21:11] + connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5] module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1] input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] - input free_in: Ty25[1] @[unit_free_regs_tracker.rs 17:11] - output alloc_out: Ty25[1] @[unit_free_regs_tracker.rs 20:11] + input free_in: Ty56[1] @[unit_free_regs_tracker.rs 17:11] + output alloc_out: Ty56[1] @[unit_free_regs_tracker.rs 20:11] wire _array_literal_expr: UInt<1>[16] connect _array_literal_expr[0], UInt<1>(0h0) connect _array_literal_expr[1], UInt<1>(0h0) @@ -273,7 +2942,7 @@ circuit reg_alloc: connect _array_literal_expr[15], UInt<1>(0h0) regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] - wire firing_data: Ty24 @[ready_valid.rs 30:27] + wire firing_data: Ty55 @[ready_valid.rs 30:27] connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when free_in[0].ready: @[ready_valid.rs 33:9] connect firing_data, free_in[0].data @[ready_valid.rs 34:13] @@ -584,7 +3253,358 @@ circuit reg_alloc: ; lhs: UInt<4> ; rhs: UInt<65> connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] - wire firing_data_1: Ty24 @[ready_valid.rs 30:27] + wire firing_data_1: Ty55 @[ready_valid.rs 30:27] + connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] + when alloc_out[0].ready: @[ready_valid.rs 33:9] + connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] + match firing_data_1: @[unit_free_regs_tracker.rs 102:9] + HdlNone: + skip + HdlSome(_match_arm_value_1): + connect allocated_reg[_match_arm_value_1], UInt<1>(0h1) @[unit_free_regs_tracker.rs 103:13] + when or(reduced_count_overflowed_0_16, gt(reduced_count_0_16, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 106:9] + connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] + else: + connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] + module alu_branch_1: @[alu_branch.rs 15:1] + input cd: Ty0 @[alu_branch.rs 18:29] + input `input`: Ty53 @[alu_branch.rs 21:11] + connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5] + module unit_free_regs_tracker_1: @[unit_free_regs_tracker.rs 7:1] + input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] + input free_in: Ty56[1] @[unit_free_regs_tracker.rs 17:11] + output alloc_out: Ty56[1] @[unit_free_regs_tracker.rs 20:11] + wire _array_literal_expr: UInt<1>[16] + connect _array_literal_expr[0], UInt<1>(0h0) + connect _array_literal_expr[1], UInt<1>(0h0) + connect _array_literal_expr[2], UInt<1>(0h0) + connect _array_literal_expr[3], UInt<1>(0h0) + connect _array_literal_expr[4], UInt<1>(0h0) + connect _array_literal_expr[5], UInt<1>(0h0) + connect _array_literal_expr[6], UInt<1>(0h0) + connect _array_literal_expr[7], UInt<1>(0h0) + connect _array_literal_expr[8], UInt<1>(0h0) + connect _array_literal_expr[9], UInt<1>(0h0) + connect _array_literal_expr[10], UInt<1>(0h0) + connect _array_literal_expr[11], UInt<1>(0h0) + connect _array_literal_expr[12], UInt<1>(0h0) + connect _array_literal_expr[13], UInt<1>(0h0) + connect _array_literal_expr[14], UInt<1>(0h0) + connect _array_literal_expr[15], UInt<1>(0h0) + regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] + connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] + wire firing_data: Ty55 @[ready_valid.rs 30:27] + connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] + when free_in[0].ready: @[ready_valid.rs 33:9] + connect firing_data, free_in[0].data @[ready_valid.rs 34:13] + match firing_data: @[unit_free_regs_tracker.rs 31:9] + HdlNone: + skip + HdlSome(_match_arm_value): + connect allocated_reg[_match_arm_value], UInt<1>(0h0) @[unit_free_regs_tracker.rs 32:13] + wire reduced_count_0_2: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_2, add(not(allocated_reg[0]), not(allocated_reg[1])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_2: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_2, or(or(neq(add(not(allocated_reg[0]), not(allocated_reg[1])), reduced_count_0_2), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_2: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[0]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_1: UInt<0>[1] + connect _array_literal_expr_1[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_0_2[0], _array_literal_expr_1[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_2: UInt<0>[1] + connect _array_literal_expr_2[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_2[0], add(_array_literal_expr_2[sub(UInt<64>(0h0), not(allocated_reg[0]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_2_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_2_4, add(not(allocated_reg[2]), not(allocated_reg[3])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_2_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_2_4, or(or(neq(add(not(allocated_reg[2]), not(allocated_reg[3])), reduced_count_2_4), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_2_4: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[2]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_3: UInt<0>[1] + connect _array_literal_expr_3[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_2_4[0], _array_literal_expr_3[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_4: UInt<0>[1] + connect _array_literal_expr_4[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_2_4[0], add(_array_literal_expr_4[sub(UInt<64>(0h0), not(allocated_reg[2]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_4, add(reduced_count_0_2, reduced_count_2_4) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_4, or(or(neq(add(reduced_count_0_2, reduced_count_2_4), reduced_count_0_4), reduced_count_overflowed_0_2), reduced_count_overflowed_2_4) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_4: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_2, gt(reduced_count_0_2, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_0_4[0], reduced_alloc_nums_0_2[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_4[0], add(reduced_alloc_nums_2_4[sub(UInt<64>(0h0), reduced_count_0_2)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_4_6: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_4_6, add(not(allocated_reg[4]), not(allocated_reg[5])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_4_6: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_4_6, or(or(neq(add(not(allocated_reg[4]), not(allocated_reg[5])), reduced_count_4_6), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_4_6: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[4]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_5: UInt<0>[1] + connect _array_literal_expr_5[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_4_6[0], _array_literal_expr_5[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_6: UInt<0>[1] + connect _array_literal_expr_6[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_4_6[0], add(_array_literal_expr_6[sub(UInt<64>(0h0), not(allocated_reg[4]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_6_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_6_8, add(not(allocated_reg[6]), not(allocated_reg[7])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_6_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_6_8, or(or(neq(add(not(allocated_reg[6]), not(allocated_reg[7])), reduced_count_6_8), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_6_8: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[6]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_7: UInt<0>[1] + connect _array_literal_expr_7[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_6_8[0], _array_literal_expr_7[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_8: UInt<0>[1] + connect _array_literal_expr_8[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_6_8[0], add(_array_literal_expr_8[sub(UInt<64>(0h0), not(allocated_reg[6]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_4_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_4_8, add(reduced_count_4_6, reduced_count_6_8) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_4_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_4_8, or(or(neq(add(reduced_count_4_6, reduced_count_6_8), reduced_count_4_8), reduced_count_overflowed_4_6), reduced_count_overflowed_6_8) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_4_8: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_4_6, gt(reduced_count_4_6, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_4_8[0], reduced_alloc_nums_4_6[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_4_8[0], add(reduced_alloc_nums_6_8[sub(UInt<64>(0h0), reduced_count_4_6)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_8, add(reduced_count_0_4, reduced_count_4_8) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_8, or(or(neq(add(reduced_count_0_4, reduced_count_4_8), reduced_count_0_8), reduced_count_overflowed_0_4), reduced_count_overflowed_4_8) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_8: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_4, gt(reduced_count_0_4, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<2> + connect reduced_alloc_nums_0_8[0], reduced_alloc_nums_0_4[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_8[0], add(reduced_alloc_nums_4_8[sub(UInt<64>(0h0), reduced_count_0_4)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_10: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_10, add(not(allocated_reg[8]), not(allocated_reg[9])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_10: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_10, or(or(neq(add(not(allocated_reg[8]), not(allocated_reg[9])), reduced_count_8_10), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_10: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[8]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_9: UInt<0>[1] + connect _array_literal_expr_9[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_8_10[0], _array_literal_expr_9[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_10: UInt<0>[1] + connect _array_literal_expr_10[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_10[0], add(_array_literal_expr_10[sub(UInt<64>(0h0), not(allocated_reg[8]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_10_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_10_12, add(not(allocated_reg[10]), not(allocated_reg[11])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_10_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_10_12, or(or(neq(add(not(allocated_reg[10]), not(allocated_reg[11])), reduced_count_10_12), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_10_12: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[10]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_11: UInt<0>[1] + connect _array_literal_expr_11[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_10_12[0], _array_literal_expr_11[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_12: UInt<0>[1] + connect _array_literal_expr_12[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_10_12[0], add(_array_literal_expr_12[sub(UInt<64>(0h0), not(allocated_reg[10]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_12, add(reduced_count_8_10, reduced_count_10_12) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_12, or(or(neq(add(reduced_count_8_10, reduced_count_10_12), reduced_count_8_12), reduced_count_overflowed_8_10), reduced_count_overflowed_10_12) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_12: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_8_10, gt(reduced_count_8_10, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_8_12[0], reduced_alloc_nums_8_10[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_12[0], add(reduced_alloc_nums_10_12[sub(UInt<64>(0h0), reduced_count_8_10)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_12_14: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_12_14, add(not(allocated_reg[12]), not(allocated_reg[13])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_12_14: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_12_14, or(or(neq(add(not(allocated_reg[12]), not(allocated_reg[13])), reduced_count_12_14), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_12_14: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[12]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_13: UInt<0>[1] + connect _array_literal_expr_13[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_12_14[0], _array_literal_expr_13[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_14: UInt<0>[1] + connect _array_literal_expr_14[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_12_14[0], add(_array_literal_expr_14[sub(UInt<64>(0h0), not(allocated_reg[12]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_14_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_14_16, add(not(allocated_reg[14]), not(allocated_reg[15])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_14_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_14_16, or(or(neq(add(not(allocated_reg[14]), not(allocated_reg[15])), reduced_count_14_16), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_14_16: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[14]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_15: UInt<0>[1] + connect _array_literal_expr_15[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_14_16[0], _array_literal_expr_15[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_16: UInt<0>[1] + connect _array_literal_expr_16[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_14_16[0], add(_array_literal_expr_16[sub(UInt<64>(0h0), not(allocated_reg[14]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_12_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_12_16, add(reduced_count_12_14, reduced_count_14_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_12_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_12_16, or(or(neq(add(reduced_count_12_14, reduced_count_14_16), reduced_count_12_16), reduced_count_overflowed_12_14), reduced_count_overflowed_14_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_12_16: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_12_14, gt(reduced_count_12_14, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_12_16[0], reduced_alloc_nums_12_14[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_12_16[0], add(reduced_alloc_nums_14_16[sub(UInt<64>(0h0), reduced_count_12_14)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_16, add(reduced_count_8_12, reduced_count_12_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_16, or(or(neq(add(reduced_count_8_12, reduced_count_12_16), reduced_count_8_16), reduced_count_overflowed_8_12), reduced_count_overflowed_12_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_16: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_8_12, gt(reduced_count_8_12, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<2> + connect reduced_alloc_nums_8_16[0], reduced_alloc_nums_8_12[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_16[0], add(reduced_alloc_nums_12_16[sub(UInt<64>(0h0), reduced_count_8_12)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_16, add(reduced_count_0_8, reduced_count_8_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_16, or(or(neq(add(reduced_count_0_8, reduced_count_8_16), reduced_count_0_16), reduced_count_overflowed_0_8), reduced_count_overflowed_8_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_16: UInt<4>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_8, gt(reduced_count_0_8, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<4> + ; rhs: UInt<3> + connect reduced_alloc_nums_0_16[0], reduced_alloc_nums_0_8[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<4> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] + wire firing_data_1: Ty55 @[ready_valid.rs 30:27] connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when alloc_out[0].ready: @[ready_valid.rs 33:9] connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]