From 4bfb20d1b0d249c8c03fc7579c816f7446270484 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 13 May 2026 23:34:24 -0700 Subject: [PATCH] WIP: updating for fayalite/redo-trace-as-string --- Cargo.lock | 4 - Cargo.toml | 3 +- crates/cpu/src/rename_execute_retire.rs | 77 +++++++------ crates/cpu/tests/rename_execute_retire.rs | 133 ++++++++++++---------- 4 files changed, 118 insertions(+), 99 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index b2d9619..51828ab 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -388,7 +388,6 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6" [[package]] name = "fayalite" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#ea183eac8722a8ed1156420f9028364428c792ff" dependencies = [ "base64", "bitvec", @@ -417,7 +416,6 @@ dependencies = [ [[package]] name = "fayalite-proc-macros" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#ea183eac8722a8ed1156420f9028364428c792ff" dependencies = [ "fayalite-proc-macros-impl", ] @@ -425,7 +423,6 @@ dependencies = [ [[package]] name = "fayalite-proc-macros-impl" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#ea183eac8722a8ed1156420f9028364428c792ff" dependencies = [ "base16ct 0.2.0", "num-bigint", @@ -440,7 +437,6 @@ dependencies = [ [[package]] name = "fayalite-visit-gen" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#ea183eac8722a8ed1156420f9028364428c792ff" dependencies = [ "indexmap", "prettyplease", diff --git a/Cargo.toml b/Cargo.toml index cc5e746..3efb769 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -15,7 +15,8 @@ rust-version = "1.93.0" [workspace.dependencies] base16ct = "1.0.0" -fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" } +#fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" } +fayalite = { path = "../fayalite/crates/fayalite" } hex-literal = "1.1.0" parse_powerisa_pdf = { git = "https://git.libre-chip.org/libre-chip/parse_powerisa_pdf.git", version = "0.1.0", branch = "master" } roxmltree = "0.21.1" diff --git a/crates/cpu/src/rename_execute_retire.rs b/crates/cpu/src/rename_execute_retire.rs index 14fb39f..c870786 100644 --- a/crates/cpu/src/rename_execute_retire.rs +++ b/crates/cpu/src/rename_execute_retire.rs @@ -56,7 +56,7 @@ pub struct MOpInstance { /// it needs to be canceled along with all other µOps that /// come from the same ISA-level instruction. pub is_last_mop_in_insn: Bool, - pub mop: MOp, + pub mop: TraceAsString, } impl SimValueDebug for MOpInstance { @@ -139,14 +139,14 @@ pub struct UnitEnqueue> { pub struct UnitInputsReady> { /// the whole `MOpInstance` is sent again so Units can just ignore all [`UnitEnqueue`] messages if desired. pub mop: MOpInstance>, - pub src_values: Array, + pub src_values: Array, { COMMON_MOP_SRC_LEN }>, pub config: C, } #[hdl(no_static)] pub struct UnitOutputReady> { pub id: MOpId, - pub dest_value: PRegValue, + pub dest_value: TraceAsString, pub predictor_op: NextPcPredictorOp, } @@ -273,13 +273,13 @@ type MOpRegCount> = DynSize; #[hdl(no_static)] struct RenameTableDebugState> { - entries: ArrayType, MOpRegCount>, + entries: ArrayType>, MOpRegCount>, config: C, } #[derive(Debug)] struct RenameTable { - entries: Box<[SimValue>; 1 << MOpRegNum::WIDTH]>, + entries: Box<[SimValue>>; 1 << MOpRegNum::WIDTH]>, config: C, } @@ -301,7 +301,7 @@ impl Clone for RenameTable { enum RenameTableUpdate { Write { unrenamed_reg_num: u32, - new: SimValue>, + new: SimValue>>, }, UpdateForReadL2Reg { dest: SimValue>, @@ -315,10 +315,13 @@ enum RenameTableUpdate { impl RenameTable { fn new(config: C) -> Self { - let entries: Box<[SimValue>; 1 << MOpRegNum::WIDTH]> = - vec![RenameTableEntry[config].const_zero(); 1 << MOpRegNum::WIDTH] - .try_into() - .expect("size is known to match"); + let entries: Box<[SimValue>>; 1 << MOpRegNum::WIDTH]> = + vec![ + RenameTableEntry[config].const_zero().into_trace_as_string(); + 1 << MOpRegNum::WIDTH + ] + .try_into() + .expect("size is known to match"); Self { entries, config } } #[hdl] @@ -350,7 +353,7 @@ impl RenameTable { (RenameTableEntry[self.config]).L1(dest); for (unrenamed_reg_num, entry) in self.entries.iter_mut().enumerate() { #[hdl(sim)] - match &entry { + match entry.inner() { RenameTableEntry::<_>::L1(_) => {} RenameTableEntry::<_>::L2(l2) => { if L2RegNum::value_sim(l2) == L2RegNum::value_sim(src) { @@ -358,7 +361,7 @@ impl RenameTable { "{rename_table_name}: UpdateForReadL2Reg: {unrenamed_reg_num:#x} \ updating from {entry:?} to {new:?}", ); - *entry = new.clone(); + *entry = new.to_trace_as_string(); } } } @@ -369,14 +372,14 @@ impl RenameTable { (RenameTableEntry[self.config]).L2(dest); for (unrenamed_reg_num, entry) in self.entries.iter_mut().enumerate() { #[hdl(sim)] - match &entry { + match entry.inner() { RenameTableEntry::<_>::L1(l1) => { if l1 == src { println!( "{rename_table_name}: UpdateForWriteL2Reg: {unrenamed_reg_num:#x} \ updating from {entry:?} to {new:?}", ); - *entry = new.clone(); + *entry = new.to_trace_as_string(); } } RenameTableEntry::<_>::L2(_) => {} @@ -390,7 +393,7 @@ impl RenameTable { let mut seen = BTreeSet::new(); for entry in self.entries.iter() { #[hdl(sim)] - match entry { + match entry.inner() { RenameTableEntry::<_>::L1(v) => { if UnitNum::index_sim(&v.unit_num) == Some(unit_index) { seen.insert(UnitOutRegNum::value_sim(&v.unit_out_reg)); @@ -649,7 +652,7 @@ impl RobEntry { } } fn dest_reg(&self) -> Option<&SimValue>> { - let dest_reg = MOpTrait::dest_reg_sim_ref(&self.mop.mop); + let dest_reg = MOpTrait::dest_reg_sim_ref(self.mop.mop.inner()); let unit_index = UnitNum::index_sim(&dest_reg.unit_num)?; assert_eq!(unit_index, self.unit_index); Some(dest_reg) @@ -1035,7 +1038,7 @@ pub struct RenameExecuteRetireDebugState> { next_pc_canceling: HdlOption, unit_canceling: ArrayType>, l1_reg_file: ArrayType< - ArrayType, CpuConfig2PowOutRegNumWidth>, + ArrayType>, CpuConfig2PowOutRegNumWidth>, CpuConfigUnitCount, >, lfsr: LFSR31, @@ -1050,7 +1053,7 @@ struct RenameExecuteRetireState { rob: ReorderBuffer, next_pc_canceling: Option, unit_canceling: Box<[bool]>, - l1_reg_file: Box<[Box<[Option>]>]>, + l1_reg_file: Box<[Box<[Option>>]>]>, lfsr: SimValue, l2_reg_file_unit_index: usize, config: C, @@ -1227,7 +1230,7 @@ impl RenameExecuteRetireState { { allocated_regs[unit_out_reg_index] = true; } - MOpTrait::for_each_src_reg_sim_ref(&renamed.mop.mop, &mut |src_reg, _index| { + MOpTrait::for_each_src_reg_sim_ref(renamed.mop.mop.inner(), &mut |src_reg, _index| { #[hdl(sim)] let PRegNum::<_> { unit_num, @@ -1245,7 +1248,7 @@ impl RenameExecuteRetireState { .chain(self.retire_rename_table.entries.iter()) { #[hdl(sim)] - match entry { + match entry.inner() { RenameTableEntry::<_>::L1(entry) => { if Some(unit_index) == UnitNum::index_sim(&entry.unit_num) { allocated_regs[UnitOutRegNum::value_sim(&entry.unit_out_reg)] = true; @@ -1262,7 +1265,7 @@ impl RenameExecuteRetireState { let mut allocated_regs = vec![false; L2RegNum.l2_reg_count()]; for renamed in self.rob.renamed() { #[hdl(sim)] - if let RenamedMOp::<_>::TransformedMove(l2_register_file_op) = &renamed.mop.mop { + if let RenamedMOp::<_>::TransformedMove(l2_register_file_op) = renamed.mop.mop.inner() { let l2_reg = #[hdl(sim)] match l2_register_file_op { L2RegisterFileMOp::<_, _>::ReadL2Reg(v) => &v.common.imm, @@ -1278,7 +1281,7 @@ impl RenameExecuteRetireState { .chain(self.retire_rename_table.entries.iter()) { #[hdl(sim)] - match entry { + match entry.inner() { RenameTableEntry::<_>::L1(_) => {} RenameTableEntry::<_>::L2(entry) => { allocated_regs[L2RegNum::value_sim(entry)] = true; @@ -1337,9 +1340,9 @@ impl RenameExecuteRetireState { }, ); } - let unit_kind = UnitMOp::kind_sim(&insn.mop); + let unit_kind = UnitMOp::kind_sim(insn.mop.inner()); #[hdl(sim)] - if let MOp::TransformedMove(move_reg_mop) = &insn.mop { + if let MOp::TransformedMove(move_reg_mop) = insn.mop.inner() { let mut src_regs = [MOpRegNum::const_zero_sim()]; MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| { src_regs[index] = src_reg.clone(); @@ -1468,14 +1471,14 @@ impl RenameExecuteRetireState { }; println!("try_rename: picked {reg_to_free:?}"); let mut any_collisions = false; - MOpTrait::for_each_src_reg_sim_ref(&insn.mop, &mut |src_reg, _| { + MOpTrait::for_each_src_reg_sim_ref(insn.mop.inner(), &mut |src_reg, _| { let renamed = &self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize]; println!( "try_rename: checking that mop src reg ({renamed:?}) doesn't conflict with picked reg" ); #[hdl(sim)] - match renamed { + match renamed.inner() { RenameTableEntry::<_>::L1(v) => { if reg_to_free == *v { any_collisions = true; @@ -1520,7 +1523,8 @@ impl RenameExecuteRetireState { PRegNum[self.config].const_zero(), repeat(®_to_free, ConstUsize::<1>), dest, - ), + ) + .into_trace_as_string(), }, self.l2_reg_file_unit_index, ), @@ -1561,21 +1565,21 @@ impl RenameExecuteRetireState { mop, } = &insn; let mut needed_load = None; - let unrenamed_dest_regs = MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(mop)); + let unrenamed_dest_regs = MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(mop.inner())); let renamed_dest_reg = #[hdl(sim)] PRegNum::<_> { unit_num: UnitNum[self.config].from_index_sim(unit_index), unit_out_reg: out_reg_num_sim, }; let mop = MOpTrait::map_regs_sim( - mop, + mop.inner(), &renamed_dest_reg, PRegNum[self.config], &mut |src_reg, index| { let renamed = &self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize]; println!("renaming src[{index}] from {src_reg:?} to {renamed:?}"); #[hdl(sim)] - match renamed { + match renamed.inner() { RenameTableEntry::<_>::L1(v) => v.clone(), RenameTableEntry::<_>::L2(v) => { needed_load.get_or_insert_with(|| v.clone()); @@ -1616,7 +1620,8 @@ impl RenameExecuteRetireState { dest, repeat(PRegNum[self.config].const_zero_sim(), ConstUsize), needed_load, - ), + ) + .into_trace_as_string(), }, self.l2_reg_file_unit_index, ), @@ -1644,7 +1649,8 @@ impl RenameExecuteRetireState { mop, RenamedMOp[self.config].TransformedMove, |_move_reg| unreachable!(), - ); + ) + .into_trace_as_string(); let renamed_dest_reg = #[hdl(sim)] (RenameTableEntry[self.config]).L1(renamed_dest_reg); for unrenamed_reg_num in unrenamed_dest_regs { @@ -1652,7 +1658,7 @@ impl RenameExecuteRetireState { &insn, RenameTableUpdate::Write { unrenamed_reg_num, - new: renamed_dest_reg.clone(), + new: renamed_dest_reg.to_trace_as_string(), }, ); } @@ -1711,14 +1717,14 @@ impl RenameExecuteRetireState { return retval; // separate variable to work around rust-analyzer parse error } let zero_reg = PRegNum[self.config].const_zero().into_sim_value(); - let zero_value = zeroed(PRegValue); + let zero_value = zeroed(TraceAsString[PRegValue]); for rob in self.rob.renamed() { if rob.unit_index == unit_index && let Some(_) = rob.mop_in_unit_state.with_inputs_ready() { let mut src_values: [_; COMMON_MOP_SRC_LEN] = std::array::from_fn(|_| Some(zero_value.clone())); - MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| { + MOpTrait::for_each_src_reg_sim_ref(rob.mop.mop.inner(), &mut |src_reg, index| { #[hdl(sim)] let PRegNum::<_> { unit_num, @@ -1730,7 +1736,6 @@ impl RenameExecuteRetireState { .clone(); } else { assert_eq!(*src_reg, zero_reg); - src_values[index] = Some(zeroed(PRegValue)); } }); if src_values.iter().all(|v| v.is_some()) { diff --git a/crates/cpu/tests/rename_execute_retire.rs b/crates/cpu/tests/rename_execute_retire.rs index 2ae3076..178ebcb 100644 --- a/crates/cpu/tests/rename_execute_retire.rs +++ b/crates/cpu/tests/rename_execute_retire.rs @@ -87,15 +87,15 @@ impl RandomState { const START_PC: u64 = 0x0; // match microwatt's reset pc #[derive(Clone, Debug)] -struct Insn>> { +struct Insn>>> { size_in_bytes: u8, power_isa: String, mops: MOps, } enum LazyMOps { - MOps(Vec>), - Lazy(Box Vec>>), + MOps(Vec>>), + Lazy(Box Vec>>>), } impl Insn { @@ -107,7 +107,11 @@ impl Insn { Self { size_in_bytes, power_isa, - mops: LazyMOps::MOps(mops.into_iter().map(|mop| mop.into_sim_value()).collect()), + mops: LazyMOps::MOps( + mops.into_iter() + .map(|mop| mop.into_sim_value().into_trace_as_string()) + .collect(), + ), } } fn new_lazy>>( @@ -121,7 +125,7 @@ impl Insn { mops: LazyMOps::Lazy(Box::new(|labels| { lazy_mops(labels) .into_iter() - .map(|mop| mop.into_sim_value()) + .map(|mop| mop.into_sim_value().into_trace_as_string()) .collect() })), } @@ -772,7 +776,7 @@ impl<'a, C: PhantomConstCpuConfig> MockNextPcState<'a, C> { }; let mop = &insn.mops[self.next_mop_index]; #[hdl(sim)] - if let MOp::AluBranch(mop) = mop { + if let MOp::AluBranch(mop) = mop.inner() { #[hdl(sim)] match mop { AluBranchMOp::<_, _>::Branch(mop) => { @@ -1043,7 +1047,8 @@ type SimOnlyMemoryChunk = SimOnly; struct MockMemoryDebugState = PhantomConst<()>> { wrote_output: Bool, memory: ArrayType>, - l1_cache: Array, { MockMemory::CACHE_LINE_COUNT }>, + l1_cache: + Array>, { MockMemory::CACHE_LINE_COUNT }>, } #[derive(Debug, Clone)] @@ -1291,6 +1296,7 @@ impl MockMemory { #[hdl(sim)] HdlNone() } + .into_trace_as_string() }), } } @@ -1298,16 +1304,16 @@ impl MockMemory { fn run_mop( &mut self, mop: &SimValue, PRegNum>>>, - src_values: &[SimValue; COMMON_MOP_SRC_LEN], + src_values: &[SimValue>; COMMON_MOP_SRC_LEN], is_speculative: bool, - ) -> Result, AddressCantBeSpeculativelyAccessed> { + ) -> Result>, AddressCantBeSpeculativelyAccessed> { println!("MockMemory::run_mop: {:#x}: {:?}", mop.pc.as_int(), mop.mop); println!( "<- {}{src_values:?}", if is_speculative { "(speculative) " } else { "" }, ); let retval = #[hdl(sim)] - match &mop.mop { + match mop.mop.inner() { LoadStoreMOp::<_, _>::Load(mop) => { #[hdl(sim)] let LoadMOp::<_, _> { load_store_common } = mop; @@ -1317,7 +1323,7 @@ impl MockMemory { width, conversion, } = load_store_common; - let addr = src_values[0].int_fp.as_int(); + let addr = src_values[0].inner().int_fp.as_int(); let loaded = #[hdl(sim)] match conversion { LoadStoreConversion::ZeroExt => @@ -1372,8 +1378,8 @@ impl MockMemory { width, conversion, } = load_store_common; - let addr = src_values[0].int_fp.as_int(); - let value = src_values[1].int_fp.as_int(); + let addr = src_values[0].inner().int_fp.as_int(); + let value = src_values[1].inner().int_fp.as_int(); #[hdl(sim)] match conversion { LoadStoreConversion::ZeroExt | LoadStoreConversion::SignExt => @@ -1399,7 +1405,7 @@ impl MockMemory { } }; println!("-> {retval:?}"); - Ok(retval) + Ok(retval.into_trace_as_string()) } } @@ -1413,8 +1419,8 @@ trait MockExecutionStateTrait: Default { &mut self, pc: u64, mop: &SimValue, PRegNum, SrcCount>>, - src_values: &[SimValue; COMMON_MOP_SRC_LEN], - ) -> SimValue { + src_values: &[SimValue>; COMMON_MOP_SRC_LEN], + ) -> SimValue> { #[hdl(sim)] let AddSubMOp::<_, _, _> { alu_common, @@ -1447,10 +1453,11 @@ trait MockExecutionStateTrait: Default { let pc_or_zero = if **add_pc { pc } else { 0 }; let [src0, src1, src2] = src_values; let int_fp = src0 + .inner() .int_fp .as_int() - .wrapping_add(src1.int_fp.as_int()) - .wrapping_add(src2.int_fp.as_int()) + .wrapping_add(src1.inner().int_fp.as_int()) + .wrapping_add(src2.inner().int_fp.as_int()) .wrapping_add(SimValue::value(imm).cast_to_static::>().as_int()) .wrapping_add(pc_or_zero); let int_fp = #[hdl(sim)] @@ -1467,18 +1474,19 @@ trait MockExecutionStateTrait: Default { OutputIntegerMode::ZeroExt8 => int_fp as u8 as u64, OutputIntegerMode::SignExt8 => int_fp as i8 as u64, }; - #[hdl(sim)] + let retval = #[hdl(sim)] PRegValue { int_fp, flags: PRegFlags::zeroed_sim(), // TODO: compute flags - } + }; + retval.into_trace_as_string() } #[hdl] fn run_compare( &mut self, mop: &SimValue, PRegNum, SrcCount>>, - src_values: &[SimValue; COMMON_MOP_SRC_LEN], - ) -> SimValue { + src_values: &[SimValue>; COMMON_MOP_SRC_LEN], + ) -> SimValue> { #[hdl(sim)] let CompareMOp::<_, _, _> { common, @@ -1493,13 +1501,16 @@ trait MockExecutionStateTrait: Default { } = common; let (lhs, rhs) = match SrcCount::VALUE { 1 => ( - src_values[0].int_fp.as_int(), + src_values[0].inner().int_fp.as_int(), SimValue::value(imm).cast_to_static::>().as_int(), ), - 2 => (src_values[0].int_fp.as_int(), src_values[1].int_fp.as_int()), + 2 => ( + src_values[0].inner().int_fp.as_int(), + src_values[1].inner().int_fp.as_int(), + ), _ => todo!(), }; - let ordering_to_result = |v: Ordering| -> SimValue { + let ordering_to_result = |v: Ordering| -> SimValue> { let mut retval = #[hdl(sim)] PRegValue { int_fp: 0u64, @@ -1511,7 +1522,7 @@ trait MockExecutionStateTrait: Default { Ordering::Equal => **flags.cr_eq = true, Ordering::Greater => **flags.cr_gt = true, } - retval + retval.into_trace_as_string() }; #[hdl(sim)] match compare_mode { @@ -1537,10 +1548,10 @@ trait MockExecutionStateTrait: Default { fallthrough_pc: u64, predicted_next_pc: u64, mop: &SimValue, PRegNum, SrcCount>>, - src_values: &[SimValue; COMMON_MOP_SRC_LEN], + src_values: &[SimValue>; COMMON_MOP_SRC_LEN], config: C, ) -> ( - SimValue, + SimValue>, SimValue>, Option>>, ) { @@ -1577,7 +1588,7 @@ trait MockExecutionStateTrait: Default { } else { true }; - let src0_flags = PRegFlags::view_sim_ref::(&src0.flags); + let src0_flags = PRegFlags::view_sim_ref::(&src0.inner().flags); let src0_cond = #[hdl(sim)] match src0_cond_mode { ConditionMode::Eq => **src0_flags.cr_eq, @@ -1592,6 +1603,7 @@ trait MockExecutionStateTrait: Default { let src0_cond = src0_cond ^ **invert_src0_cond; let pc_or_zero = if **pc_relative { pc } else { 0 }; let target_pc = src1 + .inner() .int_fp .as_int() .wrapping_add(SimValue::value(imm).cast_to_static::>().as_int()) @@ -1615,12 +1627,13 @@ trait MockExecutionStateTrait: Default { } else { None }; + let fallthrough_pc_value = #[hdl(sim)] + PRegValue { + int_fp: fallthrough_pc, + flags: PRegFlags::zeroed_sim(), + }; ( - #[hdl(sim)] - PRegValue { - int_fp: fallthrough_pc, - flags: PRegFlags::zeroed_sim(), - }, + fallthrough_pc_value.into_trace_as_string(), #[hdl(sim)] NextPcPredictorOp::<_> { call_stack_op: if **is_ret { @@ -1649,10 +1662,13 @@ trait MockExecutionStateTrait: Default { fn run_mop( &mut self, mop: &SimValue>>, - src_values: &[SimValue; COMMON_MOP_SRC_LEN], + src_values: &[SimValue>; COMMON_MOP_SRC_LEN], config: C, ) -> ( - Option<(SimValue, SimValue>)>, + Option<( + SimValue>, + SimValue>, + )>, Option>>, ) { #[hdl(sim)] @@ -1680,7 +1696,7 @@ trait MockExecutionStateTrait: Default { } }; #[hdl(sim)] - match mop { + match mop.inner() { UnitMOp::<_, _, _>::AluBranch(mop) => { #[hdl(sim)] @@ -1780,7 +1796,7 @@ impl MockExecutionStateTrait for () { #[hdl(no_static)] struct MockUnitOpDebugState> { mop: MOpInstance>, - src_values: Array, + src_values: Array, { COMMON_MOP_SRC_LEN }>, sent_cant_cause_cancel: Bool, output_ready: HdlOption>, caused_cancel: HdlOption>, @@ -1790,7 +1806,7 @@ struct MockUnitOpDebugState> { #[derive(Debug)] struct MockUnitOp { mop: SimValue>>, - src_values: [SimValue; COMMON_MOP_SRC_LEN], + src_values: [SimValue>; COMMON_MOP_SRC_LEN], sent_cant_cause_cancel: bool, output_ready: Option>>, caused_cancel: Option>>, @@ -1999,7 +2015,7 @@ impl MockUnitState { config: _, } = inputs_ready; assert_eq!( - UnitNum::index_sim(&MOpTrait::dest_reg_sim_ref(&mop.mop).unit_num), + UnitNum::index_sim(&MOpTrait::dest_reg_sim_ref(mop.mop.inner()).unit_num), Some(self.unit_index), ); let mut op = MockUnitOp { @@ -2225,8 +2241,8 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>( #[hdl(no_static)] struct MockL2RegFileOpDebugState> { mop: MOpInstance, PRegNum>>, - src_values: HdlOption>, - dest_value: HdlOption, + src_values: HdlOption, { COMMON_MOP_SRC_LEN }>>, + dest_value: HdlOption>, sent_cant_cause_cancel: Bool, sent_output_ready: Bool, config: C, @@ -2235,8 +2251,8 @@ struct MockL2RegFileOpDebugState> { #[derive(Debug)] struct MockL2RegFileOp { mop: SimValue, PRegNum>>>, - src_values: Option<[SimValue; COMMON_MOP_SRC_LEN]>, - dest_value: Option>, + src_values: Option<[SimValue>; COMMON_MOP_SRC_LEN]>, + dest_value: Option>>, sent_cant_cause_cancel: bool, sent_output_ready: bool, config: C, @@ -2274,13 +2290,13 @@ type L2RegFileSize> = DynSize; #[hdl(no_static)] struct MockL2RegFileUnitDebugState> { ops: ArrayVec, CpuConfigMaxUnitMaxInFlight>, - l2_regs: ArrayType>, + l2_regs: ArrayType, L2RegFileSize>, config: C, } struct MockL2RegFileUnitState { ops: VecDeque>, - l2_regs: Box<[SimValue]>, + l2_regs: Box<[SimValue>]>, config: C, } @@ -2288,7 +2304,8 @@ impl MockL2RegFileUnitState { fn new(config: C) -> Self { Self { ops: VecDeque::new(), - l2_regs: vec![PRegValue::zeroed_sim(); L2RegFileSize[config]].into_boxed_slice(), + l2_regs: vec![PRegValue::zeroed_sim().into_trace_as_string(); L2RegFileSize[config]] + .into_boxed_slice(), config, } } @@ -2346,7 +2363,7 @@ impl MockL2RegFileUnitState { config: _, } = op; #[hdl(sim)] - match &mop.mop { + match mop.mop.inner() { L2RegisterFileMOp::<_, _>::ReadL2Reg(mop) => { #[hdl(sim)] let ReadL2RegMOp::<_, _> { common } = mop; @@ -2361,7 +2378,7 @@ impl MockL2RegFileUnitState { && dest_value.is_none() { self.l2_regs[L2RegNum::value_sim(&common.imm)] = src_values[0].clone(); - *dest_value = Some(PRegValue::zeroed_sim()); + *dest_value = Some(PRegValue::zeroed_sim().into_trace_as_string()); } if dest_value.is_none() { // we can't run following reads yet. @@ -2387,7 +2404,7 @@ impl MockL2RegFileUnitState { mop, } = mop; let mop = #[hdl(sim)] - match &mop { + match mop.inner() { RenamedMOp::<_>::TransformedMove(mop) => mop, _ => { panic!("MockL2RegFileUnitState can only handle L2RegisterFile MOps, got: {mop:#?}"); @@ -2402,7 +2419,7 @@ impl MockL2RegFileUnitState { size_in_bytes, is_first_mop_in_insn, is_last_mop_in_insn, - mop, + mop: mop.into_trace_as_string(), }; self.ops.push_back(MockL2RegFileOp { mop, @@ -2767,8 +2784,8 @@ fn mock_l2_reg_file_unit(config: PhantomConst, unit_index: usize) { struct MockLoadStoreOpDebugState> { mop: MOpInstance, PRegNum>>, is_speculative: Bool, - src_values: HdlOption>, - dest_value: HdlOption, + src_values: HdlOption, { COMMON_MOP_SRC_LEN }>>, + dest_value: HdlOption>, ran_nonspeculatively: Bool, sent_cant_cause_cancel: Bool, sent_output_ready: Bool, @@ -2779,8 +2796,8 @@ struct MockLoadStoreOpDebugState> { struct MockLoadStoreOp { mop: SimValue, PRegNum>>>, is_speculative: bool, - src_values: Option<[SimValue; COMMON_MOP_SRC_LEN]>, - dest_value: Option>, + src_values: Option<[SimValue>; COMMON_MOP_SRC_LEN]>, + dest_value: Option>>, ran_nonspeculatively: bool, sent_cant_cause_cancel: bool, sent_output_ready: bool, @@ -2913,7 +2930,7 @@ impl MockLoadStoreUnitState { } } #[hdl(sim)] - match &mop.mop { + match mop.mop.inner() { LoadStoreMOp::<_, _>::Load(load_mop) => { #[hdl(sim)] let LoadMOp::<_, _> { load_store_common } = load_mop; @@ -2988,7 +3005,7 @@ impl MockLoadStoreUnitState { mop, } = mop; let mop = #[hdl(sim)] - match &mop { + match mop.inner() { RenamedMOp::<_>::LoadStore(mop) => mop, _ => panic!("MockLoadStoreUnitState can only handle LoadStore MOps, got: {mop:#?}"), }; @@ -3001,7 +3018,7 @@ impl MockLoadStoreUnitState { size_in_bytes, is_first_mop_in_insn, is_last_mop_in_insn, - mop, + mop: mop.into_trace_as_string(), }; self.ops.push_back(MockLoadStoreOp { mop,