WIP: adding ExecuteToUnitInterface::other_units_cant_cause_cancels_before

crates/cpu/src/rename_execute_retire.rs

@@ -203,6 +203,18 @@ pub struct UnitMOpCantCauseCancel<C: PhantomConstGet<CpuConfig>> {
     pub config: C,
 }
 
+/// This tells the Unit that:
+/// * Other Units can't cause any cancels for any µOps before [`Self::id`] (so all µOps before then are either assigned to this Unit or have reported that they can't cause a cancel or have finished without causing a cancel).
+///
+/// The rename/execute/retire logic guarantees:
+/// * [`Self::id`] refers to a µOp that is/was enqueued in this Unit.
+/// * This was not previously told to the unit.
+#[hdl(no_static)]
+pub struct UnitMOpOtherUnitsCantCauseCancelsBefore<C: PhantomConstGet<CpuConfig>> {
+    pub id: MOpId,
+    pub config: C,
+}
+
 /// Interface from the Rename/Execute/Retire control logic to a single Unit.
 ///
 /// ## State diagram for a single &micro;Op in a Unit
@@ -223,6 +235,9 @@ pub struct ExecuteToUnitInterface<C: PhantomConstGet<CpuConfig>> {
     pub inputs_ready: HdlOption<UnitInputsReady<C>>,
     /// if [`Self::unit_outputs_ready`] is `false`, then this is always [`HdlNone`]
     pub is_no_longer_speculative: HdlOption<UnitMOpIsNoLongerSpeculative<C>>,
+    /// if [`Self::unit_outputs_ready`] is `false`, then this is always [`HdlNone`]
+    pub other_units_cant_cause_cancels_before:
+        HdlOption<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
     /// this uses [`Self::unit_outputs_ready`] as a shared ready flag
     #[hdl(flip)]
     pub cant_cause_cancel: HdlOption<UnitMOpCantCauseCancel<C>>,
@@ -466,6 +481,16 @@ impl MOpInUnitState {
             Self::FinishedAndOrCausedCancel => true,
         }
     }
+    /// return `true` if this µOp has been enqueued and has neither finished nor caused a cancel.
+    fn is_active(self) -> bool {
+        match self {
+            Self::NotYetEnqueued => false,
+            Self::InputsNotReadySpeculative { .. }
+            | Self::InputsReady { .. }
+            | Self::OutputReady { .. } => true,
+            Self::FinishedAndOrCausedCancel => false,
+        }
+    }
 }
 
 impl fmt::Debug for MOpInUnitState {
@@ -614,6 +639,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel,
             output,
             caused_cancel,
+            other_units_cant_cause_cancels_before,
+            sent_other_units_cant_cause_cancels_before,
         } in self.rob.renamed()
         {
             let masked_id = mop.id.as_int() as usize & mask;
@@ -631,6 +658,11 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
                 if *all_prior_mops_finished_and_or_caused_cancel {
                     f.write_str("(apfc)")?;
                 }
+                if *sent_other_units_cant_cause_cancels_before {
+                    f.write_str("(socccb)")?;
+                } else if *other_units_cant_cause_cancels_before {
+                    f.write_str("(occcb)")?;
+                }
                 if output.is_some() {
                     f.write_str("(output)")?;
                 }
@@ -647,7 +679,6 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
                 )
             })
             .to_string();
-            // TODO
         }
         retval
     }
@@ -1219,6 +1250,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output: _,
             caused_cancel: _,
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         } in self.rob.renamed()
         {
             if *done_waiting_for_register_fences
@@ -1263,31 +1296,50 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
     fn get_unit_mop_is_no_longer_speculative(
         &self,
         unit_index: usize,
-    ) -> SimValue<HdlOption<UnitMOpIsNoLongerSpeculative<C>>> {
-        let ret_ty = HdlOption[UnitMOpIsNoLongerSpeculative[self.config]];
+    ) -> Option<SimValue<UnitMOpIsNoLongerSpeculative<C>>> {
         if self.is_canceling() {
-            let retval = #[hdl(sim)]
-            ret_ty.HdlNone();
-            return retval; // separate variable to work around rust-analyzer parse error
+            return None;
         }
         for rob in self.rob.renamed() {
             if rob.unit_index == unit_index
                 && !rob.is_speculative
                 && let Some(_) = rob.mop_in_unit_state.without_speculative()
             {
-                let retval = #[hdl(sim)]
-                ret_ty.HdlSome(
+                return Some(
                     #[hdl(sim)]
                     UnitMOpIsNoLongerSpeculative::<_> {
                         id: &rob.mop.id,
                         config: self.config,
                     },
                 );
-                return retval; // separate variable to work around rust-analyzer parse error
             }
         }
-        #[hdl(sim)]
-        ret_ty.HdlNone()
+        None
+    }
+    #[hdl]
+    fn get_unit_mop_other_units_cant_cause_cancels_before(
+        &self,
+        unit_index: usize,
+    ) -> Option<SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>> {
+        if self.is_canceling() {
+            return None;
+        }
+        for rob in self.rob.renamed() {
+            if rob.unit_index == unit_index
+                && rob.other_units_cant_cause_cancels_before
+                && rob.is_speculative
+                && !rob.sent_other_units_cant_cause_cancels_before
+            {
+                return Some(
+                    #[hdl(sim)]
+                    UnitMOpOtherUnitsCantCauseCancelsBefore::<_> {
+                        id: &rob.mop.id,
+                        config: self.config,
+                    },
+                );
+            }
+        }
+        None
     }
     #[hdl]
     fn unit_output_ready(&mut self, output_ready: SimValue<UnitOutputReady<C>>) {
@@ -1310,6 +1362,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output,
             caused_cancel,
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         } = rob;
         assert!(output.is_none());
         assert!(caused_cancel.is_none());
@@ -1345,6 +1399,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output,
             caused_cancel,
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         } = self.rob.renamed_by_id_mut(&id);
         assert!(caused_cancel.is_none());
         let cancel_after_retire;
@@ -1459,6 +1515,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
                     all_prior_mops_finished_and_or_caused_cancel: _,
                     output,
                     caused_cancel,
+                    other_units_cant_cause_cancels_before: _,
+                    sent_other_units_cant_cause_cancels_before: _,
                 } = renamed_entry
                 {
                     if caused_cancel.is_some() {
@@ -1584,6 +1642,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output: _,
             caused_cancel,
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         } in renamed_entries
         {
             assert_eq!(mop_in_unit_state, MOpInUnitState::FinishedAndOrCausedCancel);
@@ -1618,24 +1678,24 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             };
         }
         for renamed in self.rob.renamed_mut() {
-            let can_cause_cancel = match renamed.mop_in_unit_state {
-                MOpInUnitState::NotYetEnqueued => true,
-                MOpInUnitState::InputsNotReadySpeculative { can_cause_cancel } => can_cause_cancel,
-                MOpInUnitState::InputsReady {
-                    speculative: _,
-                    can_cause_cancel,
-                } => can_cause_cancel,
-                MOpInUnitState::OutputReady {
-                    speculative: _,
-                    can_cause_cancel,
-                } => can_cause_cancel,
-                MOpInUnitState::FinishedAndOrCausedCancel => renamed.caused_cancel.is_some(),
-            };
             renamed.is_speculative = false;
-            if can_cause_cancel {
+            if renamed.can_cause_cancel() {
                 break;
             }
         }
+        let mut unit_that_can_cause_cancel = None;
+        for renamed in self.rob.renamed_mut() {
+            if unit_that_can_cause_cancel.is_none_or(|v| v == renamed.unit_index) {
+                renamed.other_units_cant_cause_cancels_before = true;
+            }
+            if renamed.can_cause_cancel() {
+                let unit_that_can_cause_cancel =
+                    *unit_that_can_cause_cancel.get_or_insert(renamed.unit_index);
+                if unit_that_can_cause_cancel != renamed.unit_index {
+                    break;
+                }
+            }
+        }
         for renamed in self.rob.renamed_mut() {
             let RobEntry {
                 is_register_fence,
@@ -1647,6 +1707,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
                 all_prior_mops_finished_and_or_caused_cancel,
                 output: _,
                 caused_cancel: _,
+                other_units_cant_cause_cancels_before: _,
+                sent_other_units_cant_cause_cancels_before: _,
             } = &renamed;
             if *is_register_fence {
                 if !*all_prior_mops_finished_and_or_caused_cancel || *is_speculative {
@@ -1671,6 +1733,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output: _,
             caused_cancel: Some(caused_cancel),
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         }) = first_renamed
             && !*caused_cancel.cancel_after_retire
         {
@@ -1719,6 +1783,7 @@ async fn rename_execute_retire_run(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
+                other_units_cant_cause_cancels_before,
                 cant_cause_cancel: _,
                 output_ready: _,
                 finish_cause_cancel: _,
@@ -1747,6 +1812,11 @@ async fn rename_execute_retire_run(
                 state.get_unit_mop_is_no_longer_speculative(unit_index),
             )
             .await;
+            sim.write(
+                other_units_cant_cause_cancels_before,
+                state.get_unit_mop_other_units_cant_cause_cancels_before(unit_index),
+            )
+            .await;
             sim.write(unit_outputs_ready, !is_canceling).await;
         }
         sim.wait_for_clock_edge(cd.clk).await;
@@ -1767,6 +1837,7 @@ async fn rename_execute_retire_run(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
+                other_units_cant_cause_cancels_before,
                 cant_cause_cancel,
                 output_ready,
                 finish_cause_cancel,
@@ -1788,6 +1859,8 @@ async fn rename_execute_retire_run(
                         all_prior_mops_finished_and_or_caused_cancel: _,
                         output,
                         caused_cancel,
+                        other_units_cant_cause_cancels_before: _,
+                        sent_other_units_cant_cause_cancels_before: _,
                     } = state.rob.renamed_by_id_mut(&enqueue.mop.id);
                     assert!(output.is_none());
                     assert!(caused_cancel.is_none());
@@ -1809,6 +1882,8 @@ async fn rename_execute_retire_run(
                     all_prior_mops_finished_and_or_caused_cancel: _,
                     output,
                     caused_cancel,
+                    other_units_cant_cause_cancels_before: _,
+                    sent_other_units_cant_cause_cancels_before: _,
                 } = state.rob.renamed_by_id_mut(&inputs_ready.mop.id);
                 assert!(*done_waiting_for_register_fences);
                 assert!(output.is_none());
@@ -1832,11 +1907,37 @@ async fn rename_execute_retire_run(
                     all_prior_mops_finished_and_or_caused_cancel: _,
                     output: _,
                     caused_cancel: _,
+                    other_units_cant_cause_cancels_before: _,
+                    sent_other_units_cant_cause_cancels_before: _,
                 } = state.rob.renamed_by_id_mut(&is_no_longer_speculative.id);
                 *mop_in_unit_state = mop_in_unit_state
                     .without_speculative()
                     .expect("UnitMOpIsNoLongerSpeculative is known to be valid");
             }
+            #[hdl(sim)]
+            if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                .await
+            {
+                assert!(!state.is_canceling());
+                let RobEntry {
+                    is_register_fence: _,
+                    done_waiting_for_register_fences: _,
+                    mop: _,
+                    unit_index: _,
+                    mop_in_unit_state: _,
+                    is_speculative: _,
+                    all_prior_mops_finished_and_or_caused_cancel: _,
+                    output: _,
+                    caused_cancel: _,
+                    other_units_cant_cause_cancels_before,
+                    sent_other_units_cant_cause_cancels_before,
+                } = state
+                    .rob
+                    .renamed_by_id_mut(&other_units_cant_cause_cancels_before.id);
+                assert!(*other_units_cant_cause_cancels_before);
+                *sent_other_units_cant_cause_cancels_before = true;
+            }
             if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                 #[hdl(sim)]
                 if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
@@ -1853,6 +1954,8 @@ async fn rename_execute_retire_run(
                         all_prior_mops_finished_and_or_caused_cancel: _,
                         output: _,
                         caused_cancel,
+                        other_units_cant_cause_cancels_before: _,
+                        sent_other_units_cant_cause_cancels_before: _,
                     } = state.rob.renamed_by_id_mut(&id);
                     assert!(caused_cancel.is_none());
                     *mop_in_unit_state = mop_in_unit_state
@@ -1959,6 +2062,7 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
                             enqueue,
                             inputs_ready,
                             is_no_longer_speculative,
+                            other_units_cant_cause_cancels_before,
                             cant_cause_cancel: _,
                             output_ready: _,
                             finish_cause_cancel: _,
@@ -1992,6 +2096,12 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
                             (is_no_longer_speculative.ty()).HdlNone(),
                         )
                         .await;
+                        sim.write(
+                            other_units_cant_cause_cancels_before,
+                            #[hdl(sim)]
+                            (other_units_cant_cause_cancels_before.ty()).HdlNone(),
+                        )
+                        .await;
                         sim.write(unit_outputs_ready, false).await;
                     }
                 },

crates/cpu/src/rename_execute_retire/reorder_buffer.rs

@@ -40,6 +40,8 @@ struct RobEntryDebugState<C: PhantomConstGet<CpuConfig>> {
     all_prior_mops_finished_and_or_caused_cancel: Bool,
     output: HdlOption<NextPcPredictorOp<C>>,
     caused_cancel: HdlOption<UnitCausedCancel<C>>,
+    other_units_cant_cause_cancels_before: Bool,
+    sent_other_units_cant_cause_cancels_before: Bool,
 }
 
 impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
@@ -55,6 +57,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
             all_prior_mops_finished_and_or_caused_cancel: _,
             output,
             caused_cancel,
+            other_units_cant_cause_cancels_before: _,
+            sent_other_units_cant_cause_cancels_before: _,
         } = self;
         #[hdl(sim)]
         Self {
@@ -69,6 +73,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
             output.HdlNone(),
             caused_cancel: #[hdl(sim)]
             caused_cancel.HdlNone(),
+            other_units_cant_cause_cancels_before: false,
+            sent_other_units_cant_cause_cancels_before: false,
         }
     }
 }
@@ -87,6 +93,8 @@ pub(crate) struct RobEntry<C: PhantomConstCpuConfig> {
     pub(crate) all_prior_mops_finished_and_or_caused_cancel: bool,
     pub(crate) output: Option<SimValue<NextPcPredictorOp<C>>>,
     pub(crate) caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
+    pub(crate) other_units_cant_cause_cancels_before: bool,
+    pub(crate) sent_other_units_cant_cause_cancels_before: bool,
 }
 
 impl<C: PhantomConstCpuConfig> RobEntry<C> {
@@ -105,6 +113,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
             all_prior_mops_finished_and_or_caused_cancel: false,
             output: None,
             caused_cancel: None,
+            other_units_cant_cause_cancels_before: false,
+            sent_other_units_cant_cause_cancels_before: false,
         }
     }
     fn dest_reg(&self) -> Option<&SimValue<PRegNum<C>>> {
@@ -131,6 +141,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
             all_prior_mops_finished_and_or_caused_cancel,
             output,
             caused_cancel,
+            other_units_cant_cause_cancels_before,
+            sent_other_units_cant_cause_cancels_before,
         } = self;
         let ret_ty = RobEntryDebugState[config];
         #[hdl(sim)]
@@ -144,6 +156,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
             all_prior_mops_finished_and_or_caused_cancel,
             output: output.into_sim_value_with_type(ret_ty.output),
             caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel),
+            other_units_cant_cause_cancels_before,
+            sent_other_units_cant_cause_cancels_before,
         }
     }
     #[hdl]
@@ -173,6 +187,21 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
             }
         }
     }
+    pub(crate) fn can_cause_cancel(&self) -> bool {
+        match self.mop_in_unit_state {
+            MOpInUnitState::NotYetEnqueued => true,
+            MOpInUnitState::InputsNotReadySpeculative { can_cause_cancel } => can_cause_cancel,
+            MOpInUnitState::InputsReady {
+                speculative: _,
+                can_cause_cancel,
+            } => can_cause_cancel,
+            MOpInUnitState::OutputReady {
+                speculative: _,
+                can_cause_cancel,
+            } => can_cause_cancel,
+            MOpInUnitState::FinishedAndOrCausedCancel => self.caused_cancel.is_some(),
+        }
+    }
 }
 
 #[hdl]

crates/cpu/src/test/decode_and_run_single_insn.rs

@@ -204,6 +204,7 @@ fn connect_to_unit_nop<C: Type + PhantomConstGet<CpuConfig>>(
         enqueue,
         inputs_ready,
         is_no_longer_speculative,
+        other_units_cant_cause_cancels_before,
         cant_cause_cancel: _,
         output_ready: _,
         finish_cause_cancel: _,
@@ -218,6 +219,10 @@ fn connect_to_unit_nop<C: Type + PhantomConstGet<CpuConfig>>(
         is_no_longer_speculative,
         is_no_longer_speculative.ty().HdlNone(),
     );
+    connect(
+        other_units_cant_cause_cancels_before,
+        other_units_cant_cause_cancels_before.ty().HdlNone(),
+    );
     connect(unit_outputs_ready, false);
     connect(cancel_all.data, HdlNone());
 }
@@ -506,6 +511,7 @@ impl<C: PhantomConstCpuConfig, MaxMOpCount: Size> DecodeAndRunSingleInsnState<C,
                         enqueue,
                         inputs_ready,
                         is_no_longer_speculative,
+                        other_units_cant_cause_cancels_before,
                         cant_cause_cancel: _, // we don't track if it can cause a cancel
                         output_ready,
                         finish_cause_cancel,
@@ -513,6 +519,10 @@ impl<C: PhantomConstCpuConfig, MaxMOpCount: Size> DecodeAndRunSingleInsnState<C,
                         cancel_all,
                         config: _,
                     } = to_unit;
+                    connect(
+                        other_units_cant_cause_cancels_before,
+                        other_units_cant_cause_cancels_before.ty().HdlNone(),
+                    );
                     connect(unit_outputs_ready, true);
                     connect(cancel_all.data, HdlNone());
                     #[hdl]

crates/cpu/src/unit/alu_branch.rs

@@ -1260,6 +1260,7 @@ pub fn alu_branch(
         enqueue,
         inputs_ready,
         is_no_longer_speculative: _, // we don't care about being speculative for these instructions
+        other_units_cant_cause_cancels_before: _, // we don't care about other instructions being able to cause cancels
         cant_cause_cancel,
         output_ready,
         finish_cause_cancel,

crates/cpu/src/unit/load_store.rs

@@ -11,9 +11,10 @@ use crate::{
     next_pc::{CallStackOp, SimValueDefault},
     register::{PRegFlags, PRegValue},
     rename_execute_retire::{
-        ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp, UnitEnqueue,
-        UnitFinishCauseCancel, UnitInputsReady, UnitMOpCantCauseCancel,
-        UnitMOpIsNoLongerSpeculative, UnitOutputReady,
+        ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
+        UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel, UnitInputsReady,
+        UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
+        UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady,
     },
     unit::{DynUnit, DynUnitWrapper, RenamedMOpFilter, UnitIO, UnitKind, UnitMOp, UnitTrait},
 };
@@ -53,6 +54,8 @@ pub struct DCacheStart<C: PhantomConstGet<CpuConfig>> {
 }
 
 #[hdl]
+/// All errors here cause asynchronous error interrupts, so anything requiring precise exceptions (e.g. page
+/// faults) must happen before the D-cache.
 pub enum DCacheFinishStatus {
     /// The operation finished successfully
     Success,
@@ -116,7 +119,7 @@ pub struct LoadStoreToDCacheInterface<C: PhantomConstGet<CpuConfig>> {
     /// Operations started through `start` must maintain sequential consistency -- so earlier operations
     /// can't appear to have happened after later operations.
     pub start: ReadyValid<DCacheStart<C>>,
-    /// operations must finish in the same order they started.
+    /// Operations must finish in the same order they started.
     #[hdl(flip)]
     pub finish: ReadyValid<DCacheFinish<C>>,
     /// It's valid for `start_speculative_load.ready` to be `false` at any time (or even always)
@@ -200,11 +203,10 @@ struct Op<C: PhantomConstCpuConfig> {
     pc: SimValue<UInt<64>>,
     size_in_bytes: u8,
     mop: SimValue<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
-    /// earlier instructions can cause a cancel, so this instruction is still speculative.
-    /// not to be confused with this instruction being able to cause a cancel.
-    is_speculative: bool,
+    other_units_cant_cause_cancels_before: bool,
     src_values: Option<[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN]>,
     dest_value: Option<SimValue<TraceAsString<PRegValue>>>,
+    caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
     sent_cant_cause_cancel: bool,
     sent_output_ready: bool,
     state: OpState,
@@ -218,15 +220,16 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Op<C> {
             pc,
             size_in_bytes,
             mop,
-            is_speculative,
+            other_units_cant_cause_cancels_before,
             src_values,
             dest_value,
+            caused_cancel,
             sent_cant_cause_cancel,
             sent_output_ready,
             state,
         } = self;
-        if *is_speculative {
-            f.write_str("(s)")?;
+        if *other_units_cant_cause_cancels_before {
+            f.write_str("(occcb)")?;
         }
         if *sent_cant_cause_cancel {
             f.write_str("(sccc)")?;
@@ -234,6 +237,18 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Op<C> {
         if *sent_output_ready {
             f.write_str("(sor)")?;
         }
+        if let Some(caused_cancel) = caused_cancel {
+            #[hdl(sim)]
+            let UnitCausedCancel::<_> {
+                start_at_pc,
+                cancel_after_retire,
+                config: _,
+            } = caused_cancel;
+            write!(
+                f,
+                "(caused_cancel start_at_pc={start_at_pc},cancel_after_retire={cancel_after_retire})"
+            )?;
+        }
         write!(
             f,
             "({state}) id={id:?} pc={pc:?} sz={size_in_bytes}: {mop:?}"
@@ -262,9 +277,10 @@ impl<C: PhantomConstCpuConfig> Op<C> {
             pc,
             size_in_bytes,
             mop,
-            is_speculative: true,
+            other_units_cant_cause_cancels_before: false,
             src_values: None,
             dest_value: None,
+            caused_cancel: None,
             sent_cant_cause_cancel: false,
             sent_output_ready: false,
             state: OpState::InputNotReady,
@@ -299,10 +315,7 @@ impl<C: PhantomConstCpuConfig> Op<C> {
             LoadStoreMOp::<_, _>::Store(mop) => self.access_range_helper(&mop.load_store_common),
         }
     }
-    fn can_cause_cancel(&self) -> bool {
-        if self.is_speculative {
-            return true;
-        }
+    fn can_cause_async_error(&self) -> bool {
         match self.state {
             OpState::InputNotReady
             | OpState::StartedSpeculativeLoad
@@ -312,6 +325,15 @@ impl<C: PhantomConstCpuConfig> Op<C> {
             }
         }
     }
+    fn can_cause_cancel(&self) -> bool {
+        match self.state {
+            OpState::InputNotReady
+            | OpState::StartedSpeculativeLoad
+            | OpState::FinishedSpeculativeLoad
+            | OpState::StartedLoadStore => true,
+            OpState::FinishedLoadStore => self.dest_value.is_none(),
+        }
+    }
 }
 
 #[hdl(get(|c| c.rob_size.get().next_power_of_two()))]
@@ -324,18 +346,27 @@ type PhantomConstUnitIndex = PhantomConst<usize>;
 pub struct LoadStoreDebugState<C: PhantomConstGet<CpuConfig>> {
     global_state: GlobalState,
     ops: ArrayType<TraceAsString<OpDebugState>, OpsDebugLen<C>>,
+    async_error: Bool,
     canceling: Bool,
     config: C,
     unit_index: PhantomConstUnitIndex,
     filter: LoadStoreFilter,
 }
 
+#[derive(Debug)]
+struct AsyncErrorData<C: PhantomConstCpuConfig> {
+    caused_cancel: SimValue<UnitCausedCancel<C>>,
+    caused_async_error_id: SimValue<MOpId>,
+}
+
 #[derive(Debug)]
 struct LoadStoreState<C: PhantomConstCpuConfig> {
     global_state: SimValue<GlobalState>,
     ops: VecDeque<Op<C>>,
     d_cache_start: Option<SimValue<DCacheStart<C>>>,
     d_cache_start_speculative_load: Option<SimValue<DCacheStartSpeculativeLoad<C>>>,
+    async_error: bool,
+    async_error_data: Option<AsyncErrorData<C>>,
     canceling: bool,
     config: C,
     unit_index: usize,
@@ -349,6 +380,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             ops: VecDeque::new(),
             d_cache_start: None,
             d_cache_start_speculative_load: None,
+            async_error: false,
+            async_error_data: None,
             canceling: false,
             config,
             unit_index,
@@ -364,6 +397,9 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             d_cache_start: _,
             // not included in debug state since it's identical to `to_d_cache.start_speculative_load.data`
             d_cache_start_speculative_load: _,
+            async_error,
+            // always None by this point
+            async_error_data: _,
             canceling,
             config,
             unit_index,
@@ -378,21 +414,26 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
         LoadStoreDebugState::<_> {
             global_state,
             ops,
+            async_error,
             canceling,
             config,
             unit_index: PhantomConst::new_sized(unit_index),
             filter,
         }
     }
+    fn try_op_by_id(&mut self, id: &<MOpId as Type>::SimValue) -> Option<&mut Op<C>> {
+        self.ops.iter_mut().find(|op| *op.id == *id)
+    }
     #[track_caller]
     fn op_by_id(&mut self, id: &<MOpId as Type>::SimValue) -> &mut Op<C> {
-        match self.ops.iter_mut().find(|op| *op.id == *id) {
+        match self.try_op_by_id(id) {
             Some(op) => op,
             None => panic!("can't find load_store Op with id {id:?}"),
         }
     }
     fn from_execute_enqueue_ready(&self) -> bool {
         !self.canceling
+            && !self.async_error
             && self.ops.len() < self.config.get().unit_max_in_flight(self.unit_index).get()
     }
     #[hdl]
@@ -439,14 +480,28 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
     ) {
         #[hdl(sim)]
         let UnitMOpIsNoLongerSpeculative::<_> { id, config: _ } = is_no_longer_speculative;
-        self.op_by_id(&id).is_speculative = false;
+        self.op_by_id(&id).other_units_cant_cause_cancels_before = true;
+    }
+    #[hdl]
+    fn from_execute_other_units_cant_cause_cancels_before(
+        &mut self,
+        other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
+    ) {
+        #[hdl(sim)]
+        let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
+            other_units_cant_cause_cancels_before;
+        self.op_by_id(&id).other_units_cant_cause_cancels_before = true;
     }
     #[hdl]
     fn from_execute_cant_cause_cancel(&self) -> Option<SimValue<UnitMOpCantCauseCancel<C>>> {
-        if self.canceling {
+        if self.canceling || self.async_error {
             return None;
         }
-        for op in &self.ops {
+        let can_cause_async_error = self.ops.iter().any(|op| op.can_cause_async_error());
+        for (index, op) in self.ops.iter().enumerate() {
+            if can_cause_async_error && index + 1 == self.ops.len() {
+                return None;
+            }
             if op.sent_cant_cause_cancel || op.can_cause_cancel() {
                 continue;
             }
@@ -518,14 +573,15 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             pc: _,
             size_in_bytes: _,
             mop: _,
-            is_speculative,
+            other_units_cant_cause_cancels_before,
             src_values: _,
-            dest_value,
+            dest_value: _,
+            caused_cancel,
             sent_cant_cause_cancel: _,
             sent_output_ready,
             state,
         } = self.ops.front()?;
-        if *is_speculative {
+        if !*other_units_cant_cause_cancels_before {
             return None;
         }
         let retval_ty = UnitFinishCauseCancel[self.config];
@@ -533,7 +589,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             OpState::InputNotReady => None,
             OpState::StartedSpeculativeLoad => None,
             OpState::FinishedSpeculativeLoad => {
-                if *sent_output_ready {
+                if *sent_output_ready || caused_cancel.is_some() {
                     // TODO: handle when some other CPU stores to the same cache line before the speculative
                     // load sends UnitFinishCauseCancel -- that needs to make the load cause a cancel so it
                     // can be redone with the correct data. That enforces sequential consistency.
@@ -541,8 +597,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                         #[hdl(sim)]
                         UnitFinishCauseCancel::<_> {
                             id,
-                            caused_cancel: #[hdl(sim)]
-                            (retval_ty.caused_cancel).HdlNone(),
+                            caused_cancel: caused_cancel
+                                .into_sim_value_with_type(retval_ty.caused_cancel),
                             config: self.config,
                         },
                     )
@@ -552,16 +608,13 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             }
             OpState::StartedLoadStore => None,
             OpState::FinishedLoadStore => {
-                if dest_value.is_none() {
-                    todo!("load/store caused error -- need to translate to a cancel");
-                }
-                if *sent_output_ready {
+                if *sent_output_ready || caused_cancel.is_some() {
                     Some(
                         #[hdl(sim)]
                         UnitFinishCauseCancel::<_> {
                             id,
-                            caused_cancel: #[hdl(sim)]
-                            (retval_ty.caused_cancel).HdlNone(),
+                            caused_cancel: caused_cancel
+                                .into_sim_value_with_type(retval_ty.caused_cancel),
                             config: self.config,
                         },
                     )
@@ -630,7 +683,12 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                 };
             }
             DCacheFinishStatus::MemoryError(error) => {
-                todo!("{error:?}")
+                // cause an async error:
+                // mark this instruction as completed so the rename/execute/retire logic will progress to
+                // the instruction we mark as canceled.
+                op.dest_value = Some(PRegValue::zeroed_sim().into_trace_as_string());
+                let id = op.id.clone();
+                self.cause_async_error(error, id);
             }
         }
     }
@@ -694,8 +752,22 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
     }
     #[hdl]
     fn canceling_step(&mut self) {
-        self.d_cache_start = None;
-        self.d_cache_start_speculative_load = None;
+        let LoadStoreState {
+            global_state: _,
+            ops,
+            d_cache_start,
+            d_cache_start_speculative_load,
+            async_error,
+            async_error_data,
+            canceling,
+            config: _,
+            unit_index: _,
+            filter: _,
+        } = self;
+        *async_error = false;
+        *async_error_data = None;
+        *d_cache_start = None;
+        *d_cache_start_speculative_load = None;
         let finished_canceling = |op: &mut Op<_>| match op.state {
             OpState::InputNotReady => true,
             OpState::StartedSpeculativeLoad => false,
@@ -703,9 +775,9 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             OpState::StartedLoadStore => false,
             OpState::FinishedLoadStore => true,
         };
-        while let Some(_) = self.ops.pop_front_if(finished_canceling) {}
-        if self.ops.is_empty() {
-            self.canceling = false;
+        while let Some(_) = ops.pop_front_if(finished_canceling) {}
+        if ops.is_empty() {
+            *canceling = false;
         }
     }
     fn is_cacheable_load(mop: &SimValue<LoadMOp<PRegNum<C>, PRegNum<C>>>) -> bool {
@@ -809,27 +881,80 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
     }
     #[hdl]
     fn step(&mut self) {
-        if self.canceling {
+        let Self {
+            global_state: _,
+            ops,
+            d_cache_start,
+            d_cache_start_speculative_load,
+            async_error,
+            async_error_data,
+            canceling,
+            config,
+            unit_index: _,
+            filter: _,
+        } = self;
+        if *canceling {
             return self.canceling_step();
         }
-        self.d_cache_start = None;
-        self.d_cache_start_speculative_load = None;
+        *d_cache_start = None;
+        *d_cache_start_speculative_load = None;
+        if *async_error {
+            if let Some(AsyncErrorData {
+                caused_cancel,
+                caused_async_error_id,
+            }) = async_error_data.take()
+            {
+                let mut earliest_op_that_can_be_canceled = None;
+                for op in self.ops.iter_mut().rev() {
+                    if op.id == caused_async_error_id {
+                        // must not have instructions enqueued earlier than this one cause a cancel
+                        earliest_op_that_can_be_canceled = Some(op);
+                        break;
+                    }
+                    if op.sent_cant_cause_cancel {
+                        continue;
+                    }
+                    let state = op.state;
+                    if op.can_cause_cancel() {
+                        earliest_op_that_can_be_canceled = Some(op);
+                    }
+                    match state {
+                        OpState::InputNotReady
+                        | OpState::StartedSpeculativeLoad
+                        | OpState::FinishedSpeculativeLoad => {
+                            // no globally visible changes, so we can have earlier instructions cause a cancel
+                        }
+                        OpState::StartedLoadStore | OpState::FinishedLoadStore => {
+                            // changes are already or will be globally visible, so this instruction
+                            // must retire, so we can't cancel earlier instructions.
+                            break;
+                        }
+                    }
+                }
+                let Some(op) = earliest_op_that_can_be_canceled else {
+                    unreachable!();
+                };
+                op.caused_cancel = Some(caused_cancel);
+            }
+            return;
+        }
         let store_queue_capacity = 4; // TODO: make configurable
         struct StoreQueueEntry {
             access_range: AddressRange,
             data: [u8; MAX_LOAD_STORE_SIZE],
         }
         let mut store_queue = Vec::<StoreQueueEntry>::with_capacity(store_queue_capacity);
-        for op in &mut self.ops {
+        for op in ops {
             let access_range = op.access_range();
             let Op {
                 ref id,
                 pc: _,
                 size_in_bytes: _,
                 ref mop,
-                is_speculative,
+                other_units_cant_cause_cancels_before,
                 ref src_values,
                 ref mut dest_value,
+                caused_cancel: _,
                 sent_cant_cause_cancel: _,
                 sent_output_ready: _,
                 ref mut state,
@@ -871,21 +996,23 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                     let mask = std::array::from_fn(|i| i < size.get() as usize);
                     match state {
                         OpState::InputNotReady
-                            if is_speculative && !blocking_store && is_cacheable =>
+                            if !other_units_cant_cause_cancels_before
+                                && !blocking_store
+                                && is_cacheable =>
                         {
-                            self.d_cache_start_speculative_load.get_or_insert_with(|| {
+                            d_cache_start_speculative_load.get_or_insert_with(|| {
                                 #[hdl(sim)]
                                 DCacheStartSpeculativeLoad::<_> {
                                     id,
                                     address,
                                     mask,
-                                    config: self.config,
+                                    config,
                                 }
                             });
                         }
                         OpState::InputNotReady | OpState::FinishedSpeculativeLoad => {
-                            if !is_speculative && dest_value.is_none() {
-                                self.d_cache_start.get_or_insert_with(|| {
+                            if other_units_cant_cause_cancels_before && dest_value.is_none() {
+                                d_cache_start.get_or_insert_with(|| {
                                     #[hdl(sim)]
                                     DCacheStart::<_> {
                                         id,
@@ -896,7 +1023,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                                         ),
                                         address,
                                         data_and_mask: mask.map(|v| v.then_some(0)),
-                                        config: self.config,
+                                        config,
                                     }
                                 });
                             }
@@ -912,9 +1039,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                         pc: _,
                         size_in_bytes: _,
                         mop: _,
-                        is_speculative,
+                        other_units_cant_cause_cancels_before,
                         ref src_values,
                         ref dest_value,
+                        caused_cancel: _,
                         sent_cant_cause_cancel: _,
                         sent_output_ready: _,
                         state,
@@ -939,8 +1067,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                     }
                     match state {
                         OpState::InputNotReady => {
-                            if !is_speculative {
-                                self.d_cache_start.get_or_insert_with(|| {
+                            if other_units_cant_cause_cancels_before {
+                                d_cache_start.get_or_insert_with(|| {
                                     #[hdl(sim)]
                                     DCacheStart::<_> {
                                         id,
@@ -951,7 +1079,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
                                         ),
                                         address,
                                         data_and_mask,
-                                        config: self.config,
+                                        config,
                                     }
                                 });
                             }
@@ -966,8 +1094,36 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
             }
         }
     }
+    #[hdl]
+    fn cause_async_error(
+        &mut self,
+        error: SimValue<MemoryOperationErrorKind>,
+        caused_async_error_id: SimValue<MOpId>,
+    ) {
+        if self.async_error {
+            return; // we're already handling an error, ignore the new error
+        }
+        self.async_error = true;
+        // TODO: set other registers properly for an interrupt
+        let start_at_pc = #[hdl(sim)]
+        match error {
+            MemoryOperationErrorKind::Generic => MACHINE_CHECK_INTERRUPT_PC,
+        };
+        let caused_cancel = #[hdl(sim)]
+        UnitCausedCancel::<_> {
+            start_at_pc,
+            cancel_after_retire: true,
+            config: self.config,
+        };
+        self.async_error_data = Some(AsyncErrorData {
+            caused_cancel,
+            caused_async_error_id,
+        });
+    }
 }
 
+pub const MACHINE_CHECK_INTERRUPT_PC: u64 = 0x0000_0000_0000_0200;
+
 #[hdl]
 async fn load_store_impl(
     config: PhantomConst<CpuConfig>,
@@ -988,6 +1144,7 @@ async fn load_store_impl(
                 enqueue,
                 inputs_ready: _,
                 is_no_longer_speculative: _,
+                other_units_cant_cause_cancels_before: _,
                 cant_cause_cancel,
                 output_ready,
                 finish_cause_cancel,
@@ -1042,6 +1199,7 @@ async fn load_store_impl(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
+                other_units_cant_cause_cancels_before,
                 cant_cause_cancel,
                 output_ready,
                 finish_cause_cancel,
@@ -1066,6 +1224,15 @@ async fn load_store_impl(
             {
                 state.from_execute_is_no_longer_speculative(is_no_longer_speculative);
             }
+            #[hdl(sim)]
+            if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                .await
+            {
+                state.from_execute_other_units_cant_cause_cancels_before(
+                    other_units_cant_cause_cancels_before,
+                );
+            }
             if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                 #[hdl(sim)]
                 if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
@@ -1221,6 +1388,7 @@ pub fn load_store(
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
+                        other_units_cant_cause_cancels_before: _,
                         cant_cause_cancel,
                         output_ready,
                         finish_cause_cancel,

crates/cpu/tests/expected/units_formal_power_isa_add_sim.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14589,6 +14596,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -15210,6 +15224,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15421,6 +15442,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -17229,6 +17257,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -23167,6 +23198,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -23577,6 +23611,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -23656,6 +23693,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_0.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14164,6 +14171,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14785,6 +14799,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -14996,6 +15017,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16636,6 +16664,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22489,6 +22520,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22899,6 +22933,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22978,6 +23015,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_1.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14203,6 +14210,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14824,6 +14838,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15035,6 +15056,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16638,6 +16666,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22488,6 +22519,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22898,6 +22932,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22977,6 +23014,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_2.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14203,6 +14210,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14824,6 +14838,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15035,6 +15056,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16638,6 +16666,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22488,6 +22519,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22898,6 +22932,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22977,6 +23014,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_3.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14181,6 +14188,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14802,6 +14816,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15013,6 +15034,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16660,6 +16688,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22508,6 +22539,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22918,6 +22952,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22997,6 +23034,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_4.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14202,6 +14209,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14823,6 +14837,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15034,6 +15055,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16637,6 +16665,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22486,6 +22517,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22896,6 +22930,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22975,6 +23012,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_5.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14202,6 +14209,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -14823,6 +14837,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15034,6 +15055,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -16629,6 +16657,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -22478,6 +22509,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -22888,6 +22922,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -22967,6 +23004,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/expected/units_formal_power_isa_paddi_sim.vcd

@@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
 $var string 1 l(Ah_ config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 ;aq90 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 l{J$] id $end
+$var string 1 Nix(+ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 zJgj& \$tag $end
 $scope struct HdlSome $end
@@ -14589,6 +14596,13 @@ $var wire 16 ~w1^> id $end
 $var string 1 %RV:C config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #<FC> \$tag $end
+$scope struct HdlSome $end
+$var wire 16 z[},} id $end
+$var string 1 UnOX` config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 &KsMs \$tag $end
 $scope struct HdlSome $end
@@ -15210,6 +15224,13 @@ $var wire 16 [hMz. id $end
 $var string 1 }!B*c config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 #5`o3 \$tag $end
+$scope struct HdlSome $end
+$var wire 16 gqr/^ id $end
+$var string 1 `haz~ config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 0X}tP \$tag $end
 $scope struct HdlSome $end
@@ -15421,6 +15442,13 @@ $var wire 16 ']_J^ id $end
 $var string 1 lUFJg config $end
 $upscope $end
 $upscope $end
+$scope struct other_units_cant_cause_cancels_before $end
+$var string 1 \1bYR \$tag $end
+$scope struct HdlSome $end
+$var wire 16 }r^J= id $end
+$var string 1 ,1@Ze config $end
+$upscope $end
+$upscope $end
 $scope struct cant_cause_cancel $end
 $var string 1 `A[2< \$tag $end
 $scope struct HdlSome $end
@@ -17229,6 +17257,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) qtNE\
 b0 gDmEE
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
+sHdlNone\x20(0) ;aq90
+b0 l{J$]
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
 sHdlNone\x20(0) zJgj&
 b0 <~R^D
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
@@ -23167,6 +23198,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) Vy"k\
 b0 ~w1^>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
+sHdlNone\x20(0) #<FC>
+b0 z[},}
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
 sHdlNone\x20(0) &KsMs
 b0 |]Zt8
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
@@ -23577,6 +23611,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) 05GRu
 b0 [hMz.
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
+sHdlNone\x20(0) #5`o3
+b0 gqr/^
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
 sHdlNone\x20(0) 0X}tP
 b0 vxQK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
@@ -23656,6 +23693,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
 sHdlNone\x20(0) C2t\%
 b0 ']_J^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
+sHdlNone\x20(0) \1bYR
+b0 }r^J=
+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
 sHdlNone\x20(0) `A[2<
 b0 19hEe
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC

crates/cpu/tests/load_store_unit.rs

@@ -7,12 +7,14 @@ use cpu::{
         COMMON_MOP_SRC_LEN, CommonMOp, LoadMOp, LoadStoreCommonMOp, LoadStoreConversion,
         LoadStoreMOp, LoadStoreWidth, MOpTrait, PRegNum, StoreMOp, UnitNum, UnitOutRegNum,
     },
+    main_memory_and_io::MemoryOperationErrorKind,
     next_pc::CallStackOp,
     register::{FlagsMode, PRegFlags, PRegFlagsPowerISA, PRegValue},
     rename_execute_retire::{
         ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
         UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel, UnitInputsReady,
-        UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady,
+        UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
+        UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady,
     },
     unit::{
         UnitKind,
@@ -20,7 +22,7 @@ use cpu::{
             DCacheFinish, DCacheFinishSpeculativeLoad, DCacheFinishStatus,
             DCacheForeignWriteToCacheLine, DCacheOpKind, DCacheOpKindLoad, DCacheOpKindStore,
             DCacheStart, DCacheStartSpeculativeLoad, LoadStoreToDCacheInterface,
-            MAX_LOAD_STORE_SIZE, load_store,
+            MACHINE_CHECK_INTERRUPT_PC, MAX_LOAD_STORE_SIZE, load_store,
         },
     },
     util::array_vec::ArrayVec,
@@ -821,6 +823,7 @@ struct MockDCacheToLoadStoreTester {
     #[hdl(flip)]
     memory_state_seed: UInt<64>,
     memory_state: MemorySimState,
+    memory_error: Bool,
 }
 
 const LOAD_STORE_QUEUE_SIZE: usize = 16;
@@ -843,6 +846,7 @@ struct MockDCacheDebugState<C: PhantomConstGet<CpuConfig>> {
     cache_line_addresses: Array<TraceAsString<HdlOption<UInt<64>>>, 16>,
     load_store_queue: Array<HdlOption<MockDCacheLoadStoreDebugState<C>>, { LOAD_STORE_QUEUE_SIZE }>,
     speculative_load_queue: Array<HdlOption<DCacheStartSpeculativeLoad<C>>, 3>,
+    memory_error: Bool,
     config: C,
 }
 
@@ -851,6 +855,7 @@ struct MockDCacheState<'a, C: PhantomConstCpuConfig> {
     cache_line_addresses: [Option<u64>; 16],
     load_store_queue: VecDeque<MockDCacheLoadStore<C>>,
     speculative_load_queue: [Option<SimValue<DCacheStartSpeculativeLoad<C>>>; 3],
+    memory_error: bool,
     config: C,
     random_state: &'a RandomState,
 }
@@ -862,6 +867,7 @@ impl<C: PhantomConstCpuConfig> fmt::Debug for MockDCacheState<'_, C> {
             cache_line_addresses,
             load_store_queue,
             speculative_load_queue,
+            memory_error,
             config,
             random_state: _,
         } = self;
@@ -870,6 +876,7 @@ impl<C: PhantomConstCpuConfig> fmt::Debug for MockDCacheState<'_, C> {
             .field("cache_line_addresses", cache_line_addresses)
             .field("load_store_queue", load_store_queue)
             .field("speculative_load_queue", speculative_load_queue)
+            .field("memory_error", memory_error)
             .field("config", config)
             .finish_non_exhaustive()
     }
@@ -883,6 +890,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
             cache_line_addresses: [None; _],
             load_store_queue: VecDeque::with_capacity(LOAD_STORE_QUEUE_SIZE),
             speculative_load_queue: [const { None }; _],
+            memory_error: false,
             config,
             random_state,
         }
@@ -894,6 +902,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
             ref cache_line_addresses,
             ref load_store_queue,
             ref speculative_load_queue,
+            memory_error,
             config,
             random_state: _,
         } = *self;
@@ -915,6 +924,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
             load_store_queue: load_store_queue.into_sim_value_with_type(ret_ty.load_store_queue),
             speculative_load_queue: speculative_load_queue
                 .into_sim_value_with_type(ret_ty.speculative_load_queue),
+            memory_error,
             config,
         }
     }
@@ -1141,17 +1151,25 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
                 config: _,
             } = op;
             let address = address.as_int();
+            *finish_status = Some(
+                if self.random_state.random_u64(Self::RANDOM_KEY) % (1 << 6) == 0 {
+                    self.memory_error = true;
+                    #[hdl(sim)]
+                    DCacheFinishStatus.MemoryError(
+                        #[hdl(sim)]
+                        MemoryOperationErrorKind.Generic(),
+                    )
+                } else {
+                    #[hdl(sim)]
+                    DCacheFinishStatus.Success()
+                },
+            );
             #[hdl(sim)]
             match &kind {
                 DCacheOpKind::Load(kind) => {
                     #[hdl(sim)]
                     let DCacheOpKindLoad { is_cacheable } = kind;
                     update_cache_for_access(address, data_and_mask, **is_cacheable);
-                    // TODO: simulate random memory errors
-                    *finish_status = Some(
-                        #[hdl(sim)]
-                        DCacheFinishStatus.Success(),
-                    );
                     let data = self.memory_state.load(
                         address,
                         std::array::from_fn(|i| {
@@ -1174,11 +1192,6 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
                     #[hdl(sim)]
                     let DCacheOpKindStore { is_cacheable } = kind;
                     update_cache_for_access(address, data_and_mask, **is_cacheable);
-                    // TODO: simulate random memory errors
-                    *finish_status = Some(
-                        #[hdl(sim)]
-                        DCacheFinishStatus.Success(),
-                    );
                     self.memory_state.store(
                         address,
                         std::array::from_fn(|i| {
@@ -1242,9 +1255,11 @@ async fn mock_d_cache_impl<C: PhantomConstCpuConfig>(
             let MockDCacheToLoadStoreTester {
                 memory_state_seed: _,
                 memory_state,
+                memory_error,
             } = to_load_store_tester;
             sim.write(memory_state, state.memory_state.to_sim_value())
                 .await;
+            sim.write(memory_error, state.memory_error).await;
         }
         sim.write(debug_state, state.debug_state()).await;
         sim.wait_for_clock_edge(cd.clk).await;
@@ -1253,6 +1268,7 @@ async fn mock_d_cache_impl<C: PhantomConstCpuConfig>(
             let MockDCacheToLoadStoreTester {
                 memory_state_seed,
                 memory_state: _,
+                memory_error: _,
             } = to_load_store_tester;
             let memory_state_seed = sim.read_past(memory_state_seed, cd.clk).await.as_int();
             if state.memory_state.io_random_seed != memory_state_seed {
@@ -1372,9 +1388,11 @@ fn mock_d_cache(config: PhantomConst<CpuConfig>) {
                     let MockDCacheToLoadStoreTester {
                         memory_state_seed: _,
                         memory_state,
+                        memory_error,
                     } = to_load_store_tester;
                     sim.write(memory_state, MemoryState::default().to_sim_value())
                         .await;
+                    sim.write(memory_error, false).await;
                     sim.write(debug_state, state.debug_state()).await;
                     state
                 },
@@ -1395,13 +1413,29 @@ fn mock_d_cache(config: PhantomConst<CpuConfig>) {
     );
 }
 
+#[derive(Clone, Copy, Debug)]
+enum InsnCausedCancel {
+    Retry,
+    AsyncError,
+}
+
+impl InsnCausedCancel {
+    fn cancel_after_retire(self) -> bool {
+        match self {
+            Self::Retry => false,
+            Self::AsyncError => true,
+        }
+    }
+}
+
 #[derive(Clone, Debug)]
 struct Insn<C: PhantomConstCpuConfig> {
     cycles_after_start_to_cancel: Option<usize>,
     mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
     sent_inputs_ready: bool,
     sent_is_no_longer_speculative: bool,
-    caused_cancel_before_retire: bool,
+    sent_other_units_cant_cause_cancels_before: bool,
+    caused_cancel: Option<InsnCausedCancel>,
     cant_cause_cancel: bool,
     output: Option<SimValue<TraceAsString<PRegValue>>>,
     finished: bool,
@@ -1415,7 +1449,8 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Insn<C> {
             mop,
             sent_inputs_ready,
             sent_is_no_longer_speculative,
-            caused_cancel_before_retire,
+            sent_other_units_cant_cause_cancels_before,
+            caused_cancel,
             cant_cause_cancel,
             output,
             finished,
@@ -1432,8 +1467,14 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Insn<C> {
         if *sent_is_no_longer_speculative {
             write!(f, " (sinls)")?;
         }
-        if *caused_cancel_before_retire {
-            write!(f, " (ccbr)")?;
+        if *sent_other_units_cant_cause_cancels_before {
+            write!(f, " (socccb)")?;
+        }
+        if let Some(caused_cancel) = caused_cancel {
+            match caused_cancel {
+                InsnCausedCancel::Retry => write!(f, " (caused_cancel=retry)")?,
+                InsnCausedCancel::AsyncError => write!(f, " (caused_cancel=async_error)")?,
+            }
         }
         if *cant_cause_cancel {
             write!(f, " (ccc)")?;
@@ -1482,6 +1523,8 @@ struct LoadStoreTesterDebugState<C: PhantomConstGet<CpuConfig>> {
     canceling: Bool,
     expected_memory_state: MemorySimState,
     matches_expected_memory_state: Bool,
+    d_cache_caused_memory_error: Bool,
+    retired_async_error: Bool,
     config: C,
 }
 
@@ -1493,6 +1536,8 @@ struct LoadStoreTesterState<C: PhantomConstCpuConfig> {
     canceling: bool,
     expected_memory_state: MemoryState,
     matches_expected_memory_state: bool,
+    d_cache_caused_memory_error: bool,
+    retired_async_error: bool,
     config: C,
     load_store_unit_index: usize,
     input_unit_index: usize,
@@ -1612,7 +1657,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 },
                 sent_inputs_ready: false,
                 sent_is_no_longer_speculative: false,
-                caused_cancel_before_retire: false,
+                sent_other_units_cant_cause_cancels_before: false,
+                caused_cancel: None,
                 cant_cause_cancel: false,
                 output: None,
                 finished: false,
@@ -1626,6 +1672,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
             canceling: false,
             expected_memory_state: MemoryState::empty(random_state.random_u64(Self::RANDOM_KEY)),
             matches_expected_memory_state: false,
+            d_cache_caused_memory_error: false,
+            retired_async_error: false,
             config,
             load_store_unit_index,
             input_unit_index,
@@ -1739,6 +1787,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
             canceling,
             ref expected_memory_state,
             matches_expected_memory_state,
+            d_cache_caused_memory_error,
+            retired_async_error,
             config,
             load_store_unit_index: _,
             input_unit_index: _,
@@ -1759,6 +1809,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
             canceling,
             expected_memory_state: expected_memory_state.to_sim_value(),
             matches_expected_memory_state,
+            d_cache_caused_memory_error,
+            retired_async_error,
             config,
         }
     }
@@ -1782,7 +1834,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
     }
     #[hdl]
     fn to_load_store_enqueue(&self) -> Option<SimValue<UnitEnqueue<C>>> {
-        if self.canceling {
+        if self.canceling || self.retired_async_error {
             return None;
         }
         if self.enqueued.end < self.insns.len() {
@@ -1859,7 +1911,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 mop,
                 sent_inputs_ready,
                 sent_is_no_longer_speculative: _,
-                caused_cancel_before_retire: _,
+                sent_other_units_cant_cause_cancels_before: _,
+                caused_cancel: _,
                 cant_cause_cancel: _,
                 output: _,
                 finished: _,
@@ -1929,7 +1982,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 mop,
                 sent_inputs_ready: _,
                 sent_is_no_longer_speculative,
-                caused_cancel_before_retire,
+                sent_other_units_cant_cause_cancels_before: _,
+                caused_cancel,
                 cant_cause_cancel,
                 output: _,
                 finished,
@@ -1949,7 +2003,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
             if *cant_cause_cancel {
                 continue;
             }
-            if *finished && !*caused_cancel_before_retire {
+            if *finished && caused_cancel.is_none() {
                 continue;
             }
             break;
@@ -1964,8 +2018,60 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
         if self.canceling {
             return;
         }
-        Self::insn_by_id(&mut self.insns, &is_no_longer_speculative.id)
-            .sent_is_no_longer_speculative = true;
+        let insn = Self::insn_by_id(&mut self.insns, &is_no_longer_speculative.id);
+        insn.sent_is_no_longer_speculative = true;
+    }
+    #[hdl]
+    fn to_load_store_other_units_cant_cause_cancels_before(
+        &self,
+    ) -> Option<SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>> {
+        if self.canceling {
+            return None;
+        }
+        let mut is_speculative = false;
+        for insn in &self.insns[self.enqueued.clone()] {
+            let Insn {
+                cycles_after_start_to_cancel,
+                mop,
+                sent_inputs_ready: _,
+                sent_is_no_longer_speculative: _,
+                sent_other_units_cant_cause_cancels_before,
+                caused_cancel,
+                cant_cause_cancel,
+                output: _,
+                finished,
+            } = insn;
+            if cycles_after_start_to_cancel.is_some() {
+                return None;
+            }
+            if !*sent_other_units_cant_cause_cancels_before && is_speculative {
+                return Some(
+                    #[hdl(sim)]
+                    UnitMOpOtherUnitsCantCauseCancelsBefore::<_> {
+                        id: &mop.id,
+                        config: self.config,
+                    },
+                );
+            }
+            if *finished && caused_cancel.is_none() {
+                continue;
+            }
+            if !*cant_cause_cancel {
+                is_speculative = true;
+            }
+        }
+        None
+    }
+    #[hdl]
+    fn handle_to_load_store_other_units_cant_cause_cancels_before(
+        &mut self,
+        other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
+    ) {
+        if self.canceling {
+            return;
+        }
+        Self::insn_by_id(&mut self.insns, &other_units_cant_cause_cancels_before.id)
+            .sent_other_units_cant_cause_cancels_before = true;
     }
     #[hdl]
     fn handle_to_load_store_cant_cause_cancel(
@@ -2026,9 +2132,14 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 cancel_after_retire,
                 config: _,
             } = caused_cancel;
-            assert_eq!(start_at_pc, insn.mop.pc);
-            assert_eq!(*cancel_after_retire, false);
-            insn.caused_cancel_before_retire = true;
+            let caused_cancel = if start_at_pc.as_int() == MACHINE_CHECK_INTERRUPT_PC {
+                InsnCausedCancel::AsyncError
+            } else {
+                assert_eq!(start_at_pc, insn.mop.pc);
+                InsnCausedCancel::Retry
+            };
+            assert_eq!(*cancel_after_retire, caused_cancel.cancel_after_retire());
+            insn.caused_cancel = Some(caused_cancel);
         }
         insn.finished = true;
     }
@@ -2041,13 +2152,24 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
         self.canceling = false;
     }
     #[hdl]
-    fn handle_from_mock_d_cache_memory_state(&mut self, memory_state: SimValue<MemorySimState>) {
+    fn handle_from_mock_d_cache_memory_state(
+        &mut self,
+        memory_state: SimValue<MemorySimState>,
+        memory_error: bool,
+    ) {
+        self.d_cache_caused_memory_error = memory_error;
         self.matches_expected_memory_state =
             self.expected_memory_state == MemoryState::from_sim_value(&memory_state);
     }
     #[hdl]
     fn test_passed(&self) -> bool {
-        self.retired.end >= self.insns.len()
+        if self.retired_async_error {
+            self.d_cache_caused_memory_error
+        } else if self.retired.end >= self.insns.len() {
+            !self.d_cache_caused_memory_error && self.matches_expected_memory_state
+        } else {
+            false
+        }
     }
     #[hdl]
     fn cancel_all_unretired(&mut self) {
@@ -2059,6 +2181,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
             canceling,
             expected_memory_state: _,
             matches_expected_memory_state: _,
+            d_cache_caused_memory_error: _,
+            retired_async_error: _,
             config: _,
             load_store_unit_index: _,
             input_unit_index: _,
@@ -2071,14 +2195,16 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 mop: _,
                 sent_inputs_ready,
                 sent_is_no_longer_speculative,
-                caused_cancel_before_retire,
+                sent_other_units_cant_cause_cancels_before,
+                caused_cancel,
                 cant_cause_cancel,
                 output,
                 finished,
             } = insn;
             *sent_inputs_ready = false;
             *sent_is_no_longer_speculative = false;
-            *caused_cancel_before_retire = false;
+            *sent_other_units_cant_cause_cancels_before = false;
+            *caused_cancel = None;
             *cant_cause_cancel = false;
             *output = None;
             *finished = false;
@@ -2095,7 +2221,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 mop: _,
                 sent_inputs_ready: _,
                 sent_is_no_longer_speculative: _,
-                caused_cancel_before_retire: _,
+                sent_other_units_cant_cause_cancels_before: _,
+                caused_cancel: _,
                 cant_cause_cancel: _,
                 output: _,
                 finished: _,
@@ -2110,7 +2237,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 mop: _,
                 sent_inputs_ready: _,
                 sent_is_no_longer_speculative: _,
-                caused_cancel_before_retire,
+                sent_other_units_cant_cause_cancels_before: _,
+                caused_cancel,
                 cant_cause_cancel: _,
                 output: _,
                 finished,
@@ -2119,7 +2247,14 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
                 *cycles_after_start_to_cancel = None;
                 return self.cancel_all_unretired();
             }
-            if *caused_cancel_before_retire {
+            if let Some(caused_cancel) = caused_cancel {
+                if caused_cancel.cancel_after_retire() {
+                    self.retired.end += 1;
+                }
+                match caused_cancel {
+                    InsnCausedCancel::Retry => {}
+                    InsnCausedCancel::AsyncError => self.retired_async_error = true,
+                }
                 return self.cancel_all_unretired();
             }
             if *finished {
@@ -2149,6 +2284,7 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
+                other_units_cant_cause_cancels_before,
                 cant_cause_cancel: _,
                 output_ready: _,
                 finish_cause_cancel: _,
@@ -2168,6 +2304,11 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
                     state.to_load_store_is_no_longer_speculative(),
                 )
                 .await;
+                sim.write(
+                    other_units_cant_cause_cancels_before,
+                    state.to_load_store_other_units_cant_cause_cancels_before(),
+                )
+                .await;
             } else {
                 sim.write(enqueue.data, enqueue.ty().data.HdlNone()).await;
                 sim.write(inputs_ready, inputs_ready.ty().HdlNone()).await;
@@ -2176,6 +2317,11 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
                     is_no_longer_speculative.ty().HdlNone(),
                 )
                 .await;
+                sim.write(
+                    other_units_cant_cause_cancels_before,
+                    other_units_cant_cause_cancels_before.ty().HdlNone(),
+                )
+                .await;
             }
             sim.write(cancel_all.data, state.to_load_store_cancel_all())
                 .await;
@@ -2190,6 +2336,7 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
+                other_units_cant_cause_cancels_before,
                 cant_cause_cancel,
                 output_ready,
                 finish_cause_cancel,
@@ -2213,6 +2360,15 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
             {
                 state.handle_to_load_store_is_no_longer_speculative(is_no_longer_speculative);
             }
+            #[hdl(sim)]
+            if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                .await
+            {
+                state.handle_to_load_store_other_units_cant_cause_cancels_before(
+                    other_units_cant_cause_cancels_before,
+                );
+            }
             if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                 #[hdl(sim)]
                 if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
@@ -2243,8 +2399,12 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
             let MockDCacheToLoadStoreTester {
                 memory_state_seed: _,
                 memory_state,
+                memory_error,
             } = from_mock_d_cache;
-            state.handle_from_mock_d_cache_memory_state(sim.read_past(memory_state, cd.clk).await);
+            state.handle_from_mock_d_cache_memory_state(
+                sim.read_past(memory_state, cd.clk).await,
+                sim.read_past_bool(memory_error, cd.clk).await,
+            );
         }
         state.step();
     }
@@ -2293,6 +2453,7 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
                         enqueue,
                         inputs_ready,
                         is_no_longer_speculative,
+                        other_units_cant_cause_cancels_before,
                         cant_cause_cancel: _,
                         output_ready: _,
                         finish_cause_cancel: _,
@@ -2318,6 +2479,11 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
                         is_no_longer_speculative.ty().HdlNone(),
                     )
                     .await;
+                    sim.write(
+                        other_units_cant_cause_cancels_before,
+                        other_units_cant_cause_cancels_before.ty().HdlNone(),
+                    )
+                    .await;
                     sim.write(unit_outputs_ready, false).await;
                     sim.write(cancel_all.data, HdlNone()).await;
                     sim.write(test_passed, false).await;
@@ -2326,6 +2492,7 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
                     let MockDCacheToLoadStoreTester {
                         memory_state_seed,
                         memory_state: _,
+                        memory_error: _,
                     } = from_mock_d_cache;
                     sim.write(
                         memory_state_seed,

crates/cpu/tests/rename_execute_retire.rs

@@ -20,8 +20,9 @@ use cpu::{
         ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
         PostDecodeOutputInterface, RenamedMOp, RetireToNextPcInterface,
         RetireToNextPcInterfaceInner, UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel,
-        UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady,
-        rename_execute_retire, to_unit_interfaces::ExecuteToUnitInterfaces,
+        UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
+        UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady, rename_execute_retire,
+        to_unit_interfaces::ExecuteToUnitInterfaces,
     },
     unit::{UnitKind, UnitMOp},
     util::array_vec::ArrayVec,
@@ -2468,6 +2469,14 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
         _is_no_longer_speculative: SimValue<UnitMOpIsNoLongerSpeculative<C>>,
     ) {
     }
+    #[hdl]
+    fn handle_mop_other_units_cant_cause_cancels_before(
+        &mut self,
+        _other_units_cant_cause_cancels_before: SimValue<
+            UnitMOpOtherUnitsCantCauseCancelsBefore<C>,
+        >,
+    ) {
+    }
     fn cancel_all(&mut self) {
         let Self {
             global_state: _,
@@ -2508,6 +2517,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
+                        other_units_cant_cause_cancels_before: _,
                         cant_cause_cancel,
                         output_ready,
                         finish_cause_cancel,
@@ -2586,6 +2596,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
+                    other_units_cant_cause_cancels_before: _,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -2612,6 +2623,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                     enqueue: _, // we ignore enqueues since we don't need to track order for these instructions
                     inputs_ready,
                     is_no_longer_speculative,
+                    other_units_cant_cause_cancels_before,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -2630,6 +2642,15 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                 {
                     state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
                 }
+                #[hdl(sim)]
+                if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                    .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                    .await
+                {
+                    state.handle_mop_other_units_cant_cause_cancels_before(
+                        other_units_cant_cause_cancels_before,
+                    );
+                }
                 if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                     #[hdl(sim)]
                     if let HdlSome(cant_cause_cancel) =
@@ -2680,6 +2701,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
             enqueue,
             inputs_ready: _,
             is_no_longer_speculative: _,
+            other_units_cant_cause_cancels_before: _,
             cant_cause_cancel,
             output_ready,
             finish_cause_cancel,
@@ -2724,6 +2746,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative: _, // we don't care about being speculative for these instructions
+                other_units_cant_cause_cancels_before: _, // we don't care about being speculative for these instructions
                 cant_cause_cancel,
                 output_ready,
                 finish_cause_cancel,
@@ -2984,6 +3007,23 @@ impl<C: PhantomConstCpuConfig> MockL2RegFileUnitState<C> {
         } = self.op_by_id_mut(&id);
     }
     #[hdl]
+    fn handle_mop_other_units_cant_cause_cancels_before(
+        &mut self,
+        other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
+    ) {
+        #[hdl(sim)]
+        let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
+            other_units_cant_cause_cancels_before;
+        let MockL2RegFileOp {
+            mop: _,
+            src_values: _,
+            dest_value: _,
+            sent_cant_cause_cancel: _,
+            sent_output_ready: _,
+            config: _,
+        } = self.op_by_id_mut(&id);
+    }
+    #[hdl]
     fn peek_mop_cant_cause_cancel(&self) -> SimValue<HdlOption<UnitMOpCantCauseCancel<C>>> {
         let ret_ty = HdlOption[UnitMOpCantCauseCancel[self.config]];
         for MockL2RegFileOp {
@@ -3160,6 +3200,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
+                        other_units_cant_cause_cancels_before: _,
                         cant_cause_cancel,
                         output_ready,
                         finish_cause_cancel,
@@ -3222,6 +3263,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
+                    other_units_cant_cause_cancels_before: _,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -3246,6 +3288,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
                     enqueue,
                     inputs_ready,
                     is_no_longer_speculative,
+                    other_units_cant_cause_cancels_before,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -3270,6 +3313,15 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
                 {
                     state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
                 }
+                #[hdl(sim)]
+                if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                    .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                    .await
+                {
+                    state.handle_mop_other_units_cant_cause_cancels_before(
+                        other_units_cant_cause_cancels_before,
+                    );
+                }
                 if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                     #[hdl(sim)]
                     if let HdlSome(cant_cause_cancel) =
@@ -3631,6 +3683,27 @@ impl<'a, C: PhantomConstCpuConfig> MockLoadStoreUnitState<'a, C> {
         *is_speculative = false;
     }
     #[hdl]
+    fn handle_mop_other_units_cant_cause_cancels_before(
+        &mut self,
+        other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
+    ) {
+        #[hdl(sim)]
+        let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
+            other_units_cant_cause_cancels_before;
+        let MockLoadStoreOp {
+            mop: _,
+            is_speculative: _,
+            src_values: _,
+            dest_value: _,
+            cycles_left: _,
+            ran_nonspeculatively: _,
+            sent_cant_cause_cancel: _,
+            sent_output_ready: _,
+            config: _,
+        } = self.op_by_id_mut(&id);
+        // TODO
+    }
+    #[hdl]
     fn peek_mop_cant_cause_cancel(&self) -> SimValue<HdlOption<UnitMOpCantCauseCancel<C>>> {
         let ret_ty = HdlOption[UnitMOpCantCauseCancel[self.config]];
         for MockLoadStoreOp {
@@ -3843,6 +3916,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
+                        other_units_cant_cause_cancels_before: _,
                         cant_cause_cancel,
                         output_ready,
                         finish_cause_cancel,
@@ -3923,6 +3997,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
+                    other_units_cant_cause_cancels_before: _,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -3949,6 +4024,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
                     enqueue,
                     inputs_ready,
                     is_no_longer_speculative,
+                    other_units_cant_cause_cancels_before,
                     cant_cause_cancel,
                     output_ready,
                     finish_cause_cancel,
@@ -3972,6 +4048,15 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
                 {
                     state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
                 }
+                #[hdl(sim)]
+                if let HdlSome(other_units_cant_cause_cancels_before) = sim
+                    .read_past(other_units_cant_cause_cancels_before, cd.clk)
+                    .await
+                {
+                    state.handle_mop_other_units_cant_cause_cancels_before(
+                        other_units_cant_cause_cancels_before,
+                    );
+                }
                 if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
                     #[hdl(sim)]
                     if let HdlSome(cant_cause_cancel) =