diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs
index 28368e9..30d8fd0 100644
--- a/crates/cpu/src/config.rs
+++ b/crates/cpu/src/config.rs
@@ -1,8 +1,11 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    instruction::{PRegNum, UnitNum, UnitOutRegNum, CONST_ZERO_UNIT_NUM},
-    unit::{unit_base::UnitForwardingInfo, UnitCancelInput, UnitKind, UnitMOp, UnitOutputWrite},
+    instruction::{MOpTrait, PRegNum, UnitNum, UnitOutRegNum, CONST_ZERO_UNIT_NUM},
+    unit::{
+        unit_base::{UnitForwardingInfo, UnitToRegAlloc},
+        UnitCancelInput, UnitKind, UnitMOp, UnitOutputWrite,
+    },
 };
 use fayalite::prelude::*;
 use std::num::NonZeroUsize;
@@ -95,4 +98,20 @@ impl CpuConfig {
             .max_in_flight
             .unwrap_or(self.default_unit_max_in_flight)
     }
+    pub fn unit_to_reg_alloc<
+        MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>, SrcRegWidth = DynSize>,
+        ExtraOut: Type,
+    >(
+        &self,
+        mop_ty: MOp,
+        extra_out_ty: ExtraOut,
+    ) -> UnitToRegAlloc<MOp, ExtraOut, DynSize, DynSize, DynSize> {
+        assert_eq!(
+            mop_ty.dest_reg_ty(),
+            self.unit_out_reg_num(),
+            "inconsistent types",
+        );
+        UnitToRegAlloc[mop_ty][extra_out_ty][self.unit_num_width()][self.out_reg_num_width]
+            [self.non_const_unit_nums().len()]
+    }
 }
diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs
index befab9a..587fb0b 100644
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@@ -1,7 +1,11 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{unit::UnitMOp, util::range_u32_len};
-use fayalite::{expr::ops::ArrayLiteral, intern::Interned, prelude::*};
+use fayalite::{
+    expr::ops::{ArrayLiteral, ExprPartialEq},
+    intern::Interned,
+    prelude::*,
+};
 use std::{fmt, marker::PhantomData, ops::Range};
 
 pub mod power_isa;
@@ -12,10 +16,26 @@ pub trait MOpTrait: Type {
     type SrcRegWidth: Size;
     fn dest_reg_ty(self) -> Self::DestReg;
     fn dest_reg(input: impl ToExpr<Type = Self>) -> Expr<Self::DestReg>;
+    fn src_reg_width(self) -> <Self::SrcRegWidth as Size>::SizeType;
+    fn src_reg_ty(self) -> UIntType<Self::SrcRegWidth> {
+        UInt[self.src_reg_width()]
+    }
+    fn src_regs_ty(self) -> Array<UIntType<Self::SrcRegWidth>, { COMMON_MOP_SRC_LEN }> {
+        Array[self.src_reg_ty()][ConstUsize::<{ COMMON_MOP_SRC_LEN }>]
+    }
     fn for_each_src_reg(
         input: impl ToExpr<Type = Self>,
         f: &mut impl FnMut(Expr<UIntType<Self::SrcRegWidth>>, usize),
     );
+    fn connect_src_regs(
+        input: impl ToExpr<Type = Self>,
+        src_regs: impl ToExpr<Type = Array<UIntType<Self::SrcRegWidth>, { COMMON_MOP_SRC_LEN }>>,
+    ) {
+        let src_regs = src_regs.to_expr();
+        Self::for_each_src_reg(input.to_expr(), &mut |src_reg, index| {
+            connect(src_regs[index], src_reg);
+        });
+    }
     fn mapped_ty<NewDestReg: Type, NewSrcRegWidth: Size>(
         self,
         new_dest_reg: NewDestReg,
@@ -67,6 +87,9 @@ impl<T: CommonMOpTrait> MOpTrait for T {
     fn dest_reg(input: impl ToExpr<Type = Self>) -> Expr<Self::DestReg> {
         T::common_mop(input).dest
     }
+    fn src_reg_width(self) -> <Self::SrcRegWidth as Size>::SizeType {
+        self.common_mop_ty().src.element().width
+    }
     fn for_each_src_reg(
         input: impl ToExpr<Type = Self>,
         f: &mut impl FnMut(Expr<UIntType<Self::SrcRegWidth>>, usize),
@@ -129,13 +152,23 @@ pub enum OutputIntegerMode {
     SignExt8,
 }
 
+impl ExprPartialEq<Self> for OutputIntegerMode {
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+    }
+}
+
 pub const MOP_IMM_WIDTH: usize = 34;
 pub const MOP_MIN_REG_WIDTH: usize = 8;
 pub const COMMON_MOP_SRC_LEN: usize = 3;
 pub const COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM: usize = 2;
 pub const COMMON_MOP_IMM_LOW_WIDTH: usize = CommonMOpWithMaxSrcCount::IMM_WIDTH - 1;
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct CommonMOp<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
     pub prefix_pad: UIntType<PrefixPad>,
     pub dest: DestReg,
@@ -181,7 +214,7 @@ impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct CommonMOpImmParts<ImmInSrcCount: Size> {
     // fields must be in this exact order
     pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>,
@@ -410,6 +443,9 @@ macro_rules! mop_enum {
                 }
                 dest_reg
             }
+            fn src_reg_width(self) -> <Self::SrcRegWidth as Size>::SizeType {
+                self.$FirstVariant.src_reg_width()
+            }
             #[hdl]
             fn for_each_src_reg(
                 input: impl ToExpr<Type = Self>,
@@ -458,7 +494,7 @@ pub(crate) use mop_enum;
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> AluCommonMOp<NewDestReg, NewSrcRegWidth, SrcCount>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct AluCommonMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
         pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, SrcCount>,
@@ -468,7 +504,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> AddSubMOp<NewDestReg, NewSrcRegWidth, SrcCount>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct AddSubMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
         pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount>,
@@ -481,7 +517,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> LogicalMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct LogicalMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, ConstUsize<2>>,
@@ -491,7 +527,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> BranchMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct BranchMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, ConstUsize<2>>,
@@ -510,7 +546,7 @@ mop_enum! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> ReadL2RegMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct ReadL2RegMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub common: CommonMOp<ConstUsize<1>, DestReg, SrcRegWidth, ConstUsize<0>>,
@@ -519,7 +555,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> WriteL2RegMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct WriteL2RegMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub common: CommonMOp<ConstUsize<1>, DestReg, SrcRegWidth, ConstUsize<1>>,
@@ -536,7 +572,7 @@ mop_enum! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> LoadStoreCommonMOp<NewDestReg, NewSrcRegWidth, SrcCount>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct LoadStoreCommonMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
         pub common: CommonMOp<ConstUsize<1>, DestReg, SrcRegWidth, SrcCount>,
@@ -545,7 +581,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> LoadMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct LoadMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub load_store_common: LoadStoreCommonMOp<DestReg, SrcRegWidth, ConstUsize<1>>,
@@ -554,7 +590,7 @@ common_mop_struct! {
 
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> StoreMOp<NewDestReg, NewSrcRegWidth>)]
-    #[hdl]
+    #[hdl(cmp_eq)]
     pub struct StoreMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
         pub load_store_common: LoadStoreCommonMOp<DestReg, SrcRegWidth, ConstUsize<2>>,
@@ -569,7 +605,7 @@ mop_enum! {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// there may be more than one unit of a given kind, so UnitNum is not the same as UnitKind.
 /// zero is used for built-in constants, such as the zero register
 pub struct UnitNum<Width: Size> {
@@ -617,12 +653,12 @@ impl<Width: Size> UnitNum<Width> {
 
 pub const CONST_ZERO_UNIT_NUM: usize = 0;
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct UnitOutRegNum<Width: Size> {
     pub value: UIntType<Width>,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// Physical Register Number -- registers in the CPU's backend
 pub struct PRegNum<UnitNumWidth: Size, OutRegNumWidth: Size> {
     pub unit_num: UnitNum<UnitNumWidth>,
@@ -643,7 +679,7 @@ impl<UnitNumWidth: Size, OutRegNumWidth: Size> PRegNum<UnitNumWidth, OutRegNumWi
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// µOp Register Number -- register in a micro-operation before register renaming
 #[doc(alias = "UOpRegNum")] // help you find it in the docs if you mis-spell it
 #[doc(alias = "\u{B5}OpRegNum")] // micro sign
@@ -681,7 +717,7 @@ impl MOpRegNum {
         Self::CONST_ZERO_REG_NUM + 1..Self::SPECIAL_REG_NUMS.start;
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// all the registers this instruction will write to, they are all renamed to the same physical register.
 pub struct MOpDestReg {
     /// some instructions have multiple destination registers, e.g. x86 div
diff --git a/crates/cpu/src/instruction/power_isa.rs b/crates/cpu/src/instruction/power_isa.rs
index 9ad2679..de9b47c 100644
--- a/crates/cpu/src/instruction/power_isa.rs
+++ b/crates/cpu/src/instruction/power_isa.rs
@@ -4,22 +4,22 @@ use crate::{instruction::MOpRegNum, util::range_u32_nth_or_panic};
 use fayalite::prelude::*;
 use std::ops::Range;
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PowerIsaRegNum {
     pub value: UInt<5>,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PowerIsaFRegNum {
     pub value: UInt<5>,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PowerIsaCrFieldNum {
     pub value: UInt<3>,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PowerIsaCrBitNum {
     pub cr_field: PowerIsaCrFieldNum,
     pub bit_in_field: UInt<2>,
diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs
index 529d9a5..4ac357f 100644
--- a/crates/cpu/src/reg_alloc.rs
+++ b/crates/cpu/src/reg_alloc.rs
@@ -311,7 +311,7 @@ pub fn reg_alloc(config: &CpuConfig) {
             SourceLocation::caller(),
         );
         connect(dyn_unit.cd(unit), cd);
-        let unit_input_insn = dyn_unit.input_insn(unit);
+        let unit_to_reg_alloc = dyn_unit.unit_to_reg_alloc(unit);
         // TODO: handle assigning multiple instructions to a unit at a time
         let assign_to_unit_at_once = NonZeroUsize::new(1).unwrap();
         // TODO: handle retiring multiple instructions from a unit at a time
@@ -333,8 +333,8 @@ pub fn reg_alloc(config: &CpuConfig) {
         );
         connect(unit_free_regs_tracker.alloc_out[0].ready, false);
         connect(
-            unit_input_insn.data,
-            Expr::ty(unit_input_insn).data.HdlNone(),
+            unit_to_reg_alloc.input_insn.data,
+            Expr::ty(unit_to_reg_alloc.input_insn).data.HdlNone(),
         );
         for fetch_index in 0..config.fetch_width.get() {
             #[hdl]
@@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                 connect(available_units[fetch_index][unit_index], false);
             }
             #[hdl]
-            if !unit_input_insn.ready {
+            if !unit_to_reg_alloc.input_insn.ready {
                 // must come after to override connects in loops above
                 connect(available_units[fetch_index][unit_index], false);
             }
@@ -356,11 +356,11 @@ pub fn reg_alloc(config: &CpuConfig) {
                     if let HdlSome(renamed_mop) =
                         HdlOption::and_then(renamed_mops[fetch_index], |v| dyn_unit.extract_mop(v))
                     {
-                        connect(unit_input_insn.data, HdlSome(renamed_mop));
+                        connect(unit_to_reg_alloc.input_insn.data, HdlSome(renamed_mop));
                     } else {
                         connect(
-                            unit_input_insn.data,
-                            HdlSome(Expr::ty(unit_input_insn).data.HdlSome.uninit()),
+                            unit_to_reg_alloc.input_insn.data,
+                            HdlSome(Expr::ty(unit_to_reg_alloc.input_insn).data.HdlSome.uninit()),
                         );
                         // FIXME: add hdl_assert(cd.clk, false.to_expr(), "");
                     }
@@ -387,7 +387,7 @@ pub fn reg_alloc(config: &CpuConfig) {
         }
         // TODO: connect outputs to other units
         connect(
-            dyn_unit.unit_forwarding_info(unit),
+            unit_to_reg_alloc.unit_forwarding_info,
             #[hdl]
             UnitForwardingInfo::<_, _, _> {
                 unit_output_writes: repeat(
@@ -397,10 +397,9 @@ pub fn reg_alloc(config: &CpuConfig) {
                 _phantom: PhantomData,
             },
         );
-        connect(dyn_unit.output(unit).ready, false);
         // TODO: handle cancellation
         connect(
-            dyn_unit.cancel_input(unit).data,
+            unit_to_reg_alloc.cancel_input,
             HdlOption[config.unit_cancel_input()].HdlNone(),
         );
     }
diff --git a/crates/cpu/src/register.rs b/crates/cpu/src/register.rs
index 33b7e5c..7c81395 100644
--- a/crates/cpu/src/register.rs
+++ b/crates/cpu/src/register.rs
@@ -8,7 +8,7 @@ pub enum FlagsMode {
     X86(PRegFlagsX86),
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PRegFlagsPowerISA {}
 
 impl PRegFlagsPowerISA {
@@ -56,7 +56,7 @@ impl PRegFlagsPowerISA {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct PRegFlagsX86 {}
 
 impl PRegFlagsX86 {
@@ -100,7 +100,7 @@ impl PRegFlagsX86 {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// this is *not* the same as any particular ISA's flags register,
 /// on PowerISA it is a combination of some bits from XER with a single 4-bit CR field.
 ///
@@ -138,7 +138,7 @@ impl PRegFlags {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// Unit output register's value -- a combination of an integer/fp register
 /// and flags register and CR field.
 ///
diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs
index e76342b..1be9c65 100644
--- a/crates/cpu/src/unit.rs
+++ b/crates/cpu/src/unit.rs
@@ -7,13 +7,12 @@ use crate::{
         mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, UnitOutRegNum,
     },
     register::PRegValue,
-    unit::unit_base::UnitForwardingInfo,
+    unit::unit_base::UnitToRegAlloc,
 };
 use fayalite::{
     bundle::{Bundle, BundleType},
     intern::{Intern, Interned},
     prelude::*,
-    util::ready_valid::ReadyValid,
 };
 
 pub mod alu_branch;
@@ -143,19 +142,19 @@ all_units! {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct UnitResultCompleted<ExtraOut> {
     pub value: PRegValue,
     pub extra_out: ExtraOut,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct UnitOutputWrite<OutRegNumWidth: Size> {
     pub which: UnitOutRegNum<OutRegNumWidth>,
     pub value: PRegValue,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub struct TrapData {
     // TODO
 }
@@ -166,13 +165,25 @@ pub enum UnitResult<ExtraOut> {
     Trap(TrapData),
 }
 
+impl<ExtraOut: Type> UnitResult<ExtraOut> {
+    pub fn extra_out_ty(self) -> ExtraOut {
+        self.Completed.extra_out
+    }
+}
+
 #[hdl]
 pub struct UnitOutput<OutRegNumWidth: Size, ExtraOut> {
     pub which: UnitOutRegNum<OutRegNumWidth>,
     pub result: UnitResult<ExtraOut>,
 }
 
-#[hdl]
+impl<OutRegNumWidth: Size, ExtraOut: Type> UnitOutput<OutRegNumWidth, ExtraOut> {
+    pub fn extra_out_ty(self) -> ExtraOut {
+        self.result.extra_out_ty()
+    }
+}
+
+#[hdl(cmp_eq)]
 pub struct UnitCancelInput<OutRegNumWidth: Size> {
     pub which: UnitOutRegNum<OutRegNumWidth>,
 }
@@ -197,19 +208,10 @@ pub trait UnitTrait:
 
     fn module(&self) -> Interned<Module<Self::Type>>;
 
-    fn input_insn(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<Self::MOp>>;
-
-    fn cancel_input(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<UnitCancelInput<DynSize>>>;
-
-    fn unit_forwarding_info(
+    fn unit_to_reg_alloc(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitForwardingInfo<DynSize, DynSize, DynSize>>;
-
-    fn output(
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<ReadyValid<UnitOutput<DynSize, Self::ExtraOut>>>;
+    ) -> Expr<UnitToRegAlloc<Self::MOp, Self::ExtraOut, DynSize, DynSize, DynSize>>;
 
     fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain>;
 
@@ -266,26 +268,11 @@ impl UnitTrait for DynUnit {
         self.unit.module()
     }
 
-    fn input_insn(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<Self::MOp>> {
-        self.unit.input_insn(this)
-    }
-
-    fn cancel_input(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<UnitCancelInput<DynSize>>> {
-        self.unit.cancel_input(this)
-    }
-
-    fn unit_forwarding_info(
+    fn unit_to_reg_alloc(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitForwardingInfo<DynSize, DynSize, DynSize>> {
-        self.unit.unit_forwarding_info(this)
-    }
-
-    fn output(
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<ReadyValid<UnitOutput<DynSize, Self::ExtraOut>>> {
-        self.unit.output(this)
+    ) -> Expr<UnitToRegAlloc<Self::MOp, Self::ExtraOut, DynSize, DynSize, DynSize>> {
+        self.unit.unit_to_reg_alloc(this)
     }
 
     fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
@@ -332,26 +319,13 @@ impl<T: UnitTrait + Clone + std::hash::Hash + Eq> UnitTrait for DynUnitWrapper<T
         self.0.module().canonical().intern_sized()
     }
 
-    fn input_insn(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<Self::MOp>> {
-        Expr::from_bundle(Expr::as_bundle(self.0.input_insn(Expr::from_bundle(this))))
-    }
-
-    fn cancel_input(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<UnitCancelInput<DynSize>>> {
-        self.0.cancel_input(Expr::from_bundle(this))
-    }
-
-    fn unit_forwarding_info(
+    fn unit_to_reg_alloc(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitForwardingInfo<DynSize, DynSize, DynSize>> {
-        self.0.unit_forwarding_info(Expr::from_bundle(this))
-    }
-
-    fn output(
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<ReadyValid<UnitOutput<DynSize, Self::ExtraOut>>> {
-        Expr::from_bundle(Expr::as_bundle(self.0.output(Expr::from_bundle(this))))
+    ) -> Expr<UnitToRegAlloc<Self::MOp, Self::ExtraOut, DynSize, DynSize, DynSize>> {
+        Expr::from_bundle(Expr::as_bundle(
+            self.0.unit_to_reg_alloc(Expr::from_bundle(this)),
+        ))
     }
 
     fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs
index 1a553d4..2334ef5 100644
--- a/crates/cpu/src/unit/alu_branch.rs
+++ b/crates/cpu/src/unit/alu_branch.rs
@@ -5,14 +5,13 @@ use crate::{
     config::CpuConfig,
     instruction::{AluBranchMOp, UnitOutRegNum},
     unit::{
-        unit_base::{unit_base, UnitForwardingInfo},
-        DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitMOp, UnitOutput, UnitTrait,
+        unit_base::{unit_base, UnitToRegAlloc},
+        DynUnit, DynUnitWrapper, UnitKind, UnitMOp, UnitTrait,
     },
 };
 use fayalite::{
     intern::{Intern, Interned},
     prelude::*,
-    util::ready_valid::ReadyValid,
 };
 
 #[hdl_module]
@@ -20,30 +19,30 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
     #[hdl]
     let cd: ClockDomain = m.input();
     #[hdl]
-    let input_insn: ReadyValid<AluBranchMOp<UnitOutRegNum<DynSize>, DynSize>> =
-        m.input(ReadyValid[AluBranchMOp[config.unit_out_reg_num()][config.p_reg_num_width()]]);
-    #[hdl]
-    let unit_forwarding_info: UnitForwardingInfo<DynSize, DynSize, DynSize> =
-        m.input(config.unit_forwarding_info());
-    #[hdl]
-    let cancel_input: ReadyValid<UnitCancelInput<DynSize>> =
-        m.input(ReadyValid[config.unit_cancel_input()]);
-    #[hdl]
-    let output: ReadyValid<UnitOutput<DynSize, ()>> =
-        m.output(ReadyValid[UnitOutput[config.out_reg_num_width][()]]);
+    let unit_to_reg_alloc: UnitToRegAlloc<
+        AluBranchMOp<UnitOutRegNum<DynSize>, DynSize>,
+        (),
+        DynSize,
+        DynSize,
+        DynSize,
+    > = m.output(config.unit_to_reg_alloc(
+        AluBranchMOp[config.unit_out_reg_num()][config.p_reg_num_width()],
+        (),
+    ));
     #[hdl]
     let unit_base = instance(unit_base(
         config,
         unit_index,
-        Expr::ty(input_insn).data.HdlSome,
+        Expr::ty(unit_to_reg_alloc).input_insn.data.HdlSome,
+        (),
     ));
-    connect(unit_base.input_insn, input_insn);
+    connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
     connect(unit_base.cd, cd);
-    connect(unit_base.unit_forwarding_info, unit_forwarding_info);
-    connect(unit_base.cancel_input, cancel_input);
-    // TODO: finish
-    connect(unit_base.ready_mop.ready, true);
-    connect(output.data, Expr::ty(output.data).HdlNone());
+    connect(unit_base.execute_start.ready, true); // TODO: finish
+    connect(
+        unit_base.execute_end,
+        Expr::ty(unit_base.execute_end).HdlNone(),
+    ); // TODO: finish
 }
 
 #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
@@ -75,7 +74,7 @@ impl UnitTrait for AluBranch {
     }
 
     fn mop_ty(&self) -> Self::MOp {
-        self.module.io_ty().input_insn.data.HdlSome
+        self.module.io_ty().unit_to_reg_alloc.mop_ty()
     }
 
     fn unit_kind(&self) -> UnitKind {
@@ -93,26 +92,11 @@ impl UnitTrait for AluBranch {
         self.module
     }
 
-    fn input_insn(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<Self::MOp>> {
-        this.input_insn
-    }
-
-    fn cancel_input(&self, this: Expr<Self::Type>) -> Expr<ReadyValid<UnitCancelInput<DynSize>>> {
-        this.cancel_input
-    }
-
-    fn unit_forwarding_info(
+    fn unit_to_reg_alloc(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitForwardingInfo<DynSize, DynSize, DynSize>> {
-        this.unit_forwarding_info
-    }
-
-    fn output(
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<ReadyValid<UnitOutput<DynSize, Self::ExtraOut>>> {
-        this.output
+    ) -> Expr<UnitToRegAlloc<Self::MOp, Self::ExtraOut, DynSize, DynSize, DynSize>> {
+        this.unit_to_reg_alloc
     }
 
     fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
diff --git a/crates/cpu/src/unit/unit_base.rs b/crates/cpu/src/unit/unit_base.rs
index f6a1627..ea921f1 100644
--- a/crates/cpu/src/unit/unit_base.rs
+++ b/crates/cpu/src/unit/unit_base.rs
@@ -3,9 +3,9 @@
 
 use crate::{
     config::CpuConfig,
-    instruction::{MOpTrait, UnitOutRegNum, COMMON_MOP_SRC_LEN},
+    instruction::{MOpTrait, PRegNum, UnitOutRegNum, COMMON_MOP_SRC_LEN},
     register::PRegValue,
-    unit::{UnitCancelInput, UnitOutputWrite},
+    unit::{UnitCancelInput, UnitOutput, UnitOutputWrite},
     util::tree_reduce::tree_reduce,
 };
 use fayalite::{module::wire_with_loc, prelude::*, ty::StaticType, util::ready_valid::ReadyValid};
@@ -18,113 +18,439 @@ pub struct UnitForwardingInfo<UnitNumWidth: Size, OutRegNumWidth: Size, UnitCoun
 }
 
 #[hdl]
-pub struct ReadyMOp<MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>>> {
+pub struct UnitToRegAlloc<
+    MOp: Type,
+    ExtraOut: Type,
+    UnitNumWidth: Size,
+    OutRegNumWidth: Size,
+    UnitCount: Size,
+> {
+    #[hdl(flip)]
+    pub unit_forwarding_info: UnitForwardingInfo<UnitNumWidth, OutRegNumWidth, UnitCount>,
+    #[hdl(flip)]
+    pub input_insn: ReadyValid<MOp>,
+    #[hdl(flip)]
+    pub cancel_input: HdlOption<UnitCancelInput<OutRegNumWidth>>,
+    pub output: HdlOption<UnitOutput<OutRegNumWidth, ExtraOut>>,
+}
+
+impl<MOp: Type, ExtraOut: Type, UnitNumWidth: Size, OutRegNumWidth: Size, UnitCount: Size>
+    UnitToRegAlloc<MOp, ExtraOut, UnitNumWidth, OutRegNumWidth, UnitCount>
+{
+    pub fn mop_ty(self) -> MOp {
+        self.input_insn.data.HdlSome
+    }
+    pub fn extra_out_ty(self) -> ExtraOut {
+        self.output.HdlSome.extra_out_ty()
+    }
+}
+
+#[hdl]
+pub struct ExecuteStart<MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>>> {
     pub mop: MOp,
     pub src_values: Array<PRegValue, { COMMON_MOP_SRC_LEN }>,
 }
 
 #[hdl]
-struct InFlightOp<MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>>> {
-    pub mop: MOp,
-    pub src_values: Array<HdlOption<PRegValue>, { COMMON_MOP_SRC_LEN }>,
+pub struct ExecuteEnd<OutRegNumWidth: Size, ExtraOut> {
+    pub unit_output: UnitOutput<OutRegNumWidth, ExtraOut>,
+}
+
+#[hdl]
+enum InFlightOpState {
+    Ready,
+    Running,
+    CanceledAndRunning,
+}
+
+impl InFlightOpState {
+    fn ready_next_state(canceling: bool, starting: bool, ending: bool) -> Expr<HdlOption<Self>> {
+        match (canceling, starting, ending) {
+            (false, false, _) => HdlSome(InFlightOpState.Ready()),
+            (false, true, false) => HdlSome(InFlightOpState.Running()),
+            (false, true, true) => HdlNone(),
+            (true, false, _) => HdlNone(),
+            (true, true, false) => HdlSome(InFlightOpState.CanceledAndRunning()),
+            (true, true, true) => HdlNone(),
+        }
+    }
+    fn running_next_state(canceling: bool, _starting: bool, ending: bool) -> Expr<HdlOption<Self>> {
+        match (canceling, ending) {
+            (false, false) => HdlSome(InFlightOpState.Running()),
+            (false, true) => HdlNone(),
+            (true, false) => HdlSome(InFlightOpState.CanceledAndRunning()),
+            (true, true) => HdlNone(),
+        }
+    }
+    fn canceled_and_running_next_state(
+        _canceling: bool,
+        _starting: bool,
+        ending: bool,
+    ) -> Expr<HdlOption<Self>> {
+        if ending {
+            HdlNone()
+        } else {
+            HdlSome(InFlightOpState.CanceledAndRunning())
+        }
+    }
+    /// FIXME: this is working around #[hdl] match not supporting matching values inside structs yet
+    #[hdl]
+    fn connect_next_state(
+        canceling: Expr<Bool>,
+        starting: Expr<Bool>,
+        ending: Expr<Bool>,
+        next_state_fn: fn(canceling: bool, starting: bool, ending: bool) -> Expr<HdlOption<Self>>,
+        next_state: Expr<HdlOption<Self>>,
+    ) {
+        #[hdl]
+        fn recurse<const N: usize>(
+            exprs: &[Expr<Bool>; N],
+            bools: &mut [bool; N],
+            f: &mut impl FnMut(&[bool; N]),
+            arg_index: usize,
+        ) {
+            if arg_index < N {
+                #[hdl]
+                if exprs[arg_index] {
+                    bools[arg_index] = true;
+                    recurse(exprs, bools, f, arg_index + 1);
+                } else {
+                    bools[arg_index] = false;
+                    recurse(exprs, bools, f, arg_index + 1);
+                }
+            } else {
+                f(bools);
+            }
+        }
+        recurse(
+            &[canceling, starting, ending],
+            &mut [false; 3],
+            &mut |&[canceling, starting, ending]| {
+                connect(next_state, next_state_fn(canceling, starting, ending))
+            },
+            0,
+        );
+    }
+}
+
+#[hdl]
+struct InFlightOp<MOp: Type> {
+    state: InFlightOpState,
+    mop: MOp,
+    src_ready_flags: Array<Bool, { COMMON_MOP_SRC_LEN }>,
+}
+
+#[hdl]
+struct InFlightOpsSummary<OpIndexWidth: Size> {
+    empty_op_index: HdlOption<UIntType<OpIndexWidth>>,
+    ready_op_index: HdlOption<UIntType<OpIndexWidth>>,
+}
+
+impl<OpIndexWidth: Size> InFlightOpsSummary<OpIndexWidth> {
+    #[hdl]
+    fn new<MOp: Type>(
+        op_index: usize,
+        op_index_ty: UIntType<OpIndexWidth>,
+        in_flight_op: impl ToExpr<Type = HdlOption<InFlightOp<MOp>>>,
+    ) -> Expr<Self> {
+        let empty_op_index = wire_with_loc(
+            &format!("empty_op_index_{op_index}"),
+            SourceLocation::caller(),
+            HdlOption[op_index_ty],
+        );
+        connect(empty_op_index, HdlOption[op_index_ty].HdlNone());
+        let ready_op_index = wire_with_loc(
+            &format!("ready_op_index_{op_index}"),
+            SourceLocation::caller(),
+            HdlOption[op_index_ty],
+        );
+        connect(ready_op_index, HdlOption[op_index_ty].HdlNone());
+        #[hdl]
+        if let HdlSome(in_flight_op) = in_flight_op {
+            #[hdl]
+            let InFlightOp::<_> {
+                state,
+                mop: _,
+                src_ready_flags,
+            } = in_flight_op;
+            connect(ready_op_index, HdlOption[op_index_ty].HdlNone());
+            #[hdl]
+            match state {
+                InFlightOpState::Ready =>
+                {
+                    #[hdl]
+                    if src_ready_flags.cmp_eq([true; COMMON_MOP_SRC_LEN]) {
+                        connect(ready_op_index, HdlSome(op_index.cast_to(op_index_ty)));
+                    }
+                }
+                InFlightOpState::CanceledAndRunning | InFlightOpState::Running => {}
+            }
+        } else {
+            connect(empty_op_index, HdlSome(op_index.cast_to(op_index_ty)));
+        }
+        #[hdl]
+        InFlightOpsSummary::<_> {
+            empty_op_index,
+            ready_op_index,
+        }
+    }
+    #[hdl]
+    fn combine(l: impl ToExpr<Type = Self>, r: impl ToExpr<Type = Self>) -> Expr<Self> {
+        let l = l.to_expr();
+        let r = r.to_expr();
+        #[hdl]
+        InFlightOpsSummary::<_> {
+            empty_op_index: HdlOption::or(l.empty_op_index, r.empty_op_index),
+            ready_op_index: HdlOption::or(l.ready_op_index, r.ready_op_index),
+        }
+    }
+}
+
+impl InFlightOpsSummary<DynSize> {
+    fn summarize<MOp: Type, MaxInFlight: Size>(
+        in_flight_ops: impl ToExpr<Type = ArrayType<HdlOption<InFlightOp<MOp>>, MaxInFlight>>,
+    ) -> Expr<Self> {
+        let in_flight_ops = in_flight_ops.to_expr();
+        let max_in_flight = Expr::ty(in_flight_ops).len();
+        let index_range = 0..max_in_flight;
+        let index_ty = UInt::range(index_range.clone());
+        tree_reduce(
+            index_range.map(|i| Self::new(i, index_ty, in_flight_ops[i])),
+            Self::combine,
+        )
+        .expect("in_flight_ops is known to have len > 0")
+    }
 }
 
 #[hdl_module]
-pub fn unit_base<MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>>>(
+pub fn unit_base<
+    MOp: Type + MOpTrait<DestReg = UnitOutRegNum<DynSize>, SrcRegWidth = DynSize>,
+    ExtraOut: Type,
+>(
     config: &CpuConfig,
     unit_index: usize,
     mop_ty: MOp,
+    extra_out_ty: ExtraOut,
 ) {
     #[hdl]
     let cd: ClockDomain = m.input();
     #[hdl]
-    let unit_forwarding_info: UnitForwardingInfo<DynSize, DynSize, DynSize> =
-        m.input(config.unit_forwarding_info());
+    let unit_to_reg_alloc: UnitToRegAlloc<MOp, ExtraOut, DynSize, DynSize, DynSize> =
+        m.output(config.unit_to_reg_alloc(mop_ty, extra_out_ty));
     #[hdl]
-    let input_insn: ReadyValid<MOp> = m.input(ReadyValid[mop_ty]);
-    connect(input_insn.ready, false);
+    let execute_start: ReadyValid<ExecuteStart<MOp>> = m.output(ReadyValid[ExecuteStart[mop_ty]]);
     #[hdl]
-    let cancel_input: ReadyValid<UnitCancelInput<DynSize>> =
-        m.input(ReadyValid[config.unit_cancel_input()]);
-    connect(cancel_input.ready, true);
-    #[hdl]
-    let ready_mop: ReadyValid<ReadyMOp<MOp>> = m.output(ReadyValid[ReadyMOp[mop_ty]]);
-    connect(ready_mop.data, Expr::ty(ready_mop.data).HdlNone());
+    let execute_end: HdlOption<ExecuteEnd<DynSize, ExtraOut>> =
+        m.input(HdlOption[ExecuteEnd[config.out_reg_num_width][extra_out_ty]]);
+
+    connect(execute_start.data, Expr::ty(execute_start).data.HdlNone());
+
     let max_in_flight = config.unit_max_in_flight(unit_index).get();
+    let in_flight_op_ty = InFlightOp[mop_ty];
     #[hdl]
-    let in_flight_ops = reg_builder().clock_domain(cd).reset(repeat(
-        HdlOption[InFlightOp[mop_ty]].HdlNone(),
-        max_in_flight,
-    ));
-    let in_flight_op_index_ty = UInt::range(0..max_in_flight);
+    let in_flight_ops = reg_builder()
+        .clock_domain(cd)
+        .reset(repeat(HdlOption[in_flight_op_ty].HdlNone(), max_in_flight));
+
+    let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops);
     #[hdl]
-    let input_index = wire(HdlOption[in_flight_op_index_ty]);
+    let in_flight_ops_summary = wire(Expr::ty(in_flight_ops_summary_value));
+    connect(in_flight_ops_summary, in_flight_ops_summary_value);
+
     connect(
-        input_index,
-        tree_reduce(
-            (0..max_in_flight).map(|i| -> Expr<HdlOption<UInt>> {
-                HdlOption::map(in_flight_ops[i], |_| i.cast_to(in_flight_op_index_ty))
-            }),
-            HdlOption::or,
-        )
-        .expect("max_in_flight is known to be non-zero"),
+        unit_to_reg_alloc.input_insn.ready,
+        HdlOption::is_some(in_flight_ops_summary.empty_op_index),
     );
+    // TODO: connect(execute_start.data, <read_regs>(in_flight_ops_summary.ready_op_index));
+
+    connect(
+        unit_to_reg_alloc.output,
+        Expr::ty(unit_to_reg_alloc.output).HdlNone(),
+    ); // TODO: finish
+
     #[hdl]
-    let input_in_flight_op = wire(HdlOption[InFlightOp[mop_ty]]);
-    connect(input_in_flight_op, Expr::ty(input_in_flight_op).HdlNone());
+    let input_in_flight_op = wire(HdlOption[in_flight_op_ty]);
+    connect(input_in_flight_op, HdlOption[in_flight_op_ty].HdlNone());
     #[hdl]
-    if let HdlSome(mop) = ReadyValid::firing_data(input_insn) {
-        let src_values = wire_with_loc(
-            "input_in_flight_op_src_values",
+    if let HdlSome(mop) = ReadyValid::firing_data(unit_to_reg_alloc.input_insn) {
+        #[hdl]
+        let input_mop_src_regs = wire(mop_ty.src_regs_ty());
+        connect(
+            input_mop_src_regs,
+            repeat(config.p_reg_num().const_zero().cast_to_bits(), ConstUsize),
+        );
+        MOp::connect_src_regs(mop, input_mop_src_regs);
+        let src_ready_flags = wire_with_loc(
+            "input_in_flight_op_src_ready_flags",
             SourceLocation::caller(),
             StaticType::TYPE,
         );
-        connect(
-            src_values,
-            [HdlSome(PRegValue::zeroed()); COMMON_MOP_SRC_LEN],
-        );
-        MOp::for_each_src_reg(mop, &mut |src_reg, src_index| {
+        for src_index in 0..COMMON_MOP_SRC_LEN {
+            connect(
+                src_ready_flags[src_index],
+                config
+                    .p_reg_num()
+                    .const_zero()
+                    .cast_to_bits()
+                    .cmp_eq(input_mop_src_regs[src_index]),
+            );
+        }
+        #[hdl]
+        if unit_to_reg_alloc.cancel_input.cmp_ne(HdlSome(
             #[hdl]
-            if config
-                .p_reg_num()
-                .const_zero()
-                .cast_to_bits()
-                .cmp_ne(src_reg)
-            {
-                connect(src_values[src_index], HdlNone());
-            }
-        });
-        connect(
-            input_in_flight_op,
-            HdlSome(
-                #[hdl]
-                InFlightOp::<_> { mop, src_values },
-            ),
-        );
+            UnitCancelInput::<_> {
+                which: MOp::dest_reg(mop),
+            },
+        )) {
+            connect(
+                input_in_flight_op,
+                HdlSome(
+                    #[hdl]
+                    InFlightOp::<_> {
+                        state: InFlightOpState.Ready(),
+                        mop,
+                        src_ready_flags,
+                    },
+                ),
+            );
+        }
+        #[hdl]
+        if let HdlSome(empty_op_index) = in_flight_ops_summary.empty_op_index {
+            connect(in_flight_ops[empty_op_index], input_in_flight_op);
+        }
     }
+
+    #[hdl]
+    let in_flight_op_next_state = wire(Array[HdlOption[InFlightOpState]][max_in_flight]);
+    #[hdl]
+    let in_flight_op_next_src_ready_flags =
+        wire(Array[in_flight_op_ty.src_ready_flags][max_in_flight]);
+    #[hdl]
+    let in_flight_op_canceling = wire(Array[Bool][max_in_flight]);
+    #[hdl]
+    let in_flight_op_execute_starting = wire(Array[Bool][max_in_flight]);
+    #[hdl]
+    let in_flight_op_execute_ending = wire(Array[Bool][max_in_flight]);
     for in_flight_op_index in 0..max_in_flight {
+        connect(
+            in_flight_op_next_src_ready_flags[in_flight_op_index],
+            [false; COMMON_MOP_SRC_LEN],
+        );
+        connect(in_flight_op_canceling[in_flight_op_index], false);
+        connect(in_flight_op_execute_starting[in_flight_op_index], false);
+        connect(in_flight_op_execute_ending[in_flight_op_index], false);
         #[hdl]
         if let HdlSome(in_flight_op) = in_flight_ops[in_flight_op_index] {
             #[hdl]
-            if let HdlSome(cancel_input) = ReadyValid::firing_data(cancel_input) {
+            let InFlightOp::<_> {
+                state,
+                mop,
+                src_ready_flags,
+            } = in_flight_op;
+            let which = MOp::dest_reg(mop);
+            let src_regs = wire_with_loc(
+                &format!("in_flight_op_src_regs_{in_flight_op_index}"),
+                SourceLocation::caller(),
+                mop_ty.src_regs_ty(),
+            );
+            connect(
+                src_regs,
+                repeat(config.p_reg_num().const_zero().cast_to_bits(), ConstUsize),
+            );
+            MOp::connect_src_regs(mop, src_regs);
+
+            connect(
+                in_flight_op_next_src_ready_flags[in_flight_op_index],
+                src_ready_flags,
+            );
+            let unit_output_writes = unit_to_reg_alloc.unit_forwarding_info.unit_output_writes;
+            for unit_index in 0..Expr::ty(unit_output_writes).len() {
                 #[hdl]
-                let UnitCancelInput::<_> { which } = cancel_input;
-                #[hdl]
-                if which.value.cmp_eq(MOp::dest_reg(in_flight_op.mop).value) {
-                    // TODO: if it needs extra time to cancel (e.g. still in pipeline), handle that here
-                    connect(
-                        in_flight_ops[in_flight_op_index],
-                        HdlOption[InFlightOp[mop_ty]].HdlNone(),
-                    );
+                if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
+                    #[hdl]
+                    let UnitOutputWrite::<_> {
+                        which: unit_out_reg,
+                        value: _,
+                    } = unit_output_write;
+                    let p_reg_num = #[hdl]
+                    PRegNum::<_, _> {
+                        unit_num: config.unit_num().from_index(unit_index),
+                        unit_out_reg,
+                    };
+                    for src_index in 0..COMMON_MOP_SRC_LEN {
+                        #[hdl]
+                        if p_reg_num.cast_to_bits().cmp_eq(src_regs[src_index]) {
+                            connect(
+                                in_flight_op_next_src_ready_flags[in_flight_op_index][src_index],
+                                true,
+                            );
+                        }
+                    }
                 }
             }
-            // TODO: finish
-        } else if let HdlSome(input_index) = input_index {
-            connect(input_insn.ready, true);
+
+            connect(
+                in_flight_op_canceling[in_flight_op_index],
+                unit_to_reg_alloc.cancel_input.cmp_eq(HdlSome(
+                    #[hdl]
+                    UnitCancelInput::<_> { which },
+                )),
+            );
+
             #[hdl]
-            if input_index.cmp_eq(in_flight_op_index) {
-                connect(in_flight_ops[in_flight_op_index], input_in_flight_op);
+            if let HdlSome(execute_end) = execute_end {
+                #[hdl]
+                let ExecuteEnd::<_, _> { unit_output } = execute_end;
+                #[hdl]
+                if which.cmp_eq(unit_output.which) {
+                    connect(in_flight_op_execute_ending[in_flight_op_index], true);
+                }
             }
+            #[hdl]
+            if let HdlSome(execute_start) = ReadyValid::firing_data(execute_start) {
+                #[hdl]
+                if which.cmp_eq(MOp::dest_reg(execute_start.mop)) {
+                    connect(in_flight_op_execute_starting[in_flight_op_index], true);
+                }
+            }
+            let connect_next_state = |f| {
+                InFlightOpState::connect_next_state(
+                    in_flight_op_canceling[in_flight_op_index],
+                    in_flight_op_execute_starting[in_flight_op_index],
+                    in_flight_op_execute_ending[in_flight_op_index],
+                    f,
+                    in_flight_op_next_state[in_flight_op_index],
+                );
+            };
+            #[hdl]
+            match state {
+                InFlightOpState::Ready => connect_next_state(InFlightOpState::ready_next_state),
+                InFlightOpState::Running => connect_next_state(InFlightOpState::running_next_state),
+                InFlightOpState::CanceledAndRunning => {
+                    connect_next_state(InFlightOpState::canceled_and_running_next_state);
+                }
+            }
+            #[hdl]
+            if let HdlSome(state) = in_flight_op_next_state[in_flight_op_index] {
+                connect(
+                    in_flight_ops[in_flight_op_index],
+                    HdlSome(
+                        #[hdl]
+                        InFlightOp::<_> {
+                            state,
+                            mop,
+                            src_ready_flags,
+                        },
+                    ),
+                );
+            } else {
+                connect(
+                    in_flight_ops[in_flight_op_index],
+                    HdlOption[in_flight_op_ty].HdlNone(),
+                );
+            }
+        } else {
+            connect(in_flight_op_next_state[in_flight_op_index], HdlNone());
         }
     }
 }
diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd
index 3f2407e..126bc6a 100644
--- a/crates/cpu/tests/expected/reg_alloc.vcd
+++ b/crates/cpu/tests/expected/reg_alloc.vcd
@@ -600,2530 +600,2530 @@ $scope struct contents $end
 $scope struct \[0] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 |G adj_value $end
+$var reg 2 TP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 _J value $end
+$var reg 4 7S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 }G adj_value $end
+$var reg 2 UP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 `J value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[2] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 ~G adj_value $end
+$var reg 2 VP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 aJ value $end
+$var reg 4 9S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 !H adj_value $end
+$var reg 2 WP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 bJ value $end
+$var reg 4 :S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 "H adj_value $end
+$var reg 2 XP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 cJ value $end
+$var reg 4 ;S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[5] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 #H adj_value $end
+$var reg 2 YP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 dJ value $end
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 $upscope $end
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 $scope struct \[6] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 $H adj_value $end
+$var reg 2 ZP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 eJ value $end
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 $upscope $end
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 $scope struct \[7] $end
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 $scope struct unit_num $end
-$var reg 2 %H adj_value $end
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 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 fJ value $end
+$var reg 4 >S value $end
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 $scope struct \[8] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 &H adj_value $end
+$var reg 2 \P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 gJ value $end
+$var reg 4 ?S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[9] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 'H adj_value $end
+$var reg 2 ]P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 hJ value $end
+$var reg 4 @S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[10] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 (H adj_value $end
+$var reg 2 ^P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 iJ value $end
+$var reg 4 AS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[11] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 )H adj_value $end
+$var reg 2 _P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 jJ value $end
+$var reg 4 BS value $end
 $upscope $end
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 $scope struct \[12] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 *H adj_value $end
+$var reg 2 `P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 kJ value $end
+$var reg 4 CS value $end
 $upscope $end
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 $scope struct \[13] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 +H adj_value $end
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 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 lJ value $end
+$var reg 4 DS value $end
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 $scope struct rename_table_normal_mem $end
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-$var reg 2 ,H adj_value $end
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-$var reg 4 mJ value $end
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 $scope struct rename_table_normal_mem $end
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-$var reg 2 -H adj_value $end
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-$var reg 4 nJ value $end
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-$var reg 2 .H adj_value $end
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-$var reg 4 oJ value $end
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 $scope struct \[17] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 /H adj_value $end
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 $upscope $end
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-$var reg 4 pJ value $end
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 $scope struct \[18] $end
 $scope struct rename_table_normal_mem $end
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-$var reg 2 0H adj_value $end
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-$var reg 2 1H adj_value $end
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 $scope struct \[20] $end
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-$var reg 2 2H adj_value $end
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-$var reg 2 3H adj_value $end
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 $scope struct \[22] $end
 $scope struct rename_table_normal_mem $end
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-$var reg 2 4H adj_value $end
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-$var reg 4 uJ value $end
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 $scope struct \[23] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 5H adj_value $end
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 $upscope $end
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-$var reg 4 vJ value $end
+$var reg 4 NS value $end
 $upscope $end
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 $upscope $end
 $scope struct \[24] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 6H adj_value $end
+$var reg 2 lP adj_value $end
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-$var reg 4 wJ value $end
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 $scope struct \[25] $end
 $scope struct rename_table_normal_mem $end
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-$var reg 2 7H adj_value $end
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-$var reg 4 xJ value $end
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 $upscope $end
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 $scope struct \[26] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 8H adj_value $end
+$var reg 2 nP adj_value $end
 $upscope $end
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-$var reg 4 yJ value $end
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 $scope struct \[27] $end
 $scope struct rename_table_normal_mem $end
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-$var reg 2 9H adj_value $end
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-$var reg 4 zJ value $end
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 $scope struct \[28] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 :H adj_value $end
+$var reg 2 pP adj_value $end
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 $scope struct unit_out_reg $end
-$var reg 4 {J value $end
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 $upscope $end
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 $scope struct \[29] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 ;H adj_value $end
+$var reg 2 qP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 |J value $end
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 $upscope $end
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 $scope struct \[30] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 <H adj_value $end
+$var reg 2 rP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 }J value $end
+$var reg 4 US value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[31] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 =H adj_value $end
+$var reg 2 sP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 ~J value $end
+$var reg 4 VS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[32] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 >H adj_value $end
+$var reg 2 tP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 !K value $end
+$var reg 4 WS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[33] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 ?H adj_value $end
+$var reg 2 uP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 "K value $end
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 $scope struct \[34] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 @H adj_value $end
+$var reg 2 vP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 #K value $end
+$var reg 4 YS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[35] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 AH adj_value $end
+$var reg 2 wP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 $K value $end
+$var reg 4 ZS value $end
 $upscope $end
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 $scope struct \[36] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 BH adj_value $end
+$var reg 2 xP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 %K value $end
+$var reg 4 [S value $end
 $upscope $end
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 $upscope $end
 $scope struct \[37] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 CH adj_value $end
+$var reg 2 yP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 &K value $end
+$var reg 4 \S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[38] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 DH adj_value $end
+$var reg 2 zP adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 'K value $end
+$var reg 4 ]S value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[39] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 EH adj_value $end
+$var reg 2 {P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 (K value $end
+$var reg 4 ^S value $end
 $upscope $end
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 $upscope $end
 $scope struct \[40] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 FH adj_value $end
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 $scope struct unit_out_reg $end
-$var reg 4 )K value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[41] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 GH adj_value $end
+$var reg 2 }P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 *K value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[42] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 HH adj_value $end
+$var reg 2 ~P adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 +K value $end
+$var reg 4 aS value $end
 $upscope $end
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 $upscope $end
 $scope struct \[43] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 IH adj_value $end
+$var reg 2 !Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 ,K value $end
+$var reg 4 bS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[44] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 JH adj_value $end
+$var reg 2 "Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 -K value $end
+$var reg 4 cS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[45] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 KH adj_value $end
+$var reg 2 #Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 .K value $end
+$var reg 4 dS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[46] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 LH adj_value $end
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 $upscope $end
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-$var reg 4 /K value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[47] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 MH adj_value $end
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 $upscope $end
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-$var reg 4 0K value $end
+$var reg 4 fS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[48] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 NH adj_value $end
+$var reg 2 &Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 1K value $end
+$var reg 4 gS value $end
 $upscope $end
 $upscope $end
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 $scope struct \[49] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 OH adj_value $end
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 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 2K value $end
+$var reg 4 hS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[50] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 PH adj_value $end
+$var reg 2 (Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 3K value $end
+$var reg 4 iS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[51] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 QH adj_value $end
+$var reg 2 )Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 4K value $end
+$var reg 4 jS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[52] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 RH adj_value $end
+$var reg 2 *Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 5K value $end
+$var reg 4 kS value $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[53] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 SH adj_value $end
+$var reg 2 +Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 6K value $end
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 $upscope $end
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 $scope struct \[54] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 TH adj_value $end
+$var reg 2 ,Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 7K value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[55] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 UH adj_value $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
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 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 VH adj_value $end
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 $upscope $end
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-$var reg 4 9K value $end
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 $upscope $end
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 $scope struct \[57] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 WH adj_value $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
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 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 XH adj_value $end
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 $upscope $end
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 $scope struct \[59] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 YH adj_value $end
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 $upscope $end
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 $scope struct \[61] $end
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-$var reg 2 [H adj_value $end
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 $upscope $end
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 $scope struct rename_table_normal_mem $end
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-$var reg 2 ]H adj_value $end
+$var reg 2 5Q adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var reg 4 @K value $end
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 $upscope $end
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 $scope struct \[64] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
-$var reg 2 ^H adj_value $end
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 $upscope $end
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-$var reg 4 AK value $end
+$var reg 4 wS value $end
 $upscope $end
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 $scope struct \[65] $end
 $scope struct rename_table_normal_mem $end
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@@ -3296,20 +3296,20 @@ $scope struct contents $end
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@@ -5599,127 +5599,50 @@ $var wire 2 ]+ HdlSome $end
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 $scope struct flags $end
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-$var wire 1 97 pwr_cr_gt_x86_pf $end
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 $upscope $end
@@ -5728,38 +5651,112 @@ $upscope $end
 $scope struct _phantom $end
 $upscope $end
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-$var wire 1 H7 pwr_cr_gt_x86_pf $end
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-$var wire 1 J7 pwr_so $end
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@@ -5770,7 +5767,6 @@ $upscope $end
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@@ -5778,124 +5774,47 @@ $scope struct cd $end
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-$var wire 1 *, pwr_ca32_x86_af $end
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-$var wire 1 /, pwr_cr_eq_x86_zf $end
-$var wire 1 0, pwr_so $end
+$var wire 1 c+ pwr_ca_x86_cf $end
+$var wire 1 d+ pwr_ca32_x86_af $end
+$var wire 1 e+ pwr_ov_x86_of $end
+$var wire 1 f+ pwr_ov32_x86_df $end
+$var wire 1 g+ pwr_cr_lt_x86_sf $end
+$var wire 1 h+ pwr_cr_gt_x86_pf $end
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-$var wire 1 9, pwr_cr_gt_x86_pf $end
-$var wire 1 :, pwr_cr_eq_x86_zf $end
-$var wire 1 ;, pwr_so $end
+$var wire 1 n+ pwr_ca_x86_cf $end
+$var wire 1 o+ pwr_ca32_x86_af $end
+$var wire 1 p+ pwr_ov_x86_of $end
+$var wire 1 q+ pwr_ov32_x86_df $end
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@@ -5904,8 +5823,85 @@ $upscope $end
 $scope struct _phantom $end
 $upscope $end
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 $scope struct data $end
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+$upscope $end
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+$var wire 1 0, invert_carry_out $end
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@@ -5913,29 +5909,26 @@ $var wire 4 =, value $end
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@@ -5946,53 +5939,53 @@ $upscope $end
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 $scope struct flags $end
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@@ -6003,260 +5996,321 @@ $upscope $end
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@@ -6267,184 +6321,199 @@ $upscope $end
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 $upscope $end
-$var wire 25 L- imm_low $end
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@@ -6457,7 +6526,7 @@ $var wire 1 `- pwr_cr_eq_x86_zf $end
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@@ -6470,1223 +6539,1274 @@ $var wire 1 i- pwr_cr_eq_x86_zf $end
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@@ -7758,719 +7878,1329 @@ $upscope $end
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@@ -8479,38 +9209,112 @@ $upscope $end
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@@ -8521,132 +9325,54 @@ $upscope $end
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@@ -8655,38 +9381,112 @@ $upscope $end
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-$var wire 1 W: pwr_cr_gt_x86_pf $end
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@@ -8697,53 +9497,53 @@ $upscope $end
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-$var wire 1 bC pwr_cr_gt_x86_pf $end
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@@ -8754,260 +9554,321 @@ $upscope $end
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@@ -9018,2600 +9879,3353 @@ $upscope $end
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 $upscope $end
 $scope struct free_in $end
 $scope struct \[0] $end
 $scope struct data $end
-$var string 1 ]E \$tag $end
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+$var wire 4 6N HdlSome $end
 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct alloc_out $end
 $scope struct \[0] $end
 $scope struct data $end
-$var string 1 `E \$tag $end
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+$var string 1 8N \$tag $end
+$var wire 4 9N HdlSome $end
 $upscope $end
-$var wire 1 bE ready $end
+$var wire 1 :N ready $end
 $upscope $end
 $upscope $end
 $scope struct allocated_reg $end
-$var reg 1 cE \[0] $end
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-$var reg 1 hE \[5] $end
-$var reg 1 iE \[6] $end
-$var reg 1 jE \[7] $end
-$var reg 1 kE \[8] $end
-$var reg 1 lE \[9] $end
-$var reg 1 mE \[10] $end
-$var reg 1 nE \[11] $end
-$var reg 1 oE \[12] $end
-$var reg 1 pE \[13] $end
-$var reg 1 qE \[14] $end
-$var reg 1 rE \[15] $end
+$var reg 1 ;N \[0] $end
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+$var reg 1 =N \[2] $end
+$var reg 1 >N \[3] $end
+$var reg 1 ?N \[4] $end
+$var reg 1 @N \[5] $end
+$var reg 1 AN \[6] $end
+$var reg 1 BN \[7] $end
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+$var reg 1 DN \[9] $end
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+$var reg 1 FN \[11] $end
+$var reg 1 GN \[12] $end
+$var reg 1 HN \[13] $end
+$var reg 1 IN \[14] $end
+$var reg 1 JN \[15] $end
 $upscope $end
 $scope struct firing_data $end
-$var string 1 sE \$tag $end
-$var wire 4 tE HdlSome $end
+$var string 1 KN \$tag $end
+$var wire 4 LN HdlSome $end
 $upscope $end
-$var wire 1 uE reduced_count_0_2 $end
-$var wire 1 vE reduced_count_overflowed_0_2 $end
+$var wire 1 MN reduced_count_0_2 $end
+$var wire 1 NN reduced_count_overflowed_0_2 $end
 $scope struct reduced_alloc_nums_0_2 $end
-$var wire 1 wE \[0] $end
+$var wire 1 ON \[0] $end
 $upscope $end
-$var wire 1 xE reduced_count_2_4 $end
-$var wire 1 yE reduced_count_overflowed_2_4 $end
+$var wire 1 PN reduced_count_2_4 $end
+$var wire 1 QN reduced_count_overflowed_2_4 $end
 $scope struct reduced_alloc_nums_2_4 $end
-$var wire 1 zE \[0] $end
+$var wire 1 RN \[0] $end
 $upscope $end
-$var wire 1 {E reduced_count_0_4 $end
-$var wire 1 |E reduced_count_overflowed_0_4 $end
+$var wire 1 SN reduced_count_0_4 $end
+$var wire 1 TN reduced_count_overflowed_0_4 $end
 $scope struct reduced_alloc_nums_0_4 $end
-$var wire 2 }E \[0] $end
+$var wire 2 UN \[0] $end
 $upscope $end
-$var wire 1 ~E reduced_count_4_6 $end
-$var wire 1 !F reduced_count_overflowed_4_6 $end
+$var wire 1 VN reduced_count_4_6 $end
+$var wire 1 WN reduced_count_overflowed_4_6 $end
 $scope struct reduced_alloc_nums_4_6 $end
-$var wire 1 "F \[0] $end
+$var wire 1 XN \[0] $end
 $upscope $end
-$var wire 1 #F reduced_count_6_8 $end
-$var wire 1 $F reduced_count_overflowed_6_8 $end
+$var wire 1 YN reduced_count_6_8 $end
+$var wire 1 ZN reduced_count_overflowed_6_8 $end
 $scope struct reduced_alloc_nums_6_8 $end
-$var wire 1 %F \[0] $end
+$var wire 1 [N \[0] $end
 $upscope $end
-$var wire 1 &F reduced_count_4_8 $end
-$var wire 1 'F reduced_count_overflowed_4_8 $end
+$var wire 1 \N reduced_count_4_8 $end
+$var wire 1 ]N reduced_count_overflowed_4_8 $end
 $scope struct reduced_alloc_nums_4_8 $end
-$var wire 2 (F \[0] $end
+$var wire 2 ^N \[0] $end
 $upscope $end
-$var wire 1 )F reduced_count_0_8 $end
-$var wire 1 *F reduced_count_overflowed_0_8 $end
+$var wire 1 _N reduced_count_0_8 $end
+$var wire 1 `N reduced_count_overflowed_0_8 $end
 $scope struct reduced_alloc_nums_0_8 $end
-$var wire 3 +F \[0] $end
+$var wire 3 aN \[0] $end
 $upscope $end
-$var wire 1 ,F reduced_count_8_10 $end
-$var wire 1 -F reduced_count_overflowed_8_10 $end
+$var wire 1 bN reduced_count_8_10 $end
+$var wire 1 cN reduced_count_overflowed_8_10 $end
 $scope struct reduced_alloc_nums_8_10 $end
-$var wire 1 .F \[0] $end
+$var wire 1 dN \[0] $end
 $upscope $end
-$var wire 1 /F reduced_count_10_12 $end
-$var wire 1 0F reduced_count_overflowed_10_12 $end
+$var wire 1 eN reduced_count_10_12 $end
+$var wire 1 fN reduced_count_overflowed_10_12 $end
 $scope struct reduced_alloc_nums_10_12 $end
-$var wire 1 1F \[0] $end
+$var wire 1 gN \[0] $end
 $upscope $end
-$var wire 1 2F reduced_count_8_12 $end
-$var wire 1 3F reduced_count_overflowed_8_12 $end
+$var wire 1 hN reduced_count_8_12 $end
+$var wire 1 iN reduced_count_overflowed_8_12 $end
 $scope struct reduced_alloc_nums_8_12 $end
-$var wire 2 4F \[0] $end
+$var wire 2 jN \[0] $end
 $upscope $end
-$var wire 1 5F reduced_count_12_14 $end
-$var wire 1 6F reduced_count_overflowed_12_14 $end
+$var wire 1 kN reduced_count_12_14 $end
+$var wire 1 lN reduced_count_overflowed_12_14 $end
 $scope struct reduced_alloc_nums_12_14 $end
-$var wire 1 7F \[0] $end
+$var wire 1 mN \[0] $end
 $upscope $end
-$var wire 1 8F reduced_count_14_16 $end
-$var wire 1 9F reduced_count_overflowed_14_16 $end
+$var wire 1 nN reduced_count_14_16 $end
+$var wire 1 oN reduced_count_overflowed_14_16 $end
 $scope struct reduced_alloc_nums_14_16 $end
-$var wire 1 :F \[0] $end
+$var wire 1 pN \[0] $end
 $upscope $end
-$var wire 1 ;F reduced_count_12_16 $end
-$var wire 1 <F reduced_count_overflowed_12_16 $end
+$var wire 1 qN reduced_count_12_16 $end
+$var wire 1 rN reduced_count_overflowed_12_16 $end
 $scope struct reduced_alloc_nums_12_16 $end
-$var wire 2 =F \[0] $end
+$var wire 2 sN \[0] $end
 $upscope $end
-$var wire 1 >F reduced_count_8_16 $end
-$var wire 1 ?F reduced_count_overflowed_8_16 $end
+$var wire 1 tN reduced_count_8_16 $end
+$var wire 1 uN reduced_count_overflowed_8_16 $end
 $scope struct reduced_alloc_nums_8_16 $end
-$var wire 3 @F \[0] $end
+$var wire 3 vN \[0] $end
 $upscope $end
-$var wire 1 AF reduced_count_0_16 $end
-$var wire 1 BF reduced_count_overflowed_0_16 $end
+$var wire 1 wN reduced_count_0_16 $end
+$var wire 1 xN reduced_count_overflowed_0_16 $end
 $scope struct reduced_alloc_nums_0_16 $end
-$var wire 4 CF \[0] $end
+$var wire 4 yN \[0] $end
 $upscope $end
 $scope struct firing_data_2 $end
-$var string 1 DF \$tag $end
-$var wire 4 EF HdlSome $end
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 $upscope $end
 $scope struct and_then_out_3 $end
-$var string 1 NF \$tag $end
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 $scope struct HdlSome $end
-$var string 1 OF \$tag $end
+$var string 1 'O \$tag $end
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 $scope struct common $end
-$var string 0 PF prefix_pad $end
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 $scope struct dest $end
-$var wire 4 QF value $end
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-$var wire 6 RF \[0] $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
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 $scope struct common $end
-$var string 0 \F prefix_pad $end
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 $scope struct dest $end
-$var wire 4 ]F value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 ^F \[0] $end
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-$var wire 6 `F \[2] $end
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+$var wire 6 8O \[2] $end
 $upscope $end
-$var wire 25 aF imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 cF output_integer_mode $end
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 $upscope $end
-$var wire 1 dF invert_src0 $end
-$var wire 1 eF invert_carry_in $end
-$var wire 1 fF invert_carry_out $end
-$var wire 1 gF add_pc $end
+$var wire 1 <O invert_src0 $end
+$var wire 1 =O invert_carry_in $end
+$var wire 1 >O invert_carry_out $end
+$var wire 1 ?O add_pc $end
 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 hF prefix_pad $end
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 $scope struct dest $end
-$var wire 4 iF value $end
+$var wire 4 AO value $end
 $upscope $end
 $scope struct src $end
-$var wire 6 jF \[0] $end
-$var wire 6 kF \[1] $end
-$var wire 6 lF \[2] $end
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+$var wire 6 DO \[2] $end
 $upscope $end
-$var wire 25 mF imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 oF output_integer_mode $end
+$var string 1 GO output_integer_mode $end
 $upscope $end
-$var wire 4 pF lut $end
+$var wire 4 HO lut $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct alu_branch_mop_3 $end
-$var string 1 qF \$tag $end
+$var string 1 IO \$tag $end
 $scope struct HdlSome $end
-$var string 1 rF \$tag $end
+$var string 1 JO \$tag $end
 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 sF prefix_pad $end
+$var string 0 KO prefix_pad $end
 $scope struct dest $end
-$var wire 4 tF value $end
+$var wire 4 LO value $end
 $upscope $end
 $scope struct src $end
-$var wire 6 uF \[0] $end
-$var wire 6 vF \[1] $end
-$var wire 6 wF \[2] $end
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+$var wire 6 OO \[2] $end
 $upscope $end
-$var wire 25 xF imm_low $end
-$var wire 1 yF imm_sign $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 zF output_integer_mode $end
+$var string 1 RO output_integer_mode $end
 $upscope $end
-$var wire 1 {F invert_src0 $end
-$var wire 1 |F invert_carry_in $end
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+$var wire 1 SO invert_src0 $end
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+$var wire 1 UO invert_carry_out $end
+$var wire 1 VO add_pc $end
 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 !G prefix_pad $end
+$var string 0 WO prefix_pad $end
 $scope struct dest $end
-$var wire 4 "G value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 #G \[0] $end
-$var wire 6 $G \[1] $end
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-$var wire 25 &G imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 (G output_integer_mode $end
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 $upscope $end
-$var wire 1 )G invert_src0 $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 -G prefix_pad $end
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 $scope struct dest $end
-$var wire 4 .G value $end
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 $scope struct src $end
-$var wire 6 /G \[0] $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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-$var wire 4 5G lut $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct and_then_out_4 $end
-$var string 1 6G \$tag $end
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-$var string 1 7G \$tag $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 8G prefix_pad $end
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 $scope struct dest $end
-$var wire 4 9G value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 :G \[0] $end
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 $upscope $end
-$var wire 25 =G imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 ?G output_integer_mode $end
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 $upscope $end
-$var wire 1 @G invert_src0 $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 DG prefix_pad $end
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 $scope struct dest $end
-$var wire 4 EG value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 FG \[0] $end
-$var wire 6 GG \[1] $end
-$var wire 6 HG \[2] $end
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 $upscope $end
-$var wire 25 IG imm_low $end
-$var wire 1 JG imm_sign $end
+$var wire 25 !P imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 KG output_integer_mode $end
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 $upscope $end
-$var wire 1 LG invert_src0 $end
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 $upscope $end
 $scope struct Logical $end
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 $scope struct common $end
-$var string 0 PG prefix_pad $end
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 $scope struct dest $end
-$var wire 4 QG value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 RG \[0] $end
-$var wire 6 SG \[1] $end
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 $upscope $end
-$var wire 25 UG imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 WG output_integer_mode $end
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 $upscope $end
-$var wire 4 XG lut $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct alu_branch_mop_4 $end
-$var string 1 YG \$tag $end
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 $scope struct HdlSome $end
-$var string 1 ZG \$tag $end
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 $scope struct AddSub $end
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 $scope struct common $end
-$var string 0 [G prefix_pad $end
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 $scope struct dest $end
-$var wire 4 \G value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 ]G \[0] $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
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-$var string 0 gG prefix_pad $end
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 $scope struct dest $end
-$var wire 4 hG value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 iG \[0] $end
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 $scope struct _phantom $end
 $upscope $end
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-$var string 1 nG output_integer_mode $end
+$var string 1 FP output_integer_mode $end
 $upscope $end
-$var wire 1 oG invert_src0 $end
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+$var wire 1 JP add_pc $end
 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 sG prefix_pad $end
+$var string 0 KP prefix_pad $end
 $scope struct dest $end
-$var wire 4 tG value $end
+$var wire 4 LP value $end
 $upscope $end
 $scope struct src $end
-$var wire 6 uG \[0] $end
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 $upscope $end
-$var wire 25 xG imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 zG output_integer_mode $end
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 $upscope $end
-$var wire 4 {G lut $end
+$var wire 4 SP lut $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-b0 |G
-b0 _J
-b0 }G
-b0 `J
-b0 ~G
-b0 aJ
-b0 !H
-b0 bJ
-b0 "H
-b0 cJ
-b0 #H
-b0 dJ
-b0 $H
-b0 eJ
-b0 %H
-b0 fJ
-b0 &H
-b0 gJ
-b0 'H
-b0 hJ
-b0 (H
-b0 iJ
-b0 )H
-b0 jJ
-b0 *H
-b0 kJ
-b0 +H
-b0 lJ
-b0 ,H
-b0 mJ
-b0 -H
-b0 nJ
-b0 .H
-b0 oJ
-b0 /H
-b0 pJ
-b0 0H
-b0 qJ
-b0 1H
-b0 rJ
-b0 2H
-b0 sJ
-b0 3H
-b0 tJ
-b0 4H
-b0 uJ
-b0 5H
-b0 vJ
-b0 6H
-b0 wJ
-b0 7H
-b0 xJ
-b0 8H
-b0 yJ
-b0 9H
-b0 zJ
-b0 :H
-b0 {J
-b0 ;H
-b0 |J
-b0 <H
-b0 }J
-b0 =H
-b0 ~J
-b0 >H
-b0 !K
-b0 ?H
-b0 "K
-b0 @H
-b0 #K
-b0 AH
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 b0 e%
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 0g%
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 b0 i%
 b0 j%
 b0 k%
@@ -12067,39 +13681,39 @@ b0 l%
 b0 m%
 0n%
 sLoad\x20(0) o%
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 b0 q%
 b0 r%
 b0 s%
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 0v%
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 b0 x%
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 b0 z%
 b0 {%
 b0 |%
 0}%
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 b0 "&
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 b0 %&
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 b0 *&
 b0 +&
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 b0 -&
 b0 .&
 b0 /&
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 01&
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 b0 3&
 14&
 15&
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 1I&
 1J&
 0K&
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+1L&
 0M&
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 b0 O&
 1P&
 1Q&
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 00(
 b11111110 1(
 b0 2(
-sHdlNone\x20(0) 3(
+sHdlSome\x20(1) 3(
 b0 4(
 b0 5(
-sHdlNone\x20(0) 6(
-b0 7(
+sHdlSome\x20(1) 6(
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 b1 8(
-sHdlNone\x20(0) 9(
+sHdlSome\x20(1) 9(
 b0 :(
-b0 ;(
+b11 ;(
 b0 <(
 b0 =(
 b1 >(
@@ -12335,7 +13949,7 @@ sHdlSome\x20(1) ^(
 sHdlNone\x20(0) _(
 b11111110 `(
 b0 a(
-b0 b(
+b100 b(
 b0 c(
 b0 d(
 b1 e(
@@ -12413,10 +14027,10 @@ sHdlSome\x20(1) N)
 sHdlNone\x20(0) O)
 b11111110 P)
 b0 Q)
-b0 R)
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+b1 R)
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 0T)
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 b0 V)
 1W)
 1X)
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 b0 r)
 1s)
 1t)
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 0w)
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 b0 y)
 1z)
 1{)
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 sHdlNone\x20(0) V+
 b0 W+
 b0 X+
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 b1 [+
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 0^+
 1_+
 sHdlNone\x20(0) `+
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 08,
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 sHdlNone\x20(0) <,
 b0 =,
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 b0 <-
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 0T9
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 0|9
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 b0 #:
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 0(:
 0):
 0*:
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-04:
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 b0 6:
 b0 7:
 08:
-09:
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 0::
 0;:
 0<:
 0=:
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 b0 A:
 b0 B:
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 0D:
-0E:
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 0F:
 0G:
 0H:
 0I:
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 b0 O:
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+0P:
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 0T:
 0U:
 0V:
@@ -14021,104 +15635,104 @@ b0 Q:
 0Y:
 0Z:
 0[:
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 0`:
 0a:
 0b:
 0c:
 0d:
-0e:
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 0f:
 0g:
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-b0 i:
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 0k:
 0l:
 0m:
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 0{:
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 0";
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 0);
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 0-;
 0.;
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 b0 :;
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-0D;
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-0S;
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 0U;
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 b0 Z;
-b0 [;
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 b0 ^;
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@@ -14127,16 +15741,16 @@ b0 _;
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@@ -14145,275 +15759,275 @@ b0 q;
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 0/>
 00>
 01>
 02>
 03>
-sHdlNone\x20(0) 4>
-sAddSub\x20(0) 5>
-s0 6>
-b0 7>
+04>
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 b0 8>
 b0 9>
-b0 :>
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 0<>
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 0>>
 0?>
 0@>
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 b0 F>
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 b0 Q>
 b0 R>
 b0 S>
-0T>
-sFull64\x20(0) U>
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-b0 X>
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 0m>
 0n>
 0o>
@@ -14422,629 +16036,629 @@ b0 l>
 0r>
 0s>
 0t>
-sHdlNone\x20(0) u>
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+1u>
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 b0 x>
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 0}>
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 0!?
 0"?
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 0+?
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 0-?
-0.?
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-00?
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 b0 2?
 b0 3?
 b0 4?
 b0 5?
-b0 6?
-07?
-sFull64\x20(0) 8?
-b0 9?
-sHdlNone\x20(0) :?
-b0 ;?
-0<?
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-0??
-0@?
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+06?
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+08?
+19?
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+s0 <?
+b0 =?
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 0B?
-0C?
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-0F?
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+0D?
+1E?
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 0G?
-0H?
-0I?
-0J?
-0K?
-0L?
-0M?
-sHdlNone\x20(0) N?
-b0 O?
-0P?
-0Q?
-0R?
-0S?
-0T?
-0U?
-0V?
-0W?
-sHdlNone\x20(0) X?
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-s0 Z?
-b0 [?
-b0 \?
-b0 ]?
-b0 ^?
-b0 _?
-0`?
-sFull64\x20(0) a?
-0b?
-0c?
-0d?
-0e?
-s0 f?
+s0 H?
+b0 I?
+b0 J?
+b0 K?
+b0 L?
+b0 M?
+0N?
+sFull64\x20(0) O?
+b110 P?
+1Q?
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 1!
 1~"
 1%#
@@ -15428,17 +17916,208 @@ $end
 1p)
 1w)
 1^+
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 #2000000
 0!
 0~"
@@ -15478,18 +18157,26 @@ $end
 0p)
 0w)
 0^+
-0L,
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-0^6
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-078
-0m9
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 #2500000
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 1!
 1~"
 1%#
@@ -15528,17 +18215,263 @@ $end
 1p)
 1w)
 1^+
-1L,
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-178
-1m9
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 #3000000
 0!
 0~"
@@ -15578,18 +18511,26 @@ $end
 0p)
 0w)
 0^+
-0L,
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 1!
 1~"
 1%#
@@ -15628,17 +18569,269 @@ $end
 1p)
 1w)
 1^+
-1L,
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 #4000000
 0!
 0~"
@@ -15678,18 +18871,26 @@ $end
 0p)
 0w)
 0^+
-0L,
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 1!
 1~"
 1%#
@@ -15728,17 +18929,263 @@ $end
 1p)
 1w)
 1^+
-1L,
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-178
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 #5000000
 0!
 0~"
@@ -15778,18 +19225,26 @@ $end
 0p)
 0w)
 0^+
-0L,
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 #5500000
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+b100 {U
 1!
 1~"
 1%#
@@ -15828,17 +19283,269 @@ $end
 1p)
 1w)
 1^+
-1L,
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-178
-1m9
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 #6000000
 0!
 0~"
@@ -15878,18 +19585,26 @@ $end
 0p)
 0w)
 0^+
-0L,
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-078
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 #6500000
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+b101 {U
 1!
 1~"
 1%#
@@ -15928,17 +19643,263 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
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-178
-1m9
-1[:
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 #7000000
 0!
 0~"
@@ -15978,18 +19939,26 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
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 #7500000
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+b110 {U
 1!
 1~"
 1%#
@@ -16028,17 +19997,271 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
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 #8000000
 0!
 0~"
@@ -16078,18 +20301,26 @@ $end
 0p)
 0w)
 0^+
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 #8500000
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 1!
 1~"
 1%#
@@ -16128,17 +20359,566 @@ $end
 1p)
 1w)
 1^+
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+b0 4P
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+0=P
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+0HP
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+b0 SP
 #9000000
 0!
 0~"
@@ -16178,17 +20958,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
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+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #9500000
 1!
 1~"
@@ -16228,17 +21008,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #10000000
 0!
 0~"
@@ -16278,17 +21058,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #10500000
 1!
 1~"
@@ -16328,17 +21108,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #11000000
 0!
 0~"
@@ -16378,17 +21158,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #11500000
 1!
 1~"
@@ -16428,17 +21208,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #12000000
 0!
 0~"
@@ -16478,17 +21258,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #12500000
 1!
 1~"
@@ -16528,17 +21308,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
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+1{:
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+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #13000000
 0!
 0~"
@@ -16578,17 +21358,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #13500000
 1!
 1~"
@@ -16628,17 +21408,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
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+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #14000000
 0!
 0~"
@@ -16678,17 +21458,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #14500000
 1!
 1~"
@@ -16728,17 +21508,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #15000000
 0!
 0~"
@@ -16778,17 +21558,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #15500000
 1!
 1~"
@@ -16828,17 +21608,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #16000000
 0!
 0~"
@@ -16878,17 +21658,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #16500000
 1!
 1~"
@@ -16928,17 +21708,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #17000000
 0!
 0~"
@@ -16978,17 +21758,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #17500000
 1!
 1~"
@@ -17028,17 +21808,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #18000000
 0!
 0~"
@@ -17078,17 +21858,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #18500000
 1!
 1~"
@@ -17128,17 +21908,17 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
+1D9
+1{:
+1g;
+1R<
+1*>
+1t>
+1nK
+1GM
+13N
+1|N
 #19000000
 0!
 0~"
@@ -17178,17 +21958,17 @@ $end
 0p)
 0w)
 0^+
-0L,
-0>5
-0^6
-0L7
-078
-0m9
-0[:
-0MC
-0mD
-0[E
-0FF
+0J,
+0D9
+0{:
+0g;
+0R<
+0*>
+0t>
+0nK
+0GM
+03N
+0|N
 #19500000
 1!
 1~"
@@ -17228,15 +22008,15 @@ $end
 1p)
 1w)
 1^+
-1L,
-1>5
-1^6
-1L7
-178
-1m9
-1[:
-1MC
-1mD
-1[E
-1FF
+1J,
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+1{:
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+1R<
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+1t>
+1nK
+1GM
+13N
+1|N
 #20000000
diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs
index 5c15d13..0c0a3cd 100644
--- a/crates/cpu/tests/reg_alloc.rs
+++ b/crates/cpu/tests/reg_alloc.rs
@@ -193,33 +193,36 @@ circuit reg_alloc:
     type Ty59 = {imm_low: UInt<25>, reversed_src: UInt<0>, imm_sign: UInt<1>}
     type Ty60 = {imm_low: UInt<25>, reversed_src: UInt<8>[1], imm_sign: SInt<1>}
     type Ty61 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>}
-    type Ty62 = {|HdlNone, HdlSome: Ty46|}
-    type Ty63 = {data: Ty62, flip ready: UInt<1>}
-    type Ty64 = {pwr_ca_x86_cf: UInt<1>, pwr_ca32_x86_af: UInt<1>, pwr_ov_x86_of: UInt<1>, pwr_ov32_x86_df: UInt<1>, pwr_cr_lt_x86_sf: UInt<1>, pwr_cr_gt_x86_pf: UInt<1>, pwr_cr_eq_x86_zf: UInt<1>, pwr_so: UInt<1>}
-    type Ty65 = {int_fp: UInt<64>, flags: Ty64}
-    type Ty66 = {which: Ty24, value: Ty65}
-    type Ty67 = {|HdlNone, HdlSome: Ty66|}
-    type Ty68 = {unit_output_writes: Ty67[2], _phantom: Ty2}
+    type Ty62 = {pwr_ca_x86_cf: UInt<1>, pwr_ca32_x86_af: UInt<1>, pwr_ov_x86_of: UInt<1>, pwr_ov32_x86_df: UInt<1>, pwr_cr_lt_x86_sf: UInt<1>, pwr_cr_gt_x86_pf: UInt<1>, pwr_cr_eq_x86_zf: UInt<1>, pwr_so: UInt<1>}
+    type Ty63 = {int_fp: UInt<64>, flags: Ty62}
+    type Ty64 = {which: Ty24, value: Ty63}
+    type Ty65 = {|HdlNone, HdlSome: Ty64|}
+    type Ty66 = {unit_output_writes: Ty65[2], _phantom: Ty2}
+    type Ty67 = {|HdlNone, HdlSome: Ty46|}
+    type Ty68 = {data: Ty67, flip ready: UInt<1>}
     type Ty69 = {which: Ty24}
     type Ty70 = {|HdlNone, HdlSome: Ty69|}
-    type Ty71 = {data: Ty70, flip ready: UInt<1>}
-    type Ty72 = {value: Ty65, extra_out: Ty2}
-    type Ty73 = {|Completed: Ty72, Trap: Ty2|}
-    type Ty74 = {which: Ty24, result: Ty73}
-    type Ty75 = {|HdlNone, HdlSome: Ty74|}
-    type Ty76 = {data: Ty75, flip ready: UInt<1>}
-    type Ty77 = {flip cd: Ty0, flip input_insn: Ty63, flip unit_forwarding_info: Ty68, flip cancel_input: Ty71, `output`: Ty76}
-    type Ty78 = {|HdlNone, HdlSome: UInt<4>|}
-    type Ty79 = {data: Ty78, flip ready: UInt<1>}
-    type Ty80 = {flip cd: Ty0, flip free_in: Ty79[1], alloc_out: Ty79[1]}
-    type Ty81 = {mop: Ty46, src_values: Ty65[3]}
-    type Ty82 = {|HdlNone, HdlSome: Ty81|}
-    type Ty83 = {data: Ty82, flip ready: UInt<1>}
-    type Ty84 = {flip cd: Ty0, flip unit_forwarding_info: Ty68, flip input_insn: Ty63, flip cancel_input: Ty71, ready_mop: Ty83}
-    type Ty85 = {|HdlNone, HdlSome: UInt<3>|}
-    type Ty86 = {|HdlNone, HdlSome: Ty65|}
-    type Ty87 = {mop: Ty46, src_values: Ty86[3]}
+    type Ty71 = {value: Ty63, extra_out: Ty2}
+    type Ty72 = {|Completed: Ty71, Trap: Ty2|}
+    type Ty73 = {which: Ty24, result: Ty72}
+    type Ty74 = {|HdlNone, HdlSome: Ty73|}
+    type Ty75 = {flip unit_forwarding_info: Ty66, flip input_insn: Ty68, flip cancel_input: Ty70, `output`: Ty74}
+    type Ty76 = {flip cd: Ty0, unit_to_reg_alloc: Ty75}
+    type Ty77 = {|HdlNone, HdlSome: UInt<4>|}
+    type Ty78 = {data: Ty77, flip ready: UInt<1>}
+    type Ty79 = {flip cd: Ty0, flip free_in: Ty78[1], alloc_out: Ty78[1]}
+    type Ty80 = {mop: Ty46, src_values: Ty63[3]}
+    type Ty81 = {|HdlNone, HdlSome: Ty80|}
+    type Ty82 = {data: Ty81, flip ready: UInt<1>}
+    type Ty83 = {unit_output: Ty73}
+    type Ty84 = {|HdlNone, HdlSome: Ty83|}
+    type Ty85 = {flip cd: Ty0, unit_to_reg_alloc: Ty75, execute_start: Ty82, flip execute_end: Ty84}
+    type Ty86 = {|Ready, Running, CanceledAndRunning|}
+    type Ty87 = {state: Ty86, mop: Ty46, src_ready_flags: UInt<1>[3]}
     type Ty88 = {|HdlNone, HdlSome: Ty87|}
+    type Ty89 = {|HdlNone, HdlSome: UInt<3>|}
+    type Ty90 = {empty_op_index: Ty89, ready_op_index: Ty89}
+    type Ty91 = {|HdlNone, HdlSome: Ty86|}
     module reg_alloc: @[reg_alloc.rs 49:1]
         input cd: Ty0 @[reg_alloc.rs 53:29]
         input fetch_decode_interface: Ty22 @[reg_alloc.rs 56:11]
@@ -781,63 +784,63 @@ circuit reg_alloc:
             HdlNone:
                 skip
             HdlSome(_match_arm_value):
-                wire unit_kind: Ty56 @[unit.rs 129:1]
-                match _match_arm_value.mop: @[unit.rs 129:1]
+                wire unit_kind: Ty56 @[unit.rs 128:1]
+                match _match_arm_value.mop: @[unit.rs 128:1]
                     AluBranch(_match_arm_value_1):
-                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 129:1]
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 128:1]
                     L2RegisterFile(_match_arm_value_2):
-                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 129:1]
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 128:1]
                     LoadStore(_match_arm_value_3):
-                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 129:1]
-                wire available_units_for_kind: UInt<1>[2] @[unit.rs 129:1]
-                match unit_kind: @[unit.rs 129:1]
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 128:1]
+                wire available_units_for_kind: UInt<1>[2] @[unit.rs 128:1]
+                match unit_kind: @[unit.rs 128:1]
                     AluBranch:
-                        connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 129:1]
-                        connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 129:1]
+                        connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 128:1]
+                        connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 128:1]
                     L2RegisterFile:
-                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 129:1]
-                        connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 129:1]
+                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 128:1]
+                        connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 128:1]
                     LoadStore:
-                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 129:1]
-                        connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 129:1]
+                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 128:1]
+                        connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 128:1]
                 connect available_units[0], available_units_for_kind @[reg_alloc.rs 190:13]
                 match renamed_mops_out_reg[0]: @[reg_alloc.rs 195:13]
                     HdlNone:
                         skip
                     HdlSome(_match_arm_value_4):
-                        wire dest_reg: Ty4 @[unit.rs 129:1]
-                        match _match_arm_value.mop: @[unit.rs 129:1]
+                        wire dest_reg: Ty4 @[unit.rs 128:1]
+                        match _match_arm_value.mop: @[unit.rs 128:1]
                             AluBranch(_match_arm_value_5):
-                                wire dest_reg_1: Ty4 @[instruction.rs 502:1]
-                                match _match_arm_value_5: @[instruction.rs 502:1]
+                                wire dest_reg_1: Ty4 @[instruction.rs 538:1]
+                                match _match_arm_value_5: @[instruction.rs 538:1]
                                     AddSub(_match_arm_value_6):
-                                        connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 502:1]
+                                        connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 538:1]
                                     AddSubI(_match_arm_value_7):
-                                        connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 502:1]
+                                        connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 538:1]
                                     Logical(_match_arm_value_8):
-                                        connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 502:1]
-                                connect dest_reg, dest_reg_1 @[unit.rs 129:1]
+                                        connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 538:1]
+                                connect dest_reg, dest_reg_1 @[unit.rs 128:1]
                             L2RegisterFile(_match_arm_value_9):
-                                wire dest_reg_2: Ty4 @[instruction.rs 529:1]
-                                match _match_arm_value_9: @[instruction.rs 529:1]
+                                wire dest_reg_2: Ty4 @[instruction.rs 565:1]
+                                match _match_arm_value_9: @[instruction.rs 565:1]
                                     ReadL2Reg(_match_arm_value_10):
-                                        connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 529:1]
+                                        connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 565:1]
                                     WriteL2Reg(_match_arm_value_11):
-                                        connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 529:1]
-                                connect dest_reg, dest_reg_2 @[unit.rs 129:1]
+                                        connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 565:1]
+                                connect dest_reg, dest_reg_2 @[unit.rs 128:1]
                             LoadStore(_match_arm_value_12):
-                                wire dest_reg_3: Ty4 @[instruction.rs 564:1]
-                                match _match_arm_value_12: @[instruction.rs 564:1]
+                                wire dest_reg_3: Ty4 @[instruction.rs 600:1]
+                                match _match_arm_value_12: @[instruction.rs 600:1]
                                     Load(_match_arm_value_13):
-                                        connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 564:1]
+                                        connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 600:1]
                                     Store(_match_arm_value_14):
-                                        connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 564:1]
-                                connect dest_reg, dest_reg_3 @[unit.rs 129:1]
-                        wire mapped_regs: Ty51 @[unit.rs 129:1]
-                        match _match_arm_value.mop: @[unit.rs 129:1]
+                                        connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 600:1]
+                                connect dest_reg, dest_reg_3 @[unit.rs 128:1]
+                        wire mapped_regs: Ty51 @[unit.rs 128:1]
+                        match _match_arm_value.mop: @[unit.rs 128:1]
                             AluBranch(_match_arm_value_15):
-                                wire mapped_regs_1: Ty46 @[instruction.rs 502:1]
-                                match _match_arm_value_15: @[instruction.rs 502:1]
+                                wire mapped_regs_1: Ty46 @[instruction.rs 538:1]
+                                match _match_arm_value_15: @[instruction.rs 538:1]
                                     AddSub(_match_arm_value_16):
                                         wire _bundle_literal_expr_36: Ty1
                                         connect _bundle_literal_expr_36.value, _match_arm_value_16.alu_common.common.src[0]
@@ -951,7 +954,7 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_39.invert_carry_in, _match_arm_value_16.invert_carry_in
                                         connect _bundle_literal_expr_39.invert_carry_out, _match_arm_value_16.invert_carry_out
                                         connect _bundle_literal_expr_39.add_pc, _match_arm_value_16.add_pc
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 502:1]
+                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 538:1]
                                     AddSubI(_match_arm_value_17):
                                         wire _bundle_literal_expr_45: Ty1
                                         connect _bundle_literal_expr_45.value, _match_arm_value_17.alu_common.common.src[0]
@@ -1055,7 +1058,7 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_47.invert_carry_in, _match_arm_value_17.invert_carry_in
                                         connect _bundle_literal_expr_47.invert_carry_out, _match_arm_value_17.invert_carry_out
                                         connect _bundle_literal_expr_47.add_pc, _match_arm_value_17.add_pc
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 502:1]
+                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 538:1]
                                     Logical(_match_arm_value_18):
                                         wire _bundle_literal_expr_54: Ty1
                                         connect _bundle_literal_expr_54.value, _match_arm_value_18.alu_common.common.src[0]
@@ -1156,11 +1159,11 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_57.output_integer_mode, _match_arm_value_18.alu_common.output_integer_mode
                                         connect _bundle_literal_expr_56.alu_common, _bundle_literal_expr_57
                                         connect _bundle_literal_expr_56.lut, _match_arm_value_18.lut
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 502:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 129:1]
+                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 538:1]
+                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 128:1]
                             L2RegisterFile(_match_arm_value_19):
-                                wire mapped_regs_2: Ty49 @[instruction.rs 529:1]
-                                match _match_arm_value_19: @[instruction.rs 529:1]
+                                wire mapped_regs_2: Ty49 @[instruction.rs 565:1]
+                                match _match_arm_value_19: @[instruction.rs 565:1]
                                     ReadL2Reg(_match_arm_value_20):
                                         wire _bundle_literal_expr_63: Ty48
                                         wire _bundle_literal_expr_64: Ty47
@@ -1225,7 +1228,7 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_68
                                         connect _bundle_literal_expr_64._phantom, _bundle_literal_expr_68
                                         connect _bundle_literal_expr_63.common, _bundle_literal_expr_64
-                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 529:1]
+                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 565:1]
                                     WriteL2Reg(_match_arm_value_21):
                                         wire _bundle_literal_expr_69: Ty1
                                         connect _bundle_literal_expr_69.value, _match_arm_value_21.common.src[0]
@@ -1300,11 +1303,11 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_75
                                         connect _bundle_literal_expr_71._phantom, _bundle_literal_expr_75
                                         connect _bundle_literal_expr_70.common, _bundle_literal_expr_71
-                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 529:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 129:1]
+                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 565:1]
+                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 128:1]
                             LoadStore(_match_arm_value_22):
-                                wire mapped_regs_3: Ty50 @[instruction.rs 564:1]
-                                match _match_arm_value_22: @[instruction.rs 564:1]
+                                wire mapped_regs_3: Ty50 @[instruction.rs 600:1]
+                                match _match_arm_value_22: @[instruction.rs 600:1]
                                     Load(_match_arm_value_23):
                                         wire _bundle_literal_expr_76: Ty47
                                         connect _bundle_literal_expr_76.prefix_pad, _match_arm_value_23.prefix_pad
@@ -1367,7 +1370,7 @@ circuit reg_alloc:
                                         wire _bundle_literal_expr_80: Ty2
                                         invalidate _bundle_literal_expr_80
                                         connect _bundle_literal_expr_76._phantom, _bundle_literal_expr_80
-                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 564:1]
+                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 600:1]
                                     Store(_match_arm_value_24):
                                         wire _bundle_literal_expr_81: Ty1
                                         connect _bundle_literal_expr_81.value, _match_arm_value_24.src[0]
@@ -1440,31 +1443,31 @@ circuit reg_alloc:
                                         wire _bundle_literal_expr_86: Ty2
                                         invalidate _bundle_literal_expr_86
                                         connect _bundle_literal_expr_82._phantom, _bundle_literal_expr_86
-                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 564:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 129:1]
+                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 600:1]
+                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 128:1]
                         connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs) @[reg_alloc.rs 197:17]
-                        wire flag_reg: Ty1 @[instruction.rs 831:32]
+                        wire flag_reg: Ty1 @[instruction.rs 867:32]
                         wire _bundle_literal_expr_87: Ty1
                         connect _bundle_literal_expr_87.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 832:17]
-                        match dest_reg.flag_regs[0]: @[instruction.rs 834:17]
+                        connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 868:17]
+                        match dest_reg.flag_regs[0]: @[instruction.rs 870:17]
                             HdlNone:
                                 skip
                             HdlSome(_match_arm_value_25):
                                 wire _bundle_literal_expr_88: Ty1
                                 connect _bundle_literal_expr_88.value, tail(UInt<32>(0hFE), 24)
-                                connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 836:21]
-                        wire flag_reg_1: Ty1 @[instruction.rs 831:32]
+                                connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 872:21]
+                        wire flag_reg_1: Ty1 @[instruction.rs 867:32]
                         wire _bundle_literal_expr_89: Ty1
                         connect _bundle_literal_expr_89.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 832:17]
-                        match dest_reg.flag_regs[1]: @[instruction.rs 834:17]
+                        connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 868:17]
+                        match dest_reg.flag_regs[1]: @[instruction.rs 870:17]
                             HdlNone:
                                 skip
                             HdlSome(_match_arm_value_26):
                                 wire _bundle_literal_expr_90: Ty1
                                 connect _bundle_literal_expr_90.value, tail(UInt<32>(0hFF), 24)
-                                connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 836:21]
+                                connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 872:21]
                         when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25]
                             connect rename_table_normal_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 229:29]
                             ; connect different types:
@@ -1569,56 +1572,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_29):
-                            wire dest_reg_4: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_28.mop: @[unit.rs 129:1]
+                            wire dest_reg_4: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_28.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_30):
-                                    wire dest_reg_5: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_30: @[instruction.rs 502:1]
+                                    wire dest_reg_5: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_30: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_31):
-                                            connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_32):
-                                            connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_33):
-                                            connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_4, dest_reg_5 @[unit.rs 129:1]
+                                            connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_4, dest_reg_5 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_34):
-                                    wire dest_reg_6: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_34: @[instruction.rs 529:1]
+                                    wire dest_reg_6: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_34: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_35):
-                                            connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_36):
-                                            connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_4, dest_reg_6 @[unit.rs 129:1]
+                                            connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_4, dest_reg_6 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_37):
-                                    wire dest_reg_7: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_37: @[instruction.rs 564:1]
+                                    wire dest_reg_7: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_37: @[instruction.rs 600:1]
                                         Load(_match_arm_value_38):
-                                            connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 564:1]
+                                            connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_39):
-                                            connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 564:1]
-                                    connect dest_reg_4, dest_reg_7 @[unit.rs 129:1]
-                            wire flag_reg_2: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 600:1]
+                                    connect dest_reg_4, dest_reg_7 @[unit.rs 128:1]
+                            wire flag_reg_2: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_95: Ty1
                             connect _bundle_literal_expr_95.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 832:17]
-                            match dest_reg_4.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 868:17]
+                            match dest_reg_4.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_40):
                                     wire _bundle_literal_expr_96: Ty1
                                     connect _bundle_literal_expr_96.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 836:21]
-                            wire flag_reg_3: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 872:21]
+                            wire flag_reg_3: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_97: Ty1
                             connect _bundle_literal_expr_97.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 832:17]
-                            match dest_reg_4.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 868:17]
+                            match dest_reg_4.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_41):
                                     wire _bundle_literal_expr_98: Ty1
                                     connect _bundle_literal_expr_98.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 836:21]
+                                    connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 872:21]
                             when eq(dest_reg_4.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_4.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41]
@@ -1644,56 +1647,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_43):
-                            wire dest_reg_8: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_42.mop: @[unit.rs 129:1]
+                            wire dest_reg_8: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_42.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_44):
-                                    wire dest_reg_9: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_44: @[instruction.rs 502:1]
+                                    wire dest_reg_9: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_44: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_45):
-                                            connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_46):
-                                            connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_47):
-                                            connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_8, dest_reg_9 @[unit.rs 129:1]
+                                            connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_8, dest_reg_9 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_48):
-                                    wire dest_reg_10: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_48: @[instruction.rs 529:1]
+                                    wire dest_reg_10: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_48: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_49):
-                                            connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_50):
-                                            connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_8, dest_reg_10 @[unit.rs 129:1]
+                                            connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_8, dest_reg_10 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_51):
-                                    wire dest_reg_11: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_51: @[instruction.rs 564:1]
+                                    wire dest_reg_11: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_51: @[instruction.rs 600:1]
                                         Load(_match_arm_value_52):
-                                            connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 564:1]
+                                            connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_53):
-                                            connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 564:1]
-                                    connect dest_reg_8, dest_reg_11 @[unit.rs 129:1]
-                            wire flag_reg_4: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 600:1]
+                                    connect dest_reg_8, dest_reg_11 @[unit.rs 128:1]
+                            wire flag_reg_4: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_99: Ty1
                             connect _bundle_literal_expr_99.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 832:17]
-                            match dest_reg_8.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 868:17]
+                            match dest_reg_8.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_54):
                                     wire _bundle_literal_expr_100: Ty1
                                     connect _bundle_literal_expr_100.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 836:21]
-                            wire flag_reg_5: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 872:21]
+                            wire flag_reg_5: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_101: Ty1
                             connect _bundle_literal_expr_101.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 832:17]
-                            match dest_reg_8.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 868:17]
+                            match dest_reg_8.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_55):
                                     wire _bundle_literal_expr_102: Ty1
                                     connect _bundle_literal_expr_102.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 836:21]
+                                    connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 872:21]
                             when eq(dest_reg_8.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_8.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41]
@@ -1732,56 +1735,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_57):
-                            wire dest_reg_12: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_56.mop: @[unit.rs 129:1]
+                            wire dest_reg_12: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_56.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_58):
-                                    wire dest_reg_13: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_58: @[instruction.rs 502:1]
+                                    wire dest_reg_13: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_58: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_59):
-                                            connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_60):
-                                            connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_61):
-                                            connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_12, dest_reg_13 @[unit.rs 129:1]
+                                            connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_12, dest_reg_13 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_62):
-                                    wire dest_reg_14: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_62: @[instruction.rs 529:1]
+                                    wire dest_reg_14: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_62: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_63):
-                                            connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_64):
-                                            connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_12, dest_reg_14 @[unit.rs 129:1]
+                                            connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_12, dest_reg_14 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_65):
-                                    wire dest_reg_15: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_65: @[instruction.rs 564:1]
+                                    wire dest_reg_15: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_65: @[instruction.rs 600:1]
                                         Load(_match_arm_value_66):
-                                            connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 564:1]
+                                            connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_67):
-                                            connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 564:1]
-                                    connect dest_reg_12, dest_reg_15 @[unit.rs 129:1]
-                            wire flag_reg_6: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 600:1]
+                                    connect dest_reg_12, dest_reg_15 @[unit.rs 128:1]
+                            wire flag_reg_6: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_107: Ty1
                             connect _bundle_literal_expr_107.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 832:17]
-                            match dest_reg_12.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 868:17]
+                            match dest_reg_12.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_68):
                                     wire _bundle_literal_expr_108: Ty1
                                     connect _bundle_literal_expr_108.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 836:21]
-                            wire flag_reg_7: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 872:21]
+                            wire flag_reg_7: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_109: Ty1
                             connect _bundle_literal_expr_109.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 832:17]
-                            match dest_reg_12.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 868:17]
+                            match dest_reg_12.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_69):
                                     wire _bundle_literal_expr_110: Ty1
                                     connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 836:21]
+                                    connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 872:21]
                             when eq(dest_reg_12.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_12.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41]
@@ -1807,56 +1810,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_71):
-                            wire dest_reg_16: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_70.mop: @[unit.rs 129:1]
+                            wire dest_reg_16: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_70.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_72):
-                                    wire dest_reg_17: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_72: @[instruction.rs 502:1]
+                                    wire dest_reg_17: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_72: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_73):
-                                            connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_74):
-                                            connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_75):
-                                            connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_16, dest_reg_17 @[unit.rs 129:1]
+                                            connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_16, dest_reg_17 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_76):
-                                    wire dest_reg_18: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_76: @[instruction.rs 529:1]
+                                    wire dest_reg_18: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_76: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_77):
-                                            connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_78):
-                                            connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_16, dest_reg_18 @[unit.rs 129:1]
+                                            connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_16, dest_reg_18 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_79):
-                                    wire dest_reg_19: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_79: @[instruction.rs 564:1]
+                                    wire dest_reg_19: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_79: @[instruction.rs 600:1]
                                         Load(_match_arm_value_80):
-                                            connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 564:1]
+                                            connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_81):
-                                            connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 564:1]
-                                    connect dest_reg_16, dest_reg_19 @[unit.rs 129:1]
-                            wire flag_reg_8: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 600:1]
+                                    connect dest_reg_16, dest_reg_19 @[unit.rs 128:1]
+                            wire flag_reg_8: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_111: Ty1
                             connect _bundle_literal_expr_111.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 832:17]
-                            match dest_reg_16.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 868:17]
+                            match dest_reg_16.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_82):
                                     wire _bundle_literal_expr_112: Ty1
                                     connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 836:21]
-                            wire flag_reg_9: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 872:21]
+                            wire flag_reg_9: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_113: Ty1
                             connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 832:17]
-                            match dest_reg_16.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 868:17]
+                            match dest_reg_16.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_83):
                                     wire _bundle_literal_expr_114: Ty1
                                     connect _bundle_literal_expr_114.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 836:21]
+                                    connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 872:21]
                             when eq(dest_reg_16.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_16.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41]
@@ -1895,56 +1898,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_85):
-                            wire dest_reg_20: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_84.mop: @[unit.rs 129:1]
+                            wire dest_reg_20: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_84.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_86):
-                                    wire dest_reg_21: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_86: @[instruction.rs 502:1]
+                                    wire dest_reg_21: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_86: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_87):
-                                            connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_88):
-                                            connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_89):
-                                            connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_20, dest_reg_21 @[unit.rs 129:1]
+                                            connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_20, dest_reg_21 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_90):
-                                    wire dest_reg_22: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_90: @[instruction.rs 529:1]
+                                    wire dest_reg_22: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_90: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_91):
-                                            connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_92):
-                                            connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_20, dest_reg_22 @[unit.rs 129:1]
+                                            connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_20, dest_reg_22 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_93):
-                                    wire dest_reg_23: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_93: @[instruction.rs 564:1]
+                                    wire dest_reg_23: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_93: @[instruction.rs 600:1]
                                         Load(_match_arm_value_94):
-                                            connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 564:1]
+                                            connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_95):
-                                            connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 564:1]
-                                    connect dest_reg_20, dest_reg_23 @[unit.rs 129:1]
-                            wire flag_reg_10: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 600:1]
+                                    connect dest_reg_20, dest_reg_23 @[unit.rs 128:1]
+                            wire flag_reg_10: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_119: Ty1
                             connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 832:17]
-                            match dest_reg_20.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 868:17]
+                            match dest_reg_20.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_96):
                                     wire _bundle_literal_expr_120: Ty1
                                     connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 836:21]
-                            wire flag_reg_11: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 872:21]
+                            wire flag_reg_11: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_121: Ty1
                             connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 832:17]
-                            match dest_reg_20.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 868:17]
+                            match dest_reg_20.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_97):
                                     wire _bundle_literal_expr_122: Ty1
                                     connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 836:21]
+                                    connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 872:21]
                             when eq(dest_reg_20.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_20.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41]
@@ -1970,56 +1973,56 @@ circuit reg_alloc:
                         HdlNone:
                             skip
                         HdlSome(_match_arm_value_99):
-                            wire dest_reg_24: Ty4 @[unit.rs 129:1]
-                            match _match_arm_value_98.mop: @[unit.rs 129:1]
+                            wire dest_reg_24: Ty4 @[unit.rs 128:1]
+                            match _match_arm_value_98.mop: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_100):
-                                    wire dest_reg_25: Ty4 @[instruction.rs 502:1]
-                                    match _match_arm_value_100: @[instruction.rs 502:1]
+                                    wire dest_reg_25: Ty4 @[instruction.rs 538:1]
+                                    match _match_arm_value_100: @[instruction.rs 538:1]
                                         AddSub(_match_arm_value_101):
-                                            connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 538:1]
                                         AddSubI(_match_arm_value_102):
-                                            connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 502:1]
+                                            connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1]
                                         Logical(_match_arm_value_103):
-                                            connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 502:1]
-                                    connect dest_reg_24, dest_reg_25 @[unit.rs 129:1]
+                                            connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1]
+                                    connect dest_reg_24, dest_reg_25 @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_104):
-                                    wire dest_reg_26: Ty4 @[instruction.rs 529:1]
-                                    match _match_arm_value_104: @[instruction.rs 529:1]
+                                    wire dest_reg_26: Ty4 @[instruction.rs 565:1]
+                                    match _match_arm_value_104: @[instruction.rs 565:1]
                                         ReadL2Reg(_match_arm_value_105):
-                                            connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 529:1]
+                                            connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 565:1]
                                         WriteL2Reg(_match_arm_value_106):
-                                            connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 529:1]
-                                    connect dest_reg_24, dest_reg_26 @[unit.rs 129:1]
+                                            connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 565:1]
+                                    connect dest_reg_24, dest_reg_26 @[unit.rs 128:1]
                                 LoadStore(_match_arm_value_107):
-                                    wire dest_reg_27: Ty4 @[instruction.rs 564:1]
-                                    match _match_arm_value_107: @[instruction.rs 564:1]
+                                    wire dest_reg_27: Ty4 @[instruction.rs 600:1]
+                                    match _match_arm_value_107: @[instruction.rs 600:1]
                                         Load(_match_arm_value_108):
-                                            connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 564:1]
+                                            connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 600:1]
                                         Store(_match_arm_value_109):
-                                            connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 564:1]
-                                    connect dest_reg_24, dest_reg_27 @[unit.rs 129:1]
-                            wire flag_reg_12: Ty1 @[instruction.rs 831:32]
+                                            connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 600:1]
+                                    connect dest_reg_24, dest_reg_27 @[unit.rs 128:1]
+                            wire flag_reg_12: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_123: Ty1
                             connect _bundle_literal_expr_123.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 832:17]
-                            match dest_reg_24.flag_regs[0]: @[instruction.rs 834:17]
+                            connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 868:17]
+                            match dest_reg_24.flag_regs[0]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_110):
                                     wire _bundle_literal_expr_124: Ty1
                                     connect _bundle_literal_expr_124.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 836:21]
-                            wire flag_reg_13: Ty1 @[instruction.rs 831:32]
+                                    connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 872:21]
+                            wire flag_reg_13: Ty1 @[instruction.rs 867:32]
                             wire _bundle_literal_expr_125: Ty1
                             connect _bundle_literal_expr_125.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 832:17]
-                            match dest_reg_24.flag_regs[1]: @[instruction.rs 834:17]
+                            connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 868:17]
+                            match dest_reg_24.flag_regs[1]: @[instruction.rs 870:17]
                                 HdlNone:
                                     skip
                                 HdlSome(_match_arm_value_111):
                                     wire _bundle_literal_expr_126: Ty1
                                     connect _bundle_literal_expr_126.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 836:21]
+                                    connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 872:21]
                             when eq(dest_reg_24.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41]
                                 connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45]
                             when eq(dest_reg_24.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41]
@@ -2158,63 +2161,63 @@ circuit reg_alloc:
             HdlNone:
                 skip
             HdlSome(_match_arm_value_112):
-                wire unit_kind_1: Ty56 @[unit.rs 129:1]
-                match _match_arm_value_112.mop: @[unit.rs 129:1]
+                wire unit_kind_1: Ty56 @[unit.rs 128:1]
+                match _match_arm_value_112.mop: @[unit.rs 128:1]
                     AluBranch(_match_arm_value_113):
-                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 129:1]
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 128:1]
                     L2RegisterFile(_match_arm_value_114):
-                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 129:1]
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 128:1]
                     LoadStore(_match_arm_value_115):
-                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 129:1]
-                wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 129:1]
-                match unit_kind_1: @[unit.rs 129:1]
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 128:1]
+                wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 128:1]
+                match unit_kind_1: @[unit.rs 128:1]
                     AluBranch:
-                        connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 129:1]
-                        connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 129:1]
+                        connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 128:1]
+                        connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 128:1]
                     L2RegisterFile:
-                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 129:1]
-                        connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 129:1]
+                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 128:1]
+                        connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 128:1]
                     LoadStore:
-                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 129:1]
-                        connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 129:1]
+                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 128:1]
+                        connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 128:1]
                 connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 190:13]
                 match renamed_mops_out_reg[1]: @[reg_alloc.rs 195:13]
                     HdlNone:
                         skip
                     HdlSome(_match_arm_value_116):
-                        wire dest_reg_28: Ty4 @[unit.rs 129:1]
-                        match _match_arm_value_112.mop: @[unit.rs 129:1]
+                        wire dest_reg_28: Ty4 @[unit.rs 128:1]
+                        match _match_arm_value_112.mop: @[unit.rs 128:1]
                             AluBranch(_match_arm_value_117):
-                                wire dest_reg_29: Ty4 @[instruction.rs 502:1]
-                                match _match_arm_value_117: @[instruction.rs 502:1]
+                                wire dest_reg_29: Ty4 @[instruction.rs 538:1]
+                                match _match_arm_value_117: @[instruction.rs 538:1]
                                     AddSub(_match_arm_value_118):
-                                        connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 502:1]
+                                        connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 538:1]
                                     AddSubI(_match_arm_value_119):
-                                        connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 502:1]
+                                        connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 538:1]
                                     Logical(_match_arm_value_120):
-                                        connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 502:1]
-                                connect dest_reg_28, dest_reg_29 @[unit.rs 129:1]
+                                        connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1]
+                                connect dest_reg_28, dest_reg_29 @[unit.rs 128:1]
                             L2RegisterFile(_match_arm_value_121):
-                                wire dest_reg_30: Ty4 @[instruction.rs 529:1]
-                                match _match_arm_value_121: @[instruction.rs 529:1]
+                                wire dest_reg_30: Ty4 @[instruction.rs 565:1]
+                                match _match_arm_value_121: @[instruction.rs 565:1]
                                     ReadL2Reg(_match_arm_value_122):
-                                        connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 529:1]
+                                        connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 565:1]
                                     WriteL2Reg(_match_arm_value_123):
-                                        connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 529:1]
-                                connect dest_reg_28, dest_reg_30 @[unit.rs 129:1]
+                                        connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 565:1]
+                                connect dest_reg_28, dest_reg_30 @[unit.rs 128:1]
                             LoadStore(_match_arm_value_124):
-                                wire dest_reg_31: Ty4 @[instruction.rs 564:1]
-                                match _match_arm_value_124: @[instruction.rs 564:1]
+                                wire dest_reg_31: Ty4 @[instruction.rs 600:1]
+                                match _match_arm_value_124: @[instruction.rs 600:1]
                                     Load(_match_arm_value_125):
-                                        connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 564:1]
+                                        connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 600:1]
                                     Store(_match_arm_value_126):
-                                        connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 564:1]
-                                connect dest_reg_28, dest_reg_31 @[unit.rs 129:1]
-                        wire mapped_regs_4: Ty51 @[unit.rs 129:1]
-                        match _match_arm_value_112.mop: @[unit.rs 129:1]
+                                        connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 600:1]
+                                connect dest_reg_28, dest_reg_31 @[unit.rs 128:1]
+                        wire mapped_regs_4: Ty51 @[unit.rs 128:1]
+                        match _match_arm_value_112.mop: @[unit.rs 128:1]
                             AluBranch(_match_arm_value_127):
-                                wire mapped_regs_5: Ty46 @[instruction.rs 502:1]
-                                match _match_arm_value_127: @[instruction.rs 502:1]
+                                wire mapped_regs_5: Ty46 @[instruction.rs 538:1]
+                                match _match_arm_value_127: @[instruction.rs 538:1]
                                     AddSub(_match_arm_value_128):
                                         wire _bundle_literal_expr_151: Ty1
                                         connect _bundle_literal_expr_151.value, _match_arm_value_128.alu_common.common.src[0]
@@ -2328,7 +2331,7 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_128.invert_carry_in
                                         connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_128.invert_carry_out
                                         connect _bundle_literal_expr_154.add_pc, _match_arm_value_128.add_pc
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 502:1]
+                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 538:1]
                                     AddSubI(_match_arm_value_129):
                                         wire _bundle_literal_expr_160: Ty1
                                         connect _bundle_literal_expr_160.value, _match_arm_value_129.alu_common.common.src[0]
@@ -2432,7 +2435,7 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_162.invert_carry_in, _match_arm_value_129.invert_carry_in
                                         connect _bundle_literal_expr_162.invert_carry_out, _match_arm_value_129.invert_carry_out
                                         connect _bundle_literal_expr_162.add_pc, _match_arm_value_129.add_pc
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 502:1]
+                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 538:1]
                                     Logical(_match_arm_value_130):
                                         wire _bundle_literal_expr_169: Ty1
                                         connect _bundle_literal_expr_169.value, _match_arm_value_130.alu_common.common.src[0]
@@ -2533,11 +2536,11 @@ circuit reg_alloc:
                                         connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_130.alu_common.output_integer_mode
                                         connect _bundle_literal_expr_171.alu_common, _bundle_literal_expr_172
                                         connect _bundle_literal_expr_171.lut, _match_arm_value_130.lut
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 502:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 129:1]
+                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 538:1]
+                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 128:1]
                             L2RegisterFile(_match_arm_value_131):
-                                wire mapped_regs_6: Ty49 @[instruction.rs 529:1]
-                                match _match_arm_value_131: @[instruction.rs 529:1]
+                                wire mapped_regs_6: Ty49 @[instruction.rs 565:1]
+                                match _match_arm_value_131: @[instruction.rs 565:1]
                                     ReadL2Reg(_match_arm_value_132):
                                         wire _bundle_literal_expr_178: Ty48
                                         wire _bundle_literal_expr_179: Ty47
@@ -2602,7 +2605,7 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_183
                                         connect _bundle_literal_expr_179._phantom, _bundle_literal_expr_183
                                         connect _bundle_literal_expr_178.common, _bundle_literal_expr_179
-                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 529:1]
+                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 565:1]
                                     WriteL2Reg(_match_arm_value_133):
                                         wire _bundle_literal_expr_184: Ty1
                                         connect _bundle_literal_expr_184.value, _match_arm_value_133.common.src[0]
@@ -2677,11 +2680,11 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_190
                                         connect _bundle_literal_expr_186._phantom, _bundle_literal_expr_190
                                         connect _bundle_literal_expr_185.common, _bundle_literal_expr_186
-                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 529:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 129:1]
+                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 565:1]
+                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 128:1]
                             LoadStore(_match_arm_value_134):
-                                wire mapped_regs_7: Ty50 @[instruction.rs 564:1]
-                                match _match_arm_value_134: @[instruction.rs 564:1]
+                                wire mapped_regs_7: Ty50 @[instruction.rs 600:1]
+                                match _match_arm_value_134: @[instruction.rs 600:1]
                                     Load(_match_arm_value_135):
                                         wire _bundle_literal_expr_191: Ty47
                                         connect _bundle_literal_expr_191.prefix_pad, _match_arm_value_135.prefix_pad
@@ -2744,7 +2747,7 @@ circuit reg_alloc:
                                         wire _bundle_literal_expr_195: Ty2
                                         invalidate _bundle_literal_expr_195
                                         connect _bundle_literal_expr_191._phantom, _bundle_literal_expr_195
-                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 564:1]
+                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 600:1]
                                     Store(_match_arm_value_136):
                                         wire _bundle_literal_expr_196: Ty1
                                         connect _bundle_literal_expr_196.value, _match_arm_value_136.src[0]
@@ -2817,31 +2820,31 @@ circuit reg_alloc:
                                         wire _bundle_literal_expr_201: Ty2
                                         invalidate _bundle_literal_expr_201
                                         connect _bundle_literal_expr_197._phantom, _bundle_literal_expr_201
-                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 564:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 129:1]
+                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 600:1]
+                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 128:1]
                         connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 197:17]
-                        wire flag_reg_14: Ty1 @[instruction.rs 831:32]
+                        wire flag_reg_14: Ty1 @[instruction.rs 867:32]
                         wire _bundle_literal_expr_202: Ty1
                         connect _bundle_literal_expr_202.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 832:17]
-                        match dest_reg_28.flag_regs[0]: @[instruction.rs 834:17]
+                        connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 868:17]
+                        match dest_reg_28.flag_regs[0]: @[instruction.rs 870:17]
                             HdlNone:
                                 skip
                             HdlSome(_match_arm_value_137):
                                 wire _bundle_literal_expr_203: Ty1
                                 connect _bundle_literal_expr_203.value, tail(UInt<32>(0hFE), 24)
-                                connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 836:21]
-                        wire flag_reg_15: Ty1 @[instruction.rs 831:32]
+                                connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 872:21]
+                        wire flag_reg_15: Ty1 @[instruction.rs 867:32]
                         wire _bundle_literal_expr_204: Ty1
                         connect _bundle_literal_expr_204.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 832:17]
-                        match dest_reg_28.flag_regs[1]: @[instruction.rs 834:17]
+                        connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 868:17]
+                        match dest_reg_28.flag_regs[1]: @[instruction.rs 870:17]
                             HdlNone:
                                 skip
                             HdlSome(_match_arm_value_138):
                                 wire _bundle_literal_expr_205: Ty1
                                 connect _bundle_literal_expr_205.value, tail(UInt<32>(0hFF), 24)
-                                connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 836:21]
+                                connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 872:21]
                         when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25]
                             connect rename_table_normal_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 229:29]
                             ; connect different types:
@@ -2923,34 +2926,34 @@ circuit reg_alloc:
         connect unit_0.cd, cd @[reg_alloc.rs 313:9]
         inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 326:13]
         connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9]
-        wire _uninit_expr_12: Ty78
+        wire _uninit_expr_12: Ty77
         invalidate _uninit_expr_12
         connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr_12 @[reg_alloc.rs 330:9]
         connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9]
-        connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9]
+        connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9]
         match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13]
             HdlNone:
                 connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 343:17]
             HdlSome(_match_arm_value_141):
                 skip
-        when not(unit_0.input_insn.ready): @[reg_alloc.rs 346:13]
+        when not(unit_0.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13]
             connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 348:17]
         match selected_unit_indexes[0]: @[reg_alloc.rs 351:13]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_142):
                 when eq(_match_arm_value_142, UInt<64>(0h0)): @[reg_alloc.rs 353:17]
-                    wire and_then_out: Ty62 @[reg_alloc.rs 357:25]
+                    wire and_then_out: Ty67 @[reg_alloc.rs 357:25]
                     connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21]
                     match renamed_mops[0]: @[reg_alloc.rs 357:25]
                         HdlNone:
                             connect and_then_out, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25]
                         HdlSome(_match_arm_value_143):
-                            wire alu_branch_mop: Ty62 @[unit.rs 129:1]
-                            connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1]
-                            match _match_arm_value_143: @[unit.rs 129:1]
+                            wire alu_branch_mop: Ty67 @[unit.rs 128:1]
+                            connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1]
+                            match _match_arm_value_143: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_144):
-                                    connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 129:1]
+                                    connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_145):
                                     skip
                                 LoadStore(_match_arm_value_146):
@@ -2960,9 +2963,9 @@ circuit reg_alloc:
                         HdlNone:
                             wire _uninit_expr_13: Ty46
                             invalidate _uninit_expr_13
-                            connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 361:25]
+                            connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 361:25]
                         HdlSome(_match_arm_value_147):
-                            connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 359:25]
+                            connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 359:25]
                     match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21]
                         HdlNone:
                             skip
@@ -2980,24 +2983,24 @@ circuit reg_alloc:
                 connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 343:17]
             HdlSome(_match_arm_value_149):
                 skip
-        when not(unit_0.input_insn.ready): @[reg_alloc.rs 346:13]
+        when not(unit_0.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13]
             connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 348:17]
         match selected_unit_indexes[1]: @[reg_alloc.rs 351:13]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_150):
                 when eq(_match_arm_value_150, UInt<64>(0h0)): @[reg_alloc.rs 353:17]
-                    wire and_then_out_1: Ty62 @[reg_alloc.rs 357:25]
+                    wire and_then_out_1: Ty67 @[reg_alloc.rs 357:25]
                     connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21]
                     match renamed_mops[1]: @[reg_alloc.rs 357:25]
                         HdlNone:
                             connect and_then_out_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25]
                         HdlSome(_match_arm_value_151):
-                            wire alu_branch_mop_1: Ty62 @[unit.rs 129:1]
-                            connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1]
-                            match _match_arm_value_151: @[unit.rs 129:1]
+                            wire alu_branch_mop_1: Ty67 @[unit.rs 128:1]
+                            connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1]
+                            match _match_arm_value_151: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_152):
-                                    connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 129:1]
+                                    connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_153):
                                     skip
                                 LoadStore(_match_arm_value_154):
@@ -3007,9 +3010,9 @@ circuit reg_alloc:
                         HdlNone:
                             wire _uninit_expr_14: Ty46
                             invalidate _uninit_expr_14
-                            connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 361:25]
+                            connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 361:25]
                         HdlSome(_match_arm_value_155):
-                            connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 359:25]
+                            connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 359:25]
                     match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21]
                         HdlNone:
                             skip
@@ -3022,49 +3025,48 @@ circuit reg_alloc:
                             connect _bundle_literal_expr_211.value, _match_arm_value_156
                             connect _bundle_literal_expr_209.unit_out_reg, _bundle_literal_expr_211
                             connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_209) @[reg_alloc.rs 374:25]
-        wire _bundle_literal_expr_212: Ty68
-        wire _array_literal_expr_75: Ty67[2]
-        connect _array_literal_expr_75[0], {|HdlNone, HdlSome: Ty66|}(HdlNone)
-        connect _array_literal_expr_75[1], {|HdlNone, HdlSome: Ty66|}(HdlNone)
+        wire _bundle_literal_expr_212: Ty66
+        wire _array_literal_expr_75: Ty65[2]
+        connect _array_literal_expr_75[0], {|HdlNone, HdlSome: Ty64|}(HdlNone)
+        connect _array_literal_expr_75[1], {|HdlNone, HdlSome: Ty64|}(HdlNone)
         connect _bundle_literal_expr_212.unit_output_writes, _array_literal_expr_75
         wire _bundle_literal_expr_213: Ty2
         invalidate _bundle_literal_expr_213
         connect _bundle_literal_expr_212._phantom, _bundle_literal_expr_213
-        connect unit_0.unit_forwarding_info, _bundle_literal_expr_212 @[reg_alloc.rs 389:9]
-        connect unit_0.`output`.ready, UInt<1>(0h0) @[reg_alloc.rs 400:9]
-        connect unit_0.cancel_input.data, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 402:9]
+        connect unit_0.unit_to_reg_alloc.unit_forwarding_info, _bundle_literal_expr_212 @[reg_alloc.rs 389:9]
+        connect unit_0.unit_to_reg_alloc.cancel_input, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 401:9]
         inst unit_1 of alu_branch_1 @[reg_alloc.rs 311:13]
         connect unit_1.cd, cd @[reg_alloc.rs 313:9]
         inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 326:13]
         connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9]
-        wire _uninit_expr_15: Ty78
+        wire _uninit_expr_15: Ty77
         invalidate _uninit_expr_15
         connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_15 @[reg_alloc.rs 330:9]
         connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9]
-        connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9]
+        connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9]
         match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13]
             HdlNone:
                 connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 343:17]
             HdlSome(_match_arm_value_157):
                 skip
-        when not(unit_1.input_insn.ready): @[reg_alloc.rs 346:13]
+        when not(unit_1.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13]
             connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 348:17]
         match selected_unit_indexes[0]: @[reg_alloc.rs 351:13]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_158):
                 when eq(_match_arm_value_158, UInt<64>(0h1)): @[reg_alloc.rs 353:17]
-                    wire and_then_out_2: Ty62 @[reg_alloc.rs 357:25]
+                    wire and_then_out_2: Ty67 @[reg_alloc.rs 357:25]
                     connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21]
                     match renamed_mops[0]: @[reg_alloc.rs 357:25]
                         HdlNone:
                             connect and_then_out_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25]
                         HdlSome(_match_arm_value_159):
-                            wire alu_branch_mop_2: Ty62 @[unit.rs 129:1]
-                            connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1]
-                            match _match_arm_value_159: @[unit.rs 129:1]
+                            wire alu_branch_mop_2: Ty67 @[unit.rs 128:1]
+                            connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1]
+                            match _match_arm_value_159: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_160):
-                                    connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 129:1]
+                                    connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_161):
                                     skip
                                 LoadStore(_match_arm_value_162):
@@ -3074,9 +3076,9 @@ circuit reg_alloc:
                         HdlNone:
                             wire _uninit_expr_16: Ty46
                             invalidate _uninit_expr_16
-                            connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 361:25]
+                            connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 361:25]
                         HdlSome(_match_arm_value_163):
-                            connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 359:25]
+                            connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 359:25]
                     match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21]
                         HdlNone:
                             skip
@@ -3094,24 +3096,24 @@ circuit reg_alloc:
                 connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 343:17]
             HdlSome(_match_arm_value_165):
                 skip
-        when not(unit_1.input_insn.ready): @[reg_alloc.rs 346:13]
+        when not(unit_1.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13]
             connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 348:17]
         match selected_unit_indexes[1]: @[reg_alloc.rs 351:13]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_166):
                 when eq(_match_arm_value_166, UInt<64>(0h1)): @[reg_alloc.rs 353:17]
-                    wire and_then_out_3: Ty62 @[reg_alloc.rs 357:25]
+                    wire and_then_out_3: Ty67 @[reg_alloc.rs 357:25]
                     connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21]
                     match renamed_mops[1]: @[reg_alloc.rs 357:25]
                         HdlNone:
                             connect and_then_out_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25]
                         HdlSome(_match_arm_value_167):
-                            wire alu_branch_mop_3: Ty62 @[unit.rs 129:1]
-                            connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1]
-                            match _match_arm_value_167: @[unit.rs 129:1]
+                            wire alu_branch_mop_3: Ty67 @[unit.rs 128:1]
+                            connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1]
+                            match _match_arm_value_167: @[unit.rs 128:1]
                                 AluBranch(_match_arm_value_168):
-                                    connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 129:1]
+                                    connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 128:1]
                                 L2RegisterFile(_match_arm_value_169):
                                     skip
                                 LoadStore(_match_arm_value_170):
@@ -3121,9 +3123,9 @@ circuit reg_alloc:
                         HdlNone:
                             wire _uninit_expr_17: Ty46
                             invalidate _uninit_expr_17
-                            connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 361:25]
+                            connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 361:25]
                         HdlSome(_match_arm_value_171):
-                            connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 359:25]
+                            connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 359:25]
                     match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21]
                         HdlNone:
                             skip
@@ -3136,34 +3138,28 @@ circuit reg_alloc:
                             connect _bundle_literal_expr_219.value, _match_arm_value_172
                             connect _bundle_literal_expr_217.unit_out_reg, _bundle_literal_expr_219
                             connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_217) @[reg_alloc.rs 374:25]
-        wire _bundle_literal_expr_220: Ty68
-        wire _array_literal_expr_76: Ty67[2]
-        connect _array_literal_expr_76[0], {|HdlNone, HdlSome: Ty66|}(HdlNone)
-        connect _array_literal_expr_76[1], {|HdlNone, HdlSome: Ty66|}(HdlNone)
+        wire _bundle_literal_expr_220: Ty66
+        wire _array_literal_expr_76: Ty65[2]
+        connect _array_literal_expr_76[0], {|HdlNone, HdlSome: Ty64|}(HdlNone)
+        connect _array_literal_expr_76[1], {|HdlNone, HdlSome: Ty64|}(HdlNone)
         connect _bundle_literal_expr_220.unit_output_writes, _array_literal_expr_76
         wire _bundle_literal_expr_221: Ty2
         invalidate _bundle_literal_expr_221
         connect _bundle_literal_expr_220._phantom, _bundle_literal_expr_221
-        connect unit_1.unit_forwarding_info, _bundle_literal_expr_220 @[reg_alloc.rs 389:9]
-        connect unit_1.`output`.ready, UInt<1>(0h0) @[reg_alloc.rs 400:9]
-        connect unit_1.cancel_input.data, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 402:9]
-    module alu_branch: @[alu_branch.rs 18:1]
-        input cd: Ty0 @[alu_branch.rs 21:29]
-        input input_insn: Ty63 @[alu_branch.rs 24:11]
-        input unit_forwarding_info: Ty68 @[alu_branch.rs 27:11]
-        input cancel_input: Ty71 @[alu_branch.rs 30:11]
-        output `output`: Ty76 @[alu_branch.rs 33:11]
-        inst unit_base of unit_base @[alu_branch.rs 35:21]
-        connect unit_base.input_insn, input_insn @[alu_branch.rs 40:5]
-        connect unit_base.cd, cd @[alu_branch.rs 41:5]
-        connect unit_base.unit_forwarding_info, unit_forwarding_info @[alu_branch.rs 42:5]
-        connect unit_base.cancel_input, cancel_input @[alu_branch.rs 43:5]
-        connect unit_base.ready_mop.ready, UInt<1>(0h1) @[alu_branch.rs 45:5]
-        connect `output`.data, {|HdlNone, HdlSome: Ty74|}(HdlNone) @[alu_branch.rs 46:5]
+        connect unit_1.unit_to_reg_alloc.unit_forwarding_info, _bundle_literal_expr_220 @[reg_alloc.rs 389:9]
+        connect unit_1.unit_to_reg_alloc.cancel_input, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 401:9]
+    module alu_branch: @[alu_branch.rs 17:1]
+        input cd: Ty0 @[alu_branch.rs 20:29]
+        output unit_to_reg_alloc: Ty75 @[alu_branch.rs 28:11]
+        inst unit_base of unit_base @[alu_branch.rs 33:21]
+        connect unit_to_reg_alloc, unit_base.unit_to_reg_alloc @[alu_branch.rs 39:5]
+        connect unit_base.cd, cd @[alu_branch.rs 40:5]
+        connect unit_base.execute_start.ready, UInt<1>(0h1) @[alu_branch.rs 41:5]
+        connect unit_base.execute_end, {|HdlNone, HdlSome: Ty83|}(HdlNone) @[alu_branch.rs 42:5]
     module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1]
         input cd: Ty0 @[unit_free_regs_tracker.rs 14:29]
-        input free_in: Ty79[1] @[unit_free_regs_tracker.rs 17:11]
-        output alloc_out: Ty79[1] @[unit_free_regs_tracker.rs 20:11]
+        input free_in: Ty78[1] @[unit_free_regs_tracker.rs 17:11]
+        output alloc_out: Ty78[1] @[unit_free_regs_tracker.rs 20:11]
         wire _array_literal_expr: UInt<1>[16]
         connect _array_literal_expr[0], UInt<1>(0h0)
         connect _array_literal_expr[1], UInt<1>(0h0)
@@ -3183,7 +3179,7 @@ circuit reg_alloc:
         connect _array_literal_expr[15], UInt<1>(0h0)
         regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25]
         connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9]
-        wire firing_data: Ty78 @[ready_valid.rs 30:27]
+        wire firing_data: Ty77 @[ready_valid.rs 30:27]
         connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when free_in[0].ready: @[ready_valid.rs 33:9]
             connect firing_data, free_in[0].data @[ready_valid.rs 34:13]
@@ -3494,7 +3490,7 @@ circuit reg_alloc:
             ; lhs: UInt<4>
             ; rhs: UInt<65>
             connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21]
-        wire firing_data_1: Ty78 @[ready_valid.rs 30:27]
+        wire firing_data_1: Ty77 @[ready_valid.rs 30:27]
         connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when alloc_out[0].ready: @[ready_valid.rs 33:9]
             connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]
@@ -3507,23 +3503,18 @@ circuit reg_alloc:
             connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13]
         else:
             connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13]
-    module alu_branch_1: @[alu_branch.rs 18:1]
-        input cd: Ty0 @[alu_branch.rs 21:29]
-        input input_insn: Ty63 @[alu_branch.rs 24:11]
-        input unit_forwarding_info: Ty68 @[alu_branch.rs 27:11]
-        input cancel_input: Ty71 @[alu_branch.rs 30:11]
-        output `output`: Ty76 @[alu_branch.rs 33:11]
-        inst unit_base of unit_base_1 @[alu_branch.rs 35:21]
-        connect unit_base.input_insn, input_insn @[alu_branch.rs 40:5]
-        connect unit_base.cd, cd @[alu_branch.rs 41:5]
-        connect unit_base.unit_forwarding_info, unit_forwarding_info @[alu_branch.rs 42:5]
-        connect unit_base.cancel_input, cancel_input @[alu_branch.rs 43:5]
-        connect unit_base.ready_mop.ready, UInt<1>(0h1) @[alu_branch.rs 45:5]
-        connect `output`.data, {|HdlNone, HdlSome: Ty74|}(HdlNone) @[alu_branch.rs 46:5]
+    module alu_branch_1: @[alu_branch.rs 17:1]
+        input cd: Ty0 @[alu_branch.rs 20:29]
+        output unit_to_reg_alloc: Ty75 @[alu_branch.rs 28:11]
+        inst unit_base of unit_base_1 @[alu_branch.rs 33:21]
+        connect unit_to_reg_alloc, unit_base.unit_to_reg_alloc @[alu_branch.rs 39:5]
+        connect unit_base.cd, cd @[alu_branch.rs 40:5]
+        connect unit_base.execute_start.ready, UInt<1>(0h1) @[alu_branch.rs 41:5]
+        connect unit_base.execute_end, {|HdlNone, HdlSome: Ty83|}(HdlNone) @[alu_branch.rs 42:5]
     module unit_free_regs_tracker_1: @[unit_free_regs_tracker.rs 7:1]
         input cd: Ty0 @[unit_free_regs_tracker.rs 14:29]
-        input free_in: Ty79[1] @[unit_free_regs_tracker.rs 17:11]
-        output alloc_out: Ty79[1] @[unit_free_regs_tracker.rs 20:11]
+        input free_in: Ty78[1] @[unit_free_regs_tracker.rs 17:11]
+        output alloc_out: Ty78[1] @[unit_free_regs_tracker.rs 20:11]
         wire _array_literal_expr: UInt<1>[16]
         connect _array_literal_expr[0], UInt<1>(0h0)
         connect _array_literal_expr[1], UInt<1>(0h0)
@@ -3543,7 +3534,7 @@ circuit reg_alloc:
         connect _array_literal_expr[15], UInt<1>(0h0)
         regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25]
         connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9]
-        wire firing_data: Ty78 @[ready_valid.rs 30:27]
+        wire firing_data: Ty77 @[ready_valid.rs 30:27]
         connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when free_in[0].ready: @[ready_valid.rs 33:9]
             connect firing_data, free_in[0].data @[ready_valid.rs 34:13]
@@ -3854,7 +3845,7 @@ circuit reg_alloc:
             ; lhs: UInt<4>
             ; rhs: UInt<65>
             connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21]
-        wire firing_data_1: Ty78 @[ready_valid.rs 30:27]
+        wire firing_data_1: Ty77 @[ready_valid.rs 30:27]
         connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when alloc_out[0].ready: @[ready_valid.rs 33:9]
             connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]
@@ -3867,23 +3858,12 @@ circuit reg_alloc:
             connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13]
         else:
             connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13]
-    module unit_base: @[unit_base.rs 32:1]
-        input cd: Ty0 @[unit_base.rs 39:29]
-        input unit_forwarding_info: Ty68 @[unit_base.rs 42:11]
-        input input_insn: Ty63 @[unit_base.rs 44:41]
-        input cancel_input: Ty71 @[unit_base.rs 48:11]
-        output ready_mop: Ty83 @[unit_base.rs 51:50]
-        wire and_then_out: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_1: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_2: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_3: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_4: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_5: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_6: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_7: Ty85 @[unit_base.rs 66:17]
-        connect input_insn.ready, UInt<1>(0h0) @[unit_base.rs 45:5]
-        connect cancel_input.ready, UInt<1>(0h1) @[unit_base.rs 49:5]
-        connect ready_mop.data, {|HdlNone, HdlSome: Ty81|}(HdlNone) @[unit_base.rs 52:5]
+    module unit_base: @[unit_base.rs 225:1]
+        input cd: Ty0 @[unit_base.rs 236:29]
+        output unit_to_reg_alloc: Ty75 @[unit_base.rs 239:11]
+        output execute_start: Ty82 @[unit_base.rs 241:58]
+        input execute_end: Ty84 @[unit_base.rs 244:11]
+        connect execute_start.data, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[unit_base.rs 246:5]
         wire _array_literal_expr: Ty88[8]
         connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone)
@@ -3893,497 +3873,2844 @@ circuit reg_alloc:
         connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone)
-        regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 55:25]
-        wire input_index: Ty85 @[unit_base.rs 61:23]
-        match in_flight_ops[0]: @[unit_base.rs 66:17]
+        regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 251:25]
+        wire empty_op_index_0: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_0: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[0]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value):
-                connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[1]: @[unit_base.rs 66:17]
+                connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_1: UInt<1>[3]
+                        wire _array_literal_expr_2: UInt<1>[3]
+                        connect _array_literal_expr_2[0], UInt<1>(0h1)
+                        connect _array_literal_expr_2[1], UInt<1>(0h1)
+                        connect _array_literal_expr_2[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[0], eq(_match_arm_value.src_ready_flags[0], _array_literal_expr_2[0])
+                        wire _array_literal_expr_3: UInt<1>[3]
+                        connect _array_literal_expr_3[0], UInt<1>(0h1)
+                        connect _array_literal_expr_3[1], UInt<1>(0h1)
+                        connect _array_literal_expr_3[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[1], eq(_match_arm_value.src_ready_flags[1], _array_literal_expr_3[1])
+                        wire _array_literal_expr_4: UInt<1>[3]
+                        connect _array_literal_expr_4[0], UInt<1>(0h1)
+                        connect _array_literal_expr_4[1], UInt<1>(0h1)
+                        connect _array_literal_expr_4[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[2], eq(_match_arm_value.src_ready_flags[2], _array_literal_expr_4[2])
+                        wire _cast_array_to_bits_expr: UInt<1>[3]
+                        connect _cast_array_to_bits_expr[0], _array_literal_expr_1[0]
+                        connect _cast_array_to_bits_expr[1], _array_literal_expr_1[1]
+                        connect _cast_array_to_bits_expr[2], _array_literal_expr_1[2]
+                        wire _cast_to_bits_expr: UInt<3>
+                        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
+                        when andr(_cast_to_bits_expr): @[unit_base.rs 182:21]
+                            connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_1: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_1: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[1]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_1):
-                connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 66:17]
-        wire or_out: Ty85 @[function.rs 166:5]
-        connect or_out, and_then_out_1 @[function.rs 166:5]
-        match and_then_out: @[function.rs 166:5]
+                connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_1.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_5: UInt<1>[3]
+                        wire _array_literal_expr_6: UInt<1>[3]
+                        connect _array_literal_expr_6[0], UInt<1>(0h1)
+                        connect _array_literal_expr_6[1], UInt<1>(0h1)
+                        connect _array_literal_expr_6[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[0], eq(_match_arm_value_1.src_ready_flags[0], _array_literal_expr_6[0])
+                        wire _array_literal_expr_7: UInt<1>[3]
+                        connect _array_literal_expr_7[0], UInt<1>(0h1)
+                        connect _array_literal_expr_7[1], UInt<1>(0h1)
+                        connect _array_literal_expr_7[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[1], eq(_match_arm_value_1.src_ready_flags[1], _array_literal_expr_7[1])
+                        wire _array_literal_expr_8: UInt<1>[3]
+                        connect _array_literal_expr_8[0], UInt<1>(0h1)
+                        connect _array_literal_expr_8[1], UInt<1>(0h1)
+                        connect _array_literal_expr_8[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[2], eq(_match_arm_value_1.src_ready_flags[2], _array_literal_expr_8[2])
+                        wire _cast_array_to_bits_expr_1: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_1[0], _array_literal_expr_5[0]
+                        connect _cast_array_to_bits_expr_1[1], _array_literal_expr_5[1]
+                        connect _cast_array_to_bits_expr_1[2], _array_literal_expr_5[2]
+                        wire _cast_to_bits_expr_1: UInt<3>
+                        connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
+                        when andr(_cast_to_bits_expr_1): @[unit_base.rs 182:21]
+                            connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr: Ty90
+        connect _bundle_literal_expr.empty_op_index, empty_op_index_1
+        connect _bundle_literal_expr.ready_op_index, ready_op_index_1
+        connect or_out, _bundle_literal_expr.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_1: Ty90
+        connect _bundle_literal_expr_1.empty_op_index, empty_op_index_0
+        connect _bundle_literal_expr_1.ready_op_index, ready_op_index_0
+        match _bundle_literal_expr_1.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_2):
-                connect or_out, and_then_out @[function.rs 166:5]
-        match in_flight_ops[2]: @[unit_base.rs 66:17]
-            HdlNone:
-                connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
-            HdlSome(_match_arm_value_3):
-                connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[3]: @[unit_base.rs 66:17]
-            HdlNone:
-                connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
-            HdlSome(_match_arm_value_4):
-                connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 66:17]
-        wire or_out_1: Ty85 @[function.rs 166:5]
-        connect or_out_1, and_then_out_3 @[function.rs 166:5]
-        match and_then_out_2: @[function.rs 166:5]
+                wire _bundle_literal_expr_2: Ty90
+                connect _bundle_literal_expr_2.empty_op_index, empty_op_index_0
+                connect _bundle_literal_expr_2.ready_op_index, ready_op_index_0
+                connect or_out, _bundle_literal_expr_2.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_1: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_3: Ty90
+        connect _bundle_literal_expr_3.empty_op_index, empty_op_index_1
+        connect _bundle_literal_expr_3.ready_op_index, ready_op_index_1
+        connect or_out_1, _bundle_literal_expr_3.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_4: Ty90
+        connect _bundle_literal_expr_4.empty_op_index, empty_op_index_0
+        connect _bundle_literal_expr_4.ready_op_index, ready_op_index_0
+        match _bundle_literal_expr_4.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
+            HdlSome(_match_arm_value_3):
+                wire _bundle_literal_expr_5: Ty90
+                connect _bundle_literal_expr_5.empty_op_index, empty_op_index_0
+                connect _bundle_literal_expr_5.ready_op_index, ready_op_index_0
+                connect or_out_1, _bundle_literal_expr_5.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_2: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_2: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[2]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 189:13]
+            HdlSome(_match_arm_value_4):
+                connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_4.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_9: UInt<1>[3]
+                        wire _array_literal_expr_10: UInt<1>[3]
+                        connect _array_literal_expr_10[0], UInt<1>(0h1)
+                        connect _array_literal_expr_10[1], UInt<1>(0h1)
+                        connect _array_literal_expr_10[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[0], eq(_match_arm_value_4.src_ready_flags[0], _array_literal_expr_10[0])
+                        wire _array_literal_expr_11: UInt<1>[3]
+                        connect _array_literal_expr_11[0], UInt<1>(0h1)
+                        connect _array_literal_expr_11[1], UInt<1>(0h1)
+                        connect _array_literal_expr_11[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[1], eq(_match_arm_value_4.src_ready_flags[1], _array_literal_expr_11[1])
+                        wire _array_literal_expr_12: UInt<1>[3]
+                        connect _array_literal_expr_12[0], UInt<1>(0h1)
+                        connect _array_literal_expr_12[1], UInt<1>(0h1)
+                        connect _array_literal_expr_12[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[2], eq(_match_arm_value_4.src_ready_flags[2], _array_literal_expr_12[2])
+                        wire _cast_array_to_bits_expr_2: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_2[0], _array_literal_expr_9[0]
+                        connect _cast_array_to_bits_expr_2[1], _array_literal_expr_9[1]
+                        connect _cast_array_to_bits_expr_2[2], _array_literal_expr_9[2]
+                        wire _cast_to_bits_expr_2: UInt<3>
+                        connect _cast_to_bits_expr_2, cat(_cast_array_to_bits_expr_2[2], cat(_cast_array_to_bits_expr_2[1], _cast_array_to_bits_expr_2[0]))
+                        when andr(_cast_to_bits_expr_2): @[unit_base.rs 182:21]
+                            connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_3: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_3: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[3]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_5):
-                connect or_out_1, and_then_out_2 @[function.rs 166:5]
-        wire or_out_2: Ty85 @[function.rs 166:5]
-        connect or_out_2, or_out_1 @[function.rs 166:5]
-        match or_out: @[function.rs 166:5]
+                connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_5.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_13: UInt<1>[3]
+                        wire _array_literal_expr_14: UInt<1>[3]
+                        connect _array_literal_expr_14[0], UInt<1>(0h1)
+                        connect _array_literal_expr_14[1], UInt<1>(0h1)
+                        connect _array_literal_expr_14[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[0], eq(_match_arm_value_5.src_ready_flags[0], _array_literal_expr_14[0])
+                        wire _array_literal_expr_15: UInt<1>[3]
+                        connect _array_literal_expr_15[0], UInt<1>(0h1)
+                        connect _array_literal_expr_15[1], UInt<1>(0h1)
+                        connect _array_literal_expr_15[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[1], eq(_match_arm_value_5.src_ready_flags[1], _array_literal_expr_15[1])
+                        wire _array_literal_expr_16: UInt<1>[3]
+                        connect _array_literal_expr_16[0], UInt<1>(0h1)
+                        connect _array_literal_expr_16[1], UInt<1>(0h1)
+                        connect _array_literal_expr_16[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[2], eq(_match_arm_value_5.src_ready_flags[2], _array_literal_expr_16[2])
+                        wire _cast_array_to_bits_expr_3: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_3[0], _array_literal_expr_13[0]
+                        connect _cast_array_to_bits_expr_3[1], _array_literal_expr_13[1]
+                        connect _cast_array_to_bits_expr_3[2], _array_literal_expr_13[2]
+                        wire _cast_to_bits_expr_3: UInt<3>
+                        connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr_3[2], cat(_cast_array_to_bits_expr_3[1], _cast_array_to_bits_expr_3[0]))
+                        when andr(_cast_to_bits_expr_3): @[unit_base.rs 182:21]
+                            connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_2: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_6: Ty90
+        connect _bundle_literal_expr_6.empty_op_index, empty_op_index_3
+        connect _bundle_literal_expr_6.ready_op_index, ready_op_index_3
+        connect or_out_2, _bundle_literal_expr_6.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_7: Ty90
+        connect _bundle_literal_expr_7.empty_op_index, empty_op_index_2
+        connect _bundle_literal_expr_7.ready_op_index, ready_op_index_2
+        match _bundle_literal_expr_7.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_6):
-                connect or_out_2, or_out @[function.rs 166:5]
-        match in_flight_ops[4]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_8: Ty90
+                connect _bundle_literal_expr_8.empty_op_index, empty_op_index_2
+                connect _bundle_literal_expr_8.ready_op_index, ready_op_index_2
+                connect or_out_2, _bundle_literal_expr_8.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_3: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_9: Ty90
+        connect _bundle_literal_expr_9.empty_op_index, empty_op_index_3
+        connect _bundle_literal_expr_9.ready_op_index, ready_op_index_3
+        connect or_out_3, _bundle_literal_expr_9.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_10: Ty90
+        connect _bundle_literal_expr_10.empty_op_index, empty_op_index_2
+        connect _bundle_literal_expr_10.ready_op_index, ready_op_index_2
+        match _bundle_literal_expr_10.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                skip
             HdlSome(_match_arm_value_7):
-                connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[5]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_11: Ty90
+                connect _bundle_literal_expr_11.empty_op_index, empty_op_index_2
+                connect _bundle_literal_expr_11.ready_op_index, ready_op_index_2
+                connect or_out_3, _bundle_literal_expr_11.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_4: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_12: Ty90
+        connect _bundle_literal_expr_12.empty_op_index, or_out_2
+        connect _bundle_literal_expr_12.ready_op_index, or_out_3
+        connect or_out_4, _bundle_literal_expr_12.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_13: Ty90
+        connect _bundle_literal_expr_13.empty_op_index, or_out
+        connect _bundle_literal_expr_13.ready_op_index, or_out_1
+        match _bundle_literal_expr_13.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
-                connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                skip
             HdlSome(_match_arm_value_8):
-                connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 66:17]
-        wire or_out_3: Ty85 @[function.rs 166:5]
-        connect or_out_3, and_then_out_5 @[function.rs 166:5]
-        match and_then_out_4: @[function.rs 166:5]
+                wire _bundle_literal_expr_14: Ty90
+                connect _bundle_literal_expr_14.empty_op_index, or_out
+                connect _bundle_literal_expr_14.ready_op_index, or_out_1
+                connect or_out_4, _bundle_literal_expr_14.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_5: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_15: Ty90
+        connect _bundle_literal_expr_15.empty_op_index, or_out_2
+        connect _bundle_literal_expr_15.ready_op_index, or_out_3
+        connect or_out_5, _bundle_literal_expr_15.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_16: Ty90
+        connect _bundle_literal_expr_16.empty_op_index, or_out
+        connect _bundle_literal_expr_16.ready_op_index, or_out_1
+        match _bundle_literal_expr_16.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_9):
-                connect or_out_3, and_then_out_4 @[function.rs 166:5]
-        match in_flight_ops[6]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_17: Ty90
+                connect _bundle_literal_expr_17.empty_op_index, or_out
+                connect _bundle_literal_expr_17.ready_op_index, or_out_1
+                connect or_out_5, _bundle_literal_expr_17.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_4: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_4: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[4]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_10):
-                connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[7]: @[unit_base.rs 66:17]
+                connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_10.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_17: UInt<1>[3]
+                        wire _array_literal_expr_18: UInt<1>[3]
+                        connect _array_literal_expr_18[0], UInt<1>(0h1)
+                        connect _array_literal_expr_18[1], UInt<1>(0h1)
+                        connect _array_literal_expr_18[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[0], eq(_match_arm_value_10.src_ready_flags[0], _array_literal_expr_18[0])
+                        wire _array_literal_expr_19: UInt<1>[3]
+                        connect _array_literal_expr_19[0], UInt<1>(0h1)
+                        connect _array_literal_expr_19[1], UInt<1>(0h1)
+                        connect _array_literal_expr_19[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[1], eq(_match_arm_value_10.src_ready_flags[1], _array_literal_expr_19[1])
+                        wire _array_literal_expr_20: UInt<1>[3]
+                        connect _array_literal_expr_20[0], UInt<1>(0h1)
+                        connect _array_literal_expr_20[1], UInt<1>(0h1)
+                        connect _array_literal_expr_20[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[2], eq(_match_arm_value_10.src_ready_flags[2], _array_literal_expr_20[2])
+                        wire _cast_array_to_bits_expr_4: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_4[0], _array_literal_expr_17[0]
+                        connect _cast_array_to_bits_expr_4[1], _array_literal_expr_17[1]
+                        connect _cast_array_to_bits_expr_4[2], _array_literal_expr_17[2]
+                        wire _cast_to_bits_expr_4: UInt<3>
+                        connect _cast_to_bits_expr_4, cat(_cast_array_to_bits_expr_4[2], cat(_cast_array_to_bits_expr_4[1], _cast_array_to_bits_expr_4[0]))
+                        when andr(_cast_to_bits_expr_4): @[unit_base.rs 182:21]
+                            connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_5: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_5: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[5]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_11):
-                connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 66:17]
-        wire or_out_4: Ty85 @[function.rs 166:5]
-        connect or_out_4, and_then_out_7 @[function.rs 166:5]
-        match and_then_out_6: @[function.rs 166:5]
+                connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_11.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_21: UInt<1>[3]
+                        wire _array_literal_expr_22: UInt<1>[3]
+                        connect _array_literal_expr_22[0], UInt<1>(0h1)
+                        connect _array_literal_expr_22[1], UInt<1>(0h1)
+                        connect _array_literal_expr_22[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[0], eq(_match_arm_value_11.src_ready_flags[0], _array_literal_expr_22[0])
+                        wire _array_literal_expr_23: UInt<1>[3]
+                        connect _array_literal_expr_23[0], UInt<1>(0h1)
+                        connect _array_literal_expr_23[1], UInt<1>(0h1)
+                        connect _array_literal_expr_23[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[1], eq(_match_arm_value_11.src_ready_flags[1], _array_literal_expr_23[1])
+                        wire _array_literal_expr_24: UInt<1>[3]
+                        connect _array_literal_expr_24[0], UInt<1>(0h1)
+                        connect _array_literal_expr_24[1], UInt<1>(0h1)
+                        connect _array_literal_expr_24[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[2], eq(_match_arm_value_11.src_ready_flags[2], _array_literal_expr_24[2])
+                        wire _cast_array_to_bits_expr_5: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_5[0], _array_literal_expr_21[0]
+                        connect _cast_array_to_bits_expr_5[1], _array_literal_expr_21[1]
+                        connect _cast_array_to_bits_expr_5[2], _array_literal_expr_21[2]
+                        wire _cast_to_bits_expr_5: UInt<3>
+                        connect _cast_to_bits_expr_5, cat(_cast_array_to_bits_expr_5[2], cat(_cast_array_to_bits_expr_5[1], _cast_array_to_bits_expr_5[0]))
+                        when andr(_cast_to_bits_expr_5): @[unit_base.rs 182:21]
+                            connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_6: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_18: Ty90
+        connect _bundle_literal_expr_18.empty_op_index, empty_op_index_5
+        connect _bundle_literal_expr_18.ready_op_index, ready_op_index_5
+        connect or_out_6, _bundle_literal_expr_18.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_19: Ty90
+        connect _bundle_literal_expr_19.empty_op_index, empty_op_index_4
+        connect _bundle_literal_expr_19.ready_op_index, ready_op_index_4
+        match _bundle_literal_expr_19.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_12):
-                connect or_out_4, and_then_out_6 @[function.rs 166:5]
-        wire or_out_5: Ty85 @[function.rs 166:5]
-        connect or_out_5, or_out_4 @[function.rs 166:5]
-        match or_out_3: @[function.rs 166:5]
+                wire _bundle_literal_expr_20: Ty90
+                connect _bundle_literal_expr_20.empty_op_index, empty_op_index_4
+                connect _bundle_literal_expr_20.ready_op_index, ready_op_index_4
+                connect or_out_6, _bundle_literal_expr_20.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_7: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_21: Ty90
+        connect _bundle_literal_expr_21.empty_op_index, empty_op_index_5
+        connect _bundle_literal_expr_21.ready_op_index, ready_op_index_5
+        connect or_out_7, _bundle_literal_expr_21.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_22: Ty90
+        connect _bundle_literal_expr_22.empty_op_index, empty_op_index_4
+        connect _bundle_literal_expr_22.ready_op_index, ready_op_index_4
+        match _bundle_literal_expr_22.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_13):
-                connect or_out_5, or_out_3 @[function.rs 166:5]
-        wire or_out_6: Ty85 @[function.rs 166:5]
-        connect or_out_6, or_out_5 @[function.rs 166:5]
-        match or_out_2: @[function.rs 166:5]
+                wire _bundle_literal_expr_23: Ty90
+                connect _bundle_literal_expr_23.empty_op_index, empty_op_index_4
+                connect _bundle_literal_expr_23.ready_op_index, ready_op_index_4
+                connect or_out_7, _bundle_literal_expr_23.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_6: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_6: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[6]: @[unit_base.rs 169:9]
             HdlNone:
-                skip
+                connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_14):
-                connect or_out_6, or_out_2 @[function.rs 166:5]
-        connect input_index, or_out_6 @[unit_base.rs 62:5]
-        wire input_in_flight_op: Ty88 @[unit_base.rs 73:30]
-        connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 74:5]
-        wire firing_data: Ty62 @[ready_valid.rs 30:27]
-        connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9]
-        when input_insn.ready: @[ready_valid.rs 33:9]
-            connect firing_data, input_insn.data @[ready_valid.rs 34:13]
-        match firing_data: @[unit_base.rs 76:5]
+                connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_14.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_25: UInt<1>[3]
+                        wire _array_literal_expr_26: UInt<1>[3]
+                        connect _array_literal_expr_26[0], UInt<1>(0h1)
+                        connect _array_literal_expr_26[1], UInt<1>(0h1)
+                        connect _array_literal_expr_26[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[0], eq(_match_arm_value_14.src_ready_flags[0], _array_literal_expr_26[0])
+                        wire _array_literal_expr_27: UInt<1>[3]
+                        connect _array_literal_expr_27[0], UInt<1>(0h1)
+                        connect _array_literal_expr_27[1], UInt<1>(0h1)
+                        connect _array_literal_expr_27[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[1], eq(_match_arm_value_14.src_ready_flags[1], _array_literal_expr_27[1])
+                        wire _array_literal_expr_28: UInt<1>[3]
+                        connect _array_literal_expr_28[0], UInt<1>(0h1)
+                        connect _array_literal_expr_28[1], UInt<1>(0h1)
+                        connect _array_literal_expr_28[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[2], eq(_match_arm_value_14.src_ready_flags[2], _array_literal_expr_28[2])
+                        wire _cast_array_to_bits_expr_6: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_6[0], _array_literal_expr_25[0]
+                        connect _cast_array_to_bits_expr_6[1], _array_literal_expr_25[1]
+                        connect _cast_array_to_bits_expr_6[2], _array_literal_expr_25[2]
+                        wire _cast_to_bits_expr_6: UInt<3>
+                        connect _cast_to_bits_expr_6, cat(_cast_array_to_bits_expr_6[2], cat(_cast_array_to_bits_expr_6[1], _cast_array_to_bits_expr_6[0]))
+                        when andr(_cast_to_bits_expr_6): @[unit_base.rs 182:21]
+                            connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_7: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_7: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[7]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 189:13]
+            HdlSome(_match_arm_value_15):
+                connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_15.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_29: UInt<1>[3]
+                        wire _array_literal_expr_30: UInt<1>[3]
+                        connect _array_literal_expr_30[0], UInt<1>(0h1)
+                        connect _array_literal_expr_30[1], UInt<1>(0h1)
+                        connect _array_literal_expr_30[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[0], eq(_match_arm_value_15.src_ready_flags[0], _array_literal_expr_30[0])
+                        wire _array_literal_expr_31: UInt<1>[3]
+                        connect _array_literal_expr_31[0], UInt<1>(0h1)
+                        connect _array_literal_expr_31[1], UInt<1>(0h1)
+                        connect _array_literal_expr_31[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[1], eq(_match_arm_value_15.src_ready_flags[1], _array_literal_expr_31[1])
+                        wire _array_literal_expr_32: UInt<1>[3]
+                        connect _array_literal_expr_32[0], UInt<1>(0h1)
+                        connect _array_literal_expr_32[1], UInt<1>(0h1)
+                        connect _array_literal_expr_32[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[2], eq(_match_arm_value_15.src_ready_flags[2], _array_literal_expr_32[2])
+                        wire _cast_array_to_bits_expr_7: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_7[0], _array_literal_expr_29[0]
+                        connect _cast_array_to_bits_expr_7[1], _array_literal_expr_29[1]
+                        connect _cast_array_to_bits_expr_7[2], _array_literal_expr_29[2]
+                        wire _cast_to_bits_expr_7: UInt<3>
+                        connect _cast_to_bits_expr_7, cat(_cast_array_to_bits_expr_7[2], cat(_cast_array_to_bits_expr_7[1], _cast_array_to_bits_expr_7[0]))
+                        when andr(_cast_to_bits_expr_7): @[unit_base.rs 182:21]
+                            connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_8: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_24: Ty90
+        connect _bundle_literal_expr_24.empty_op_index, empty_op_index_7
+        connect _bundle_literal_expr_24.ready_op_index, ready_op_index_7
+        connect or_out_8, _bundle_literal_expr_24.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_25: Ty90
+        connect _bundle_literal_expr_25.empty_op_index, empty_op_index_6
+        connect _bundle_literal_expr_25.ready_op_index, ready_op_index_6
+        match _bundle_literal_expr_25.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_15):
-                wire input_in_flight_op_src_values: Ty86[3] @[unit_base.rs 79:13]
-                wire _array_literal_expr_1: Ty86[3]
-                wire _bundle_literal_expr: Ty65
-                connect _bundle_literal_expr.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_1: Ty64
-                connect _bundle_literal_expr_1.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr.flags, _bundle_literal_expr_1
-                connect _array_literal_expr_1[0], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr)
-                wire _bundle_literal_expr_2: Ty65
-                connect _bundle_literal_expr_2.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_3: Ty64
-                connect _bundle_literal_expr_3.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr_2.flags, _bundle_literal_expr_3
-                connect _array_literal_expr_1[1], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_2)
-                wire _bundle_literal_expr_4: Ty65
-                connect _bundle_literal_expr_4.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_5: Ty64
-                connect _bundle_literal_expr_5.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr_4.flags, _bundle_literal_expr_5
-                connect _array_literal_expr_1[2], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_4)
-                connect input_in_flight_op_src_values, _array_literal_expr_1 @[unit_base.rs 82:9]
-                match _match_arm_value_15: @[instruction.rs 502:1]
-                    AddSub(_match_arm_value_16):
-                        wire _bundle_literal_expr_6: Ty25
-                        wire _bundle_literal_expr_7: Ty23
-                        connect _bundle_literal_expr_7.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_6.unit_num, _bundle_literal_expr_7
-                        wire _bundle_literal_expr_8: Ty24
-                        connect _bundle_literal_expr_8.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_6.unit_out_reg, _bundle_literal_expr_8
-                        wire _cast_bundle_to_bits_expr: Ty57
-                        connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_6.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_6.unit_out_reg.value
-                        wire _cast_to_bits_expr: UInt<6>
-                        connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num)
-                        when neq(_cast_to_bits_expr, _match_arm_value_16.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_9: Ty25
-                        wire _bundle_literal_expr_10: Ty23
-                        connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10
-                        wire _bundle_literal_expr_11: Ty24
-                        connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11
-                        wire _cast_bundle_to_bits_expr_1: Ty57
-                        connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_9.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_9.unit_out_reg.value
-                        wire _cast_to_bits_expr_1: UInt<6>
-                        connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num)
-                        when neq(_cast_to_bits_expr_1, _match_arm_value_16.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_12: Ty25
-                        wire _bundle_literal_expr_13: Ty23
-                        connect _bundle_literal_expr_13.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_12.unit_num, _bundle_literal_expr_13
-                        wire _bundle_literal_expr_14: Ty24
-                        connect _bundle_literal_expr_14.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_12.unit_out_reg, _bundle_literal_expr_14
-                        wire _cast_bundle_to_bits_expr_2: Ty57
-                        connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_12.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_12.unit_out_reg.value
-                        wire _cast_to_bits_expr_2: UInt<6>
-                        connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num)
-                        when neq(_cast_to_bits_expr_2, _match_arm_value_16.alu_common.common.src[2]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[2], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                    AddSubI(_match_arm_value_17):
-                        wire _bundle_literal_expr_15: Ty25
-                        wire _bundle_literal_expr_16: Ty23
-                        connect _bundle_literal_expr_16.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_15.unit_num, _bundle_literal_expr_16
-                        wire _bundle_literal_expr_17: Ty24
-                        connect _bundle_literal_expr_17.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_15.unit_out_reg, _bundle_literal_expr_17
-                        wire _cast_bundle_to_bits_expr_3: Ty57
-                        connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_15.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_15.unit_out_reg.value
-                        wire _cast_to_bits_expr_3: UInt<6>
-                        connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num)
-                        when neq(_cast_to_bits_expr_3, _match_arm_value_17.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_18: Ty25
-                        wire _bundle_literal_expr_19: Ty23
-                        connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19
-                        wire _bundle_literal_expr_20: Ty24
-                        connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20
-                        wire _cast_bundle_to_bits_expr_4: Ty57
-                        connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_18.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_18.unit_out_reg.value
-                        wire _cast_to_bits_expr_4: UInt<6>
-                        connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num)
-                        when neq(_cast_to_bits_expr_4, _match_arm_value_17.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                    Logical(_match_arm_value_18):
-                        wire _bundle_literal_expr_21: Ty25
-                        wire _bundle_literal_expr_22: Ty23
-                        connect _bundle_literal_expr_22.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22
-                        wire _bundle_literal_expr_23: Ty24
-                        connect _bundle_literal_expr_23.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23
-                        wire _cast_bundle_to_bits_expr_5: Ty57
-                        connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_21.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_21.unit_out_reg.value
-                        wire _cast_to_bits_expr_5: UInt<6>
-                        connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num)
-                        when neq(_cast_to_bits_expr_5, _match_arm_value_18.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_24: Ty25
-                        wire _bundle_literal_expr_25: Ty23
-                        connect _bundle_literal_expr_25.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_24.unit_num, _bundle_literal_expr_25
-                        wire _bundle_literal_expr_26: Ty24
-                        connect _bundle_literal_expr_26.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_24.unit_out_reg, _bundle_literal_expr_26
-                        wire _cast_bundle_to_bits_expr_6: Ty57
-                        connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_24.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_24.unit_out_reg.value
-                        wire _cast_to_bits_expr_6: UInt<6>
-                        connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num)
-                        when neq(_cast_to_bits_expr_6, _match_arm_value_18.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                wire _bundle_literal_expr_27: Ty87
-                connect _bundle_literal_expr_27.mop, _match_arm_value_15
-                connect _bundle_literal_expr_27.src_values, input_in_flight_op_src_values
-                connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_27) @[unit_base.rs 97:9]
-        match in_flight_ops[0]: @[unit_base.rs 107:9]
+            HdlSome(_match_arm_value_16):
+                wire _bundle_literal_expr_26: Ty90
+                connect _bundle_literal_expr_26.empty_op_index, empty_op_index_6
+                connect _bundle_literal_expr_26.ready_op_index, ready_op_index_6
+                connect or_out_8, _bundle_literal_expr_26.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_9: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_27: Ty90
+        connect _bundle_literal_expr_27.empty_op_index, empty_op_index_7
+        connect _bundle_literal_expr_27.ready_op_index, ready_op_index_7
+        connect or_out_9, _bundle_literal_expr_27.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_28: Ty90
+        connect _bundle_literal_expr_28.empty_op_index, empty_op_index_6
+        connect _bundle_literal_expr_28.ready_op_index, ready_op_index_6
+        match _bundle_literal_expr_28.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_19):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_19, UInt<64>(0h0)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[0], input_in_flight_op @[unit_base.rs 126:17]
+                skip
+            HdlSome(_match_arm_value_17):
+                wire _bundle_literal_expr_29: Ty90
+                connect _bundle_literal_expr_29.empty_op_index, empty_op_index_6
+                connect _bundle_literal_expr_29.ready_op_index, ready_op_index_6
+                connect or_out_9, _bundle_literal_expr_29.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_10: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_30: Ty90
+        connect _bundle_literal_expr_30.empty_op_index, or_out_8
+        connect _bundle_literal_expr_30.ready_op_index, or_out_9
+        connect or_out_10, _bundle_literal_expr_30.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_31: Ty90
+        connect _bundle_literal_expr_31.empty_op_index, or_out_6
+        connect _bundle_literal_expr_31.ready_op_index, or_out_7
+        match _bundle_literal_expr_31.empty_op_index: @[unit_base.rs 203:29]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_18):
+                wire _bundle_literal_expr_32: Ty90
+                connect _bundle_literal_expr_32.empty_op_index, or_out_6
+                connect _bundle_literal_expr_32.ready_op_index, or_out_7
+                connect or_out_10, _bundle_literal_expr_32.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_11: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_33: Ty90
+        connect _bundle_literal_expr_33.empty_op_index, or_out_8
+        connect _bundle_literal_expr_33.ready_op_index, or_out_9
+        connect or_out_11, _bundle_literal_expr_33.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_34: Ty90
+        connect _bundle_literal_expr_34.empty_op_index, or_out_6
+        connect _bundle_literal_expr_34.ready_op_index, or_out_7
+        match _bundle_literal_expr_34.ready_op_index: @[unit_base.rs 204:29]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_19):
+                wire _bundle_literal_expr_35: Ty90
+                connect _bundle_literal_expr_35.empty_op_index, or_out_6
+                connect _bundle_literal_expr_35.ready_op_index, or_out_7
+                connect or_out_11, _bundle_literal_expr_35.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_12: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_36: Ty90
+        connect _bundle_literal_expr_36.empty_op_index, or_out_10
+        connect _bundle_literal_expr_36.ready_op_index, or_out_11
+        connect or_out_12, _bundle_literal_expr_36.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_37: Ty90
+        connect _bundle_literal_expr_37.empty_op_index, or_out_4
+        connect _bundle_literal_expr_37.ready_op_index, or_out_5
+        match _bundle_literal_expr_37.empty_op_index: @[unit_base.rs 203:29]
+            HdlNone:
+                skip
             HdlSome(_match_arm_value_20):
-                wire firing_data_1: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_1, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_1, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_1: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_21):
-                        wire dest_reg: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_20.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_22):
-                                connect dest_reg, _match_arm_value_22.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_23):
-                                connect dest_reg, _match_arm_value_23.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_24):
-                                connect dest_reg, _match_arm_value_24.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_21.which.value, dest_reg.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[1]: @[unit_base.rs 107:9]
+                wire _bundle_literal_expr_38: Ty90
+                connect _bundle_literal_expr_38.empty_op_index, or_out_4
+                connect _bundle_literal_expr_38.ready_op_index, or_out_5
+                connect or_out_12, _bundle_literal_expr_38.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_13: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_39: Ty90
+        connect _bundle_literal_expr_39.empty_op_index, or_out_10
+        connect _bundle_literal_expr_39.ready_op_index, or_out_11
+        connect or_out_13, _bundle_literal_expr_39.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_40: Ty90
+        connect _bundle_literal_expr_40.empty_op_index, or_out_4
+        connect _bundle_literal_expr_40.ready_op_index, or_out_5
+        match _bundle_literal_expr_40.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_25):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_25, UInt<64>(0h1)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[1], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_26):
-                wire firing_data_2: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_2, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_2, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_2: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_27):
-                        wire dest_reg_1: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_26.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_28):
-                                connect dest_reg_1, _match_arm_value_28.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_29):
-                                connect dest_reg_1, _match_arm_value_29.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_30):
-                                connect dest_reg_1, _match_arm_value_30.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_27.which.value, dest_reg_1.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[2]: @[unit_base.rs 107:9]
+                skip
+            HdlSome(_match_arm_value_21):
+                wire _bundle_literal_expr_41: Ty90
+                connect _bundle_literal_expr_41.empty_op_index, or_out_4
+                connect _bundle_literal_expr_41.ready_op_index, or_out_5
+                connect or_out_13, _bundle_literal_expr_41.ready_op_index @[unit_base.rs 204:29]
+        wire in_flight_ops_summary: Ty90 @[unit_base.rs 257:33]
+        wire _bundle_literal_expr_42: Ty90
+        connect _bundle_literal_expr_42.empty_op_index, or_out_12
+        connect _bundle_literal_expr_42.ready_op_index, or_out_13
+        connect in_flight_ops_summary, _bundle_literal_expr_42 @[unit_base.rs 258:5]
+        wire is_some_out: UInt<1> @[unit_base.rs 262:9]
+        connect is_some_out, UInt<1>(0h0) @[unit_base.rs 262:9]
+        match in_flight_ops_summary.empty_op_index: @[unit_base.rs 262:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                skip
+            HdlSome(_match_arm_value_22):
+                connect is_some_out, UInt<1>(0h1) @[unit_base.rs 262:9]
+        connect unit_to_reg_alloc.input_insn.ready, is_some_out @[unit_base.rs 260:5]
+        connect unit_to_reg_alloc.`output`, {|HdlNone, HdlSome: Ty73|}(HdlNone) @[unit_base.rs 266:5]
+        wire input_in_flight_op: Ty88 @[unit_base.rs 272:30]
+        connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 273:5]
+        wire firing_data: Ty67 @[ready_valid.rs 30:27]
+        connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9]
+        when unit_to_reg_alloc.input_insn.ready: @[ready_valid.rs 33:9]
+            connect firing_data, unit_to_reg_alloc.input_insn.data @[ready_valid.rs 34:13]
+        match firing_data: @[unit_base.rs 275:5]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_23):
+                wire input_mop_src_regs: UInt<6>[3] @[unit_base.rs 277:34]
+                wire _array_literal_expr_33: UInt<6>[3]
+                wire _bundle_literal_expr_43: Ty25
+                wire _bundle_literal_expr_44: Ty23
+                connect _bundle_literal_expr_44.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_43.unit_num, _bundle_literal_expr_44
+                wire _bundle_literal_expr_45: Ty24
+                connect _bundle_literal_expr_45.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_43.unit_out_reg, _bundle_literal_expr_45
+                wire _cast_bundle_to_bits_expr: Ty57
+                connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_43.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_43.unit_out_reg.value
+                wire _cast_to_bits_expr_8: UInt<6>
+                connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num)
+                connect _array_literal_expr_33[0], _cast_to_bits_expr_8
+                wire _bundle_literal_expr_46: Ty25
+                wire _bundle_literal_expr_47: Ty23
+                connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47
+                wire _bundle_literal_expr_48: Ty24
+                connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48
+                wire _cast_bundle_to_bits_expr_1: Ty57
+                connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_46.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_46.unit_out_reg.value
+                wire _cast_to_bits_expr_9: UInt<6>
+                connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num)
+                connect _array_literal_expr_33[1], _cast_to_bits_expr_9
+                wire _bundle_literal_expr_49: Ty25
+                wire _bundle_literal_expr_50: Ty23
+                connect _bundle_literal_expr_50.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_49.unit_num, _bundle_literal_expr_50
+                wire _bundle_literal_expr_51: Ty24
+                connect _bundle_literal_expr_51.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_49.unit_out_reg, _bundle_literal_expr_51
+                wire _cast_bundle_to_bits_expr_2: Ty57
+                connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_49.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_49.unit_out_reg.value
+                wire _cast_to_bits_expr_10: UInt<6>
+                connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num)
+                connect _array_literal_expr_33[2], _cast_to_bits_expr_10
+                connect input_mop_src_regs, _array_literal_expr_33 @[unit_base.rs 278:9]
+                match _match_arm_value_23: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_24):
+                        connect input_mop_src_regs[0], _match_arm_value_24.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_24.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[2], _match_arm_value_24.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_25):
+                        connect input_mop_src_regs[0], _match_arm_value_25.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_25.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_26):
+                        connect input_mop_src_regs[0], _match_arm_value_26.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_26.alu_common.common.src[1] @[instruction.rs 36:13]
+                wire input_in_flight_op_src_ready_flags: UInt<1>[3] @[unit_base.rs 285:13]
+                wire _bundle_literal_expr_52: Ty25
+                wire _bundle_literal_expr_53: Ty23
+                connect _bundle_literal_expr_53.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_52.unit_num, _bundle_literal_expr_53
+                wire _bundle_literal_expr_54: Ty24
+                connect _bundle_literal_expr_54.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_52.unit_out_reg, _bundle_literal_expr_54
+                wire _cast_bundle_to_bits_expr_3: Ty57
+                connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_52.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_52.unit_out_reg.value
+                wire _cast_to_bits_expr_11: UInt<6>
+                connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num)
+                connect input_in_flight_op_src_ready_flags[0], eq(_cast_to_bits_expr_11, input_mop_src_regs[0]) @[unit_base.rs 289:13]
+                wire _bundle_literal_expr_55: Ty25
+                wire _bundle_literal_expr_56: Ty23
+                connect _bundle_literal_expr_56.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_55.unit_num, _bundle_literal_expr_56
+                wire _bundle_literal_expr_57: Ty24
+                connect _bundle_literal_expr_57.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_55.unit_out_reg, _bundle_literal_expr_57
+                wire _cast_bundle_to_bits_expr_4: Ty57
+                connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_55.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_55.unit_out_reg.value
+                wire _cast_to_bits_expr_12: UInt<6>
+                connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num)
+                connect input_in_flight_op_src_ready_flags[1], eq(_cast_to_bits_expr_12, input_mop_src_regs[1]) @[unit_base.rs 289:13]
+                wire _bundle_literal_expr_58: Ty25
+                wire _bundle_literal_expr_59: Ty23
+                connect _bundle_literal_expr_59.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_58.unit_num, _bundle_literal_expr_59
+                wire _bundle_literal_expr_60: Ty24
+                connect _bundle_literal_expr_60.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_58.unit_out_reg, _bundle_literal_expr_60
+                wire _cast_bundle_to_bits_expr_5: Ty57
+                connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_58.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_58.unit_out_reg.value
+                wire _cast_to_bits_expr_13: UInt<6>
+                connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num)
+                connect input_in_flight_op_src_ready_flags[2], eq(_cast_to_bits_expr_13, input_mop_src_regs[2]) @[unit_base.rs 289:13]
+                wire dest_reg: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_23: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_27):
+                        connect dest_reg, _match_arm_value_27.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_28):
+                        connect dest_reg, _match_arm_value_28.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_29):
+                        connect dest_reg, _match_arm_value_29.alu_common.common.dest @[instruction.rs 538:1]
+                wire cmp_ne: UInt<1> @[enum_.rs 396:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 398:9]
                     HdlNone:
-                        skip
+                        wire _bundle_literal_expr_61: Ty69
+                        connect _bundle_literal_expr_61.which, dest_reg
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_61): @[enum_.rs 410:17]
+                            HdlNone:
+                                connect cmp_ne, UInt<1>(0h0) @[enum_.rs 412:32]
+                            HdlSome(_match_arm_value_30):
+                                connect cmp_ne, UInt<1>(0h1) @[enum_.rs 411:35]
                     HdlSome(_match_arm_value_31):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_31, UInt<64>(0h2)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[2], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_32):
-                wire firing_data_3: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_3, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_3, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_3: @[unit_base.rs 109:13]
+                        wire _bundle_literal_expr_62: Ty69
+                        connect _bundle_literal_expr_62.which, dest_reg
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_62): @[enum_.rs 402:17]
+                            HdlNone:
+                                connect cmp_ne, UInt<1>(0h1) @[enum_.rs 404:32]
+                            HdlSome(_match_arm_value_32):
+                                connect cmp_ne, neq(_match_arm_value_31.which.value, _match_arm_value_32.which.value) @[enum_.rs 403:37]
+                when cmp_ne: @[unit_base.rs 299:9]
+                    wire _bundle_literal_expr_63: Ty87
+                    connect _bundle_literal_expr_63.state, {|Ready, Running, CanceledAndRunning|}(Ready)
+                    connect _bundle_literal_expr_63.mop, _match_arm_value_23
+                    connect _bundle_literal_expr_63.src_ready_flags, input_in_flight_op_src_ready_flags
+                    connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_63) @[unit_base.rs 305:13]
+                match in_flight_ops_summary.empty_op_index: @[unit_base.rs 318:9]
                     HdlNone:
                         skip
                     HdlSome(_match_arm_value_33):
-                        wire dest_reg_2: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_32.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_34):
-                                connect dest_reg_2, _match_arm_value_34.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_35):
-                                connect dest_reg_2, _match_arm_value_35.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_36):
-                                connect dest_reg_2, _match_arm_value_36.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_33.which.value, dest_reg_2.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[3]: @[unit_base.rs 107:9]
+                        connect in_flight_ops[_match_arm_value_33], input_in_flight_op @[unit_base.rs 319:13]
+        wire in_flight_op_next_state: Ty91[8] @[unit_base.rs 324:35]
+        wire in_flight_op_next_src_ready_flags: UInt<1>[3][8] @[unit_base.rs 327:9]
+        wire in_flight_op_canceling: UInt<1>[8] @[unit_base.rs 329:34]
+        wire in_flight_op_execute_starting: UInt<1>[8] @[unit_base.rs 331:41]
+        wire in_flight_op_execute_ending: UInt<1>[8] @[unit_base.rs 333:39]
+        wire _array_literal_expr_34: UInt<1>[3]
+        connect _array_literal_expr_34[0], UInt<1>(0h0)
+        connect _array_literal_expr_34[1], UInt<1>(0h0)
+        connect _array_literal_expr_34[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[0], _array_literal_expr_34 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[0], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[0], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[0], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[0]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_34):
+                wire dest_reg_1: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_34.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_35):
+                        connect dest_reg_1, _match_arm_value_35.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_36):
+                        connect dest_reg_1, _match_arm_value_36.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_37):
+                        connect dest_reg_1, _match_arm_value_37.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_0: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_35: UInt<6>[3]
+                wire _bundle_literal_expr_64: Ty25
+                wire _bundle_literal_expr_65: Ty23
+                connect _bundle_literal_expr_65.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_64.unit_num, _bundle_literal_expr_65
+                wire _bundle_literal_expr_66: Ty24
+                connect _bundle_literal_expr_66.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_64.unit_out_reg, _bundle_literal_expr_66
+                wire _cast_bundle_to_bits_expr_6: Ty57
+                connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_64.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_64.unit_out_reg.value
+                wire _cast_to_bits_expr_14: UInt<6>
+                connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num)
+                connect _array_literal_expr_35[0], _cast_to_bits_expr_14
+                wire _bundle_literal_expr_67: Ty25
+                wire _bundle_literal_expr_68: Ty23
+                connect _bundle_literal_expr_68.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_67.unit_num, _bundle_literal_expr_68
+                wire _bundle_literal_expr_69: Ty24
+                connect _bundle_literal_expr_69.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_67.unit_out_reg, _bundle_literal_expr_69
+                wire _cast_bundle_to_bits_expr_7: Ty57
+                connect _cast_bundle_to_bits_expr_7.unit_num, _bundle_literal_expr_67.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_7.unit_out_reg, _bundle_literal_expr_67.unit_out_reg.value
+                wire _cast_to_bits_expr_15: UInt<6>
+                connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num)
+                connect _array_literal_expr_35[1], _cast_to_bits_expr_15
+                wire _bundle_literal_expr_70: Ty25
+                wire _bundle_literal_expr_71: Ty23
+                connect _bundle_literal_expr_71.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_70.unit_num, _bundle_literal_expr_71
+                wire _bundle_literal_expr_72: Ty24
+                connect _bundle_literal_expr_72.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_70.unit_out_reg, _bundle_literal_expr_72
+                wire _cast_bundle_to_bits_expr_8: Ty57
+                connect _cast_bundle_to_bits_expr_8.unit_num, _bundle_literal_expr_70.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_8.unit_out_reg, _bundle_literal_expr_70.unit_out_reg.value
+                wire _cast_to_bits_expr_16: UInt<6>
+                connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num)
+                connect _array_literal_expr_35[2], _cast_to_bits_expr_16
+                connect in_flight_op_src_regs_0, _array_literal_expr_35 @[unit_base.rs 356:13]
+                match _match_arm_value_34.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_38):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_38.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_38.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[2], _match_arm_value_38.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_39):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_39.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_39.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_40):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_40.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_40.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[0], _match_arm_value_34.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_37):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_37, UInt<64>(0h3)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[3], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_38):
-                wire firing_data_4: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_4, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_4, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_4: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_41):
+                        wire _bundle_literal_expr_73: Ty25
+                        wire _bundle_literal_expr_74: Ty23
+                        connect _bundle_literal_expr_74.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_73.unit_num, _bundle_literal_expr_74
+                        connect _bundle_literal_expr_73.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_9: Ty57
+                        connect _cast_bundle_to_bits_expr_9.unit_num, _bundle_literal_expr_73.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_9.unit_out_reg, _bundle_literal_expr_73.unit_out_reg.value
+                        wire _cast_to_bits_expr_17: UInt<6>
+                        connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_9.unit_out_reg, _cast_bundle_to_bits_expr_9.unit_num)
+                        when eq(_cast_to_bits_expr_17, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_75: Ty25
+                        wire _bundle_literal_expr_76: Ty23
+                        connect _bundle_literal_expr_76.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_75.unit_num, _bundle_literal_expr_76
+                        connect _bundle_literal_expr_75.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_10: Ty57
+                        connect _cast_bundle_to_bits_expr_10.unit_num, _bundle_literal_expr_75.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_10.unit_out_reg, _bundle_literal_expr_75.unit_out_reg.value
+                        wire _cast_to_bits_expr_18: UInt<6>
+                        connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_10.unit_out_reg, _cast_bundle_to_bits_expr_10.unit_num)
+                        when eq(_cast_to_bits_expr_18, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_77: Ty25
+                        wire _bundle_literal_expr_78: Ty23
+                        connect _bundle_literal_expr_78.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_77.unit_num, _bundle_literal_expr_78
+                        connect _bundle_literal_expr_77.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_11: Ty57
+                        connect _cast_bundle_to_bits_expr_11.unit_num, _bundle_literal_expr_77.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_11.unit_out_reg, _bundle_literal_expr_77.unit_out_reg.value
+                        wire _cast_to_bits_expr_19: UInt<6>
+                        connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num)
+                        when eq(_cast_to_bits_expr_19, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_39):
-                        wire dest_reg_3: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_38.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_40):
-                                connect dest_reg_3, _match_arm_value_40.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_41):
-                                connect dest_reg_3, _match_arm_value_41.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_42):
-                                connect dest_reg_3, _match_arm_value_42.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_39.which.value, dest_reg_3.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[4]: @[unit_base.rs 107:9]
-            HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                    HdlSome(_match_arm_value_42):
+                        wire _bundle_literal_expr_79: Ty25
+                        wire _bundle_literal_expr_80: Ty23
+                        connect _bundle_literal_expr_80.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_79.unit_num, _bundle_literal_expr_80
+                        connect _bundle_literal_expr_79.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_12: Ty57
+                        connect _cast_bundle_to_bits_expr_12.unit_num, _bundle_literal_expr_79.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_12.unit_out_reg, _bundle_literal_expr_79.unit_out_reg.value
+                        wire _cast_to_bits_expr_20: UInt<6>
+                        connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num)
+                        when eq(_cast_to_bits_expr_20, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_81: Ty25
+                        wire _bundle_literal_expr_82: Ty23
+                        connect _bundle_literal_expr_82.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_81.unit_num, _bundle_literal_expr_82
+                        connect _bundle_literal_expr_81.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_13: Ty57
+                        connect _cast_bundle_to_bits_expr_13.unit_num, _bundle_literal_expr_81.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_13.unit_out_reg, _bundle_literal_expr_81.unit_out_reg.value
+                        wire _cast_to_bits_expr_21: UInt<6>
+                        connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num)
+                        when eq(_cast_to_bits_expr_21, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_83: Ty25
+                        wire _bundle_literal_expr_84: Ty23
+                        connect _bundle_literal_expr_84.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_83.unit_num, _bundle_literal_expr_84
+                        connect _bundle_literal_expr_83.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_14: Ty57
+                        connect _cast_bundle_to_bits_expr_14.unit_num, _bundle_literal_expr_83.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_14.unit_out_reg, _bundle_literal_expr_83.unit_out_reg.value
+                        wire _cast_to_bits_expr_22: UInt<6>
+                        connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num)
+                        when eq(_cast_to_bits_expr_22, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_85: Ty69
+                        connect _bundle_literal_expr_85.which, dest_reg_1
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_85): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_43):
+                                connect cmp_eq, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_44):
+                        wire _bundle_literal_expr_86: Ty69
+                        connect _bundle_literal_expr_86.which, dest_reg_1
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_86): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_45):
+                                connect cmp_eq, eq(_match_arm_value_44.which.value, _match_arm_value_45.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[0], cmp_eq @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_43):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_43, UInt<64>(0h4)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[4], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_44):
-                wire firing_data_5: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_5, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_5, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_5: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_46):
+                        when eq(dest_reg_1.value, _match_arm_value_46.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[0], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_1: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_1, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_1, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_1: @[unit_base.rs 410:13]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_45):
-                        wire dest_reg_4: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_44.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_46):
-                                connect dest_reg_4, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_47):
-                                connect dest_reg_4, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_48):
-                                connect dest_reg_4, _match_arm_value_48.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_45.which.value, dest_reg_4.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[5]: @[unit_base.rs 107:9]
-            HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                    HdlSome(_match_arm_value_47):
+                        wire dest_reg_2: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_47.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_48):
+                                connect dest_reg_2, _match_arm_value_48.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_49):
+                                connect dest_reg_2, _match_arm_value_49.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_50):
+                                connect dest_reg_2, _match_arm_value_50.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_1.value, dest_reg_2.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[0], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_34.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[0]: @[unit_base.rs 434:13]
                     HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_49):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_49, UInt<64>(0h5)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[5], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_50):
-                wire firing_data_6: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_6, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_6, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_6: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
+                        connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
                     HdlSome(_match_arm_value_51):
-                        wire dest_reg_5: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_50.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_52):
-                                connect dest_reg_5, _match_arm_value_52.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_53):
-                                connect dest_reg_5, _match_arm_value_53.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_54):
-                                connect dest_reg_5, _match_arm_value_54.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_51.which.value, dest_reg_5.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[6]: @[unit_base.rs 107:9]
+                        wire _bundle_literal_expr_87: Ty87
+                        connect _bundle_literal_expr_87.state, _match_arm_value_51
+                        connect _bundle_literal_expr_87.mop, _match_arm_value_34.mop
+                        connect _bundle_literal_expr_87.src_ready_flags, _match_arm_value_34.src_ready_flags
+                        connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_87) @[unit_base.rs 435:17]
+        wire _array_literal_expr_36: UInt<1>[3]
+        connect _array_literal_expr_36[0], UInt<1>(0h0)
+        connect _array_literal_expr_36[1], UInt<1>(0h0)
+        connect _array_literal_expr_36[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[1], _array_literal_expr_36 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[1], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[1], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[1], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[1]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_52):
+                wire dest_reg_3: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_52.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_53):
+                        connect dest_reg_3, _match_arm_value_53.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_54):
+                        connect dest_reg_3, _match_arm_value_54.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_55):
+                        connect dest_reg_3, _match_arm_value_55.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_1: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_37: UInt<6>[3]
+                wire _bundle_literal_expr_88: Ty25
+                wire _bundle_literal_expr_89: Ty23
+                connect _bundle_literal_expr_89.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_88.unit_num, _bundle_literal_expr_89
+                wire _bundle_literal_expr_90: Ty24
+                connect _bundle_literal_expr_90.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_88.unit_out_reg, _bundle_literal_expr_90
+                wire _cast_bundle_to_bits_expr_15: Ty57
+                connect _cast_bundle_to_bits_expr_15.unit_num, _bundle_literal_expr_88.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_15.unit_out_reg, _bundle_literal_expr_88.unit_out_reg.value
+                wire _cast_to_bits_expr_23: UInt<6>
+                connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_15.unit_out_reg, _cast_bundle_to_bits_expr_15.unit_num)
+                connect _array_literal_expr_37[0], _cast_to_bits_expr_23
+                wire _bundle_literal_expr_91: Ty25
+                wire _bundle_literal_expr_92: Ty23
+                connect _bundle_literal_expr_92.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_91.unit_num, _bundle_literal_expr_92
+                wire _bundle_literal_expr_93: Ty24
+                connect _bundle_literal_expr_93.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_91.unit_out_reg, _bundle_literal_expr_93
+                wire _cast_bundle_to_bits_expr_16: Ty57
+                connect _cast_bundle_to_bits_expr_16.unit_num, _bundle_literal_expr_91.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_16.unit_out_reg, _bundle_literal_expr_91.unit_out_reg.value
+                wire _cast_to_bits_expr_24: UInt<6>
+                connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_16.unit_out_reg, _cast_bundle_to_bits_expr_16.unit_num)
+                connect _array_literal_expr_37[1], _cast_to_bits_expr_24
+                wire _bundle_literal_expr_94: Ty25
+                wire _bundle_literal_expr_95: Ty23
+                connect _bundle_literal_expr_95.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_94.unit_num, _bundle_literal_expr_95
+                wire _bundle_literal_expr_96: Ty24
+                connect _bundle_literal_expr_96.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_94.unit_out_reg, _bundle_literal_expr_96
+                wire _cast_bundle_to_bits_expr_17: Ty57
+                connect _cast_bundle_to_bits_expr_17.unit_num, _bundle_literal_expr_94.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_17.unit_out_reg, _bundle_literal_expr_94.unit_out_reg.value
+                wire _cast_to_bits_expr_25: UInt<6>
+                connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_17.unit_out_reg, _cast_bundle_to_bits_expr_17.unit_num)
+                connect _array_literal_expr_37[2], _cast_to_bits_expr_25
+                connect in_flight_op_src_regs_1, _array_literal_expr_37 @[unit_base.rs 356:13]
+                match _match_arm_value_52.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_56):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_56.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_56.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[2], _match_arm_value_56.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_57):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_57.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_57.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_58):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_58.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_58.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[1], _match_arm_value_52.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_55):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_55, UInt<64>(0h6)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[6], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_56):
-                wire firing_data_7: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_7, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_7, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_7: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_59):
+                        wire _bundle_literal_expr_97: Ty25
+                        wire _bundle_literal_expr_98: Ty23
+                        connect _bundle_literal_expr_98.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_97.unit_num, _bundle_literal_expr_98
+                        connect _bundle_literal_expr_97.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_18: Ty57
+                        connect _cast_bundle_to_bits_expr_18.unit_num, _bundle_literal_expr_97.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_18.unit_out_reg, _bundle_literal_expr_97.unit_out_reg.value
+                        wire _cast_to_bits_expr_26: UInt<6>
+                        connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num)
+                        when eq(_cast_to_bits_expr_26, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_99: Ty25
+                        wire _bundle_literal_expr_100: Ty23
+                        connect _bundle_literal_expr_100.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_99.unit_num, _bundle_literal_expr_100
+                        connect _bundle_literal_expr_99.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_19: Ty57
+                        connect _cast_bundle_to_bits_expr_19.unit_num, _bundle_literal_expr_99.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_19.unit_out_reg, _bundle_literal_expr_99.unit_out_reg.value
+                        wire _cast_to_bits_expr_27: UInt<6>
+                        connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num)
+                        when eq(_cast_to_bits_expr_27, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_101: Ty25
+                        wire _bundle_literal_expr_102: Ty23
+                        connect _bundle_literal_expr_102.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_101.unit_num, _bundle_literal_expr_102
+                        connect _bundle_literal_expr_101.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_20: Ty57
+                        connect _cast_bundle_to_bits_expr_20.unit_num, _bundle_literal_expr_101.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_20.unit_out_reg, _bundle_literal_expr_101.unit_out_reg.value
+                        wire _cast_to_bits_expr_28: UInt<6>
+                        connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num)
+                        when eq(_cast_to_bits_expr_28, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_57):
-                        wire dest_reg_6: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_56.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_58):
-                                connect dest_reg_6, _match_arm_value_58.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_59):
-                                connect dest_reg_6, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_60):
-                                connect dest_reg_6, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_57.which.value, dest_reg_6.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[7]: @[unit_base.rs 107:9]
+                    HdlSome(_match_arm_value_60):
+                        wire _bundle_literal_expr_103: Ty25
+                        wire _bundle_literal_expr_104: Ty23
+                        connect _bundle_literal_expr_104.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_103.unit_num, _bundle_literal_expr_104
+                        connect _bundle_literal_expr_103.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_21: Ty57
+                        connect _cast_bundle_to_bits_expr_21.unit_num, _bundle_literal_expr_103.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_21.unit_out_reg, _bundle_literal_expr_103.unit_out_reg.value
+                        wire _cast_to_bits_expr_29: UInt<6>
+                        connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num)
+                        when eq(_cast_to_bits_expr_29, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_105: Ty25
+                        wire _bundle_literal_expr_106: Ty23
+                        connect _bundle_literal_expr_106.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_105.unit_num, _bundle_literal_expr_106
+                        connect _bundle_literal_expr_105.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_22: Ty57
+                        connect _cast_bundle_to_bits_expr_22.unit_num, _bundle_literal_expr_105.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_22.unit_out_reg, _bundle_literal_expr_105.unit_out_reg.value
+                        wire _cast_to_bits_expr_30: UInt<6>
+                        connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_22.unit_out_reg, _cast_bundle_to_bits_expr_22.unit_num)
+                        when eq(_cast_to_bits_expr_30, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_107: Ty25
+                        wire _bundle_literal_expr_108: Ty23
+                        connect _bundle_literal_expr_108.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_107.unit_num, _bundle_literal_expr_108
+                        connect _bundle_literal_expr_107.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_23: Ty57
+                        connect _cast_bundle_to_bits_expr_23.unit_num, _bundle_literal_expr_107.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_23.unit_out_reg, _bundle_literal_expr_107.unit_out_reg.value
+                        wire _cast_to_bits_expr_31: UInt<6>
+                        connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_23.unit_out_reg, _cast_bundle_to_bits_expr_23.unit_num)
+                        when eq(_cast_to_bits_expr_31, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_1: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_109: Ty69
+                        connect _bundle_literal_expr_109.which, dest_reg_3
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_109): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_1, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_61):
+                                connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_62):
+                        wire _bundle_literal_expr_110: Ty69
+                        connect _bundle_literal_expr_110.which, dest_reg_3
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_110): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_63):
+                                connect cmp_eq_1, eq(_match_arm_value_62.which.value, _match_arm_value_63.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[1], cmp_eq_1 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_64):
+                        when eq(dest_reg_3.value, _match_arm_value_64.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[1], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_2: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_2, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_2, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_2: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_65):
+                        wire dest_reg_4: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_65.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_66):
+                                connect dest_reg_4, _match_arm_value_66.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_67):
+                                connect dest_reg_4, _match_arm_value_67.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_68):
+                                connect dest_reg_4, _match_arm_value_68.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_3.value, dest_reg_4.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[1], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_52.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[1]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_69):
+                        wire _bundle_literal_expr_111: Ty87
+                        connect _bundle_literal_expr_111.state, _match_arm_value_69
+                        connect _bundle_literal_expr_111.mop, _match_arm_value_52.mop
+                        connect _bundle_literal_expr_111.src_ready_flags, _match_arm_value_52.src_ready_flags
+                        connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_111) @[unit_base.rs 435:17]
+        wire _array_literal_expr_38: UInt<1>[3]
+        connect _array_literal_expr_38[0], UInt<1>(0h0)
+        connect _array_literal_expr_38[1], UInt<1>(0h0)
+        connect _array_literal_expr_38[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[2], _array_literal_expr_38 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[2], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[2], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[2], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[2]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_70):
+                wire dest_reg_5: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_70.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_71):
+                        connect dest_reg_5, _match_arm_value_71.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_72):
+                        connect dest_reg_5, _match_arm_value_72.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_73):
+                        connect dest_reg_5, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_2: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_39: UInt<6>[3]
+                wire _bundle_literal_expr_112: Ty25
+                wire _bundle_literal_expr_113: Ty23
+                connect _bundle_literal_expr_113.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_112.unit_num, _bundle_literal_expr_113
+                wire _bundle_literal_expr_114: Ty24
+                connect _bundle_literal_expr_114.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_112.unit_out_reg, _bundle_literal_expr_114
+                wire _cast_bundle_to_bits_expr_24: Ty57
+                connect _cast_bundle_to_bits_expr_24.unit_num, _bundle_literal_expr_112.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_24.unit_out_reg, _bundle_literal_expr_112.unit_out_reg.value
+                wire _cast_to_bits_expr_32: UInt<6>
+                connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_24.unit_out_reg, _cast_bundle_to_bits_expr_24.unit_num)
+                connect _array_literal_expr_39[0], _cast_to_bits_expr_32
+                wire _bundle_literal_expr_115: Ty25
+                wire _bundle_literal_expr_116: Ty23
+                connect _bundle_literal_expr_116.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_115.unit_num, _bundle_literal_expr_116
+                wire _bundle_literal_expr_117: Ty24
+                connect _bundle_literal_expr_117.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_115.unit_out_reg, _bundle_literal_expr_117
+                wire _cast_bundle_to_bits_expr_25: Ty57
+                connect _cast_bundle_to_bits_expr_25.unit_num, _bundle_literal_expr_115.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_25.unit_out_reg, _bundle_literal_expr_115.unit_out_reg.value
+                wire _cast_to_bits_expr_33: UInt<6>
+                connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_25.unit_out_reg, _cast_bundle_to_bits_expr_25.unit_num)
+                connect _array_literal_expr_39[1], _cast_to_bits_expr_33
+                wire _bundle_literal_expr_118: Ty25
+                wire _bundle_literal_expr_119: Ty23
+                connect _bundle_literal_expr_119.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_118.unit_num, _bundle_literal_expr_119
+                wire _bundle_literal_expr_120: Ty24
+                connect _bundle_literal_expr_120.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_118.unit_out_reg, _bundle_literal_expr_120
+                wire _cast_bundle_to_bits_expr_26: Ty57
+                connect _cast_bundle_to_bits_expr_26.unit_num, _bundle_literal_expr_118.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_26.unit_out_reg, _bundle_literal_expr_118.unit_out_reg.value
+                wire _cast_to_bits_expr_34: UInt<6>
+                connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_26.unit_out_reg, _cast_bundle_to_bits_expr_26.unit_num)
+                connect _array_literal_expr_39[2], _cast_to_bits_expr_34
+                connect in_flight_op_src_regs_2, _array_literal_expr_39 @[unit_base.rs 356:13]
+                match _match_arm_value_70.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_74):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_74.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_74.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[2], _match_arm_value_74.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_75):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_75.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_75.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_76):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_76.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_76.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[2], _match_arm_value_70.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_61):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_61, UInt<64>(0h7)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[7], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_62):
-                wire firing_data_8: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_8, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_8, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_8: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_77):
+                        wire _bundle_literal_expr_121: Ty25
+                        wire _bundle_literal_expr_122: Ty23
+                        connect _bundle_literal_expr_122.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_121.unit_num, _bundle_literal_expr_122
+                        connect _bundle_literal_expr_121.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_27: Ty57
+                        connect _cast_bundle_to_bits_expr_27.unit_num, _bundle_literal_expr_121.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_27.unit_out_reg, _bundle_literal_expr_121.unit_out_reg.value
+                        wire _cast_to_bits_expr_35: UInt<6>
+                        connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_27.unit_out_reg, _cast_bundle_to_bits_expr_27.unit_num)
+                        when eq(_cast_to_bits_expr_35, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_123: Ty25
+                        wire _bundle_literal_expr_124: Ty23
+                        connect _bundle_literal_expr_124.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_123.unit_num, _bundle_literal_expr_124
+                        connect _bundle_literal_expr_123.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_28: Ty57
+                        connect _cast_bundle_to_bits_expr_28.unit_num, _bundle_literal_expr_123.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_28.unit_out_reg, _bundle_literal_expr_123.unit_out_reg.value
+                        wire _cast_to_bits_expr_36: UInt<6>
+                        connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num)
+                        when eq(_cast_to_bits_expr_36, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_125: Ty25
+                        wire _bundle_literal_expr_126: Ty23
+                        connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126
+                        connect _bundle_literal_expr_125.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_29: Ty57
+                        connect _cast_bundle_to_bits_expr_29.unit_num, _bundle_literal_expr_125.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_29.unit_out_reg, _bundle_literal_expr_125.unit_out_reg.value
+                        wire _cast_to_bits_expr_37: UInt<6>
+                        connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_29.unit_out_reg, _cast_bundle_to_bits_expr_29.unit_num)
+                        when eq(_cast_to_bits_expr_37, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_63):
-                        wire dest_reg_7: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_62.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_64):
-                                connect dest_reg_7, _match_arm_value_64.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_65):
-                                connect dest_reg_7, _match_arm_value_65.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_66):
-                                connect dest_reg_7, _match_arm_value_66.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_63.which.value, dest_reg_7.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-    module unit_base_1: @[unit_base.rs 32:1]
-        input cd: Ty0 @[unit_base.rs 39:29]
-        input unit_forwarding_info: Ty68 @[unit_base.rs 42:11]
-        input input_insn: Ty63 @[unit_base.rs 44:41]
-        input cancel_input: Ty71 @[unit_base.rs 48:11]
-        output ready_mop: Ty83 @[unit_base.rs 51:50]
-        wire and_then_out: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_1: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_2: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_3: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_4: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_5: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_6: Ty85 @[unit_base.rs 66:17]
-        wire and_then_out_7: Ty85 @[unit_base.rs 66:17]
-        connect input_insn.ready, UInt<1>(0h0) @[unit_base.rs 45:5]
-        connect cancel_input.ready, UInt<1>(0h1) @[unit_base.rs 49:5]
-        connect ready_mop.data, {|HdlNone, HdlSome: Ty81|}(HdlNone) @[unit_base.rs 52:5]
+                    HdlSome(_match_arm_value_78):
+                        wire _bundle_literal_expr_127: Ty25
+                        wire _bundle_literal_expr_128: Ty23
+                        connect _bundle_literal_expr_128.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_127.unit_num, _bundle_literal_expr_128
+                        connect _bundle_literal_expr_127.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_30: Ty57
+                        connect _cast_bundle_to_bits_expr_30.unit_num, _bundle_literal_expr_127.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_30.unit_out_reg, _bundle_literal_expr_127.unit_out_reg.value
+                        wire _cast_to_bits_expr_38: UInt<6>
+                        connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_30.unit_out_reg, _cast_bundle_to_bits_expr_30.unit_num)
+                        when eq(_cast_to_bits_expr_38, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_129: Ty25
+                        wire _bundle_literal_expr_130: Ty23
+                        connect _bundle_literal_expr_130.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_129.unit_num, _bundle_literal_expr_130
+                        connect _bundle_literal_expr_129.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_31: Ty57
+                        connect _cast_bundle_to_bits_expr_31.unit_num, _bundle_literal_expr_129.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_31.unit_out_reg, _bundle_literal_expr_129.unit_out_reg.value
+                        wire _cast_to_bits_expr_39: UInt<6>
+                        connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_31.unit_out_reg, _cast_bundle_to_bits_expr_31.unit_num)
+                        when eq(_cast_to_bits_expr_39, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_131: Ty25
+                        wire _bundle_literal_expr_132: Ty23
+                        connect _bundle_literal_expr_132.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_131.unit_num, _bundle_literal_expr_132
+                        connect _bundle_literal_expr_131.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_32: Ty57
+                        connect _cast_bundle_to_bits_expr_32.unit_num, _bundle_literal_expr_131.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_32.unit_out_reg, _bundle_literal_expr_131.unit_out_reg.value
+                        wire _cast_to_bits_expr_40: UInt<6>
+                        connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_32.unit_out_reg, _cast_bundle_to_bits_expr_32.unit_num)
+                        when eq(_cast_to_bits_expr_40, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_2: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_133: Ty69
+                        connect _bundle_literal_expr_133.which, dest_reg_5
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_133): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_2, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_79):
+                                connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_80):
+                        wire _bundle_literal_expr_134: Ty69
+                        connect _bundle_literal_expr_134.which, dest_reg_5
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_134): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_81):
+                                connect cmp_eq_2, eq(_match_arm_value_80.which.value, _match_arm_value_81.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[2], cmp_eq_2 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_82):
+                        when eq(dest_reg_5.value, _match_arm_value_82.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[2], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_3: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_3, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_3, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_3: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_83):
+                        wire dest_reg_6: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_83.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_84):
+                                connect dest_reg_6, _match_arm_value_84.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_85):
+                                connect dest_reg_6, _match_arm_value_85.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_86):
+                                connect dest_reg_6, _match_arm_value_86.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_5.value, dest_reg_6.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[2], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_70.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[2]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_87):
+                        wire _bundle_literal_expr_135: Ty87
+                        connect _bundle_literal_expr_135.state, _match_arm_value_87
+                        connect _bundle_literal_expr_135.mop, _match_arm_value_70.mop
+                        connect _bundle_literal_expr_135.src_ready_flags, _match_arm_value_70.src_ready_flags
+                        connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_135) @[unit_base.rs 435:17]
+        wire _array_literal_expr_40: UInt<1>[3]
+        connect _array_literal_expr_40[0], UInt<1>(0h0)
+        connect _array_literal_expr_40[1], UInt<1>(0h0)
+        connect _array_literal_expr_40[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[3], _array_literal_expr_40 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[3], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[3], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[3], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[3]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_88):
+                wire dest_reg_7: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_88.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_89):
+                        connect dest_reg_7, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_90):
+                        connect dest_reg_7, _match_arm_value_90.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_91):
+                        connect dest_reg_7, _match_arm_value_91.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_3: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_41: UInt<6>[3]
+                wire _bundle_literal_expr_136: Ty25
+                wire _bundle_literal_expr_137: Ty23
+                connect _bundle_literal_expr_137.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137
+                wire _bundle_literal_expr_138: Ty24
+                connect _bundle_literal_expr_138.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138
+                wire _cast_bundle_to_bits_expr_33: Ty57
+                connect _cast_bundle_to_bits_expr_33.unit_num, _bundle_literal_expr_136.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_33.unit_out_reg, _bundle_literal_expr_136.unit_out_reg.value
+                wire _cast_to_bits_expr_41: UInt<6>
+                connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_33.unit_out_reg, _cast_bundle_to_bits_expr_33.unit_num)
+                connect _array_literal_expr_41[0], _cast_to_bits_expr_41
+                wire _bundle_literal_expr_139: Ty25
+                wire _bundle_literal_expr_140: Ty23
+                connect _bundle_literal_expr_140.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_139.unit_num, _bundle_literal_expr_140
+                wire _bundle_literal_expr_141: Ty24
+                connect _bundle_literal_expr_141.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_139.unit_out_reg, _bundle_literal_expr_141
+                wire _cast_bundle_to_bits_expr_34: Ty57
+                connect _cast_bundle_to_bits_expr_34.unit_num, _bundle_literal_expr_139.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_34.unit_out_reg, _bundle_literal_expr_139.unit_out_reg.value
+                wire _cast_to_bits_expr_42: UInt<6>
+                connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_34.unit_out_reg, _cast_bundle_to_bits_expr_34.unit_num)
+                connect _array_literal_expr_41[1], _cast_to_bits_expr_42
+                wire _bundle_literal_expr_142: Ty25
+                wire _bundle_literal_expr_143: Ty23
+                connect _bundle_literal_expr_143.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_142.unit_num, _bundle_literal_expr_143
+                wire _bundle_literal_expr_144: Ty24
+                connect _bundle_literal_expr_144.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_142.unit_out_reg, _bundle_literal_expr_144
+                wire _cast_bundle_to_bits_expr_35: Ty57
+                connect _cast_bundle_to_bits_expr_35.unit_num, _bundle_literal_expr_142.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_35.unit_out_reg, _bundle_literal_expr_142.unit_out_reg.value
+                wire _cast_to_bits_expr_43: UInt<6>
+                connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num)
+                connect _array_literal_expr_41[2], _cast_to_bits_expr_43
+                connect in_flight_op_src_regs_3, _array_literal_expr_41 @[unit_base.rs 356:13]
+                match _match_arm_value_88.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_92):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_92.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_92.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[2], _match_arm_value_92.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_93):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_93.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_93.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_94):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_94.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_94.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[3], _match_arm_value_88.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_95):
+                        wire _bundle_literal_expr_145: Ty25
+                        wire _bundle_literal_expr_146: Ty23
+                        connect _bundle_literal_expr_146.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_145.unit_num, _bundle_literal_expr_146
+                        connect _bundle_literal_expr_145.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_36: Ty57
+                        connect _cast_bundle_to_bits_expr_36.unit_num, _bundle_literal_expr_145.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_36.unit_out_reg, _bundle_literal_expr_145.unit_out_reg.value
+                        wire _cast_to_bits_expr_44: UInt<6>
+                        connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_36.unit_out_reg, _cast_bundle_to_bits_expr_36.unit_num)
+                        when eq(_cast_to_bits_expr_44, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_147: Ty25
+                        wire _bundle_literal_expr_148: Ty23
+                        connect _bundle_literal_expr_148.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_147.unit_num, _bundle_literal_expr_148
+                        connect _bundle_literal_expr_147.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_37: Ty57
+                        connect _cast_bundle_to_bits_expr_37.unit_num, _bundle_literal_expr_147.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_37.unit_out_reg, _bundle_literal_expr_147.unit_out_reg.value
+                        wire _cast_to_bits_expr_45: UInt<6>
+                        connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_37.unit_out_reg, _cast_bundle_to_bits_expr_37.unit_num)
+                        when eq(_cast_to_bits_expr_45, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_149: Ty25
+                        wire _bundle_literal_expr_150: Ty23
+                        connect _bundle_literal_expr_150.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_149.unit_num, _bundle_literal_expr_150
+                        connect _bundle_literal_expr_149.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_38: Ty57
+                        connect _cast_bundle_to_bits_expr_38.unit_num, _bundle_literal_expr_149.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_38.unit_out_reg, _bundle_literal_expr_149.unit_out_reg.value
+                        wire _cast_to_bits_expr_46: UInt<6>
+                        connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_38.unit_out_reg, _cast_bundle_to_bits_expr_38.unit_num)
+                        when eq(_cast_to_bits_expr_46, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_96):
+                        wire _bundle_literal_expr_151: Ty25
+                        wire _bundle_literal_expr_152: Ty23
+                        connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152
+                        connect _bundle_literal_expr_151.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_39: Ty57
+                        connect _cast_bundle_to_bits_expr_39.unit_num, _bundle_literal_expr_151.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_39.unit_out_reg, _bundle_literal_expr_151.unit_out_reg.value
+                        wire _cast_to_bits_expr_47: UInt<6>
+                        connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num)
+                        when eq(_cast_to_bits_expr_47, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_153: Ty25
+                        wire _bundle_literal_expr_154: Ty23
+                        connect _bundle_literal_expr_154.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_153.unit_num, _bundle_literal_expr_154
+                        connect _bundle_literal_expr_153.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_40: Ty57
+                        connect _cast_bundle_to_bits_expr_40.unit_num, _bundle_literal_expr_153.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_40.unit_out_reg, _bundle_literal_expr_153.unit_out_reg.value
+                        wire _cast_to_bits_expr_48: UInt<6>
+                        connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num)
+                        when eq(_cast_to_bits_expr_48, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_155: Ty25
+                        wire _bundle_literal_expr_156: Ty23
+                        connect _bundle_literal_expr_156.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_155.unit_num, _bundle_literal_expr_156
+                        connect _bundle_literal_expr_155.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_41: Ty57
+                        connect _cast_bundle_to_bits_expr_41.unit_num, _bundle_literal_expr_155.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_41.unit_out_reg, _bundle_literal_expr_155.unit_out_reg.value
+                        wire _cast_to_bits_expr_49: UInt<6>
+                        connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num)
+                        when eq(_cast_to_bits_expr_49, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_3: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_157: Ty69
+                        connect _bundle_literal_expr_157.which, dest_reg_7
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_157): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_3, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_97):
+                                connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_98):
+                        wire _bundle_literal_expr_158: Ty69
+                        connect _bundle_literal_expr_158.which, dest_reg_7
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_158): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_99):
+                                connect cmp_eq_3, eq(_match_arm_value_98.which.value, _match_arm_value_99.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[3], cmp_eq_3 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_100):
+                        when eq(dest_reg_7.value, _match_arm_value_100.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[3], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_4: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_4, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_4, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_4: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_101):
+                        wire dest_reg_8: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_101.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_102):
+                                connect dest_reg_8, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_103):
+                                connect dest_reg_8, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_104):
+                                connect dest_reg_8, _match_arm_value_104.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_7.value, dest_reg_8.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[3], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_88.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[3]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_105):
+                        wire _bundle_literal_expr_159: Ty87
+                        connect _bundle_literal_expr_159.state, _match_arm_value_105
+                        connect _bundle_literal_expr_159.mop, _match_arm_value_88.mop
+                        connect _bundle_literal_expr_159.src_ready_flags, _match_arm_value_88.src_ready_flags
+                        connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_159) @[unit_base.rs 435:17]
+        wire _array_literal_expr_42: UInt<1>[3]
+        connect _array_literal_expr_42[0], UInt<1>(0h0)
+        connect _array_literal_expr_42[1], UInt<1>(0h0)
+        connect _array_literal_expr_42[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[4], _array_literal_expr_42 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[4], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[4], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[4], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[4]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_106):
+                wire dest_reg_9: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_106.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_107):
+                        connect dest_reg_9, _match_arm_value_107.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_108):
+                        connect dest_reg_9, _match_arm_value_108.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_109):
+                        connect dest_reg_9, _match_arm_value_109.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_4: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_43: UInt<6>[3]
+                wire _bundle_literal_expr_160: Ty25
+                wire _bundle_literal_expr_161: Ty23
+                connect _bundle_literal_expr_161.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_160.unit_num, _bundle_literal_expr_161
+                wire _bundle_literal_expr_162: Ty24
+                connect _bundle_literal_expr_162.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_160.unit_out_reg, _bundle_literal_expr_162
+                wire _cast_bundle_to_bits_expr_42: Ty57
+                connect _cast_bundle_to_bits_expr_42.unit_num, _bundle_literal_expr_160.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_42.unit_out_reg, _bundle_literal_expr_160.unit_out_reg.value
+                wire _cast_to_bits_expr_50: UInt<6>
+                connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num)
+                connect _array_literal_expr_43[0], _cast_to_bits_expr_50
+                wire _bundle_literal_expr_163: Ty25
+                wire _bundle_literal_expr_164: Ty23
+                connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164
+                wire _bundle_literal_expr_165: Ty24
+                connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165
+                wire _cast_bundle_to_bits_expr_43: Ty57
+                connect _cast_bundle_to_bits_expr_43.unit_num, _bundle_literal_expr_163.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_43.unit_out_reg, _bundle_literal_expr_163.unit_out_reg.value
+                wire _cast_to_bits_expr_51: UInt<6>
+                connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num)
+                connect _array_literal_expr_43[1], _cast_to_bits_expr_51
+                wire _bundle_literal_expr_166: Ty25
+                wire _bundle_literal_expr_167: Ty23
+                connect _bundle_literal_expr_167.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_166.unit_num, _bundle_literal_expr_167
+                wire _bundle_literal_expr_168: Ty24
+                connect _bundle_literal_expr_168.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_166.unit_out_reg, _bundle_literal_expr_168
+                wire _cast_bundle_to_bits_expr_44: Ty57
+                connect _cast_bundle_to_bits_expr_44.unit_num, _bundle_literal_expr_166.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_44.unit_out_reg, _bundle_literal_expr_166.unit_out_reg.value
+                wire _cast_to_bits_expr_52: UInt<6>
+                connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num)
+                connect _array_literal_expr_43[2], _cast_to_bits_expr_52
+                connect in_flight_op_src_regs_4, _array_literal_expr_43 @[unit_base.rs 356:13]
+                match _match_arm_value_106.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_110):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_110.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_110.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[2], _match_arm_value_110.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_111):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_111.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_111.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_112):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_112.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_112.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[4], _match_arm_value_106.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_113):
+                        wire _bundle_literal_expr_169: Ty25
+                        wire _bundle_literal_expr_170: Ty23
+                        connect _bundle_literal_expr_170.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_169.unit_num, _bundle_literal_expr_170
+                        connect _bundle_literal_expr_169.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_45: Ty57
+                        connect _cast_bundle_to_bits_expr_45.unit_num, _bundle_literal_expr_169.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_45.unit_out_reg, _bundle_literal_expr_169.unit_out_reg.value
+                        wire _cast_to_bits_expr_53: UInt<6>
+                        connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num)
+                        when eq(_cast_to_bits_expr_53, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_171: Ty25
+                        wire _bundle_literal_expr_172: Ty23
+                        connect _bundle_literal_expr_172.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_171.unit_num, _bundle_literal_expr_172
+                        connect _bundle_literal_expr_171.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_46: Ty57
+                        connect _cast_bundle_to_bits_expr_46.unit_num, _bundle_literal_expr_171.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_46.unit_out_reg, _bundle_literal_expr_171.unit_out_reg.value
+                        wire _cast_to_bits_expr_54: UInt<6>
+                        connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num)
+                        when eq(_cast_to_bits_expr_54, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_173: Ty25
+                        wire _bundle_literal_expr_174: Ty23
+                        connect _bundle_literal_expr_174.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_173.unit_num, _bundle_literal_expr_174
+                        connect _bundle_literal_expr_173.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_47: Ty57
+                        connect _cast_bundle_to_bits_expr_47.unit_num, _bundle_literal_expr_173.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_47.unit_out_reg, _bundle_literal_expr_173.unit_out_reg.value
+                        wire _cast_to_bits_expr_55: UInt<6>
+                        connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num)
+                        when eq(_cast_to_bits_expr_55, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_114):
+                        wire _bundle_literal_expr_175: Ty25
+                        wire _bundle_literal_expr_176: Ty23
+                        connect _bundle_literal_expr_176.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_175.unit_num, _bundle_literal_expr_176
+                        connect _bundle_literal_expr_175.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_48: Ty57
+                        connect _cast_bundle_to_bits_expr_48.unit_num, _bundle_literal_expr_175.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_48.unit_out_reg, _bundle_literal_expr_175.unit_out_reg.value
+                        wire _cast_to_bits_expr_56: UInt<6>
+                        connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_48.unit_out_reg, _cast_bundle_to_bits_expr_48.unit_num)
+                        when eq(_cast_to_bits_expr_56, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_177: Ty25
+                        wire _bundle_literal_expr_178: Ty23
+                        connect _bundle_literal_expr_178.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_177.unit_num, _bundle_literal_expr_178
+                        connect _bundle_literal_expr_177.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_49: Ty57
+                        connect _cast_bundle_to_bits_expr_49.unit_num, _bundle_literal_expr_177.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_49.unit_out_reg, _bundle_literal_expr_177.unit_out_reg.value
+                        wire _cast_to_bits_expr_57: UInt<6>
+                        connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_49.unit_out_reg, _cast_bundle_to_bits_expr_49.unit_num)
+                        when eq(_cast_to_bits_expr_57, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_179: Ty25
+                        wire _bundle_literal_expr_180: Ty23
+                        connect _bundle_literal_expr_180.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_179.unit_num, _bundle_literal_expr_180
+                        connect _bundle_literal_expr_179.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_50: Ty57
+                        connect _cast_bundle_to_bits_expr_50.unit_num, _bundle_literal_expr_179.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_50.unit_out_reg, _bundle_literal_expr_179.unit_out_reg.value
+                        wire _cast_to_bits_expr_58: UInt<6>
+                        connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num)
+                        when eq(_cast_to_bits_expr_58, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_4: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_181: Ty69
+                        connect _bundle_literal_expr_181.which, dest_reg_9
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_181): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_4, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_115):
+                                connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_116):
+                        wire _bundle_literal_expr_182: Ty69
+                        connect _bundle_literal_expr_182.which, dest_reg_9
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_182): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_117):
+                                connect cmp_eq_4, eq(_match_arm_value_116.which.value, _match_arm_value_117.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[4], cmp_eq_4 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_118):
+                        when eq(dest_reg_9.value, _match_arm_value_118.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[4], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_5: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_5, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_5, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_5: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_119):
+                        wire dest_reg_10: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_119.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_120):
+                                connect dest_reg_10, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_121):
+                                connect dest_reg_10, _match_arm_value_121.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_122):
+                                connect dest_reg_10, _match_arm_value_122.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_9.value, dest_reg_10.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[4], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_106.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[4]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_123):
+                        wire _bundle_literal_expr_183: Ty87
+                        connect _bundle_literal_expr_183.state, _match_arm_value_123
+                        connect _bundle_literal_expr_183.mop, _match_arm_value_106.mop
+                        connect _bundle_literal_expr_183.src_ready_flags, _match_arm_value_106.src_ready_flags
+                        connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_183) @[unit_base.rs 435:17]
+        wire _array_literal_expr_44: UInt<1>[3]
+        connect _array_literal_expr_44[0], UInt<1>(0h0)
+        connect _array_literal_expr_44[1], UInt<1>(0h0)
+        connect _array_literal_expr_44[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[5], _array_literal_expr_44 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[5], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[5], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[5], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[5]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_124):
+                wire dest_reg_11: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_124.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_125):
+                        connect dest_reg_11, _match_arm_value_125.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_126):
+                        connect dest_reg_11, _match_arm_value_126.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_127):
+                        connect dest_reg_11, _match_arm_value_127.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_5: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_45: UInt<6>[3]
+                wire _bundle_literal_expr_184: Ty25
+                wire _bundle_literal_expr_185: Ty23
+                connect _bundle_literal_expr_185.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_184.unit_num, _bundle_literal_expr_185
+                wire _bundle_literal_expr_186: Ty24
+                connect _bundle_literal_expr_186.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_184.unit_out_reg, _bundle_literal_expr_186
+                wire _cast_bundle_to_bits_expr_51: Ty57
+                connect _cast_bundle_to_bits_expr_51.unit_num, _bundle_literal_expr_184.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_51.unit_out_reg, _bundle_literal_expr_184.unit_out_reg.value
+                wire _cast_to_bits_expr_59: UInt<6>
+                connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num)
+                connect _array_literal_expr_45[0], _cast_to_bits_expr_59
+                wire _bundle_literal_expr_187: Ty25
+                wire _bundle_literal_expr_188: Ty23
+                connect _bundle_literal_expr_188.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_187.unit_num, _bundle_literal_expr_188
+                wire _bundle_literal_expr_189: Ty24
+                connect _bundle_literal_expr_189.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_187.unit_out_reg, _bundle_literal_expr_189
+                wire _cast_bundle_to_bits_expr_52: Ty57
+                connect _cast_bundle_to_bits_expr_52.unit_num, _bundle_literal_expr_187.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_52.unit_out_reg, _bundle_literal_expr_187.unit_out_reg.value
+                wire _cast_to_bits_expr_60: UInt<6>
+                connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num)
+                connect _array_literal_expr_45[1], _cast_to_bits_expr_60
+                wire _bundle_literal_expr_190: Ty25
+                wire _bundle_literal_expr_191: Ty23
+                connect _bundle_literal_expr_191.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_190.unit_num, _bundle_literal_expr_191
+                wire _bundle_literal_expr_192: Ty24
+                connect _bundle_literal_expr_192.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_190.unit_out_reg, _bundle_literal_expr_192
+                wire _cast_bundle_to_bits_expr_53: Ty57
+                connect _cast_bundle_to_bits_expr_53.unit_num, _bundle_literal_expr_190.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_53.unit_out_reg, _bundle_literal_expr_190.unit_out_reg.value
+                wire _cast_to_bits_expr_61: UInt<6>
+                connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num)
+                connect _array_literal_expr_45[2], _cast_to_bits_expr_61
+                connect in_flight_op_src_regs_5, _array_literal_expr_45 @[unit_base.rs 356:13]
+                match _match_arm_value_124.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_128):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_128.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_128.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[2], _match_arm_value_128.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_129):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_129.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_129.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_130):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_130.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_130.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[5], _match_arm_value_124.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_131):
+                        wire _bundle_literal_expr_193: Ty25
+                        wire _bundle_literal_expr_194: Ty23
+                        connect _bundle_literal_expr_194.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_193.unit_num, _bundle_literal_expr_194
+                        connect _bundle_literal_expr_193.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_54: Ty57
+                        connect _cast_bundle_to_bits_expr_54.unit_num, _bundle_literal_expr_193.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_54.unit_out_reg, _bundle_literal_expr_193.unit_out_reg.value
+                        wire _cast_to_bits_expr_62: UInt<6>
+                        connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_54.unit_out_reg, _cast_bundle_to_bits_expr_54.unit_num)
+                        when eq(_cast_to_bits_expr_62, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_195: Ty25
+                        wire _bundle_literal_expr_196: Ty23
+                        connect _bundle_literal_expr_196.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_195.unit_num, _bundle_literal_expr_196
+                        connect _bundle_literal_expr_195.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_55: Ty57
+                        connect _cast_bundle_to_bits_expr_55.unit_num, _bundle_literal_expr_195.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_55.unit_out_reg, _bundle_literal_expr_195.unit_out_reg.value
+                        wire _cast_to_bits_expr_63: UInt<6>
+                        connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_55.unit_out_reg, _cast_bundle_to_bits_expr_55.unit_num)
+                        when eq(_cast_to_bits_expr_63, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_197: Ty25
+                        wire _bundle_literal_expr_198: Ty23
+                        connect _bundle_literal_expr_198.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_197.unit_num, _bundle_literal_expr_198
+                        connect _bundle_literal_expr_197.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_56: Ty57
+                        connect _cast_bundle_to_bits_expr_56.unit_num, _bundle_literal_expr_197.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_56.unit_out_reg, _bundle_literal_expr_197.unit_out_reg.value
+                        wire _cast_to_bits_expr_64: UInt<6>
+                        connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_56.unit_out_reg, _cast_bundle_to_bits_expr_56.unit_num)
+                        when eq(_cast_to_bits_expr_64, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_132):
+                        wire _bundle_literal_expr_199: Ty25
+                        wire _bundle_literal_expr_200: Ty23
+                        connect _bundle_literal_expr_200.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_199.unit_num, _bundle_literal_expr_200
+                        connect _bundle_literal_expr_199.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_57: Ty57
+                        connect _cast_bundle_to_bits_expr_57.unit_num, _bundle_literal_expr_199.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_57.unit_out_reg, _bundle_literal_expr_199.unit_out_reg.value
+                        wire _cast_to_bits_expr_65: UInt<6>
+                        connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num)
+                        when eq(_cast_to_bits_expr_65, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_201: Ty25
+                        wire _bundle_literal_expr_202: Ty23
+                        connect _bundle_literal_expr_202.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_201.unit_num, _bundle_literal_expr_202
+                        connect _bundle_literal_expr_201.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_58: Ty57
+                        connect _cast_bundle_to_bits_expr_58.unit_num, _bundle_literal_expr_201.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_58.unit_out_reg, _bundle_literal_expr_201.unit_out_reg.value
+                        wire _cast_to_bits_expr_66: UInt<6>
+                        connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num)
+                        when eq(_cast_to_bits_expr_66, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_203: Ty25
+                        wire _bundle_literal_expr_204: Ty23
+                        connect _bundle_literal_expr_204.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_203.unit_num, _bundle_literal_expr_204
+                        connect _bundle_literal_expr_203.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_59: Ty57
+                        connect _cast_bundle_to_bits_expr_59.unit_num, _bundle_literal_expr_203.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_59.unit_out_reg, _bundle_literal_expr_203.unit_out_reg.value
+                        wire _cast_to_bits_expr_67: UInt<6>
+                        connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num)
+                        when eq(_cast_to_bits_expr_67, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_5: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_205: Ty69
+                        connect _bundle_literal_expr_205.which, dest_reg_11
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_205): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_5, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_133):
+                                connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_134):
+                        wire _bundle_literal_expr_206: Ty69
+                        connect _bundle_literal_expr_206.which, dest_reg_11
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_206): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_135):
+                                connect cmp_eq_5, eq(_match_arm_value_134.which.value, _match_arm_value_135.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[5], cmp_eq_5 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_136):
+                        when eq(dest_reg_11.value, _match_arm_value_136.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[5], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_6: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_6, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_6, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_6: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_137):
+                        wire dest_reg_12: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_137.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_138):
+                                connect dest_reg_12, _match_arm_value_138.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_139):
+                                connect dest_reg_12, _match_arm_value_139.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_140):
+                                connect dest_reg_12, _match_arm_value_140.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_11.value, dest_reg_12.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[5], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_124.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[5]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_141):
+                        wire _bundle_literal_expr_207: Ty87
+                        connect _bundle_literal_expr_207.state, _match_arm_value_141
+                        connect _bundle_literal_expr_207.mop, _match_arm_value_124.mop
+                        connect _bundle_literal_expr_207.src_ready_flags, _match_arm_value_124.src_ready_flags
+                        connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_207) @[unit_base.rs 435:17]
+        wire _array_literal_expr_46: UInt<1>[3]
+        connect _array_literal_expr_46[0], UInt<1>(0h0)
+        connect _array_literal_expr_46[1], UInt<1>(0h0)
+        connect _array_literal_expr_46[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[6], _array_literal_expr_46 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[6], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[6], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[6], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[6]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_142):
+                wire dest_reg_13: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_142.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_143):
+                        connect dest_reg_13, _match_arm_value_143.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_144):
+                        connect dest_reg_13, _match_arm_value_144.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_145):
+                        connect dest_reg_13, _match_arm_value_145.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_6: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_47: UInt<6>[3]
+                wire _bundle_literal_expr_208: Ty25
+                wire _bundle_literal_expr_209: Ty23
+                connect _bundle_literal_expr_209.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_208.unit_num, _bundle_literal_expr_209
+                wire _bundle_literal_expr_210: Ty24
+                connect _bundle_literal_expr_210.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_208.unit_out_reg, _bundle_literal_expr_210
+                wire _cast_bundle_to_bits_expr_60: Ty57
+                connect _cast_bundle_to_bits_expr_60.unit_num, _bundle_literal_expr_208.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_60.unit_out_reg, _bundle_literal_expr_208.unit_out_reg.value
+                wire _cast_to_bits_expr_68: UInt<6>
+                connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num)
+                connect _array_literal_expr_47[0], _cast_to_bits_expr_68
+                wire _bundle_literal_expr_211: Ty25
+                wire _bundle_literal_expr_212: Ty23
+                connect _bundle_literal_expr_212.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_211.unit_num, _bundle_literal_expr_212
+                wire _bundle_literal_expr_213: Ty24
+                connect _bundle_literal_expr_213.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_211.unit_out_reg, _bundle_literal_expr_213
+                wire _cast_bundle_to_bits_expr_61: Ty57
+                connect _cast_bundle_to_bits_expr_61.unit_num, _bundle_literal_expr_211.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_61.unit_out_reg, _bundle_literal_expr_211.unit_out_reg.value
+                wire _cast_to_bits_expr_69: UInt<6>
+                connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_61.unit_out_reg, _cast_bundle_to_bits_expr_61.unit_num)
+                connect _array_literal_expr_47[1], _cast_to_bits_expr_69
+                wire _bundle_literal_expr_214: Ty25
+                wire _bundle_literal_expr_215: Ty23
+                connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215
+                wire _bundle_literal_expr_216: Ty24
+                connect _bundle_literal_expr_216.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216
+                wire _cast_bundle_to_bits_expr_62: Ty57
+                connect _cast_bundle_to_bits_expr_62.unit_num, _bundle_literal_expr_214.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_62.unit_out_reg, _bundle_literal_expr_214.unit_out_reg.value
+                wire _cast_to_bits_expr_70: UInt<6>
+                connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_62.unit_out_reg, _cast_bundle_to_bits_expr_62.unit_num)
+                connect _array_literal_expr_47[2], _cast_to_bits_expr_70
+                connect in_flight_op_src_regs_6, _array_literal_expr_47 @[unit_base.rs 356:13]
+                match _match_arm_value_142.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_146):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_146.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_146.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[2], _match_arm_value_146.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_147):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_147.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_147.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_148):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_148.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_148.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[6], _match_arm_value_142.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_149):
+                        wire _bundle_literal_expr_217: Ty25
+                        wire _bundle_literal_expr_218: Ty23
+                        connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218
+                        connect _bundle_literal_expr_217.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_63: Ty57
+                        connect _cast_bundle_to_bits_expr_63.unit_num, _bundle_literal_expr_217.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_63.unit_out_reg, _bundle_literal_expr_217.unit_out_reg.value
+                        wire _cast_to_bits_expr_71: UInt<6>
+                        connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_63.unit_out_reg, _cast_bundle_to_bits_expr_63.unit_num)
+                        when eq(_cast_to_bits_expr_71, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_219: Ty25
+                        wire _bundle_literal_expr_220: Ty23
+                        connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220
+                        connect _bundle_literal_expr_219.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_64: Ty57
+                        connect _cast_bundle_to_bits_expr_64.unit_num, _bundle_literal_expr_219.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_64.unit_out_reg, _bundle_literal_expr_219.unit_out_reg.value
+                        wire _cast_to_bits_expr_72: UInt<6>
+                        connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_64.unit_out_reg, _cast_bundle_to_bits_expr_64.unit_num)
+                        when eq(_cast_to_bits_expr_72, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_221: Ty25
+                        wire _bundle_literal_expr_222: Ty23
+                        connect _bundle_literal_expr_222.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_221.unit_num, _bundle_literal_expr_222
+                        connect _bundle_literal_expr_221.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_65: Ty57
+                        connect _cast_bundle_to_bits_expr_65.unit_num, _bundle_literal_expr_221.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_65.unit_out_reg, _bundle_literal_expr_221.unit_out_reg.value
+                        wire _cast_to_bits_expr_73: UInt<6>
+                        connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_65.unit_out_reg, _cast_bundle_to_bits_expr_65.unit_num)
+                        when eq(_cast_to_bits_expr_73, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_150):
+                        wire _bundle_literal_expr_223: Ty25
+                        wire _bundle_literal_expr_224: Ty23
+                        connect _bundle_literal_expr_224.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_223.unit_num, _bundle_literal_expr_224
+                        connect _bundle_literal_expr_223.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_66: Ty57
+                        connect _cast_bundle_to_bits_expr_66.unit_num, _bundle_literal_expr_223.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_66.unit_out_reg, _bundle_literal_expr_223.unit_out_reg.value
+                        wire _cast_to_bits_expr_74: UInt<6>
+                        connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_66.unit_out_reg, _cast_bundle_to_bits_expr_66.unit_num)
+                        when eq(_cast_to_bits_expr_74, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_225: Ty25
+                        wire _bundle_literal_expr_226: Ty23
+                        connect _bundle_literal_expr_226.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_225.unit_num, _bundle_literal_expr_226
+                        connect _bundle_literal_expr_225.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_67: Ty57
+                        connect _cast_bundle_to_bits_expr_67.unit_num, _bundle_literal_expr_225.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_67.unit_out_reg, _bundle_literal_expr_225.unit_out_reg.value
+                        wire _cast_to_bits_expr_75: UInt<6>
+                        connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num)
+                        when eq(_cast_to_bits_expr_75, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_227: Ty25
+                        wire _bundle_literal_expr_228: Ty23
+                        connect _bundle_literal_expr_228.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_227.unit_num, _bundle_literal_expr_228
+                        connect _bundle_literal_expr_227.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_68: Ty57
+                        connect _cast_bundle_to_bits_expr_68.unit_num, _bundle_literal_expr_227.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_68.unit_out_reg, _bundle_literal_expr_227.unit_out_reg.value
+                        wire _cast_to_bits_expr_76: UInt<6>
+                        connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_68.unit_out_reg, _cast_bundle_to_bits_expr_68.unit_num)
+                        when eq(_cast_to_bits_expr_76, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_6: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_229: Ty69
+                        connect _bundle_literal_expr_229.which, dest_reg_13
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_229): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_6, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_151):
+                                connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_152):
+                        wire _bundle_literal_expr_230: Ty69
+                        connect _bundle_literal_expr_230.which, dest_reg_13
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_230): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_153):
+                                connect cmp_eq_6, eq(_match_arm_value_152.which.value, _match_arm_value_153.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[6], cmp_eq_6 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_154):
+                        when eq(dest_reg_13.value, _match_arm_value_154.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[6], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_7: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_7, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_7, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_7: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_155):
+                        wire dest_reg_14: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_155.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_156):
+                                connect dest_reg_14, _match_arm_value_156.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_157):
+                                connect dest_reg_14, _match_arm_value_157.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_158):
+                                connect dest_reg_14, _match_arm_value_158.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_13.value, dest_reg_14.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[6], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_142.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[6]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_159):
+                        wire _bundle_literal_expr_231: Ty87
+                        connect _bundle_literal_expr_231.state, _match_arm_value_159
+                        connect _bundle_literal_expr_231.mop, _match_arm_value_142.mop
+                        connect _bundle_literal_expr_231.src_ready_flags, _match_arm_value_142.src_ready_flags
+                        connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_231) @[unit_base.rs 435:17]
+        wire _array_literal_expr_48: UInt<1>[3]
+        connect _array_literal_expr_48[0], UInt<1>(0h0)
+        connect _array_literal_expr_48[1], UInt<1>(0h0)
+        connect _array_literal_expr_48[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[7], _array_literal_expr_48 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[7], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[7], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[7], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[7]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_160):
+                wire dest_reg_15: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_160.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_161):
+                        connect dest_reg_15, _match_arm_value_161.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_162):
+                        connect dest_reg_15, _match_arm_value_162.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_163):
+                        connect dest_reg_15, _match_arm_value_163.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_7: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_49: UInt<6>[3]
+                wire _bundle_literal_expr_232: Ty25
+                wire _bundle_literal_expr_233: Ty23
+                connect _bundle_literal_expr_233.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_232.unit_num, _bundle_literal_expr_233
+                wire _bundle_literal_expr_234: Ty24
+                connect _bundle_literal_expr_234.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_232.unit_out_reg, _bundle_literal_expr_234
+                wire _cast_bundle_to_bits_expr_69: Ty57
+                connect _cast_bundle_to_bits_expr_69.unit_num, _bundle_literal_expr_232.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_69.unit_out_reg, _bundle_literal_expr_232.unit_out_reg.value
+                wire _cast_to_bits_expr_77: UInt<6>
+                connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_69.unit_out_reg, _cast_bundle_to_bits_expr_69.unit_num)
+                connect _array_literal_expr_49[0], _cast_to_bits_expr_77
+                wire _bundle_literal_expr_235: Ty25
+                wire _bundle_literal_expr_236: Ty23
+                connect _bundle_literal_expr_236.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_235.unit_num, _bundle_literal_expr_236
+                wire _bundle_literal_expr_237: Ty24
+                connect _bundle_literal_expr_237.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_235.unit_out_reg, _bundle_literal_expr_237
+                wire _cast_bundle_to_bits_expr_70: Ty57
+                connect _cast_bundle_to_bits_expr_70.unit_num, _bundle_literal_expr_235.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_70.unit_out_reg, _bundle_literal_expr_235.unit_out_reg.value
+                wire _cast_to_bits_expr_78: UInt<6>
+                connect _cast_to_bits_expr_78, cat(_cast_bundle_to_bits_expr_70.unit_out_reg, _cast_bundle_to_bits_expr_70.unit_num)
+                connect _array_literal_expr_49[1], _cast_to_bits_expr_78
+                wire _bundle_literal_expr_238: Ty25
+                wire _bundle_literal_expr_239: Ty23
+                connect _bundle_literal_expr_239.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_238.unit_num, _bundle_literal_expr_239
+                wire _bundle_literal_expr_240: Ty24
+                connect _bundle_literal_expr_240.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_238.unit_out_reg, _bundle_literal_expr_240
+                wire _cast_bundle_to_bits_expr_71: Ty57
+                connect _cast_bundle_to_bits_expr_71.unit_num, _bundle_literal_expr_238.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_71.unit_out_reg, _bundle_literal_expr_238.unit_out_reg.value
+                wire _cast_to_bits_expr_79: UInt<6>
+                connect _cast_to_bits_expr_79, cat(_cast_bundle_to_bits_expr_71.unit_out_reg, _cast_bundle_to_bits_expr_71.unit_num)
+                connect _array_literal_expr_49[2], _cast_to_bits_expr_79
+                connect in_flight_op_src_regs_7, _array_literal_expr_49 @[unit_base.rs 356:13]
+                match _match_arm_value_160.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_164):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_164.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_164.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[2], _match_arm_value_164.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_165):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_165.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_165.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_166):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_166.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_166.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[7], _match_arm_value_160.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_167):
+                        wire _bundle_literal_expr_241: Ty25
+                        wire _bundle_literal_expr_242: Ty23
+                        connect _bundle_literal_expr_242.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_241.unit_num, _bundle_literal_expr_242
+                        connect _bundle_literal_expr_241.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_72: Ty57
+                        connect _cast_bundle_to_bits_expr_72.unit_num, _bundle_literal_expr_241.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_72.unit_out_reg, _bundle_literal_expr_241.unit_out_reg.value
+                        wire _cast_to_bits_expr_80: UInt<6>
+                        connect _cast_to_bits_expr_80, cat(_cast_bundle_to_bits_expr_72.unit_out_reg, _cast_bundle_to_bits_expr_72.unit_num)
+                        when eq(_cast_to_bits_expr_80, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_243: Ty25
+                        wire _bundle_literal_expr_244: Ty23
+                        connect _bundle_literal_expr_244.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_243.unit_num, _bundle_literal_expr_244
+                        connect _bundle_literal_expr_243.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_73: Ty57
+                        connect _cast_bundle_to_bits_expr_73.unit_num, _bundle_literal_expr_243.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_73.unit_out_reg, _bundle_literal_expr_243.unit_out_reg.value
+                        wire _cast_to_bits_expr_81: UInt<6>
+                        connect _cast_to_bits_expr_81, cat(_cast_bundle_to_bits_expr_73.unit_out_reg, _cast_bundle_to_bits_expr_73.unit_num)
+                        when eq(_cast_to_bits_expr_81, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_245: Ty25
+                        wire _bundle_literal_expr_246: Ty23
+                        connect _bundle_literal_expr_246.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_245.unit_num, _bundle_literal_expr_246
+                        connect _bundle_literal_expr_245.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_74: Ty57
+                        connect _cast_bundle_to_bits_expr_74.unit_num, _bundle_literal_expr_245.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_74.unit_out_reg, _bundle_literal_expr_245.unit_out_reg.value
+                        wire _cast_to_bits_expr_82: UInt<6>
+                        connect _cast_to_bits_expr_82, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num)
+                        when eq(_cast_to_bits_expr_82, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_168):
+                        wire _bundle_literal_expr_247: Ty25
+                        wire _bundle_literal_expr_248: Ty23
+                        connect _bundle_literal_expr_248.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_247.unit_num, _bundle_literal_expr_248
+                        connect _bundle_literal_expr_247.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_75: Ty57
+                        connect _cast_bundle_to_bits_expr_75.unit_num, _bundle_literal_expr_247.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_75.unit_out_reg, _bundle_literal_expr_247.unit_out_reg.value
+                        wire _cast_to_bits_expr_83: UInt<6>
+                        connect _cast_to_bits_expr_83, cat(_cast_bundle_to_bits_expr_75.unit_out_reg, _cast_bundle_to_bits_expr_75.unit_num)
+                        when eq(_cast_to_bits_expr_83, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_249: Ty25
+                        wire _bundle_literal_expr_250: Ty23
+                        connect _bundle_literal_expr_250.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_249.unit_num, _bundle_literal_expr_250
+                        connect _bundle_literal_expr_249.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_76: Ty57
+                        connect _cast_bundle_to_bits_expr_76.unit_num, _bundle_literal_expr_249.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_76.unit_out_reg, _bundle_literal_expr_249.unit_out_reg.value
+                        wire _cast_to_bits_expr_84: UInt<6>
+                        connect _cast_to_bits_expr_84, cat(_cast_bundle_to_bits_expr_76.unit_out_reg, _cast_bundle_to_bits_expr_76.unit_num)
+                        when eq(_cast_to_bits_expr_84, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_251: Ty25
+                        wire _bundle_literal_expr_252: Ty23
+                        connect _bundle_literal_expr_252.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_251.unit_num, _bundle_literal_expr_252
+                        connect _bundle_literal_expr_251.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_77: Ty57
+                        connect _cast_bundle_to_bits_expr_77.unit_num, _bundle_literal_expr_251.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_77.unit_out_reg, _bundle_literal_expr_251.unit_out_reg.value
+                        wire _cast_to_bits_expr_85: UInt<6>
+                        connect _cast_to_bits_expr_85, cat(_cast_bundle_to_bits_expr_77.unit_out_reg, _cast_bundle_to_bits_expr_77.unit_num)
+                        when eq(_cast_to_bits_expr_85, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_7: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_253: Ty69
+                        connect _bundle_literal_expr_253.which, dest_reg_15
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_253): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_7, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_169):
+                                connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_170):
+                        wire _bundle_literal_expr_254: Ty69
+                        connect _bundle_literal_expr_254.which, dest_reg_15
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_254): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_171):
+                                connect cmp_eq_7, eq(_match_arm_value_170.which.value, _match_arm_value_171.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[7], cmp_eq_7 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_172):
+                        when eq(dest_reg_15.value, _match_arm_value_172.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[7], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_8: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_8, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_8, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_8: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_173):
+                        wire dest_reg_16: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_173.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_174):
+                                connect dest_reg_16, _match_arm_value_174.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_175):
+                                connect dest_reg_16, _match_arm_value_175.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_176):
+                                connect dest_reg_16, _match_arm_value_176.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_15.value, dest_reg_16.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[7], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_160.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[7]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_177):
+                        wire _bundle_literal_expr_255: Ty87
+                        connect _bundle_literal_expr_255.state, _match_arm_value_177
+                        connect _bundle_literal_expr_255.mop, _match_arm_value_160.mop
+                        connect _bundle_literal_expr_255.src_ready_flags, _match_arm_value_160.src_ready_flags
+                        connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_255) @[unit_base.rs 435:17]
+    module unit_base_1: @[unit_base.rs 225:1]
+        input cd: Ty0 @[unit_base.rs 236:29]
+        output unit_to_reg_alloc: Ty75 @[unit_base.rs 239:11]
+        output execute_start: Ty82 @[unit_base.rs 241:58]
+        input execute_end: Ty84 @[unit_base.rs 244:11]
+        connect execute_start.data, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[unit_base.rs 246:5]
         wire _array_literal_expr: Ty88[8]
         connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone)
@@ -4393,480 +6720,2838 @@ circuit reg_alloc:
         connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone)
         connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone)
-        regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 55:25]
-        wire input_index: Ty85 @[unit_base.rs 61:23]
-        match in_flight_ops[0]: @[unit_base.rs 66:17]
+        regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 251:25]
+        wire empty_op_index_0: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_0: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[0]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value):
-                connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[1]: @[unit_base.rs 66:17]
+                connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_1: UInt<1>[3]
+                        wire _array_literal_expr_2: UInt<1>[3]
+                        connect _array_literal_expr_2[0], UInt<1>(0h1)
+                        connect _array_literal_expr_2[1], UInt<1>(0h1)
+                        connect _array_literal_expr_2[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[0], eq(_match_arm_value.src_ready_flags[0], _array_literal_expr_2[0])
+                        wire _array_literal_expr_3: UInt<1>[3]
+                        connect _array_literal_expr_3[0], UInt<1>(0h1)
+                        connect _array_literal_expr_3[1], UInt<1>(0h1)
+                        connect _array_literal_expr_3[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[1], eq(_match_arm_value.src_ready_flags[1], _array_literal_expr_3[1])
+                        wire _array_literal_expr_4: UInt<1>[3]
+                        connect _array_literal_expr_4[0], UInt<1>(0h1)
+                        connect _array_literal_expr_4[1], UInt<1>(0h1)
+                        connect _array_literal_expr_4[2], UInt<1>(0h1)
+                        connect _array_literal_expr_1[2], eq(_match_arm_value.src_ready_flags[2], _array_literal_expr_4[2])
+                        wire _cast_array_to_bits_expr: UInt<1>[3]
+                        connect _cast_array_to_bits_expr[0], _array_literal_expr_1[0]
+                        connect _cast_array_to_bits_expr[1], _array_literal_expr_1[1]
+                        connect _cast_array_to_bits_expr[2], _array_literal_expr_1[2]
+                        wire _cast_to_bits_expr: UInt<3>
+                        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
+                        when andr(_cast_to_bits_expr): @[unit_base.rs 182:21]
+                            connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_1: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_1: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[1]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_1):
-                connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 66:17]
-        wire or_out: Ty85 @[function.rs 166:5]
-        connect or_out, and_then_out_1 @[function.rs 166:5]
-        match and_then_out: @[function.rs 166:5]
+                connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_1.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_5: UInt<1>[3]
+                        wire _array_literal_expr_6: UInt<1>[3]
+                        connect _array_literal_expr_6[0], UInt<1>(0h1)
+                        connect _array_literal_expr_6[1], UInt<1>(0h1)
+                        connect _array_literal_expr_6[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[0], eq(_match_arm_value_1.src_ready_flags[0], _array_literal_expr_6[0])
+                        wire _array_literal_expr_7: UInt<1>[3]
+                        connect _array_literal_expr_7[0], UInt<1>(0h1)
+                        connect _array_literal_expr_7[1], UInt<1>(0h1)
+                        connect _array_literal_expr_7[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[1], eq(_match_arm_value_1.src_ready_flags[1], _array_literal_expr_7[1])
+                        wire _array_literal_expr_8: UInt<1>[3]
+                        connect _array_literal_expr_8[0], UInt<1>(0h1)
+                        connect _array_literal_expr_8[1], UInt<1>(0h1)
+                        connect _array_literal_expr_8[2], UInt<1>(0h1)
+                        connect _array_literal_expr_5[2], eq(_match_arm_value_1.src_ready_flags[2], _array_literal_expr_8[2])
+                        wire _cast_array_to_bits_expr_1: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_1[0], _array_literal_expr_5[0]
+                        connect _cast_array_to_bits_expr_1[1], _array_literal_expr_5[1]
+                        connect _cast_array_to_bits_expr_1[2], _array_literal_expr_5[2]
+                        wire _cast_to_bits_expr_1: UInt<3>
+                        connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
+                        when andr(_cast_to_bits_expr_1): @[unit_base.rs 182:21]
+                            connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr: Ty90
+        connect _bundle_literal_expr.empty_op_index, empty_op_index_1
+        connect _bundle_literal_expr.ready_op_index, ready_op_index_1
+        connect or_out, _bundle_literal_expr.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_1: Ty90
+        connect _bundle_literal_expr_1.empty_op_index, empty_op_index_0
+        connect _bundle_literal_expr_1.ready_op_index, ready_op_index_0
+        match _bundle_literal_expr_1.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_2):
-                connect or_out, and_then_out @[function.rs 166:5]
-        match in_flight_ops[2]: @[unit_base.rs 66:17]
-            HdlNone:
-                connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
-            HdlSome(_match_arm_value_3):
-                connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[3]: @[unit_base.rs 66:17]
-            HdlNone:
-                connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
-            HdlSome(_match_arm_value_4):
-                connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 66:17]
-        wire or_out_1: Ty85 @[function.rs 166:5]
-        connect or_out_1, and_then_out_3 @[function.rs 166:5]
-        match and_then_out_2: @[function.rs 166:5]
+                wire _bundle_literal_expr_2: Ty90
+                connect _bundle_literal_expr_2.empty_op_index, empty_op_index_0
+                connect _bundle_literal_expr_2.ready_op_index, ready_op_index_0
+                connect or_out, _bundle_literal_expr_2.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_1: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_3: Ty90
+        connect _bundle_literal_expr_3.empty_op_index, empty_op_index_1
+        connect _bundle_literal_expr_3.ready_op_index, ready_op_index_1
+        connect or_out_1, _bundle_literal_expr_3.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_4: Ty90
+        connect _bundle_literal_expr_4.empty_op_index, empty_op_index_0
+        connect _bundle_literal_expr_4.ready_op_index, ready_op_index_0
+        match _bundle_literal_expr_4.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
+            HdlSome(_match_arm_value_3):
+                wire _bundle_literal_expr_5: Ty90
+                connect _bundle_literal_expr_5.empty_op_index, empty_op_index_0
+                connect _bundle_literal_expr_5.ready_op_index, ready_op_index_0
+                connect or_out_1, _bundle_literal_expr_5.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_2: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_2: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[2]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 189:13]
+            HdlSome(_match_arm_value_4):
+                connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_4.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_9: UInt<1>[3]
+                        wire _array_literal_expr_10: UInt<1>[3]
+                        connect _array_literal_expr_10[0], UInt<1>(0h1)
+                        connect _array_literal_expr_10[1], UInt<1>(0h1)
+                        connect _array_literal_expr_10[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[0], eq(_match_arm_value_4.src_ready_flags[0], _array_literal_expr_10[0])
+                        wire _array_literal_expr_11: UInt<1>[3]
+                        connect _array_literal_expr_11[0], UInt<1>(0h1)
+                        connect _array_literal_expr_11[1], UInt<1>(0h1)
+                        connect _array_literal_expr_11[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[1], eq(_match_arm_value_4.src_ready_flags[1], _array_literal_expr_11[1])
+                        wire _array_literal_expr_12: UInt<1>[3]
+                        connect _array_literal_expr_12[0], UInt<1>(0h1)
+                        connect _array_literal_expr_12[1], UInt<1>(0h1)
+                        connect _array_literal_expr_12[2], UInt<1>(0h1)
+                        connect _array_literal_expr_9[2], eq(_match_arm_value_4.src_ready_flags[2], _array_literal_expr_12[2])
+                        wire _cast_array_to_bits_expr_2: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_2[0], _array_literal_expr_9[0]
+                        connect _cast_array_to_bits_expr_2[1], _array_literal_expr_9[1]
+                        connect _cast_array_to_bits_expr_2[2], _array_literal_expr_9[2]
+                        wire _cast_to_bits_expr_2: UInt<3>
+                        connect _cast_to_bits_expr_2, cat(_cast_array_to_bits_expr_2[2], cat(_cast_array_to_bits_expr_2[1], _cast_array_to_bits_expr_2[0]))
+                        when andr(_cast_to_bits_expr_2): @[unit_base.rs 182:21]
+                            connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_3: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_3: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[3]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_5):
-                connect or_out_1, and_then_out_2 @[function.rs 166:5]
-        wire or_out_2: Ty85 @[function.rs 166:5]
-        connect or_out_2, or_out_1 @[function.rs 166:5]
-        match or_out: @[function.rs 166:5]
+                connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_5.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_13: UInt<1>[3]
+                        wire _array_literal_expr_14: UInt<1>[3]
+                        connect _array_literal_expr_14[0], UInt<1>(0h1)
+                        connect _array_literal_expr_14[1], UInt<1>(0h1)
+                        connect _array_literal_expr_14[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[0], eq(_match_arm_value_5.src_ready_flags[0], _array_literal_expr_14[0])
+                        wire _array_literal_expr_15: UInt<1>[3]
+                        connect _array_literal_expr_15[0], UInt<1>(0h1)
+                        connect _array_literal_expr_15[1], UInt<1>(0h1)
+                        connect _array_literal_expr_15[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[1], eq(_match_arm_value_5.src_ready_flags[1], _array_literal_expr_15[1])
+                        wire _array_literal_expr_16: UInt<1>[3]
+                        connect _array_literal_expr_16[0], UInt<1>(0h1)
+                        connect _array_literal_expr_16[1], UInt<1>(0h1)
+                        connect _array_literal_expr_16[2], UInt<1>(0h1)
+                        connect _array_literal_expr_13[2], eq(_match_arm_value_5.src_ready_flags[2], _array_literal_expr_16[2])
+                        wire _cast_array_to_bits_expr_3: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_3[0], _array_literal_expr_13[0]
+                        connect _cast_array_to_bits_expr_3[1], _array_literal_expr_13[1]
+                        connect _cast_array_to_bits_expr_3[2], _array_literal_expr_13[2]
+                        wire _cast_to_bits_expr_3: UInt<3>
+                        connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr_3[2], cat(_cast_array_to_bits_expr_3[1], _cast_array_to_bits_expr_3[0]))
+                        when andr(_cast_to_bits_expr_3): @[unit_base.rs 182:21]
+                            connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_2: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_6: Ty90
+        connect _bundle_literal_expr_6.empty_op_index, empty_op_index_3
+        connect _bundle_literal_expr_6.ready_op_index, ready_op_index_3
+        connect or_out_2, _bundle_literal_expr_6.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_7: Ty90
+        connect _bundle_literal_expr_7.empty_op_index, empty_op_index_2
+        connect _bundle_literal_expr_7.ready_op_index, ready_op_index_2
+        match _bundle_literal_expr_7.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_6):
-                connect or_out_2, or_out @[function.rs 166:5]
-        match in_flight_ops[4]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_8: Ty90
+                connect _bundle_literal_expr_8.empty_op_index, empty_op_index_2
+                connect _bundle_literal_expr_8.ready_op_index, ready_op_index_2
+                connect or_out_2, _bundle_literal_expr_8.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_3: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_9: Ty90
+        connect _bundle_literal_expr_9.empty_op_index, empty_op_index_3
+        connect _bundle_literal_expr_9.ready_op_index, ready_op_index_3
+        connect or_out_3, _bundle_literal_expr_9.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_10: Ty90
+        connect _bundle_literal_expr_10.empty_op_index, empty_op_index_2
+        connect _bundle_literal_expr_10.ready_op_index, ready_op_index_2
+        match _bundle_literal_expr_10.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                skip
             HdlSome(_match_arm_value_7):
-                connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[5]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_11: Ty90
+                connect _bundle_literal_expr_11.empty_op_index, empty_op_index_2
+                connect _bundle_literal_expr_11.ready_op_index, ready_op_index_2
+                connect or_out_3, _bundle_literal_expr_11.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_4: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_12: Ty90
+        connect _bundle_literal_expr_12.empty_op_index, or_out_2
+        connect _bundle_literal_expr_12.ready_op_index, or_out_3
+        connect or_out_4, _bundle_literal_expr_12.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_13: Ty90
+        connect _bundle_literal_expr_13.empty_op_index, or_out
+        connect _bundle_literal_expr_13.ready_op_index, or_out_1
+        match _bundle_literal_expr_13.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
-                connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                skip
             HdlSome(_match_arm_value_8):
-                connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 66:17]
-        wire or_out_3: Ty85 @[function.rs 166:5]
-        connect or_out_3, and_then_out_5 @[function.rs 166:5]
-        match and_then_out_4: @[function.rs 166:5]
+                wire _bundle_literal_expr_14: Ty90
+                connect _bundle_literal_expr_14.empty_op_index, or_out
+                connect _bundle_literal_expr_14.ready_op_index, or_out_1
+                connect or_out_4, _bundle_literal_expr_14.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_5: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_15: Ty90
+        connect _bundle_literal_expr_15.empty_op_index, or_out_2
+        connect _bundle_literal_expr_15.ready_op_index, or_out_3
+        connect or_out_5, _bundle_literal_expr_15.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_16: Ty90
+        connect _bundle_literal_expr_16.empty_op_index, or_out
+        connect _bundle_literal_expr_16.ready_op_index, or_out_1
+        match _bundle_literal_expr_16.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_9):
-                connect or_out_3, and_then_out_4 @[function.rs 166:5]
-        match in_flight_ops[6]: @[unit_base.rs 66:17]
+                wire _bundle_literal_expr_17: Ty90
+                connect _bundle_literal_expr_17.empty_op_index, or_out
+                connect _bundle_literal_expr_17.ready_op_index, or_out_1
+                connect or_out_5, _bundle_literal_expr_17.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_4: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_4: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[4]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_10):
-                connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 66:17]
-        match in_flight_ops[7]: @[unit_base.rs 66:17]
+                connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_10.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_17: UInt<1>[3]
+                        wire _array_literal_expr_18: UInt<1>[3]
+                        connect _array_literal_expr_18[0], UInt<1>(0h1)
+                        connect _array_literal_expr_18[1], UInt<1>(0h1)
+                        connect _array_literal_expr_18[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[0], eq(_match_arm_value_10.src_ready_flags[0], _array_literal_expr_18[0])
+                        wire _array_literal_expr_19: UInt<1>[3]
+                        connect _array_literal_expr_19[0], UInt<1>(0h1)
+                        connect _array_literal_expr_19[1], UInt<1>(0h1)
+                        connect _array_literal_expr_19[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[1], eq(_match_arm_value_10.src_ready_flags[1], _array_literal_expr_19[1])
+                        wire _array_literal_expr_20: UInt<1>[3]
+                        connect _array_literal_expr_20[0], UInt<1>(0h1)
+                        connect _array_literal_expr_20[1], UInt<1>(0h1)
+                        connect _array_literal_expr_20[2], UInt<1>(0h1)
+                        connect _array_literal_expr_17[2], eq(_match_arm_value_10.src_ready_flags[2], _array_literal_expr_20[2])
+                        wire _cast_array_to_bits_expr_4: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_4[0], _array_literal_expr_17[0]
+                        connect _cast_array_to_bits_expr_4[1], _array_literal_expr_17[1]
+                        connect _cast_array_to_bits_expr_4[2], _array_literal_expr_17[2]
+                        wire _cast_to_bits_expr_4: UInt<3>
+                        connect _cast_to_bits_expr_4, cat(_cast_array_to_bits_expr_4[2], cat(_cast_array_to_bits_expr_4[1], _cast_array_to_bits_expr_4[0]))
+                        when andr(_cast_to_bits_expr_4): @[unit_base.rs 182:21]
+                            connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_5: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_5: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[5]: @[unit_base.rs 169:9]
             HdlNone:
-                connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17]
+                connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_11):
-                connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 66:17]
-        wire or_out_4: Ty85 @[function.rs 166:5]
-        connect or_out_4, and_then_out_7 @[function.rs 166:5]
-        match and_then_out_6: @[function.rs 166:5]
+                connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_11.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_21: UInt<1>[3]
+                        wire _array_literal_expr_22: UInt<1>[3]
+                        connect _array_literal_expr_22[0], UInt<1>(0h1)
+                        connect _array_literal_expr_22[1], UInt<1>(0h1)
+                        connect _array_literal_expr_22[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[0], eq(_match_arm_value_11.src_ready_flags[0], _array_literal_expr_22[0])
+                        wire _array_literal_expr_23: UInt<1>[3]
+                        connect _array_literal_expr_23[0], UInt<1>(0h1)
+                        connect _array_literal_expr_23[1], UInt<1>(0h1)
+                        connect _array_literal_expr_23[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[1], eq(_match_arm_value_11.src_ready_flags[1], _array_literal_expr_23[1])
+                        wire _array_literal_expr_24: UInt<1>[3]
+                        connect _array_literal_expr_24[0], UInt<1>(0h1)
+                        connect _array_literal_expr_24[1], UInt<1>(0h1)
+                        connect _array_literal_expr_24[2], UInt<1>(0h1)
+                        connect _array_literal_expr_21[2], eq(_match_arm_value_11.src_ready_flags[2], _array_literal_expr_24[2])
+                        wire _cast_array_to_bits_expr_5: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_5[0], _array_literal_expr_21[0]
+                        connect _cast_array_to_bits_expr_5[1], _array_literal_expr_21[1]
+                        connect _cast_array_to_bits_expr_5[2], _array_literal_expr_21[2]
+                        wire _cast_to_bits_expr_5: UInt<3>
+                        connect _cast_to_bits_expr_5, cat(_cast_array_to_bits_expr_5[2], cat(_cast_array_to_bits_expr_5[1], _cast_array_to_bits_expr_5[0]))
+                        when andr(_cast_to_bits_expr_5): @[unit_base.rs 182:21]
+                            connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_6: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_18: Ty90
+        connect _bundle_literal_expr_18.empty_op_index, empty_op_index_5
+        connect _bundle_literal_expr_18.ready_op_index, ready_op_index_5
+        connect or_out_6, _bundle_literal_expr_18.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_19: Ty90
+        connect _bundle_literal_expr_19.empty_op_index, empty_op_index_4
+        connect _bundle_literal_expr_19.ready_op_index, ready_op_index_4
+        match _bundle_literal_expr_19.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_12):
-                connect or_out_4, and_then_out_6 @[function.rs 166:5]
-        wire or_out_5: Ty85 @[function.rs 166:5]
-        connect or_out_5, or_out_4 @[function.rs 166:5]
-        match or_out_3: @[function.rs 166:5]
+                wire _bundle_literal_expr_20: Ty90
+                connect _bundle_literal_expr_20.empty_op_index, empty_op_index_4
+                connect _bundle_literal_expr_20.ready_op_index, ready_op_index_4
+                connect or_out_6, _bundle_literal_expr_20.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_7: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_21: Ty90
+        connect _bundle_literal_expr_21.empty_op_index, empty_op_index_5
+        connect _bundle_literal_expr_21.ready_op_index, ready_op_index_5
+        connect or_out_7, _bundle_literal_expr_21.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_22: Ty90
+        connect _bundle_literal_expr_22.empty_op_index, empty_op_index_4
+        connect _bundle_literal_expr_22.ready_op_index, ready_op_index_4
+        match _bundle_literal_expr_22.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
                 skip
             HdlSome(_match_arm_value_13):
-                connect or_out_5, or_out_3 @[function.rs 166:5]
-        wire or_out_6: Ty85 @[function.rs 166:5]
-        connect or_out_6, or_out_5 @[function.rs 166:5]
-        match or_out_2: @[function.rs 166:5]
+                wire _bundle_literal_expr_23: Ty90
+                connect _bundle_literal_expr_23.empty_op_index, empty_op_index_4
+                connect _bundle_literal_expr_23.ready_op_index, ready_op_index_4
+                connect or_out_7, _bundle_literal_expr_23.ready_op_index @[unit_base.rs 204:29]
+        wire empty_op_index_6: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_6: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[6]: @[unit_base.rs 169:9]
             HdlNone:
-                skip
+                connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 189:13]
             HdlSome(_match_arm_value_14):
-                connect or_out_6, or_out_2 @[function.rs 166:5]
-        connect input_index, or_out_6 @[unit_base.rs 62:5]
-        wire input_in_flight_op: Ty88 @[unit_base.rs 73:30]
-        connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 74:5]
-        wire firing_data: Ty62 @[ready_valid.rs 30:27]
-        connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9]
-        when input_insn.ready: @[ready_valid.rs 33:9]
-            connect firing_data, input_insn.data @[ready_valid.rs 34:13]
-        match firing_data: @[unit_base.rs 76:5]
+                connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_14.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_25: UInt<1>[3]
+                        wire _array_literal_expr_26: UInt<1>[3]
+                        connect _array_literal_expr_26[0], UInt<1>(0h1)
+                        connect _array_literal_expr_26[1], UInt<1>(0h1)
+                        connect _array_literal_expr_26[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[0], eq(_match_arm_value_14.src_ready_flags[0], _array_literal_expr_26[0])
+                        wire _array_literal_expr_27: UInt<1>[3]
+                        connect _array_literal_expr_27[0], UInt<1>(0h1)
+                        connect _array_literal_expr_27[1], UInt<1>(0h1)
+                        connect _array_literal_expr_27[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[1], eq(_match_arm_value_14.src_ready_flags[1], _array_literal_expr_27[1])
+                        wire _array_literal_expr_28: UInt<1>[3]
+                        connect _array_literal_expr_28[0], UInt<1>(0h1)
+                        connect _array_literal_expr_28[1], UInt<1>(0h1)
+                        connect _array_literal_expr_28[2], UInt<1>(0h1)
+                        connect _array_literal_expr_25[2], eq(_match_arm_value_14.src_ready_flags[2], _array_literal_expr_28[2])
+                        wire _cast_array_to_bits_expr_6: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_6[0], _array_literal_expr_25[0]
+                        connect _cast_array_to_bits_expr_6[1], _array_literal_expr_25[1]
+                        connect _cast_array_to_bits_expr_6[2], _array_literal_expr_25[2]
+                        wire _cast_to_bits_expr_6: UInt<3>
+                        connect _cast_to_bits_expr_6, cat(_cast_array_to_bits_expr_6[2], cat(_cast_array_to_bits_expr_6[1], _cast_array_to_bits_expr_6[0]))
+                        when andr(_cast_to_bits_expr_6): @[unit_base.rs 182:21]
+                            connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire empty_op_index_7: Ty89 @[unit_base.rs 158:13]
+        connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9]
+        wire ready_op_index_7: Ty89 @[unit_base.rs 164:13]
+        connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9]
+        match in_flight_ops[7]: @[unit_base.rs 169:9]
+            HdlNone:
+                connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 189:13]
+            HdlSome(_match_arm_value_15):
+                connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13]
+                match _match_arm_value_15.state: @[unit_base.rs 178:13]
+                    Ready:
+                        wire _array_literal_expr_29: UInt<1>[3]
+                        wire _array_literal_expr_30: UInt<1>[3]
+                        connect _array_literal_expr_30[0], UInt<1>(0h1)
+                        connect _array_literal_expr_30[1], UInt<1>(0h1)
+                        connect _array_literal_expr_30[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[0], eq(_match_arm_value_15.src_ready_flags[0], _array_literal_expr_30[0])
+                        wire _array_literal_expr_31: UInt<1>[3]
+                        connect _array_literal_expr_31[0], UInt<1>(0h1)
+                        connect _array_literal_expr_31[1], UInt<1>(0h1)
+                        connect _array_literal_expr_31[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[1], eq(_match_arm_value_15.src_ready_flags[1], _array_literal_expr_31[1])
+                        wire _array_literal_expr_32: UInt<1>[3]
+                        connect _array_literal_expr_32[0], UInt<1>(0h1)
+                        connect _array_literal_expr_32[1], UInt<1>(0h1)
+                        connect _array_literal_expr_32[2], UInt<1>(0h1)
+                        connect _array_literal_expr_29[2], eq(_match_arm_value_15.src_ready_flags[2], _array_literal_expr_32[2])
+                        wire _cast_array_to_bits_expr_7: UInt<1>[3]
+                        connect _cast_array_to_bits_expr_7[0], _array_literal_expr_29[0]
+                        connect _cast_array_to_bits_expr_7[1], _array_literal_expr_29[1]
+                        connect _cast_array_to_bits_expr_7[2], _array_literal_expr_29[2]
+                        wire _cast_to_bits_expr_7: UInt<3>
+                        connect _cast_to_bits_expr_7, cat(_cast_array_to_bits_expr_7[2], cat(_cast_array_to_bits_expr_7[1], _cast_array_to_bits_expr_7[0]))
+                        when andr(_cast_to_bits_expr_7): @[unit_base.rs 182:21]
+                            connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 183:25]
+                    Running:
+                        skip
+                    CanceledAndRunning:
+                        skip
+        wire or_out_8: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_24: Ty90
+        connect _bundle_literal_expr_24.empty_op_index, empty_op_index_7
+        connect _bundle_literal_expr_24.ready_op_index, ready_op_index_7
+        connect or_out_8, _bundle_literal_expr_24.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_25: Ty90
+        connect _bundle_literal_expr_25.empty_op_index, empty_op_index_6
+        connect _bundle_literal_expr_25.ready_op_index, ready_op_index_6
+        match _bundle_literal_expr_25.empty_op_index: @[unit_base.rs 203:29]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_15):
-                wire input_in_flight_op_src_values: Ty86[3] @[unit_base.rs 79:13]
-                wire _array_literal_expr_1: Ty86[3]
-                wire _bundle_literal_expr: Ty65
-                connect _bundle_literal_expr.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_1: Ty64
-                connect _bundle_literal_expr_1.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_1.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr.flags, _bundle_literal_expr_1
-                connect _array_literal_expr_1[0], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr)
-                wire _bundle_literal_expr_2: Ty65
-                connect _bundle_literal_expr_2.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_3: Ty64
-                connect _bundle_literal_expr_3.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_3.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr_2.flags, _bundle_literal_expr_3
-                connect _array_literal_expr_1[1], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_2)
-                wire _bundle_literal_expr_4: Ty65
-                connect _bundle_literal_expr_4.int_fp, UInt<64>(0h0)
-                wire _bundle_literal_expr_5: Ty64
-                connect _bundle_literal_expr_5.pwr_ca_x86_cf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ca32_x86_af, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ov_x86_of, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_ov32_x86_df, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_lt_x86_sf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_gt_x86_pf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_cr_eq_x86_zf, UInt<1>(0h0)
-                connect _bundle_literal_expr_5.pwr_so, UInt<1>(0h0)
-                connect _bundle_literal_expr_4.flags, _bundle_literal_expr_5
-                connect _array_literal_expr_1[2], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_4)
-                connect input_in_flight_op_src_values, _array_literal_expr_1 @[unit_base.rs 82:9]
-                match _match_arm_value_15: @[instruction.rs 502:1]
-                    AddSub(_match_arm_value_16):
-                        wire _bundle_literal_expr_6: Ty25
-                        wire _bundle_literal_expr_7: Ty23
-                        connect _bundle_literal_expr_7.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_6.unit_num, _bundle_literal_expr_7
-                        wire _bundle_literal_expr_8: Ty24
-                        connect _bundle_literal_expr_8.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_6.unit_out_reg, _bundle_literal_expr_8
-                        wire _cast_bundle_to_bits_expr: Ty57
-                        connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_6.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_6.unit_out_reg.value
-                        wire _cast_to_bits_expr: UInt<6>
-                        connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num)
-                        when neq(_cast_to_bits_expr, _match_arm_value_16.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_9: Ty25
-                        wire _bundle_literal_expr_10: Ty23
-                        connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10
-                        wire _bundle_literal_expr_11: Ty24
-                        connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11
-                        wire _cast_bundle_to_bits_expr_1: Ty57
-                        connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_9.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_9.unit_out_reg.value
-                        wire _cast_to_bits_expr_1: UInt<6>
-                        connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num)
-                        when neq(_cast_to_bits_expr_1, _match_arm_value_16.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_12: Ty25
-                        wire _bundle_literal_expr_13: Ty23
-                        connect _bundle_literal_expr_13.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_12.unit_num, _bundle_literal_expr_13
-                        wire _bundle_literal_expr_14: Ty24
-                        connect _bundle_literal_expr_14.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_12.unit_out_reg, _bundle_literal_expr_14
-                        wire _cast_bundle_to_bits_expr_2: Ty57
-                        connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_12.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_12.unit_out_reg.value
-                        wire _cast_to_bits_expr_2: UInt<6>
-                        connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num)
-                        when neq(_cast_to_bits_expr_2, _match_arm_value_16.alu_common.common.src[2]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[2], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                    AddSubI(_match_arm_value_17):
-                        wire _bundle_literal_expr_15: Ty25
-                        wire _bundle_literal_expr_16: Ty23
-                        connect _bundle_literal_expr_16.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_15.unit_num, _bundle_literal_expr_16
-                        wire _bundle_literal_expr_17: Ty24
-                        connect _bundle_literal_expr_17.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_15.unit_out_reg, _bundle_literal_expr_17
-                        wire _cast_bundle_to_bits_expr_3: Ty57
-                        connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_15.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_15.unit_out_reg.value
-                        wire _cast_to_bits_expr_3: UInt<6>
-                        connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num)
-                        when neq(_cast_to_bits_expr_3, _match_arm_value_17.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_18: Ty25
-                        wire _bundle_literal_expr_19: Ty23
-                        connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19
-                        wire _bundle_literal_expr_20: Ty24
-                        connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20
-                        wire _cast_bundle_to_bits_expr_4: Ty57
-                        connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_18.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_18.unit_out_reg.value
-                        wire _cast_to_bits_expr_4: UInt<6>
-                        connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num)
-                        when neq(_cast_to_bits_expr_4, _match_arm_value_17.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                    Logical(_match_arm_value_18):
-                        wire _bundle_literal_expr_21: Ty25
-                        wire _bundle_literal_expr_22: Ty23
-                        connect _bundle_literal_expr_22.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22
-                        wire _bundle_literal_expr_23: Ty24
-                        connect _bundle_literal_expr_23.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23
-                        wire _cast_bundle_to_bits_expr_5: Ty57
-                        connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_21.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_21.unit_out_reg.value
-                        wire _cast_to_bits_expr_5: UInt<6>
-                        connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num)
-                        when neq(_cast_to_bits_expr_5, _match_arm_value_18.alu_common.common.src[0]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                        wire _bundle_literal_expr_24: Ty25
-                        wire _bundle_literal_expr_25: Ty23
-                        connect _bundle_literal_expr_25.adj_value, tail(UInt<64>(0h0), 62)
-                        connect _bundle_literal_expr_24.unit_num, _bundle_literal_expr_25
-                        wire _bundle_literal_expr_26: Ty24
-                        connect _bundle_literal_expr_26.value, tail(UInt<8>(0h0), 4)
-                        connect _bundle_literal_expr_24.unit_out_reg, _bundle_literal_expr_26
-                        wire _cast_bundle_to_bits_expr_6: Ty57
-                        connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_24.unit_num.adj_value
-                        connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_24.unit_out_reg.value
-                        wire _cast_to_bits_expr_6: UInt<6>
-                        connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num)
-                        when neq(_cast_to_bits_expr_6, _match_arm_value_18.alu_common.common.src[1]): @[unit_base.rs 88:13]
-                            connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17]
-                wire _bundle_literal_expr_27: Ty87
-                connect _bundle_literal_expr_27.mop, _match_arm_value_15
-                connect _bundle_literal_expr_27.src_values, input_in_flight_op_src_values
-                connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_27) @[unit_base.rs 97:9]
-        match in_flight_ops[0]: @[unit_base.rs 107:9]
+            HdlSome(_match_arm_value_16):
+                wire _bundle_literal_expr_26: Ty90
+                connect _bundle_literal_expr_26.empty_op_index, empty_op_index_6
+                connect _bundle_literal_expr_26.ready_op_index, ready_op_index_6
+                connect or_out_8, _bundle_literal_expr_26.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_9: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_27: Ty90
+        connect _bundle_literal_expr_27.empty_op_index, empty_op_index_7
+        connect _bundle_literal_expr_27.ready_op_index, ready_op_index_7
+        connect or_out_9, _bundle_literal_expr_27.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_28: Ty90
+        connect _bundle_literal_expr_28.empty_op_index, empty_op_index_6
+        connect _bundle_literal_expr_28.ready_op_index, ready_op_index_6
+        match _bundle_literal_expr_28.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_19):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_19, UInt<64>(0h0)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[0], input_in_flight_op @[unit_base.rs 126:17]
+                skip
+            HdlSome(_match_arm_value_17):
+                wire _bundle_literal_expr_29: Ty90
+                connect _bundle_literal_expr_29.empty_op_index, empty_op_index_6
+                connect _bundle_literal_expr_29.ready_op_index, ready_op_index_6
+                connect or_out_9, _bundle_literal_expr_29.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_10: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_30: Ty90
+        connect _bundle_literal_expr_30.empty_op_index, or_out_8
+        connect _bundle_literal_expr_30.ready_op_index, or_out_9
+        connect or_out_10, _bundle_literal_expr_30.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_31: Ty90
+        connect _bundle_literal_expr_31.empty_op_index, or_out_6
+        connect _bundle_literal_expr_31.ready_op_index, or_out_7
+        match _bundle_literal_expr_31.empty_op_index: @[unit_base.rs 203:29]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_18):
+                wire _bundle_literal_expr_32: Ty90
+                connect _bundle_literal_expr_32.empty_op_index, or_out_6
+                connect _bundle_literal_expr_32.ready_op_index, or_out_7
+                connect or_out_10, _bundle_literal_expr_32.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_11: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_33: Ty90
+        connect _bundle_literal_expr_33.empty_op_index, or_out_8
+        connect _bundle_literal_expr_33.ready_op_index, or_out_9
+        connect or_out_11, _bundle_literal_expr_33.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_34: Ty90
+        connect _bundle_literal_expr_34.empty_op_index, or_out_6
+        connect _bundle_literal_expr_34.ready_op_index, or_out_7
+        match _bundle_literal_expr_34.ready_op_index: @[unit_base.rs 204:29]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_19):
+                wire _bundle_literal_expr_35: Ty90
+                connect _bundle_literal_expr_35.empty_op_index, or_out_6
+                connect _bundle_literal_expr_35.ready_op_index, or_out_7
+                connect or_out_11, _bundle_literal_expr_35.ready_op_index @[unit_base.rs 204:29]
+        wire or_out_12: Ty89 @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_36: Ty90
+        connect _bundle_literal_expr_36.empty_op_index, or_out_10
+        connect _bundle_literal_expr_36.ready_op_index, or_out_11
+        connect or_out_12, _bundle_literal_expr_36.empty_op_index @[unit_base.rs 203:29]
+        wire _bundle_literal_expr_37: Ty90
+        connect _bundle_literal_expr_37.empty_op_index, or_out_4
+        connect _bundle_literal_expr_37.ready_op_index, or_out_5
+        match _bundle_literal_expr_37.empty_op_index: @[unit_base.rs 203:29]
+            HdlNone:
+                skip
             HdlSome(_match_arm_value_20):
-                wire firing_data_1: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_1, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_1, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_1: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_21):
-                        wire dest_reg: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_20.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_22):
-                                connect dest_reg, _match_arm_value_22.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_23):
-                                connect dest_reg, _match_arm_value_23.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_24):
-                                connect dest_reg, _match_arm_value_24.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_21.which.value, dest_reg.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[1]: @[unit_base.rs 107:9]
+                wire _bundle_literal_expr_38: Ty90
+                connect _bundle_literal_expr_38.empty_op_index, or_out_4
+                connect _bundle_literal_expr_38.ready_op_index, or_out_5
+                connect or_out_12, _bundle_literal_expr_38.empty_op_index @[unit_base.rs 203:29]
+        wire or_out_13: Ty89 @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_39: Ty90
+        connect _bundle_literal_expr_39.empty_op_index, or_out_10
+        connect _bundle_literal_expr_39.ready_op_index, or_out_11
+        connect or_out_13, _bundle_literal_expr_39.ready_op_index @[unit_base.rs 204:29]
+        wire _bundle_literal_expr_40: Ty90
+        connect _bundle_literal_expr_40.empty_op_index, or_out_4
+        connect _bundle_literal_expr_40.ready_op_index, or_out_5
+        match _bundle_literal_expr_40.ready_op_index: @[unit_base.rs 204:29]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_25):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_25, UInt<64>(0h1)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[1], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_26):
-                wire firing_data_2: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_2, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_2, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_2: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_27):
-                        wire dest_reg_1: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_26.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_28):
-                                connect dest_reg_1, _match_arm_value_28.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_29):
-                                connect dest_reg_1, _match_arm_value_29.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_30):
-                                connect dest_reg_1, _match_arm_value_30.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_27.which.value, dest_reg_1.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[2]: @[unit_base.rs 107:9]
+                skip
+            HdlSome(_match_arm_value_21):
+                wire _bundle_literal_expr_41: Ty90
+                connect _bundle_literal_expr_41.empty_op_index, or_out_4
+                connect _bundle_literal_expr_41.ready_op_index, or_out_5
+                connect or_out_13, _bundle_literal_expr_41.ready_op_index @[unit_base.rs 204:29]
+        wire in_flight_ops_summary: Ty90 @[unit_base.rs 257:33]
+        wire _bundle_literal_expr_42: Ty90
+        connect _bundle_literal_expr_42.empty_op_index, or_out_12
+        connect _bundle_literal_expr_42.ready_op_index, or_out_13
+        connect in_flight_ops_summary, _bundle_literal_expr_42 @[unit_base.rs 258:5]
+        wire is_some_out: UInt<1> @[unit_base.rs 262:9]
+        connect is_some_out, UInt<1>(0h0) @[unit_base.rs 262:9]
+        match in_flight_ops_summary.empty_op_index: @[unit_base.rs 262:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                skip
+            HdlSome(_match_arm_value_22):
+                connect is_some_out, UInt<1>(0h1) @[unit_base.rs 262:9]
+        connect unit_to_reg_alloc.input_insn.ready, is_some_out @[unit_base.rs 260:5]
+        connect unit_to_reg_alloc.`output`, {|HdlNone, HdlSome: Ty73|}(HdlNone) @[unit_base.rs 266:5]
+        wire input_in_flight_op: Ty88 @[unit_base.rs 272:30]
+        connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 273:5]
+        wire firing_data: Ty67 @[ready_valid.rs 30:27]
+        connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9]
+        when unit_to_reg_alloc.input_insn.ready: @[ready_valid.rs 33:9]
+            connect firing_data, unit_to_reg_alloc.input_insn.data @[ready_valid.rs 34:13]
+        match firing_data: @[unit_base.rs 275:5]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_23):
+                wire input_mop_src_regs: UInt<6>[3] @[unit_base.rs 277:34]
+                wire _array_literal_expr_33: UInt<6>[3]
+                wire _bundle_literal_expr_43: Ty25
+                wire _bundle_literal_expr_44: Ty23
+                connect _bundle_literal_expr_44.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_43.unit_num, _bundle_literal_expr_44
+                wire _bundle_literal_expr_45: Ty24
+                connect _bundle_literal_expr_45.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_43.unit_out_reg, _bundle_literal_expr_45
+                wire _cast_bundle_to_bits_expr: Ty57
+                connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_43.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_43.unit_out_reg.value
+                wire _cast_to_bits_expr_8: UInt<6>
+                connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num)
+                connect _array_literal_expr_33[0], _cast_to_bits_expr_8
+                wire _bundle_literal_expr_46: Ty25
+                wire _bundle_literal_expr_47: Ty23
+                connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47
+                wire _bundle_literal_expr_48: Ty24
+                connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48
+                wire _cast_bundle_to_bits_expr_1: Ty57
+                connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_46.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_46.unit_out_reg.value
+                wire _cast_to_bits_expr_9: UInt<6>
+                connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num)
+                connect _array_literal_expr_33[1], _cast_to_bits_expr_9
+                wire _bundle_literal_expr_49: Ty25
+                wire _bundle_literal_expr_50: Ty23
+                connect _bundle_literal_expr_50.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_49.unit_num, _bundle_literal_expr_50
+                wire _bundle_literal_expr_51: Ty24
+                connect _bundle_literal_expr_51.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_49.unit_out_reg, _bundle_literal_expr_51
+                wire _cast_bundle_to_bits_expr_2: Ty57
+                connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_49.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_49.unit_out_reg.value
+                wire _cast_to_bits_expr_10: UInt<6>
+                connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num)
+                connect _array_literal_expr_33[2], _cast_to_bits_expr_10
+                connect input_mop_src_regs, _array_literal_expr_33 @[unit_base.rs 278:9]
+                match _match_arm_value_23: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_24):
+                        connect input_mop_src_regs[0], _match_arm_value_24.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_24.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[2], _match_arm_value_24.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_25):
+                        connect input_mop_src_regs[0], _match_arm_value_25.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_25.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_26):
+                        connect input_mop_src_regs[0], _match_arm_value_26.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect input_mop_src_regs[1], _match_arm_value_26.alu_common.common.src[1] @[instruction.rs 36:13]
+                wire input_in_flight_op_src_ready_flags: UInt<1>[3] @[unit_base.rs 285:13]
+                wire _bundle_literal_expr_52: Ty25
+                wire _bundle_literal_expr_53: Ty23
+                connect _bundle_literal_expr_53.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_52.unit_num, _bundle_literal_expr_53
+                wire _bundle_literal_expr_54: Ty24
+                connect _bundle_literal_expr_54.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_52.unit_out_reg, _bundle_literal_expr_54
+                wire _cast_bundle_to_bits_expr_3: Ty57
+                connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_52.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_52.unit_out_reg.value
+                wire _cast_to_bits_expr_11: UInt<6>
+                connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num)
+                connect input_in_flight_op_src_ready_flags[0], eq(_cast_to_bits_expr_11, input_mop_src_regs[0]) @[unit_base.rs 289:13]
+                wire _bundle_literal_expr_55: Ty25
+                wire _bundle_literal_expr_56: Ty23
+                connect _bundle_literal_expr_56.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_55.unit_num, _bundle_literal_expr_56
+                wire _bundle_literal_expr_57: Ty24
+                connect _bundle_literal_expr_57.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_55.unit_out_reg, _bundle_literal_expr_57
+                wire _cast_bundle_to_bits_expr_4: Ty57
+                connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_55.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_55.unit_out_reg.value
+                wire _cast_to_bits_expr_12: UInt<6>
+                connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num)
+                connect input_in_flight_op_src_ready_flags[1], eq(_cast_to_bits_expr_12, input_mop_src_regs[1]) @[unit_base.rs 289:13]
+                wire _bundle_literal_expr_58: Ty25
+                wire _bundle_literal_expr_59: Ty23
+                connect _bundle_literal_expr_59.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_58.unit_num, _bundle_literal_expr_59
+                wire _bundle_literal_expr_60: Ty24
+                connect _bundle_literal_expr_60.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_58.unit_out_reg, _bundle_literal_expr_60
+                wire _cast_bundle_to_bits_expr_5: Ty57
+                connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_58.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_58.unit_out_reg.value
+                wire _cast_to_bits_expr_13: UInt<6>
+                connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num)
+                connect input_in_flight_op_src_ready_flags[2], eq(_cast_to_bits_expr_13, input_mop_src_regs[2]) @[unit_base.rs 289:13]
+                wire dest_reg: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_23: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_27):
+                        connect dest_reg, _match_arm_value_27.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_28):
+                        connect dest_reg, _match_arm_value_28.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_29):
+                        connect dest_reg, _match_arm_value_29.alu_common.common.dest @[instruction.rs 538:1]
+                wire cmp_ne: UInt<1> @[enum_.rs 396:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 398:9]
                     HdlNone:
-                        skip
+                        wire _bundle_literal_expr_61: Ty69
+                        connect _bundle_literal_expr_61.which, dest_reg
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_61): @[enum_.rs 410:17]
+                            HdlNone:
+                                connect cmp_ne, UInt<1>(0h0) @[enum_.rs 412:32]
+                            HdlSome(_match_arm_value_30):
+                                connect cmp_ne, UInt<1>(0h1) @[enum_.rs 411:35]
                     HdlSome(_match_arm_value_31):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_31, UInt<64>(0h2)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[2], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_32):
-                wire firing_data_3: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_3, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_3, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_3: @[unit_base.rs 109:13]
+                        wire _bundle_literal_expr_62: Ty69
+                        connect _bundle_literal_expr_62.which, dest_reg
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_62): @[enum_.rs 402:17]
+                            HdlNone:
+                                connect cmp_ne, UInt<1>(0h1) @[enum_.rs 404:32]
+                            HdlSome(_match_arm_value_32):
+                                connect cmp_ne, neq(_match_arm_value_31.which.value, _match_arm_value_32.which.value) @[enum_.rs 403:37]
+                when cmp_ne: @[unit_base.rs 299:9]
+                    wire _bundle_literal_expr_63: Ty87
+                    connect _bundle_literal_expr_63.state, {|Ready, Running, CanceledAndRunning|}(Ready)
+                    connect _bundle_literal_expr_63.mop, _match_arm_value_23
+                    connect _bundle_literal_expr_63.src_ready_flags, input_in_flight_op_src_ready_flags
+                    connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_63) @[unit_base.rs 305:13]
+                match in_flight_ops_summary.empty_op_index: @[unit_base.rs 318:9]
                     HdlNone:
                         skip
                     HdlSome(_match_arm_value_33):
-                        wire dest_reg_2: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_32.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_34):
-                                connect dest_reg_2, _match_arm_value_34.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_35):
-                                connect dest_reg_2, _match_arm_value_35.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_36):
-                                connect dest_reg_2, _match_arm_value_36.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_33.which.value, dest_reg_2.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[3]: @[unit_base.rs 107:9]
+                        connect in_flight_ops[_match_arm_value_33], input_in_flight_op @[unit_base.rs 319:13]
+        wire in_flight_op_next_state: Ty91[8] @[unit_base.rs 324:35]
+        wire in_flight_op_next_src_ready_flags: UInt<1>[3][8] @[unit_base.rs 327:9]
+        wire in_flight_op_canceling: UInt<1>[8] @[unit_base.rs 329:34]
+        wire in_flight_op_execute_starting: UInt<1>[8] @[unit_base.rs 331:41]
+        wire in_flight_op_execute_ending: UInt<1>[8] @[unit_base.rs 333:39]
+        wire _array_literal_expr_34: UInt<1>[3]
+        connect _array_literal_expr_34[0], UInt<1>(0h0)
+        connect _array_literal_expr_34[1], UInt<1>(0h0)
+        connect _array_literal_expr_34[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[0], _array_literal_expr_34 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[0], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[0], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[0], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[0]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_34):
+                wire dest_reg_1: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_34.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_35):
+                        connect dest_reg_1, _match_arm_value_35.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_36):
+                        connect dest_reg_1, _match_arm_value_36.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_37):
+                        connect dest_reg_1, _match_arm_value_37.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_0: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_35: UInt<6>[3]
+                wire _bundle_literal_expr_64: Ty25
+                wire _bundle_literal_expr_65: Ty23
+                connect _bundle_literal_expr_65.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_64.unit_num, _bundle_literal_expr_65
+                wire _bundle_literal_expr_66: Ty24
+                connect _bundle_literal_expr_66.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_64.unit_out_reg, _bundle_literal_expr_66
+                wire _cast_bundle_to_bits_expr_6: Ty57
+                connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_64.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_64.unit_out_reg.value
+                wire _cast_to_bits_expr_14: UInt<6>
+                connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num)
+                connect _array_literal_expr_35[0], _cast_to_bits_expr_14
+                wire _bundle_literal_expr_67: Ty25
+                wire _bundle_literal_expr_68: Ty23
+                connect _bundle_literal_expr_68.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_67.unit_num, _bundle_literal_expr_68
+                wire _bundle_literal_expr_69: Ty24
+                connect _bundle_literal_expr_69.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_67.unit_out_reg, _bundle_literal_expr_69
+                wire _cast_bundle_to_bits_expr_7: Ty57
+                connect _cast_bundle_to_bits_expr_7.unit_num, _bundle_literal_expr_67.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_7.unit_out_reg, _bundle_literal_expr_67.unit_out_reg.value
+                wire _cast_to_bits_expr_15: UInt<6>
+                connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num)
+                connect _array_literal_expr_35[1], _cast_to_bits_expr_15
+                wire _bundle_literal_expr_70: Ty25
+                wire _bundle_literal_expr_71: Ty23
+                connect _bundle_literal_expr_71.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_70.unit_num, _bundle_literal_expr_71
+                wire _bundle_literal_expr_72: Ty24
+                connect _bundle_literal_expr_72.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_70.unit_out_reg, _bundle_literal_expr_72
+                wire _cast_bundle_to_bits_expr_8: Ty57
+                connect _cast_bundle_to_bits_expr_8.unit_num, _bundle_literal_expr_70.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_8.unit_out_reg, _bundle_literal_expr_70.unit_out_reg.value
+                wire _cast_to_bits_expr_16: UInt<6>
+                connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num)
+                connect _array_literal_expr_35[2], _cast_to_bits_expr_16
+                connect in_flight_op_src_regs_0, _array_literal_expr_35 @[unit_base.rs 356:13]
+                match _match_arm_value_34.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_38):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_38.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_38.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[2], _match_arm_value_38.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_39):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_39.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_39.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_40):
+                        connect in_flight_op_src_regs_0[0], _match_arm_value_40.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_0[1], _match_arm_value_40.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[0], _match_arm_value_34.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_37):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_37, UInt<64>(0h3)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[3], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_38):
-                wire firing_data_4: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_4, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_4, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_4: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_41):
+                        wire _bundle_literal_expr_73: Ty25
+                        wire _bundle_literal_expr_74: Ty23
+                        connect _bundle_literal_expr_74.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_73.unit_num, _bundle_literal_expr_74
+                        connect _bundle_literal_expr_73.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_9: Ty57
+                        connect _cast_bundle_to_bits_expr_9.unit_num, _bundle_literal_expr_73.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_9.unit_out_reg, _bundle_literal_expr_73.unit_out_reg.value
+                        wire _cast_to_bits_expr_17: UInt<6>
+                        connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_9.unit_out_reg, _cast_bundle_to_bits_expr_9.unit_num)
+                        when eq(_cast_to_bits_expr_17, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_75: Ty25
+                        wire _bundle_literal_expr_76: Ty23
+                        connect _bundle_literal_expr_76.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_75.unit_num, _bundle_literal_expr_76
+                        connect _bundle_literal_expr_75.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_10: Ty57
+                        connect _cast_bundle_to_bits_expr_10.unit_num, _bundle_literal_expr_75.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_10.unit_out_reg, _bundle_literal_expr_75.unit_out_reg.value
+                        wire _cast_to_bits_expr_18: UInt<6>
+                        connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_10.unit_out_reg, _cast_bundle_to_bits_expr_10.unit_num)
+                        when eq(_cast_to_bits_expr_18, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_77: Ty25
+                        wire _bundle_literal_expr_78: Ty23
+                        connect _bundle_literal_expr_78.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_77.unit_num, _bundle_literal_expr_78
+                        connect _bundle_literal_expr_77.unit_out_reg, _match_arm_value_41.which
+                        wire _cast_bundle_to_bits_expr_11: Ty57
+                        connect _cast_bundle_to_bits_expr_11.unit_num, _bundle_literal_expr_77.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_11.unit_out_reg, _bundle_literal_expr_77.unit_out_reg.value
+                        wire _cast_to_bits_expr_19: UInt<6>
+                        connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num)
+                        when eq(_cast_to_bits_expr_19, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_39):
-                        wire dest_reg_3: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_38.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_40):
-                                connect dest_reg_3, _match_arm_value_40.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_41):
-                                connect dest_reg_3, _match_arm_value_41.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_42):
-                                connect dest_reg_3, _match_arm_value_42.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_39.which.value, dest_reg_3.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[4]: @[unit_base.rs 107:9]
-            HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                    HdlSome(_match_arm_value_42):
+                        wire _bundle_literal_expr_79: Ty25
+                        wire _bundle_literal_expr_80: Ty23
+                        connect _bundle_literal_expr_80.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_79.unit_num, _bundle_literal_expr_80
+                        connect _bundle_literal_expr_79.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_12: Ty57
+                        connect _cast_bundle_to_bits_expr_12.unit_num, _bundle_literal_expr_79.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_12.unit_out_reg, _bundle_literal_expr_79.unit_out_reg.value
+                        wire _cast_to_bits_expr_20: UInt<6>
+                        connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num)
+                        when eq(_cast_to_bits_expr_20, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_81: Ty25
+                        wire _bundle_literal_expr_82: Ty23
+                        connect _bundle_literal_expr_82.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_81.unit_num, _bundle_literal_expr_82
+                        connect _bundle_literal_expr_81.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_13: Ty57
+                        connect _cast_bundle_to_bits_expr_13.unit_num, _bundle_literal_expr_81.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_13.unit_out_reg, _bundle_literal_expr_81.unit_out_reg.value
+                        wire _cast_to_bits_expr_21: UInt<6>
+                        connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num)
+                        when eq(_cast_to_bits_expr_21, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_83: Ty25
+                        wire _bundle_literal_expr_84: Ty23
+                        connect _bundle_literal_expr_84.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_83.unit_num, _bundle_literal_expr_84
+                        connect _bundle_literal_expr_83.unit_out_reg, _match_arm_value_42.which
+                        wire _cast_bundle_to_bits_expr_14: Ty57
+                        connect _cast_bundle_to_bits_expr_14.unit_num, _bundle_literal_expr_83.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_14.unit_out_reg, _bundle_literal_expr_83.unit_out_reg.value
+                        wire _cast_to_bits_expr_22: UInt<6>
+                        connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num)
+                        when eq(_cast_to_bits_expr_22, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_85: Ty69
+                        connect _bundle_literal_expr_85.which, dest_reg_1
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_85): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_43):
+                                connect cmp_eq, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_44):
+                        wire _bundle_literal_expr_86: Ty69
+                        connect _bundle_literal_expr_86.which, dest_reg_1
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_86): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_45):
+                                connect cmp_eq, eq(_match_arm_value_44.which.value, _match_arm_value_45.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[0], cmp_eq @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_43):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_43, UInt<64>(0h4)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[4], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_44):
-                wire firing_data_5: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_5, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_5, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_5: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_46):
+                        when eq(dest_reg_1.value, _match_arm_value_46.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[0], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_1: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_1, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_1, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_1: @[unit_base.rs 410:13]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_45):
-                        wire dest_reg_4: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_44.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_46):
-                                connect dest_reg_4, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_47):
-                                connect dest_reg_4, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_48):
-                                connect dest_reg_4, _match_arm_value_48.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_45.which.value, dest_reg_4.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[5]: @[unit_base.rs 107:9]
-            HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                    HdlSome(_match_arm_value_47):
+                        wire dest_reg_2: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_47.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_48):
+                                connect dest_reg_2, _match_arm_value_48.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_49):
+                                connect dest_reg_2, _match_arm_value_49.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_50):
+                                connect dest_reg_2, _match_arm_value_50.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_1.value, dest_reg_2.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[0], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_34.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[0]: @[unit_base.rs 434:13]
                     HdlNone:
-                        skip
-                    HdlSome(_match_arm_value_49):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_49, UInt<64>(0h5)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[5], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_50):
-                wire firing_data_6: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_6, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_6, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_6: @[unit_base.rs 109:13]
-                    HdlNone:
-                        skip
+                        connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
                     HdlSome(_match_arm_value_51):
-                        wire dest_reg_5: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_50.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_52):
-                                connect dest_reg_5, _match_arm_value_52.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_53):
-                                connect dest_reg_5, _match_arm_value_53.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_54):
-                                connect dest_reg_5, _match_arm_value_54.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_51.which.value, dest_reg_5.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[6]: @[unit_base.rs 107:9]
+                        wire _bundle_literal_expr_87: Ty87
+                        connect _bundle_literal_expr_87.state, _match_arm_value_51
+                        connect _bundle_literal_expr_87.mop, _match_arm_value_34.mop
+                        connect _bundle_literal_expr_87.src_ready_flags, _match_arm_value_34.src_ready_flags
+                        connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_87) @[unit_base.rs 435:17]
+        wire _array_literal_expr_36: UInt<1>[3]
+        connect _array_literal_expr_36[0], UInt<1>(0h0)
+        connect _array_literal_expr_36[1], UInt<1>(0h0)
+        connect _array_literal_expr_36[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[1], _array_literal_expr_36 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[1], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[1], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[1], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[1]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_52):
+                wire dest_reg_3: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_52.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_53):
+                        connect dest_reg_3, _match_arm_value_53.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_54):
+                        connect dest_reg_3, _match_arm_value_54.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_55):
+                        connect dest_reg_3, _match_arm_value_55.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_1: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_37: UInt<6>[3]
+                wire _bundle_literal_expr_88: Ty25
+                wire _bundle_literal_expr_89: Ty23
+                connect _bundle_literal_expr_89.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_88.unit_num, _bundle_literal_expr_89
+                wire _bundle_literal_expr_90: Ty24
+                connect _bundle_literal_expr_90.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_88.unit_out_reg, _bundle_literal_expr_90
+                wire _cast_bundle_to_bits_expr_15: Ty57
+                connect _cast_bundle_to_bits_expr_15.unit_num, _bundle_literal_expr_88.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_15.unit_out_reg, _bundle_literal_expr_88.unit_out_reg.value
+                wire _cast_to_bits_expr_23: UInt<6>
+                connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_15.unit_out_reg, _cast_bundle_to_bits_expr_15.unit_num)
+                connect _array_literal_expr_37[0], _cast_to_bits_expr_23
+                wire _bundle_literal_expr_91: Ty25
+                wire _bundle_literal_expr_92: Ty23
+                connect _bundle_literal_expr_92.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_91.unit_num, _bundle_literal_expr_92
+                wire _bundle_literal_expr_93: Ty24
+                connect _bundle_literal_expr_93.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_91.unit_out_reg, _bundle_literal_expr_93
+                wire _cast_bundle_to_bits_expr_16: Ty57
+                connect _cast_bundle_to_bits_expr_16.unit_num, _bundle_literal_expr_91.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_16.unit_out_reg, _bundle_literal_expr_91.unit_out_reg.value
+                wire _cast_to_bits_expr_24: UInt<6>
+                connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_16.unit_out_reg, _cast_bundle_to_bits_expr_16.unit_num)
+                connect _array_literal_expr_37[1], _cast_to_bits_expr_24
+                wire _bundle_literal_expr_94: Ty25
+                wire _bundle_literal_expr_95: Ty23
+                connect _bundle_literal_expr_95.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_94.unit_num, _bundle_literal_expr_95
+                wire _bundle_literal_expr_96: Ty24
+                connect _bundle_literal_expr_96.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_94.unit_out_reg, _bundle_literal_expr_96
+                wire _cast_bundle_to_bits_expr_17: Ty57
+                connect _cast_bundle_to_bits_expr_17.unit_num, _bundle_literal_expr_94.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_17.unit_out_reg, _bundle_literal_expr_94.unit_out_reg.value
+                wire _cast_to_bits_expr_25: UInt<6>
+                connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_17.unit_out_reg, _cast_bundle_to_bits_expr_17.unit_num)
+                connect _array_literal_expr_37[2], _cast_to_bits_expr_25
+                connect in_flight_op_src_regs_1, _array_literal_expr_37 @[unit_base.rs 356:13]
+                match _match_arm_value_52.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_56):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_56.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_56.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[2], _match_arm_value_56.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_57):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_57.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_57.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_58):
+                        connect in_flight_op_src_regs_1[0], _match_arm_value_58.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_1[1], _match_arm_value_58.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[1], _match_arm_value_52.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_55):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_55, UInt<64>(0h6)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[6], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_56):
-                wire firing_data_7: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_7, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_7, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_7: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_59):
+                        wire _bundle_literal_expr_97: Ty25
+                        wire _bundle_literal_expr_98: Ty23
+                        connect _bundle_literal_expr_98.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_97.unit_num, _bundle_literal_expr_98
+                        connect _bundle_literal_expr_97.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_18: Ty57
+                        connect _cast_bundle_to_bits_expr_18.unit_num, _bundle_literal_expr_97.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_18.unit_out_reg, _bundle_literal_expr_97.unit_out_reg.value
+                        wire _cast_to_bits_expr_26: UInt<6>
+                        connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num)
+                        when eq(_cast_to_bits_expr_26, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_99: Ty25
+                        wire _bundle_literal_expr_100: Ty23
+                        connect _bundle_literal_expr_100.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_99.unit_num, _bundle_literal_expr_100
+                        connect _bundle_literal_expr_99.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_19: Ty57
+                        connect _cast_bundle_to_bits_expr_19.unit_num, _bundle_literal_expr_99.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_19.unit_out_reg, _bundle_literal_expr_99.unit_out_reg.value
+                        wire _cast_to_bits_expr_27: UInt<6>
+                        connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num)
+                        when eq(_cast_to_bits_expr_27, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_101: Ty25
+                        wire _bundle_literal_expr_102: Ty23
+                        connect _bundle_literal_expr_102.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_101.unit_num, _bundle_literal_expr_102
+                        connect _bundle_literal_expr_101.unit_out_reg, _match_arm_value_59.which
+                        wire _cast_bundle_to_bits_expr_20: Ty57
+                        connect _cast_bundle_to_bits_expr_20.unit_num, _bundle_literal_expr_101.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_20.unit_out_reg, _bundle_literal_expr_101.unit_out_reg.value
+                        wire _cast_to_bits_expr_28: UInt<6>
+                        connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num)
+                        when eq(_cast_to_bits_expr_28, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_57):
-                        wire dest_reg_6: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_56.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_58):
-                                connect dest_reg_6, _match_arm_value_58.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_59):
-                                connect dest_reg_6, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_60):
-                                connect dest_reg_6, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_57.which.value, dest_reg_6.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
-        match in_flight_ops[7]: @[unit_base.rs 107:9]
+                    HdlSome(_match_arm_value_60):
+                        wire _bundle_literal_expr_103: Ty25
+                        wire _bundle_literal_expr_104: Ty23
+                        connect _bundle_literal_expr_104.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_103.unit_num, _bundle_literal_expr_104
+                        connect _bundle_literal_expr_103.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_21: Ty57
+                        connect _cast_bundle_to_bits_expr_21.unit_num, _bundle_literal_expr_103.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_21.unit_out_reg, _bundle_literal_expr_103.unit_out_reg.value
+                        wire _cast_to_bits_expr_29: UInt<6>
+                        connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num)
+                        when eq(_cast_to_bits_expr_29, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_105: Ty25
+                        wire _bundle_literal_expr_106: Ty23
+                        connect _bundle_literal_expr_106.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_105.unit_num, _bundle_literal_expr_106
+                        connect _bundle_literal_expr_105.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_22: Ty57
+                        connect _cast_bundle_to_bits_expr_22.unit_num, _bundle_literal_expr_105.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_22.unit_out_reg, _bundle_literal_expr_105.unit_out_reg.value
+                        wire _cast_to_bits_expr_30: UInt<6>
+                        connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_22.unit_out_reg, _cast_bundle_to_bits_expr_22.unit_num)
+                        when eq(_cast_to_bits_expr_30, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_107: Ty25
+                        wire _bundle_literal_expr_108: Ty23
+                        connect _bundle_literal_expr_108.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_107.unit_num, _bundle_literal_expr_108
+                        connect _bundle_literal_expr_107.unit_out_reg, _match_arm_value_60.which
+                        wire _cast_bundle_to_bits_expr_23: Ty57
+                        connect _cast_bundle_to_bits_expr_23.unit_num, _bundle_literal_expr_107.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_23.unit_out_reg, _bundle_literal_expr_107.unit_out_reg.value
+                        wire _cast_to_bits_expr_31: UInt<6>
+                        connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_23.unit_out_reg, _cast_bundle_to_bits_expr_23.unit_num)
+                        when eq(_cast_to_bits_expr_31, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_1: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_109: Ty69
+                        connect _bundle_literal_expr_109.which, dest_reg_3
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_109): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_1, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_61):
+                                connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_62):
+                        wire _bundle_literal_expr_110: Ty69
+                        connect _bundle_literal_expr_110.which, dest_reg_3
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_110): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_63):
+                                connect cmp_eq_1, eq(_match_arm_value_62.which.value, _match_arm_value_63.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[1], cmp_eq_1 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_64):
+                        when eq(dest_reg_3.value, _match_arm_value_64.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[1], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_2: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_2, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_2, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_2: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_65):
+                        wire dest_reg_4: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_65.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_66):
+                                connect dest_reg_4, _match_arm_value_66.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_67):
+                                connect dest_reg_4, _match_arm_value_67.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_68):
+                                connect dest_reg_4, _match_arm_value_68.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_3.value, dest_reg_4.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[1], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_52.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[1]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_69):
+                        wire _bundle_literal_expr_111: Ty87
+                        connect _bundle_literal_expr_111.state, _match_arm_value_69
+                        connect _bundle_literal_expr_111.mop, _match_arm_value_52.mop
+                        connect _bundle_literal_expr_111.src_ready_flags, _match_arm_value_52.src_ready_flags
+                        connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_111) @[unit_base.rs 435:17]
+        wire _array_literal_expr_38: UInt<1>[3]
+        connect _array_literal_expr_38[0], UInt<1>(0h0)
+        connect _array_literal_expr_38[1], UInt<1>(0h0)
+        connect _array_literal_expr_38[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[2], _array_literal_expr_38 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[2], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[2], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[2], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[2]: @[unit_base.rs 343:9]
             HdlNone:
-                match input_index: @[unit_base.rs 122:16]
+                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_70):
+                wire dest_reg_5: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_70.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_71):
+                        connect dest_reg_5, _match_arm_value_71.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_72):
+                        connect dest_reg_5, _match_arm_value_72.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_73):
+                        connect dest_reg_5, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_2: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_39: UInt<6>[3]
+                wire _bundle_literal_expr_112: Ty25
+                wire _bundle_literal_expr_113: Ty23
+                connect _bundle_literal_expr_113.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_112.unit_num, _bundle_literal_expr_113
+                wire _bundle_literal_expr_114: Ty24
+                connect _bundle_literal_expr_114.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_112.unit_out_reg, _bundle_literal_expr_114
+                wire _cast_bundle_to_bits_expr_24: Ty57
+                connect _cast_bundle_to_bits_expr_24.unit_num, _bundle_literal_expr_112.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_24.unit_out_reg, _bundle_literal_expr_112.unit_out_reg.value
+                wire _cast_to_bits_expr_32: UInt<6>
+                connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_24.unit_out_reg, _cast_bundle_to_bits_expr_24.unit_num)
+                connect _array_literal_expr_39[0], _cast_to_bits_expr_32
+                wire _bundle_literal_expr_115: Ty25
+                wire _bundle_literal_expr_116: Ty23
+                connect _bundle_literal_expr_116.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_115.unit_num, _bundle_literal_expr_116
+                wire _bundle_literal_expr_117: Ty24
+                connect _bundle_literal_expr_117.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_115.unit_out_reg, _bundle_literal_expr_117
+                wire _cast_bundle_to_bits_expr_25: Ty57
+                connect _cast_bundle_to_bits_expr_25.unit_num, _bundle_literal_expr_115.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_25.unit_out_reg, _bundle_literal_expr_115.unit_out_reg.value
+                wire _cast_to_bits_expr_33: UInt<6>
+                connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_25.unit_out_reg, _cast_bundle_to_bits_expr_25.unit_num)
+                connect _array_literal_expr_39[1], _cast_to_bits_expr_33
+                wire _bundle_literal_expr_118: Ty25
+                wire _bundle_literal_expr_119: Ty23
+                connect _bundle_literal_expr_119.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_118.unit_num, _bundle_literal_expr_119
+                wire _bundle_literal_expr_120: Ty24
+                connect _bundle_literal_expr_120.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_118.unit_out_reg, _bundle_literal_expr_120
+                wire _cast_bundle_to_bits_expr_26: Ty57
+                connect _cast_bundle_to_bits_expr_26.unit_num, _bundle_literal_expr_118.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_26.unit_out_reg, _bundle_literal_expr_118.unit_out_reg.value
+                wire _cast_to_bits_expr_34: UInt<6>
+                connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_26.unit_out_reg, _cast_bundle_to_bits_expr_26.unit_num)
+                connect _array_literal_expr_39[2], _cast_to_bits_expr_34
+                connect in_flight_op_src_regs_2, _array_literal_expr_39 @[unit_base.rs 356:13]
+                match _match_arm_value_70.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_74):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_74.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_74.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[2], _match_arm_value_74.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_75):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_75.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_75.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_76):
+                        connect in_flight_op_src_regs_2[0], _match_arm_value_76.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_2[1], _match_arm_value_76.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[2], _match_arm_value_70.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_61):
-                        connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13]
-                        when eq(_match_arm_value_61, UInt<64>(0h7)): @[unit_base.rs 125:13]
-                            connect in_flight_ops[7], input_in_flight_op @[unit_base.rs 126:17]
-            HdlSome(_match_arm_value_62):
-                wire firing_data_8: Ty70 @[ready_valid.rs 30:27]
-                connect firing_data_8, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9]
-                when cancel_input.ready: @[ready_valid.rs 33:9]
-                    connect firing_data_8, cancel_input.data @[ready_valid.rs 34:13]
-                match firing_data_8: @[unit_base.rs 109:13]
+                    HdlSome(_match_arm_value_77):
+                        wire _bundle_literal_expr_121: Ty25
+                        wire _bundle_literal_expr_122: Ty23
+                        connect _bundle_literal_expr_122.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_121.unit_num, _bundle_literal_expr_122
+                        connect _bundle_literal_expr_121.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_27: Ty57
+                        connect _cast_bundle_to_bits_expr_27.unit_num, _bundle_literal_expr_121.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_27.unit_out_reg, _bundle_literal_expr_121.unit_out_reg.value
+                        wire _cast_to_bits_expr_35: UInt<6>
+                        connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_27.unit_out_reg, _cast_bundle_to_bits_expr_27.unit_num)
+                        when eq(_cast_to_bits_expr_35, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_123: Ty25
+                        wire _bundle_literal_expr_124: Ty23
+                        connect _bundle_literal_expr_124.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_123.unit_num, _bundle_literal_expr_124
+                        connect _bundle_literal_expr_123.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_28: Ty57
+                        connect _cast_bundle_to_bits_expr_28.unit_num, _bundle_literal_expr_123.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_28.unit_out_reg, _bundle_literal_expr_123.unit_out_reg.value
+                        wire _cast_to_bits_expr_36: UInt<6>
+                        connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num)
+                        when eq(_cast_to_bits_expr_36, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_125: Ty25
+                        wire _bundle_literal_expr_126: Ty23
+                        connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126
+                        connect _bundle_literal_expr_125.unit_out_reg, _match_arm_value_77.which
+                        wire _cast_bundle_to_bits_expr_29: Ty57
+                        connect _cast_bundle_to_bits_expr_29.unit_num, _bundle_literal_expr_125.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_29.unit_out_reg, _bundle_literal_expr_125.unit_out_reg.value
+                        wire _cast_to_bits_expr_37: UInt<6>
+                        connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_29.unit_out_reg, _cast_bundle_to_bits_expr_29.unit_num)
+                        when eq(_cast_to_bits_expr_37, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_63):
-                        wire dest_reg_7: Ty24 @[instruction.rs 502:1]
-                        match _match_arm_value_62.mop: @[instruction.rs 502:1]
-                            AddSub(_match_arm_value_64):
-                                connect dest_reg_7, _match_arm_value_64.alu_common.common.dest @[instruction.rs 502:1]
-                            AddSubI(_match_arm_value_65):
-                                connect dest_reg_7, _match_arm_value_65.alu_common.common.dest @[instruction.rs 502:1]
-                            Logical(_match_arm_value_66):
-                                connect dest_reg_7, _match_arm_value_66.alu_common.common.dest @[instruction.rs 502:1]
-                        when eq(_match_arm_value_63.which.value, dest_reg_7.value): @[unit_base.rs 113:17]
-                            connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21]
+                    HdlSome(_match_arm_value_78):
+                        wire _bundle_literal_expr_127: Ty25
+                        wire _bundle_literal_expr_128: Ty23
+                        connect _bundle_literal_expr_128.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_127.unit_num, _bundle_literal_expr_128
+                        connect _bundle_literal_expr_127.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_30: Ty57
+                        connect _cast_bundle_to_bits_expr_30.unit_num, _bundle_literal_expr_127.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_30.unit_out_reg, _bundle_literal_expr_127.unit_out_reg.value
+                        wire _cast_to_bits_expr_38: UInt<6>
+                        connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_30.unit_out_reg, _cast_bundle_to_bits_expr_30.unit_num)
+                        when eq(_cast_to_bits_expr_38, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_129: Ty25
+                        wire _bundle_literal_expr_130: Ty23
+                        connect _bundle_literal_expr_130.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_129.unit_num, _bundle_literal_expr_130
+                        connect _bundle_literal_expr_129.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_31: Ty57
+                        connect _cast_bundle_to_bits_expr_31.unit_num, _bundle_literal_expr_129.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_31.unit_out_reg, _bundle_literal_expr_129.unit_out_reg.value
+                        wire _cast_to_bits_expr_39: UInt<6>
+                        connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_31.unit_out_reg, _cast_bundle_to_bits_expr_31.unit_num)
+                        when eq(_cast_to_bits_expr_39, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_131: Ty25
+                        wire _bundle_literal_expr_132: Ty23
+                        connect _bundle_literal_expr_132.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_131.unit_num, _bundle_literal_expr_132
+                        connect _bundle_literal_expr_131.unit_out_reg, _match_arm_value_78.which
+                        wire _cast_bundle_to_bits_expr_32: Ty57
+                        connect _cast_bundle_to_bits_expr_32.unit_num, _bundle_literal_expr_131.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_32.unit_out_reg, _bundle_literal_expr_131.unit_out_reg.value
+                        wire _cast_to_bits_expr_40: UInt<6>
+                        connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_32.unit_out_reg, _cast_bundle_to_bits_expr_32.unit_num)
+                        when eq(_cast_to_bits_expr_40, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_2: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_133: Ty69
+                        connect _bundle_literal_expr_133.which, dest_reg_5
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_133): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_2, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_79):
+                                connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_80):
+                        wire _bundle_literal_expr_134: Ty69
+                        connect _bundle_literal_expr_134.which, dest_reg_5
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_134): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_81):
+                                connect cmp_eq_2, eq(_match_arm_value_80.which.value, _match_arm_value_81.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[2], cmp_eq_2 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_82):
+                        when eq(dest_reg_5.value, _match_arm_value_82.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[2], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_3: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_3, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_3, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_3: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_83):
+                        wire dest_reg_6: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_83.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_84):
+                                connect dest_reg_6, _match_arm_value_84.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_85):
+                                connect dest_reg_6, _match_arm_value_85.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_86):
+                                connect dest_reg_6, _match_arm_value_86.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_5.value, dest_reg_6.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[2], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_70.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[2]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_87):
+                        wire _bundle_literal_expr_135: Ty87
+                        connect _bundle_literal_expr_135.state, _match_arm_value_87
+                        connect _bundle_literal_expr_135.mop, _match_arm_value_70.mop
+                        connect _bundle_literal_expr_135.src_ready_flags, _match_arm_value_70.src_ready_flags
+                        connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_135) @[unit_base.rs 435:17]
+        wire _array_literal_expr_40: UInt<1>[3]
+        connect _array_literal_expr_40[0], UInt<1>(0h0)
+        connect _array_literal_expr_40[1], UInt<1>(0h0)
+        connect _array_literal_expr_40[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[3], _array_literal_expr_40 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[3], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[3], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[3], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[3]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_88):
+                wire dest_reg_7: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_88.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_89):
+                        connect dest_reg_7, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_90):
+                        connect dest_reg_7, _match_arm_value_90.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_91):
+                        connect dest_reg_7, _match_arm_value_91.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_3: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_41: UInt<6>[3]
+                wire _bundle_literal_expr_136: Ty25
+                wire _bundle_literal_expr_137: Ty23
+                connect _bundle_literal_expr_137.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137
+                wire _bundle_literal_expr_138: Ty24
+                connect _bundle_literal_expr_138.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138
+                wire _cast_bundle_to_bits_expr_33: Ty57
+                connect _cast_bundle_to_bits_expr_33.unit_num, _bundle_literal_expr_136.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_33.unit_out_reg, _bundle_literal_expr_136.unit_out_reg.value
+                wire _cast_to_bits_expr_41: UInt<6>
+                connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_33.unit_out_reg, _cast_bundle_to_bits_expr_33.unit_num)
+                connect _array_literal_expr_41[0], _cast_to_bits_expr_41
+                wire _bundle_literal_expr_139: Ty25
+                wire _bundle_literal_expr_140: Ty23
+                connect _bundle_literal_expr_140.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_139.unit_num, _bundle_literal_expr_140
+                wire _bundle_literal_expr_141: Ty24
+                connect _bundle_literal_expr_141.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_139.unit_out_reg, _bundle_literal_expr_141
+                wire _cast_bundle_to_bits_expr_34: Ty57
+                connect _cast_bundle_to_bits_expr_34.unit_num, _bundle_literal_expr_139.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_34.unit_out_reg, _bundle_literal_expr_139.unit_out_reg.value
+                wire _cast_to_bits_expr_42: UInt<6>
+                connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_34.unit_out_reg, _cast_bundle_to_bits_expr_34.unit_num)
+                connect _array_literal_expr_41[1], _cast_to_bits_expr_42
+                wire _bundle_literal_expr_142: Ty25
+                wire _bundle_literal_expr_143: Ty23
+                connect _bundle_literal_expr_143.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_142.unit_num, _bundle_literal_expr_143
+                wire _bundle_literal_expr_144: Ty24
+                connect _bundle_literal_expr_144.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_142.unit_out_reg, _bundle_literal_expr_144
+                wire _cast_bundle_to_bits_expr_35: Ty57
+                connect _cast_bundle_to_bits_expr_35.unit_num, _bundle_literal_expr_142.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_35.unit_out_reg, _bundle_literal_expr_142.unit_out_reg.value
+                wire _cast_to_bits_expr_43: UInt<6>
+                connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num)
+                connect _array_literal_expr_41[2], _cast_to_bits_expr_43
+                connect in_flight_op_src_regs_3, _array_literal_expr_41 @[unit_base.rs 356:13]
+                match _match_arm_value_88.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_92):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_92.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_92.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[2], _match_arm_value_92.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_93):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_93.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_93.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_94):
+                        connect in_flight_op_src_regs_3[0], _match_arm_value_94.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_3[1], _match_arm_value_94.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[3], _match_arm_value_88.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_95):
+                        wire _bundle_literal_expr_145: Ty25
+                        wire _bundle_literal_expr_146: Ty23
+                        connect _bundle_literal_expr_146.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_145.unit_num, _bundle_literal_expr_146
+                        connect _bundle_literal_expr_145.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_36: Ty57
+                        connect _cast_bundle_to_bits_expr_36.unit_num, _bundle_literal_expr_145.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_36.unit_out_reg, _bundle_literal_expr_145.unit_out_reg.value
+                        wire _cast_to_bits_expr_44: UInt<6>
+                        connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_36.unit_out_reg, _cast_bundle_to_bits_expr_36.unit_num)
+                        when eq(_cast_to_bits_expr_44, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_147: Ty25
+                        wire _bundle_literal_expr_148: Ty23
+                        connect _bundle_literal_expr_148.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_147.unit_num, _bundle_literal_expr_148
+                        connect _bundle_literal_expr_147.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_37: Ty57
+                        connect _cast_bundle_to_bits_expr_37.unit_num, _bundle_literal_expr_147.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_37.unit_out_reg, _bundle_literal_expr_147.unit_out_reg.value
+                        wire _cast_to_bits_expr_45: UInt<6>
+                        connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_37.unit_out_reg, _cast_bundle_to_bits_expr_37.unit_num)
+                        when eq(_cast_to_bits_expr_45, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_149: Ty25
+                        wire _bundle_literal_expr_150: Ty23
+                        connect _bundle_literal_expr_150.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_149.unit_num, _bundle_literal_expr_150
+                        connect _bundle_literal_expr_149.unit_out_reg, _match_arm_value_95.which
+                        wire _cast_bundle_to_bits_expr_38: Ty57
+                        connect _cast_bundle_to_bits_expr_38.unit_num, _bundle_literal_expr_149.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_38.unit_out_reg, _bundle_literal_expr_149.unit_out_reg.value
+                        wire _cast_to_bits_expr_46: UInt<6>
+                        connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_38.unit_out_reg, _cast_bundle_to_bits_expr_38.unit_num)
+                        when eq(_cast_to_bits_expr_46, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_96):
+                        wire _bundle_literal_expr_151: Ty25
+                        wire _bundle_literal_expr_152: Ty23
+                        connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152
+                        connect _bundle_literal_expr_151.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_39: Ty57
+                        connect _cast_bundle_to_bits_expr_39.unit_num, _bundle_literal_expr_151.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_39.unit_out_reg, _bundle_literal_expr_151.unit_out_reg.value
+                        wire _cast_to_bits_expr_47: UInt<6>
+                        connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num)
+                        when eq(_cast_to_bits_expr_47, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_153: Ty25
+                        wire _bundle_literal_expr_154: Ty23
+                        connect _bundle_literal_expr_154.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_153.unit_num, _bundle_literal_expr_154
+                        connect _bundle_literal_expr_153.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_40: Ty57
+                        connect _cast_bundle_to_bits_expr_40.unit_num, _bundle_literal_expr_153.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_40.unit_out_reg, _bundle_literal_expr_153.unit_out_reg.value
+                        wire _cast_to_bits_expr_48: UInt<6>
+                        connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num)
+                        when eq(_cast_to_bits_expr_48, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_155: Ty25
+                        wire _bundle_literal_expr_156: Ty23
+                        connect _bundle_literal_expr_156.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_155.unit_num, _bundle_literal_expr_156
+                        connect _bundle_literal_expr_155.unit_out_reg, _match_arm_value_96.which
+                        wire _cast_bundle_to_bits_expr_41: Ty57
+                        connect _cast_bundle_to_bits_expr_41.unit_num, _bundle_literal_expr_155.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_41.unit_out_reg, _bundle_literal_expr_155.unit_out_reg.value
+                        wire _cast_to_bits_expr_49: UInt<6>
+                        connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num)
+                        when eq(_cast_to_bits_expr_49, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_3: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_157: Ty69
+                        connect _bundle_literal_expr_157.which, dest_reg_7
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_157): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_3, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_97):
+                                connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_98):
+                        wire _bundle_literal_expr_158: Ty69
+                        connect _bundle_literal_expr_158.which, dest_reg_7
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_158): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_99):
+                                connect cmp_eq_3, eq(_match_arm_value_98.which.value, _match_arm_value_99.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[3], cmp_eq_3 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_100):
+                        when eq(dest_reg_7.value, _match_arm_value_100.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[3], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_4: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_4, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_4, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_4: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_101):
+                        wire dest_reg_8: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_101.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_102):
+                                connect dest_reg_8, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_103):
+                                connect dest_reg_8, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_104):
+                                connect dest_reg_8, _match_arm_value_104.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_7.value, dest_reg_8.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[3], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_88.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[3]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_105):
+                        wire _bundle_literal_expr_159: Ty87
+                        connect _bundle_literal_expr_159.state, _match_arm_value_105
+                        connect _bundle_literal_expr_159.mop, _match_arm_value_88.mop
+                        connect _bundle_literal_expr_159.src_ready_flags, _match_arm_value_88.src_ready_flags
+                        connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_159) @[unit_base.rs 435:17]
+        wire _array_literal_expr_42: UInt<1>[3]
+        connect _array_literal_expr_42[0], UInt<1>(0h0)
+        connect _array_literal_expr_42[1], UInt<1>(0h0)
+        connect _array_literal_expr_42[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[4], _array_literal_expr_42 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[4], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[4], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[4], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[4]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_106):
+                wire dest_reg_9: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_106.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_107):
+                        connect dest_reg_9, _match_arm_value_107.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_108):
+                        connect dest_reg_9, _match_arm_value_108.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_109):
+                        connect dest_reg_9, _match_arm_value_109.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_4: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_43: UInt<6>[3]
+                wire _bundle_literal_expr_160: Ty25
+                wire _bundle_literal_expr_161: Ty23
+                connect _bundle_literal_expr_161.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_160.unit_num, _bundle_literal_expr_161
+                wire _bundle_literal_expr_162: Ty24
+                connect _bundle_literal_expr_162.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_160.unit_out_reg, _bundle_literal_expr_162
+                wire _cast_bundle_to_bits_expr_42: Ty57
+                connect _cast_bundle_to_bits_expr_42.unit_num, _bundle_literal_expr_160.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_42.unit_out_reg, _bundle_literal_expr_160.unit_out_reg.value
+                wire _cast_to_bits_expr_50: UInt<6>
+                connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num)
+                connect _array_literal_expr_43[0], _cast_to_bits_expr_50
+                wire _bundle_literal_expr_163: Ty25
+                wire _bundle_literal_expr_164: Ty23
+                connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164
+                wire _bundle_literal_expr_165: Ty24
+                connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165
+                wire _cast_bundle_to_bits_expr_43: Ty57
+                connect _cast_bundle_to_bits_expr_43.unit_num, _bundle_literal_expr_163.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_43.unit_out_reg, _bundle_literal_expr_163.unit_out_reg.value
+                wire _cast_to_bits_expr_51: UInt<6>
+                connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num)
+                connect _array_literal_expr_43[1], _cast_to_bits_expr_51
+                wire _bundle_literal_expr_166: Ty25
+                wire _bundle_literal_expr_167: Ty23
+                connect _bundle_literal_expr_167.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_166.unit_num, _bundle_literal_expr_167
+                wire _bundle_literal_expr_168: Ty24
+                connect _bundle_literal_expr_168.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_166.unit_out_reg, _bundle_literal_expr_168
+                wire _cast_bundle_to_bits_expr_44: Ty57
+                connect _cast_bundle_to_bits_expr_44.unit_num, _bundle_literal_expr_166.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_44.unit_out_reg, _bundle_literal_expr_166.unit_out_reg.value
+                wire _cast_to_bits_expr_52: UInt<6>
+                connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num)
+                connect _array_literal_expr_43[2], _cast_to_bits_expr_52
+                connect in_flight_op_src_regs_4, _array_literal_expr_43 @[unit_base.rs 356:13]
+                match _match_arm_value_106.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_110):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_110.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_110.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[2], _match_arm_value_110.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_111):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_111.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_111.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_112):
+                        connect in_flight_op_src_regs_4[0], _match_arm_value_112.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_4[1], _match_arm_value_112.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[4], _match_arm_value_106.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_113):
+                        wire _bundle_literal_expr_169: Ty25
+                        wire _bundle_literal_expr_170: Ty23
+                        connect _bundle_literal_expr_170.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_169.unit_num, _bundle_literal_expr_170
+                        connect _bundle_literal_expr_169.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_45: Ty57
+                        connect _cast_bundle_to_bits_expr_45.unit_num, _bundle_literal_expr_169.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_45.unit_out_reg, _bundle_literal_expr_169.unit_out_reg.value
+                        wire _cast_to_bits_expr_53: UInt<6>
+                        connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num)
+                        when eq(_cast_to_bits_expr_53, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_171: Ty25
+                        wire _bundle_literal_expr_172: Ty23
+                        connect _bundle_literal_expr_172.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_171.unit_num, _bundle_literal_expr_172
+                        connect _bundle_literal_expr_171.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_46: Ty57
+                        connect _cast_bundle_to_bits_expr_46.unit_num, _bundle_literal_expr_171.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_46.unit_out_reg, _bundle_literal_expr_171.unit_out_reg.value
+                        wire _cast_to_bits_expr_54: UInt<6>
+                        connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num)
+                        when eq(_cast_to_bits_expr_54, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_173: Ty25
+                        wire _bundle_literal_expr_174: Ty23
+                        connect _bundle_literal_expr_174.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_173.unit_num, _bundle_literal_expr_174
+                        connect _bundle_literal_expr_173.unit_out_reg, _match_arm_value_113.which
+                        wire _cast_bundle_to_bits_expr_47: Ty57
+                        connect _cast_bundle_to_bits_expr_47.unit_num, _bundle_literal_expr_173.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_47.unit_out_reg, _bundle_literal_expr_173.unit_out_reg.value
+                        wire _cast_to_bits_expr_55: UInt<6>
+                        connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num)
+                        when eq(_cast_to_bits_expr_55, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_114):
+                        wire _bundle_literal_expr_175: Ty25
+                        wire _bundle_literal_expr_176: Ty23
+                        connect _bundle_literal_expr_176.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_175.unit_num, _bundle_literal_expr_176
+                        connect _bundle_literal_expr_175.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_48: Ty57
+                        connect _cast_bundle_to_bits_expr_48.unit_num, _bundle_literal_expr_175.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_48.unit_out_reg, _bundle_literal_expr_175.unit_out_reg.value
+                        wire _cast_to_bits_expr_56: UInt<6>
+                        connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_48.unit_out_reg, _cast_bundle_to_bits_expr_48.unit_num)
+                        when eq(_cast_to_bits_expr_56, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_177: Ty25
+                        wire _bundle_literal_expr_178: Ty23
+                        connect _bundle_literal_expr_178.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_177.unit_num, _bundle_literal_expr_178
+                        connect _bundle_literal_expr_177.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_49: Ty57
+                        connect _cast_bundle_to_bits_expr_49.unit_num, _bundle_literal_expr_177.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_49.unit_out_reg, _bundle_literal_expr_177.unit_out_reg.value
+                        wire _cast_to_bits_expr_57: UInt<6>
+                        connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_49.unit_out_reg, _cast_bundle_to_bits_expr_49.unit_num)
+                        when eq(_cast_to_bits_expr_57, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_179: Ty25
+                        wire _bundle_literal_expr_180: Ty23
+                        connect _bundle_literal_expr_180.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_179.unit_num, _bundle_literal_expr_180
+                        connect _bundle_literal_expr_179.unit_out_reg, _match_arm_value_114.which
+                        wire _cast_bundle_to_bits_expr_50: Ty57
+                        connect _cast_bundle_to_bits_expr_50.unit_num, _bundle_literal_expr_179.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_50.unit_out_reg, _bundle_literal_expr_179.unit_out_reg.value
+                        wire _cast_to_bits_expr_58: UInt<6>
+                        connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num)
+                        when eq(_cast_to_bits_expr_58, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_4: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_181: Ty69
+                        connect _bundle_literal_expr_181.which, dest_reg_9
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_181): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_4, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_115):
+                                connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_116):
+                        wire _bundle_literal_expr_182: Ty69
+                        connect _bundle_literal_expr_182.which, dest_reg_9
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_182): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_117):
+                                connect cmp_eq_4, eq(_match_arm_value_116.which.value, _match_arm_value_117.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[4], cmp_eq_4 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_118):
+                        when eq(dest_reg_9.value, _match_arm_value_118.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[4], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_5: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_5, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_5, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_5: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_119):
+                        wire dest_reg_10: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_119.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_120):
+                                connect dest_reg_10, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_121):
+                                connect dest_reg_10, _match_arm_value_121.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_122):
+                                connect dest_reg_10, _match_arm_value_122.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_9.value, dest_reg_10.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[4], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_106.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[4]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_123):
+                        wire _bundle_literal_expr_183: Ty87
+                        connect _bundle_literal_expr_183.state, _match_arm_value_123
+                        connect _bundle_literal_expr_183.mop, _match_arm_value_106.mop
+                        connect _bundle_literal_expr_183.src_ready_flags, _match_arm_value_106.src_ready_flags
+                        connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_183) @[unit_base.rs 435:17]
+        wire _array_literal_expr_44: UInt<1>[3]
+        connect _array_literal_expr_44[0], UInt<1>(0h0)
+        connect _array_literal_expr_44[1], UInt<1>(0h0)
+        connect _array_literal_expr_44[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[5], _array_literal_expr_44 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[5], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[5], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[5], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[5]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_124):
+                wire dest_reg_11: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_124.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_125):
+                        connect dest_reg_11, _match_arm_value_125.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_126):
+                        connect dest_reg_11, _match_arm_value_126.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_127):
+                        connect dest_reg_11, _match_arm_value_127.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_5: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_45: UInt<6>[3]
+                wire _bundle_literal_expr_184: Ty25
+                wire _bundle_literal_expr_185: Ty23
+                connect _bundle_literal_expr_185.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_184.unit_num, _bundle_literal_expr_185
+                wire _bundle_literal_expr_186: Ty24
+                connect _bundle_literal_expr_186.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_184.unit_out_reg, _bundle_literal_expr_186
+                wire _cast_bundle_to_bits_expr_51: Ty57
+                connect _cast_bundle_to_bits_expr_51.unit_num, _bundle_literal_expr_184.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_51.unit_out_reg, _bundle_literal_expr_184.unit_out_reg.value
+                wire _cast_to_bits_expr_59: UInt<6>
+                connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num)
+                connect _array_literal_expr_45[0], _cast_to_bits_expr_59
+                wire _bundle_literal_expr_187: Ty25
+                wire _bundle_literal_expr_188: Ty23
+                connect _bundle_literal_expr_188.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_187.unit_num, _bundle_literal_expr_188
+                wire _bundle_literal_expr_189: Ty24
+                connect _bundle_literal_expr_189.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_187.unit_out_reg, _bundle_literal_expr_189
+                wire _cast_bundle_to_bits_expr_52: Ty57
+                connect _cast_bundle_to_bits_expr_52.unit_num, _bundle_literal_expr_187.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_52.unit_out_reg, _bundle_literal_expr_187.unit_out_reg.value
+                wire _cast_to_bits_expr_60: UInt<6>
+                connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num)
+                connect _array_literal_expr_45[1], _cast_to_bits_expr_60
+                wire _bundle_literal_expr_190: Ty25
+                wire _bundle_literal_expr_191: Ty23
+                connect _bundle_literal_expr_191.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_190.unit_num, _bundle_literal_expr_191
+                wire _bundle_literal_expr_192: Ty24
+                connect _bundle_literal_expr_192.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_190.unit_out_reg, _bundle_literal_expr_192
+                wire _cast_bundle_to_bits_expr_53: Ty57
+                connect _cast_bundle_to_bits_expr_53.unit_num, _bundle_literal_expr_190.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_53.unit_out_reg, _bundle_literal_expr_190.unit_out_reg.value
+                wire _cast_to_bits_expr_61: UInt<6>
+                connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num)
+                connect _array_literal_expr_45[2], _cast_to_bits_expr_61
+                connect in_flight_op_src_regs_5, _array_literal_expr_45 @[unit_base.rs 356:13]
+                match _match_arm_value_124.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_128):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_128.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_128.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[2], _match_arm_value_128.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_129):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_129.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_129.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_130):
+                        connect in_flight_op_src_regs_5[0], _match_arm_value_130.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_5[1], _match_arm_value_130.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[5], _match_arm_value_124.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_131):
+                        wire _bundle_literal_expr_193: Ty25
+                        wire _bundle_literal_expr_194: Ty23
+                        connect _bundle_literal_expr_194.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_193.unit_num, _bundle_literal_expr_194
+                        connect _bundle_literal_expr_193.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_54: Ty57
+                        connect _cast_bundle_to_bits_expr_54.unit_num, _bundle_literal_expr_193.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_54.unit_out_reg, _bundle_literal_expr_193.unit_out_reg.value
+                        wire _cast_to_bits_expr_62: UInt<6>
+                        connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_54.unit_out_reg, _cast_bundle_to_bits_expr_54.unit_num)
+                        when eq(_cast_to_bits_expr_62, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_195: Ty25
+                        wire _bundle_literal_expr_196: Ty23
+                        connect _bundle_literal_expr_196.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_195.unit_num, _bundle_literal_expr_196
+                        connect _bundle_literal_expr_195.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_55: Ty57
+                        connect _cast_bundle_to_bits_expr_55.unit_num, _bundle_literal_expr_195.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_55.unit_out_reg, _bundle_literal_expr_195.unit_out_reg.value
+                        wire _cast_to_bits_expr_63: UInt<6>
+                        connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_55.unit_out_reg, _cast_bundle_to_bits_expr_55.unit_num)
+                        when eq(_cast_to_bits_expr_63, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_197: Ty25
+                        wire _bundle_literal_expr_198: Ty23
+                        connect _bundle_literal_expr_198.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_197.unit_num, _bundle_literal_expr_198
+                        connect _bundle_literal_expr_197.unit_out_reg, _match_arm_value_131.which
+                        wire _cast_bundle_to_bits_expr_56: Ty57
+                        connect _cast_bundle_to_bits_expr_56.unit_num, _bundle_literal_expr_197.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_56.unit_out_reg, _bundle_literal_expr_197.unit_out_reg.value
+                        wire _cast_to_bits_expr_64: UInt<6>
+                        connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_56.unit_out_reg, _cast_bundle_to_bits_expr_56.unit_num)
+                        when eq(_cast_to_bits_expr_64, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_132):
+                        wire _bundle_literal_expr_199: Ty25
+                        wire _bundle_literal_expr_200: Ty23
+                        connect _bundle_literal_expr_200.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_199.unit_num, _bundle_literal_expr_200
+                        connect _bundle_literal_expr_199.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_57: Ty57
+                        connect _cast_bundle_to_bits_expr_57.unit_num, _bundle_literal_expr_199.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_57.unit_out_reg, _bundle_literal_expr_199.unit_out_reg.value
+                        wire _cast_to_bits_expr_65: UInt<6>
+                        connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num)
+                        when eq(_cast_to_bits_expr_65, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_201: Ty25
+                        wire _bundle_literal_expr_202: Ty23
+                        connect _bundle_literal_expr_202.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_201.unit_num, _bundle_literal_expr_202
+                        connect _bundle_literal_expr_201.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_58: Ty57
+                        connect _cast_bundle_to_bits_expr_58.unit_num, _bundle_literal_expr_201.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_58.unit_out_reg, _bundle_literal_expr_201.unit_out_reg.value
+                        wire _cast_to_bits_expr_66: UInt<6>
+                        connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num)
+                        when eq(_cast_to_bits_expr_66, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_203: Ty25
+                        wire _bundle_literal_expr_204: Ty23
+                        connect _bundle_literal_expr_204.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_203.unit_num, _bundle_literal_expr_204
+                        connect _bundle_literal_expr_203.unit_out_reg, _match_arm_value_132.which
+                        wire _cast_bundle_to_bits_expr_59: Ty57
+                        connect _cast_bundle_to_bits_expr_59.unit_num, _bundle_literal_expr_203.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_59.unit_out_reg, _bundle_literal_expr_203.unit_out_reg.value
+                        wire _cast_to_bits_expr_67: UInt<6>
+                        connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num)
+                        when eq(_cast_to_bits_expr_67, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_5: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_205: Ty69
+                        connect _bundle_literal_expr_205.which, dest_reg_11
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_205): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_5, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_133):
+                                connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_134):
+                        wire _bundle_literal_expr_206: Ty69
+                        connect _bundle_literal_expr_206.which, dest_reg_11
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_206): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_135):
+                                connect cmp_eq_5, eq(_match_arm_value_134.which.value, _match_arm_value_135.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[5], cmp_eq_5 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_136):
+                        when eq(dest_reg_11.value, _match_arm_value_136.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[5], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_6: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_6, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_6, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_6: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_137):
+                        wire dest_reg_12: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_137.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_138):
+                                connect dest_reg_12, _match_arm_value_138.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_139):
+                                connect dest_reg_12, _match_arm_value_139.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_140):
+                                connect dest_reg_12, _match_arm_value_140.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_11.value, dest_reg_12.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[5], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_124.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[5]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_141):
+                        wire _bundle_literal_expr_207: Ty87
+                        connect _bundle_literal_expr_207.state, _match_arm_value_141
+                        connect _bundle_literal_expr_207.mop, _match_arm_value_124.mop
+                        connect _bundle_literal_expr_207.src_ready_flags, _match_arm_value_124.src_ready_flags
+                        connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_207) @[unit_base.rs 435:17]
+        wire _array_literal_expr_46: UInt<1>[3]
+        connect _array_literal_expr_46[0], UInt<1>(0h0)
+        connect _array_literal_expr_46[1], UInt<1>(0h0)
+        connect _array_literal_expr_46[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[6], _array_literal_expr_46 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[6], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[6], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[6], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[6]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_142):
+                wire dest_reg_13: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_142.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_143):
+                        connect dest_reg_13, _match_arm_value_143.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_144):
+                        connect dest_reg_13, _match_arm_value_144.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_145):
+                        connect dest_reg_13, _match_arm_value_145.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_6: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_47: UInt<6>[3]
+                wire _bundle_literal_expr_208: Ty25
+                wire _bundle_literal_expr_209: Ty23
+                connect _bundle_literal_expr_209.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_208.unit_num, _bundle_literal_expr_209
+                wire _bundle_literal_expr_210: Ty24
+                connect _bundle_literal_expr_210.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_208.unit_out_reg, _bundle_literal_expr_210
+                wire _cast_bundle_to_bits_expr_60: Ty57
+                connect _cast_bundle_to_bits_expr_60.unit_num, _bundle_literal_expr_208.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_60.unit_out_reg, _bundle_literal_expr_208.unit_out_reg.value
+                wire _cast_to_bits_expr_68: UInt<6>
+                connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num)
+                connect _array_literal_expr_47[0], _cast_to_bits_expr_68
+                wire _bundle_literal_expr_211: Ty25
+                wire _bundle_literal_expr_212: Ty23
+                connect _bundle_literal_expr_212.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_211.unit_num, _bundle_literal_expr_212
+                wire _bundle_literal_expr_213: Ty24
+                connect _bundle_literal_expr_213.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_211.unit_out_reg, _bundle_literal_expr_213
+                wire _cast_bundle_to_bits_expr_61: Ty57
+                connect _cast_bundle_to_bits_expr_61.unit_num, _bundle_literal_expr_211.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_61.unit_out_reg, _bundle_literal_expr_211.unit_out_reg.value
+                wire _cast_to_bits_expr_69: UInt<6>
+                connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_61.unit_out_reg, _cast_bundle_to_bits_expr_61.unit_num)
+                connect _array_literal_expr_47[1], _cast_to_bits_expr_69
+                wire _bundle_literal_expr_214: Ty25
+                wire _bundle_literal_expr_215: Ty23
+                connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215
+                wire _bundle_literal_expr_216: Ty24
+                connect _bundle_literal_expr_216.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216
+                wire _cast_bundle_to_bits_expr_62: Ty57
+                connect _cast_bundle_to_bits_expr_62.unit_num, _bundle_literal_expr_214.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_62.unit_out_reg, _bundle_literal_expr_214.unit_out_reg.value
+                wire _cast_to_bits_expr_70: UInt<6>
+                connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_62.unit_out_reg, _cast_bundle_to_bits_expr_62.unit_num)
+                connect _array_literal_expr_47[2], _cast_to_bits_expr_70
+                connect in_flight_op_src_regs_6, _array_literal_expr_47 @[unit_base.rs 356:13]
+                match _match_arm_value_142.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_146):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_146.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_146.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[2], _match_arm_value_146.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_147):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_147.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_147.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_148):
+                        connect in_flight_op_src_regs_6[0], _match_arm_value_148.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_6[1], _match_arm_value_148.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[6], _match_arm_value_142.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_149):
+                        wire _bundle_literal_expr_217: Ty25
+                        wire _bundle_literal_expr_218: Ty23
+                        connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218
+                        connect _bundle_literal_expr_217.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_63: Ty57
+                        connect _cast_bundle_to_bits_expr_63.unit_num, _bundle_literal_expr_217.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_63.unit_out_reg, _bundle_literal_expr_217.unit_out_reg.value
+                        wire _cast_to_bits_expr_71: UInt<6>
+                        connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_63.unit_out_reg, _cast_bundle_to_bits_expr_63.unit_num)
+                        when eq(_cast_to_bits_expr_71, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_219: Ty25
+                        wire _bundle_literal_expr_220: Ty23
+                        connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220
+                        connect _bundle_literal_expr_219.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_64: Ty57
+                        connect _cast_bundle_to_bits_expr_64.unit_num, _bundle_literal_expr_219.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_64.unit_out_reg, _bundle_literal_expr_219.unit_out_reg.value
+                        wire _cast_to_bits_expr_72: UInt<6>
+                        connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_64.unit_out_reg, _cast_bundle_to_bits_expr_64.unit_num)
+                        when eq(_cast_to_bits_expr_72, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_221: Ty25
+                        wire _bundle_literal_expr_222: Ty23
+                        connect _bundle_literal_expr_222.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_221.unit_num, _bundle_literal_expr_222
+                        connect _bundle_literal_expr_221.unit_out_reg, _match_arm_value_149.which
+                        wire _cast_bundle_to_bits_expr_65: Ty57
+                        connect _cast_bundle_to_bits_expr_65.unit_num, _bundle_literal_expr_221.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_65.unit_out_reg, _bundle_literal_expr_221.unit_out_reg.value
+                        wire _cast_to_bits_expr_73: UInt<6>
+                        connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_65.unit_out_reg, _cast_bundle_to_bits_expr_65.unit_num)
+                        when eq(_cast_to_bits_expr_73, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_150):
+                        wire _bundle_literal_expr_223: Ty25
+                        wire _bundle_literal_expr_224: Ty23
+                        connect _bundle_literal_expr_224.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_223.unit_num, _bundle_literal_expr_224
+                        connect _bundle_literal_expr_223.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_66: Ty57
+                        connect _cast_bundle_to_bits_expr_66.unit_num, _bundle_literal_expr_223.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_66.unit_out_reg, _bundle_literal_expr_223.unit_out_reg.value
+                        wire _cast_to_bits_expr_74: UInt<6>
+                        connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_66.unit_out_reg, _cast_bundle_to_bits_expr_66.unit_num)
+                        when eq(_cast_to_bits_expr_74, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_225: Ty25
+                        wire _bundle_literal_expr_226: Ty23
+                        connect _bundle_literal_expr_226.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_225.unit_num, _bundle_literal_expr_226
+                        connect _bundle_literal_expr_225.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_67: Ty57
+                        connect _cast_bundle_to_bits_expr_67.unit_num, _bundle_literal_expr_225.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_67.unit_out_reg, _bundle_literal_expr_225.unit_out_reg.value
+                        wire _cast_to_bits_expr_75: UInt<6>
+                        connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num)
+                        when eq(_cast_to_bits_expr_75, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_227: Ty25
+                        wire _bundle_literal_expr_228: Ty23
+                        connect _bundle_literal_expr_228.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_227.unit_num, _bundle_literal_expr_228
+                        connect _bundle_literal_expr_227.unit_out_reg, _match_arm_value_150.which
+                        wire _cast_bundle_to_bits_expr_68: Ty57
+                        connect _cast_bundle_to_bits_expr_68.unit_num, _bundle_literal_expr_227.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_68.unit_out_reg, _bundle_literal_expr_227.unit_out_reg.value
+                        wire _cast_to_bits_expr_76: UInt<6>
+                        connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_68.unit_out_reg, _cast_bundle_to_bits_expr_68.unit_num)
+                        when eq(_cast_to_bits_expr_76, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_6: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_229: Ty69
+                        connect _bundle_literal_expr_229.which, dest_reg_13
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_229): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_6, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_151):
+                                connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_152):
+                        wire _bundle_literal_expr_230: Ty69
+                        connect _bundle_literal_expr_230.which, dest_reg_13
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_230): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_153):
+                                connect cmp_eq_6, eq(_match_arm_value_152.which.value, _match_arm_value_153.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[6], cmp_eq_6 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_154):
+                        when eq(dest_reg_13.value, _match_arm_value_154.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[6], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_7: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_7, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_7, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_7: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_155):
+                        wire dest_reg_14: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_155.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_156):
+                                connect dest_reg_14, _match_arm_value_156.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_157):
+                                connect dest_reg_14, _match_arm_value_157.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_158):
+                                connect dest_reg_14, _match_arm_value_158.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_13.value, dest_reg_14.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[6], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_142.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[6]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_159):
+                        wire _bundle_literal_expr_231: Ty87
+                        connect _bundle_literal_expr_231.state, _match_arm_value_159
+                        connect _bundle_literal_expr_231.mop, _match_arm_value_142.mop
+                        connect _bundle_literal_expr_231.src_ready_flags, _match_arm_value_142.src_ready_flags
+                        connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_231) @[unit_base.rs 435:17]
+        wire _array_literal_expr_48: UInt<1>[3]
+        connect _array_literal_expr_48[0], UInt<1>(0h0)
+        connect _array_literal_expr_48[1], UInt<1>(0h0)
+        connect _array_literal_expr_48[2], UInt<1>(0h0)
+        connect in_flight_op_next_src_ready_flags[7], _array_literal_expr_48 @[unit_base.rs 335:9]
+        connect in_flight_op_canceling[7], UInt<1>(0h0) @[unit_base.rs 339:9]
+        connect in_flight_op_execute_starting[7], UInt<1>(0h0) @[unit_base.rs 340:9]
+        connect in_flight_op_execute_ending[7], UInt<1>(0h0) @[unit_base.rs 341:9]
+        match in_flight_ops[7]: @[unit_base.rs 343:9]
+            HdlNone:
+                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13]
+            HdlSome(_match_arm_value_160):
+                wire dest_reg_15: Ty24 @[instruction.rs 538:1]
+                match _match_arm_value_160.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_161):
+                        connect dest_reg_15, _match_arm_value_161.alu_common.common.dest @[instruction.rs 538:1]
+                    AddSubI(_match_arm_value_162):
+                        connect dest_reg_15, _match_arm_value_162.alu_common.common.dest @[instruction.rs 538:1]
+                    Logical(_match_arm_value_163):
+                        connect dest_reg_15, _match_arm_value_163.alu_common.common.dest @[instruction.rs 538:1]
+                wire in_flight_op_src_regs_7: UInt<6>[3] @[unit_base.rs 353:17]
+                wire _array_literal_expr_49: UInt<6>[3]
+                wire _bundle_literal_expr_232: Ty25
+                wire _bundle_literal_expr_233: Ty23
+                connect _bundle_literal_expr_233.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_232.unit_num, _bundle_literal_expr_233
+                wire _bundle_literal_expr_234: Ty24
+                connect _bundle_literal_expr_234.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_232.unit_out_reg, _bundle_literal_expr_234
+                wire _cast_bundle_to_bits_expr_69: Ty57
+                connect _cast_bundle_to_bits_expr_69.unit_num, _bundle_literal_expr_232.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_69.unit_out_reg, _bundle_literal_expr_232.unit_out_reg.value
+                wire _cast_to_bits_expr_77: UInt<6>
+                connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_69.unit_out_reg, _cast_bundle_to_bits_expr_69.unit_num)
+                connect _array_literal_expr_49[0], _cast_to_bits_expr_77
+                wire _bundle_literal_expr_235: Ty25
+                wire _bundle_literal_expr_236: Ty23
+                connect _bundle_literal_expr_236.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_235.unit_num, _bundle_literal_expr_236
+                wire _bundle_literal_expr_237: Ty24
+                connect _bundle_literal_expr_237.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_235.unit_out_reg, _bundle_literal_expr_237
+                wire _cast_bundle_to_bits_expr_70: Ty57
+                connect _cast_bundle_to_bits_expr_70.unit_num, _bundle_literal_expr_235.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_70.unit_out_reg, _bundle_literal_expr_235.unit_out_reg.value
+                wire _cast_to_bits_expr_78: UInt<6>
+                connect _cast_to_bits_expr_78, cat(_cast_bundle_to_bits_expr_70.unit_out_reg, _cast_bundle_to_bits_expr_70.unit_num)
+                connect _array_literal_expr_49[1], _cast_to_bits_expr_78
+                wire _bundle_literal_expr_238: Ty25
+                wire _bundle_literal_expr_239: Ty23
+                connect _bundle_literal_expr_239.adj_value, tail(UInt<64>(0h0), 62)
+                connect _bundle_literal_expr_238.unit_num, _bundle_literal_expr_239
+                wire _bundle_literal_expr_240: Ty24
+                connect _bundle_literal_expr_240.value, tail(UInt<8>(0h0), 4)
+                connect _bundle_literal_expr_238.unit_out_reg, _bundle_literal_expr_240
+                wire _cast_bundle_to_bits_expr_71: Ty57
+                connect _cast_bundle_to_bits_expr_71.unit_num, _bundle_literal_expr_238.unit_num.adj_value
+                connect _cast_bundle_to_bits_expr_71.unit_out_reg, _bundle_literal_expr_238.unit_out_reg.value
+                wire _cast_to_bits_expr_79: UInt<6>
+                connect _cast_to_bits_expr_79, cat(_cast_bundle_to_bits_expr_71.unit_out_reg, _cast_bundle_to_bits_expr_71.unit_num)
+                connect _array_literal_expr_49[2], _cast_to_bits_expr_79
+                connect in_flight_op_src_regs_7, _array_literal_expr_49 @[unit_base.rs 356:13]
+                match _match_arm_value_160.mop: @[instruction.rs 538:1]
+                    AddSub(_match_arm_value_164):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_164.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_164.alu_common.common.src[1] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[2], _match_arm_value_164.alu_common.common.src[2] @[instruction.rs 36:13]
+                    AddSubI(_match_arm_value_165):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_165.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_165.alu_common.common.src[1] @[instruction.rs 36:13]
+                    Logical(_match_arm_value_166):
+                        connect in_flight_op_src_regs_7[0], _match_arm_value_166.alu_common.common.src[0] @[instruction.rs 36:13]
+                        connect in_flight_op_src_regs_7[1], _match_arm_value_166.alu_common.common.src[1] @[instruction.rs 36:13]
+                connect in_flight_op_next_src_ready_flags[7], _match_arm_value_160.src_ready_flags @[unit_base.rs 362:13]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_167):
+                        wire _bundle_literal_expr_241: Ty25
+                        wire _bundle_literal_expr_242: Ty23
+                        connect _bundle_literal_expr_242.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_241.unit_num, _bundle_literal_expr_242
+                        connect _bundle_literal_expr_241.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_72: Ty57
+                        connect _cast_bundle_to_bits_expr_72.unit_num, _bundle_literal_expr_241.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_72.unit_out_reg, _bundle_literal_expr_241.unit_out_reg.value
+                        wire _cast_to_bits_expr_80: UInt<6>
+                        connect _cast_to_bits_expr_80, cat(_cast_bundle_to_bits_expr_72.unit_out_reg, _cast_bundle_to_bits_expr_72.unit_num)
+                        when eq(_cast_to_bits_expr_80, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_243: Ty25
+                        wire _bundle_literal_expr_244: Ty23
+                        connect _bundle_literal_expr_244.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_243.unit_num, _bundle_literal_expr_244
+                        connect _bundle_literal_expr_243.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_73: Ty57
+                        connect _cast_bundle_to_bits_expr_73.unit_num, _bundle_literal_expr_243.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_73.unit_out_reg, _bundle_literal_expr_243.unit_out_reg.value
+                        wire _cast_to_bits_expr_81: UInt<6>
+                        connect _cast_to_bits_expr_81, cat(_cast_bundle_to_bits_expr_73.unit_out_reg, _cast_bundle_to_bits_expr_73.unit_num)
+                        when eq(_cast_to_bits_expr_81, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_245: Ty25
+                        wire _bundle_literal_expr_246: Ty23
+                        connect _bundle_literal_expr_246.adj_value, tail(UInt<64>(0h1), 62)
+                        connect _bundle_literal_expr_245.unit_num, _bundle_literal_expr_246
+                        connect _bundle_literal_expr_245.unit_out_reg, _match_arm_value_167.which
+                        wire _cast_bundle_to_bits_expr_74: Ty57
+                        connect _cast_bundle_to_bits_expr_74.unit_num, _bundle_literal_expr_245.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_74.unit_out_reg, _bundle_literal_expr_245.unit_out_reg.value
+                        wire _cast_to_bits_expr_82: UInt<6>
+                        connect _cast_to_bits_expr_82, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num)
+                        when eq(_cast_to_bits_expr_82, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_168):
+                        wire _bundle_literal_expr_247: Ty25
+                        wire _bundle_literal_expr_248: Ty23
+                        connect _bundle_literal_expr_248.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_247.unit_num, _bundle_literal_expr_248
+                        connect _bundle_literal_expr_247.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_75: Ty57
+                        connect _cast_bundle_to_bits_expr_75.unit_num, _bundle_literal_expr_247.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_75.unit_out_reg, _bundle_literal_expr_247.unit_out_reg.value
+                        wire _cast_to_bits_expr_83: UInt<6>
+                        connect _cast_to_bits_expr_83, cat(_cast_bundle_to_bits_expr_75.unit_out_reg, _cast_bundle_to_bits_expr_75.unit_num)
+                        when eq(_cast_to_bits_expr_83, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_249: Ty25
+                        wire _bundle_literal_expr_250: Ty23
+                        connect _bundle_literal_expr_250.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_249.unit_num, _bundle_literal_expr_250
+                        connect _bundle_literal_expr_249.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_76: Ty57
+                        connect _cast_bundle_to_bits_expr_76.unit_num, _bundle_literal_expr_249.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_76.unit_out_reg, _bundle_literal_expr_249.unit_out_reg.value
+                        wire _cast_to_bits_expr_84: UInt<6>
+                        connect _cast_to_bits_expr_84, cat(_cast_bundle_to_bits_expr_76.unit_out_reg, _cast_bundle_to_bits_expr_76.unit_num)
+                        when eq(_cast_to_bits_expr_84, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29]
+                        wire _bundle_literal_expr_251: Ty25
+                        wire _bundle_literal_expr_252: Ty23
+                        connect _bundle_literal_expr_252.adj_value, tail(UInt<64>(0h2), 62)
+                        connect _bundle_literal_expr_251.unit_num, _bundle_literal_expr_252
+                        connect _bundle_literal_expr_251.unit_out_reg, _match_arm_value_168.which
+                        wire _cast_bundle_to_bits_expr_77: Ty57
+                        connect _cast_bundle_to_bits_expr_77.unit_num, _bundle_literal_expr_251.unit_num.adj_value
+                        connect _cast_bundle_to_bits_expr_77.unit_out_reg, _bundle_literal_expr_251.unit_out_reg.value
+                        wire _cast_to_bits_expr_85: UInt<6>
+                        connect _cast_to_bits_expr_85, cat(_cast_bundle_to_bits_expr_77.unit_out_reg, _cast_bundle_to_bits_expr_77.unit_num)
+                        when eq(_cast_to_bits_expr_85, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25]
+                            connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29]
+                wire cmp_eq_7: UInt<1> @[enum_.rs 370:22]
+                match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9]
+                    HdlNone:
+                        wire _bundle_literal_expr_253: Ty69
+                        connect _bundle_literal_expr_253.which, dest_reg_15
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_253): @[enum_.rs 384:17]
+                            HdlNone:
+                                connect cmp_eq_7, UInt<1>(0h1) @[enum_.rs 386:32]
+                            HdlSome(_match_arm_value_169):
+                                connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 385:35]
+                    HdlSome(_match_arm_value_170):
+                        wire _bundle_literal_expr_254: Ty69
+                        connect _bundle_literal_expr_254.which, dest_reg_15
+                        match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_254): @[enum_.rs 376:17]
+                            HdlNone:
+                                connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 378:32]
+                            HdlSome(_match_arm_value_171):
+                                connect cmp_eq_7, eq(_match_arm_value_170.which.value, _match_arm_value_171.which.value) @[enum_.rs 377:37]
+                connect in_flight_op_canceling[7], cmp_eq_7 @[unit_base.rs 392:13]
+                match execute_end: @[unit_base.rs 401:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_172):
+                        when eq(dest_reg_15.value, _match_arm_value_172.unit_output.which.value): @[unit_base.rs 405:17]
+                            connect in_flight_op_execute_ending[7], UInt<1>(0h1) @[unit_base.rs 406:21]
+                wire firing_data_8: Ty81 @[ready_valid.rs 30:27]
+                connect firing_data_8, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9]
+                when execute_start.ready: @[ready_valid.rs 33:9]
+                    connect firing_data_8, execute_start.data @[ready_valid.rs 34:13]
+                match firing_data_8: @[unit_base.rs 410:13]
+                    HdlNone:
+                        skip
+                    HdlSome(_match_arm_value_173):
+                        wire dest_reg_16: Ty24 @[instruction.rs 538:1]
+                        match _match_arm_value_173.mop: @[instruction.rs 538:1]
+                            AddSub(_match_arm_value_174):
+                                connect dest_reg_16, _match_arm_value_174.alu_common.common.dest @[instruction.rs 538:1]
+                            AddSubI(_match_arm_value_175):
+                                connect dest_reg_16, _match_arm_value_175.alu_common.common.dest @[instruction.rs 538:1]
+                            Logical(_match_arm_value_176):
+                                connect dest_reg_16, _match_arm_value_176.alu_common.common.dest @[instruction.rs 538:1]
+                        when eq(dest_reg_15.value, dest_reg_16.value): @[unit_base.rs 412:17]
+                            connect in_flight_op_execute_starting[7], UInt<1>(0h1) @[unit_base.rs 413:21]
+                match _match_arm_value_160.state: @[unit_base.rs 426:13]
+                    Ready:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17]
+                    Running:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17]
+                    CanceledAndRunning:
+                        when in_flight_op_canceling[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                                when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                                else:
+                                    connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                            else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17]
+                            when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                            else:
+                                connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                        else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17]
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17]
+                        else:
+                            connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17]
+                match in_flight_op_next_state[7]: @[unit_base.rs 434:13]
+                    HdlNone:
+                        connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17]
+                    HdlSome(_match_arm_value_177):
+                        wire _bundle_literal_expr_255: Ty87
+                        connect _bundle_literal_expr_255.state, _match_arm_value_177
+                        connect _bundle_literal_expr_255.mop, _match_arm_value_160.mop
+                        connect _bundle_literal_expr_255.src_ready_flags, _match_arm_value_160.src_ready_flags
+                        connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_255) @[unit_base.rs 435:17]
 ",
     };
     // let sim_debug = format!("{sim:#?}");