diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index 587fb0b..2a0d6b5 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -509,8 +509,10 @@ common_mop_struct! { #[common] pub alu_common: AluCommonMOp, pub invert_src0: Bool, + /// * if this is `true`, use `alu_common.src[1]`'s [`PRegFlagsPowerISA::xer_ca`] as a carry-in/borrow-in + /// * else, use `alu_common.src[1]` as a normal addend + pub src1_is_carry_in: Bool, pub invert_carry_in: Bool, - pub invert_carry_out: Bool, pub add_pc: Bool, } } diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs index 4ac357f..0dc3168 100644 --- a/crates/cpu/src/reg_alloc.rs +++ b/crates/cpu/src/reg_alloc.rs @@ -6,7 +6,10 @@ use crate::{ MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, RenameTableName, UnitOutRegNum, COMMON_MOP_SRC_LEN, }, - unit::{unit_base::UnitForwardingInfo, TrapData, UnitTrait}, + unit::{ + unit_base::UnitInput, GlobalState, TrapData, UnitOutput, UnitOutputWrite, UnitResult, + UnitResultCompleted, UnitTrait, + }, util::tree_reduce::tree_reduce_with_state, }; use fayalite::{ @@ -17,7 +20,6 @@ use fayalite::{ }; use std::{ collections::{BTreeMap, VecDeque}, - marker::PhantomData, num::NonZeroUsize, }; @@ -54,6 +56,8 @@ pub fn reg_alloc(config: &CpuConfig) { #[hdl] let fetch_decode_interface: FetchDecodeInterface = m.input(FetchDecodeInterface[config.fetch_width.get()]); + #[hdl] + let global_state: GlobalState = m.input(); // TODO: propagate traps, branch mis-predictions, and special ops connect( fetch_decode_interface.fetch_decode_special_op.data, @@ -85,7 +89,8 @@ pub fn reg_alloc(config: &CpuConfig) { let selected_unit_indexes = wire(Array[HdlOption[UInt[config.unit_num_width()]]][config.fetch_width.get()]); #[hdl] - let renamed_mops = wire(Array[HdlOption[config.unit_mop_in_unit()]][config.fetch_width.get()]); + let renamed_mops = + wire(Array[HdlOption[UnitInput[config.unit_mop_in_unit()]]][config.fetch_width.get()]); #[hdl] let renamed_mops_out_reg = wire(Array[HdlOption[config.p_reg_num()]][config.fetch_width.get()]); for fetch_index in 0..config.fetch_width.get() { @@ -196,19 +201,25 @@ pub fn reg_alloc(config: &CpuConfig) { let dest_reg = MOpTrait::dest_reg(decoded_insn.mop); connect( renamed_mops[fetch_index], - HdlSome(MOpTrait::map_regs( - decoded_insn.mop, - renamed_mop_out_reg.unit_out_reg, - config.p_reg_num_width(), - &mut |src_reg, src_index| { - connect( - rename_table_read_ports[src_index].addr, - #[hdl] - MOpRegNum { value: src_reg }, - ); - rename_table_read_ports[src_index].data.cast_to_bits() + HdlSome( + #[hdl] + UnitInput::<_> { + mop: MOpTrait::map_regs( + decoded_insn.mop, + renamed_mop_out_reg.unit_out_reg, + config.p_reg_num_width(), + &mut |src_reg, src_index| { + connect( + rename_table_read_ports[src_index].addr, + #[hdl] + MOpRegNum { value: src_reg }, + ); + rename_table_read_ports[src_index].data.cast_to_bits() + }, + ), + pc: decoded_insn.pc, }, - )), + ), ); for (reg, reg_kind) in MOpDestReg::regs(dest_reg) .into_iter() @@ -303,6 +314,8 @@ pub fn reg_alloc(config: &CpuConfig) { config.fetch_width.get(), ), ); + #[hdl] + let unit_forwarding_info = wire(config.unit_forwarding_info()); for (unit_index, unit_config) in config.units.iter().enumerate() { let dyn_unit = unit_config.kind.unit(config, unit_index); let unit = instance_with_loc( @@ -311,6 +324,7 @@ pub fn reg_alloc(config: &CpuConfig) { SourceLocation::caller(), ); connect(dyn_unit.cd(unit), cd); + connect(dyn_unit.global_state(unit), global_state); let unit_to_reg_alloc = dyn_unit.unit_to_reg_alloc(unit); // TODO: handle assigning multiple instructions to a unit at a time let assign_to_unit_at_once = NonZeroUsize::new(1).unwrap(); @@ -333,8 +347,8 @@ pub fn reg_alloc(config: &CpuConfig) { ); connect(unit_free_regs_tracker.alloc_out[0].ready, false); connect( - unit_to_reg_alloc.input_insn.data, - Expr::ty(unit_to_reg_alloc.input_insn).data.HdlNone(), + unit_to_reg_alloc.input.data, + Expr::ty(unit_to_reg_alloc.input).data.HdlNone(), ); for fetch_index in 0..config.fetch_width.get() { #[hdl] @@ -343,7 +357,7 @@ pub fn reg_alloc(config: &CpuConfig) { connect(available_units[fetch_index][unit_index], false); } #[hdl] - if !unit_to_reg_alloc.input_insn.ready { + if !unit_to_reg_alloc.input.ready { // must come after to override connects in loops above connect(available_units[fetch_index][unit_index], false); } @@ -354,13 +368,21 @@ pub fn reg_alloc(config: &CpuConfig) { connect(unit_free_regs_tracker.alloc_out[0].ready, true); #[hdl] if let HdlSome(renamed_mop) = - HdlOption::and_then(renamed_mops[fetch_index], |v| dyn_unit.extract_mop(v)) + HdlOption::and_then(renamed_mops[fetch_index], |v| { + #[hdl] + let UnitInput::<_> { mop, pc } = v; + let mop = dyn_unit.extract_mop(mop); + HdlOption::map(mop, |mop| { + #[hdl] + UnitInput::<_> { mop, pc } + }) + }) { - connect(unit_to_reg_alloc.input_insn.data, HdlSome(renamed_mop)); + connect(unit_to_reg_alloc.input.data, HdlSome(renamed_mop)); } else { connect( - unit_to_reg_alloc.input_insn.data, - HdlSome(Expr::ty(unit_to_reg_alloc.input_insn).data.HdlSome.uninit()), + unit_to_reg_alloc.input.data, + HdlSome(Expr::ty(unit_to_reg_alloc.input).data.HdlSome.uninit()), ); // FIXME: add hdl_assert(cd.clk, false.to_expr(), ""); } @@ -385,18 +407,37 @@ pub fn reg_alloc(config: &CpuConfig) { } } } - // TODO: connect outputs to other units + connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info); connect( - unit_to_reg_alloc.unit_forwarding_info, - #[hdl] - UnitForwardingInfo::<_, _, _> { - unit_output_writes: repeat( - HdlOption[config.unit_output_write()].HdlNone(), - config.units.len(), - ), - _phantom: PhantomData, - }, + unit_forwarding_info.unit_output_writes[unit_index], + Expr::ty(unit_forwarding_info) + .unit_output_writes + .element() + .HdlNone(), ); + #[hdl] + if let HdlSome(output) = unit_to_reg_alloc.output { + #[hdl] + let UnitOutput::<_, _> { which, result } = output; + #[hdl] + match result { + UnitResult::<_>::Completed(completed) => { + #[hdl] + let UnitResultCompleted::<_> { value, extra_out } = completed; + connect( + unit_forwarding_info.unit_output_writes[unit_index], + HdlSome( + #[hdl] + UnitOutputWrite::<_> { which, value }, + ), + ); + // TODO: handle extra_out + } + UnitResult::<_>::Trap(trap_data) => { + // TODO: handle traps + } + } + } // TODO: handle cancellation connect( unit_to_reg_alloc.cancel_input, diff --git a/crates/cpu/src/register.rs b/crates/cpu/src/register.rs index 7c81395..43eb52b 100644 --- a/crates/cpu/src/register.rs +++ b/crates/cpu/src/register.rs @@ -39,20 +39,18 @@ impl PRegFlagsPowerISA { } #[hdl] pub fn clear_unused(flags: impl ToExpr) { + // list all flags explicitly so we don't miss handling any new flags #[hdl] - match flags { - // list all flags explicitly so we don't miss handling any new flags - PRegFlags { - pwr_ca_x86_cf: _, - pwr_ca32_x86_af: _, - pwr_ov_x86_of: _, - pwr_ov32_x86_df: _, - pwr_cr_lt_x86_sf: _, - pwr_cr_gt_x86_pf: _, - pwr_cr_eq_x86_zf: _, - pwr_so: _, - } => {} - } + let PRegFlags { + pwr_ca_x86_cf: _, + pwr_ca32_x86_af: _, + pwr_ov_x86_of: _, + pwr_ov32_x86_df: _, + pwr_cr_lt_x86_sf: _, + pwr_cr_gt_x86_pf: _, + pwr_cr_eq_x86_zf: _, + pwr_so: _, + } = flags; } } @@ -83,20 +81,19 @@ impl PRegFlagsX86 { } #[hdl] pub fn clear_unused(flags: impl ToExpr) { + // list all flags explicitly so we don't miss handling any new flags #[hdl] - match flags { - // list all flags explicitly so we don't miss handling any new flags - PRegFlags { - pwr_ca_x86_cf: _, - pwr_ca32_x86_af: _, - pwr_ov_x86_of: _, - pwr_ov32_x86_df: _, - pwr_cr_lt_x86_sf: _, - pwr_cr_gt_x86_pf: _, - pwr_cr_eq_x86_zf: _, - pwr_so: unused1, - } => connect(unused1, false), - } + let PRegFlags { + pwr_ca_x86_cf: _, + pwr_ca32_x86_af: _, + pwr_ov_x86_of: _, + pwr_ov32_x86_df: _, + pwr_cr_lt_x86_sf: _, + pwr_cr_gt_x86_pf: _, + pwr_cr_eq_x86_zf: _, + pwr_so: unused1, + } = flags; + connect(unused1, false); } } diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index 1be9c65..d4d2d78 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -6,7 +6,7 @@ use crate::{ instruction::{ mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, UnitOutRegNum, }, - register::PRegValue, + register::{FlagsMode, PRegValue}, unit::unit_base::UnitToRegAlloc, }; use fayalite::{ @@ -142,6 +142,11 @@ all_units! { } } +#[hdl] +pub struct GlobalState { + pub flags_mode: FlagsMode, +} + #[hdl(cmp_eq)] pub struct UnitResultCompleted { pub value: PRegValue, @@ -215,6 +220,8 @@ pub trait UnitTrait: fn cd(&self, this: Expr) -> Expr; + fn global_state(&self, this: Expr) -> Expr; + fn to_dyn(&self) -> DynUnit; } @@ -279,6 +286,10 @@ impl UnitTrait for DynUnit { self.unit.cd(this) } + fn global_state(&self, this: Expr) -> Expr { + self.unit.global_state(this) + } + fn to_dyn(&self) -> DynUnit { *self } @@ -332,6 +343,10 @@ impl UnitTrait for DynUnitWrapper) -> Expr { + self.0.global_state(Expr::from_bundle(this)) + } + fn to_dyn(&self) -> DynUnit { let unit = self.intern(); DynUnit { diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index 2334ef5..19981e4 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -3,16 +3,246 @@ use crate::{ config::CpuConfig, - instruction::{AluBranchMOp, UnitOutRegNum}, + instruction::{ + AddSubMOp, AluBranchMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOpTrait, OutputIntegerMode, + UnitOutRegNum, COMMON_MOP_SRC_LEN, + }, + register::{FlagsMode, PRegFlagsPowerISA, PRegFlagsX86, PRegValue}, unit::{ - unit_base::{unit_base, UnitToRegAlloc}, - DynUnit, DynUnitWrapper, UnitKind, UnitMOp, UnitTrait, + unit_base::{unit_base, ExecuteEnd, ExecuteStart, UnitToRegAlloc}, + DynUnit, DynUnitWrapper, GlobalState, UnitKind, UnitMOp, UnitOutput, UnitResult, + UnitResultCompleted, UnitTrait, }, }; use fayalite::{ intern::{Intern, Interned}, + module::wire_with_loc, prelude::*, + util::ready_valid::ReadyValid, }; +use std::{collections::HashMap, ops::RangeTo}; + +#[hdl] +fn add_sub( + mop: Expr, DynSize, SrcCount>>, + pc: Expr>, + flags_mode: Expr, + src_values: Expr>, +) -> Expr> { + #[hdl] + let AddSubMOp::<_, _, _> { + alu_common, + invert_src0, + src1_is_carry_in, + invert_carry_in, + add_pc, + } = mop; + #[hdl] + let AluCommonMOp::<_, _, _> { + common, + output_integer_mode, + } = alu_common; + let imm: Expr> = CommonMOp::imm(common).cast_to_static(); + #[hdl] + let carry_in_before_inversion = wire(); + connect(carry_in_before_inversion, false); + #[hdl] + let src1 = wire(); + connect(src1, 0u64); + #[hdl] + if src1_is_carry_in { + #[hdl] + match flags_mode { + FlagsMode::PowerISA(_) => { + connect( + carry_in_before_inversion, + PRegFlagsPowerISA::xer_ca(src_values[1].flags), + ); + } + FlagsMode::X86(_) => { + connect( + carry_in_before_inversion, + PRegFlagsX86::cf(src_values[1].flags), + ); + } + } + } else { + connect(src1, src_values[1].int_fp); + } + #[hdl] + let carry_in = wire(); + connect(carry_in, carry_in_before_inversion ^ invert_carry_in); + #[hdl] + let src0 = wire(); + connect(src0, src_values[0].int_fp); + #[hdl] + if invert_src0 { + connect(src0, !src_values[0].int_fp); + } + #[hdl] + let pc_or_zero = wire(); + connect(pc_or_zero, 0u64); + #[hdl] + if add_pc { + connect(pc_or_zero, pc); + } + let sum_of_sliced = |slice: RangeTo| { + src0[slice] + src1[slice] + src_values[2].int_fp[slice] + pc_or_zero[slice] + imm[slice] + }; + #[hdl] + let sum: UInt<64> = wire(); + connect(sum, sum_of_sliced(..64).cast_to_static()); + let carries = + HashMap::::from_iter([4, 7, 8, 15, 16, 31, 32, 63, 64].into_iter().map( + |bit_index| { + let carry_at = wire_with_loc( + &format!("carry_at_{bit_index}"), + SourceLocation::caller(), + Bool, + ); + connect(carry_at, sum_of_sliced(..bit_index)[bit_index]); + (bit_index, carry_at) + }, + )); + + #[hdl] + let int_fp: UInt<64> = wire(); + + #[hdl] + let x86_cf = wire(); + #[hdl] + let x86_af = wire(); + connect(x86_af, carries[&4]); + #[hdl] + let x86_of = wire(); + #[hdl] + let x86_sf = wire(); + #[hdl] + let x86_pf = wire(); + connect(x86_pf, sum[..8].parity_even()); + #[hdl] + let x86_zf = wire(); + let set_x86_flags = |width| { + connect(x86_cf, carries[&width]); + connect(x86_of, carries[&width].cmp_ne(carries[&(width - 1)])); + connect(x86_sf, sum[width - 1]); + connect(x86_zf, sum[..width].cmp_eq(0u8)); + }; + #[hdl] + let pwr_ca = wire(); + connect(pwr_ca, carries[&64]); + #[hdl] + let pwr_ca32 = wire(); + connect(pwr_ca32, carries[&32]); + #[hdl] + let pwr_ov = wire(); + connect(pwr_ov, carries[&64] ^ carries[&63]); + #[hdl] + let pwr_ov32 = wire(); + connect(pwr_ov32, carries[&32] ^ carries[&31]); + #[hdl] + let pwr_cr_lt = wire(); + connect(pwr_cr_lt, int_fp[63]); + #[hdl] + let pwr_cr_eq = wire(); + connect(pwr_cr_eq, int_fp.cmp_eq(0u64)); + #[hdl] + let pwr_cr_gt = wire(); + connect(pwr_cr_gt, !pwr_cr_lt & !pwr_cr_eq); + #[hdl] + let pwr_so = wire(); + // TODO: SO needs to OR-in the previous value of SO + connect(pwr_so, pwr_ov); + + #[hdl] + match output_integer_mode { + OutputIntegerMode::Full64 => { + set_x86_flags(64); + connect(int_fp, sum); + } + OutputIntegerMode::DupLow32 => { + set_x86_flags(32); + connect( + int_fp, + [sum.cast_to_static::>(); 2] + .cast_to_bits() + .cast_to_static(), + ); + } + OutputIntegerMode::ZeroExt32 => { + set_x86_flags(32); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + OutputIntegerMode::SignExt32 => { + set_x86_flags(32); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + OutputIntegerMode::ZeroExt16 => { + set_x86_flags(16); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + OutputIntegerMode::SignExt16 => { + set_x86_flags(16); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + OutputIntegerMode::ZeroExt8 => { + set_x86_flags(8); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + OutputIntegerMode::SignExt8 => { + set_x86_flags(8); + connect(int_fp, sum.cast_to_static::>().cast_to_static()); + } + } + #[hdl] + let flags = wire(); + #[hdl] + match flags_mode { + FlagsMode::PowerISA(_) => { + PRegFlagsPowerISA::clear_unused(flags); + connect(PRegFlagsPowerISA::xer_ca(flags), pwr_ca); + connect(PRegFlagsPowerISA::xer_ca32(flags), pwr_ca32); + connect(PRegFlagsPowerISA::xer_ov(flags), pwr_ov); + connect(PRegFlagsPowerISA::xer_ov32(flags), pwr_ov32); + connect(PRegFlagsPowerISA::cr_lt(flags), pwr_cr_lt); + connect(PRegFlagsPowerISA::cr_gt(flags), pwr_cr_gt); + connect(PRegFlagsPowerISA::cr_eq(flags), pwr_cr_eq); + connect(PRegFlagsPowerISA::so(flags), pwr_so); + } + FlagsMode::X86(_) => { + PRegFlagsX86::clear_unused(flags); + connect(PRegFlagsX86::cf(flags), x86_cf); + connect(PRegFlagsX86::af(flags), x86_af); + connect(PRegFlagsX86::of(flags), x86_of); + connect(PRegFlagsX86::sf(flags), x86_sf); + connect(PRegFlagsX86::pf(flags), x86_pf); + connect(PRegFlagsX86::zf(flags), x86_zf); + + // this insn doesn't write DF, so it's output isn't used for reading DF + connect(PRegFlagsX86::df(flags), false); + } + } + #[hdl] + UnitResultCompleted::<_> { + value: #[hdl] + PRegValue { int_fp, flags }, + extra_out: (), + } +} + +#[hdl] +fn logical( + mop: Expr, DynSize>>, + flags_mode: Expr, + src_values: Expr>, +) -> Expr> { + // TODO: finish + #[hdl] + UnitResultCompleted::<_> { + value: PRegValue::zeroed(), + extra_out: (), + } +} #[hdl_module] pub fn alu_branch(config: &CpuConfig, unit_index: usize) { @@ -29,20 +259,88 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) { AluBranchMOp[config.unit_out_reg_num()][config.p_reg_num_width()], (), )); + #[hdl] + let global_state: GlobalState = m.input(); + #[hdl] let unit_base = instance(unit_base( config, unit_index, - Expr::ty(unit_to_reg_alloc).input_insn.data.HdlSome, + Expr::ty(unit_to_reg_alloc).input.data.HdlSome.mop, (), )); connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc); connect(unit_base.cd, cd); - connect(unit_base.execute_start.ready, true); // TODO: finish + connect(unit_base.execute_start.ready, true); connect( unit_base.execute_end, Expr::ty(unit_base.execute_end).HdlNone(), - ); // TODO: finish + ); + #[hdl] + if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) { + #[hdl] + let ExecuteStart::<_> { + mop, + pc, + src_values, + } = execute_start; + #[hdl] + match mop { + AluBranchMOp::<_, _>::AddSub(mop) => connect( + unit_base.execute_end, + HdlSome( + #[hdl] + ExecuteEnd::<_, _> { + unit_output: #[hdl] + UnitOutput::<_, _> { + which: MOpTrait::dest_reg(mop), + result: UnitResult[()].Completed(add_sub( + mop, + pc, + global_state.flags_mode, + src_values, + )), + }, + }, + ), + ), + AluBranchMOp::<_, _>::AddSubI(mop) => connect( + unit_base.execute_end, + HdlSome( + #[hdl] + ExecuteEnd::<_, _> { + unit_output: #[hdl] + UnitOutput::<_, _> { + which: MOpTrait::dest_reg(mop), + result: UnitResult[()].Completed(add_sub( + mop, + pc, + global_state.flags_mode, + src_values, + )), + }, + }, + ), + ), + AluBranchMOp::<_, _>::Logical(mop) => connect( + unit_base.execute_end, + HdlSome( + #[hdl] + ExecuteEnd::<_, _> { + unit_output: #[hdl] + UnitOutput::<_, _> { + which: MOpTrait::dest_reg(mop), + result: UnitResult[()].Completed(logical( + mop, + global_state.flags_mode, + src_values, + )), + }, + }, + ), + ), + } + } } #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] @@ -103,6 +401,10 @@ impl UnitTrait for AluBranch { this.cd } + fn global_state(&self, this: Expr) -> Expr { + this.global_state + } + fn to_dyn(&self) -> DynUnit { DynUnitWrapper(*self).to_dyn() } diff --git a/crates/cpu/src/unit/unit_base.rs b/crates/cpu/src/unit/unit_base.rs index ea921f1..4a98396 100644 --- a/crates/cpu/src/unit/unit_base.rs +++ b/crates/cpu/src/unit/unit_base.rs @@ -3,12 +3,18 @@ use crate::{ config::CpuConfig, - instruction::{MOpTrait, PRegNum, UnitOutRegNum, COMMON_MOP_SRC_LEN}, + instruction::{MOpTrait, PRegNum, UnitNum, UnitOutRegNum, COMMON_MOP_SRC_LEN}, register::PRegValue, unit::{UnitCancelInput, UnitOutput, UnitOutputWrite}, util::tree_reduce::tree_reduce, }; -use fayalite::{module::wire_with_loc, prelude::*, ty::StaticType, util::ready_valid::ReadyValid}; +use fayalite::{ + memory::splat_mask, + module::{memory_with_loc, wire_with_loc}, + prelude::*, + ty::StaticType, + util::ready_valid::ReadyValid, +}; use std::marker::PhantomData; #[hdl] @@ -17,6 +23,12 @@ pub struct UnitForwardingInfo, } +#[hdl] +pub struct UnitInput { + pub mop: MOp, + pub pc: UInt<64>, +} + #[hdl] pub struct UnitToRegAlloc< MOp: Type, @@ -28,7 +40,7 @@ pub struct UnitToRegAlloc< #[hdl(flip)] pub unit_forwarding_info: UnitForwardingInfo, #[hdl(flip)] - pub input_insn: ReadyValid, + pub input: ReadyValid>, #[hdl(flip)] pub cancel_input: HdlOption>, pub output: HdlOption>, @@ -38,7 +50,7 @@ impl { pub fn mop_ty(self) -> MOp { - self.input_insn.data.HdlSome + self.input.data.HdlSome.mop } pub fn extra_out_ty(self) -> ExtraOut { self.output.HdlSome.extra_out_ty() @@ -48,6 +60,7 @@ impl>> { pub mop: MOp, + pub pc: UInt<64>, pub src_values: Array, } @@ -137,6 +150,7 @@ impl InFlightOpState { struct InFlightOp { state: InFlightOpState, mop: MOp, + pc: UInt<64>, src_ready_flags: Array, } @@ -171,6 +185,7 @@ impl InFlightOpsSummary { let InFlightOp::<_> { state, mop: _, + pc: _, src_ready_flags, } = in_flight_op; connect(ready_op_index, HdlOption[op_index_ty].HdlNone()); @@ -258,21 +273,85 @@ pub fn unit_base< connect(in_flight_ops_summary, in_flight_ops_summary_value); connect( - unit_to_reg_alloc.input_insn.ready, + unit_to_reg_alloc.input.ready, HdlOption::is_some(in_flight_ops_summary.empty_op_index), ); - // TODO: connect(execute_start.data, (in_flight_ops_summary.ready_op_index)); + + let unit_output_writes = unit_to_reg_alloc.unit_forwarding_info.unit_output_writes; + #[hdl] + let read_src_regs = wire(mop_ty.src_regs_ty()); + connect( + read_src_regs, + repeat(config.p_reg_num().const_zero().cast_to_bits(), ConstUsize), + ); + #[hdl] + let read_src_values = wire(); + connect(read_src_values, [PRegValue::zeroed(); COMMON_MOP_SRC_LEN]); + for unit_index in 0..Expr::ty(unit_output_writes).len() { + let mut unit_output_regs = memory_with_loc( + &format!("unit_{unit_index}_output_regs"), + PRegValue, + SourceLocation::caller(), + ); + unit_output_regs.depth(1 << config.out_reg_num_width); + + for src_index in 0..COMMON_MOP_SRC_LEN { + let read_port = unit_output_regs.new_read_port(); + let p_reg_num = read_src_regs[src_index].cast_bits_to(config.p_reg_num()); + connect_any(read_port.addr, p_reg_num.unit_out_reg.value); + connect(read_port.en, false); + connect(read_port.clk, cd.clk); + #[hdl] + if UnitNum::is_index(p_reg_num.unit_num, unit_index) { + connect(read_port.en, true); + connect(read_src_values[src_index], read_port.data); + } + } + + let write_port = unit_output_regs.new_write_port(); + connect_any(write_port.addr, 0u8); + connect(write_port.en, false); + connect(write_port.clk, cd.clk); + connect(write_port.data, PRegValue::zeroed()); + connect(write_port.mask, splat_mask(PRegValue, true.to_expr())); + #[hdl] + if let HdlSome(unit_output_write) = unit_output_writes[unit_index] { + connect_any(write_port.addr, unit_output_write.which.value); + connect(write_port.data, unit_output_write.value); + connect(write_port.en, true); + } + } + + #[hdl] + if let HdlSome(ready_op_index) = in_flight_ops_summary.ready_op_index { + #[hdl] + if let HdlSome(in_flight_op) = in_flight_ops[ready_op_index] { + connect( + execute_start.data, + HdlSome( + #[hdl] + ExecuteStart::<_> { + mop: in_flight_op.mop, + pc: in_flight_op.pc, + src_values: read_src_values, + }, + ), + ); + } + } connect( unit_to_reg_alloc.output, Expr::ty(unit_to_reg_alloc.output).HdlNone(), - ); // TODO: finish + ); #[hdl] let input_in_flight_op = wire(HdlOption[in_flight_op_ty]); connect(input_in_flight_op, HdlOption[in_flight_op_ty].HdlNone()); #[hdl] - if let HdlSome(mop) = ReadyValid::firing_data(unit_to_reg_alloc.input_insn) { + if let HdlSome(input) = ReadyValid::firing_data(unit_to_reg_alloc.input) { + #[hdl] + let UnitInput::<_> { mop, pc } = input; #[hdl] let input_mop_src_regs = wire(mop_ty.src_regs_ty()); connect( @@ -309,6 +388,7 @@ pub fn unit_base< InFlightOp::<_> { state: InFlightOpState.Ready(), mop, + pc, src_ready_flags, }, ), @@ -345,6 +425,7 @@ pub fn unit_base< let InFlightOp::<_> { state, mop, + pc, src_ready_flags, } = in_flight_op; let which = MOp::dest_reg(mop); @@ -359,11 +440,17 @@ pub fn unit_base< ); MOp::connect_src_regs(mop, src_regs); + #[hdl] + if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome( + in_flight_op_index.cast_to(Expr::ty(in_flight_ops_summary).ready_op_index.HdlSome), + )) { + connect(read_src_regs, src_regs); + } + connect( in_flight_op_next_src_ready_flags[in_flight_op_index], src_ready_flags, ); - let unit_output_writes = unit_to_reg_alloc.unit_forwarding_info.unit_output_writes; for unit_index in 0..Expr::ty(unit_output_writes).len() { #[hdl] if let HdlSome(unit_output_write) = unit_output_writes[unit_index] { @@ -404,6 +491,13 @@ pub fn unit_base< #[hdl] if which.cmp_eq(unit_output.which) { connect(in_flight_op_execute_ending[in_flight_op_index], true); + #[hdl] + if !in_flight_op_canceling[in_flight_op_index] { + #[hdl] + if let InFlightOpState::Running = state { + connect(unit_to_reg_alloc.output, HdlSome(unit_output)); + } + } } } #[hdl] @@ -439,7 +533,8 @@ pub fn unit_base< InFlightOp::<_> { state, mop, - src_ready_flags, + pc, + src_ready_flags: in_flight_op_next_src_ready_flags[in_flight_op_index], }, ), ); diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd index 126bc6a..30e794c 100644 --- a/crates/cpu/tests/expected/reg_alloc.vcd +++ b/crates/cpu/tests/expected/reg_alloc.vcd @@ -53,8 +53,8 @@ $upscope $end $var string 1 0 output_integer_mode $end $upscope $end $var wire 1 1 invert_src0 $end -$var wire 1 2 invert_carry_in $end -$var wire 1 3 invert_carry_out $end +$var wire 1 2 src1_is_carry_in $end +$var wire 1 3 invert_carry_in $end $var wire 1 4 add_pc $end $upscope $end $scope struct AddSubI $end @@ -96,8 +96,8 @@ $upscope $end $var string 1 ? output_integer_mode $end $upscope $end $var wire 1 @ invert_src0 $end -$var wire 1 A invert_carry_in $end -$var wire 1 B invert_carry_out $end +$var wire 1 A src1_is_carry_in $end +$var wire 1 B invert_carry_in $end $var wire 1 C add_pc $end $upscope $end $scope struct Logical $end @@ -341,8 +341,8 @@ $upscope $end $var string 1 ," output_integer_mode $end $upscope $end $var wire 1 -" invert_src0 $end -$var wire 1 ." invert_carry_in $end -$var wire 1 /" invert_carry_out $end +$var wire 1 ." src1_is_carry_in $end +$var wire 1 /" invert_carry_in $end $var wire 1 0" add_pc $end $upscope $end $scope struct AddSubI $end @@ -384,8 +384,8 @@ $upscope $end $var string 1 ;" output_integer_mode $end $upscope $end $var wire 1 <" invert_src0 $end -$var wire 1 =" invert_carry_in $end -$var wire 1 >" invert_carry_out $end +$var wire 1 =" src1_is_carry_in $end +$var wire 1 >" invert_carry_in $end $var wire 1 ?" add_pc $end $upscope $end $scope struct Logical $end @@ -595,2698 +595,2707 @@ $upscope $end $var wire 1 {" ready $end $upscope $end $upscope $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 |" \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end $scope struct rename_table_normal_mem $end $scope struct contents $end $scope struct \[0] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 TP adj_value $end +$var reg 2 -Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 7S value $end +$var reg 4 n[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 UP adj_value $end +$var reg 2 .Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 8S value $end +$var reg 4 o[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[2] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 VP adj_value $end +$var reg 2 /Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 9S value $end +$var reg 4 p[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[3] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 WP adj_value $end +$var reg 2 0Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :S value $end +$var reg 4 q[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[4] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 XP adj_value $end +$var reg 2 1Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;S value $end +$var reg 4 r[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[5] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 YP adj_value $end +$var reg 2 2Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 S value $end +$var reg 4 u[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[8] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \P adj_value $end +$var reg 2 5Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?S value $end +$var reg 4 v[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[9] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]P adj_value $end +$var reg 2 6Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @S value $end +$var reg 4 w[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[10] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^P adj_value $end +$var reg 2 7Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 AS value $end +$var reg 4 x[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[11] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 _P adj_value $end +$var reg 2 8Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 BS value $end +$var reg 4 y[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[12] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 `P adj_value $end +$var reg 2 9Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 CS value $end +$var reg 4 z[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[13] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 aP adj_value $end +$var reg 2 :Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 DS value $end +$var reg 4 {[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[14] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 bP adj_value $end +$var reg 2 ;Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ES value $end +$var reg 4 |[ value $end $upscope $end $upscope $end $upscope $end $scope struct \[15] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 cP adj_value $end +$var reg 2 Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 HS value $end +$var reg 4 !\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[18] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 fP adj_value $end +$var reg 2 ?Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 IS value $end +$var reg 4 "\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[19] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 gP adj_value $end +$var reg 2 @Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 JS value $end +$var reg 4 #\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[20] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 hP adj_value $end +$var reg 2 AY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 KS value $end +$var reg 4 $\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[21] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 iP adj_value $end +$var reg 2 BY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 LS value $end +$var reg 4 %\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[22] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 jP adj_value $end +$var reg 2 CY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 MS value $end +$var reg 4 &\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[23] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 kP adj_value $end +$var reg 2 DY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 NS value $end +$var reg 4 '\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[24] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 lP adj_value $end +$var reg 2 EY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 OS value $end +$var reg 4 (\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[25] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 mP adj_value $end +$var reg 2 FY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 PS value $end +$var reg 4 )\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[26] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 nP adj_value $end +$var reg 2 GY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 QS value $end +$var reg 4 *\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[27] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 oP adj_value $end +$var reg 2 HY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 RS value $end +$var reg 4 +\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[28] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 pP adj_value $end +$var reg 2 IY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 SS value $end +$var reg 4 ,\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[29] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 qP adj_value $end +$var reg 2 JY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 TS value $end +$var reg 4 -\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[30] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 rP adj_value $end +$var reg 2 KY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 US value $end +$var reg 4 .\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[31] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 sP adj_value $end +$var reg 2 LY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 VS value $end +$var reg 4 /\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[32] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 tP adj_value $end +$var reg 2 MY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 WS value $end +$var reg 4 0\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[33] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 uP adj_value $end +$var reg 2 NY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 XS value $end +$var reg 4 1\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[34] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 vP adj_value $end +$var reg 2 OY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 YS value $end +$var reg 4 2\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[35] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 wP adj_value $end +$var reg 2 PY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ZS value $end +$var reg 4 3\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[36] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 xP adj_value $end +$var reg 2 QY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 [S value $end +$var reg 4 4\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[37] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 yP adj_value $end +$var reg 2 RY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 \S value $end +$var reg 4 5\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[38] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 zP adj_value $end +$var reg 2 SY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ]S value $end +$var reg 4 6\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[39] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 {P adj_value $end +$var reg 2 TY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ^S value $end +$var reg 4 7\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[40] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |P adj_value $end +$var reg 2 UY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _S value $end +$var reg 4 8\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[41] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }P adj_value $end +$var reg 2 VY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `S value $end +$var reg 4 9\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[42] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~P adj_value $end +$var reg 2 WY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 aS value $end +$var reg 4 :\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[43] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !Q adj_value $end +$var reg 2 XY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 bS value $end +$var reg 4 ;\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[44] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "Q adj_value $end +$var reg 2 YY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 cS value $end +$var reg 4 <\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[45] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #Q adj_value $end +$var reg 2 ZY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 dS value $end +$var reg 4 =\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[46] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $Q adj_value $end +$var reg 2 [Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 eS value $end +$var reg 4 >\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[47] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %Q adj_value $end +$var reg 2 \Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 fS value $end +$var reg 4 ?\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[48] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &Q adj_value $end +$var reg 2 ]Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 gS value $end +$var reg 4 @\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[49] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 'Q adj_value $end +$var reg 2 ^Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 hS value $end +$var reg 4 A\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[50] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (Q adj_value $end +$var reg 2 _Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 iS value $end +$var reg 4 B\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[51] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )Q adj_value $end +$var reg 2 `Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 jS value $end +$var reg 4 C\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[52] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *Q adj_value $end +$var reg 2 aY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 kS value $end +$var reg 4 D\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[53] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +Q adj_value $end +$var reg 2 bY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 lS value $end +$var reg 4 E\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[54] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,Q adj_value $end +$var reg 2 cY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 mS value $end +$var reg 4 F\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[55] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -Q adj_value $end +$var reg 2 dY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 nS value $end +$var reg 4 G\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[56] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .Q adj_value $end +$var reg 2 eY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 oS value $end +$var reg 4 H\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[57] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /Q adj_value $end +$var reg 2 fY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 pS value $end +$var reg 4 I\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[58] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 0Q adj_value $end +$var reg 2 gY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 qS value $end +$var reg 4 J\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[59] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 1Q adj_value $end +$var reg 2 hY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 rS value $end +$var reg 4 K\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[60] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 2Q adj_value $end +$var reg 2 iY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 sS value $end +$var reg 4 L\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[61] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 3Q adj_value $end +$var reg 2 jY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 tS value $end +$var reg 4 M\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[62] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 4Q adj_value $end +$var reg 2 kY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 uS value $end +$var reg 4 N\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[63] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 5Q adj_value $end +$var reg 2 lY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 vS value $end +$var reg 4 O\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[64] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 6Q adj_value $end +$var reg 2 mY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 wS value $end +$var reg 4 P\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[65] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 7Q adj_value $end +$var reg 2 nY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 xS value $end +$var reg 4 Q\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[66] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 8Q adj_value $end +$var reg 2 oY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 yS value $end +$var reg 4 R\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[67] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 9Q adj_value $end +$var reg 2 pY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 zS value $end +$var reg 4 S\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[68] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 :Q adj_value $end +$var reg 2 qY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {S value $end +$var reg 4 T\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[69] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ;Q adj_value $end +$var reg 2 rY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 |S value $end +$var reg 4 U\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[70] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Q adj_value $end +$var reg 2 uY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 !T value $end +$var reg 4 X\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[73] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ?Q adj_value $end +$var reg 2 vY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 "T value $end +$var reg 4 Y\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[74] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 @Q adj_value $end +$var reg 2 wY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 #T value $end +$var reg 4 Z\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[75] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 AQ adj_value $end +$var reg 2 xY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 $T value $end +$var reg 4 [\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[76] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 BQ adj_value $end +$var reg 2 yY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 %T value $end +$var reg 4 \\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[77] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 CQ adj_value $end +$var reg 2 zY adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 &T value $end +$var reg 4 ]\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[78] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 DQ adj_value $end +$var reg 2 {Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 'T value $end +$var reg 4 ^\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[79] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 EQ adj_value $end +$var reg 2 |Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 (T value $end +$var reg 4 _\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[80] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 FQ adj_value $end +$var reg 2 }Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 )T value $end +$var reg 4 `\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[81] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 GQ adj_value $end +$var reg 2 ~Y adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 *T value $end +$var reg 4 a\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[82] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 HQ adj_value $end +$var reg 2 !Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 +T value $end +$var reg 4 b\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[83] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 IQ adj_value $end +$var reg 2 "Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ,T value $end +$var reg 4 c\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[84] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 JQ adj_value $end +$var reg 2 #Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 -T value $end +$var reg 4 d\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[85] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 KQ adj_value $end +$var reg 2 $Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 .T value $end +$var reg 4 e\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[86] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 LQ adj_value $end +$var reg 2 %Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 /T value $end +$var reg 4 f\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[87] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 MQ adj_value $end +$var reg 2 &Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 0T value $end +$var reg 4 g\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[88] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 NQ adj_value $end +$var reg 2 'Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 1T value $end +$var reg 4 h\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[89] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 OQ adj_value $end +$var reg 2 (Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 2T value $end +$var reg 4 i\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[90] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 PQ adj_value $end +$var reg 2 )Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 3T value $end +$var reg 4 j\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[91] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 QQ adj_value $end +$var reg 2 *Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 4T value $end +$var reg 4 k\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[92] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 RQ adj_value $end +$var reg 2 +Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 5T value $end +$var reg 4 l\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[93] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 SQ adj_value $end +$var reg 2 ,Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 6T value $end +$var reg 4 m\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[94] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 TQ adj_value $end +$var reg 2 -Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 7T value $end +$var reg 4 n\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[95] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 UQ adj_value $end +$var reg 2 .Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 8T value $end +$var reg 4 o\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[96] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 VQ adj_value $end +$var reg 2 /Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 9T value $end +$var reg 4 p\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[97] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 WQ adj_value $end +$var reg 2 0Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :T value $end +$var reg 4 q\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[98] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 XQ adj_value $end +$var reg 2 1Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;T value $end +$var reg 4 r\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[99] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 YQ adj_value $end +$var reg 2 2Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 T value $end +$var reg 4 u\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[102] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \Q adj_value $end +$var reg 2 5Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?T value $end +$var reg 4 v\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[103] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]Q adj_value $end +$var reg 2 6Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @T value $end +$var reg 4 w\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[104] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^Q adj_value $end +$var reg 2 7Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 AT value $end +$var reg 4 x\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[105] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 _Q adj_value $end +$var reg 2 8Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 BT value $end +$var reg 4 y\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[106] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 `Q adj_value $end +$var reg 2 9Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 CT value $end +$var reg 4 z\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[107] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 aQ adj_value $end +$var reg 2 :Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 DT value $end +$var reg 4 {\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[108] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 bQ adj_value $end +$var reg 2 ;Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ET value $end +$var reg 4 |\ value $end $upscope $end $upscope $end $upscope $end $scope struct \[109] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 cQ adj_value $end +$var reg 2 Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 HT value $end +$var reg 4 !] value $end $upscope $end $upscope $end $upscope $end $scope struct \[112] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 fQ adj_value $end +$var reg 2 ?Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 IT value $end +$var reg 4 "] value $end $upscope $end $upscope $end $upscope $end $scope struct \[113] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 gQ adj_value $end +$var reg 2 @Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 JT value $end +$var reg 4 #] value $end $upscope $end $upscope $end $upscope $end $scope struct \[114] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 hQ adj_value $end +$var reg 2 AZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 KT value $end +$var reg 4 $] value $end $upscope $end $upscope $end $upscope $end $scope struct \[115] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 iQ adj_value $end +$var reg 2 BZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 LT value $end +$var reg 4 %] value $end $upscope $end $upscope $end $upscope $end $scope struct \[116] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 jQ adj_value $end +$var reg 2 CZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 MT value $end +$var reg 4 &] value $end $upscope $end $upscope $end $upscope $end $scope struct \[117] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 kQ adj_value $end +$var reg 2 DZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 NT value $end +$var reg 4 '] value $end $upscope $end $upscope $end $upscope $end $scope struct \[118] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 lQ adj_value $end +$var reg 2 EZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 OT value $end +$var reg 4 (] value $end $upscope $end $upscope $end $upscope $end $scope struct \[119] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 mQ adj_value $end +$var reg 2 FZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 PT value $end +$var reg 4 )] value $end $upscope $end $upscope $end $upscope $end $scope struct \[120] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 nQ adj_value $end +$var reg 2 GZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 QT value $end +$var reg 4 *] value $end $upscope $end $upscope $end $upscope $end $scope struct \[121] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 oQ adj_value $end +$var reg 2 HZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 RT value $end +$var reg 4 +] value $end $upscope $end $upscope $end $upscope $end $scope struct \[122] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 pQ adj_value $end +$var reg 2 IZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ST value $end +$var reg 4 ,] value $end $upscope $end $upscope $end $upscope $end $scope struct \[123] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 qQ adj_value $end +$var reg 2 JZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 TT value $end +$var reg 4 -] value $end $upscope $end $upscope $end $upscope $end $scope struct \[124] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 rQ adj_value $end +$var reg 2 KZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 UT value $end +$var reg 4 .] value $end $upscope $end $upscope $end $upscope $end $scope struct \[125] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 sQ adj_value $end +$var reg 2 LZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 VT value $end +$var reg 4 /] value $end $upscope $end $upscope $end $upscope $end $scope struct \[126] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 tQ adj_value $end +$var reg 2 MZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 WT value $end +$var reg 4 0] value $end $upscope $end $upscope $end $upscope $end $scope struct \[127] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 uQ adj_value $end +$var reg 2 NZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 XT value $end +$var reg 4 1] value $end $upscope $end $upscope $end $upscope $end $scope struct \[128] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 vQ adj_value $end +$var reg 2 OZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 YT value $end +$var reg 4 2] value $end $upscope $end $upscope $end $upscope $end $scope struct \[129] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 wQ adj_value $end +$var reg 2 PZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ZT value $end +$var reg 4 3] value $end $upscope $end $upscope $end $upscope $end $scope struct \[130] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 xQ adj_value $end +$var reg 2 QZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 [T value $end +$var reg 4 4] value $end $upscope $end $upscope $end $upscope $end $scope struct \[131] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 yQ adj_value $end +$var reg 2 RZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 \T value $end +$var reg 4 5] value $end $upscope $end $upscope $end $upscope $end $scope struct \[132] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 zQ adj_value $end +$var reg 2 SZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ]T value $end +$var reg 4 6] value $end $upscope $end $upscope $end $upscope $end $scope struct \[133] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 {Q adj_value $end +$var reg 2 TZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ^T value $end +$var reg 4 7] value $end $upscope $end $upscope $end $upscope $end $scope struct \[134] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |Q adj_value $end +$var reg 2 UZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _T value $end +$var reg 4 8] value $end $upscope $end $upscope $end $upscope $end $scope struct \[135] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }Q adj_value $end +$var reg 2 VZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `T value $end +$var reg 4 9] value $end $upscope $end $upscope $end $upscope $end $scope struct \[136] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~Q adj_value $end +$var reg 2 WZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 aT value $end +$var reg 4 :] value $end $upscope $end $upscope $end $upscope $end $scope struct \[137] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !R adj_value $end +$var reg 2 XZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 bT value $end +$var reg 4 ;] value $end $upscope $end $upscope $end $upscope $end $scope struct \[138] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "R adj_value $end +$var reg 2 YZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 cT value $end +$var reg 4 <] value $end $upscope $end $upscope $end $upscope $end $scope struct \[139] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #R adj_value $end +$var reg 2 ZZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 dT value $end +$var reg 4 =] value $end $upscope $end $upscope $end $upscope $end $scope struct \[140] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $R adj_value $end +$var reg 2 [Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 eT value $end +$var reg 4 >] value $end $upscope $end $upscope $end $upscope $end $scope struct \[141] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %R adj_value $end +$var reg 2 \Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 fT value $end +$var reg 4 ?] value $end $upscope $end $upscope $end $upscope $end $scope struct \[142] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &R adj_value $end +$var reg 2 ]Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 gT value $end +$var reg 4 @] value $end $upscope $end $upscope $end $upscope $end $scope struct \[143] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 'R adj_value $end +$var reg 2 ^Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 hT value $end +$var reg 4 A] value $end $upscope $end $upscope $end $upscope $end $scope struct \[144] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (R adj_value $end +$var reg 2 _Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 iT value $end +$var reg 4 B] value $end $upscope $end $upscope $end $upscope $end $scope struct \[145] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )R adj_value $end +$var reg 2 `Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 jT value $end +$var reg 4 C] value $end $upscope $end $upscope $end $upscope $end $scope struct \[146] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *R adj_value $end +$var reg 2 aZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 kT value $end +$var reg 4 D] value $end $upscope $end $upscope $end $upscope $end $scope struct \[147] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +R adj_value $end +$var reg 2 bZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 lT value $end +$var reg 4 E] value $end $upscope $end $upscope $end $upscope $end $scope struct \[148] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,R adj_value $end +$var reg 2 cZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 mT value $end +$var reg 4 F] value $end $upscope $end $upscope $end $upscope $end $scope struct \[149] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -R adj_value $end +$var reg 2 dZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 nT value $end +$var reg 4 G] value $end $upscope $end $upscope $end $upscope $end $scope struct \[150] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .R adj_value $end +$var reg 2 eZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 oT value $end +$var reg 4 H] value $end $upscope $end $upscope $end $upscope $end $scope struct \[151] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /R adj_value $end +$var reg 2 fZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 pT value $end +$var reg 4 I] value $end $upscope $end $upscope $end $upscope $end $scope struct \[152] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 0R adj_value $end +$var reg 2 gZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 qT value $end +$var reg 4 J] value $end $upscope $end $upscope $end $upscope $end $scope struct \[153] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 1R adj_value $end +$var reg 2 hZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 rT value $end +$var reg 4 K] value $end $upscope $end $upscope $end $upscope $end $scope struct \[154] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 2R adj_value $end +$var reg 2 iZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 sT value $end +$var reg 4 L] value $end $upscope $end $upscope $end $upscope $end $scope struct \[155] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 3R adj_value $end +$var reg 2 jZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 tT value $end +$var reg 4 M] value $end $upscope $end $upscope $end $upscope $end $scope struct \[156] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 4R adj_value $end +$var reg 2 kZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 uT value $end +$var reg 4 N] value $end $upscope $end $upscope $end $upscope $end $scope struct \[157] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 5R adj_value $end +$var reg 2 lZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 vT value $end +$var reg 4 O] value $end $upscope $end $upscope $end $upscope $end $scope struct \[158] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 6R adj_value $end +$var reg 2 mZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 wT value $end +$var reg 4 P] value $end $upscope $end $upscope $end $upscope $end $scope struct \[159] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 7R adj_value $end +$var reg 2 nZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 xT value $end +$var reg 4 Q] value $end $upscope $end $upscope $end $upscope $end $scope struct \[160] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 8R adj_value $end +$var reg 2 oZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 yT value $end +$var reg 4 R] value $end $upscope $end $upscope $end $upscope $end $scope struct \[161] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 9R adj_value $end +$var reg 2 pZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 zT value $end +$var reg 4 S] value $end $upscope $end $upscope $end $upscope $end $scope struct \[162] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 :R adj_value $end +$var reg 2 qZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {T value $end +$var reg 4 T] value $end $upscope $end $upscope $end $upscope $end $scope struct \[163] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ;R adj_value $end +$var reg 2 rZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 |T value $end +$var reg 4 U] value $end $upscope $end $upscope $end $upscope $end $scope struct \[164] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 R adj_value $end +$var reg 2 uZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 !U value $end +$var reg 4 X] value $end $upscope $end $upscope $end $upscope $end $scope struct \[167] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ?R adj_value $end +$var reg 2 vZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 "U value $end +$var reg 4 Y] value $end $upscope $end $upscope $end $upscope $end $scope struct \[168] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 @R adj_value $end +$var reg 2 wZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 #U value $end +$var reg 4 Z] value $end $upscope $end $upscope $end $upscope $end $scope struct \[169] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 AR adj_value $end +$var reg 2 xZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 $U value $end +$var reg 4 [] value $end $upscope $end $upscope $end $upscope $end $scope struct \[170] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 BR adj_value $end +$var reg 2 yZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 %U value $end +$var reg 4 \] value $end $upscope $end $upscope $end $upscope $end $scope struct \[171] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 CR adj_value $end +$var reg 2 zZ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 &U value $end +$var reg 4 ]] value $end $upscope $end $upscope $end $upscope $end $scope struct \[172] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 DR adj_value $end +$var reg 2 {Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 'U value $end +$var reg 4 ^] value $end $upscope $end $upscope $end $upscope $end $scope struct \[173] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ER adj_value $end +$var reg 2 |Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 (U value $end +$var reg 4 _] value $end $upscope $end $upscope $end $upscope $end $scope struct \[174] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 FR adj_value $end +$var reg 2 }Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 )U value $end +$var reg 4 `] value $end $upscope $end $upscope $end $upscope $end $scope struct \[175] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 GR adj_value $end +$var reg 2 ~Z adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 *U value $end +$var reg 4 a] value $end $upscope $end $upscope $end $upscope $end $scope struct \[176] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 HR adj_value $end +$var reg 2 ![ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 +U value $end +$var reg 4 b] value $end $upscope $end $upscope $end $upscope $end $scope struct \[177] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 IR adj_value $end +$var reg 2 "[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ,U value $end +$var reg 4 c] value $end $upscope $end $upscope $end $upscope $end $scope struct \[178] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 JR adj_value $end +$var reg 2 #[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 -U value $end +$var reg 4 d] value $end $upscope $end $upscope $end $upscope $end $scope struct \[179] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 KR adj_value $end +$var reg 2 $[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 .U value $end +$var reg 4 e] value $end $upscope $end $upscope $end $upscope $end $scope struct \[180] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 LR adj_value $end +$var reg 2 %[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 /U value $end +$var reg 4 f] value $end $upscope $end $upscope $end $upscope $end $scope struct \[181] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 MR adj_value $end +$var reg 2 &[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 0U value $end +$var reg 4 g] value $end $upscope $end $upscope $end $upscope $end $scope struct \[182] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 NR adj_value $end +$var reg 2 '[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 1U value $end +$var reg 4 h] value $end $upscope $end $upscope $end $upscope $end $scope struct \[183] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 OR adj_value $end +$var reg 2 ([ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 2U value $end +$var reg 4 i] value $end $upscope $end $upscope $end $upscope $end $scope struct \[184] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 PR adj_value $end +$var reg 2 )[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 3U value $end +$var reg 4 j] value $end $upscope $end $upscope $end $upscope $end $scope struct \[185] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 QR adj_value $end +$var reg 2 *[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 4U value $end +$var reg 4 k] value $end $upscope $end $upscope $end $upscope $end $scope struct \[186] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 RR adj_value $end +$var reg 2 +[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 5U value $end +$var reg 4 l] value $end $upscope $end $upscope $end $upscope $end $scope struct \[187] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 SR adj_value $end +$var reg 2 ,[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 6U value $end +$var reg 4 m] value $end $upscope $end $upscope $end $upscope $end $scope struct \[188] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 TR adj_value $end +$var reg 2 -[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 7U value $end +$var reg 4 n] value $end $upscope $end $upscope $end $upscope $end $scope struct \[189] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 UR adj_value $end +$var reg 2 .[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 8U value $end +$var reg 4 o] value $end $upscope $end $upscope $end $upscope $end $scope struct \[190] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 VR adj_value $end +$var reg 2 /[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 9U value $end +$var reg 4 p] value $end $upscope $end $upscope $end $upscope $end $scope struct \[191] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 WR adj_value $end +$var reg 2 0[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :U value $end +$var reg 4 q] value $end $upscope $end $upscope $end $upscope $end $scope struct \[192] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 XR adj_value $end +$var reg 2 1[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;U value $end +$var reg 4 r] value $end $upscope $end $upscope $end $upscope $end $scope struct \[193] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 YR adj_value $end +$var reg 2 2[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 U value $end +$var reg 4 u] value $end $upscope $end $upscope $end $upscope $end $scope struct \[196] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \R adj_value $end +$var reg 2 5[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?U value $end +$var reg 4 v] value $end $upscope $end $upscope $end $upscope $end $scope struct \[197] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]R adj_value $end +$var reg 2 6[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @U value $end +$var reg 4 w] value $end $upscope $end $upscope $end $upscope $end $scope struct \[198] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^R adj_value $end +$var reg 2 7[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 AU value $end +$var reg 4 x] value $end $upscope $end $upscope $end $upscope $end $scope struct \[199] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 _R adj_value $end +$var reg 2 8[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 BU value $end +$var reg 4 y] value $end $upscope $end $upscope $end $upscope $end $scope struct \[200] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 `R adj_value $end +$var reg 2 9[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 CU value $end +$var reg 4 z] value $end $upscope $end $upscope $end $upscope $end $scope struct \[201] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 aR adj_value $end +$var reg 2 :[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 DU value $end +$var reg 4 {] value $end $upscope $end $upscope $end $upscope $end $scope struct \[202] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 bR adj_value $end +$var reg 2 ;[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 EU value $end +$var reg 4 |] value $end $upscope $end $upscope $end $upscope $end $scope struct \[203] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 cR adj_value $end +$var reg 2 <[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 FU value $end +$var reg 4 }] value $end $upscope $end $upscope $end $upscope $end $scope struct \[204] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 dR adj_value $end +$var reg 2 =[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 GU value $end +$var reg 4 ~] value $end $upscope $end $upscope $end $upscope $end $scope struct \[205] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 eR adj_value $end +$var reg 2 >[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 HU value $end +$var reg 4 !^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[206] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 fR adj_value $end +$var reg 2 ?[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 IU value $end +$var reg 4 "^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[207] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 gR adj_value $end +$var reg 2 @[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 JU value $end +$var reg 4 #^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[208] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 hR adj_value $end +$var reg 2 A[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 KU value $end +$var reg 4 $^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[209] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 iR adj_value $end +$var reg 2 B[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 LU value $end +$var reg 4 %^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[210] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 jR adj_value $end +$var reg 2 C[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 MU value $end +$var reg 4 &^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[211] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 kR adj_value $end +$var reg 2 D[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 NU value $end +$var reg 4 '^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[212] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 lR adj_value $end +$var reg 2 E[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 OU value $end +$var reg 4 (^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[213] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 mR adj_value $end +$var reg 2 F[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 PU value $end +$var reg 4 )^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[214] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 nR adj_value $end +$var reg 2 G[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 QU value $end +$var reg 4 *^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[215] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 oR adj_value $end +$var reg 2 H[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 RU value $end +$var reg 4 +^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[216] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 pR adj_value $end +$var reg 2 I[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 SU value $end +$var reg 4 ,^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[217] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 qR adj_value $end +$var reg 2 J[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 TU value $end +$var reg 4 -^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[218] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 rR adj_value $end +$var reg 2 K[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 UU value $end +$var reg 4 .^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[219] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 sR adj_value $end +$var reg 2 L[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 VU value $end +$var reg 4 /^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[220] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 tR adj_value $end +$var reg 2 M[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 WU value $end +$var reg 4 0^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[221] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 uR adj_value $end +$var reg 2 N[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 XU value $end +$var reg 4 1^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[222] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 vR adj_value $end +$var reg 2 O[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 YU value $end +$var reg 4 2^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[223] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 wR adj_value $end +$var reg 2 P[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ZU value $end +$var reg 4 3^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[224] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 xR adj_value $end +$var reg 2 Q[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 [U value $end +$var reg 4 4^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[225] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 yR adj_value $end +$var reg 2 R[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 \U value $end +$var reg 4 5^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[226] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 zR adj_value $end +$var reg 2 S[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ]U value $end +$var reg 4 6^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[227] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 {R adj_value $end +$var reg 2 T[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ^U value $end +$var reg 4 7^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[228] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |R adj_value $end +$var reg 2 U[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _U value $end +$var reg 4 8^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[229] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }R adj_value $end +$var reg 2 V[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `U value $end +$var reg 4 9^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[230] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~R adj_value $end +$var reg 2 W[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 aU value $end +$var reg 4 :^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[231] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !S adj_value $end +$var reg 2 X[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 bU value $end +$var reg 4 ;^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[232] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "S adj_value $end +$var reg 2 Y[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 cU value $end +$var reg 4 <^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[233] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #S adj_value $end +$var reg 2 Z[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 dU value $end +$var reg 4 =^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[234] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $S adj_value $end +$var reg 2 [[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 eU value $end +$var reg 4 >^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[235] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %S adj_value $end +$var reg 2 \[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 fU value $end +$var reg 4 ?^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[236] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &S adj_value $end +$var reg 2 ][ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 gU value $end +$var reg 4 @^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[237] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 'S adj_value $end +$var reg 2 ^[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 hU value $end +$var reg 4 A^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[238] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (S adj_value $end +$var reg 2 _[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 iU value $end +$var reg 4 B^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[239] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )S adj_value $end +$var reg 2 `[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 jU value $end +$var reg 4 C^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[240] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *S adj_value $end +$var reg 2 a[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 kU value $end +$var reg 4 D^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[241] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +S adj_value $end +$var reg 2 b[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 lU value $end +$var reg 4 E^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[242] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,S adj_value $end +$var reg 2 c[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 mU value $end +$var reg 4 F^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[243] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -S adj_value $end +$var reg 2 d[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 nU value $end +$var reg 4 G^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[244] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .S adj_value $end +$var reg 2 e[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 oU value $end +$var reg 4 H^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[245] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /S adj_value $end +$var reg 2 f[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 pU value $end +$var reg 4 I^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[246] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 0S adj_value $end +$var reg 2 g[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 qU value $end +$var reg 4 J^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[247] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 1S adj_value $end +$var reg 2 h[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 rU value $end +$var reg 4 K^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[248] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 2S adj_value $end +$var reg 2 i[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 sU value $end +$var reg 4 L^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[249] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 3S adj_value $end +$var reg 2 j[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 tU value $end +$var reg 4 M^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[250] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 4S adj_value $end +$var reg 2 k[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 uU value $end +$var reg 4 N^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[251] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 5S adj_value $end +$var reg 2 l[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 vU value $end +$var reg 4 O^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[252] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 6S adj_value $end +$var reg 2 m[ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 wU value $end +$var reg 4 P^ value $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 8 |" addr $end -$var wire 1 }" en $end -$var wire 1 ~" clk $end +$var wire 8 }" addr $end +$var wire 1 ~" en $end +$var wire 1 !# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 !# adj_value $end +$var wire 2 "# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 "# value $end +$var wire 4 ## value $end $upscope $end $upscope $end $upscope $end $scope struct r1 $end -$var wire 8 ## addr $end -$var wire 1 $# en $end -$var wire 1 %# clk $end +$var wire 8 $# addr $end +$var wire 1 %# en $end +$var wire 1 &# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 &# adj_value $end +$var wire 2 '# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 '# value $end +$var wire 4 (# value $end $upscope $end $upscope $end $upscope $end $scope struct r2 $end -$var wire 8 (# addr $end -$var wire 1 )# en $end -$var wire 1 *# clk $end +$var wire 8 )# addr $end +$var wire 1 *# en $end +$var wire 1 +# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 +# adj_value $end +$var wire 2 ,# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 ,# value $end +$var wire 4 -# value $end $upscope $end $upscope $end $upscope $end $scope struct w3 $end -$var wire 8 -# addr $end -$var wire 1 .# en $end -$var wire 1 /# clk $end +$var wire 8 .# addr $end +$var wire 1 /# en $end +$var wire 1 0# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 0# adj_value $end +$var wire 2 1# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 1# value $end +$var wire 4 2# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 2# adj_value $end +$var wire 1 3# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 3# value $end +$var wire 1 4# value $end $upscope $end $upscope $end $upscope $end $scope struct w4 $end -$var wire 8 4# addr $end -$var wire 1 5# en $end -$var wire 1 6# clk $end +$var wire 8 5# addr $end +$var wire 1 6# en $end +$var wire 1 7# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 7# adj_value $end +$var wire 2 8# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 8# value $end +$var wire 4 9# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 9# adj_value $end +$var wire 1 :# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 :# value $end +$var wire 1 ;# value $end $upscope $end $upscope $end $upscope $end $scope struct r5 $end -$var wire 8 ;# addr $end -$var wire 1 <# en $end -$var wire 1 =# clk $end +$var wire 8 <# addr $end +$var wire 1 =# en $end +$var wire 1 ># clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 ># adj_value $end +$var wire 2 ?# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 ?# value $end +$var wire 4 @# value $end $upscope $end $upscope $end $upscope $end $scope struct r6 $end -$var wire 8 @# addr $end -$var wire 1 A# en $end -$var wire 1 B# clk $end +$var wire 8 A# addr $end +$var wire 1 B# en $end +$var wire 1 C# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 C# adj_value $end +$var wire 2 D# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 D# value $end +$var wire 4 E# value $end $upscope $end $upscope $end $upscope $end $scope struct r7 $end -$var wire 8 E# addr $end -$var wire 1 F# en $end -$var wire 1 G# clk $end +$var wire 8 F# addr $end +$var wire 1 G# en $end +$var wire 1 H# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 H# adj_value $end +$var wire 2 I# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 I# value $end +$var wire 4 J# value $end $upscope $end $upscope $end $upscope $end $scope struct w8 $end -$var wire 8 J# addr $end -$var wire 1 K# en $end -$var wire 1 L# clk $end +$var wire 8 K# addr $end +$var wire 1 L# en $end +$var wire 1 M# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 M# adj_value $end +$var wire 2 N# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 N# value $end +$var wire 4 O# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 O# adj_value $end +$var wire 1 P# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 P# value $end +$var wire 1 Q# value $end $upscope $end $upscope $end $upscope $end $scope struct w9 $end -$var wire 8 Q# addr $end -$var wire 1 R# en $end -$var wire 1 S# clk $end +$var wire 8 R# addr $end +$var wire 1 S# en $end +$var wire 1 T# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 T# adj_value $end +$var wire 2 U# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 U# value $end +$var wire 4 V# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 V# adj_value $end +$var wire 1 W# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 W# value $end +$var wire 1 X# value $end $upscope $end $upscope $end $upscope $end @@ -3296,602 +3305,597 @@ $scope struct contents $end $scope struct \[0] $end $scope struct rename_table_special_mem $end $scope struct unit_num $end -$var reg 2 xU adj_value $end +$var reg 2 Q^ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 zU value $end +$var reg 4 S^ value $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct rename_table_special_mem $end $scope struct unit_num $end -$var reg 2 yU adj_value $end +$var reg 2 R^ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {U value $end +$var reg 4 T^ value $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 1 X# addr $end -$var wire 1 Y# en $end -$var wire 1 Z# clk $end +$var wire 1 Y# addr $end +$var wire 1 Z# en $end +$var wire 1 [# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 [# adj_value $end +$var wire 2 \# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 \# value $end +$var wire 4 ]# value $end $upscope $end $upscope $end $upscope $end $scope struct r1 $end -$var wire 1 ]# addr $end -$var wire 1 ^# en $end -$var wire 1 _# clk $end +$var wire 1 ^# addr $end +$var wire 1 _# en $end +$var wire 1 `# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 `# adj_value $end +$var wire 2 a# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 a# value $end +$var wire 4 b# value $end $upscope $end $upscope $end $upscope $end $scope struct r2 $end -$var wire 1 b# addr $end -$var wire 1 c# en $end -$var wire 1 d# clk $end +$var wire 1 c# addr $end +$var wire 1 d# en $end +$var wire 1 e# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 e# adj_value $end +$var wire 2 f# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 f# value $end +$var wire 4 g# value $end $upscope $end $upscope $end $upscope $end $scope struct w3 $end -$var wire 1 g# addr $end -$var wire 1 h# en $end -$var wire 1 i# clk $end +$var wire 1 h# addr $end +$var wire 1 i# en $end +$var wire 1 j# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 j# adj_value $end +$var wire 2 k# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 k# value $end +$var wire 4 l# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 l# adj_value $end +$var wire 1 m# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 m# value $end +$var wire 1 n# value $end $upscope $end $upscope $end $upscope $end $scope struct w4 $end -$var wire 1 n# addr $end -$var wire 1 o# en $end -$var wire 1 p# clk $end +$var wire 1 o# addr $end +$var wire 1 p# en $end +$var wire 1 q# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 q# adj_value $end +$var wire 2 r# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 r# value $end +$var wire 4 s# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 s# adj_value $end +$var wire 1 t# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 t# value $end +$var wire 1 u# value $end $upscope $end $upscope $end $upscope $end $scope struct w5 $end -$var wire 1 u# addr $end -$var wire 1 v# en $end -$var wire 1 w# clk $end +$var wire 1 v# addr $end +$var wire 1 w# en $end +$var wire 1 x# clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 x# adj_value $end +$var wire 2 y# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 y# value $end +$var wire 4 z# value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 z# adj_value $end +$var wire 1 {# adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 {# value $end +$var wire 1 |# value $end $upscope $end $upscope $end $upscope $end $scope struct w6 $end -$var wire 1 |# addr $end -$var wire 1 }# en $end -$var wire 1 ~# clk $end +$var wire 1 }# addr $end +$var wire 1 ~# en $end +$var wire 1 !$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 !$ adj_value $end +$var wire 2 "$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 "$ value $end +$var wire 4 #$ value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 #$ adj_value $end +$var wire 1 $$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 $$ value $end +$var wire 1 %$ value $end $upscope $end $upscope $end $upscope $end $scope struct r7 $end -$var wire 1 %$ addr $end -$var wire 1 &$ en $end -$var wire 1 '$ clk $end +$var wire 1 &$ addr $end +$var wire 1 '$ en $end +$var wire 1 ($ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 ($ adj_value $end +$var wire 2 )$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 )$ value $end +$var wire 4 *$ value $end $upscope $end $upscope $end $upscope $end $scope struct r8 $end -$var wire 1 *$ addr $end -$var wire 1 +$ en $end -$var wire 1 ,$ clk $end +$var wire 1 +$ addr $end +$var wire 1 ,$ en $end +$var wire 1 -$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 -$ adj_value $end +$var wire 2 .$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 .$ value $end +$var wire 4 /$ value $end $upscope $end $upscope $end $upscope $end $scope struct r9 $end -$var wire 1 /$ addr $end -$var wire 1 0$ en $end -$var wire 1 1$ clk $end +$var wire 1 0$ addr $end +$var wire 1 1$ en $end +$var wire 1 2$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 2$ adj_value $end +$var wire 2 3$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 3$ value $end +$var wire 4 4$ value $end $upscope $end $upscope $end $upscope $end $scope struct w10 $end -$var wire 1 4$ addr $end -$var wire 1 5$ en $end -$var wire 1 6$ clk $end +$var wire 1 5$ addr $end +$var wire 1 6$ en $end +$var wire 1 7$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 7$ adj_value $end +$var wire 2 8$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 8$ value $end +$var wire 4 9$ value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 9$ adj_value $end +$var wire 1 :$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 :$ value $end +$var wire 1 ;$ value $end $upscope $end $upscope $end $upscope $end $scope struct w11 $end -$var wire 1 ;$ addr $end -$var wire 1 <$ en $end -$var wire 1 =$ clk $end +$var wire 1 <$ addr $end +$var wire 1 =$ en $end +$var wire 1 >$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 >$ adj_value $end +$var wire 2 ?$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 ?$ value $end +$var wire 4 @$ value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 @$ adj_value $end +$var wire 1 A$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 A$ value $end +$var wire 1 B$ value $end $upscope $end $upscope $end $upscope $end $scope struct w12 $end -$var wire 1 B$ addr $end -$var wire 1 C$ en $end -$var wire 1 D$ clk $end +$var wire 1 C$ addr $end +$var wire 1 D$ en $end +$var wire 1 E$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 E$ adj_value $end +$var wire 2 F$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 F$ value $end +$var wire 4 G$ value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 G$ adj_value $end +$var wire 1 H$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 H$ value $end +$var wire 1 I$ value $end $upscope $end $upscope $end $upscope $end $scope struct w13 $end -$var wire 1 I$ addr $end -$var wire 1 J$ en $end -$var wire 1 K$ clk $end +$var wire 1 J$ addr $end +$var wire 1 K$ en $end +$var wire 1 L$ clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 L$ adj_value $end +$var wire 2 M$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 M$ value $end +$var wire 4 N$ value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 N$ adj_value $end +$var wire 1 O$ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 O$ value $end +$var wire 1 P$ value $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct available_units $end $scope struct \[0] $end -$var wire 1 P$ \[0] $end -$var wire 1 Q$ \[1] $end +$var wire 1 Q$ \[0] $end +$var wire 1 R$ \[1] $end $upscope $end $scope struct \[1] $end -$var wire 1 R$ \[0] $end -$var wire 1 S$ \[1] $end +$var wire 1 S$ \[0] $end +$var wire 1 T$ \[1] $end $upscope $end $upscope $end $scope struct selected_unit_indexes $end $scope struct \[0] $end -$var string 1 T$ \$tag $end -$var wire 2 U$ HdlSome $end +$var string 1 U$ \$tag $end +$var wire 2 V$ HdlSome $end $upscope $end $scope struct \[1] $end -$var string 1 V$ \$tag $end -$var wire 2 W$ HdlSome $end +$var string 1 W$ \$tag $end +$var wire 2 X$ HdlSome $end $upscope $end $upscope $end $scope struct renamed_mops $end $scope struct \[0] $end -$var string 1 X$ \$tag $end -$scope struct HdlSome $end $var string 1 Y$ \$tag $end -$scope struct AluBranch $end +$scope struct HdlSome $end +$scope struct mop $end $var string 1 Z$ \$tag $end +$scope struct AluBranch $end +$var string 1 [$ \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 [$ prefix_pad $end +$var string 0 \$ prefix_pad $end $scope struct dest $end -$var wire 4 \$ value $end +$var wire 4 ]$ value $end $upscope $end $scope struct src $end -$var wire 6 ]$ \[0] $end -$var wire 6 ^$ \[1] $end -$var wire 6 _$ \[2] $end +$var wire 6 ^$ \[0] $end +$var wire 6 _$ \[1] $end +$var wire 6 `$ \[2] $end $upscope $end -$var wire 25 `$ imm_low $end -$var wire 1 a$ imm_sign $end +$var wire 25 a$ imm_low $end +$var wire 1 b$ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 b$ output_integer_mode $end +$var string 1 c$ output_integer_mode $end $upscope $end -$var wire 1 c$ invert_src0 $end -$var wire 1 d$ invert_carry_in $end -$var wire 1 e$ invert_carry_out $end -$var wire 1 f$ add_pc $end +$var wire 1 d$ invert_src0 $end +$var wire 1 e$ src1_is_carry_in $end +$var wire 1 f$ invert_carry_in $end +$var wire 1 g$ add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 g$ prefix_pad $end +$var string 0 h$ prefix_pad $end $scope struct dest $end -$var wire 4 h$ value $end +$var wire 4 i$ value $end $upscope $end $scope struct src $end -$var wire 6 i$ \[0] $end -$var wire 6 j$ \[1] $end -$var wire 6 k$ \[2] $end +$var wire 6 j$ \[0] $end +$var wire 6 k$ \[1] $end +$var wire 6 l$ \[2] $end $upscope $end -$var wire 25 l$ imm_low $end -$var wire 1 m$ imm_sign $end +$var wire 25 m$ imm_low $end +$var wire 1 n$ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 n$ output_integer_mode $end +$var string 1 o$ output_integer_mode $end $upscope $end -$var wire 1 o$ invert_src0 $end -$var wire 1 p$ invert_carry_in $end -$var wire 1 q$ invert_carry_out $end -$var wire 1 r$ add_pc $end +$var wire 1 p$ invert_src0 $end +$var wire 1 q$ src1_is_carry_in $end +$var wire 1 r$ invert_carry_in $end +$var wire 1 s$ add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 s$ prefix_pad $end +$var string 0 t$ prefix_pad $end $scope struct dest $end -$var wire 4 t$ value $end +$var wire 4 u$ value $end $upscope $end $scope struct src $end -$var wire 6 u$ \[0] $end -$var wire 6 v$ \[1] $end -$var wire 6 w$ \[2] $end +$var wire 6 v$ \[0] $end +$var wire 6 w$ \[1] $end +$var wire 6 x$ \[2] $end $upscope $end -$var wire 25 x$ imm_low $end -$var wire 1 y$ imm_sign $end +$var wire 25 y$ imm_low $end +$var wire 1 z$ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 z$ output_integer_mode $end +$var string 1 {$ output_integer_mode $end $upscope $end -$var wire 4 {$ lut $end +$var wire 4 |$ lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 |$ \$tag $end +$var string 1 }$ \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 }$ prefix_pad $end +$var wire 1 ~$ prefix_pad $end $scope struct dest $end -$var wire 4 ~$ value $end +$var wire 4 !% value $end $upscope $end $scope struct src $end -$var wire 6 !% \[0] $end -$var wire 6 "% \[1] $end -$var wire 6 #% \[2] $end +$var wire 6 "% \[0] $end +$var wire 6 #% \[1] $end +$var wire 6 $% \[2] $end $upscope $end -$var wire 25 $% imm_low $end -$var wire 1 %% imm_sign $end +$var wire 25 %% imm_low $end +$var wire 1 &% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 &% prefix_pad $end +$var wire 1 '% prefix_pad $end $scope struct dest $end -$var wire 4 '% value $end +$var wire 4 (% value $end $upscope $end $scope struct src $end -$var wire 6 (% \[0] $end -$var wire 6 )% \[1] $end -$var wire 6 *% \[2] $end +$var wire 6 )% \[0] $end +$var wire 6 *% \[1] $end +$var wire 6 +% \[2] $end $upscope $end -$var wire 25 +% imm_low $end -$var wire 1 ,% imm_sign $end +$var wire 25 ,% imm_low $end +$var wire 1 -% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct LoadStore $end -$var string 1 -% \$tag $end +$var string 1 .% \$tag $end $scope struct Load $end -$var wire 1 .% prefix_pad $end +$var wire 1 /% prefix_pad $end $scope struct dest $end -$var wire 4 /% value $end +$var wire 4 0% value $end $upscope $end $scope struct src $end -$var wire 6 0% \[0] $end -$var wire 6 1% \[1] $end -$var wire 6 2% \[2] $end +$var wire 6 1% \[0] $end +$var wire 6 2% \[1] $end +$var wire 6 3% \[2] $end $upscope $end -$var wire 25 3% imm_low $end -$var wire 1 4% imm_sign $end +$var wire 25 4% imm_low $end +$var wire 1 5% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 5% prefix_pad $end +$var wire 1 6% prefix_pad $end $scope struct dest $end -$var wire 4 6% value $end +$var wire 4 7% value $end $upscope $end $scope struct src $end -$var wire 6 7% \[0] $end -$var wire 6 8% \[1] $end -$var wire 6 9% \[2] $end +$var wire 6 8% \[0] $end +$var wire 6 9% \[1] $end +$var wire 6 :% \[2] $end $upscope $end -$var wire 25 :% imm_low $end -$var wire 1 ;% imm_sign $end +$var wire 25 ;% imm_low $end +$var wire 1 <% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end +$var wire 64 =% pc $end +$upscope $end $upscope $end $scope struct \[1] $end -$var string 1 <% \$tag $end -$scope struct HdlSome $end -$var string 1 =% \$tag $end -$scope struct AluBranch $end $var string 1 >% \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 ?% \$tag $end +$scope struct AluBranch $end +$var string 1 @% \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 ?% prefix_pad $end +$var string 0 A% prefix_pad $end $scope struct dest $end -$var wire 4 @% value $end +$var wire 4 B% value $end $upscope $end $scope struct src $end -$var wire 6 A% \[0] $end -$var wire 6 B% \[1] $end -$var wire 6 C% \[2] $end +$var wire 6 C% \[0] $end +$var wire 6 D% \[1] $end +$var wire 6 E% \[2] $end $upscope $end -$var wire 25 D% imm_low $end -$var wire 1 E% imm_sign $end +$var wire 25 F% imm_low $end +$var wire 1 G% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 F% output_integer_mode $end +$var string 1 H% output_integer_mode $end $upscope $end -$var wire 1 G% invert_src0 $end -$var wire 1 H% invert_carry_in $end -$var wire 1 I% invert_carry_out $end -$var wire 1 J% add_pc $end +$var wire 1 I% invert_src0 $end +$var wire 1 J% src1_is_carry_in $end +$var wire 1 K% invert_carry_in $end +$var wire 1 L% add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 K% prefix_pad $end +$var string 0 M% prefix_pad $end $scope struct dest $end -$var wire 4 L% value $end +$var wire 4 N% value $end $upscope $end $scope struct src $end -$var wire 6 M% \[0] $end -$var wire 6 N% \[1] $end -$var wire 6 O% \[2] $end +$var wire 6 O% \[0] $end +$var wire 6 P% \[1] $end +$var wire 6 Q% \[2] $end $upscope $end -$var wire 25 P% imm_low $end -$var wire 1 Q% imm_sign $end +$var wire 25 R% imm_low $end +$var wire 1 S% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 R% output_integer_mode $end +$var string 1 T% output_integer_mode $end $upscope $end -$var wire 1 S% invert_src0 $end -$var wire 1 T% invert_carry_in $end -$var wire 1 U% invert_carry_out $end -$var wire 1 V% add_pc $end +$var wire 1 U% invert_src0 $end +$var wire 1 V% src1_is_carry_in $end +$var wire 1 W% invert_carry_in $end +$var wire 1 X% add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 W% prefix_pad $end +$var string 0 Y% prefix_pad $end $scope struct dest $end -$var wire 4 X% value $end +$var wire 4 Z% value $end $upscope $end $scope struct src $end -$var wire 6 Y% \[0] $end -$var wire 6 Z% \[1] $end -$var wire 6 [% \[2] $end +$var wire 6 [% \[0] $end +$var wire 6 \% \[1] $end +$var wire 6 ]% \[2] $end $upscope $end -$var wire 25 \% imm_low $end -$var wire 1 ]% imm_sign $end +$var wire 25 ^% imm_low $end +$var wire 1 _% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 ^% output_integer_mode $end +$var string 1 `% output_integer_mode $end $upscope $end -$var wire 4 _% lut $end +$var wire 4 a% lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 `% \$tag $end +$var string 1 b% \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 a% prefix_pad $end +$var wire 1 c% prefix_pad $end $scope struct dest $end -$var wire 4 b% value $end +$var wire 4 d% value $end $upscope $end $scope struct src $end -$var wire 6 c% \[0] $end -$var wire 6 d% \[1] $end -$var wire 6 e% \[2] $end +$var wire 6 e% \[0] $end +$var wire 6 f% \[1] $end +$var wire 6 g% \[2] $end $upscope $end -$var wire 25 f% imm_low $end -$var wire 1 g% imm_sign $end +$var wire 25 h% imm_low $end +$var wire 1 i% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 h% prefix_pad $end +$var wire 1 j% prefix_pad $end $scope struct dest $end -$var wire 4 i% value $end +$var wire 4 k% value $end $upscope $end $scope struct src $end -$var wire 6 j% \[0] $end -$var wire 6 k% \[1] $end -$var wire 6 l% \[2] $end +$var wire 6 l% \[0] $end +$var wire 6 m% \[1] $end +$var wire 6 n% \[2] $end $upscope $end -$var wire 25 m% imm_low $end -$var wire 1 n% imm_sign $end +$var wire 25 o% imm_low $end +$var wire 1 p% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct LoadStore $end -$var string 1 o% \$tag $end +$var string 1 q% \$tag $end $scope struct Load $end -$var wire 1 p% prefix_pad $end +$var wire 1 r% prefix_pad $end $scope struct dest $end -$var wire 4 q% value $end +$var wire 4 s% value $end $upscope $end $scope struct src $end -$var wire 6 r% \[0] $end -$var wire 6 s% \[1] $end -$var wire 6 t% \[2] $end +$var wire 6 t% \[0] $end +$var wire 6 u% \[1] $end +$var wire 6 v% \[2] $end $upscope $end -$var wire 25 u% imm_low $end -$var wire 1 v% imm_sign $end +$var wire 25 w% imm_low $end +$var wire 1 x% imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 w% prefix_pad $end +$var wire 1 y% prefix_pad $end $scope struct dest $end -$var wire 4 x% value $end +$var wire 4 z% value $end $upscope $end $scope struct src $end -$var wire 6 y% \[0] $end -$var wire 6 z% \[1] $end -$var wire 6 {% \[2] $end +$var wire 6 {% \[0] $end +$var wire 6 |% \[1] $end +$var wire 6 }% \[2] $end $upscope $end -$var wire 25 |% imm_low $end -$var wire 1 }% imm_sign $end +$var wire 25 ~% imm_low $end +$var wire 1 !& imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end +$var wire 64 "& pc $end +$upscope $end $upscope $end $upscope $end $scope struct renamed_mops_out_reg $end $scope struct \[0] $end -$var string 1 ~% \$tag $end -$scope struct HdlSome $end -$scope struct unit_num $end -$var wire 2 !& adj_value $end -$upscope $end -$scope struct unit_out_reg $end -$var wire 4 "& value $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[1] $end $var string 1 #& \$tag $end $scope struct HdlSome $end $scope struct unit_num $end @@ -3902,12 +3906,9 @@ $var wire 4 %& value $end $upscope $end $upscope $end $upscope $end -$upscope $end -$scope struct rename_0_src_0 $end -$scope struct addr $end -$var wire 8 && value $end -$upscope $end -$scope struct data $end +$scope struct \[1] $end +$var string 1 && \$tag $end +$scope struct HdlSome $end $scope struct unit_num $end $var wire 2 '& adj_value $end $upscope $end @@ -3916,7 +3917,8 @@ $var wire 4 (& value $end $upscope $end $upscope $end $upscope $end -$scope struct rename_0_src_1 $end +$upscope $end +$scope struct rename_0_src_0 $end $scope struct addr $end $var wire 8 )& value $end $upscope $end @@ -3929,7 +3931,7 @@ $var wire 4 +& value $end $upscope $end $upscope $end $upscope $end -$scope struct rename_0_src_2 $end +$scope struct rename_0_src_1 $end $scope struct addr $end $var wire 8 ,& value $end $upscope $end @@ -3942,154 +3944,167 @@ $var wire 4 .& value $end $upscope $end $upscope $end $upscope $end -$scope struct rename_table_normal_0_dest0 $end -$var wire 8 /& addr $end -$var wire 1 0& en $end -$var wire 1 1& clk $end +$scope struct rename_0_src_2 $end +$scope struct addr $end +$var wire 8 /& value $end +$upscope $end $scope struct data $end $scope struct unit_num $end -$var wire 2 2& adj_value $end +$var wire 2 0& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 3& value $end +$var wire 4 1& value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rename_table_normal_0_dest0 $end +$var wire 8 2& addr $end +$var wire 1 3& en $end +$var wire 1 4& clk $end +$scope struct data $end +$scope struct unit_num $end +$var wire 2 5& adj_value $end +$upscope $end +$scope struct unit_out_reg $end +$var wire 4 6& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 4& adj_value $end +$var wire 1 7& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 5& value $end +$var wire 1 8& value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_0_dest0 $end -$var wire 1 6& addr $end -$var wire 1 7& en $end -$var wire 1 8& clk $end +$var wire 1 9& addr $end +$var wire 1 :& en $end +$var wire 1 ;& clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 9& adj_value $end +$var wire 2 <& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 :& value $end +$var wire 4 =& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 ;& adj_value $end +$var wire 1 >& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 <& value $end +$var wire 1 ?& value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_normal_0_dest1 $end -$var wire 8 =& addr $end -$var wire 1 >& en $end -$var wire 1 ?& clk $end +$var wire 8 @& addr $end +$var wire 1 A& en $end +$var wire 1 B& clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 @& adj_value $end +$var wire 2 C& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 A& value $end +$var wire 4 D& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 B& adj_value $end +$var wire 1 E& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 C& value $end +$var wire 1 F& value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_0_dest1 $end -$var wire 1 D& addr $end -$var wire 1 E& en $end -$var wire 1 F& clk $end +$var wire 1 G& addr $end +$var wire 1 H& en $end +$var wire 1 I& clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 G& adj_value $end +$var wire 2 J& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 H& value $end +$var wire 4 K& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 I& adj_value $end +$var wire 1 L& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 J& value $end +$var wire 1 M& value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_0_flag0_rFE $end -$var wire 1 K& addr $end -$var wire 1 L& en $end -$var wire 1 M& clk $end +$var wire 1 N& addr $end +$var wire 1 O& en $end +$var wire 1 P& clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 N& adj_value $end +$var wire 2 Q& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 O& value $end +$var wire 4 R& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 P& adj_value $end +$var wire 1 S& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 Q& value $end +$var wire 1 T& value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_0_flag1_rFF $end -$var wire 1 R& addr $end -$var wire 1 S& en $end -$var wire 1 T& clk $end +$var wire 1 U& addr $end +$var wire 1 V& en $end +$var wire 1 W& clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 U& adj_value $end +$var wire 2 X& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 V& value $end +$var wire 4 Y& value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 W& adj_value $end +$var wire 1 Z& adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 X& value $end +$var wire 1 [& value $end $upscope $end $upscope $end $upscope $end -$var string 1 Y& unit_kind $end +$var string 1 \& unit_kind $end $scope struct available_units_for_kind $end -$var wire 1 Z& \[0] $end -$var wire 1 [& \[1] $end +$var wire 1 ]& \[0] $end +$var wire 1 ^& \[1] $end $upscope $end $scope struct dest_reg $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 \& value $end +$var wire 8 _& value $end $upscope $end $scope struct \[1] $end -$var wire 8 ]& value $end +$var wire 8 `& value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 ^& \$tag $end +$var string 1 a& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 _& \$tag $end +$var string 1 b& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4098,20 +4113,20 @@ $upscope $end $scope struct dest_reg_2 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 `& value $end +$var wire 8 c& value $end $upscope $end $scope struct \[1] $end -$var wire 8 a& value $end +$var wire 8 d& value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 b& \$tag $end +$var string 1 e& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 c& \$tag $end +$var string 1 f& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4120,20 +4135,20 @@ $upscope $end $scope struct dest_reg_3 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 d& value $end +$var wire 8 g& value $end $upscope $end $scope struct \[1] $end -$var wire 8 e& value $end +$var wire 8 h& value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 f& \$tag $end +$var string 1 i& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 g& \$tag $end +$var string 1 j& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4142,362 +4157,362 @@ $upscope $end $scope struct dest_reg_4 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 h& value $end +$var wire 8 k& value $end $upscope $end $scope struct \[1] $end -$var wire 8 i& value $end +$var wire 8 l& value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 j& \$tag $end +$var string 1 m& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 k& \$tag $end +$var string 1 n& \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs $end -$var string 1 l& \$tag $end +$var string 1 o& \$tag $end $scope struct AluBranch $end -$var string 1 m& \$tag $end +$var string 1 p& \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 n& prefix_pad $end +$var string 0 q& prefix_pad $end $scope struct dest $end -$var wire 4 o& value $end +$var wire 4 r& value $end $upscope $end $scope struct src $end -$var wire 6 p& \[0] $end -$var wire 6 q& \[1] $end -$var wire 6 r& \[2] $end +$var wire 6 s& \[0] $end +$var wire 6 t& \[1] $end +$var wire 6 u& \[2] $end $upscope $end -$var wire 25 s& imm_low $end -$var wire 1 t& imm_sign $end +$var wire 25 v& imm_low $end +$var wire 1 w& imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 u& output_integer_mode $end +$var string 1 x& output_integer_mode $end $upscope $end -$var wire 1 v& invert_src0 $end -$var wire 1 w& invert_carry_in $end -$var wire 1 x& invert_carry_out $end -$var wire 1 y& add_pc $end +$var wire 1 y& invert_src0 $end +$var wire 1 z& src1_is_carry_in $end +$var wire 1 {& invert_carry_in $end +$var wire 1 |& add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 z& prefix_pad $end +$var string 0 }& prefix_pad $end $scope struct dest $end -$var wire 4 {& value $end +$var wire 4 ~& value $end $upscope $end $scope struct src $end -$var wire 6 |& \[0] $end -$var wire 6 }& \[1] $end -$var wire 6 ~& \[2] $end +$var wire 6 !' \[0] $end +$var wire 6 "' \[1] $end +$var wire 6 #' \[2] $end $upscope $end -$var wire 25 !' imm_low $end -$var wire 1 "' imm_sign $end +$var wire 25 $' imm_low $end +$var wire 1 %' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 #' output_integer_mode $end +$var string 1 &' output_integer_mode $end $upscope $end -$var wire 1 $' invert_src0 $end -$var wire 1 %' invert_carry_in $end -$var wire 1 &' invert_carry_out $end -$var wire 1 '' add_pc $end +$var wire 1 '' invert_src0 $end +$var wire 1 (' src1_is_carry_in $end +$var wire 1 )' invert_carry_in $end +$var wire 1 *' add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 (' prefix_pad $end +$var string 0 +' prefix_pad $end $scope struct dest $end -$var wire 4 )' value $end +$var wire 4 ,' value $end $upscope $end $scope struct src $end -$var wire 6 *' \[0] $end -$var wire 6 +' \[1] $end -$var wire 6 ,' \[2] $end +$var wire 6 -' \[0] $end +$var wire 6 .' \[1] $end +$var wire 6 /' \[2] $end $upscope $end -$var wire 25 -' imm_low $end -$var wire 1 .' imm_sign $end +$var wire 25 0' imm_low $end +$var wire 1 1' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 /' output_integer_mode $end +$var string 1 2' output_integer_mode $end $upscope $end -$var wire 4 0' lut $end +$var wire 4 3' lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 1' \$tag $end +$var string 1 4' \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 2' prefix_pad $end +$var wire 1 5' prefix_pad $end $scope struct dest $end -$var wire 4 3' value $end +$var wire 4 6' value $end $upscope $end $scope struct src $end -$var wire 6 4' \[0] $end -$var wire 6 5' \[1] $end -$var wire 6 6' \[2] $end +$var wire 6 7' \[0] $end +$var wire 6 8' \[1] $end +$var wire 6 9' \[2] $end $upscope $end -$var wire 25 7' imm_low $end -$var wire 1 8' imm_sign $end +$var wire 25 :' imm_low $end +$var wire 1 ;' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 9' prefix_pad $end +$var wire 1 <' prefix_pad $end $scope struct dest $end -$var wire 4 :' value $end +$var wire 4 =' value $end $upscope $end $scope struct src $end -$var wire 6 ;' \[0] $end -$var wire 6 <' \[1] $end -$var wire 6 =' \[2] $end +$var wire 6 >' \[0] $end +$var wire 6 ?' \[1] $end +$var wire 6 @' \[2] $end $upscope $end -$var wire 25 >' imm_low $end -$var wire 1 ?' imm_sign $end +$var wire 25 A' imm_low $end +$var wire 1 B' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct LoadStore $end -$var string 1 @' \$tag $end +$var string 1 C' \$tag $end $scope struct Load $end -$var wire 1 A' prefix_pad $end +$var wire 1 D' prefix_pad $end $scope struct dest $end -$var wire 4 B' value $end +$var wire 4 E' value $end $upscope $end $scope struct src $end -$var wire 6 C' \[0] $end -$var wire 6 D' \[1] $end -$var wire 6 E' \[2] $end +$var wire 6 F' \[0] $end +$var wire 6 G' \[1] $end +$var wire 6 H' \[2] $end $upscope $end -$var wire 25 F' imm_low $end -$var wire 1 G' imm_sign $end +$var wire 25 I' imm_low $end +$var wire 1 J' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 H' prefix_pad $end +$var wire 1 K' prefix_pad $end $scope struct dest $end -$var wire 4 I' value $end +$var wire 4 L' value $end $upscope $end $scope struct src $end -$var wire 6 J' \[0] $end -$var wire 6 K' \[1] $end -$var wire 6 L' \[2] $end +$var wire 6 M' \[0] $end +$var wire 6 N' \[1] $end +$var wire 6 O' \[2] $end $upscope $end -$var wire 25 M' imm_low $end -$var wire 1 N' imm_sign $end +$var wire 25 P' imm_low $end +$var wire 1 Q' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs_2 $end -$var string 1 O' \$tag $end +$var string 1 R' \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 P' prefix_pad $end +$var string 0 S' prefix_pad $end $scope struct dest $end -$var wire 4 Q' value $end +$var wire 4 T' value $end $upscope $end $scope struct src $end -$var wire 6 R' \[0] $end -$var wire 6 S' \[1] $end -$var wire 6 T' \[2] $end +$var wire 6 U' \[0] $end +$var wire 6 V' \[1] $end +$var wire 6 W' \[2] $end $upscope $end -$var wire 25 U' imm_low $end -$var wire 1 V' imm_sign $end +$var wire 25 X' imm_low $end +$var wire 1 Y' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 W' output_integer_mode $end +$var string 1 Z' output_integer_mode $end $upscope $end -$var wire 1 X' invert_src0 $end -$var wire 1 Y' invert_carry_in $end -$var wire 1 Z' invert_carry_out $end -$var wire 1 [' add_pc $end +$var wire 1 [' invert_src0 $end +$var wire 1 \' src1_is_carry_in $end +$var wire 1 ]' invert_carry_in $end +$var wire 1 ^' add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 \' prefix_pad $end +$var string 0 _' prefix_pad $end $scope struct dest $end -$var wire 4 ]' value $end +$var wire 4 `' value $end $upscope $end $scope struct src $end -$var wire 6 ^' \[0] $end -$var wire 6 _' \[1] $end -$var wire 6 `' \[2] $end +$var wire 6 a' \[0] $end +$var wire 6 b' \[1] $end +$var wire 6 c' \[2] $end $upscope $end -$var wire 25 a' imm_low $end -$var wire 1 b' imm_sign $end +$var wire 25 d' imm_low $end +$var wire 1 e' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 c' output_integer_mode $end +$var string 1 f' output_integer_mode $end $upscope $end -$var wire 1 d' invert_src0 $end -$var wire 1 e' invert_carry_in $end -$var wire 1 f' invert_carry_out $end -$var wire 1 g' add_pc $end +$var wire 1 g' invert_src0 $end +$var wire 1 h' src1_is_carry_in $end +$var wire 1 i' invert_carry_in $end +$var wire 1 j' add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 h' prefix_pad $end +$var string 0 k' prefix_pad $end $scope struct dest $end -$var wire 4 i' value $end +$var wire 4 l' value $end $upscope $end $scope struct src $end -$var wire 6 j' \[0] $end -$var wire 6 k' \[1] $end -$var wire 6 l' \[2] $end +$var wire 6 m' \[0] $end +$var wire 6 n' \[1] $end +$var wire 6 o' \[2] $end $upscope $end -$var wire 25 m' imm_low $end -$var wire 1 n' imm_sign $end +$var wire 25 p' imm_low $end +$var wire 1 q' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 o' output_integer_mode $end +$var string 1 r' output_integer_mode $end $upscope $end -$var wire 4 p' lut $end +$var wire 4 s' lut $end $upscope $end $upscope $end $scope struct mapped_regs_3 $end -$var string 1 q' \$tag $end +$var string 1 t' \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 r' prefix_pad $end +$var wire 1 u' prefix_pad $end $scope struct dest $end -$var wire 4 s' value $end +$var wire 4 v' value $end $upscope $end $scope struct src $end -$var wire 6 t' \[0] $end -$var wire 6 u' \[1] $end -$var wire 6 v' \[2] $end +$var wire 6 w' \[0] $end +$var wire 6 x' \[1] $end +$var wire 6 y' \[2] $end $upscope $end -$var wire 25 w' imm_low $end -$var wire 1 x' imm_sign $end +$var wire 25 z' imm_low $end +$var wire 1 {' imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 y' prefix_pad $end +$var wire 1 |' prefix_pad $end $scope struct dest $end -$var wire 4 z' value $end +$var wire 4 }' value $end $upscope $end $scope struct src $end -$var wire 6 {' \[0] $end -$var wire 6 |' \[1] $end -$var wire 6 }' \[2] $end +$var wire 6 ~' \[0] $end +$var wire 6 !( \[1] $end +$var wire 6 "( \[2] $end $upscope $end -$var wire 25 ~' imm_low $end -$var wire 1 !( imm_sign $end +$var wire 25 #( imm_low $end +$var wire 1 $( imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs_4 $end -$var string 1 "( \$tag $end +$var string 1 %( \$tag $end $scope struct Load $end -$var wire 1 #( prefix_pad $end +$var wire 1 &( prefix_pad $end $scope struct dest $end -$var wire 4 $( value $end +$var wire 4 '( value $end $upscope $end $scope struct src $end -$var wire 6 %( \[0] $end -$var wire 6 &( \[1] $end -$var wire 6 '( \[2] $end +$var wire 6 (( \[0] $end +$var wire 6 )( \[1] $end +$var wire 6 *( \[2] $end $upscope $end -$var wire 25 (( imm_low $end -$var wire 1 )( imm_sign $end +$var wire 25 +( imm_low $end +$var wire 1 ,( imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 *( prefix_pad $end +$var wire 1 -( prefix_pad $end $scope struct dest $end -$var wire 4 +( value $end +$var wire 4 .( value $end $upscope $end $scope struct src $end -$var wire 6 ,( \[0] $end -$var wire 6 -( \[1] $end -$var wire 6 .( \[2] $end +$var wire 6 /( \[0] $end +$var wire 6 0( \[1] $end +$var wire 6 1( \[2] $end $upscope $end -$var wire 25 /( imm_low $end -$var wire 1 0( imm_sign $end +$var wire 25 2( imm_low $end +$var wire 1 3( imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg $end -$var wire 8 1( value $end +$var wire 8 4( value $end $upscope $end $scope struct flag_reg_2 $end -$var wire 8 2( value $end +$var wire 8 5( value $end $upscope $end $scope struct selected_unit_index_leaf_0_0 $end -$var string 1 3( \$tag $end -$var wire 2 4( HdlSome $end -$upscope $end -$var wire 2 5( unit_index_0_0 $end -$scope struct selected_unit_index_leaf_0_1 $end $var string 1 6( \$tag $end $var wire 2 7( HdlSome $end $upscope $end -$var wire 2 8( unit_index_0_1 $end -$scope struct selected_unit_index_node_0_0 $end +$var wire 2 8( unit_index_0_0 $end +$scope struct selected_unit_index_leaf_0_1 $end $var string 1 9( \$tag $end $var wire 2 :( HdlSome $end $upscope $end +$var wire 2 ;( unit_index_0_1 $end +$scope struct selected_unit_index_node_0_0 $end +$var string 1 <( \$tag $end +$var wire 2 =( HdlSome $end +$upscope $end $scope struct rename_1_src_0 $end $scope struct addr $end -$var wire 8 ;( value $end +$var wire 8 >( value $end $upscope $end $scope struct data $end $scope struct unit_num $end -$var wire 2 <( adj_value $end +$var wire 2 ?( adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 =( value $end +$var wire 4 @( value $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_5 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 >( value $end +$var wire 8 A( value $end $upscope $end $scope struct \[1] $end -$var wire 8 ?( value $end +$var wire 8 B( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 @( \$tag $end +$var string 1 C( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 A( \$tag $end +$var string 1 D( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4506,20 +4521,20 @@ $upscope $end $scope struct dest_reg_6 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 B( value $end +$var wire 8 E( value $end $upscope $end $scope struct \[1] $end -$var wire 8 C( value $end +$var wire 8 F( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 D( \$tag $end +$var string 1 G( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 E( \$tag $end +$var string 1 H( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4528,20 +4543,20 @@ $upscope $end $scope struct dest_reg_7 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 F( value $end +$var wire 8 I( value $end $upscope $end $scope struct \[1] $end -$var wire 8 G( value $end +$var wire 8 J( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 H( \$tag $end +$var string 1 K( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 I( \$tag $end +$var string 1 L( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4550,48 +4565,48 @@ $upscope $end $scope struct dest_reg_8 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 J( value $end +$var wire 8 M( value $end $upscope $end $scope struct \[1] $end -$var wire 8 K( value $end +$var wire 8 N( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 L( \$tag $end +$var string 1 O( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 M( \$tag $end +$var string 1 P( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_3 $end -$var wire 8 N( value $end +$var wire 8 Q( value $end $upscope $end $scope struct flag_reg_4 $end -$var wire 8 O( value $end +$var wire 8 R( value $end $upscope $end $scope struct dest_reg_9 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 P( value $end +$var wire 8 S( value $end $upscope $end $scope struct \[1] $end -$var wire 8 Q( value $end +$var wire 8 T( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 R( \$tag $end +$var string 1 U( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 S( \$tag $end +$var string 1 V( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4600,20 +4615,20 @@ $upscope $end $scope struct dest_reg_10 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 T( value $end +$var wire 8 W( value $end $upscope $end $scope struct \[1] $end -$var wire 8 U( value $end +$var wire 8 X( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 V( \$tag $end +$var string 1 Y( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 W( \$tag $end +$var string 1 Z( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4622,20 +4637,20 @@ $upscope $end $scope struct dest_reg_11 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 X( value $end +$var wire 8 [( value $end $upscope $end $scope struct \[1] $end -$var wire 8 Y( value $end +$var wire 8 \( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 Z( \$tag $end +$var string 1 ]( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 [( \$tag $end +$var string 1 ^( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4644,61 +4659,61 @@ $upscope $end $scope struct dest_reg_12 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 \( value $end +$var wire 8 _( value $end $upscope $end $scope struct \[1] $end -$var wire 8 ]( value $end +$var wire 8 `( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 ^( \$tag $end +$var string 1 a( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 _( \$tag $end +$var string 1 b( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_5 $end -$var wire 8 `( value $end +$var wire 8 c( value $end $upscope $end $scope struct flag_reg_6 $end -$var wire 8 a( value $end +$var wire 8 d( value $end $upscope $end $scope struct rename_1_src_1 $end $scope struct addr $end -$var wire 8 b( value $end +$var wire 8 e( value $end $upscope $end $scope struct data $end $scope struct unit_num $end -$var wire 2 c( adj_value $end +$var wire 2 f( adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 d( value $end +$var wire 4 g( value $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_13 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 e( value $end +$var wire 8 h( value $end $upscope $end $scope struct \[1] $end -$var wire 8 f( value $end +$var wire 8 i( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 g( \$tag $end +$var string 1 j( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 h( \$tag $end +$var string 1 k( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4707,20 +4722,20 @@ $upscope $end $scope struct dest_reg_14 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 i( value $end +$var wire 8 l( value $end $upscope $end $scope struct \[1] $end -$var wire 8 j( value $end +$var wire 8 m( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 k( \$tag $end +$var string 1 n( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 l( \$tag $end +$var string 1 o( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4729,20 +4744,20 @@ $upscope $end $scope struct dest_reg_15 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 m( value $end +$var wire 8 p( value $end $upscope $end $scope struct \[1] $end -$var wire 8 n( value $end +$var wire 8 q( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 o( \$tag $end +$var string 1 r( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 p( \$tag $end +$var string 1 s( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4751,48 +4766,48 @@ $upscope $end $scope struct dest_reg_16 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 q( value $end +$var wire 8 t( value $end $upscope $end $scope struct \[1] $end -$var wire 8 r( value $end +$var wire 8 u( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 s( \$tag $end +$var string 1 v( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 t( \$tag $end +$var string 1 w( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_7 $end -$var wire 8 u( value $end +$var wire 8 x( value $end $upscope $end $scope struct flag_reg_8 $end -$var wire 8 v( value $end +$var wire 8 y( value $end $upscope $end $scope struct dest_reg_17 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 w( value $end +$var wire 8 z( value $end $upscope $end $scope struct \[1] $end -$var wire 8 x( value $end +$var wire 8 {( value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 y( \$tag $end +$var string 1 |( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 z( \$tag $end +$var string 1 }( \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4801,20 +4816,20 @@ $upscope $end $scope struct dest_reg_18 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 {( value $end +$var wire 8 ~( value $end $upscope $end $scope struct \[1] $end -$var wire 8 |( value $end +$var wire 8 !) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 }( \$tag $end +$var string 1 ") \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 ~( \$tag $end +$var string 1 #) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4823,20 +4838,20 @@ $upscope $end $scope struct dest_reg_19 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 !) value $end +$var wire 8 $) value $end $upscope $end $scope struct \[1] $end -$var wire 8 ") value $end +$var wire 8 %) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 #) \$tag $end +$var string 1 &) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 $) \$tag $end +$var string 1 ') \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4845,61 +4860,61 @@ $upscope $end $scope struct dest_reg_20 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 %) value $end +$var wire 8 () value $end $upscope $end $scope struct \[1] $end -$var wire 8 &) value $end +$var wire 8 )) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 ') \$tag $end +$var string 1 *) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 () \$tag $end +$var string 1 +) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_9 $end -$var wire 8 )) value $end +$var wire 8 ,) value $end $upscope $end $scope struct flag_reg_10 $end -$var wire 8 *) value $end +$var wire 8 -) value $end $upscope $end $scope struct rename_1_src_2 $end $scope struct addr $end -$var wire 8 +) value $end +$var wire 8 .) value $end $upscope $end $scope struct data $end $scope struct unit_num $end -$var wire 2 ,) adj_value $end +$var wire 2 /) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 -) value $end +$var wire 4 0) value $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_21 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 .) value $end +$var wire 8 1) value $end $upscope $end $scope struct \[1] $end -$var wire 8 /) value $end +$var wire 8 2) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 0) \$tag $end +$var string 1 3) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 1) \$tag $end +$var string 1 4) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4908,20 +4923,20 @@ $upscope $end $scope struct dest_reg_22 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 2) value $end +$var wire 8 5) value $end $upscope $end $scope struct \[1] $end -$var wire 8 3) value $end +$var wire 8 6) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 4) \$tag $end +$var string 1 7) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 5) \$tag $end +$var string 1 8) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4930,20 +4945,20 @@ $upscope $end $scope struct dest_reg_23 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 6) value $end +$var wire 8 9) value $end $upscope $end $scope struct \[1] $end -$var wire 8 7) value $end +$var wire 8 :) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 8) \$tag $end +$var string 1 ;) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 9) \$tag $end +$var string 1 <) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -4952,48 +4967,48 @@ $upscope $end $scope struct dest_reg_24 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 :) value $end +$var wire 8 =) value $end $upscope $end $scope struct \[1] $end -$var wire 8 ;) value $end +$var wire 8 >) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 <) \$tag $end +$var string 1 ?) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 =) \$tag $end +$var string 1 @) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_11 $end -$var wire 8 >) value $end +$var wire 8 A) value $end $upscope $end $scope struct flag_reg_12 $end -$var wire 8 ?) value $end +$var wire 8 B) value $end $upscope $end $scope struct dest_reg_25 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 @) value $end +$var wire 8 C) value $end $upscope $end $scope struct \[1] $end -$var wire 8 A) value $end +$var wire 8 D) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 B) \$tag $end +$var string 1 E) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 C) \$tag $end +$var string 1 F) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5002,20 +5017,20 @@ $upscope $end $scope struct dest_reg_26 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 D) value $end +$var wire 8 G) value $end $upscope $end $scope struct \[1] $end -$var wire 8 E) value $end +$var wire 8 H) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 F) \$tag $end +$var string 1 I) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 G) \$tag $end +$var string 1 J) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5024,20 +5039,20 @@ $upscope $end $scope struct dest_reg_27 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 H) value $end +$var wire 8 K) value $end $upscope $end $scope struct \[1] $end -$var wire 8 I) value $end +$var wire 8 L) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 J) \$tag $end +$var string 1 M) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 K) \$tag $end +$var string 1 N) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5046,179 +5061,179 @@ $upscope $end $scope struct dest_reg_28 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 L) value $end +$var wire 8 O) value $end $upscope $end $scope struct \[1] $end -$var wire 8 M) value $end +$var wire 8 P) value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 N) \$tag $end +$var string 1 Q) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 O) \$tag $end +$var string 1 R) \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_13 $end -$var wire 8 P) value $end +$var wire 8 S) value $end $upscope $end $scope struct flag_reg_14 $end -$var wire 8 Q) value $end +$var wire 8 T) value $end $upscope $end $scope struct rename_table_normal_1_dest0 $end -$var wire 8 R) addr $end -$var wire 1 S) en $end -$var wire 1 T) clk $end +$var wire 8 U) addr $end +$var wire 1 V) en $end +$var wire 1 W) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 U) adj_value $end +$var wire 2 X) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 V) value $end +$var wire 4 Y) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 W) adj_value $end +$var wire 1 Z) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 X) value $end +$var wire 1 [) value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_1_dest0 $end -$var wire 1 Y) addr $end -$var wire 1 Z) en $end -$var wire 1 [) clk $end +$var wire 1 \) addr $end +$var wire 1 ]) en $end +$var wire 1 ^) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 \) adj_value $end +$var wire 2 _) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 ]) value $end +$var wire 4 `) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 ^) adj_value $end +$var wire 1 a) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 _) value $end +$var wire 1 b) value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_normal_1_dest1 $end -$var wire 8 `) addr $end -$var wire 1 a) en $end -$var wire 1 b) clk $end +$var wire 8 c) addr $end +$var wire 1 d) en $end +$var wire 1 e) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 c) adj_value $end +$var wire 2 f) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 d) value $end +$var wire 4 g) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 e) adj_value $end +$var wire 1 h) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 f) value $end +$var wire 1 i) value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_1_dest1 $end -$var wire 1 g) addr $end -$var wire 1 h) en $end -$var wire 1 i) clk $end +$var wire 1 j) addr $end +$var wire 1 k) en $end +$var wire 1 l) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 j) adj_value $end +$var wire 2 m) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 k) value $end +$var wire 4 n) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 l) adj_value $end +$var wire 1 o) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 m) value $end +$var wire 1 p) value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_1_flag0_rFE $end -$var wire 1 n) addr $end -$var wire 1 o) en $end -$var wire 1 p) clk $end +$var wire 1 q) addr $end +$var wire 1 r) en $end +$var wire 1 s) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 q) adj_value $end +$var wire 2 t) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 r) value $end +$var wire 4 u) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 s) adj_value $end +$var wire 1 v) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 t) value $end +$var wire 1 w) value $end $upscope $end $upscope $end $upscope $end $scope struct rename_table_special_1_flag1_rFF $end -$var wire 1 u) addr $end -$var wire 1 v) en $end -$var wire 1 w) clk $end +$var wire 1 x) addr $end +$var wire 1 y) en $end +$var wire 1 z) clk $end $scope struct data $end $scope struct unit_num $end -$var wire 2 x) adj_value $end +$var wire 2 {) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 4 y) value $end +$var wire 4 |) value $end $upscope $end $upscope $end $scope struct mask $end $scope struct unit_num $end -$var wire 1 z) adj_value $end +$var wire 1 }) adj_value $end $upscope $end $scope struct unit_out_reg $end -$var wire 1 {) value $end +$var wire 1 ~) value $end $upscope $end $upscope $end $upscope $end -$var string 1 |) unit_kind_2 $end +$var string 1 !* unit_kind_2 $end $scope struct available_units_for_kind_2 $end -$var wire 1 }) \[0] $end -$var wire 1 ~) \[1] $end +$var wire 1 "* \[0] $end +$var wire 1 #* \[1] $end $upscope $end $scope struct dest_reg_29 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 !* value $end +$var wire 8 $* value $end $upscope $end $scope struct \[1] $end -$var wire 8 "* value $end +$var wire 8 %* value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 #* \$tag $end +$var string 1 &* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 $* \$tag $end +$var string 1 '* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5227,20 +5242,20 @@ $upscope $end $scope struct dest_reg_30 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 %* value $end +$var wire 8 (* value $end $upscope $end $scope struct \[1] $end -$var wire 8 &* value $end +$var wire 8 )* value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 '* \$tag $end +$var string 1 ** \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 (* \$tag $end +$var string 1 +* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5249,20 +5264,20 @@ $upscope $end $scope struct dest_reg_31 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 )* value $end +$var wire 8 ,* value $end $upscope $end $scope struct \[1] $end -$var wire 8 ** value $end +$var wire 8 -* value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 +* \$tag $end +$var string 1 .* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 ,* \$tag $end +$var string 1 /* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end @@ -5271,378 +5286,372 @@ $upscope $end $scope struct dest_reg_32 $end $scope struct normal_regs $end $scope struct \[0] $end -$var wire 8 -* value $end +$var wire 8 0* value $end $upscope $end $scope struct \[1] $end -$var wire 8 .* value $end +$var wire 8 1* value $end $upscope $end $upscope $end $scope struct flag_regs $end $scope struct \[0] $end -$var string 1 /* \$tag $end +$var string 1 2* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 0* \$tag $end +$var string 1 3* \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs_5 $end -$var string 1 1* \$tag $end +$var string 1 4* \$tag $end $scope struct AluBranch $end -$var string 1 2* \$tag $end +$var string 1 5* \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 3* prefix_pad $end +$var string 0 6* prefix_pad $end $scope struct dest $end -$var wire 4 4* value $end +$var wire 4 7* value $end $upscope $end $scope struct src $end -$var wire 6 5* \[0] $end -$var wire 6 6* \[1] $end -$var wire 6 7* \[2] $end +$var wire 6 8* \[0] $end +$var wire 6 9* \[1] $end +$var wire 6 :* \[2] $end $upscope $end -$var wire 25 8* imm_low $end -$var wire 1 9* imm_sign $end +$var wire 25 ;* imm_low $end +$var wire 1 <* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 :* output_integer_mode $end +$var string 1 =* output_integer_mode $end $upscope $end -$var wire 1 ;* invert_src0 $end -$var wire 1 <* invert_carry_in $end -$var wire 1 =* invert_carry_out $end -$var wire 1 >* add_pc $end +$var wire 1 >* invert_src0 $end +$var wire 1 ?* src1_is_carry_in $end +$var wire 1 @* invert_carry_in $end +$var wire 1 A* add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 ?* prefix_pad $end +$var string 0 B* prefix_pad $end $scope struct dest $end -$var wire 4 @* value $end +$var wire 4 C* value $end $upscope $end $scope struct src $end -$var wire 6 A* \[0] $end -$var wire 6 B* \[1] $end -$var wire 6 C* \[2] $end +$var wire 6 D* \[0] $end +$var wire 6 E* \[1] $end +$var wire 6 F* \[2] $end $upscope $end -$var wire 25 D* imm_low $end -$var wire 1 E* imm_sign $end +$var wire 25 G* imm_low $end +$var wire 1 H* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 F* output_integer_mode $end +$var string 1 I* output_integer_mode $end $upscope $end -$var wire 1 G* invert_src0 $end -$var wire 1 H* invert_carry_in $end -$var wire 1 I* invert_carry_out $end -$var wire 1 J* add_pc $end +$var wire 1 J* invert_src0 $end +$var wire 1 K* src1_is_carry_in $end +$var wire 1 L* invert_carry_in $end +$var wire 1 M* add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 K* prefix_pad $end +$var string 0 N* prefix_pad $end $scope struct dest $end -$var wire 4 L* value $end +$var wire 4 O* value $end $upscope $end $scope struct src $end -$var wire 6 M* \[0] $end -$var wire 6 N* \[1] $end -$var wire 6 O* \[2] $end +$var wire 6 P* \[0] $end +$var wire 6 Q* \[1] $end +$var wire 6 R* \[2] $end $upscope $end -$var wire 25 P* imm_low $end -$var wire 1 Q* imm_sign $end +$var wire 25 S* imm_low $end +$var wire 1 T* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 R* output_integer_mode $end +$var string 1 U* output_integer_mode $end $upscope $end -$var wire 4 S* lut $end +$var wire 4 V* lut $end $upscope $end $upscope $end $scope struct L2RegisterFile $end -$var string 1 T* \$tag $end +$var string 1 W* \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 U* prefix_pad $end +$var wire 1 X* prefix_pad $end $scope struct dest $end -$var wire 4 V* value $end +$var wire 4 Y* value $end $upscope $end $scope struct src $end -$var wire 6 W* \[0] $end -$var wire 6 X* \[1] $end -$var wire 6 Y* \[2] $end +$var wire 6 Z* \[0] $end +$var wire 6 [* \[1] $end +$var wire 6 \* \[2] $end $upscope $end -$var wire 25 Z* imm_low $end -$var wire 1 [* imm_sign $end +$var wire 25 ]* imm_low $end +$var wire 1 ^* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 \* prefix_pad $end +$var wire 1 _* prefix_pad $end $scope struct dest $end -$var wire 4 ]* value $end +$var wire 4 `* value $end $upscope $end $scope struct src $end -$var wire 6 ^* \[0] $end -$var wire 6 _* \[1] $end -$var wire 6 `* \[2] $end +$var wire 6 a* \[0] $end +$var wire 6 b* \[1] $end +$var wire 6 c* \[2] $end $upscope $end -$var wire 25 a* imm_low $end -$var wire 1 b* imm_sign $end +$var wire 25 d* imm_low $end +$var wire 1 e* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct LoadStore $end -$var string 1 c* \$tag $end +$var string 1 f* \$tag $end $scope struct Load $end -$var wire 1 d* prefix_pad $end +$var wire 1 g* prefix_pad $end $scope struct dest $end -$var wire 4 e* value $end +$var wire 4 h* value $end $upscope $end $scope struct src $end -$var wire 6 f* \[0] $end -$var wire 6 g* \[1] $end -$var wire 6 h* \[2] $end +$var wire 6 i* \[0] $end +$var wire 6 j* \[1] $end +$var wire 6 k* \[2] $end $upscope $end -$var wire 25 i* imm_low $end -$var wire 1 j* imm_sign $end +$var wire 25 l* imm_low $end +$var wire 1 m* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 k* prefix_pad $end +$var wire 1 n* prefix_pad $end $scope struct dest $end -$var wire 4 l* value $end +$var wire 4 o* value $end $upscope $end $scope struct src $end -$var wire 6 m* \[0] $end -$var wire 6 n* \[1] $end -$var wire 6 o* \[2] $end +$var wire 6 p* \[0] $end +$var wire 6 q* \[1] $end +$var wire 6 r* \[2] $end $upscope $end -$var wire 25 p* imm_low $end -$var wire 1 q* imm_sign $end +$var wire 25 s* imm_low $end +$var wire 1 t* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs_6 $end -$var string 1 r* \$tag $end +$var string 1 u* \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 s* prefix_pad $end +$var string 0 v* prefix_pad $end $scope struct dest $end -$var wire 4 t* value $end +$var wire 4 w* value $end $upscope $end $scope struct src $end -$var wire 6 u* \[0] $end -$var wire 6 v* \[1] $end -$var wire 6 w* \[2] $end +$var wire 6 x* \[0] $end +$var wire 6 y* \[1] $end +$var wire 6 z* \[2] $end $upscope $end -$var wire 25 x* imm_low $end -$var wire 1 y* imm_sign $end +$var wire 25 {* imm_low $end +$var wire 1 |* imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 z* output_integer_mode $end +$var string 1 }* output_integer_mode $end $upscope $end -$var wire 1 {* invert_src0 $end -$var wire 1 |* invert_carry_in $end -$var wire 1 }* invert_carry_out $end -$var wire 1 ~* add_pc $end +$var wire 1 ~* invert_src0 $end +$var wire 1 !+ src1_is_carry_in $end +$var wire 1 "+ invert_carry_in $end +$var wire 1 #+ add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 !+ prefix_pad $end +$var string 0 $+ prefix_pad $end $scope struct dest $end -$var wire 4 "+ value $end +$var wire 4 %+ value $end $upscope $end $scope struct src $end -$var wire 6 #+ \[0] $end -$var wire 6 $+ \[1] $end -$var wire 6 %+ \[2] $end +$var wire 6 &+ \[0] $end +$var wire 6 '+ \[1] $end +$var wire 6 (+ \[2] $end $upscope $end -$var wire 25 &+ imm_low $end -$var wire 1 '+ imm_sign $end +$var wire 25 )+ imm_low $end +$var wire 1 *+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 (+ output_integer_mode $end +$var string 1 ++ output_integer_mode $end $upscope $end -$var wire 1 )+ invert_src0 $end -$var wire 1 *+ invert_carry_in $end -$var wire 1 ++ invert_carry_out $end -$var wire 1 ,+ add_pc $end +$var wire 1 ,+ invert_src0 $end +$var wire 1 -+ src1_is_carry_in $end +$var wire 1 .+ invert_carry_in $end +$var wire 1 /+ add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 -+ prefix_pad $end +$var string 0 0+ prefix_pad $end $scope struct dest $end -$var wire 4 .+ value $end +$var wire 4 1+ value $end $upscope $end $scope struct src $end -$var wire 6 /+ \[0] $end -$var wire 6 0+ \[1] $end -$var wire 6 1+ \[2] $end +$var wire 6 2+ \[0] $end +$var wire 6 3+ \[1] $end +$var wire 6 4+ \[2] $end $upscope $end -$var wire 25 2+ imm_low $end -$var wire 1 3+ imm_sign $end +$var wire 25 5+ imm_low $end +$var wire 1 6+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 4+ output_integer_mode $end +$var string 1 7+ output_integer_mode $end $upscope $end -$var wire 4 5+ lut $end +$var wire 4 8+ lut $end $upscope $end $upscope $end $scope struct mapped_regs_7 $end -$var string 1 6+ \$tag $end +$var string 1 9+ \$tag $end $scope struct ReadL2Reg $end $scope struct common $end -$var wire 1 7+ prefix_pad $end +$var wire 1 :+ prefix_pad $end $scope struct dest $end -$var wire 4 8+ value $end +$var wire 4 ;+ value $end $upscope $end $scope struct src $end -$var wire 6 9+ \[0] $end -$var wire 6 :+ \[1] $end -$var wire 6 ;+ \[2] $end +$var wire 6 <+ \[0] $end +$var wire 6 =+ \[1] $end +$var wire 6 >+ \[2] $end $upscope $end -$var wire 25 <+ imm_low $end -$var wire 1 =+ imm_sign $end +$var wire 25 ?+ imm_low $end +$var wire 1 @+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct WriteL2Reg $end $scope struct common $end -$var wire 1 >+ prefix_pad $end +$var wire 1 A+ prefix_pad $end $scope struct dest $end -$var wire 4 ?+ value $end +$var wire 4 B+ value $end $upscope $end $scope struct src $end -$var wire 6 @+ \[0] $end -$var wire 6 A+ \[1] $end -$var wire 6 B+ \[2] $end +$var wire 6 C+ \[0] $end +$var wire 6 D+ \[1] $end +$var wire 6 E+ \[2] $end $upscope $end -$var wire 25 C+ imm_low $end -$var wire 1 D+ imm_sign $end +$var wire 25 F+ imm_low $end +$var wire 1 G+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct mapped_regs_8 $end -$var string 1 E+ \$tag $end +$var string 1 H+ \$tag $end $scope struct Load $end -$var wire 1 F+ prefix_pad $end +$var wire 1 I+ prefix_pad $end $scope struct dest $end -$var wire 4 G+ value $end +$var wire 4 J+ value $end $upscope $end $scope struct src $end -$var wire 6 H+ \[0] $end -$var wire 6 I+ \[1] $end -$var wire 6 J+ \[2] $end +$var wire 6 K+ \[0] $end +$var wire 6 L+ \[1] $end +$var wire 6 M+ \[2] $end $upscope $end -$var wire 25 K+ imm_low $end -$var wire 1 L+ imm_sign $end +$var wire 25 N+ imm_low $end +$var wire 1 O+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 M+ prefix_pad $end +$var wire 1 P+ prefix_pad $end $scope struct dest $end -$var wire 4 N+ value $end +$var wire 4 Q+ value $end $upscope $end $scope struct src $end -$var wire 6 O+ \[0] $end -$var wire 6 P+ \[1] $end -$var wire 6 Q+ \[2] $end +$var wire 6 R+ \[0] $end +$var wire 6 S+ \[1] $end +$var wire 6 T+ \[2] $end $upscope $end -$var wire 25 R+ imm_low $end -$var wire 1 S+ imm_sign $end +$var wire 25 U+ imm_low $end +$var wire 1 V+ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $upscope $end $scope struct flag_reg_15 $end -$var wire 8 T+ value $end +$var wire 8 W+ value $end $upscope $end $scope struct flag_reg_16 $end -$var wire 8 U+ value $end +$var wire 8 X+ value $end $upscope $end $scope struct selected_unit_index_leaf_1_0 $end -$var string 1 V+ \$tag $end -$var wire 2 W+ HdlSome $end -$upscope $end -$var wire 2 X+ unit_index_1_0 $end -$scope struct selected_unit_index_leaf_1_1 $end $var string 1 Y+ \$tag $end $var wire 2 Z+ HdlSome $end $upscope $end -$var wire 2 [+ unit_index_1_1 $end -$scope struct selected_unit_index_node_1_0 $end +$var wire 2 [+ unit_index_1_0 $end +$scope struct selected_unit_index_leaf_1_1 $end $var string 1 \+ \$tag $end $var wire 2 ]+ HdlSome $end $upscope $end -$scope struct unit_0 $end -$scope struct cd $end -$var wire 1 {: clk $end -$var wire 1 |: rst $end +$var wire 2 ^+ unit_index_1_1 $end +$scope struct selected_unit_index_node_1_0 $end +$var string 1 _+ \$tag $end +$var wire 2 `+ HdlSome $end $upscope $end -$scope struct unit_to_reg_alloc $end $scope struct unit_forwarding_info $end $scope struct unit_output_writes $end $scope struct \[0] $end -$var string 1 }: \$tag $end +$var string 1 a+ \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 ~: value $end +$var wire 4 b+ value $end $upscope $end $scope struct value $end -$var wire 64 !; int_fp $end +$var wire 64 c+ int_fp $end $scope struct flags $end -$var wire 1 "; pwr_ca_x86_cf $end -$var wire 1 #; pwr_ca32_x86_af $end -$var wire 1 $; pwr_ov_x86_of $end -$var wire 1 %; pwr_ov32_x86_df $end -$var wire 1 &; pwr_cr_lt_x86_sf $end -$var wire 1 '; pwr_cr_gt_x86_pf $end -$var wire 1 (; pwr_cr_eq_x86_zf $end -$var wire 1 ); pwr_so $end +$var wire 1 d+ pwr_ca_x86_cf $end +$var wire 1 e+ pwr_ca32_x86_af $end +$var wire 1 f+ pwr_ov_x86_of $end +$var wire 1 g+ pwr_ov32_x86_df $end +$var wire 1 h+ pwr_cr_lt_x86_sf $end +$var wire 1 i+ pwr_cr_gt_x86_pf $end +$var wire 1 j+ pwr_cr_eq_x86_zf $end +$var wire 1 k+ pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 *; \$tag $end +$var string 1 l+ \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 +; value $end +$var wire 4 m+ value $end $upscope $end $scope struct value $end -$var wire 64 ,; int_fp $end +$var wire 64 n+ int_fp $end $scope struct flags $end -$var wire 1 -; pwr_ca_x86_cf $end -$var wire 1 .; pwr_ca32_x86_af $end -$var wire 1 /; pwr_ov_x86_of $end -$var wire 1 0; pwr_ov32_x86_df $end -$var wire 1 1; pwr_cr_lt_x86_sf $end -$var wire 1 2; pwr_cr_gt_x86_pf $end -$var wire 1 3; pwr_cr_eq_x86_zf $end -$var wire 1 4; pwr_so $end +$var wire 1 o+ pwr_ca_x86_cf $end +$var wire 1 p+ pwr_ca32_x86_af $end +$var wire 1 q+ pwr_ov_x86_of $end +$var wire 1 r+ pwr_ov32_x86_df $end +$var wire 1 s+ pwr_cr_lt_x86_sf $end +$var wire 1 t+ pwr_cr_gt_x86_pf $end +$var wire 1 u+ pwr_cr_eq_x86_zf $end +$var wire 1 v+ pwr_so $end $upscope $end $upscope $end $upscope $end @@ -5651,102 +5660,409 @@ $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end -$scope struct data $end -$var string 1 5; \$tag $end +$scope struct unit_0 $end +$scope struct cd $end +$var wire 1 W> clk $end +$var wire 1 X> rst $end +$upscope $end +$scope struct unit_to_reg_alloc $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 Y> \$tag $end $scope struct HdlSome $end -$var string 1 6; \$tag $end +$scope struct which $end +$var wire 4 Z> value $end +$upscope $end +$scope struct value $end +$var wire 64 [> int_fp $end +$scope struct flags $end +$var wire 1 \> pwr_ca_x86_cf $end +$var wire 1 ]> pwr_ca32_x86_af $end +$var wire 1 ^> pwr_ov_x86_of $end +$var wire 1 _> pwr_ov32_x86_df $end +$var wire 1 `> pwr_cr_lt_x86_sf $end +$var wire 1 a> pwr_cr_gt_x86_pf $end +$var wire 1 b> pwr_cr_eq_x86_zf $end +$var wire 1 c> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 d> \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 e> value $end +$upscope $end +$scope struct value $end +$var wire 64 f> int_fp $end +$scope struct flags $end +$var wire 1 g> pwr_ca_x86_cf $end +$var wire 1 h> pwr_ca32_x86_af $end +$var wire 1 i> pwr_ov_x86_of $end +$var wire 1 j> pwr_ov32_x86_df $end +$var wire 1 k> pwr_cr_lt_x86_sf $end +$var wire 1 l> pwr_cr_gt_x86_pf $end +$var wire 1 m> pwr_cr_eq_x86_zf $end +$var wire 1 n> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 o> \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 p> \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 7; prefix_pad $end +$var string 0 q> prefix_pad $end $scope struct dest $end -$var wire 4 8; value $end +$var wire 4 r> value $end $upscope $end $scope struct src $end -$var wire 6 9; \[0] $end -$var wire 6 :; \[1] $end -$var wire 6 ;; \[2] $end +$var wire 6 s> \[0] $end +$var wire 6 t> \[1] $end +$var wire 6 u> \[2] $end $upscope $end -$var wire 25 <; imm_low $end -$var wire 1 =; imm_sign $end +$var wire 25 v> imm_low $end +$var wire 1 w> imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 >; output_integer_mode $end +$var string 1 x> output_integer_mode $end $upscope $end -$var wire 1 ?; invert_src0 $end -$var wire 1 @; invert_carry_in $end -$var wire 1 A; invert_carry_out $end -$var wire 1 B; add_pc $end +$var wire 1 y> invert_src0 $end +$var wire 1 z> src1_is_carry_in $end +$var wire 1 {> invert_carry_in $end +$var wire 1 |> add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 C; prefix_pad $end +$var string 0 }> prefix_pad $end $scope struct dest $end -$var wire 4 D; value $end +$var wire 4 ~> value $end $upscope $end $scope struct src $end -$var wire 6 E; \[0] $end -$var wire 6 F; \[1] $end -$var wire 6 G; \[2] $end +$var wire 6 !? \[0] $end +$var wire 6 "? \[1] $end +$var wire 6 #? \[2] $end $upscope $end -$var wire 25 H; imm_low $end -$var wire 1 I; imm_sign $end +$var wire 25 $? imm_low $end +$var wire 1 %? imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 J; output_integer_mode $end +$var string 1 &? output_integer_mode $end $upscope $end -$var wire 1 K; invert_src0 $end -$var wire 1 L; invert_carry_in $end -$var wire 1 M; invert_carry_out $end -$var wire 1 N; add_pc $end +$var wire 1 '? invert_src0 $end +$var wire 1 (? src1_is_carry_in $end +$var wire 1 )? invert_carry_in $end +$var wire 1 *? add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 O; prefix_pad $end +$var string 0 +? prefix_pad $end $scope struct dest $end -$var wire 4 P; value $end +$var wire 4 ,? value $end $upscope $end $scope struct src $end -$var wire 6 Q; \[0] $end -$var wire 6 R; \[1] $end -$var wire 6 S; \[2] $end +$var wire 6 -? \[0] $end +$var wire 6 .? \[1] $end +$var wire 6 /? \[2] $end $upscope $end -$var wire 25 T; imm_low $end -$var wire 1 U; imm_sign $end +$var wire 25 0? imm_low $end +$var wire 1 1? imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 V; output_integer_mode $end +$var string 1 2? output_integer_mode $end $upscope $end -$var wire 4 W; lut $end +$var wire 4 3? lut $end $upscope $end $upscope $end +$var wire 64 4? pc $end $upscope $end -$var wire 1 X; ready $end +$upscope $end +$var wire 1 5? ready $end $upscope $end $scope struct cancel_input $end -$var string 1 Y; \$tag $end +$var string 1 6? \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 Z; value $end +$var wire 4 7? value $end $upscope $end $upscope $end $upscope $end $scope struct output $end -$var string 1 [; \$tag $end +$var string 1 8? \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 \; value $end +$var wire 4 9? value $end $upscope $end $scope struct result $end -$var string 1 ]; \$tag $end +$var string 1 :? \$tag $end $scope struct Completed $end $scope struct value $end +$var wire 64 ;? int_fp $end +$scope struct flags $end +$var wire 1 ? pwr_ov_x86_of $end +$var wire 1 ?? pwr_ov32_x86_df $end +$var wire 1 @? pwr_cr_lt_x86_sf $end +$var wire 1 A? pwr_cr_gt_x86_pf $end +$var wire 1 B? pwr_cr_eq_x86_zf $end +$var wire 1 C? pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 D? \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module alu_branch $end +$scope struct cd $end +$var wire 1 w+ clk $end +$var wire 1 x+ rst $end +$upscope $end +$scope struct unit_to_reg_alloc $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 y+ \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 z+ value $end +$upscope $end +$scope struct value $end +$var wire 64 {+ int_fp $end +$scope struct flags $end +$var wire 1 |+ pwr_ca_x86_cf $end +$var wire 1 }+ pwr_ca32_x86_af $end +$var wire 1 ~+ pwr_ov_x86_of $end +$var wire 1 !, pwr_ov32_x86_df $end +$var wire 1 ", pwr_cr_lt_x86_sf $end +$var wire 1 #, pwr_cr_gt_x86_pf $end +$var wire 1 $, pwr_cr_eq_x86_zf $end +$var wire 1 %, pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 &, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ', value $end +$upscope $end +$scope struct value $end +$var wire 64 (, int_fp $end +$scope struct flags $end +$var wire 1 ), pwr_ca_x86_cf $end +$var wire 1 *, pwr_ca32_x86_af $end +$var wire 1 +, pwr_ov_x86_of $end +$var wire 1 ,, pwr_ov32_x86_df $end +$var wire 1 -, pwr_cr_lt_x86_sf $end +$var wire 1 ., pwr_cr_gt_x86_pf $end +$var wire 1 /, pwr_cr_eq_x86_zf $end +$var wire 1 0, pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 1, \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 2, \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 3, prefix_pad $end +$scope struct dest $end +$var wire 4 4, value $end +$upscope $end +$scope struct src $end +$var wire 6 5, \[0] $end +$var wire 6 6, \[1] $end +$var wire 6 7, \[2] $end +$upscope $end +$var wire 25 8, imm_low $end +$var wire 1 9, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 :, output_integer_mode $end +$upscope $end +$var wire 1 ;, invert_src0 $end +$var wire 1 <, src1_is_carry_in $end +$var wire 1 =, invert_carry_in $end +$var wire 1 >, add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ?, prefix_pad $end +$scope struct dest $end +$var wire 4 @, value $end +$upscope $end +$scope struct src $end +$var wire 6 A, \[0] $end +$var wire 6 B, \[1] $end +$var wire 6 C, \[2] $end +$upscope $end +$var wire 25 D, imm_low $end +$var wire 1 E, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 F, output_integer_mode $end +$upscope $end +$var wire 1 G, invert_src0 $end +$var wire 1 H, src1_is_carry_in $end +$var wire 1 I, invert_carry_in $end +$var wire 1 J, add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 K, prefix_pad $end +$scope struct dest $end +$var wire 4 L, value $end +$upscope $end +$scope struct src $end +$var wire 6 M, \[0] $end +$var wire 6 N, \[1] $end +$var wire 6 O, \[2] $end +$upscope $end +$var wire 25 P, imm_low $end +$var wire 1 Q, imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 R, output_integer_mode $end +$upscope $end +$var wire 4 S, lut $end +$upscope $end +$upscope $end +$var wire 64 T, pc $end +$upscope $end +$upscope $end +$var wire 1 U, ready $end +$upscope $end +$scope struct cancel_input $end +$var string 1 V, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 W, value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct output $end +$var string 1 X, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 Y, value $end +$upscope $end +$scope struct result $end +$var string 1 Z, \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 [, int_fp $end +$scope struct flags $end +$var wire 1 \, pwr_ca_x86_cf $end +$var wire 1 ], pwr_ca32_x86_af $end +$var wire 1 ^, pwr_ov_x86_of $end +$var wire 1 _, pwr_ov32_x86_df $end +$var wire 1 `, pwr_cr_lt_x86_sf $end +$var wire 1 a, pwr_cr_gt_x86_pf $end +$var wire 1 b, pwr_cr_eq_x86_zf $end +$var wire 1 c, pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 d, \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_base $end +$scope struct cd $end +$var wire 1 O; clk $end +$var wire 1 P; rst $end +$upscope $end +$scope struct unit_to_reg_alloc $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 Q; \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 R; value $end +$upscope $end +$scope struct value $end +$var wire 64 S; int_fp $end +$scope struct flags $end +$var wire 1 T; pwr_ca_x86_cf $end +$var wire 1 U; pwr_ca32_x86_af $end +$var wire 1 V; pwr_ov_x86_of $end +$var wire 1 W; pwr_ov32_x86_df $end +$var wire 1 X; pwr_cr_lt_x86_sf $end +$var wire 1 Y; pwr_cr_gt_x86_pf $end +$var wire 1 Z; pwr_cr_eq_x86_zf $end +$var wire 1 [; pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 \; \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ]; value $end +$upscope $end +$scope struct value $end $var wire 64 ^; int_fp $end $scope struct flags $end $var wire 1 _; pwr_ca_x86_cf $end @@ -5759,347 +6075,121 @@ $var wire 1 e; pwr_cr_eq_x86_zf $end $var wire 1 f; pwr_so $end $upscope $end $upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module alu_branch $end -$scope struct cd $end -$var wire 1 ^+ clk $end -$var wire 1 _+ rst $end -$upscope $end -$scope struct unit_to_reg_alloc $end -$scope struct unit_forwarding_info $end -$scope struct unit_output_writes $end -$scope struct \[0] $end -$var string 1 `+ \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 a+ value $end -$upscope $end -$scope struct value $end -$var wire 64 b+ int_fp $end -$scope struct flags $end -$var wire 1 c+ pwr_ca_x86_cf $end -$var wire 1 d+ pwr_ca32_x86_af $end -$var wire 1 e+ pwr_ov_x86_of $end -$var wire 1 f+ pwr_ov32_x86_df $end -$var wire 1 g+ pwr_cr_lt_x86_sf $end -$var wire 1 h+ pwr_cr_gt_x86_pf $end -$var wire 1 i+ pwr_cr_eq_x86_zf $end -$var wire 1 j+ pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var string 1 k+ \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 l+ value $end -$upscope $end -$scope struct value $end -$var wire 64 m+ int_fp $end -$scope struct flags $end -$var wire 1 n+ pwr_ca_x86_cf $end -$var wire 1 o+ pwr_ca32_x86_af $end -$var wire 1 p+ pwr_ov_x86_of $end -$var wire 1 q+ pwr_ov32_x86_df $end -$var wire 1 r+ pwr_cr_lt_x86_sf $end -$var wire 1 s+ pwr_cr_gt_x86_pf $end -$var wire 1 t+ pwr_cr_eq_x86_zf $end -$var wire 1 u+ pwr_so $end -$upscope $end -$upscope $end $upscope $end $upscope $end $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end +$scope struct input $end $scope struct data $end -$var string 1 v+ \$tag $end +$var string 1 g; \$tag $end $scope struct HdlSome $end -$var string 1 w+ \$tag $end +$scope struct mop $end +$var string 1 h; \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 x+ prefix_pad $end +$var string 0 i; prefix_pad $end $scope struct dest $end -$var wire 4 y+ value $end +$var wire 4 j; value $end $upscope $end $scope struct src $end -$var wire 6 z+ \[0] $end -$var wire 6 {+ \[1] $end -$var wire 6 |+ \[2] $end +$var wire 6 k; \[0] $end +$var wire 6 l; \[1] $end +$var wire 6 m; \[2] $end $upscope $end -$var wire 25 }+ imm_low $end -$var wire 1 ~+ imm_sign $end +$var wire 25 n; imm_low $end +$var wire 1 o; imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 !, output_integer_mode $end +$var string 1 p; output_integer_mode $end $upscope $end -$var wire 1 ", invert_src0 $end -$var wire 1 #, invert_carry_in $end -$var wire 1 $, invert_carry_out $end -$var wire 1 %, add_pc $end +$var wire 1 q; invert_src0 $end +$var wire 1 r; src1_is_carry_in $end +$var wire 1 s; invert_carry_in $end +$var wire 1 t; add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 &, prefix_pad $end +$var string 0 u; prefix_pad $end $scope struct dest $end -$var wire 4 ', value $end +$var wire 4 v; value $end $upscope $end $scope struct src $end -$var wire 6 (, \[0] $end -$var wire 6 ), \[1] $end -$var wire 6 *, \[2] $end +$var wire 6 w; \[0] $end +$var wire 6 x; \[1] $end +$var wire 6 y; \[2] $end $upscope $end -$var wire 25 +, imm_low $end -$var wire 1 ,, imm_sign $end +$var wire 25 z; imm_low $end +$var wire 1 {; imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 -, output_integer_mode $end +$var string 1 |; output_integer_mode $end $upscope $end -$var wire 1 ., invert_src0 $end -$var wire 1 /, invert_carry_in $end -$var wire 1 0, invert_carry_out $end -$var wire 1 1, add_pc $end +$var wire 1 }; invert_src0 $end +$var wire 1 ~; src1_is_carry_in $end +$var wire 1 !< invert_carry_in $end +$var wire 1 "< add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 2, prefix_pad $end +$var string 0 #< prefix_pad $end $scope struct dest $end -$var wire 4 3, value $end +$var wire 4 $< value $end $upscope $end $scope struct src $end -$var wire 6 4, \[0] $end -$var wire 6 5, \[1] $end -$var wire 6 6, \[2] $end +$var wire 6 %< \[0] $end +$var wire 6 &< \[1] $end +$var wire 6 '< \[2] $end $upscope $end -$var wire 25 7, imm_low $end -$var wire 1 8, imm_sign $end +$var wire 25 (< imm_low $end +$var wire 1 )< imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 9, output_integer_mode $end +$var string 1 *< output_integer_mode $end $upscope $end -$var wire 4 :, lut $end +$var wire 4 +< lut $end $upscope $end $upscope $end +$var wire 64 ,< pc $end $upscope $end -$var wire 1 ;, ready $end +$upscope $end +$var wire 1 -< ready $end $upscope $end $scope struct cancel_input $end -$var string 1 <, \$tag $end +$var string 1 .< \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 =, value $end +$var wire 4 /< value $end $upscope $end $upscope $end $upscope $end $scope struct output $end -$var string 1 >, \$tag $end +$var string 1 0< \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 ?, value $end +$var wire 4 1< value $end $upscope $end $scope struct result $end -$var string 1 @, \$tag $end +$var string 1 2< \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 A, int_fp $end +$var wire 64 3< int_fp $end $scope struct flags $end -$var wire 1 B, pwr_ca_x86_cf $end -$var wire 1 C, pwr_ca32_x86_af $end -$var wire 1 D, pwr_ov_x86_of $end -$var wire 1 E, pwr_ov32_x86_df $end -$var wire 1 F, pwr_cr_lt_x86_sf $end -$var wire 1 G, pwr_cr_gt_x86_pf $end -$var wire 1 H, pwr_cr_eq_x86_zf $end -$var wire 1 I, pwr_so $end -$upscope $end -$upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct unit_base $end -$scope struct cd $end -$var wire 1 D9 clk $end -$var wire 1 E9 rst $end -$upscope $end -$scope struct unit_to_reg_alloc $end -$scope struct unit_forwarding_info $end -$scope struct unit_output_writes $end -$scope struct \[0] $end -$var string 1 F9 \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 G9 value $end -$upscope $end -$scope struct value $end -$var wire 64 H9 int_fp $end -$scope struct flags $end -$var wire 1 I9 pwr_ca_x86_cf $end -$var wire 1 J9 pwr_ca32_x86_af $end -$var wire 1 K9 pwr_ov_x86_of $end -$var wire 1 L9 pwr_ov32_x86_df $end -$var wire 1 M9 pwr_cr_lt_x86_sf $end -$var wire 1 N9 pwr_cr_gt_x86_pf $end -$var wire 1 O9 pwr_cr_eq_x86_zf $end -$var wire 1 P9 pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var string 1 Q9 \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 R9 value $end -$upscope $end -$scope struct value $end -$var wire 64 S9 int_fp $end -$scope struct flags $end -$var wire 1 T9 pwr_ca_x86_cf $end -$var wire 1 U9 pwr_ca32_x86_af $end -$var wire 1 V9 pwr_ov_x86_of $end -$var wire 1 W9 pwr_ov32_x86_df $end -$var wire 1 X9 pwr_cr_lt_x86_sf $end -$var wire 1 Y9 pwr_cr_gt_x86_pf $end -$var wire 1 Z9 pwr_cr_eq_x86_zf $end -$var wire 1 [9 pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$scope struct input_insn $end -$scope struct data $end -$var string 1 \9 \$tag $end -$scope struct HdlSome $end -$var string 1 ]9 \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ^9 prefix_pad $end -$scope struct dest $end -$var wire 4 _9 value $end -$upscope $end -$scope struct src $end -$var wire 6 `9 \[0] $end -$var wire 6 a9 \[1] $end -$var wire 6 b9 \[2] $end -$upscope $end -$var wire 25 c9 imm_low $end -$var wire 1 d9 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 e9 output_integer_mode $end -$upscope $end -$var wire 1 f9 invert_src0 $end -$var wire 1 g9 invert_carry_in $end -$var wire 1 h9 invert_carry_out $end -$var wire 1 i9 add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 j9 prefix_pad $end -$scope struct dest $end -$var wire 4 k9 value $end -$upscope $end -$scope struct src $end -$var wire 6 l9 \[0] $end -$var wire 6 m9 \[1] $end -$var wire 6 n9 \[2] $end -$upscope $end -$var wire 25 o9 imm_low $end -$var wire 1 p9 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 q9 output_integer_mode $end -$upscope $end -$var wire 1 r9 invert_src0 $end -$var wire 1 s9 invert_carry_in $end -$var wire 1 t9 invert_carry_out $end -$var wire 1 u9 add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 v9 prefix_pad $end -$scope struct dest $end -$var wire 4 w9 value $end -$upscope $end -$scope struct src $end -$var wire 6 x9 \[0] $end -$var wire 6 y9 \[1] $end -$var wire 6 z9 \[2] $end -$upscope $end -$var wire 25 {9 imm_low $end -$var wire 1 |9 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 }9 output_integer_mode $end -$upscope $end -$var wire 4 ~9 lut $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 !: ready $end -$upscope $end -$scope struct cancel_input $end -$var string 1 ": \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 #: value $end -$upscope $end -$upscope $end -$upscope $end -$scope struct output $end -$var string 1 $: \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 %: value $end -$upscope $end -$scope struct result $end -$var string 1 &: \$tag $end -$scope struct Completed $end -$scope struct value $end -$var wire 64 ': int_fp $end -$scope struct flags $end -$var wire 1 (: pwr_ca_x86_cf $end -$var wire 1 ): pwr_ca32_x86_af $end -$var wire 1 *: pwr_ov_x86_of $end -$var wire 1 +: pwr_ov32_x86_df $end -$var wire 1 ,: pwr_cr_lt_x86_sf $end -$var wire 1 -: pwr_cr_gt_x86_pf $end -$var wire 1 .: pwr_cr_eq_x86_zf $end -$var wire 1 /: pwr_so $end +$var wire 1 4< pwr_ca_x86_cf $end +$var wire 1 5< pwr_ca32_x86_af $end +$var wire 1 6< pwr_ov_x86_of $end +$var wire 1 7< pwr_ov32_x86_df $end +$var wire 1 8< pwr_cr_lt_x86_sf $end +$var wire 1 9< pwr_cr_gt_x86_pf $end +$var wire 1 :< pwr_cr_eq_x86_zf $end +$var wire 1 ;< pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -6113,146 +6203,147 @@ $upscope $end $upscope $end $scope struct execute_start $end $scope struct data $end -$var string 1 0: \$tag $end +$var string 1 << \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 1: \$tag $end +$var string 1 =< \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 2: prefix_pad $end +$var string 0 >< prefix_pad $end $scope struct dest $end -$var wire 4 3: value $end +$var wire 4 ?< value $end $upscope $end $scope struct src $end -$var wire 6 4: \[0] $end -$var wire 6 5: \[1] $end -$var wire 6 6: \[2] $end +$var wire 6 @< \[0] $end +$var wire 6 A< \[1] $end +$var wire 6 B< \[2] $end $upscope $end -$var wire 25 7: imm_low $end -$var wire 1 8: imm_sign $end +$var wire 25 C< imm_low $end +$var wire 1 D< imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 9: output_integer_mode $end +$var string 1 E< output_integer_mode $end $upscope $end -$var wire 1 :: invert_src0 $end -$var wire 1 ;: invert_carry_in $end -$var wire 1 <: invert_carry_out $end -$var wire 1 =: add_pc $end +$var wire 1 F< invert_src0 $end +$var wire 1 G< src1_is_carry_in $end +$var wire 1 H< invert_carry_in $end +$var wire 1 I< add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 >: prefix_pad $end +$var string 0 J< prefix_pad $end $scope struct dest $end -$var wire 4 ?: value $end +$var wire 4 K< value $end $upscope $end $scope struct src $end -$var wire 6 @: \[0] $end -$var wire 6 A: \[1] $end -$var wire 6 B: \[2] $end +$var wire 6 L< \[0] $end +$var wire 6 M< \[1] $end +$var wire 6 N< \[2] $end $upscope $end -$var wire 25 C: imm_low $end -$var wire 1 D: imm_sign $end +$var wire 25 O< imm_low $end +$var wire 1 P< imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 E: output_integer_mode $end +$var string 1 Q< output_integer_mode $end $upscope $end -$var wire 1 F: invert_src0 $end -$var wire 1 G: invert_carry_in $end -$var wire 1 H: invert_carry_out $end -$var wire 1 I: add_pc $end +$var wire 1 R< invert_src0 $end +$var wire 1 S< src1_is_carry_in $end +$var wire 1 T< invert_carry_in $end +$var wire 1 U< add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 J: prefix_pad $end +$var string 0 V< prefix_pad $end $scope struct dest $end -$var wire 4 K: value $end +$var wire 4 W< value $end $upscope $end $scope struct src $end -$var wire 6 L: \[0] $end -$var wire 6 M: \[1] $end -$var wire 6 N: \[2] $end +$var wire 6 X< \[0] $end +$var wire 6 Y< \[1] $end +$var wire 6 Z< \[2] $end $upscope $end -$var wire 25 O: imm_low $end -$var wire 1 P: imm_sign $end +$var wire 25 [< imm_low $end +$var wire 1 \< imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 Q: output_integer_mode $end +$var string 1 ]< output_integer_mode $end $upscope $end -$var wire 4 R: lut $end +$var wire 4 ^< lut $end $upscope $end $upscope $end +$var wire 64 _< pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 S: int_fp $end +$var wire 64 `< int_fp $end $scope struct flags $end -$var wire 1 T: pwr_ca_x86_cf $end -$var wire 1 U: pwr_ca32_x86_af $end -$var wire 1 V: pwr_ov_x86_of $end -$var wire 1 W: pwr_ov32_x86_df $end -$var wire 1 X: pwr_cr_lt_x86_sf $end -$var wire 1 Y: pwr_cr_gt_x86_pf $end -$var wire 1 Z: pwr_cr_eq_x86_zf $end -$var wire 1 [: pwr_so $end +$var wire 1 a< pwr_ca_x86_cf $end +$var wire 1 b< pwr_ca32_x86_af $end +$var wire 1 c< pwr_ov_x86_of $end +$var wire 1 d< pwr_ov32_x86_df $end +$var wire 1 e< pwr_cr_lt_x86_sf $end +$var wire 1 f< pwr_cr_gt_x86_pf $end +$var wire 1 g< pwr_cr_eq_x86_zf $end +$var wire 1 h< pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 \: int_fp $end +$var wire 64 i< int_fp $end $scope struct flags $end -$var wire 1 ]: pwr_ca_x86_cf $end -$var wire 1 ^: pwr_ca32_x86_af $end -$var wire 1 _: pwr_ov_x86_of $end -$var wire 1 `: pwr_ov32_x86_df $end -$var wire 1 a: pwr_cr_lt_x86_sf $end -$var wire 1 b: pwr_cr_gt_x86_pf $end -$var wire 1 c: pwr_cr_eq_x86_zf $end -$var wire 1 d: pwr_so $end +$var wire 1 j< pwr_ca_x86_cf $end +$var wire 1 k< pwr_ca32_x86_af $end +$var wire 1 l< pwr_ov_x86_of $end +$var wire 1 m< pwr_ov32_x86_df $end +$var wire 1 n< pwr_cr_lt_x86_sf $end +$var wire 1 o< pwr_cr_gt_x86_pf $end +$var wire 1 p< pwr_cr_eq_x86_zf $end +$var wire 1 q< pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 e: int_fp $end +$var wire 64 r< int_fp $end $scope struct flags $end -$var wire 1 f: pwr_ca_x86_cf $end -$var wire 1 g: pwr_ca32_x86_af $end -$var wire 1 h: pwr_ov_x86_of $end -$var wire 1 i: pwr_ov32_x86_df $end -$var wire 1 j: pwr_cr_lt_x86_sf $end -$var wire 1 k: pwr_cr_gt_x86_pf $end -$var wire 1 l: pwr_cr_eq_x86_zf $end -$var wire 1 m: pwr_so $end +$var wire 1 s< pwr_ca_x86_cf $end +$var wire 1 t< pwr_ca32_x86_af $end +$var wire 1 u< pwr_ov_x86_of $end +$var wire 1 v< pwr_ov32_x86_df $end +$var wire 1 w< pwr_cr_lt_x86_sf $end +$var wire 1 x< pwr_cr_gt_x86_pf $end +$var wire 1 y< pwr_cr_eq_x86_zf $end +$var wire 1 z< pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end -$var wire 1 n: ready $end +$var wire 1 {< ready $end $upscope $end $scope struct execute_end $end -$var string 1 o: \$tag $end +$var string 1 |< \$tag $end $scope struct HdlSome $end $scope struct unit_output $end $scope struct which $end -$var wire 4 p: value $end +$var wire 4 }< value $end $upscope $end $scope struct result $end -$var string 1 q: \$tag $end +$var string 1 ~< \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 r: int_fp $end +$var wire 64 != int_fp $end $scope struct flags $end -$var wire 1 s: pwr_ca_x86_cf $end -$var wire 1 t: pwr_ca32_x86_af $end -$var wire 1 u: pwr_ov_x86_of $end -$var wire 1 v: pwr_ov32_x86_df $end -$var wire 1 w: pwr_cr_lt_x86_sf $end -$var wire 1 x: pwr_cr_gt_x86_pf $end -$var wire 1 y: pwr_cr_eq_x86_zf $end -$var wire 1 z: pwr_so $end +$var wire 1 "= pwr_ca_x86_cf $end +$var wire 1 #= pwr_ca32_x86_af $end +$var wire 1 $= pwr_ov_x86_of $end +$var wire 1 %= pwr_ov32_x86_df $end +$var wire 1 &= pwr_cr_lt_x86_sf $end +$var wire 1 '= pwr_cr_gt_x86_pf $end +$var wire 1 (= pwr_cr_eq_x86_zf $end +$var wire 1 )= pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -6267,50 +6358,50 @@ $upscope $end $upscope $end $scope module unit_base_2 $end $scope struct cd $end -$var wire 1 J, clk $end -$var wire 1 K, rst $end +$var wire 1 e, clk $end +$var wire 1 f, rst $end $upscope $end $scope struct unit_to_reg_alloc $end $scope struct unit_forwarding_info $end $scope struct unit_output_writes $end $scope struct \[0] $end -$var string 1 L, \$tag $end +$var string 1 g, \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 M, value $end +$var wire 4 h, value $end $upscope $end $scope struct value $end -$var wire 64 N, int_fp $end +$var wire 64 i, int_fp $end $scope struct flags $end -$var wire 1 O, pwr_ca_x86_cf $end -$var wire 1 P, pwr_ca32_x86_af $end -$var wire 1 Q, pwr_ov_x86_of $end -$var wire 1 R, pwr_ov32_x86_df $end -$var wire 1 S, pwr_cr_lt_x86_sf $end -$var wire 1 T, pwr_cr_gt_x86_pf $end -$var wire 1 U, pwr_cr_eq_x86_zf $end -$var wire 1 V, pwr_so $end +$var wire 1 j, pwr_ca_x86_cf $end +$var wire 1 k, pwr_ca32_x86_af $end +$var wire 1 l, pwr_ov_x86_of $end +$var wire 1 m, pwr_ov32_x86_df $end +$var wire 1 n, pwr_cr_lt_x86_sf $end +$var wire 1 o, pwr_cr_gt_x86_pf $end +$var wire 1 p, pwr_cr_eq_x86_zf $end +$var wire 1 q, pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 W, \$tag $end +$var string 1 r, \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 X, value $end +$var wire 4 s, value $end $upscope $end $scope struct value $end -$var wire 64 Y, int_fp $end +$var wire 64 t, int_fp $end $scope struct flags $end -$var wire 1 Z, pwr_ca_x86_cf $end -$var wire 1 [, pwr_ca32_x86_af $end -$var wire 1 \, pwr_ov_x86_of $end -$var wire 1 ], pwr_ov32_x86_df $end -$var wire 1 ^, pwr_cr_lt_x86_sf $end -$var wire 1 _, pwr_cr_gt_x86_pf $end -$var wire 1 `, pwr_cr_eq_x86_zf $end -$var wire 1 a, pwr_so $end +$var wire 1 u, pwr_ca_x86_cf $end +$var wire 1 v, pwr_ca32_x86_af $end +$var wire 1 w, pwr_ov_x86_of $end +$var wire 1 x, pwr_ov32_x86_df $end +$var wire 1 y, pwr_cr_lt_x86_sf $end +$var wire 1 z, pwr_cr_gt_x86_pf $end +$var wire 1 {, pwr_cr_eq_x86_zf $end +$var wire 1 |, pwr_so $end $upscope $end $upscope $end $upscope $end @@ -6319,112 +6410,115 @@ $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end +$scope struct input $end $scope struct data $end -$var string 1 b, \$tag $end +$var string 1 }, \$tag $end $scope struct HdlSome $end -$var string 1 c, \$tag $end +$scope struct mop $end +$var string 1 ~, \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 d, prefix_pad $end +$var string 0 !- prefix_pad $end $scope struct dest $end -$var wire 4 e, value $end +$var wire 4 "- value $end $upscope $end $scope struct src $end -$var wire 6 f, \[0] $end -$var wire 6 g, \[1] $end -$var wire 6 h, \[2] $end +$var wire 6 #- \[0] $end +$var wire 6 $- \[1] $end +$var wire 6 %- \[2] $end $upscope $end -$var wire 25 i, imm_low $end -$var wire 1 j, imm_sign $end +$var wire 25 &- imm_low $end +$var wire 1 '- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 k, output_integer_mode $end +$var string 1 (- output_integer_mode $end $upscope $end -$var wire 1 l, invert_src0 $end -$var wire 1 m, invert_carry_in $end -$var wire 1 n, invert_carry_out $end -$var wire 1 o, add_pc $end +$var wire 1 )- invert_src0 $end +$var wire 1 *- src1_is_carry_in $end +$var wire 1 +- invert_carry_in $end +$var wire 1 ,- add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 p, prefix_pad $end +$var string 0 -- prefix_pad $end $scope struct dest $end -$var wire 4 q, value $end +$var wire 4 .- value $end $upscope $end $scope struct src $end -$var wire 6 r, \[0] $end -$var wire 6 s, \[1] $end -$var wire 6 t, \[2] $end +$var wire 6 /- \[0] $end +$var wire 6 0- \[1] $end +$var wire 6 1- \[2] $end $upscope $end -$var wire 25 u, imm_low $end -$var wire 1 v, imm_sign $end +$var wire 25 2- imm_low $end +$var wire 1 3- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 w, output_integer_mode $end +$var string 1 4- output_integer_mode $end $upscope $end -$var wire 1 x, invert_src0 $end -$var wire 1 y, invert_carry_in $end -$var wire 1 z, invert_carry_out $end -$var wire 1 {, add_pc $end +$var wire 1 5- invert_src0 $end +$var wire 1 6- src1_is_carry_in $end +$var wire 1 7- invert_carry_in $end +$var wire 1 8- add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 |, prefix_pad $end +$var string 0 9- prefix_pad $end $scope struct dest $end -$var wire 4 }, value $end +$var wire 4 :- value $end $upscope $end $scope struct src $end -$var wire 6 ~, \[0] $end -$var wire 6 !- \[1] $end -$var wire 6 "- \[2] $end +$var wire 6 ;- \[0] $end +$var wire 6 <- \[1] $end +$var wire 6 =- \[2] $end $upscope $end -$var wire 25 #- imm_low $end -$var wire 1 $- imm_sign $end +$var wire 25 >- imm_low $end +$var wire 1 ?- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 %- output_integer_mode $end +$var string 1 @- output_integer_mode $end $upscope $end -$var wire 4 &- lut $end +$var wire 4 A- lut $end $upscope $end $upscope $end +$var wire 64 B- pc $end $upscope $end -$var wire 1 '- ready $end +$upscope $end +$var wire 1 C- ready $end $upscope $end $scope struct cancel_input $end -$var string 1 (- \$tag $end +$var string 1 D- \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 )- value $end +$var wire 4 E- value $end $upscope $end $upscope $end $upscope $end $scope struct output $end -$var string 1 *- \$tag $end +$var string 1 F- \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 +- value $end +$var wire 4 G- value $end $upscope $end $scope struct result $end -$var string 1 ,- \$tag $end +$var string 1 H- \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 -- int_fp $end +$var wire 64 I- int_fp $end $scope struct flags $end -$var wire 1 .- pwr_ca_x86_cf $end -$var wire 1 /- pwr_ca32_x86_af $end -$var wire 1 0- pwr_ov_x86_of $end -$var wire 1 1- pwr_ov32_x86_df $end -$var wire 1 2- pwr_cr_lt_x86_sf $end -$var wire 1 3- pwr_cr_gt_x86_pf $end -$var wire 1 4- pwr_cr_eq_x86_zf $end -$var wire 1 5- pwr_so $end +$var wire 1 J- pwr_ca_x86_cf $end +$var wire 1 K- pwr_ca32_x86_af $end +$var wire 1 L- pwr_ov_x86_of $end +$var wire 1 M- pwr_ov32_x86_df $end +$var wire 1 N- pwr_cr_lt_x86_sf $end +$var wire 1 O- pwr_cr_gt_x86_pf $end +$var wire 1 P- pwr_cr_eq_x86_zf $end +$var wire 1 Q- pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -6438,146 +6532,147 @@ $upscope $end $upscope $end $scope struct execute_start $end $scope struct data $end -$var string 1 6- \$tag $end +$var string 1 R- \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 7- \$tag $end +$var string 1 S- \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 8- prefix_pad $end +$var string 0 T- prefix_pad $end $scope struct dest $end -$var wire 4 9- value $end +$var wire 4 U- value $end $upscope $end $scope struct src $end -$var wire 6 :- \[0] $end -$var wire 6 ;- \[1] $end -$var wire 6 <- \[2] $end +$var wire 6 V- \[0] $end +$var wire 6 W- \[1] $end +$var wire 6 X- \[2] $end $upscope $end -$var wire 25 =- imm_low $end -$var wire 1 >- imm_sign $end +$var wire 25 Y- imm_low $end +$var wire 1 Z- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 ?- output_integer_mode $end +$var string 1 [- output_integer_mode $end $upscope $end -$var wire 1 @- invert_src0 $end -$var wire 1 A- invert_carry_in $end -$var wire 1 B- invert_carry_out $end -$var wire 1 C- add_pc $end +$var wire 1 \- invert_src0 $end +$var wire 1 ]- src1_is_carry_in $end +$var wire 1 ^- invert_carry_in $end +$var wire 1 _- add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 D- prefix_pad $end +$var string 0 `- prefix_pad $end $scope struct dest $end -$var wire 4 E- value $end +$var wire 4 a- value $end $upscope $end $scope struct src $end -$var wire 6 F- \[0] $end -$var wire 6 G- \[1] $end -$var wire 6 H- \[2] $end +$var wire 6 b- \[0] $end +$var wire 6 c- \[1] $end +$var wire 6 d- \[2] $end $upscope $end -$var wire 25 I- imm_low $end -$var wire 1 J- imm_sign $end +$var wire 25 e- imm_low $end +$var wire 1 f- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 K- output_integer_mode $end +$var string 1 g- output_integer_mode $end $upscope $end -$var wire 1 L- invert_src0 $end -$var wire 1 M- invert_carry_in $end -$var wire 1 N- invert_carry_out $end -$var wire 1 O- add_pc $end +$var wire 1 h- invert_src0 $end +$var wire 1 i- src1_is_carry_in $end +$var wire 1 j- invert_carry_in $end +$var wire 1 k- add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 P- prefix_pad $end +$var string 0 l- prefix_pad $end $scope struct dest $end -$var wire 4 Q- value $end +$var wire 4 m- value $end $upscope $end $scope struct src $end -$var wire 6 R- \[0] $end -$var wire 6 S- \[1] $end -$var wire 6 T- \[2] $end +$var wire 6 n- \[0] $end +$var wire 6 o- \[1] $end +$var wire 6 p- \[2] $end $upscope $end -$var wire 25 U- imm_low $end -$var wire 1 V- imm_sign $end +$var wire 25 q- imm_low $end +$var wire 1 r- imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 W- output_integer_mode $end +$var string 1 s- output_integer_mode $end $upscope $end -$var wire 4 X- lut $end +$var wire 4 t- lut $end $upscope $end $upscope $end +$var wire 64 u- pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 Y- int_fp $end +$var wire 64 v- int_fp $end $scope struct flags $end -$var wire 1 Z- pwr_ca_x86_cf $end -$var wire 1 [- pwr_ca32_x86_af $end -$var wire 1 \- pwr_ov_x86_of $end -$var wire 1 ]- pwr_ov32_x86_df $end -$var wire 1 ^- pwr_cr_lt_x86_sf $end -$var wire 1 _- pwr_cr_gt_x86_pf $end -$var wire 1 `- pwr_cr_eq_x86_zf $end -$var wire 1 a- pwr_so $end +$var wire 1 w- pwr_ca_x86_cf $end +$var wire 1 x- pwr_ca32_x86_af $end +$var wire 1 y- pwr_ov_x86_of $end +$var wire 1 z- pwr_ov32_x86_df $end +$var wire 1 {- pwr_cr_lt_x86_sf $end +$var wire 1 |- pwr_cr_gt_x86_pf $end +$var wire 1 }- pwr_cr_eq_x86_zf $end +$var wire 1 ~- pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 b- int_fp $end +$var wire 64 !. int_fp $end $scope struct flags $end -$var wire 1 c- pwr_ca_x86_cf $end -$var wire 1 d- pwr_ca32_x86_af $end -$var wire 1 e- pwr_ov_x86_of $end -$var wire 1 f- pwr_ov32_x86_df $end -$var wire 1 g- pwr_cr_lt_x86_sf $end -$var wire 1 h- pwr_cr_gt_x86_pf $end -$var wire 1 i- pwr_cr_eq_x86_zf $end -$var wire 1 j- pwr_so $end +$var wire 1 ". pwr_ca_x86_cf $end +$var wire 1 #. pwr_ca32_x86_af $end +$var wire 1 $. pwr_ov_x86_of $end +$var wire 1 %. pwr_ov32_x86_df $end +$var wire 1 &. pwr_cr_lt_x86_sf $end +$var wire 1 '. pwr_cr_gt_x86_pf $end +$var wire 1 (. pwr_cr_eq_x86_zf $end +$var wire 1 ). pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 k- int_fp $end +$var wire 64 *. int_fp $end $scope struct flags $end -$var wire 1 l- pwr_ca_x86_cf $end -$var wire 1 m- pwr_ca32_x86_af $end -$var wire 1 n- pwr_ov_x86_of $end -$var wire 1 o- pwr_ov32_x86_df $end -$var wire 1 p- pwr_cr_lt_x86_sf $end -$var wire 1 q- pwr_cr_gt_x86_pf $end -$var wire 1 r- pwr_cr_eq_x86_zf $end -$var wire 1 s- pwr_so $end +$var wire 1 +. pwr_ca_x86_cf $end +$var wire 1 ,. pwr_ca32_x86_af $end +$var wire 1 -. pwr_ov_x86_of $end +$var wire 1 .. pwr_ov32_x86_df $end +$var wire 1 /. pwr_cr_lt_x86_sf $end +$var wire 1 0. pwr_cr_gt_x86_pf $end +$var wire 1 1. pwr_cr_eq_x86_zf $end +$var wire 1 2. pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end -$var wire 1 t- ready $end +$var wire 1 3. ready $end $upscope $end $scope struct execute_end $end -$var string 1 u- \$tag $end +$var string 1 4. \$tag $end $scope struct HdlSome $end $scope struct unit_output $end $scope struct which $end -$var wire 4 v- value $end +$var wire 4 5. value $end $upscope $end $scope struct result $end -$var string 1 w- \$tag $end +$var string 1 6. \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 x- int_fp $end +$var wire 64 7. int_fp $end $scope struct flags $end -$var wire 1 y- pwr_ca_x86_cf $end -$var wire 1 z- pwr_ca32_x86_af $end -$var wire 1 {- pwr_ov_x86_of $end -$var wire 1 |- pwr_ov32_x86_df $end -$var wire 1 }- pwr_cr_lt_x86_sf $end -$var wire 1 ~- pwr_cr_gt_x86_pf $end -$var wire 1 !. pwr_cr_eq_x86_zf $end -$var wire 1 ". pwr_so $end +$var wire 1 8. pwr_ca_x86_cf $end +$var wire 1 9. pwr_ca32_x86_af $end +$var wire 1 :. pwr_ov_x86_of $end +$var wire 1 ;. pwr_ov32_x86_df $end +$var wire 1 <. pwr_cr_lt_x86_sf $end +$var wire 1 =. pwr_cr_gt_x86_pf $end +$var wire 1 >. pwr_cr_eq_x86_zf $end +$var wire 1 ?. pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -6589,431 +6684,782 @@ $upscope $end $upscope $end $upscope $end $upscope $end -$scope struct in_flight_ops $end +$scope struct unit_0_output_regs $end +$scope struct contents $end $scope struct \[0] $end -$var string 1 #. \$tag $end -$scope struct HdlSome $end -$var string 1 $. state $end -$scope struct mop $end -$var string 1 %. \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 &. prefix_pad $end -$scope struct dest $end -$var reg 4 '. value $end -$upscope $end -$scope struct src $end -$var reg 6 (. \[0] $end -$var reg 6 ). \[1] $end -$var reg 6 *. \[2] $end -$upscope $end -$var reg 25 +. imm_low $end -$var reg 1 ,. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 -. output_integer_mode $end -$upscope $end -$var reg 1 .. invert_src0 $end -$var reg 1 /. invert_carry_in $end -$var reg 1 0. invert_carry_out $end -$var reg 1 1. add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 2. prefix_pad $end -$scope struct dest $end -$var reg 4 3. value $end -$upscope $end -$scope struct src $end -$var reg 6 4. \[0] $end -$var reg 6 5. \[1] $end -$var reg 6 6. \[2] $end -$upscope $end -$var reg 25 7. imm_low $end -$var reg 1 8. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 9. output_integer_mode $end -$upscope $end -$var reg 1 :. invert_src0 $end -$var reg 1 ;. invert_carry_in $end -$var reg 1 <. invert_carry_out $end -$var reg 1 =. add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 >. prefix_pad $end -$scope struct dest $end -$var reg 4 ?. value $end -$upscope $end -$scope struct src $end -$var reg 6 @. \[0] $end -$var reg 6 A. \[1] $end -$var reg 6 B. \[2] $end -$upscope $end -$var reg 25 C. imm_low $end -$var reg 1 D. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 E. output_integer_mode $end -$upscope $end -$var reg 4 F. lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 G. \[0] $end -$var reg 1 H. \[1] $end -$var reg 1 I. \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 U^ int_fp $end +$scope struct flags $end +$var reg 1 e^ pwr_ca_x86_cf $end +$var reg 1 u^ pwr_ca32_x86_af $end +$var reg 1 '_ pwr_ov_x86_of $end +$var reg 1 7_ pwr_ov32_x86_df $end +$var reg 1 G_ pwr_cr_lt_x86_sf $end +$var reg 1 W_ pwr_cr_gt_x86_pf $end +$var reg 1 g_ pwr_cr_eq_x86_zf $end +$var reg 1 w_ pwr_so $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 J. \$tag $end -$scope struct HdlSome $end -$var string 1 K. state $end -$scope struct mop $end -$var string 1 L. \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 M. prefix_pad $end -$scope struct dest $end -$var reg 4 N. value $end -$upscope $end -$scope struct src $end -$var reg 6 O. \[0] $end -$var reg 6 P. \[1] $end -$var reg 6 Q. \[2] $end -$upscope $end -$var reg 25 R. imm_low $end -$var reg 1 S. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 T. output_integer_mode $end -$upscope $end -$var reg 1 U. invert_src0 $end -$var reg 1 V. invert_carry_in $end -$var reg 1 W. invert_carry_out $end -$var reg 1 X. add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 Y. prefix_pad $end -$scope struct dest $end -$var reg 4 Z. value $end -$upscope $end -$scope struct src $end -$var reg 6 [. \[0] $end -$var reg 6 \. \[1] $end -$var reg 6 ]. \[2] $end -$upscope $end -$var reg 25 ^. imm_low $end -$var reg 1 _. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 `. output_integer_mode $end -$upscope $end -$var reg 1 a. invert_src0 $end -$var reg 1 b. invert_carry_in $end -$var reg 1 c. invert_carry_out $end -$var reg 1 d. add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 e. prefix_pad $end -$scope struct dest $end -$var reg 4 f. value $end -$upscope $end -$scope struct src $end -$var reg 6 g. \[0] $end -$var reg 6 h. \[1] $end -$var reg 6 i. \[2] $end -$upscope $end -$var reg 25 j. imm_low $end -$var reg 1 k. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 l. output_integer_mode $end -$upscope $end -$var reg 4 m. lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 n. \[0] $end -$var reg 1 o. \[1] $end -$var reg 1 p. \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 V^ int_fp $end +$scope struct flags $end +$var reg 1 f^ pwr_ca_x86_cf $end +$var reg 1 v^ pwr_ca32_x86_af $end +$var reg 1 (_ pwr_ov_x86_of $end +$var reg 1 8_ pwr_ov32_x86_df $end +$var reg 1 H_ pwr_cr_lt_x86_sf $end +$var reg 1 X_ pwr_cr_gt_x86_pf $end +$var reg 1 h_ pwr_cr_eq_x86_zf $end +$var reg 1 x_ pwr_so $end $upscope $end $upscope $end $upscope $end $scope struct \[2] $end -$var string 1 q. \$tag $end -$scope struct HdlSome $end -$var string 1 r. state $end -$scope struct mop $end -$var string 1 s. \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 t. prefix_pad $end -$scope struct dest $end -$var reg 4 u. value $end -$upscope $end -$scope struct src $end -$var reg 6 v. \[0] $end -$var reg 6 w. \[1] $end -$var reg 6 x. \[2] $end -$upscope $end -$var reg 25 y. imm_low $end -$var reg 1 z. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 {. output_integer_mode $end -$upscope $end -$var reg 1 |. invert_src0 $end -$var reg 1 }. invert_carry_in $end -$var reg 1 ~. invert_carry_out $end -$var reg 1 !/ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 "/ prefix_pad $end -$scope struct dest $end -$var reg 4 #/ value $end -$upscope $end -$scope struct src $end -$var reg 6 $/ \[0] $end -$var reg 6 %/ \[1] $end -$var reg 6 &/ \[2] $end -$upscope $end -$var reg 25 '/ imm_low $end -$var reg 1 (/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 )/ output_integer_mode $end -$upscope $end -$var reg 1 */ invert_src0 $end -$var reg 1 +/ invert_carry_in $end -$var reg 1 ,/ invert_carry_out $end -$var reg 1 -/ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ./ prefix_pad $end -$scope struct dest $end -$var reg 4 // value $end -$upscope $end -$scope struct src $end -$var reg 6 0/ \[0] $end -$var reg 6 1/ \[1] $end -$var reg 6 2/ \[2] $end -$upscope $end -$var reg 25 3/ imm_low $end -$var reg 1 4/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 5/ output_integer_mode $end -$upscope $end -$var reg 4 6/ lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 7/ \[0] $end -$var reg 1 8/ \[1] $end -$var reg 1 9/ \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 W^ int_fp $end +$scope struct flags $end +$var reg 1 g^ pwr_ca_x86_cf $end +$var reg 1 w^ pwr_ca32_x86_af $end +$var reg 1 )_ pwr_ov_x86_of $end +$var reg 1 9_ pwr_ov32_x86_df $end +$var reg 1 I_ pwr_cr_lt_x86_sf $end +$var reg 1 Y_ pwr_cr_gt_x86_pf $end +$var reg 1 i_ pwr_cr_eq_x86_zf $end +$var reg 1 y_ pwr_so $end $upscope $end $upscope $end $upscope $end $scope struct \[3] $end -$var string 1 :/ \$tag $end -$scope struct HdlSome $end -$var string 1 ;/ state $end -$scope struct mop $end -$var string 1 / value $end -$upscope $end -$scope struct src $end -$var reg 6 ?/ \[0] $end -$var reg 6 @/ \[1] $end -$var reg 6 A/ \[2] $end -$upscope $end -$var reg 25 B/ imm_low $end -$var reg 1 C/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 D/ output_integer_mode $end -$upscope $end -$var reg 1 E/ invert_src0 $end -$var reg 1 F/ invert_carry_in $end -$var reg 1 G/ invert_carry_out $end -$var reg 1 H/ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 I/ prefix_pad $end -$scope struct dest $end -$var reg 4 J/ value $end -$upscope $end -$scope struct src $end -$var reg 6 K/ \[0] $end -$var reg 6 L/ \[1] $end -$var reg 6 M/ \[2] $end -$upscope $end -$var reg 25 N/ imm_low $end -$var reg 1 O/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 P/ output_integer_mode $end -$upscope $end -$var reg 1 Q/ invert_src0 $end -$var reg 1 R/ invert_carry_in $end -$var reg 1 S/ invert_carry_out $end -$var reg 1 T/ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 U/ prefix_pad $end -$scope struct dest $end -$var reg 4 V/ value $end -$upscope $end -$scope struct src $end -$var reg 6 W/ \[0] $end -$var reg 6 X/ \[1] $end -$var reg 6 Y/ \[2] $end -$upscope $end -$var reg 25 Z/ imm_low $end -$var reg 1 [/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 \/ output_integer_mode $end -$upscope $end -$var reg 4 ]/ lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 ^/ \[0] $end -$var reg 1 _/ \[1] $end -$var reg 1 `/ \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 X^ int_fp $end +$scope struct flags $end +$var reg 1 h^ pwr_ca_x86_cf $end +$var reg 1 x^ pwr_ca32_x86_af $end +$var reg 1 *_ pwr_ov_x86_of $end +$var reg 1 :_ pwr_ov32_x86_df $end +$var reg 1 J_ pwr_cr_lt_x86_sf $end +$var reg 1 Z_ pwr_cr_gt_x86_pf $end +$var reg 1 j_ pwr_cr_eq_x86_zf $end +$var reg 1 z_ pwr_so $end $upscope $end $upscope $end $upscope $end $scope struct \[4] $end -$var string 1 a/ \$tag $end -$scope struct HdlSome $end -$var string 1 b/ state $end -$scope struct mop $end -$var string 1 c/ \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 d/ prefix_pad $end -$scope struct dest $end -$var reg 4 e/ value $end -$upscope $end -$scope struct src $end -$var reg 6 f/ \[0] $end -$var reg 6 g/ \[1] $end -$var reg 6 h/ \[2] $end -$upscope $end -$var reg 25 i/ imm_low $end -$var reg 1 j/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 k/ output_integer_mode $end -$upscope $end -$var reg 1 l/ invert_src0 $end -$var reg 1 m/ invert_carry_in $end -$var reg 1 n/ invert_carry_out $end -$var reg 1 o/ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 p/ prefix_pad $end -$scope struct dest $end -$var reg 4 q/ value $end -$upscope $end -$scope struct src $end -$var reg 6 r/ \[0] $end -$var reg 6 s/ \[1] $end -$var reg 6 t/ \[2] $end -$upscope $end -$var reg 25 u/ imm_low $end -$var reg 1 v/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 w/ output_integer_mode $end -$upscope $end -$var reg 1 x/ invert_src0 $end -$var reg 1 y/ invert_carry_in $end -$var reg 1 z/ invert_carry_out $end -$var reg 1 {/ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 |/ prefix_pad $end -$scope struct dest $end -$var reg 4 }/ value $end -$upscope $end -$scope struct src $end -$var reg 6 ~/ \[0] $end -$var reg 6 !0 \[1] $end -$var reg 6 "0 \[2] $end -$upscope $end -$var reg 25 #0 imm_low $end -$var reg 1 $0 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 %0 output_integer_mode $end -$upscope $end -$var reg 4 &0 lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 '0 \[0] $end -$var reg 1 (0 \[1] $end -$var reg 1 )0 \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 Y^ int_fp $end +$scope struct flags $end +$var reg 1 i^ pwr_ca_x86_cf $end +$var reg 1 y^ pwr_ca32_x86_af $end +$var reg 1 +_ pwr_ov_x86_of $end +$var reg 1 ;_ pwr_ov32_x86_df $end +$var reg 1 K_ pwr_cr_lt_x86_sf $end +$var reg 1 [_ pwr_cr_gt_x86_pf $end +$var reg 1 k_ pwr_cr_eq_x86_zf $end +$var reg 1 {_ pwr_so $end $upscope $end $upscope $end $upscope $end $scope struct \[5] $end -$var string 1 *0 \$tag $end +$scope struct unit_0_output_regs $end +$var reg 64 Z^ int_fp $end +$scope struct flags $end +$var reg 1 j^ pwr_ca_x86_cf $end +$var reg 1 z^ pwr_ca32_x86_af $end +$var reg 1 ,_ pwr_ov_x86_of $end +$var reg 1 <_ pwr_ov32_x86_df $end +$var reg 1 L_ pwr_cr_lt_x86_sf $end +$var reg 1 \_ pwr_cr_gt_x86_pf $end +$var reg 1 l_ pwr_cr_eq_x86_zf $end +$var reg 1 |_ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$scope struct unit_0_output_regs $end +$var reg 64 [^ int_fp $end +$scope struct flags $end +$var reg 1 k^ pwr_ca_x86_cf $end +$var reg 1 {^ pwr_ca32_x86_af $end +$var reg 1 -_ pwr_ov_x86_of $end +$var reg 1 =_ pwr_ov32_x86_df $end +$var reg 1 M_ pwr_cr_lt_x86_sf $end +$var reg 1 ]_ pwr_cr_gt_x86_pf $end +$var reg 1 m_ pwr_cr_eq_x86_zf $end +$var reg 1 }_ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$scope struct unit_0_output_regs $end +$var reg 64 \^ int_fp $end +$scope struct flags $end +$var reg 1 l^ pwr_ca_x86_cf $end +$var reg 1 |^ pwr_ca32_x86_af $end +$var reg 1 ._ pwr_ov_x86_of $end +$var reg 1 >_ pwr_ov32_x86_df $end +$var reg 1 N_ pwr_cr_lt_x86_sf $end +$var reg 1 ^_ pwr_cr_gt_x86_pf $end +$var reg 1 n_ pwr_cr_eq_x86_zf $end +$var reg 1 ~_ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$scope struct unit_0_output_regs $end +$var reg 64 ]^ int_fp $end +$scope struct flags $end +$var reg 1 m^ pwr_ca_x86_cf $end +$var reg 1 }^ pwr_ca32_x86_af $end +$var reg 1 /_ pwr_ov_x86_of $end +$var reg 1 ?_ pwr_ov32_x86_df $end +$var reg 1 O_ pwr_cr_lt_x86_sf $end +$var reg 1 __ pwr_cr_gt_x86_pf $end +$var reg 1 o_ pwr_cr_eq_x86_zf $end +$var reg 1 !` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$scope struct unit_0_output_regs $end +$var reg 64 ^^ int_fp $end +$scope struct flags $end +$var reg 1 n^ pwr_ca_x86_cf $end +$var reg 1 ~^ pwr_ca32_x86_af $end +$var reg 1 0_ pwr_ov_x86_of $end +$var reg 1 @_ pwr_ov32_x86_df $end +$var reg 1 P_ pwr_cr_lt_x86_sf $end +$var reg 1 `_ pwr_cr_gt_x86_pf $end +$var reg 1 p_ pwr_cr_eq_x86_zf $end +$var reg 1 "` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$scope struct unit_0_output_regs $end +$var reg 64 _^ int_fp $end +$scope struct flags $end +$var reg 1 o^ pwr_ca_x86_cf $end +$var reg 1 !_ pwr_ca32_x86_af $end +$var reg 1 1_ pwr_ov_x86_of $end +$var reg 1 A_ pwr_ov32_x86_df $end +$var reg 1 Q_ pwr_cr_lt_x86_sf $end +$var reg 1 a_ pwr_cr_gt_x86_pf $end +$var reg 1 q_ pwr_cr_eq_x86_zf $end +$var reg 1 #` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$scope struct unit_0_output_regs $end +$var reg 64 `^ int_fp $end +$scope struct flags $end +$var reg 1 p^ pwr_ca_x86_cf $end +$var reg 1 "_ pwr_ca32_x86_af $end +$var reg 1 2_ pwr_ov_x86_of $end +$var reg 1 B_ pwr_ov32_x86_df $end +$var reg 1 R_ pwr_cr_lt_x86_sf $end +$var reg 1 b_ pwr_cr_gt_x86_pf $end +$var reg 1 r_ pwr_cr_eq_x86_zf $end +$var reg 1 $` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$scope struct unit_0_output_regs $end +$var reg 64 a^ int_fp $end +$scope struct flags $end +$var reg 1 q^ pwr_ca_x86_cf $end +$var reg 1 #_ pwr_ca32_x86_af $end +$var reg 1 3_ pwr_ov_x86_of $end +$var reg 1 C_ pwr_ov32_x86_df $end +$var reg 1 S_ pwr_cr_lt_x86_sf $end +$var reg 1 c_ pwr_cr_gt_x86_pf $end +$var reg 1 s_ pwr_cr_eq_x86_zf $end +$var reg 1 %` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$scope struct unit_0_output_regs $end +$var reg 64 b^ int_fp $end +$scope struct flags $end +$var reg 1 r^ pwr_ca_x86_cf $end +$var reg 1 $_ pwr_ca32_x86_af $end +$var reg 1 4_ pwr_ov_x86_of $end +$var reg 1 D_ pwr_ov32_x86_df $end +$var reg 1 T_ pwr_cr_lt_x86_sf $end +$var reg 1 d_ pwr_cr_gt_x86_pf $end +$var reg 1 t_ pwr_cr_eq_x86_zf $end +$var reg 1 &` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$scope struct unit_0_output_regs $end +$var reg 64 c^ int_fp $end +$scope struct flags $end +$var reg 1 s^ pwr_ca_x86_cf $end +$var reg 1 %_ pwr_ca32_x86_af $end +$var reg 1 5_ pwr_ov_x86_of $end +$var reg 1 E_ pwr_ov32_x86_df $end +$var reg 1 U_ pwr_cr_lt_x86_sf $end +$var reg 1 e_ pwr_cr_gt_x86_pf $end +$var reg 1 u_ pwr_cr_eq_x86_zf $end +$var reg 1 '` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$scope struct unit_0_output_regs $end +$var reg 64 d^ int_fp $end +$scope struct flags $end +$var reg 1 t^ pwr_ca_x86_cf $end +$var reg 1 &_ pwr_ca32_x86_af $end +$var reg 1 6_ pwr_ov_x86_of $end +$var reg 1 F_ pwr_ov32_x86_df $end +$var reg 1 V_ pwr_cr_lt_x86_sf $end +$var reg 1 f_ pwr_cr_gt_x86_pf $end +$var reg 1 v_ pwr_cr_eq_x86_zf $end +$var reg 1 (` pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 @. addr $end +$var wire 1 A. en $end +$var wire 1 B. clk $end +$scope struct data $end +$var wire 64 C. int_fp $end +$scope struct flags $end +$var wire 1 D. pwr_ca_x86_cf $end +$var wire 1 E. pwr_ca32_x86_af $end +$var wire 1 F. pwr_ov_x86_of $end +$var wire 1 G. pwr_ov32_x86_df $end +$var wire 1 H. pwr_cr_lt_x86_sf $end +$var wire 1 I. pwr_cr_gt_x86_pf $end +$var wire 1 J. pwr_cr_eq_x86_zf $end +$var wire 1 K. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r1 $end +$var wire 4 L. addr $end +$var wire 1 M. en $end +$var wire 1 N. clk $end +$scope struct data $end +$var wire 64 O. int_fp $end +$scope struct flags $end +$var wire 1 P. pwr_ca_x86_cf $end +$var wire 1 Q. pwr_ca32_x86_af $end +$var wire 1 R. pwr_ov_x86_of $end +$var wire 1 S. pwr_ov32_x86_df $end +$var wire 1 T. pwr_cr_lt_x86_sf $end +$var wire 1 U. pwr_cr_gt_x86_pf $end +$var wire 1 V. pwr_cr_eq_x86_zf $end +$var wire 1 W. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r2 $end +$var wire 4 X. addr $end +$var wire 1 Y. en $end +$var wire 1 Z. clk $end +$scope struct data $end +$var wire 64 [. int_fp $end +$scope struct flags $end +$var wire 1 \. pwr_ca_x86_cf $end +$var wire 1 ]. pwr_ca32_x86_af $end +$var wire 1 ^. pwr_ov_x86_of $end +$var wire 1 _. pwr_ov32_x86_df $end +$var wire 1 `. pwr_cr_lt_x86_sf $end +$var wire 1 a. pwr_cr_gt_x86_pf $end +$var wire 1 b. pwr_cr_eq_x86_zf $end +$var wire 1 c. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct w3 $end +$var wire 4 d. addr $end +$var wire 1 e. en $end +$var wire 1 f. clk $end +$scope struct data $end +$var wire 64 g. int_fp $end +$scope struct flags $end +$var wire 1 h. pwr_ca_x86_cf $end +$var wire 1 i. pwr_ca32_x86_af $end +$var wire 1 j. pwr_ov_x86_of $end +$var wire 1 k. pwr_ov32_x86_df $end +$var wire 1 l. pwr_cr_lt_x86_sf $end +$var wire 1 m. pwr_cr_gt_x86_pf $end +$var wire 1 n. pwr_cr_eq_x86_zf $end +$var wire 1 o. pwr_so $end +$upscope $end +$upscope $end +$scope struct mask $end +$var wire 1 p. int_fp $end +$scope struct flags $end +$var wire 1 q. pwr_ca_x86_cf $end +$var wire 1 r. pwr_ca32_x86_af $end +$var wire 1 s. pwr_ov_x86_of $end +$var wire 1 t. pwr_ov32_x86_df $end +$var wire 1 u. pwr_cr_lt_x86_sf $end +$var wire 1 v. pwr_cr_gt_x86_pf $end +$var wire 1 w. pwr_cr_eq_x86_zf $end +$var wire 1 x. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_1_output_regs $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct unit_1_output_regs $end +$var reg 64 )` int_fp $end +$scope struct flags $end +$var reg 1 9` pwr_ca_x86_cf $end +$var reg 1 I` pwr_ca32_x86_af $end +$var reg 1 Y` pwr_ov_x86_of $end +$var reg 1 i` pwr_ov32_x86_df $end +$var reg 1 y` pwr_cr_lt_x86_sf $end +$var reg 1 +a pwr_cr_gt_x86_pf $end +$var reg 1 ;a pwr_cr_eq_x86_zf $end +$var reg 1 Ka pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct unit_1_output_regs $end +$var reg 64 *` int_fp $end +$scope struct flags $end +$var reg 1 :` pwr_ca_x86_cf $end +$var reg 1 J` pwr_ca32_x86_af $end +$var reg 1 Z` pwr_ov_x86_of $end +$var reg 1 j` pwr_ov32_x86_df $end +$var reg 1 z` pwr_cr_lt_x86_sf $end +$var reg 1 ,a pwr_cr_gt_x86_pf $end +$var reg 1 a pwr_cr_eq_x86_zf $end +$var reg 1 Na pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$scope struct unit_1_output_regs $end +$var reg 64 -` int_fp $end +$scope struct flags $end +$var reg 1 =` pwr_ca_x86_cf $end +$var reg 1 M` pwr_ca32_x86_af $end +$var reg 1 ]` pwr_ov_x86_of $end +$var reg 1 m` pwr_ov32_x86_df $end +$var reg 1 }` pwr_cr_lt_x86_sf $end +$var reg 1 /a pwr_cr_gt_x86_pf $end +$var reg 1 ?a pwr_cr_eq_x86_zf $end +$var reg 1 Oa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$scope struct unit_1_output_regs $end +$var reg 64 .` int_fp $end +$scope struct flags $end +$var reg 1 >` pwr_ca_x86_cf $end +$var reg 1 N` pwr_ca32_x86_af $end +$var reg 1 ^` pwr_ov_x86_of $end +$var reg 1 n` pwr_ov32_x86_df $end +$var reg 1 ~` pwr_cr_lt_x86_sf $end +$var reg 1 0a pwr_cr_gt_x86_pf $end +$var reg 1 @a pwr_cr_eq_x86_zf $end +$var reg 1 Pa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$scope struct unit_1_output_regs $end +$var reg 64 /` int_fp $end +$scope struct flags $end +$var reg 1 ?` pwr_ca_x86_cf $end +$var reg 1 O` pwr_ca32_x86_af $end +$var reg 1 _` pwr_ov_x86_of $end +$var reg 1 o` pwr_ov32_x86_df $end +$var reg 1 !a pwr_cr_lt_x86_sf $end +$var reg 1 1a pwr_cr_gt_x86_pf $end +$var reg 1 Aa pwr_cr_eq_x86_zf $end +$var reg 1 Qa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$scope struct unit_1_output_regs $end +$var reg 64 0` int_fp $end +$scope struct flags $end +$var reg 1 @` pwr_ca_x86_cf $end +$var reg 1 P` pwr_ca32_x86_af $end +$var reg 1 `` pwr_ov_x86_of $end +$var reg 1 p` pwr_ov32_x86_df $end +$var reg 1 "a pwr_cr_lt_x86_sf $end +$var reg 1 2a pwr_cr_gt_x86_pf $end +$var reg 1 Ba pwr_cr_eq_x86_zf $end +$var reg 1 Ra pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$scope struct unit_1_output_regs $end +$var reg 64 1` int_fp $end +$scope struct flags $end +$var reg 1 A` pwr_ca_x86_cf $end +$var reg 1 Q` pwr_ca32_x86_af $end +$var reg 1 a` pwr_ov_x86_of $end +$var reg 1 q` pwr_ov32_x86_df $end +$var reg 1 #a pwr_cr_lt_x86_sf $end +$var reg 1 3a pwr_cr_gt_x86_pf $end +$var reg 1 Ca pwr_cr_eq_x86_zf $end +$var reg 1 Sa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$scope struct unit_1_output_regs $end +$var reg 64 2` int_fp $end +$scope struct flags $end +$var reg 1 B` pwr_ca_x86_cf $end +$var reg 1 R` pwr_ca32_x86_af $end +$var reg 1 b` pwr_ov_x86_of $end +$var reg 1 r` pwr_ov32_x86_df $end +$var reg 1 $a pwr_cr_lt_x86_sf $end +$var reg 1 4a pwr_cr_gt_x86_pf $end +$var reg 1 Da pwr_cr_eq_x86_zf $end +$var reg 1 Ta pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$scope struct unit_1_output_regs $end +$var reg 64 3` int_fp $end +$scope struct flags $end +$var reg 1 C` pwr_ca_x86_cf $end +$var reg 1 S` pwr_ca32_x86_af $end +$var reg 1 c` pwr_ov_x86_of $end +$var reg 1 s` pwr_ov32_x86_df $end +$var reg 1 %a pwr_cr_lt_x86_sf $end +$var reg 1 5a pwr_cr_gt_x86_pf $end +$var reg 1 Ea pwr_cr_eq_x86_zf $end +$var reg 1 Ua pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$scope struct unit_1_output_regs $end +$var reg 64 4` int_fp $end +$scope struct flags $end +$var reg 1 D` pwr_ca_x86_cf $end +$var reg 1 T` pwr_ca32_x86_af $end +$var reg 1 d` pwr_ov_x86_of $end +$var reg 1 t` pwr_ov32_x86_df $end +$var reg 1 &a pwr_cr_lt_x86_sf $end +$var reg 1 6a pwr_cr_gt_x86_pf $end +$var reg 1 Fa pwr_cr_eq_x86_zf $end +$var reg 1 Va pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$scope struct unit_1_output_regs $end +$var reg 64 5` int_fp $end +$scope struct flags $end +$var reg 1 E` pwr_ca_x86_cf $end +$var reg 1 U` pwr_ca32_x86_af $end +$var reg 1 e` pwr_ov_x86_of $end +$var reg 1 u` pwr_ov32_x86_df $end +$var reg 1 'a pwr_cr_lt_x86_sf $end +$var reg 1 7a pwr_cr_gt_x86_pf $end +$var reg 1 Ga pwr_cr_eq_x86_zf $end +$var reg 1 Wa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$scope struct unit_1_output_regs $end +$var reg 64 6` int_fp $end +$scope struct flags $end +$var reg 1 F` pwr_ca_x86_cf $end +$var reg 1 V` pwr_ca32_x86_af $end +$var reg 1 f` pwr_ov_x86_of $end +$var reg 1 v` pwr_ov32_x86_df $end +$var reg 1 (a pwr_cr_lt_x86_sf $end +$var reg 1 8a pwr_cr_gt_x86_pf $end +$var reg 1 Ha pwr_cr_eq_x86_zf $end +$var reg 1 Xa pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$scope struct unit_1_output_regs $end +$var reg 64 7` int_fp $end +$scope struct flags $end +$var reg 1 G` pwr_ca_x86_cf $end +$var reg 1 W` pwr_ca32_x86_af $end +$var reg 1 g` pwr_ov_x86_of $end +$var reg 1 w` pwr_ov32_x86_df $end +$var reg 1 )a pwr_cr_lt_x86_sf $end +$var reg 1 9a pwr_cr_gt_x86_pf $end +$var reg 1 Ia pwr_cr_eq_x86_zf $end +$var reg 1 Ya pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$scope struct unit_1_output_regs $end +$var reg 64 8` int_fp $end +$scope struct flags $end +$var reg 1 H` pwr_ca_x86_cf $end +$var reg 1 X` pwr_ca32_x86_af $end +$var reg 1 h` pwr_ov_x86_of $end +$var reg 1 x` pwr_ov32_x86_df $end +$var reg 1 *a pwr_cr_lt_x86_sf $end +$var reg 1 :a pwr_cr_gt_x86_pf $end +$var reg 1 Ja pwr_cr_eq_x86_zf $end +$var reg 1 Za pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 y. addr $end +$var wire 1 z. en $end +$var wire 1 {. clk $end +$scope struct data $end +$var wire 64 |. int_fp $end +$scope struct flags $end +$var wire 1 }. pwr_ca_x86_cf $end +$var wire 1 ~. pwr_ca32_x86_af $end +$var wire 1 !/ pwr_ov_x86_of $end +$var wire 1 "/ pwr_ov32_x86_df $end +$var wire 1 #/ pwr_cr_lt_x86_sf $end +$var wire 1 $/ pwr_cr_gt_x86_pf $end +$var wire 1 %/ pwr_cr_eq_x86_zf $end +$var wire 1 &/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r1 $end +$var wire 4 '/ addr $end +$var wire 1 (/ en $end +$var wire 1 )/ clk $end +$scope struct data $end +$var wire 64 */ int_fp $end +$scope struct flags $end +$var wire 1 +/ pwr_ca_x86_cf $end +$var wire 1 ,/ pwr_ca32_x86_af $end +$var wire 1 -/ pwr_ov_x86_of $end +$var wire 1 ./ pwr_ov32_x86_df $end +$var wire 1 // pwr_cr_lt_x86_sf $end +$var wire 1 0/ pwr_cr_gt_x86_pf $end +$var wire 1 1/ pwr_cr_eq_x86_zf $end +$var wire 1 2/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r2 $end +$var wire 4 3/ addr $end +$var wire 1 4/ en $end +$var wire 1 5/ clk $end +$scope struct data $end +$var wire 64 6/ int_fp $end +$scope struct flags $end +$var wire 1 7/ pwr_ca_x86_cf $end +$var wire 1 8/ pwr_ca32_x86_af $end +$var wire 1 9/ pwr_ov_x86_of $end +$var wire 1 :/ pwr_ov32_x86_df $end +$var wire 1 ;/ pwr_cr_lt_x86_sf $end +$var wire 1 / pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct w3 $end +$var wire 4 ?/ addr $end +$var wire 1 @/ en $end +$var wire 1 A/ clk $end +$scope struct data $end +$var wire 64 B/ int_fp $end +$scope struct flags $end +$var wire 1 C/ pwr_ca_x86_cf $end +$var wire 1 D/ pwr_ca32_x86_af $end +$var wire 1 E/ pwr_ov_x86_of $end +$var wire 1 F/ pwr_ov32_x86_df $end +$var wire 1 G/ pwr_cr_lt_x86_sf $end +$var wire 1 H/ pwr_cr_gt_x86_pf $end +$var wire 1 I/ pwr_cr_eq_x86_zf $end +$var wire 1 J/ pwr_so $end +$upscope $end +$upscope $end +$scope struct mask $end +$var wire 1 K/ int_fp $end +$scope struct flags $end +$var wire 1 L/ pwr_ca_x86_cf $end +$var wire 1 M/ pwr_ca32_x86_af $end +$var wire 1 N/ pwr_ov_x86_of $end +$var wire 1 O/ pwr_ov32_x86_df $end +$var wire 1 P/ pwr_cr_lt_x86_sf $end +$var wire 1 Q/ pwr_cr_gt_x86_pf $end +$var wire 1 R/ pwr_cr_eq_x86_zf $end +$var wire 1 S/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct in_flight_ops $end +$scope struct \[0] $end +$var string 1 T/ \$tag $end $scope struct HdlSome $end -$var string 1 +0 state $end +$var string 1 U/ state $end $scope struct mop $end -$var string 1 ,0 \$tag $end +$var string 1 V/ \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end +$var string 0 W/ prefix_pad $end +$scope struct dest $end +$var reg 4 X/ value $end +$upscope $end +$scope struct src $end +$var reg 6 Y/ \[0] $end +$var reg 6 Z/ \[1] $end +$var reg 6 [/ \[2] $end +$upscope $end +$var reg 25 \/ imm_low $end +$var reg 1 ]/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ^/ output_integer_mode $end +$upscope $end +$var reg 1 _/ invert_src0 $end +$var reg 1 `/ src1_is_carry_in $end +$var reg 1 a/ invert_carry_in $end +$var reg 1 b/ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 c/ prefix_pad $end +$scope struct dest $end +$var reg 4 d/ value $end +$upscope $end +$scope struct src $end +$var reg 6 e/ \[0] $end +$var reg 6 f/ \[1] $end +$var reg 6 g/ \[2] $end +$upscope $end +$var reg 25 h/ imm_low $end +$var reg 1 i/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 j/ output_integer_mode $end +$upscope $end +$var reg 1 k/ invert_src0 $end +$var reg 1 l/ src1_is_carry_in $end +$var reg 1 m/ invert_carry_in $end +$var reg 1 n/ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 o/ prefix_pad $end +$scope struct dest $end +$var reg 4 p/ value $end +$upscope $end +$scope struct src $end +$var reg 6 q/ \[0] $end +$var reg 6 r/ \[1] $end +$var reg 6 s/ \[2] $end +$upscope $end +$var reg 25 t/ imm_low $end +$var reg 1 u/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 v/ output_integer_mode $end +$upscope $end +$var reg 4 w/ lut $end +$upscope $end +$upscope $end +$var reg 64 x/ pc $end +$scope struct src_ready_flags $end +$var reg 1 y/ \[0] $end +$var reg 1 z/ \[1] $end +$var reg 1 {/ \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 |/ \$tag $end +$scope struct HdlSome $end +$var string 1 }/ state $end +$scope struct mop $end +$var string 1 ~/ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 !0 prefix_pad $end +$scope struct dest $end +$var reg 4 "0 value $end +$upscope $end +$scope struct src $end +$var reg 6 #0 \[0] $end +$var reg 6 $0 \[1] $end +$var reg 6 %0 \[2] $end +$upscope $end +$var reg 25 &0 imm_low $end +$var reg 1 '0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 (0 output_integer_mode $end +$upscope $end +$var reg 1 )0 invert_src0 $end +$var reg 1 *0 src1_is_carry_in $end +$var reg 1 +0 invert_carry_in $end +$var reg 1 ,0 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end $var string 0 -0 prefix_pad $end $scope struct dest $end $var reg 4 .0 value $end @@ -7031,11 +7477,11 @@ $upscope $end $var string 1 40 output_integer_mode $end $upscope $end $var reg 1 50 invert_src0 $end -$var reg 1 60 invert_carry_in $end -$var reg 1 70 invert_carry_out $end +$var reg 1 60 src1_is_carry_in $end +$var reg 1 70 invert_carry_in $end $var reg 1 80 add_pc $end $upscope $end -$scope struct AddSubI $end +$scope struct Logical $end $scope struct alu_common $end $scope struct common $end $var string 0 90 prefix_pad $end @@ -7054,1543 +7500,1551 @@ $upscope $end $upscope $end $var string 1 @0 output_integer_mode $end $upscope $end -$var reg 1 A0 invert_src0 $end -$var reg 1 B0 invert_carry_in $end -$var reg 1 C0 invert_carry_out $end -$var reg 1 D0 add_pc $end +$var reg 4 A0 lut $end +$upscope $end +$upscope $end +$var reg 64 B0 pc $end +$scope struct src_ready_flags $end +$var reg 1 C0 \[0] $end +$var reg 1 D0 \[1] $end +$var reg 1 E0 \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 F0 \$tag $end +$scope struct HdlSome $end +$var string 1 G0 state $end +$scope struct mop $end +$var string 1 H0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 I0 prefix_pad $end +$scope struct dest $end +$var reg 4 J0 value $end +$upscope $end +$scope struct src $end +$var reg 6 K0 \[0] $end +$var reg 6 L0 \[1] $end +$var reg 6 M0 \[2] $end +$upscope $end +$var reg 25 N0 imm_low $end +$var reg 1 O0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 P0 output_integer_mode $end +$upscope $end +$var reg 1 Q0 invert_src0 $end +$var reg 1 R0 src1_is_carry_in $end +$var reg 1 S0 invert_carry_in $end +$var reg 1 T0 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 U0 prefix_pad $end +$scope struct dest $end +$var reg 4 V0 value $end +$upscope $end +$scope struct src $end +$var reg 6 W0 \[0] $end +$var reg 6 X0 \[1] $end +$var reg 6 Y0 \[2] $end +$upscope $end +$var reg 25 Z0 imm_low $end +$var reg 1 [0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 \0 output_integer_mode $end +$upscope $end +$var reg 1 ]0 invert_src0 $end +$var reg 1 ^0 src1_is_carry_in $end +$var reg 1 _0 invert_carry_in $end +$var reg 1 `0 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 E0 prefix_pad $end +$var string 0 a0 prefix_pad $end $scope struct dest $end -$var reg 4 F0 value $end +$var reg 4 b0 value $end $upscope $end $scope struct src $end -$var reg 6 G0 \[0] $end -$var reg 6 H0 \[1] $end -$var reg 6 I0 \[2] $end +$var reg 6 c0 \[0] $end +$var reg 6 d0 \[1] $end +$var reg 6 e0 \[2] $end $upscope $end -$var reg 25 J0 imm_low $end -$var reg 1 K0 imm_sign $end +$var reg 25 f0 imm_low $end +$var reg 1 g0 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 L0 output_integer_mode $end +$var string 1 h0 output_integer_mode $end $upscope $end -$var reg 4 M0 lut $end +$var reg 4 i0 lut $end $upscope $end $upscope $end +$var reg 64 j0 pc $end $scope struct src_ready_flags $end -$var reg 1 N0 \[0] $end -$var reg 1 O0 \[1] $end -$var reg 1 P0 \[2] $end +$var reg 1 k0 \[0] $end +$var reg 1 l0 \[1] $end +$var reg 1 m0 \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 n0 \$tag $end +$scope struct HdlSome $end +$var string 1 o0 state $end +$scope struct mop $end +$var string 1 p0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 q0 prefix_pad $end +$scope struct dest $end +$var reg 4 r0 value $end +$upscope $end +$scope struct src $end +$var reg 6 s0 \[0] $end +$var reg 6 t0 \[1] $end +$var reg 6 u0 \[2] $end +$upscope $end +$var reg 25 v0 imm_low $end +$var reg 1 w0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 x0 output_integer_mode $end +$upscope $end +$var reg 1 y0 invert_src0 $end +$var reg 1 z0 src1_is_carry_in $end +$var reg 1 {0 invert_carry_in $end +$var reg 1 |0 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }0 prefix_pad $end +$scope struct dest $end +$var reg 4 ~0 value $end +$upscope $end +$scope struct src $end +$var reg 6 !1 \[0] $end +$var reg 6 "1 \[1] $end +$var reg 6 #1 \[2] $end +$upscope $end +$var reg 25 $1 imm_low $end +$var reg 1 %1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &1 output_integer_mode $end +$upscope $end +$var reg 1 '1 invert_src0 $end +$var reg 1 (1 src1_is_carry_in $end +$var reg 1 )1 invert_carry_in $end +$var reg 1 *1 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 +1 prefix_pad $end +$scope struct dest $end +$var reg 4 ,1 value $end +$upscope $end +$scope struct src $end +$var reg 6 -1 \[0] $end +$var reg 6 .1 \[1] $end +$var reg 6 /1 \[2] $end +$upscope $end +$var reg 25 01 imm_low $end +$var reg 1 11 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 21 output_integer_mode $end +$upscope $end +$var reg 4 31 lut $end +$upscope $end +$upscope $end +$var reg 64 41 pc $end +$scope struct src_ready_flags $end +$var reg 1 51 \[0] $end +$var reg 1 61 \[1] $end +$var reg 1 71 \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 81 \$tag $end +$scope struct HdlSome $end +$var string 1 91 state $end +$scope struct mop $end +$var string 1 :1 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ;1 prefix_pad $end +$scope struct dest $end +$var reg 4 <1 value $end +$upscope $end +$scope struct src $end +$var reg 6 =1 \[0] $end +$var reg 6 >1 \[1] $end +$var reg 6 ?1 \[2] $end +$upscope $end +$var reg 25 @1 imm_low $end +$var reg 1 A1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 B1 output_integer_mode $end +$upscope $end +$var reg 1 C1 invert_src0 $end +$var reg 1 D1 src1_is_carry_in $end +$var reg 1 E1 invert_carry_in $end +$var reg 1 F1 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 G1 prefix_pad $end +$scope struct dest $end +$var reg 4 H1 value $end +$upscope $end +$scope struct src $end +$var reg 6 I1 \[0] $end +$var reg 6 J1 \[1] $end +$var reg 6 K1 \[2] $end +$upscope $end +$var reg 25 L1 imm_low $end +$var reg 1 M1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 N1 output_integer_mode $end +$upscope $end +$var reg 1 O1 invert_src0 $end +$var reg 1 P1 src1_is_carry_in $end +$var reg 1 Q1 invert_carry_in $end +$var reg 1 R1 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 S1 prefix_pad $end +$scope struct dest $end +$var reg 4 T1 value $end +$upscope $end +$scope struct src $end +$var reg 6 U1 \[0] $end +$var reg 6 V1 \[1] $end +$var reg 6 W1 \[2] $end +$upscope $end +$var reg 25 X1 imm_low $end +$var reg 1 Y1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 Z1 output_integer_mode $end +$upscope $end +$var reg 4 [1 lut $end +$upscope $end +$upscope $end +$var reg 64 \1 pc $end +$scope struct src_ready_flags $end +$var reg 1 ]1 \[0] $end +$var reg 1 ^1 \[1] $end +$var reg 1 _1 \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 `1 \$tag $end +$scope struct HdlSome $end +$var string 1 a1 state $end +$scope struct mop $end +$var string 1 b1 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 c1 prefix_pad $end +$scope struct dest $end +$var reg 4 d1 value $end +$upscope $end +$scope struct src $end +$var reg 6 e1 \[0] $end +$var reg 6 f1 \[1] $end +$var reg 6 g1 \[2] $end +$upscope $end +$var reg 25 h1 imm_low $end +$var reg 1 i1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 j1 output_integer_mode $end +$upscope $end +$var reg 1 k1 invert_src0 $end +$var reg 1 l1 src1_is_carry_in $end +$var reg 1 m1 invert_carry_in $end +$var reg 1 n1 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 o1 prefix_pad $end +$scope struct dest $end +$var reg 4 p1 value $end +$upscope $end +$scope struct src $end +$var reg 6 q1 \[0] $end +$var reg 6 r1 \[1] $end +$var reg 6 s1 \[2] $end +$upscope $end +$var reg 25 t1 imm_low $end +$var reg 1 u1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 v1 output_integer_mode $end +$upscope $end +$var reg 1 w1 invert_src0 $end +$var reg 1 x1 src1_is_carry_in $end +$var reg 1 y1 invert_carry_in $end +$var reg 1 z1 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 {1 prefix_pad $end +$scope struct dest $end +$var reg 4 |1 value $end +$upscope $end +$scope struct src $end +$var reg 6 }1 \[0] $end +$var reg 6 ~1 \[1] $end +$var reg 6 !2 \[2] $end +$upscope $end +$var reg 25 "2 imm_low $end +$var reg 1 #2 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 $2 output_integer_mode $end +$upscope $end +$var reg 4 %2 lut $end +$upscope $end +$upscope $end +$var reg 64 &2 pc $end +$scope struct src_ready_flags $end +$var reg 1 '2 \[0] $end +$var reg 1 (2 \[1] $end +$var reg 1 )2 \[2] $end $upscope $end $upscope $end $upscope $end $scope struct \[6] $end -$var string 1 Q0 \$tag $end +$var string 1 *2 \$tag $end $scope struct HdlSome $end -$var string 1 R0 state $end +$var string 1 +2 state $end $scope struct mop $end -$var string 1 S0 \$tag $end +$var string 1 ,2 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 T0 prefix_pad $end +$var string 0 -2 prefix_pad $end $scope struct dest $end -$var reg 4 U0 value $end +$var reg 4 .2 value $end $upscope $end $scope struct src $end -$var reg 6 V0 \[0] $end -$var reg 6 W0 \[1] $end -$var reg 6 X0 \[2] $end +$var reg 6 /2 \[0] $end +$var reg 6 02 \[1] $end +$var reg 6 12 \[2] $end $upscope $end -$var reg 25 Y0 imm_low $end -$var reg 1 Z0 imm_sign $end +$var reg 25 22 imm_low $end +$var reg 1 32 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 [0 output_integer_mode $end +$var string 1 42 output_integer_mode $end $upscope $end -$var reg 1 \0 invert_src0 $end -$var reg 1 ]0 invert_carry_in $end -$var reg 1 ^0 invert_carry_out $end -$var reg 1 _0 add_pc $end +$var reg 1 52 invert_src0 $end +$var reg 1 62 src1_is_carry_in $end +$var reg 1 72 invert_carry_in $end +$var reg 1 82 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 `0 prefix_pad $end +$var string 0 92 prefix_pad $end $scope struct dest $end -$var reg 4 a0 value $end +$var reg 4 :2 value $end $upscope $end $scope struct src $end -$var reg 6 b0 \[0] $end -$var reg 6 c0 \[1] $end -$var reg 6 d0 \[2] $end +$var reg 6 ;2 \[0] $end +$var reg 6 <2 \[1] $end +$var reg 6 =2 \[2] $end $upscope $end -$var reg 25 e0 imm_low $end -$var reg 1 f0 imm_sign $end +$var reg 25 >2 imm_low $end +$var reg 1 ?2 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 g0 output_integer_mode $end +$var string 1 @2 output_integer_mode $end $upscope $end -$var reg 1 h0 invert_src0 $end -$var reg 1 i0 invert_carry_in $end -$var reg 1 j0 invert_carry_out $end -$var reg 1 k0 add_pc $end +$var reg 1 A2 invert_src0 $end +$var reg 1 B2 src1_is_carry_in $end +$var reg 1 C2 invert_carry_in $end +$var reg 1 D2 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 l0 prefix_pad $end +$var string 0 E2 prefix_pad $end $scope struct dest $end -$var reg 4 m0 value $end +$var reg 4 F2 value $end $upscope $end $scope struct src $end -$var reg 6 n0 \[0] $end -$var reg 6 o0 \[1] $end -$var reg 6 p0 \[2] $end +$var reg 6 G2 \[0] $end +$var reg 6 H2 \[1] $end +$var reg 6 I2 \[2] $end $upscope $end -$var reg 25 q0 imm_low $end -$var reg 1 r0 imm_sign $end +$var reg 25 J2 imm_low $end +$var reg 1 K2 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 s0 output_integer_mode $end +$var string 1 L2 output_integer_mode $end $upscope $end -$var reg 4 t0 lut $end +$var reg 4 M2 lut $end $upscope $end $upscope $end +$var reg 64 N2 pc $end $scope struct src_ready_flags $end -$var reg 1 u0 \[0] $end -$var reg 1 v0 \[1] $end -$var reg 1 w0 \[2] $end +$var reg 1 O2 \[0] $end +$var reg 1 P2 \[1] $end +$var reg 1 Q2 \[2] $end $upscope $end $upscope $end $upscope $end $scope struct \[7] $end -$var string 1 x0 \$tag $end +$var string 1 R2 \$tag $end $scope struct HdlSome $end -$var string 1 y0 state $end +$var string 1 S2 state $end $scope struct mop $end -$var string 1 z0 \$tag $end +$var string 1 T2 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 {0 prefix_pad $end +$var string 0 U2 prefix_pad $end $scope struct dest $end -$var reg 4 |0 value $end +$var reg 4 V2 value $end $upscope $end $scope struct src $end -$var reg 6 }0 \[0] $end -$var reg 6 ~0 \[1] $end -$var reg 6 !1 \[2] $end +$var reg 6 W2 \[0] $end +$var reg 6 X2 \[1] $end +$var reg 6 Y2 \[2] $end $upscope $end -$var reg 25 "1 imm_low $end -$var reg 1 #1 imm_sign $end +$var reg 25 Z2 imm_low $end +$var reg 1 [2 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 $1 output_integer_mode $end +$var string 1 \2 output_integer_mode $end $upscope $end -$var reg 1 %1 invert_src0 $end -$var reg 1 &1 invert_carry_in $end -$var reg 1 '1 invert_carry_out $end -$var reg 1 (1 add_pc $end +$var reg 1 ]2 invert_src0 $end +$var reg 1 ^2 src1_is_carry_in $end +$var reg 1 _2 invert_carry_in $end +$var reg 1 `2 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 )1 prefix_pad $end +$var string 0 a2 prefix_pad $end $scope struct dest $end -$var reg 4 *1 value $end +$var reg 4 b2 value $end $upscope $end $scope struct src $end -$var reg 6 +1 \[0] $end -$var reg 6 ,1 \[1] $end -$var reg 6 -1 \[2] $end +$var reg 6 c2 \[0] $end +$var reg 6 d2 \[1] $end +$var reg 6 e2 \[2] $end $upscope $end -$var reg 25 .1 imm_low $end -$var reg 1 /1 imm_sign $end +$var reg 25 f2 imm_low $end +$var reg 1 g2 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 01 output_integer_mode $end +$var string 1 h2 output_integer_mode $end $upscope $end -$var reg 1 11 invert_src0 $end -$var reg 1 21 invert_carry_in $end -$var reg 1 31 invert_carry_out $end -$var reg 1 41 add_pc $end +$var reg 1 i2 invert_src0 $end +$var reg 1 j2 src1_is_carry_in $end +$var reg 1 k2 invert_carry_in $end +$var reg 1 l2 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 51 prefix_pad $end +$var string 0 m2 prefix_pad $end $scope struct dest $end -$var reg 4 61 value $end +$var reg 4 n2 value $end $upscope $end $scope struct src $end -$var reg 6 71 \[0] $end -$var reg 6 81 \[1] $end -$var reg 6 91 \[2] $end +$var reg 6 o2 \[0] $end +$var reg 6 p2 \[1] $end +$var reg 6 q2 \[2] $end $upscope $end -$var reg 25 :1 imm_low $end -$var reg 1 ;1 imm_sign $end +$var reg 25 r2 imm_low $end +$var reg 1 s2 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 <1 output_integer_mode $end +$var string 1 t2 output_integer_mode $end $upscope $end -$var reg 4 =1 lut $end +$var reg 4 u2 lut $end $upscope $end $upscope $end +$var reg 64 v2 pc $end $scope struct src_ready_flags $end -$var reg 1 >1 \[0] $end -$var reg 1 ?1 \[1] $end -$var reg 1 @1 \[2] $end +$var reg 1 w2 \[0] $end +$var reg 1 x2 \[1] $end +$var reg 1 y2 \[2] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct empty_op_index_0 $end -$var string 1 A1 \$tag $end -$var wire 3 B1 HdlSome $end +$var string 1 z2 \$tag $end +$var wire 3 {2 HdlSome $end $upscope $end $scope struct ready_op_index_0 $end -$var string 1 C1 \$tag $end -$var wire 3 D1 HdlSome $end +$var string 1 |2 \$tag $end +$var wire 3 }2 HdlSome $end $upscope $end $scope struct empty_op_index_1 $end -$var string 1 E1 \$tag $end -$var wire 3 F1 HdlSome $end +$var string 1 ~2 \$tag $end +$var wire 3 !3 HdlSome $end $upscope $end $scope struct ready_op_index_1 $end -$var string 1 G1 \$tag $end -$var wire 3 H1 HdlSome $end +$var string 1 "3 \$tag $end +$var wire 3 #3 HdlSome $end $upscope $end $scope struct or_out $end -$var string 1 I1 \$tag $end -$var wire 3 J1 HdlSome $end +$var string 1 $3 \$tag $end +$var wire 3 %3 HdlSome $end $upscope $end $scope struct or_out_2 $end -$var string 1 K1 \$tag $end -$var wire 3 L1 HdlSome $end +$var string 1 &3 \$tag $end +$var wire 3 '3 HdlSome $end $upscope $end $scope struct empty_op_index_2 $end -$var string 1 M1 \$tag $end -$var wire 3 N1 HdlSome $end +$var string 1 (3 \$tag $end +$var wire 3 )3 HdlSome $end $upscope $end $scope struct ready_op_index_2 $end -$var string 1 O1 \$tag $end -$var wire 3 P1 HdlSome $end +$var string 1 *3 \$tag $end +$var wire 3 +3 HdlSome $end $upscope $end $scope struct empty_op_index_3 $end -$var string 1 Q1 \$tag $end -$var wire 3 R1 HdlSome $end +$var string 1 ,3 \$tag $end +$var wire 3 -3 HdlSome $end $upscope $end $scope struct ready_op_index_3 $end -$var string 1 S1 \$tag $end -$var wire 3 T1 HdlSome $end +$var string 1 .3 \$tag $end +$var wire 3 /3 HdlSome $end $upscope $end $scope struct or_out_3 $end -$var string 1 U1 \$tag $end -$var wire 3 V1 HdlSome $end +$var string 1 03 \$tag $end +$var wire 3 13 HdlSome $end $upscope $end $scope struct or_out_4 $end -$var string 1 W1 \$tag $end -$var wire 3 X1 HdlSome $end +$var string 1 23 \$tag $end +$var wire 3 33 HdlSome $end $upscope $end $scope struct or_out_5 $end -$var string 1 Y1 \$tag $end -$var wire 3 Z1 HdlSome $end +$var string 1 43 \$tag $end +$var wire 3 53 HdlSome $end $upscope $end $scope struct or_out_6 $end -$var string 1 [1 \$tag $end -$var wire 3 \1 HdlSome $end +$var string 1 63 \$tag $end +$var wire 3 73 HdlSome $end $upscope $end $scope struct empty_op_index_4 $end -$var string 1 ]1 \$tag $end -$var wire 3 ^1 HdlSome $end +$var string 1 83 \$tag $end +$var wire 3 93 HdlSome $end $upscope $end $scope struct ready_op_index_4 $end -$var string 1 _1 \$tag $end -$var wire 3 `1 HdlSome $end +$var string 1 :3 \$tag $end +$var wire 3 ;3 HdlSome $end $upscope $end $scope struct empty_op_index_5 $end -$var string 1 a1 \$tag $end -$var wire 3 b1 HdlSome $end +$var string 1 <3 \$tag $end +$var wire 3 =3 HdlSome $end $upscope $end $scope struct ready_op_index_5 $end -$var string 1 c1 \$tag $end -$var wire 3 d1 HdlSome $end +$var string 1 >3 \$tag $end +$var wire 3 ?3 HdlSome $end $upscope $end $scope struct or_out_7 $end -$var string 1 e1 \$tag $end -$var wire 3 f1 HdlSome $end +$var string 1 @3 \$tag $end +$var wire 3 A3 HdlSome $end $upscope $end $scope struct or_out_8 $end -$var string 1 g1 \$tag $end -$var wire 3 h1 HdlSome $end +$var string 1 B3 \$tag $end +$var wire 3 C3 HdlSome $end $upscope $end $scope struct empty_op_index_6 $end -$var string 1 i1 \$tag $end -$var wire 3 j1 HdlSome $end +$var string 1 D3 \$tag $end +$var wire 3 E3 HdlSome $end $upscope $end $scope struct ready_op_index_6 $end -$var string 1 k1 \$tag $end -$var wire 3 l1 HdlSome $end +$var string 1 F3 \$tag $end +$var wire 3 G3 HdlSome $end $upscope $end $scope struct empty_op_index_7 $end -$var string 1 m1 \$tag $end -$var wire 3 n1 HdlSome $end +$var string 1 H3 \$tag $end +$var wire 3 I3 HdlSome $end $upscope $end $scope struct ready_op_index_7 $end -$var string 1 o1 \$tag $end -$var wire 3 p1 HdlSome $end +$var string 1 J3 \$tag $end +$var wire 3 K3 HdlSome $end $upscope $end $scope struct or_out_9 $end -$var string 1 q1 \$tag $end -$var wire 3 r1 HdlSome $end +$var string 1 L3 \$tag $end +$var wire 3 M3 HdlSome $end $upscope $end $scope struct or_out_10 $end -$var string 1 s1 \$tag $end -$var wire 3 t1 HdlSome $end +$var string 1 N3 \$tag $end +$var wire 3 O3 HdlSome $end $upscope $end $scope struct or_out_11 $end -$var string 1 u1 \$tag $end -$var wire 3 v1 HdlSome $end +$var string 1 P3 \$tag $end +$var wire 3 Q3 HdlSome $end $upscope $end $scope struct or_out_12 $end -$var string 1 w1 \$tag $end -$var wire 3 x1 HdlSome $end +$var string 1 R3 \$tag $end +$var wire 3 S3 HdlSome $end $upscope $end $scope struct or_out_13 $end -$var string 1 y1 \$tag $end -$var wire 3 z1 HdlSome $end +$var string 1 T3 \$tag $end +$var wire 3 U3 HdlSome $end $upscope $end $scope struct or_out_14 $end -$var string 1 {1 \$tag $end -$var wire 3 |1 HdlSome $end +$var string 1 V3 \$tag $end +$var wire 3 W3 HdlSome $end $upscope $end $scope struct in_flight_ops_summary $end $scope struct empty_op_index $end -$var string 1 }1 \$tag $end -$var wire 3 ~1 HdlSome $end +$var string 1 X3 \$tag $end +$var wire 3 Y3 HdlSome $end $upscope $end $scope struct ready_op_index $end -$var string 1 !2 \$tag $end -$var wire 3 "2 HdlSome $end +$var string 1 Z3 \$tag $end +$var wire 3 [3 HdlSome $end +$upscope $end +$upscope $end +$var wire 1 \3 is_some_out $end +$scope struct read_src_regs $end +$var wire 6 ]3 \[0] $end +$var wire 6 ^3 \[1] $end +$var wire 6 _3 \[2] $end +$upscope $end +$scope struct read_src_values $end +$scope struct \[0] $end +$var wire 64 `3 int_fp $end +$scope struct flags $end +$var wire 1 a3 pwr_ca_x86_cf $end +$var wire 1 b3 pwr_ca32_x86_af $end +$var wire 1 c3 pwr_ov_x86_of $end +$var wire 1 d3 pwr_ov32_x86_df $end +$var wire 1 e3 pwr_cr_lt_x86_sf $end +$var wire 1 f3 pwr_cr_gt_x86_pf $end +$var wire 1 g3 pwr_cr_eq_x86_zf $end +$var wire 1 h3 pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 i3 int_fp $end +$scope struct flags $end +$var wire 1 j3 pwr_ca_x86_cf $end +$var wire 1 k3 pwr_ca32_x86_af $end +$var wire 1 l3 pwr_ov_x86_of $end +$var wire 1 m3 pwr_ov32_x86_df $end +$var wire 1 n3 pwr_cr_lt_x86_sf $end +$var wire 1 o3 pwr_cr_gt_x86_pf $end +$var wire 1 p3 pwr_cr_eq_x86_zf $end +$var wire 1 q3 pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 r3 int_fp $end +$scope struct flags $end +$var wire 1 s3 pwr_ca_x86_cf $end +$var wire 1 t3 pwr_ca32_x86_af $end +$var wire 1 u3 pwr_ov_x86_of $end +$var wire 1 v3 pwr_ov32_x86_df $end +$var wire 1 w3 pwr_cr_lt_x86_sf $end +$var wire 1 x3 pwr_cr_gt_x86_pf $end +$var wire 1 y3 pwr_cr_eq_x86_zf $end +$var wire 1 z3 pwr_so $end +$upscope $end $upscope $end $upscope $end -$var wire 1 #2 is_some_out $end $scope struct input_in_flight_op $end -$var string 1 $2 \$tag $end +$var string 1 {3 \$tag $end $scope struct HdlSome $end -$var string 1 %2 state $end +$var string 1 |3 state $end $scope struct mop $end -$var string 1 &2 \$tag $end +$var string 1 }3 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 '2 prefix_pad $end +$var string 0 ~3 prefix_pad $end $scope struct dest $end -$var wire 4 (2 value $end +$var wire 4 !4 value $end $upscope $end $scope struct src $end -$var wire 6 )2 \[0] $end -$var wire 6 *2 \[1] $end -$var wire 6 +2 \[2] $end +$var wire 6 "4 \[0] $end +$var wire 6 #4 \[1] $end +$var wire 6 $4 \[2] $end $upscope $end -$var wire 25 ,2 imm_low $end -$var wire 1 -2 imm_sign $end +$var wire 25 %4 imm_low $end +$var wire 1 &4 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 .2 output_integer_mode $end +$var string 1 '4 output_integer_mode $end $upscope $end -$var wire 1 /2 invert_src0 $end -$var wire 1 02 invert_carry_in $end -$var wire 1 12 invert_carry_out $end -$var wire 1 22 add_pc $end +$var wire 1 (4 invert_src0 $end +$var wire 1 )4 src1_is_carry_in $end +$var wire 1 *4 invert_carry_in $end +$var wire 1 +4 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 32 prefix_pad $end +$var string 0 ,4 prefix_pad $end $scope struct dest $end -$var wire 4 42 value $end +$var wire 4 -4 value $end $upscope $end $scope struct src $end -$var wire 6 52 \[0] $end -$var wire 6 62 \[1] $end -$var wire 6 72 \[2] $end +$var wire 6 .4 \[0] $end +$var wire 6 /4 \[1] $end +$var wire 6 04 \[2] $end $upscope $end -$var wire 25 82 imm_low $end -$var wire 1 92 imm_sign $end +$var wire 25 14 imm_low $end +$var wire 1 24 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 :2 output_integer_mode $end +$var string 1 34 output_integer_mode $end $upscope $end -$var wire 1 ;2 invert_src0 $end -$var wire 1 <2 invert_carry_in $end -$var wire 1 =2 invert_carry_out $end -$var wire 1 >2 add_pc $end +$var wire 1 44 invert_src0 $end +$var wire 1 54 src1_is_carry_in $end +$var wire 1 64 invert_carry_in $end +$var wire 1 74 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 ?2 prefix_pad $end +$var string 0 84 prefix_pad $end $scope struct dest $end -$var wire 4 @2 value $end +$var wire 4 94 value $end $upscope $end $scope struct src $end -$var wire 6 A2 \[0] $end -$var wire 6 B2 \[1] $end -$var wire 6 C2 \[2] $end +$var wire 6 :4 \[0] $end +$var wire 6 ;4 \[1] $end +$var wire 6 <4 \[2] $end $upscope $end -$var wire 25 D2 imm_low $end -$var wire 1 E2 imm_sign $end +$var wire 25 =4 imm_low $end +$var wire 1 >4 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 F2 output_integer_mode $end +$var string 1 ?4 output_integer_mode $end $upscope $end -$var wire 4 G2 lut $end +$var wire 4 @4 lut $end $upscope $end $upscope $end +$var wire 64 A4 pc $end $scope struct src_ready_flags $end -$var wire 1 H2 \[0] $end -$var wire 1 I2 \[1] $end -$var wire 1 J2 \[2] $end +$var wire 1 B4 \[0] $end +$var wire 1 C4 \[1] $end +$var wire 1 D4 \[2] $end $upscope $end $upscope $end $upscope $end $scope struct firing_data $end -$var string 1 K2 \$tag $end +$var string 1 E4 \$tag $end $scope struct HdlSome $end -$var string 1 L2 \$tag $end +$scope struct mop $end +$var string 1 F4 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 M2 prefix_pad $end +$var string 0 G4 prefix_pad $end $scope struct dest $end -$var wire 4 N2 value $end +$var wire 4 H4 value $end $upscope $end $scope struct src $end -$var wire 6 O2 \[0] $end -$var wire 6 P2 \[1] $end -$var wire 6 Q2 \[2] $end +$var wire 6 I4 \[0] $end +$var wire 6 J4 \[1] $end +$var wire 6 K4 \[2] $end $upscope $end -$var wire 25 R2 imm_low $end -$var wire 1 S2 imm_sign $end +$var wire 25 L4 imm_low $end +$var wire 1 M4 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 T2 output_integer_mode $end +$var string 1 N4 output_integer_mode $end $upscope $end -$var wire 1 U2 invert_src0 $end -$var wire 1 V2 invert_carry_in $end -$var wire 1 W2 invert_carry_out $end -$var wire 1 X2 add_pc $end +$var wire 1 O4 invert_src0 $end +$var wire 1 P4 src1_is_carry_in $end +$var wire 1 Q4 invert_carry_in $end +$var wire 1 R4 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 Y2 prefix_pad $end +$var string 0 S4 prefix_pad $end $scope struct dest $end -$var wire 4 Z2 value $end +$var wire 4 T4 value $end $upscope $end $scope struct src $end -$var wire 6 [2 \[0] $end -$var wire 6 \2 \[1] $end -$var wire 6 ]2 \[2] $end +$var wire 6 U4 \[0] $end +$var wire 6 V4 \[1] $end +$var wire 6 W4 \[2] $end $upscope $end -$var wire 25 ^2 imm_low $end -$var wire 1 _2 imm_sign $end +$var wire 25 X4 imm_low $end +$var wire 1 Y4 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 `2 output_integer_mode $end +$var string 1 Z4 output_integer_mode $end $upscope $end -$var wire 1 a2 invert_src0 $end -$var wire 1 b2 invert_carry_in $end -$var wire 1 c2 invert_carry_out $end -$var wire 1 d2 add_pc $end +$var wire 1 [4 invert_src0 $end +$var wire 1 \4 src1_is_carry_in $end +$var wire 1 ]4 invert_carry_in $end +$var wire 1 ^4 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 e2 prefix_pad $end +$var string 0 _4 prefix_pad $end $scope struct dest $end -$var wire 4 f2 value $end +$var wire 4 `4 value $end $upscope $end $scope struct src $end -$var wire 6 g2 \[0] $end -$var wire 6 h2 \[1] $end -$var wire 6 i2 \[2] $end +$var wire 6 a4 \[0] $end +$var wire 6 b4 \[1] $end +$var wire 6 c4 \[2] $end $upscope $end -$var wire 25 j2 imm_low $end -$var wire 1 k2 imm_sign $end +$var wire 25 d4 imm_low $end +$var wire 1 e4 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 l2 output_integer_mode $end +$var string 1 f4 output_integer_mode $end $upscope $end -$var wire 4 m2 lut $end +$var wire 4 g4 lut $end $upscope $end $upscope $end +$var wire 64 h4 pc $end +$upscope $end $upscope $end $scope struct input_mop_src_regs $end -$var wire 6 n2 \[0] $end -$var wire 6 o2 \[1] $end -$var wire 6 p2 \[2] $end +$var wire 6 i4 \[0] $end +$var wire 6 j4 \[1] $end +$var wire 6 k4 \[2] $end $upscope $end $scope struct input_in_flight_op_src_ready_flags $end -$var wire 1 q2 \[0] $end -$var wire 1 r2 \[1] $end -$var wire 1 s2 \[2] $end +$var wire 1 l4 \[0] $end +$var wire 1 m4 \[1] $end +$var wire 1 n4 \[2] $end $upscope $end $scope struct dest_reg $end -$var wire 4 t2 value $end +$var wire 4 o4 value $end $upscope $end -$var wire 1 u2 cmp_ne $end +$var wire 1 p4 cmp_ne $end $scope struct in_flight_op_next_state $end $scope struct \[0] $end -$var string 1 v2 \$tag $end -$var string 1 w2 HdlSome $end +$var string 1 q4 \$tag $end +$var string 1 r4 HdlSome $end $upscope $end $scope struct \[1] $end -$var string 1 x2 \$tag $end -$var string 1 y2 HdlSome $end +$var string 1 s4 \$tag $end +$var string 1 t4 HdlSome $end $upscope $end $scope struct \[2] $end -$var string 1 z2 \$tag $end -$var string 1 {2 HdlSome $end +$var string 1 u4 \$tag $end +$var string 1 v4 HdlSome $end $upscope $end $scope struct \[3] $end -$var string 1 |2 \$tag $end -$var string 1 }2 HdlSome $end +$var string 1 w4 \$tag $end +$var string 1 x4 HdlSome $end $upscope $end $scope struct \[4] $end -$var string 1 ~2 \$tag $end -$var string 1 !3 HdlSome $end +$var string 1 y4 \$tag $end +$var string 1 z4 HdlSome $end $upscope $end $scope struct \[5] $end -$var string 1 "3 \$tag $end -$var string 1 #3 HdlSome $end +$var string 1 {4 \$tag $end +$var string 1 |4 HdlSome $end $upscope $end $scope struct \[6] $end -$var string 1 $3 \$tag $end -$var string 1 %3 HdlSome $end +$var string 1 }4 \$tag $end +$var string 1 ~4 HdlSome $end $upscope $end $scope struct \[7] $end -$var string 1 &3 \$tag $end -$var string 1 '3 HdlSome $end +$var string 1 !5 \$tag $end +$var string 1 "5 HdlSome $end $upscope $end $upscope $end $scope struct in_flight_op_next_src_ready_flags $end $scope struct \[0] $end -$var wire 1 (3 \[0] $end -$var wire 1 )3 \[1] $end -$var wire 1 *3 \[2] $end +$var wire 1 #5 \[0] $end +$var wire 1 $5 \[1] $end +$var wire 1 %5 \[2] $end $upscope $end $scope struct \[1] $end -$var wire 1 +3 \[0] $end -$var wire 1 ,3 \[1] $end -$var wire 1 -3 \[2] $end +$var wire 1 &5 \[0] $end +$var wire 1 '5 \[1] $end +$var wire 1 (5 \[2] $end $upscope $end $scope struct \[2] $end -$var wire 1 .3 \[0] $end -$var wire 1 /3 \[1] $end -$var wire 1 03 \[2] $end +$var wire 1 )5 \[0] $end +$var wire 1 *5 \[1] $end +$var wire 1 +5 \[2] $end $upscope $end $scope struct \[3] $end -$var wire 1 13 \[0] $end -$var wire 1 23 \[1] $end -$var wire 1 33 \[2] $end +$var wire 1 ,5 \[0] $end +$var wire 1 -5 \[1] $end +$var wire 1 .5 \[2] $end $upscope $end $scope struct \[4] $end -$var wire 1 43 \[0] $end -$var wire 1 53 \[1] $end -$var wire 1 63 \[2] $end +$var wire 1 /5 \[0] $end +$var wire 1 05 \[1] $end +$var wire 1 15 \[2] $end $upscope $end $scope struct \[5] $end -$var wire 1 73 \[0] $end -$var wire 1 83 \[1] $end -$var wire 1 93 \[2] $end +$var wire 1 25 \[0] $end +$var wire 1 35 \[1] $end +$var wire 1 45 \[2] $end $upscope $end $scope struct \[6] $end -$var wire 1 :3 \[0] $end -$var wire 1 ;3 \[1] $end -$var wire 1 <3 \[2] $end +$var wire 1 55 \[0] $end +$var wire 1 65 \[1] $end +$var wire 1 75 \[2] $end $upscope $end $scope struct \[7] $end -$var wire 1 =3 \[0] $end -$var wire 1 >3 \[1] $end -$var wire 1 ?3 \[2] $end +$var wire 1 85 \[0] $end +$var wire 1 95 \[1] $end +$var wire 1 :5 \[2] $end $upscope $end $upscope $end $scope struct in_flight_op_canceling $end -$var wire 1 @3 \[0] $end -$var wire 1 A3 \[1] $end -$var wire 1 B3 \[2] $end -$var wire 1 C3 \[3] $end -$var wire 1 D3 \[4] $end -$var wire 1 E3 \[5] $end -$var wire 1 F3 \[6] $end -$var wire 1 G3 \[7] $end +$var wire 1 ;5 \[0] $end +$var wire 1 <5 \[1] $end +$var wire 1 =5 \[2] $end +$var wire 1 >5 \[3] $end +$var wire 1 ?5 \[4] $end +$var wire 1 @5 \[5] $end +$var wire 1 A5 \[6] $end +$var wire 1 B5 \[7] $end $upscope $end $scope struct in_flight_op_execute_starting $end -$var wire 1 H3 \[0] $end -$var wire 1 I3 \[1] $end -$var wire 1 J3 \[2] $end -$var wire 1 K3 \[3] $end -$var wire 1 L3 \[4] $end -$var wire 1 M3 \[5] $end -$var wire 1 N3 \[6] $end -$var wire 1 O3 \[7] $end +$var wire 1 C5 \[0] $end +$var wire 1 D5 \[1] $end +$var wire 1 E5 \[2] $end +$var wire 1 F5 \[3] $end +$var wire 1 G5 \[4] $end +$var wire 1 H5 \[5] $end +$var wire 1 I5 \[6] $end +$var wire 1 J5 \[7] $end $upscope $end $scope struct in_flight_op_execute_ending $end -$var wire 1 P3 \[0] $end -$var wire 1 Q3 \[1] $end -$var wire 1 R3 \[2] $end -$var wire 1 S3 \[3] $end -$var wire 1 T3 \[4] $end -$var wire 1 U3 \[5] $end -$var wire 1 V3 \[6] $end -$var wire 1 W3 \[7] $end +$var wire 1 K5 \[0] $end +$var wire 1 L5 \[1] $end +$var wire 1 M5 \[2] $end +$var wire 1 N5 \[3] $end +$var wire 1 O5 \[4] $end +$var wire 1 P5 \[5] $end +$var wire 1 Q5 \[6] $end +$var wire 1 R5 \[7] $end $upscope $end $scope struct dest_reg_2 $end -$var wire 4 X3 value $end +$var wire 4 S5 value $end $upscope $end $scope struct in_flight_op_src_regs_0 $end -$var wire 6 Y3 \[0] $end -$var wire 6 Z3 \[1] $end -$var wire 6 [3 \[2] $end +$var wire 6 T5 \[0] $end +$var wire 6 U5 \[1] $end +$var wire 6 V5 \[2] $end $upscope $end -$var wire 1 \3 cmp_eq $end +$var wire 1 W5 cmp_eq $end +$var wire 1 X5 cmp_eq_2 $end $scope struct firing_data_2 $end -$var string 1 ]3 \$tag $end +$var string 1 Y5 \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 ^3 \$tag $end +$var string 1 Z5 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 _3 prefix_pad $end +$var string 0 [5 prefix_pad $end $scope struct dest $end -$var wire 4 `3 value $end +$var wire 4 \5 value $end $upscope $end $scope struct src $end -$var wire 6 a3 \[0] $end -$var wire 6 b3 \[1] $end -$var wire 6 c3 \[2] $end +$var wire 6 ]5 \[0] $end +$var wire 6 ^5 \[1] $end +$var wire 6 _5 \[2] $end $upscope $end -$var wire 25 d3 imm_low $end -$var wire 1 e3 imm_sign $end +$var wire 25 `5 imm_low $end +$var wire 1 a5 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 f3 output_integer_mode $end +$var string 1 b5 output_integer_mode $end $upscope $end -$var wire 1 g3 invert_src0 $end -$var wire 1 h3 invert_carry_in $end -$var wire 1 i3 invert_carry_out $end -$var wire 1 j3 add_pc $end +$var wire 1 c5 invert_src0 $end +$var wire 1 d5 src1_is_carry_in $end +$var wire 1 e5 invert_carry_in $end +$var wire 1 f5 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 k3 prefix_pad $end +$var string 0 g5 prefix_pad $end $scope struct dest $end -$var wire 4 l3 value $end +$var wire 4 h5 value $end $upscope $end $scope struct src $end -$var wire 6 m3 \[0] $end -$var wire 6 n3 \[1] $end -$var wire 6 o3 \[2] $end +$var wire 6 i5 \[0] $end +$var wire 6 j5 \[1] $end +$var wire 6 k5 \[2] $end $upscope $end -$var wire 25 p3 imm_low $end -$var wire 1 q3 imm_sign $end +$var wire 25 l5 imm_low $end +$var wire 1 m5 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 r3 output_integer_mode $end +$var string 1 n5 output_integer_mode $end $upscope $end -$var wire 1 s3 invert_src0 $end -$var wire 1 t3 invert_carry_in $end -$var wire 1 u3 invert_carry_out $end -$var wire 1 v3 add_pc $end +$var wire 1 o5 invert_src0 $end +$var wire 1 p5 src1_is_carry_in $end +$var wire 1 q5 invert_carry_in $end +$var wire 1 r5 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 w3 prefix_pad $end +$var string 0 s5 prefix_pad $end $scope struct dest $end -$var wire 4 x3 value $end +$var wire 4 t5 value $end $upscope $end $scope struct src $end -$var wire 6 y3 \[0] $end -$var wire 6 z3 \[1] $end -$var wire 6 {3 \[2] $end +$var wire 6 u5 \[0] $end +$var wire 6 v5 \[1] $end +$var wire 6 w5 \[2] $end $upscope $end -$var wire 25 |3 imm_low $end -$var wire 1 }3 imm_sign $end +$var wire 25 x5 imm_low $end +$var wire 1 y5 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 ~3 output_integer_mode $end +$var string 1 z5 output_integer_mode $end $upscope $end -$var wire 4 !4 lut $end +$var wire 4 {5 lut $end $upscope $end $upscope $end +$var wire 64 |5 pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 "4 int_fp $end +$var wire 64 }5 int_fp $end $scope struct flags $end -$var wire 1 #4 pwr_ca_x86_cf $end -$var wire 1 $4 pwr_ca32_x86_af $end -$var wire 1 %4 pwr_ov_x86_of $end -$var wire 1 &4 pwr_ov32_x86_df $end -$var wire 1 '4 pwr_cr_lt_x86_sf $end -$var wire 1 (4 pwr_cr_gt_x86_pf $end -$var wire 1 )4 pwr_cr_eq_x86_zf $end -$var wire 1 *4 pwr_so $end +$var wire 1 ~5 pwr_ca_x86_cf $end +$var wire 1 !6 pwr_ca32_x86_af $end +$var wire 1 "6 pwr_ov_x86_of $end +$var wire 1 #6 pwr_ov32_x86_df $end +$var wire 1 $6 pwr_cr_lt_x86_sf $end +$var wire 1 %6 pwr_cr_gt_x86_pf $end +$var wire 1 &6 pwr_cr_eq_x86_zf $end +$var wire 1 '6 pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 +4 int_fp $end +$var wire 64 (6 int_fp $end $scope struct flags $end -$var wire 1 ,4 pwr_ca_x86_cf $end -$var wire 1 -4 pwr_ca32_x86_af $end -$var wire 1 .4 pwr_ov_x86_of $end -$var wire 1 /4 pwr_ov32_x86_df $end -$var wire 1 04 pwr_cr_lt_x86_sf $end -$var wire 1 14 pwr_cr_gt_x86_pf $end -$var wire 1 24 pwr_cr_eq_x86_zf $end -$var wire 1 34 pwr_so $end +$var wire 1 )6 pwr_ca_x86_cf $end +$var wire 1 *6 pwr_ca32_x86_af $end +$var wire 1 +6 pwr_ov_x86_of $end +$var wire 1 ,6 pwr_ov32_x86_df $end +$var wire 1 -6 pwr_cr_lt_x86_sf $end +$var wire 1 .6 pwr_cr_gt_x86_pf $end +$var wire 1 /6 pwr_cr_eq_x86_zf $end +$var wire 1 06 pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 44 int_fp $end +$var wire 64 16 int_fp $end $scope struct flags $end -$var wire 1 54 pwr_ca_x86_cf $end -$var wire 1 64 pwr_ca32_x86_af $end -$var wire 1 74 pwr_ov_x86_of $end -$var wire 1 84 pwr_ov32_x86_df $end -$var wire 1 94 pwr_cr_lt_x86_sf $end -$var wire 1 :4 pwr_cr_gt_x86_pf $end -$var wire 1 ;4 pwr_cr_eq_x86_zf $end -$var wire 1 <4 pwr_so $end +$var wire 1 26 pwr_ca_x86_cf $end +$var wire 1 36 pwr_ca32_x86_af $end +$var wire 1 46 pwr_ov_x86_of $end +$var wire 1 56 pwr_ov32_x86_df $end +$var wire 1 66 pwr_cr_lt_x86_sf $end +$var wire 1 76 pwr_cr_gt_x86_pf $end +$var wire 1 86 pwr_cr_eq_x86_zf $end +$var wire 1 96 pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_3 $end -$var wire 4 =4 value $end +$var wire 4 :6 value $end $upscope $end $scope struct dest_reg_4 $end -$var wire 4 >4 value $end +$var wire 4 ;6 value $end $upscope $end $scope struct in_flight_op_src_regs_1 $end -$var wire 6 ?4 \[0] $end -$var wire 6 @4 \[1] $end -$var wire 6 A4 \[2] $end +$var wire 6 <6 \[0] $end +$var wire 6 =6 \[1] $end +$var wire 6 >6 \[2] $end $upscope $end -$var wire 1 B4 cmp_eq_2 $end +$var wire 1 ?6 cmp_eq_3 $end +$var wire 1 @6 cmp_eq_4 $end $scope struct firing_data_3 $end -$var string 1 C4 \$tag $end +$var string 1 A6 \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 D4 \$tag $end +$var string 1 B6 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 E4 prefix_pad $end +$var string 0 C6 prefix_pad $end $scope struct dest $end -$var wire 4 F4 value $end +$var wire 4 D6 value $end $upscope $end $scope struct src $end -$var wire 6 G4 \[0] $end -$var wire 6 H4 \[1] $end -$var wire 6 I4 \[2] $end +$var wire 6 E6 \[0] $end +$var wire 6 F6 \[1] $end +$var wire 6 G6 \[2] $end $upscope $end -$var wire 25 J4 imm_low $end -$var wire 1 K4 imm_sign $end +$var wire 25 H6 imm_low $end +$var wire 1 I6 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 L4 output_integer_mode $end +$var string 1 J6 output_integer_mode $end $upscope $end -$var wire 1 M4 invert_src0 $end -$var wire 1 N4 invert_carry_in $end -$var wire 1 O4 invert_carry_out $end -$var wire 1 P4 add_pc $end +$var wire 1 K6 invert_src0 $end +$var wire 1 L6 src1_is_carry_in $end +$var wire 1 M6 invert_carry_in $end +$var wire 1 N6 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 Q4 prefix_pad $end +$var string 0 O6 prefix_pad $end $scope struct dest $end -$var wire 4 R4 value $end +$var wire 4 P6 value $end $upscope $end $scope struct src $end -$var wire 6 S4 \[0] $end -$var wire 6 T4 \[1] $end -$var wire 6 U4 \[2] $end +$var wire 6 Q6 \[0] $end +$var wire 6 R6 \[1] $end +$var wire 6 S6 \[2] $end $upscope $end -$var wire 25 V4 imm_low $end -$var wire 1 W4 imm_sign $end +$var wire 25 T6 imm_low $end +$var wire 1 U6 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 X4 output_integer_mode $end +$var string 1 V6 output_integer_mode $end $upscope $end -$var wire 1 Y4 invert_src0 $end -$var wire 1 Z4 invert_carry_in $end -$var wire 1 [4 invert_carry_out $end -$var wire 1 \4 add_pc $end +$var wire 1 W6 invert_src0 $end +$var wire 1 X6 src1_is_carry_in $end +$var wire 1 Y6 invert_carry_in $end +$var wire 1 Z6 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 ]4 prefix_pad $end +$var string 0 [6 prefix_pad $end $scope struct dest $end -$var wire 4 ^4 value $end +$var wire 4 \6 value $end $upscope $end $scope struct src $end -$var wire 6 _4 \[0] $end -$var wire 6 `4 \[1] $end -$var wire 6 a4 \[2] $end +$var wire 6 ]6 \[0] $end +$var wire 6 ^6 \[1] $end +$var wire 6 _6 \[2] $end $upscope $end -$var wire 25 b4 imm_low $end -$var wire 1 c4 imm_sign $end +$var wire 25 `6 imm_low $end +$var wire 1 a6 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 d4 output_integer_mode $end +$var string 1 b6 output_integer_mode $end $upscope $end -$var wire 4 e4 lut $end +$var wire 4 c6 lut $end $upscope $end $upscope $end +$var wire 64 d6 pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 f4 int_fp $end +$var wire 64 e6 int_fp $end $scope struct flags $end -$var wire 1 g4 pwr_ca_x86_cf $end -$var wire 1 h4 pwr_ca32_x86_af $end -$var wire 1 i4 pwr_ov_x86_of $end -$var wire 1 j4 pwr_ov32_x86_df $end -$var wire 1 k4 pwr_cr_lt_x86_sf $end -$var wire 1 l4 pwr_cr_gt_x86_pf $end -$var wire 1 m4 pwr_cr_eq_x86_zf $end -$var wire 1 n4 pwr_so $end +$var wire 1 f6 pwr_ca_x86_cf $end +$var wire 1 g6 pwr_ca32_x86_af $end +$var wire 1 h6 pwr_ov_x86_of $end +$var wire 1 i6 pwr_ov32_x86_df $end +$var wire 1 j6 pwr_cr_lt_x86_sf $end +$var wire 1 k6 pwr_cr_gt_x86_pf $end +$var wire 1 l6 pwr_cr_eq_x86_zf $end +$var wire 1 m6 pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 o4 int_fp $end +$var wire 64 n6 int_fp $end $scope struct flags $end -$var wire 1 p4 pwr_ca_x86_cf $end -$var wire 1 q4 pwr_ca32_x86_af $end -$var wire 1 r4 pwr_ov_x86_of $end -$var wire 1 s4 pwr_ov32_x86_df $end -$var wire 1 t4 pwr_cr_lt_x86_sf $end -$var wire 1 u4 pwr_cr_gt_x86_pf $end -$var wire 1 v4 pwr_cr_eq_x86_zf $end -$var wire 1 w4 pwr_so $end +$var wire 1 o6 pwr_ca_x86_cf $end +$var wire 1 p6 pwr_ca32_x86_af $end +$var wire 1 q6 pwr_ov_x86_of $end +$var wire 1 r6 pwr_ov32_x86_df $end +$var wire 1 s6 pwr_cr_lt_x86_sf $end +$var wire 1 t6 pwr_cr_gt_x86_pf $end +$var wire 1 u6 pwr_cr_eq_x86_zf $end +$var wire 1 v6 pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 x4 int_fp $end +$var wire 64 w6 int_fp $end $scope struct flags $end -$var wire 1 y4 pwr_ca_x86_cf $end -$var wire 1 z4 pwr_ca32_x86_af $end -$var wire 1 {4 pwr_ov_x86_of $end -$var wire 1 |4 pwr_ov32_x86_df $end -$var wire 1 }4 pwr_cr_lt_x86_sf $end -$var wire 1 ~4 pwr_cr_gt_x86_pf $end -$var wire 1 !5 pwr_cr_eq_x86_zf $end -$var wire 1 "5 pwr_so $end +$var wire 1 x6 pwr_ca_x86_cf $end +$var wire 1 y6 pwr_ca32_x86_af $end +$var wire 1 z6 pwr_ov_x86_of $end +$var wire 1 {6 pwr_ov32_x86_df $end +$var wire 1 |6 pwr_cr_lt_x86_sf $end +$var wire 1 }6 pwr_cr_gt_x86_pf $end +$var wire 1 ~6 pwr_cr_eq_x86_zf $end +$var wire 1 !7 pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_5 $end -$var wire 4 #5 value $end +$var wire 4 "7 value $end $upscope $end $scope struct dest_reg_6 $end -$var wire 4 $5 value $end +$var wire 4 #7 value $end $upscope $end $scope struct in_flight_op_src_regs_2 $end -$var wire 6 %5 \[0] $end -$var wire 6 &5 \[1] $end -$var wire 6 '5 \[2] $end +$var wire 6 $7 \[0] $end +$var wire 6 %7 \[1] $end +$var wire 6 &7 \[2] $end $upscope $end -$var wire 1 (5 cmp_eq_3 $end +$var wire 1 '7 cmp_eq_5 $end +$var wire 1 (7 cmp_eq_6 $end $scope struct firing_data_4 $end -$var string 1 )5 \$tag $end +$var string 1 )7 \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 *5 \$tag $end +$var string 1 *7 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 +5 prefix_pad $end +$var string 0 +7 prefix_pad $end $scope struct dest $end -$var wire 4 ,5 value $end +$var wire 4 ,7 value $end $upscope $end $scope struct src $end -$var wire 6 -5 \[0] $end -$var wire 6 .5 \[1] $end -$var wire 6 /5 \[2] $end +$var wire 6 -7 \[0] $end +$var wire 6 .7 \[1] $end +$var wire 6 /7 \[2] $end $upscope $end -$var wire 25 05 imm_low $end -$var wire 1 15 imm_sign $end +$var wire 25 07 imm_low $end +$var wire 1 17 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 25 output_integer_mode $end +$var string 1 27 output_integer_mode $end $upscope $end -$var wire 1 35 invert_src0 $end -$var wire 1 45 invert_carry_in $end -$var wire 1 55 invert_carry_out $end -$var wire 1 65 add_pc $end +$var wire 1 37 invert_src0 $end +$var wire 1 47 src1_is_carry_in $end +$var wire 1 57 invert_carry_in $end +$var wire 1 67 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 75 prefix_pad $end +$var string 0 77 prefix_pad $end $scope struct dest $end -$var wire 4 85 value $end +$var wire 4 87 value $end $upscope $end $scope struct src $end -$var wire 6 95 \[0] $end -$var wire 6 :5 \[1] $end -$var wire 6 ;5 \[2] $end +$var wire 6 97 \[0] $end +$var wire 6 :7 \[1] $end +$var wire 6 ;7 \[2] $end $upscope $end -$var wire 25 <5 imm_low $end -$var wire 1 =5 imm_sign $end +$var wire 25 <7 imm_low $end +$var wire 1 =7 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 >5 output_integer_mode $end +$var string 1 >7 output_integer_mode $end $upscope $end -$var wire 1 ?5 invert_src0 $end -$var wire 1 @5 invert_carry_in $end -$var wire 1 A5 invert_carry_out $end -$var wire 1 B5 add_pc $end +$var wire 1 ?7 invert_src0 $end +$var wire 1 @7 src1_is_carry_in $end +$var wire 1 A7 invert_carry_in $end +$var wire 1 B7 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 C5 prefix_pad $end +$var string 0 C7 prefix_pad $end $scope struct dest $end -$var wire 4 D5 value $end +$var wire 4 D7 value $end $upscope $end $scope struct src $end -$var wire 6 E5 \[0] $end -$var wire 6 F5 \[1] $end -$var wire 6 G5 \[2] $end +$var wire 6 E7 \[0] $end +$var wire 6 F7 \[1] $end +$var wire 6 G7 \[2] $end $upscope $end -$var wire 25 H5 imm_low $end -$var wire 1 I5 imm_sign $end +$var wire 25 H7 imm_low $end +$var wire 1 I7 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 J5 output_integer_mode $end +$var string 1 J7 output_integer_mode $end $upscope $end -$var wire 4 K5 lut $end +$var wire 4 K7 lut $end $upscope $end $upscope $end +$var wire 64 L7 pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 L5 int_fp $end +$var wire 64 M7 int_fp $end $scope struct flags $end -$var wire 1 M5 pwr_ca_x86_cf $end -$var wire 1 N5 pwr_ca32_x86_af $end -$var wire 1 O5 pwr_ov_x86_of $end -$var wire 1 P5 pwr_ov32_x86_df $end -$var wire 1 Q5 pwr_cr_lt_x86_sf $end -$var wire 1 R5 pwr_cr_gt_x86_pf $end -$var wire 1 S5 pwr_cr_eq_x86_zf $end -$var wire 1 T5 pwr_so $end +$var wire 1 N7 pwr_ca_x86_cf $end +$var wire 1 O7 pwr_ca32_x86_af $end +$var wire 1 P7 pwr_ov_x86_of $end +$var wire 1 Q7 pwr_ov32_x86_df $end +$var wire 1 R7 pwr_cr_lt_x86_sf $end +$var wire 1 S7 pwr_cr_gt_x86_pf $end +$var wire 1 T7 pwr_cr_eq_x86_zf $end +$var wire 1 U7 pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 U5 int_fp $end +$var wire 64 V7 int_fp $end $scope struct flags $end -$var wire 1 V5 pwr_ca_x86_cf $end -$var wire 1 W5 pwr_ca32_x86_af $end -$var wire 1 X5 pwr_ov_x86_of $end -$var wire 1 Y5 pwr_ov32_x86_df $end -$var wire 1 Z5 pwr_cr_lt_x86_sf $end -$var wire 1 [5 pwr_cr_gt_x86_pf $end -$var wire 1 \5 pwr_cr_eq_x86_zf $end -$var wire 1 ]5 pwr_so $end +$var wire 1 W7 pwr_ca_x86_cf $end +$var wire 1 X7 pwr_ca32_x86_af $end +$var wire 1 Y7 pwr_ov_x86_of $end +$var wire 1 Z7 pwr_ov32_x86_df $end +$var wire 1 [7 pwr_cr_lt_x86_sf $end +$var wire 1 \7 pwr_cr_gt_x86_pf $end +$var wire 1 ]7 pwr_cr_eq_x86_zf $end +$var wire 1 ^7 pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 ^5 int_fp $end +$var wire 64 _7 int_fp $end $scope struct flags $end -$var wire 1 _5 pwr_ca_x86_cf $end -$var wire 1 `5 pwr_ca32_x86_af $end -$var wire 1 a5 pwr_ov_x86_of $end -$var wire 1 b5 pwr_ov32_x86_df $end -$var wire 1 c5 pwr_cr_lt_x86_sf $end -$var wire 1 d5 pwr_cr_gt_x86_pf $end -$var wire 1 e5 pwr_cr_eq_x86_zf $end -$var wire 1 f5 pwr_so $end +$var wire 1 `7 pwr_ca_x86_cf $end +$var wire 1 a7 pwr_ca32_x86_af $end +$var wire 1 b7 pwr_ov_x86_of $end +$var wire 1 c7 pwr_ov32_x86_df $end +$var wire 1 d7 pwr_cr_lt_x86_sf $end +$var wire 1 e7 pwr_cr_gt_x86_pf $end +$var wire 1 f7 pwr_cr_eq_x86_zf $end +$var wire 1 g7 pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_7 $end -$var wire 4 g5 value $end +$var wire 4 h7 value $end $upscope $end $scope struct dest_reg_8 $end -$var wire 4 h5 value $end +$var wire 4 i7 value $end $upscope $end $scope struct in_flight_op_src_regs_3 $end -$var wire 6 i5 \[0] $end -$var wire 6 j5 \[1] $end -$var wire 6 k5 \[2] $end +$var wire 6 j7 \[0] $end +$var wire 6 k7 \[1] $end +$var wire 6 l7 \[2] $end $upscope $end -$var wire 1 l5 cmp_eq_4 $end +$var wire 1 m7 cmp_eq_7 $end +$var wire 1 n7 cmp_eq_8 $end $scope struct firing_data_5 $end -$var string 1 m5 \$tag $end +$var string 1 o7 \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 n5 \$tag $end +$var string 1 p7 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 o5 prefix_pad $end +$var string 0 q7 prefix_pad $end $scope struct dest $end -$var wire 4 p5 value $end +$var wire 4 r7 value $end $upscope $end $scope struct src $end -$var wire 6 q5 \[0] $end -$var wire 6 r5 \[1] $end -$var wire 6 s5 \[2] $end +$var wire 6 s7 \[0] $end +$var wire 6 t7 \[1] $end +$var wire 6 u7 \[2] $end $upscope $end -$var wire 25 t5 imm_low $end -$var wire 1 u5 imm_sign $end +$var wire 25 v7 imm_low $end +$var wire 1 w7 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 v5 output_integer_mode $end +$var string 1 x7 output_integer_mode $end $upscope $end -$var wire 1 w5 invert_src0 $end -$var wire 1 x5 invert_carry_in $end -$var wire 1 y5 invert_carry_out $end -$var wire 1 z5 add_pc $end +$var wire 1 y7 invert_src0 $end +$var wire 1 z7 src1_is_carry_in $end +$var wire 1 {7 invert_carry_in $end +$var wire 1 |7 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 {5 prefix_pad $end +$var string 0 }7 prefix_pad $end $scope struct dest $end -$var wire 4 |5 value $end +$var wire 4 ~7 value $end $upscope $end $scope struct src $end -$var wire 6 }5 \[0] $end -$var wire 6 ~5 \[1] $end -$var wire 6 !6 \[2] $end +$var wire 6 !8 \[0] $end +$var wire 6 "8 \[1] $end +$var wire 6 #8 \[2] $end $upscope $end -$var wire 25 "6 imm_low $end -$var wire 1 #6 imm_sign $end +$var wire 25 $8 imm_low $end +$var wire 1 %8 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 $6 output_integer_mode $end +$var string 1 &8 output_integer_mode $end $upscope $end -$var wire 1 %6 invert_src0 $end -$var wire 1 &6 invert_carry_in $end -$var wire 1 '6 invert_carry_out $end -$var wire 1 (6 add_pc $end +$var wire 1 '8 invert_src0 $end +$var wire 1 (8 src1_is_carry_in $end +$var wire 1 )8 invert_carry_in $end +$var wire 1 *8 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 )6 prefix_pad $end +$var string 0 +8 prefix_pad $end $scope struct dest $end -$var wire 4 *6 value $end +$var wire 4 ,8 value $end $upscope $end $scope struct src $end -$var wire 6 +6 \[0] $end -$var wire 6 ,6 \[1] $end -$var wire 6 -6 \[2] $end +$var wire 6 -8 \[0] $end +$var wire 6 .8 \[1] $end +$var wire 6 /8 \[2] $end $upscope $end -$var wire 25 .6 imm_low $end -$var wire 1 /6 imm_sign $end +$var wire 25 08 imm_low $end +$var wire 1 18 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 06 output_integer_mode $end +$var string 1 28 output_integer_mode $end $upscope $end -$var wire 4 16 lut $end +$var wire 4 38 lut $end $upscope $end $upscope $end +$var wire 64 48 pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 26 int_fp $end +$var wire 64 58 int_fp $end $scope struct flags $end -$var wire 1 36 pwr_ca_x86_cf $end -$var wire 1 46 pwr_ca32_x86_af $end -$var wire 1 56 pwr_ov_x86_of $end -$var wire 1 66 pwr_ov32_x86_df $end -$var wire 1 76 pwr_cr_lt_x86_sf $end -$var wire 1 86 pwr_cr_gt_x86_pf $end -$var wire 1 96 pwr_cr_eq_x86_zf $end -$var wire 1 :6 pwr_so $end +$var wire 1 68 pwr_ca_x86_cf $end +$var wire 1 78 pwr_ca32_x86_af $end +$var wire 1 88 pwr_ov_x86_of $end +$var wire 1 98 pwr_ov32_x86_df $end +$var wire 1 :8 pwr_cr_lt_x86_sf $end +$var wire 1 ;8 pwr_cr_gt_x86_pf $end +$var wire 1 <8 pwr_cr_eq_x86_zf $end +$var wire 1 =8 pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 ;6 int_fp $end +$var wire 64 >8 int_fp $end $scope struct flags $end -$var wire 1 <6 pwr_ca_x86_cf $end -$var wire 1 =6 pwr_ca32_x86_af $end -$var wire 1 >6 pwr_ov_x86_of $end -$var wire 1 ?6 pwr_ov32_x86_df $end -$var wire 1 @6 pwr_cr_lt_x86_sf $end -$var wire 1 A6 pwr_cr_gt_x86_pf $end -$var wire 1 B6 pwr_cr_eq_x86_zf $end -$var wire 1 C6 pwr_so $end +$var wire 1 ?8 pwr_ca_x86_cf $end +$var wire 1 @8 pwr_ca32_x86_af $end +$var wire 1 A8 pwr_ov_x86_of $end +$var wire 1 B8 pwr_ov32_x86_df $end +$var wire 1 C8 pwr_cr_lt_x86_sf $end +$var wire 1 D8 pwr_cr_gt_x86_pf $end +$var wire 1 E8 pwr_cr_eq_x86_zf $end +$var wire 1 F8 pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 D6 int_fp $end +$var wire 64 G8 int_fp $end $scope struct flags $end -$var wire 1 E6 pwr_ca_x86_cf $end -$var wire 1 F6 pwr_ca32_x86_af $end -$var wire 1 G6 pwr_ov_x86_of $end -$var wire 1 H6 pwr_ov32_x86_df $end -$var wire 1 I6 pwr_cr_lt_x86_sf $end -$var wire 1 J6 pwr_cr_gt_x86_pf $end -$var wire 1 K6 pwr_cr_eq_x86_zf $end -$var wire 1 L6 pwr_so $end +$var wire 1 H8 pwr_ca_x86_cf $end +$var wire 1 I8 pwr_ca32_x86_af $end +$var wire 1 J8 pwr_ov_x86_of $end +$var wire 1 K8 pwr_ov32_x86_df $end +$var wire 1 L8 pwr_cr_lt_x86_sf $end +$var wire 1 M8 pwr_cr_gt_x86_pf $end +$var wire 1 N8 pwr_cr_eq_x86_zf $end +$var wire 1 O8 pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_9 $end -$var wire 4 M6 value $end +$var wire 4 P8 value $end $upscope $end $scope struct dest_reg_10 $end -$var wire 4 N6 value $end +$var wire 4 Q8 value $end $upscope $end $scope struct in_flight_op_src_regs_4 $end -$var wire 6 O6 \[0] $end -$var wire 6 P6 \[1] $end -$var wire 6 Q6 \[2] $end +$var wire 6 R8 \[0] $end +$var wire 6 S8 \[1] $end +$var wire 6 T8 \[2] $end $upscope $end -$var wire 1 R6 cmp_eq_5 $end +$var wire 1 U8 cmp_eq_9 $end +$var wire 1 V8 cmp_eq_10 $end $scope struct firing_data_6 $end -$var string 1 S6 \$tag $end +$var string 1 W8 \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 T6 \$tag $end +$var string 1 X8 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 U6 prefix_pad $end +$var string 0 Y8 prefix_pad $end $scope struct dest $end -$var wire 4 V6 value $end +$var wire 4 Z8 value $end $upscope $end $scope struct src $end -$var wire 6 W6 \[0] $end -$var wire 6 X6 \[1] $end -$var wire 6 Y6 \[2] $end +$var wire 6 [8 \[0] $end +$var wire 6 \8 \[1] $end +$var wire 6 ]8 \[2] $end $upscope $end -$var wire 25 Z6 imm_low $end -$var wire 1 [6 imm_sign $end +$var wire 25 ^8 imm_low $end +$var wire 1 _8 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 \6 output_integer_mode $end +$var string 1 `8 output_integer_mode $end $upscope $end -$var wire 1 ]6 invert_src0 $end -$var wire 1 ^6 invert_carry_in $end -$var wire 1 _6 invert_carry_out $end -$var wire 1 `6 add_pc $end +$var wire 1 a8 invert_src0 $end +$var wire 1 b8 src1_is_carry_in $end +$var wire 1 c8 invert_carry_in $end +$var wire 1 d8 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 a6 prefix_pad $end -$scope struct dest $end -$var wire 4 b6 value $end -$upscope $end -$scope struct src $end -$var wire 6 c6 \[0] $end -$var wire 6 d6 \[1] $end -$var wire 6 e6 \[2] $end -$upscope $end -$var wire 25 f6 imm_low $end -$var wire 1 g6 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 h6 output_integer_mode $end -$upscope $end -$var wire 1 i6 invert_src0 $end -$var wire 1 j6 invert_carry_in $end -$var wire 1 k6 invert_carry_out $end -$var wire 1 l6 add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 m6 prefix_pad $end -$scope struct dest $end -$var wire 4 n6 value $end -$upscope $end -$scope struct src $end -$var wire 6 o6 \[0] $end -$var wire 6 p6 \[1] $end -$var wire 6 q6 \[2] $end -$upscope $end -$var wire 25 r6 imm_low $end -$var wire 1 s6 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 t6 output_integer_mode $end -$upscope $end -$var wire 4 u6 lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 v6 int_fp $end -$scope struct flags $end -$var wire 1 w6 pwr_ca_x86_cf $end -$var wire 1 x6 pwr_ca32_x86_af $end -$var wire 1 y6 pwr_ov_x86_of $end -$var wire 1 z6 pwr_ov32_x86_df $end -$var wire 1 {6 pwr_cr_lt_x86_sf $end -$var wire 1 |6 pwr_cr_gt_x86_pf $end -$var wire 1 }6 pwr_cr_eq_x86_zf $end -$var wire 1 ~6 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 !7 int_fp $end -$scope struct flags $end -$var wire 1 "7 pwr_ca_x86_cf $end -$var wire 1 #7 pwr_ca32_x86_af $end -$var wire 1 $7 pwr_ov_x86_of $end -$var wire 1 %7 pwr_ov32_x86_df $end -$var wire 1 &7 pwr_cr_lt_x86_sf $end -$var wire 1 '7 pwr_cr_gt_x86_pf $end -$var wire 1 (7 pwr_cr_eq_x86_zf $end -$var wire 1 )7 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 *7 int_fp $end -$scope struct flags $end -$var wire 1 +7 pwr_ca_x86_cf $end -$var wire 1 ,7 pwr_ca32_x86_af $end -$var wire 1 -7 pwr_ov_x86_of $end -$var wire 1 .7 pwr_ov32_x86_df $end -$var wire 1 /7 pwr_cr_lt_x86_sf $end -$var wire 1 07 pwr_cr_gt_x86_pf $end -$var wire 1 17 pwr_cr_eq_x86_zf $end -$var wire 1 27 pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_11 $end -$var wire 4 37 value $end -$upscope $end -$scope struct dest_reg_12 $end -$var wire 4 47 value $end -$upscope $end -$scope struct in_flight_op_src_regs_5 $end -$var wire 6 57 \[0] $end -$var wire 6 67 \[1] $end -$var wire 6 77 \[2] $end -$upscope $end -$var wire 1 87 cmp_eq_6 $end -$scope struct firing_data_7 $end -$var string 1 97 \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 :7 \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ;7 prefix_pad $end -$scope struct dest $end -$var wire 4 <7 value $end -$upscope $end -$scope struct src $end -$var wire 6 =7 \[0] $end -$var wire 6 >7 \[1] $end -$var wire 6 ?7 \[2] $end -$upscope $end -$var wire 25 @7 imm_low $end -$var wire 1 A7 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 B7 output_integer_mode $end -$upscope $end -$var wire 1 C7 invert_src0 $end -$var wire 1 D7 invert_carry_in $end -$var wire 1 E7 invert_carry_out $end -$var wire 1 F7 add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 G7 prefix_pad $end -$scope struct dest $end -$var wire 4 H7 value $end -$upscope $end -$scope struct src $end -$var wire 6 I7 \[0] $end -$var wire 6 J7 \[1] $end -$var wire 6 K7 \[2] $end -$upscope $end -$var wire 25 L7 imm_low $end -$var wire 1 M7 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 N7 output_integer_mode $end -$upscope $end -$var wire 1 O7 invert_src0 $end -$var wire 1 P7 invert_carry_in $end -$var wire 1 Q7 invert_carry_out $end -$var wire 1 R7 add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 S7 prefix_pad $end -$scope struct dest $end -$var wire 4 T7 value $end -$upscope $end -$scope struct src $end -$var wire 6 U7 \[0] $end -$var wire 6 V7 \[1] $end -$var wire 6 W7 \[2] $end -$upscope $end -$var wire 25 X7 imm_low $end -$var wire 1 Y7 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 Z7 output_integer_mode $end -$upscope $end -$var wire 4 [7 lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 \7 int_fp $end -$scope struct flags $end -$var wire 1 ]7 pwr_ca_x86_cf $end -$var wire 1 ^7 pwr_ca32_x86_af $end -$var wire 1 _7 pwr_ov_x86_of $end -$var wire 1 `7 pwr_ov32_x86_df $end -$var wire 1 a7 pwr_cr_lt_x86_sf $end -$var wire 1 b7 pwr_cr_gt_x86_pf $end -$var wire 1 c7 pwr_cr_eq_x86_zf $end -$var wire 1 d7 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 e7 int_fp $end -$scope struct flags $end -$var wire 1 f7 pwr_ca_x86_cf $end -$var wire 1 g7 pwr_ca32_x86_af $end -$var wire 1 h7 pwr_ov_x86_of $end -$var wire 1 i7 pwr_ov32_x86_df $end -$var wire 1 j7 pwr_cr_lt_x86_sf $end -$var wire 1 k7 pwr_cr_gt_x86_pf $end -$var wire 1 l7 pwr_cr_eq_x86_zf $end -$var wire 1 m7 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 n7 int_fp $end -$scope struct flags $end -$var wire 1 o7 pwr_ca_x86_cf $end -$var wire 1 p7 pwr_ca32_x86_af $end -$var wire 1 q7 pwr_ov_x86_of $end -$var wire 1 r7 pwr_ov32_x86_df $end -$var wire 1 s7 pwr_cr_lt_x86_sf $end -$var wire 1 t7 pwr_cr_gt_x86_pf $end -$var wire 1 u7 pwr_cr_eq_x86_zf $end -$var wire 1 v7 pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_13 $end -$var wire 4 w7 value $end -$upscope $end -$scope struct dest_reg_14 $end -$var wire 4 x7 value $end -$upscope $end -$scope struct in_flight_op_src_regs_6 $end -$var wire 6 y7 \[0] $end -$var wire 6 z7 \[1] $end -$var wire 6 {7 \[2] $end -$upscope $end -$var wire 1 |7 cmp_eq_7 $end -$scope struct firing_data_8 $end -$var string 1 }7 \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 ~7 \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 !8 prefix_pad $end -$scope struct dest $end -$var wire 4 "8 value $end -$upscope $end -$scope struct src $end -$var wire 6 #8 \[0] $end -$var wire 6 $8 \[1] $end -$var wire 6 %8 \[2] $end -$upscope $end -$var wire 25 &8 imm_low $end -$var wire 1 '8 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 (8 output_integer_mode $end -$upscope $end -$var wire 1 )8 invert_src0 $end -$var wire 1 *8 invert_carry_in $end -$var wire 1 +8 invert_carry_out $end -$var wire 1 ,8 add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 -8 prefix_pad $end -$scope struct dest $end -$var wire 4 .8 value $end -$upscope $end -$scope struct src $end -$var wire 6 /8 \[0] $end -$var wire 6 08 \[1] $end -$var wire 6 18 \[2] $end -$upscope $end -$var wire 25 28 imm_low $end -$var wire 1 38 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 48 output_integer_mode $end -$upscope $end -$var wire 1 58 invert_src0 $end -$var wire 1 68 invert_carry_in $end -$var wire 1 78 invert_carry_out $end -$var wire 1 88 add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 98 prefix_pad $end -$scope struct dest $end -$var wire 4 :8 value $end -$upscope $end -$scope struct src $end -$var wire 6 ;8 \[0] $end -$var wire 6 <8 \[1] $end -$var wire 6 =8 \[2] $end -$upscope $end -$var wire 25 >8 imm_low $end -$var wire 1 ?8 imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 @8 output_integer_mode $end -$upscope $end -$var wire 4 A8 lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 B8 int_fp $end -$scope struct flags $end -$var wire 1 C8 pwr_ca_x86_cf $end -$var wire 1 D8 pwr_ca32_x86_af $end -$var wire 1 E8 pwr_ov_x86_of $end -$var wire 1 F8 pwr_ov32_x86_df $end -$var wire 1 G8 pwr_cr_lt_x86_sf $end -$var wire 1 H8 pwr_cr_gt_x86_pf $end -$var wire 1 I8 pwr_cr_eq_x86_zf $end -$var wire 1 J8 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 K8 int_fp $end -$scope struct flags $end -$var wire 1 L8 pwr_ca_x86_cf $end -$var wire 1 M8 pwr_ca32_x86_af $end -$var wire 1 N8 pwr_ov_x86_of $end -$var wire 1 O8 pwr_ov32_x86_df $end -$var wire 1 P8 pwr_cr_lt_x86_sf $end -$var wire 1 Q8 pwr_cr_gt_x86_pf $end -$var wire 1 R8 pwr_cr_eq_x86_zf $end -$var wire 1 S8 pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 T8 int_fp $end -$scope struct flags $end -$var wire 1 U8 pwr_ca_x86_cf $end -$var wire 1 V8 pwr_ca32_x86_af $end -$var wire 1 W8 pwr_ov_x86_of $end -$var wire 1 X8 pwr_ov32_x86_df $end -$var wire 1 Y8 pwr_cr_lt_x86_sf $end -$var wire 1 Z8 pwr_cr_gt_x86_pf $end -$var wire 1 [8 pwr_cr_eq_x86_zf $end -$var wire 1 \8 pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_15 $end -$var wire 4 ]8 value $end -$upscope $end -$scope struct dest_reg_16 $end -$var wire 4 ^8 value $end -$upscope $end -$scope struct in_flight_op_src_regs_7 $end -$var wire 6 _8 \[0] $end -$var wire 6 `8 \[1] $end -$var wire 6 a8 \[2] $end -$upscope $end -$var wire 1 b8 cmp_eq_8 $end -$scope struct firing_data_9 $end -$var string 1 c8 \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 d8 \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end $var string 0 e8 prefix_pad $end $scope struct dest $end $var wire 4 f8 value $end @@ -8608,11 +9062,11 @@ $upscope $end $var string 1 l8 output_integer_mode $end $upscope $end $var wire 1 m8 invert_src0 $end -$var wire 1 n8 invert_carry_in $end -$var wire 1 o8 invert_carry_out $end +$var wire 1 n8 src1_is_carry_in $end +$var wire 1 o8 invert_carry_in $end $var wire 1 p8 add_pc $end $upscope $end -$scope struct AddSubI $end +$scope struct Logical $end $scope struct alu_common $end $scope struct common $end $var string 0 q8 prefix_pad $end @@ -8631,385 +9085,507 @@ $upscope $end $upscope $end $var string 1 x8 output_integer_mode $end $upscope $end -$var wire 1 y8 invert_src0 $end -$var wire 1 z8 invert_carry_in $end -$var wire 1 {8 invert_carry_out $end -$var wire 1 |8 add_pc $end +$var wire 4 y8 lut $end +$upscope $end +$upscope $end +$var wire 64 z8 pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 {8 int_fp $end +$scope struct flags $end +$var wire 1 |8 pwr_ca_x86_cf $end +$var wire 1 }8 pwr_ca32_x86_af $end +$var wire 1 ~8 pwr_ov_x86_of $end +$var wire 1 !9 pwr_ov32_x86_df $end +$var wire 1 "9 pwr_cr_lt_x86_sf $end +$var wire 1 #9 pwr_cr_gt_x86_pf $end +$var wire 1 $9 pwr_cr_eq_x86_zf $end +$var wire 1 %9 pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 &9 int_fp $end +$scope struct flags $end +$var wire 1 '9 pwr_ca_x86_cf $end +$var wire 1 (9 pwr_ca32_x86_af $end +$var wire 1 )9 pwr_ov_x86_of $end +$var wire 1 *9 pwr_ov32_x86_df $end +$var wire 1 +9 pwr_cr_lt_x86_sf $end +$var wire 1 ,9 pwr_cr_gt_x86_pf $end +$var wire 1 -9 pwr_cr_eq_x86_zf $end +$var wire 1 .9 pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 /9 int_fp $end +$scope struct flags $end +$var wire 1 09 pwr_ca_x86_cf $end +$var wire 1 19 pwr_ca32_x86_af $end +$var wire 1 29 pwr_ov_x86_of $end +$var wire 1 39 pwr_ov32_x86_df $end +$var wire 1 49 pwr_cr_lt_x86_sf $end +$var wire 1 59 pwr_cr_gt_x86_pf $end +$var wire 1 69 pwr_cr_eq_x86_zf $end +$var wire 1 79 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_11 $end +$var wire 4 89 value $end +$upscope $end +$scope struct dest_reg_12 $end +$var wire 4 99 value $end +$upscope $end +$scope struct in_flight_op_src_regs_5 $end +$var wire 6 :9 \[0] $end +$var wire 6 ;9 \[1] $end +$var wire 6 <9 \[2] $end +$upscope $end +$var wire 1 =9 cmp_eq_11 $end +$var wire 1 >9 cmp_eq_12 $end +$scope struct firing_data_7 $end +$var string 1 ?9 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 @9 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A9 prefix_pad $end +$scope struct dest $end +$var wire 4 B9 value $end +$upscope $end +$scope struct src $end +$var wire 6 C9 \[0] $end +$var wire 6 D9 \[1] $end +$var wire 6 E9 \[2] $end +$upscope $end +$var wire 25 F9 imm_low $end +$var wire 1 G9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 H9 output_integer_mode $end +$upscope $end +$var wire 1 I9 invert_src0 $end +$var wire 1 J9 src1_is_carry_in $end +$var wire 1 K9 invert_carry_in $end +$var wire 1 L9 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 M9 prefix_pad $end +$scope struct dest $end +$var wire 4 N9 value $end +$upscope $end +$scope struct src $end +$var wire 6 O9 \[0] $end +$var wire 6 P9 \[1] $end +$var wire 6 Q9 \[2] $end +$upscope $end +$var wire 25 R9 imm_low $end +$var wire 1 S9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 T9 output_integer_mode $end +$upscope $end +$var wire 1 U9 invert_src0 $end +$var wire 1 V9 src1_is_carry_in $end +$var wire 1 W9 invert_carry_in $end +$var wire 1 X9 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 }8 prefix_pad $end +$var string 0 Y9 prefix_pad $end $scope struct dest $end -$var wire 4 ~8 value $end +$var wire 4 Z9 value $end $upscope $end $scope struct src $end -$var wire 6 !9 \[0] $end -$var wire 6 "9 \[1] $end -$var wire 6 #9 \[2] $end +$var wire 6 [9 \[0] $end +$var wire 6 \9 \[1] $end +$var wire 6 ]9 \[2] $end $upscope $end -$var wire 25 $9 imm_low $end -$var wire 1 %9 imm_sign $end +$var wire 25 ^9 imm_low $end +$var wire 1 _9 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 &9 output_integer_mode $end +$var string 1 `9 output_integer_mode $end $upscope $end -$var wire 4 '9 lut $end +$var wire 4 a9 lut $end $upscope $end $upscope $end +$var wire 64 b9 pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 (9 int_fp $end +$var wire 64 c9 int_fp $end $scope struct flags $end -$var wire 1 )9 pwr_ca_x86_cf $end -$var wire 1 *9 pwr_ca32_x86_af $end -$var wire 1 +9 pwr_ov_x86_of $end -$var wire 1 ,9 pwr_ov32_x86_df $end -$var wire 1 -9 pwr_cr_lt_x86_sf $end -$var wire 1 .9 pwr_cr_gt_x86_pf $end -$var wire 1 /9 pwr_cr_eq_x86_zf $end -$var wire 1 09 pwr_so $end +$var wire 1 d9 pwr_ca_x86_cf $end +$var wire 1 e9 pwr_ca32_x86_af $end +$var wire 1 f9 pwr_ov_x86_of $end +$var wire 1 g9 pwr_ov32_x86_df $end +$var wire 1 h9 pwr_cr_lt_x86_sf $end +$var wire 1 i9 pwr_cr_gt_x86_pf $end +$var wire 1 j9 pwr_cr_eq_x86_zf $end +$var wire 1 k9 pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 19 int_fp $end +$var wire 64 l9 int_fp $end $scope struct flags $end -$var wire 1 29 pwr_ca_x86_cf $end -$var wire 1 39 pwr_ca32_x86_af $end -$var wire 1 49 pwr_ov_x86_of $end -$var wire 1 59 pwr_ov32_x86_df $end -$var wire 1 69 pwr_cr_lt_x86_sf $end -$var wire 1 79 pwr_cr_gt_x86_pf $end -$var wire 1 89 pwr_cr_eq_x86_zf $end -$var wire 1 99 pwr_so $end +$var wire 1 m9 pwr_ca_x86_cf $end +$var wire 1 n9 pwr_ca32_x86_af $end +$var wire 1 o9 pwr_ov_x86_of $end +$var wire 1 p9 pwr_ov32_x86_df $end +$var wire 1 q9 pwr_cr_lt_x86_sf $end +$var wire 1 r9 pwr_cr_gt_x86_pf $end +$var wire 1 s9 pwr_cr_eq_x86_zf $end +$var wire 1 t9 pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 :9 int_fp $end +$var wire 64 u9 int_fp $end $scope struct flags $end -$var wire 1 ;9 pwr_ca_x86_cf $end -$var wire 1 <9 pwr_ca32_x86_af $end -$var wire 1 =9 pwr_ov_x86_of $end -$var wire 1 >9 pwr_ov32_x86_df $end -$var wire 1 ?9 pwr_cr_lt_x86_sf $end -$var wire 1 @9 pwr_cr_gt_x86_pf $end -$var wire 1 A9 pwr_cr_eq_x86_zf $end -$var wire 1 B9 pwr_so $end +$var wire 1 v9 pwr_ca_x86_cf $end +$var wire 1 w9 pwr_ca32_x86_af $end +$var wire 1 x9 pwr_ov_x86_of $end +$var wire 1 y9 pwr_ov32_x86_df $end +$var wire 1 z9 pwr_cr_lt_x86_sf $end +$var wire 1 {9 pwr_cr_gt_x86_pf $end +$var wire 1 |9 pwr_cr_eq_x86_zf $end +$var wire 1 }9 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_13 $end +$var wire 4 ~9 value $end +$upscope $end +$scope struct dest_reg_14 $end +$var wire 4 !: value $end +$upscope $end +$scope struct in_flight_op_src_regs_6 $end +$var wire 6 ": \[0] $end +$var wire 6 #: \[1] $end +$var wire 6 $: \[2] $end +$upscope $end +$var wire 1 %: cmp_eq_13 $end +$var wire 1 &: cmp_eq_14 $end +$scope struct firing_data_8 $end +$var string 1 ': \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 (: \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ): prefix_pad $end +$scope struct dest $end +$var wire 4 *: value $end +$upscope $end +$scope struct src $end +$var wire 6 +: \[0] $end +$var wire 6 ,: \[1] $end +$var wire 6 -: \[2] $end +$upscope $end +$var wire 25 .: imm_low $end +$var wire 1 /: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 0: output_integer_mode $end +$upscope $end +$var wire 1 1: invert_src0 $end +$var wire 1 2: src1_is_carry_in $end +$var wire 1 3: invert_carry_in $end +$var wire 1 4: add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 5: prefix_pad $end +$scope struct dest $end +$var wire 4 6: value $end +$upscope $end +$scope struct src $end +$var wire 6 7: \[0] $end +$var wire 6 8: \[1] $end +$var wire 6 9: \[2] $end +$upscope $end +$var wire 25 :: imm_low $end +$var wire 1 ;: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 <: output_integer_mode $end +$upscope $end +$var wire 1 =: invert_src0 $end +$var wire 1 >: src1_is_carry_in $end +$var wire 1 ?: invert_carry_in $end +$var wire 1 @: add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A: prefix_pad $end +$scope struct dest $end +$var wire 4 B: value $end +$upscope $end +$scope struct src $end +$var wire 6 C: \[0] $end +$var wire 6 D: \[1] $end +$var wire 6 E: \[2] $end +$upscope $end +$var wire 25 F: imm_low $end +$var wire 1 G: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 H: output_integer_mode $end +$upscope $end +$var wire 4 I: lut $end +$upscope $end +$upscope $end +$var wire 64 J: pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 K: int_fp $end +$scope struct flags $end +$var wire 1 L: pwr_ca_x86_cf $end +$var wire 1 M: pwr_ca32_x86_af $end +$var wire 1 N: pwr_ov_x86_of $end +$var wire 1 O: pwr_ov32_x86_df $end +$var wire 1 P: pwr_cr_lt_x86_sf $end +$var wire 1 Q: pwr_cr_gt_x86_pf $end +$var wire 1 R: pwr_cr_eq_x86_zf $end +$var wire 1 S: pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 T: int_fp $end +$scope struct flags $end +$var wire 1 U: pwr_ca_x86_cf $end +$var wire 1 V: pwr_ca32_x86_af $end +$var wire 1 W: pwr_ov_x86_of $end +$var wire 1 X: pwr_ov32_x86_df $end +$var wire 1 Y: pwr_cr_lt_x86_sf $end +$var wire 1 Z: pwr_cr_gt_x86_pf $end +$var wire 1 [: pwr_cr_eq_x86_zf $end +$var wire 1 \: pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 ]: int_fp $end +$scope struct flags $end +$var wire 1 ^: pwr_ca_x86_cf $end +$var wire 1 _: pwr_ca32_x86_af $end +$var wire 1 `: pwr_ov_x86_of $end +$var wire 1 a: pwr_ov32_x86_df $end +$var wire 1 b: pwr_cr_lt_x86_sf $end +$var wire 1 c: pwr_cr_gt_x86_pf $end +$var wire 1 d: pwr_cr_eq_x86_zf $end +$var wire 1 e: pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_15 $end +$var wire 4 f: value $end +$upscope $end +$scope struct dest_reg_16 $end +$var wire 4 g: value $end +$upscope $end +$scope struct in_flight_op_src_regs_7 $end +$var wire 6 h: \[0] $end +$var wire 6 i: \[1] $end +$var wire 6 j: \[2] $end +$upscope $end +$var wire 1 k: cmp_eq_15 $end +$var wire 1 l: cmp_eq_16 $end +$scope struct firing_data_9 $end +$var string 1 m: \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 n: \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 o: prefix_pad $end +$scope struct dest $end +$var wire 4 p: value $end +$upscope $end +$scope struct src $end +$var wire 6 q: \[0] $end +$var wire 6 r: \[1] $end +$var wire 6 s: \[2] $end +$upscope $end +$var wire 25 t: imm_low $end +$var wire 1 u: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 v: output_integer_mode $end +$upscope $end +$var wire 1 w: invert_src0 $end +$var wire 1 x: src1_is_carry_in $end +$var wire 1 y: invert_carry_in $end +$var wire 1 z: add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 {: prefix_pad $end +$scope struct dest $end +$var wire 4 |: value $end +$upscope $end +$scope struct src $end +$var wire 6 }: \[0] $end +$var wire 6 ~: \[1] $end +$var wire 6 !; \[2] $end +$upscope $end +$var wire 25 "; imm_low $end +$var wire 1 #; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 $; output_integer_mode $end +$upscope $end +$var wire 1 %; invert_src0 $end +$var wire 1 &; src1_is_carry_in $end +$var wire 1 '; invert_carry_in $end +$var wire 1 (; add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ); prefix_pad $end +$scope struct dest $end +$var wire 4 *; value $end +$upscope $end +$scope struct src $end +$var wire 6 +; \[0] $end +$var wire 6 ,; \[1] $end +$var wire 6 -; \[2] $end +$upscope $end +$var wire 25 .; imm_low $end +$var wire 1 /; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 0; output_integer_mode $end +$upscope $end +$var wire 4 1; lut $end +$upscope $end +$upscope $end +$var wire 64 2; pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 3; int_fp $end +$scope struct flags $end +$var wire 1 4; pwr_ca_x86_cf $end +$var wire 1 5; pwr_ca32_x86_af $end +$var wire 1 6; pwr_ov_x86_of $end +$var wire 1 7; pwr_ov32_x86_df $end +$var wire 1 8; pwr_cr_lt_x86_sf $end +$var wire 1 9; pwr_cr_gt_x86_pf $end +$var wire 1 :; pwr_cr_eq_x86_zf $end +$var wire 1 ;; pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 <; int_fp $end +$scope struct flags $end +$var wire 1 =; pwr_ca_x86_cf $end +$var wire 1 >; pwr_ca32_x86_af $end +$var wire 1 ?; pwr_ov_x86_of $end +$var wire 1 @; pwr_ov32_x86_df $end +$var wire 1 A; pwr_cr_lt_x86_sf $end +$var wire 1 B; pwr_cr_gt_x86_pf $end +$var wire 1 C; pwr_cr_eq_x86_zf $end +$var wire 1 D; pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 E; int_fp $end +$scope struct flags $end +$var wire 1 F; pwr_ca_x86_cf $end +$var wire 1 G; pwr_ca32_x86_af $end +$var wire 1 H; pwr_ov_x86_of $end +$var wire 1 I; pwr_ov32_x86_df $end +$var wire 1 J; pwr_cr_lt_x86_sf $end +$var wire 1 K; pwr_cr_gt_x86_pf $end +$var wire 1 L; pwr_cr_eq_x86_zf $end +$var wire 1 M; pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_17 $end -$var wire 4 C9 value $end +$var wire 4 N; value $end $upscope $end $upscope $end -$upscope $end -$scope struct unit_0_free_regs_tracker $end -$scope struct cd $end -$var wire 1 R< clk $end -$var wire 1 S< rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 T< \$tag $end -$var wire 4 U< HdlSome $end -$upscope $end -$var wire 1 V< ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 W< \$tag $end -$var wire 4 X< HdlSome $end -$upscope $end -$var wire 1 Y< ready $end -$upscope $end -$upscope $end -$upscope $end -$scope module unit_free_regs_tracker $end -$scope struct cd $end -$var wire 1 g; clk $end -$var wire 1 h; rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 i; \$tag $end -$var wire 4 j; HdlSome $end -$upscope $end -$var wire 1 k; ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 l; \$tag $end -$var wire 4 m; HdlSome $end -$upscope $end -$var wire 1 n; ready $end -$upscope $end -$upscope $end -$scope struct allocated_reg $end -$var reg 1 o; \[0] $end -$var reg 1 p; \[1] $end -$var reg 1 q; \[2] $end -$var reg 1 r; \[3] $end -$var reg 1 s; \[4] $end -$var reg 1 t; \[5] $end -$var reg 1 u; \[6] $end -$var reg 1 v; \[7] $end -$var reg 1 w; \[8] $end -$var reg 1 x; \[9] $end -$var reg 1 y; \[10] $end -$var reg 1 z; \[11] $end -$var reg 1 {; \[12] $end -$var reg 1 |; \[13] $end -$var reg 1 }; \[14] $end -$var reg 1 ~; \[15] $end -$upscope $end $scope struct firing_data $end -$var string 1 !< \$tag $end -$var wire 4 "< HdlSome $end -$upscope $end -$var wire 1 #< reduced_count_0_2 $end -$var wire 1 $< reduced_count_overflowed_0_2 $end -$scope struct reduced_alloc_nums_0_2 $end -$var wire 1 %< \[0] $end -$upscope $end -$var wire 1 &< reduced_count_2_4 $end -$var wire 1 '< reduced_count_overflowed_2_4 $end -$scope struct reduced_alloc_nums_2_4 $end -$var wire 1 (< \[0] $end -$upscope $end -$var wire 1 )< reduced_count_0_4 $end -$var wire 1 *< reduced_count_overflowed_0_4 $end -$scope struct reduced_alloc_nums_0_4 $end -$var wire 2 +< \[0] $end -$upscope $end -$var wire 1 ,< reduced_count_4_6 $end -$var wire 1 -< reduced_count_overflowed_4_6 $end -$scope struct reduced_alloc_nums_4_6 $end -$var wire 1 .< \[0] $end -$upscope $end -$var wire 1 /< reduced_count_6_8 $end -$var wire 1 0< reduced_count_overflowed_6_8 $end -$scope struct reduced_alloc_nums_6_8 $end -$var wire 1 1< \[0] $end -$upscope $end -$var wire 1 2< reduced_count_4_8 $end -$var wire 1 3< reduced_count_overflowed_4_8 $end -$scope struct reduced_alloc_nums_4_8 $end -$var wire 2 4< \[0] $end -$upscope $end -$var wire 1 5< reduced_count_0_8 $end -$var wire 1 6< reduced_count_overflowed_0_8 $end -$scope struct reduced_alloc_nums_0_8 $end -$var wire 3 7< \[0] $end -$upscope $end -$var wire 1 8< reduced_count_8_10 $end -$var wire 1 9< reduced_count_overflowed_8_10 $end -$scope struct reduced_alloc_nums_8_10 $end -$var wire 1 :< \[0] $end -$upscope $end -$var wire 1 ;< reduced_count_10_12 $end -$var wire 1 << reduced_count_overflowed_10_12 $end -$scope struct reduced_alloc_nums_10_12 $end -$var wire 1 =< \[0] $end -$upscope $end -$var wire 1 >< reduced_count_8_12 $end -$var wire 1 ?< reduced_count_overflowed_8_12 $end -$scope struct reduced_alloc_nums_8_12 $end -$var wire 2 @< \[0] $end -$upscope $end -$var wire 1 A< reduced_count_12_14 $end -$var wire 1 B< reduced_count_overflowed_12_14 $end -$scope struct reduced_alloc_nums_12_14 $end -$var wire 1 C< \[0] $end -$upscope $end -$var wire 1 D< reduced_count_14_16 $end -$var wire 1 E< reduced_count_overflowed_14_16 $end -$scope struct reduced_alloc_nums_14_16 $end -$var wire 1 F< \[0] $end -$upscope $end -$var wire 1 G< reduced_count_12_16 $end -$var wire 1 H< reduced_count_overflowed_12_16 $end -$scope struct reduced_alloc_nums_12_16 $end -$var wire 2 I< \[0] $end -$upscope $end -$var wire 1 J< reduced_count_8_16 $end -$var wire 1 K< reduced_count_overflowed_8_16 $end -$scope struct reduced_alloc_nums_8_16 $end -$var wire 3 L< \[0] $end -$upscope $end -$var wire 1 M< reduced_count_0_16 $end -$var wire 1 N< reduced_count_overflowed_0_16 $end -$scope struct reduced_alloc_nums_0_16 $end -$var wire 4 O< \[0] $end -$upscope $end -$scope struct firing_data_2 $end -$var string 1 P< \$tag $end -$var wire 4 Q< HdlSome $end -$upscope $end -$upscope $end -$scope struct and_then_out $end -$var string 1 Z< \$tag $end +$var string 1 *= \$tag $end $scope struct HdlSome $end -$var string 1 [< \$tag $end +$scope struct mop $end +$var string 1 += \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 \< prefix_pad $end +$var string 0 ,= prefix_pad $end $scope struct dest $end -$var wire 4 ]< value $end +$var wire 4 -= value $end $upscope $end $scope struct src $end -$var wire 6 ^< \[0] $end -$var wire 6 _< \[1] $end -$var wire 6 `< \[2] $end +$var wire 6 .= \[0] $end +$var wire 6 /= \[1] $end +$var wire 6 0= \[2] $end $upscope $end -$var wire 25 a< imm_low $end -$var wire 1 b< imm_sign $end +$var wire 25 1= imm_low $end +$var wire 1 2= imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 c< output_integer_mode $end +$var string 1 3= output_integer_mode $end $upscope $end -$var wire 1 d< invert_src0 $end -$var wire 1 e< invert_carry_in $end -$var wire 1 f< invert_carry_out $end -$var wire 1 g< add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 h< prefix_pad $end -$scope struct dest $end -$var wire 4 i< value $end -$upscope $end -$scope struct src $end -$var wire 6 j< \[0] $end -$var wire 6 k< \[1] $end -$var wire 6 l< \[2] $end -$upscope $end -$var wire 25 m< imm_low $end -$var wire 1 n< imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 o< output_integer_mode $end -$upscope $end -$var wire 1 p< invert_src0 $end -$var wire 1 q< invert_carry_in $end -$var wire 1 r< invert_carry_out $end -$var wire 1 s< add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 t< prefix_pad $end -$scope struct dest $end -$var wire 4 u< value $end -$upscope $end -$scope struct src $end -$var wire 6 v< \[0] $end -$var wire 6 w< \[1] $end -$var wire 6 x< \[2] $end -$upscope $end -$var wire 25 y< imm_low $end -$var wire 1 z< imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 {< output_integer_mode $end -$upscope $end -$var wire 4 |< lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct alu_branch_mop $end -$var string 1 }< \$tag $end -$scope struct HdlSome $end -$var string 1 ~< \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 != prefix_pad $end -$scope struct dest $end -$var wire 4 "= value $end -$upscope $end -$scope struct src $end -$var wire 6 #= \[0] $end -$var wire 6 $= \[1] $end -$var wire 6 %= \[2] $end -$upscope $end -$var wire 25 &= imm_low $end -$var wire 1 '= imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 (= output_integer_mode $end -$upscope $end -$var wire 1 )= invert_src0 $end -$var wire 1 *= invert_carry_in $end -$var wire 1 += invert_carry_out $end -$var wire 1 ,= add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 -= prefix_pad $end -$scope struct dest $end -$var wire 4 .= value $end -$upscope $end -$scope struct src $end -$var wire 6 /= \[0] $end -$var wire 6 0= \[1] $end -$var wire 6 1= \[2] $end -$upscope $end -$var wire 25 2= imm_low $end -$var wire 1 3= imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 4= output_integer_mode $end -$upscope $end -$var wire 1 5= invert_src0 $end +$var wire 1 4= invert_src0 $end +$var wire 1 5= src1_is_carry_in $end $var wire 1 6= invert_carry_in $end -$var wire 1 7= invert_carry_out $end -$var wire 1 8= add_pc $end +$var wire 1 7= add_pc $end $upscope $end -$scope struct Logical $end +$scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 9= prefix_pad $end +$var string 0 8= prefix_pad $end $scope struct dest $end -$var wire 4 := value $end +$var wire 4 9= value $end $upscope $end $scope struct src $end -$var wire 6 ;= \[0] $end -$var wire 6 <= \[1] $end -$var wire 6 == \[2] $end +$var wire 6 := \[0] $end +$var wire 6 ;= \[1] $end +$var wire 6 <= \[2] $end $upscope $end -$var wire 25 >= imm_low $end -$var wire 1 ?= imm_sign $end +$var wire 25 == imm_low $end +$var wire 1 >= imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 @= output_integer_mode $end +$var string 1 ?= output_integer_mode $end $upscope $end -$var wire 4 A= lut $end +$var wire 1 @= invert_src0 $end +$var wire 1 A= src1_is_carry_in $end +$var wire 1 B= invert_carry_in $end +$var wire 1 C= add_pc $end $upscope $end -$upscope $end -$upscope $end -$scope struct and_then_out_2 $end -$var string 1 B= \$tag $end -$scope struct HdlSome $end -$var string 1 C= \$tag $end -$scope struct AddSub $end +$scope struct Logical $end $scope struct alu_common $end $scope struct common $end $var string 0 D= prefix_pad $end @@ -9028,179 +9604,791 @@ $upscope $end $upscope $end $var string 1 K= output_integer_mode $end $upscope $end -$var wire 1 L= invert_src0 $end -$var wire 1 M= invert_carry_in $end -$var wire 1 N= invert_carry_out $end -$var wire 1 O= add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 P= prefix_pad $end -$scope struct dest $end -$var wire 4 Q= value $end -$upscope $end -$scope struct src $end -$var wire 6 R= \[0] $end -$var wire 6 S= \[1] $end -$var wire 6 T= \[2] $end -$upscope $end -$var wire 25 U= imm_low $end -$var wire 1 V= imm_sign $end -$scope struct _phantom $end +$var wire 4 L= lut $end $upscope $end $upscope $end -$var string 1 W= output_integer_mode $end -$upscope $end -$var wire 1 X= invert_src0 $end -$var wire 1 Y= invert_carry_in $end -$var wire 1 Z= invert_carry_out $end -$var wire 1 [= add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 \= prefix_pad $end -$scope struct dest $end -$var wire 4 ]= value $end -$upscope $end -$scope struct src $end -$var wire 6 ^= \[0] $end -$var wire 6 _= \[1] $end -$var wire 6 `= \[2] $end -$upscope $end -$var wire 25 a= imm_low $end -$var wire 1 b= imm_sign $end -$scope struct _phantom $end +$var wire 64 M= pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 N= int_fp $end +$scope struct flags $end +$var wire 1 O= pwr_ca_x86_cf $end +$var wire 1 P= pwr_ca32_x86_af $end +$var wire 1 Q= pwr_ov_x86_of $end +$var wire 1 R= pwr_ov32_x86_df $end +$var wire 1 S= pwr_cr_lt_x86_sf $end +$var wire 1 T= pwr_cr_gt_x86_pf $end +$var wire 1 U= pwr_cr_eq_x86_zf $end +$var wire 1 V= pwr_so $end $upscope $end $upscope $end -$var string 1 c= output_integer_mode $end +$scope struct \[1] $end +$var wire 64 W= int_fp $end +$scope struct flags $end +$var wire 1 X= pwr_ca_x86_cf $end +$var wire 1 Y= pwr_ca32_x86_af $end +$var wire 1 Z= pwr_ov_x86_of $end +$var wire 1 [= pwr_ov32_x86_df $end +$var wire 1 \= pwr_cr_lt_x86_sf $end +$var wire 1 ]= pwr_cr_gt_x86_pf $end +$var wire 1 ^= pwr_cr_eq_x86_zf $end +$var wire 1 _= pwr_so $end $upscope $end -$var wire 4 d= lut $end +$upscope $end +$scope struct \[2] $end +$var wire 64 `= int_fp $end +$scope struct flags $end +$var wire 1 a= pwr_ca_x86_cf $end +$var wire 1 b= pwr_ca32_x86_af $end +$var wire 1 c= pwr_ov_x86_of $end +$var wire 1 d= pwr_ov32_x86_df $end +$var wire 1 e= pwr_cr_lt_x86_sf $end +$var wire 1 f= pwr_cr_gt_x86_pf $end +$var wire 1 g= pwr_cr_eq_x86_zf $end +$var wire 1 h= pwr_so $end $upscope $end $upscope $end $upscope $end -$scope struct alu_branch_mop_2 $end -$var string 1 e= \$tag $end +$upscope $end +$upscope $end +$var wire 1 i= carry_in_before_inversion $end +$var wire 64 j= src1 $end +$var wire 1 k= carry_in $end +$var wire 64 l= src0 $end +$var wire 64 m= pc_or_zero $end +$var wire 64 n= sum $end +$var wire 1 o= carry_at_4 $end +$var wire 1 p= carry_at_7 $end +$var wire 1 q= carry_at_8 $end +$var wire 1 r= carry_at_15 $end +$var wire 1 s= carry_at_16 $end +$var wire 1 t= carry_at_31 $end +$var wire 1 u= carry_at_32 $end +$var wire 1 v= carry_at_63 $end +$var wire 1 w= carry_at_64 $end +$var wire 64 x= int_fp $end +$var wire 1 y= x86_cf $end +$var wire 1 z= x86_af $end +$var wire 1 {= x86_of $end +$var wire 1 |= x86_sf $end +$var wire 1 }= x86_pf $end +$var wire 1 ~= x86_zf $end +$var wire 1 !> pwr_ca $end +$var wire 1 "> pwr_ca32 $end +$var wire 1 #> pwr_ov $end +$var wire 1 $> pwr_ov32 $end +$var wire 1 %> pwr_cr_lt $end +$var wire 1 &> pwr_cr_eq $end +$var wire 1 '> pwr_cr_gt $end +$var wire 1 (> pwr_so $end +$scope struct flags $end +$var wire 1 )> pwr_ca_x86_cf $end +$var wire 1 *> pwr_ca32_x86_af $end +$var wire 1 +> pwr_ov_x86_of $end +$var wire 1 ,> pwr_ov32_x86_df $end +$var wire 1 -> pwr_cr_lt_x86_sf $end +$var wire 1 .> pwr_cr_gt_x86_pf $end +$var wire 1 /> pwr_cr_eq_x86_zf $end +$var wire 1 0> pwr_so $end +$upscope $end +$var wire 1 1> carry_in_before_inversion_2 $end +$var wire 64 2> src1_2 $end +$var wire 1 3> carry_in_2 $end +$var wire 64 4> src0_2 $end +$var wire 64 5> pc_or_zero_2 $end +$var wire 64 6> sum_2 $end +$var wire 1 7> carry_at_4_2 $end +$var wire 1 8> carry_at_7_2 $end +$var wire 1 9> carry_at_8_2 $end +$var wire 1 :> carry_at_15_2 $end +$var wire 1 ;> carry_at_16_2 $end +$var wire 1 <> carry_at_31_2 $end +$var wire 1 => carry_at_32_2 $end +$var wire 1 >> carry_at_63_2 $end +$var wire 1 ?> carry_at_64_2 $end +$var wire 64 @> int_fp_2 $end +$var wire 1 A> x86_cf_2 $end +$var wire 1 B> x86_af_2 $end +$var wire 1 C> x86_of_2 $end +$var wire 1 D> x86_sf_2 $end +$var wire 1 E> x86_pf_2 $end +$var wire 1 F> x86_zf_2 $end +$var wire 1 G> pwr_ca_2 $end +$var wire 1 H> pwr_ca32_2 $end +$var wire 1 I> pwr_ov_2 $end +$var wire 1 J> pwr_ov32_2 $end +$var wire 1 K> pwr_cr_lt_2 $end +$var wire 1 L> pwr_cr_eq_2 $end +$var wire 1 M> pwr_cr_gt_2 $end +$var wire 1 N> pwr_so_2 $end +$scope struct flags_2 $end +$var wire 1 O> pwr_ca_x86_cf $end +$var wire 1 P> pwr_ca32_x86_af $end +$var wire 1 Q> pwr_ov_x86_of $end +$var wire 1 R> pwr_ov32_x86_df $end +$var wire 1 S> pwr_cr_lt_x86_sf $end +$var wire 1 T> pwr_cr_gt_x86_pf $end +$var wire 1 U> pwr_cr_eq_x86_zf $end +$var wire 1 V> pwr_so $end +$upscope $end +$upscope $end +$scope struct unit_0_free_regs_tracker $end +$scope struct cd $end +$var wire 1 0@ clk $end +$var wire 1 1@ rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 2@ \$tag $end +$var wire 4 3@ HdlSome $end +$upscope $end +$var wire 1 4@ ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 5@ \$tag $end +$var wire 4 6@ HdlSome $end +$upscope $end +$var wire 1 7@ ready $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_free_regs_tracker $end +$scope struct cd $end +$var wire 1 E? clk $end +$var wire 1 F? rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 G? \$tag $end +$var wire 4 H? HdlSome $end +$upscope $end +$var wire 1 I? ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 J? \$tag $end +$var wire 4 K? HdlSome $end +$upscope $end +$var wire 1 L? ready $end +$upscope $end +$upscope $end +$scope struct allocated_reg $end +$var reg 1 M? \[0] $end +$var reg 1 N? \[1] $end +$var reg 1 O? \[2] $end +$var reg 1 P? \[3] $end +$var reg 1 Q? \[4] $end +$var reg 1 R? \[5] $end +$var reg 1 S? \[6] $end +$var reg 1 T? \[7] $end +$var reg 1 U? \[8] $end +$var reg 1 V? \[9] $end +$var reg 1 W? \[10] $end +$var reg 1 X? \[11] $end +$var reg 1 Y? \[12] $end +$var reg 1 Z? \[13] $end +$var reg 1 [? \[14] $end +$var reg 1 \? \[15] $end +$upscope $end +$scope struct firing_data $end +$var string 1 ]? \$tag $end +$var wire 4 ^? HdlSome $end +$upscope $end +$var wire 1 _? reduced_count_0_2 $end +$var wire 1 `? reduced_count_overflowed_0_2 $end +$scope struct reduced_alloc_nums_0_2 $end +$var wire 1 a? \[0] $end +$upscope $end +$var wire 1 b? reduced_count_2_4 $end +$var wire 1 c? reduced_count_overflowed_2_4 $end +$scope struct reduced_alloc_nums_2_4 $end +$var wire 1 d? \[0] $end +$upscope $end +$var wire 1 e? reduced_count_0_4 $end +$var wire 1 f? reduced_count_overflowed_0_4 $end +$scope struct reduced_alloc_nums_0_4 $end +$var wire 2 g? \[0] $end +$upscope $end +$var wire 1 h? reduced_count_4_6 $end +$var wire 1 i? reduced_count_overflowed_4_6 $end +$scope struct reduced_alloc_nums_4_6 $end +$var wire 1 j? \[0] $end +$upscope $end +$var wire 1 k? reduced_count_6_8 $end +$var wire 1 l? reduced_count_overflowed_6_8 $end +$scope struct reduced_alloc_nums_6_8 $end +$var wire 1 m? \[0] $end +$upscope $end +$var wire 1 n? reduced_count_4_8 $end +$var wire 1 o? reduced_count_overflowed_4_8 $end +$scope struct reduced_alloc_nums_4_8 $end +$var wire 2 p? \[0] $end +$upscope $end +$var wire 1 q? reduced_count_0_8 $end +$var wire 1 r? reduced_count_overflowed_0_8 $end +$scope struct reduced_alloc_nums_0_8 $end +$var wire 3 s? \[0] $end +$upscope $end +$var wire 1 t? reduced_count_8_10 $end +$var wire 1 u? reduced_count_overflowed_8_10 $end +$scope struct reduced_alloc_nums_8_10 $end +$var wire 1 v? \[0] $end +$upscope $end +$var wire 1 w? reduced_count_10_12 $end +$var wire 1 x? reduced_count_overflowed_10_12 $end +$scope struct reduced_alloc_nums_10_12 $end +$var wire 1 y? \[0] $end +$upscope $end +$var wire 1 z? reduced_count_8_12 $end +$var wire 1 {? reduced_count_overflowed_8_12 $end +$scope struct reduced_alloc_nums_8_12 $end +$var wire 2 |? \[0] $end +$upscope $end +$var wire 1 }? reduced_count_12_14 $end +$var wire 1 ~? reduced_count_overflowed_12_14 $end +$scope struct reduced_alloc_nums_12_14 $end +$var wire 1 !@ \[0] $end +$upscope $end +$var wire 1 "@ reduced_count_14_16 $end +$var wire 1 #@ reduced_count_overflowed_14_16 $end +$scope struct reduced_alloc_nums_14_16 $end +$var wire 1 $@ \[0] $end +$upscope $end +$var wire 1 %@ reduced_count_12_16 $end +$var wire 1 &@ reduced_count_overflowed_12_16 $end +$scope struct reduced_alloc_nums_12_16 $end +$var wire 2 '@ \[0] $end +$upscope $end +$var wire 1 (@ reduced_count_8_16 $end +$var wire 1 )@ reduced_count_overflowed_8_16 $end +$scope struct reduced_alloc_nums_8_16 $end +$var wire 3 *@ \[0] $end +$upscope $end +$var wire 1 +@ reduced_count_0_16 $end +$var wire 1 ,@ reduced_count_overflowed_0_16 $end +$scope struct reduced_alloc_nums_0_16 $end +$var wire 4 -@ \[0] $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 .@ \$tag $end +$var wire 4 /@ HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out $end +$var string 1 8@ \$tag $end $scope struct HdlSome $end -$var string 1 f= \$tag $end +$scope struct mop $end +$var string 1 9@ \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 g= prefix_pad $end +$var string 0 :@ prefix_pad $end $scope struct dest $end -$var wire 4 h= value $end +$var wire 4 ;@ value $end $upscope $end $scope struct src $end -$var wire 6 i= \[0] $end -$var wire 6 j= \[1] $end -$var wire 6 k= \[2] $end +$var wire 6 <@ \[0] $end +$var wire 6 =@ \[1] $end +$var wire 6 >@ \[2] $end $upscope $end -$var wire 25 l= imm_low $end -$var wire 1 m= imm_sign $end +$var wire 25 ?@ imm_low $end +$var wire 1 @@ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 n= output_integer_mode $end +$var string 1 A@ output_integer_mode $end $upscope $end -$var wire 1 o= invert_src0 $end -$var wire 1 p= invert_carry_in $end -$var wire 1 q= invert_carry_out $end -$var wire 1 r= add_pc $end +$var wire 1 B@ invert_src0 $end +$var wire 1 C@ src1_is_carry_in $end +$var wire 1 D@ invert_carry_in $end +$var wire 1 E@ add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 s= prefix_pad $end +$var string 0 F@ prefix_pad $end $scope struct dest $end -$var wire 4 t= value $end +$var wire 4 G@ value $end $upscope $end $scope struct src $end -$var wire 6 u= \[0] $end -$var wire 6 v= \[1] $end -$var wire 6 w= \[2] $end +$var wire 6 H@ \[0] $end +$var wire 6 I@ \[1] $end +$var wire 6 J@ \[2] $end $upscope $end -$var wire 25 x= imm_low $end -$var wire 1 y= imm_sign $end +$var wire 25 K@ imm_low $end +$var wire 1 L@ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 z= output_integer_mode $end +$var string 1 M@ output_integer_mode $end $upscope $end -$var wire 1 {= invert_src0 $end -$var wire 1 |= invert_carry_in $end -$var wire 1 }= invert_carry_out $end -$var wire 1 ~= add_pc $end +$var wire 1 N@ invert_src0 $end +$var wire 1 O@ src1_is_carry_in $end +$var wire 1 P@ invert_carry_in $end +$var wire 1 Q@ add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 !> prefix_pad $end +$var string 0 R@ prefix_pad $end $scope struct dest $end -$var wire 4 "> value $end +$var wire 4 S@ value $end $upscope $end $scope struct src $end -$var wire 6 #> \[0] $end -$var wire 6 $> \[1] $end -$var wire 6 %> \[2] $end +$var wire 6 T@ \[0] $end +$var wire 6 U@ \[1] $end +$var wire 6 V@ \[2] $end $upscope $end -$var wire 25 &> imm_low $end -$var wire 1 '> imm_sign $end +$var wire 25 W@ imm_low $end +$var wire 1 X@ imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 (> output_integer_mode $end +$var string 1 Y@ output_integer_mode $end $upscope $end -$var wire 4 )> lut $end +$var wire 4 Z@ lut $end +$upscope $end +$upscope $end +$var wire 64 [@ pc $end +$upscope $end +$upscope $end +$scope struct and_then_out_2 $end +$var string 1 \@ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 ]@ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ^@ prefix_pad $end +$scope struct dest $end +$var wire 4 _@ value $end +$upscope $end +$scope struct src $end +$var wire 6 `@ \[0] $end +$var wire 6 a@ \[1] $end +$var wire 6 b@ \[2] $end +$upscope $end +$var wire 25 c@ imm_low $end +$var wire 1 d@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 e@ output_integer_mode $end +$upscope $end +$var wire 1 f@ invert_src0 $end +$var wire 1 g@ src1_is_carry_in $end +$var wire 1 h@ invert_carry_in $end +$var wire 1 i@ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 j@ prefix_pad $end +$scope struct dest $end +$var wire 4 k@ value $end +$upscope $end +$scope struct src $end +$var wire 6 l@ \[0] $end +$var wire 6 m@ \[1] $end +$var wire 6 n@ \[2] $end +$upscope $end +$var wire 25 o@ imm_low $end +$var wire 1 p@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 q@ output_integer_mode $end +$upscope $end +$var wire 1 r@ invert_src0 $end +$var wire 1 s@ src1_is_carry_in $end +$var wire 1 t@ invert_carry_in $end +$var wire 1 u@ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 v@ prefix_pad $end +$scope struct dest $end +$var wire 4 w@ value $end +$upscope $end +$scope struct src $end +$var wire 6 x@ \[0] $end +$var wire 6 y@ \[1] $end +$var wire 6 z@ \[2] $end +$upscope $end +$var wire 25 {@ imm_low $end +$var wire 1 |@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 }@ output_integer_mode $end +$upscope $end +$var wire 4 ~@ lut $end +$upscope $end +$upscope $end +$var wire 64 !A pc $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop $end +$var string 1 "A \$tag $end +$scope struct HdlSome $end +$var string 1 #A \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 $A prefix_pad $end +$scope struct dest $end +$var wire 4 %A value $end +$upscope $end +$scope struct src $end +$var wire 6 &A \[0] $end +$var wire 6 'A \[1] $end +$var wire 6 (A \[2] $end +$upscope $end +$var wire 25 )A imm_low $end +$var wire 1 *A imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 +A output_integer_mode $end +$upscope $end +$var wire 1 ,A invert_src0 $end +$var wire 1 -A src1_is_carry_in $end +$var wire 1 .A invert_carry_in $end +$var wire 1 /A add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 0A prefix_pad $end +$scope struct dest $end +$var wire 4 1A value $end +$upscope $end +$scope struct src $end +$var wire 6 2A \[0] $end +$var wire 6 3A \[1] $end +$var wire 6 4A \[2] $end +$upscope $end +$var wire 25 5A imm_low $end +$var wire 1 6A imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 7A output_integer_mode $end +$upscope $end +$var wire 1 8A invert_src0 $end +$var wire 1 9A src1_is_carry_in $end +$var wire 1 :A invert_carry_in $end +$var wire 1 ;A add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A \[0] $end +$var wire 6 ?A \[1] $end +$var wire 6 @A \[2] $end +$upscope $end +$var wire 25 AA imm_low $end +$var wire 1 BA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 CA output_integer_mode $end +$upscope $end +$var wire 4 DA lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct and_then_out_3 $end +$var string 1 EA \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 FA \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 GA prefix_pad $end +$scope struct dest $end +$var wire 4 HA value $end +$upscope $end +$scope struct src $end +$var wire 6 IA \[0] $end +$var wire 6 JA \[1] $end +$var wire 6 KA \[2] $end +$upscope $end +$var wire 25 LA imm_low $end +$var wire 1 MA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 NA output_integer_mode $end +$upscope $end +$var wire 1 OA invert_src0 $end +$var wire 1 PA src1_is_carry_in $end +$var wire 1 QA invert_carry_in $end +$var wire 1 RA add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 SA prefix_pad $end +$scope struct dest $end +$var wire 4 TA value $end +$upscope $end +$scope struct src $end +$var wire 6 UA \[0] $end +$var wire 6 VA \[1] $end +$var wire 6 WA \[2] $end +$upscope $end +$var wire 25 XA imm_low $end +$var wire 1 YA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ZA output_integer_mode $end +$upscope $end +$var wire 1 [A invert_src0 $end +$var wire 1 \A src1_is_carry_in $end +$var wire 1 ]A invert_carry_in $end +$var wire 1 ^A add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 _A prefix_pad $end +$scope struct dest $end +$var wire 4 `A value $end +$upscope $end +$scope struct src $end +$var wire 6 aA \[0] $end +$var wire 6 bA \[1] $end +$var wire 6 cA \[2] $end +$upscope $end +$var wire 25 dA imm_low $end +$var wire 1 eA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 fA output_integer_mode $end +$upscope $end +$var wire 4 gA lut $end +$upscope $end +$upscope $end +$var wire 64 hA pc $end +$upscope $end +$upscope $end +$scope struct and_then_out_4 $end +$var string 1 iA \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 jA \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 kA prefix_pad $end +$scope struct dest $end +$var wire 4 lA value $end +$upscope $end +$scope struct src $end +$var wire 6 mA \[0] $end +$var wire 6 nA \[1] $end +$var wire 6 oA \[2] $end +$upscope $end +$var wire 25 pA imm_low $end +$var wire 1 qA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 rA output_integer_mode $end +$upscope $end +$var wire 1 sA invert_src0 $end +$var wire 1 tA src1_is_carry_in $end +$var wire 1 uA invert_carry_in $end +$var wire 1 vA add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 wA prefix_pad $end +$scope struct dest $end +$var wire 4 xA value $end +$upscope $end +$scope struct src $end +$var wire 6 yA \[0] $end +$var wire 6 zA \[1] $end +$var wire 6 {A \[2] $end +$upscope $end +$var wire 25 |A imm_low $end +$var wire 1 }A imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ~A output_integer_mode $end +$upscope $end +$var wire 1 !B invert_src0 $end +$var wire 1 "B src1_is_carry_in $end +$var wire 1 #B invert_carry_in $end +$var wire 1 $B add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 %B prefix_pad $end +$scope struct dest $end +$var wire 4 &B value $end +$upscope $end +$scope struct src $end +$var wire 6 'B \[0] $end +$var wire 6 (B \[1] $end +$var wire 6 )B \[2] $end +$upscope $end +$var wire 25 *B imm_low $end +$var wire 1 +B imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ,B output_integer_mode $end +$upscope $end +$var wire 4 -B lut $end +$upscope $end +$upscope $end +$var wire 64 .B pc $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_2 $end +$var string 1 /B \$tag $end +$scope struct HdlSome $end +$var string 1 0B \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 1B prefix_pad $end +$scope struct dest $end +$var wire 4 2B value $end +$upscope $end +$scope struct src $end +$var wire 6 3B \[0] $end +$var wire 6 4B \[1] $end +$var wire 6 5B \[2] $end +$upscope $end +$var wire 25 6B imm_low $end +$var wire 1 7B imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 8B output_integer_mode $end +$upscope $end +$var wire 1 9B invert_src0 $end +$var wire 1 :B src1_is_carry_in $end +$var wire 1 ;B invert_carry_in $end +$var wire 1 B value $end +$upscope $end +$scope struct src $end +$var wire 6 ?B \[0] $end +$var wire 6 @B \[1] $end +$var wire 6 AB \[2] $end +$upscope $end +$var wire 25 BB imm_low $end +$var wire 1 CB imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 DB output_integer_mode $end +$upscope $end +$var wire 1 EB invert_src0 $end +$var wire 1 FB src1_is_carry_in $end +$var wire 1 GB invert_carry_in $end +$var wire 1 HB add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 IB prefix_pad $end +$scope struct dest $end +$var wire 4 JB value $end +$upscope $end +$scope struct src $end +$var wire 6 KB \[0] $end +$var wire 6 LB \[1] $end +$var wire 6 MB \[2] $end +$upscope $end +$var wire 25 NB imm_low $end +$var wire 1 OB imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 PB output_integer_mode $end +$upscope $end +$var wire 4 QB lut $end $upscope $end $upscope $end $upscope $end $scope struct unit_1 $end $scope struct cd $end -$var wire 1 GM clk $end -$var wire 1 HM rst $end +$var wire 1 2U clk $end +$var wire 1 3U rst $end $upscope $end $scope struct unit_to_reg_alloc $end $scope struct unit_forwarding_info $end $scope struct unit_output_writes $end $scope struct \[0] $end -$var string 1 IM \$tag $end +$var string 1 4U \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 JM value $end +$var wire 4 5U value $end $upscope $end $scope struct value $end -$var wire 64 KM int_fp $end +$var wire 64 6U int_fp $end $scope struct flags $end -$var wire 1 LM pwr_ca_x86_cf $end -$var wire 1 MM pwr_ca32_x86_af $end -$var wire 1 NM pwr_ov_x86_of $end -$var wire 1 OM pwr_ov32_x86_df $end -$var wire 1 PM pwr_cr_lt_x86_sf $end -$var wire 1 QM pwr_cr_gt_x86_pf $end -$var wire 1 RM pwr_cr_eq_x86_zf $end -$var wire 1 SM pwr_so $end +$var wire 1 7U pwr_ca_x86_cf $end +$var wire 1 8U pwr_ca32_x86_af $end +$var wire 1 9U pwr_ov_x86_of $end +$var wire 1 :U pwr_ov32_x86_df $end +$var wire 1 ;U pwr_cr_lt_x86_sf $end +$var wire 1 U pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 TM \$tag $end +$var string 1 ?U \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 UM value $end +$var wire 4 @U value $end $upscope $end $scope struct value $end -$var wire 64 VM int_fp $end +$var wire 64 AU int_fp $end $scope struct flags $end -$var wire 1 WM pwr_ca_x86_cf $end -$var wire 1 XM pwr_ca32_x86_af $end -$var wire 1 YM pwr_ov_x86_of $end -$var wire 1 ZM pwr_ov32_x86_df $end -$var wire 1 [M pwr_cr_lt_x86_sf $end -$var wire 1 \M pwr_cr_gt_x86_pf $end -$var wire 1 ]M pwr_cr_eq_x86_zf $end -$var wire 1 ^M pwr_so $end +$var wire 1 BU pwr_ca_x86_cf $end +$var wire 1 CU pwr_ca32_x86_af $end +$var wire 1 DU pwr_ov_x86_of $end +$var wire 1 EU pwr_ov32_x86_df $end +$var wire 1 FU pwr_cr_lt_x86_sf $end +$var wire 1 GU pwr_cr_gt_x86_pf $end +$var wire 1 HU pwr_cr_eq_x86_zf $end +$var wire 1 IU pwr_so $end $upscope $end $upscope $end $upscope $end @@ -9209,112 +10397,115 @@ $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end +$scope struct input $end $scope struct data $end -$var string 1 _M \$tag $end +$var string 1 JU \$tag $end $scope struct HdlSome $end -$var string 1 `M \$tag $end +$scope struct mop $end +$var string 1 KU \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 aM prefix_pad $end +$var string 0 LU prefix_pad $end $scope struct dest $end -$var wire 4 bM value $end +$var wire 4 MU value $end $upscope $end $scope struct src $end -$var wire 6 cM \[0] $end -$var wire 6 dM \[1] $end -$var wire 6 eM \[2] $end +$var wire 6 NU \[0] $end +$var wire 6 OU \[1] $end +$var wire 6 PU \[2] $end $upscope $end -$var wire 25 fM imm_low $end -$var wire 1 gM imm_sign $end +$var wire 25 QU imm_low $end +$var wire 1 RU imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 hM output_integer_mode $end +$var string 1 SU output_integer_mode $end $upscope $end -$var wire 1 iM invert_src0 $end -$var wire 1 jM invert_carry_in $end -$var wire 1 kM invert_carry_out $end -$var wire 1 lM add_pc $end +$var wire 1 TU invert_src0 $end +$var wire 1 UU src1_is_carry_in $end +$var wire 1 VU invert_carry_in $end +$var wire 1 WU add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 mM prefix_pad $end +$var string 0 XU prefix_pad $end $scope struct dest $end -$var wire 4 nM value $end +$var wire 4 YU value $end $upscope $end $scope struct src $end -$var wire 6 oM \[0] $end -$var wire 6 pM \[1] $end -$var wire 6 qM \[2] $end +$var wire 6 ZU \[0] $end +$var wire 6 [U \[1] $end +$var wire 6 \U \[2] $end $upscope $end -$var wire 25 rM imm_low $end -$var wire 1 sM imm_sign $end +$var wire 25 ]U imm_low $end +$var wire 1 ^U imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 tM output_integer_mode $end +$var string 1 _U output_integer_mode $end $upscope $end -$var wire 1 uM invert_src0 $end -$var wire 1 vM invert_carry_in $end -$var wire 1 wM invert_carry_out $end -$var wire 1 xM add_pc $end +$var wire 1 `U invert_src0 $end +$var wire 1 aU src1_is_carry_in $end +$var wire 1 bU invert_carry_in $end +$var wire 1 cU add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 yM prefix_pad $end +$var string 0 dU prefix_pad $end $scope struct dest $end -$var wire 4 zM value $end +$var wire 4 eU value $end $upscope $end $scope struct src $end -$var wire 6 {M \[0] $end -$var wire 6 |M \[1] $end -$var wire 6 }M \[2] $end +$var wire 6 fU \[0] $end +$var wire 6 gU \[1] $end +$var wire 6 hU \[2] $end $upscope $end -$var wire 25 ~M imm_low $end -$var wire 1 !N imm_sign $end +$var wire 25 iU imm_low $end +$var wire 1 jU imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 "N output_integer_mode $end +$var string 1 kU output_integer_mode $end $upscope $end -$var wire 4 #N lut $end +$var wire 4 lU lut $end $upscope $end $upscope $end +$var wire 64 mU pc $end $upscope $end -$var wire 1 $N ready $end +$upscope $end +$var wire 1 nU ready $end $upscope $end $scope struct cancel_input $end -$var string 1 %N \$tag $end +$var string 1 oU \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 &N value $end +$var wire 4 pU value $end $upscope $end $upscope $end $upscope $end $scope struct output $end -$var string 1 'N \$tag $end +$var string 1 qU \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 (N value $end +$var wire 4 rU value $end $upscope $end $scope struct result $end -$var string 1 )N \$tag $end +$var string 1 sU \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 *N int_fp $end +$var wire 64 tU int_fp $end $scope struct flags $end -$var wire 1 +N pwr_ca_x86_cf $end -$var wire 1 ,N pwr_ca32_x86_af $end -$var wire 1 -N pwr_ov_x86_of $end -$var wire 1 .N pwr_ov32_x86_df $end -$var wire 1 /N pwr_cr_lt_x86_sf $end -$var wire 1 0N pwr_cr_gt_x86_pf $end -$var wire 1 1N pwr_cr_eq_x86_zf $end -$var wire 1 2N pwr_so $end +$var wire 1 uU pwr_ca_x86_cf $end +$var wire 1 vU pwr_ca32_x86_af $end +$var wire 1 wU pwr_ov_x86_of $end +$var wire 1 xU pwr_ov32_x86_df $end +$var wire 1 yU pwr_cr_lt_x86_sf $end +$var wire 1 zU pwr_cr_gt_x86_pf $end +$var wire 1 {U pwr_cr_eq_x86_zf $end +$var wire 1 |U pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -9326,53 +10517,62 @@ $upscope $end $upscope $end $upscope $end $upscope $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 }U \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end $upscope $end $scope module alu_branch_2 $end $scope struct cd $end -$var wire 1 *> clk $end -$var wire 1 +> rst $end +$var wire 1 RB clk $end +$var wire 1 SB rst $end $upscope $end $scope struct unit_to_reg_alloc $end $scope struct unit_forwarding_info $end $scope struct unit_output_writes $end $scope struct \[0] $end -$var string 1 ,> \$tag $end +$var string 1 TB \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 -> value $end +$var wire 4 UB value $end $upscope $end $scope struct value $end -$var wire 64 .> int_fp $end +$var wire 64 VB int_fp $end $scope struct flags $end -$var wire 1 /> pwr_ca_x86_cf $end -$var wire 1 0> pwr_ca32_x86_af $end -$var wire 1 1> pwr_ov_x86_of $end -$var wire 1 2> pwr_ov32_x86_df $end -$var wire 1 3> pwr_cr_lt_x86_sf $end -$var wire 1 4> pwr_cr_gt_x86_pf $end -$var wire 1 5> pwr_cr_eq_x86_zf $end -$var wire 1 6> pwr_so $end +$var wire 1 WB pwr_ca_x86_cf $end +$var wire 1 XB pwr_ca32_x86_af $end +$var wire 1 YB pwr_ov_x86_of $end +$var wire 1 ZB pwr_ov32_x86_df $end +$var wire 1 [B pwr_cr_lt_x86_sf $end +$var wire 1 \B pwr_cr_gt_x86_pf $end +$var wire 1 ]B pwr_cr_eq_x86_zf $end +$var wire 1 ^B pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 7> \$tag $end +$var string 1 _B \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 8> value $end +$var wire 4 `B value $end $upscope $end $scope struct value $end -$var wire 64 9> int_fp $end +$var wire 64 aB int_fp $end $scope struct flags $end -$var wire 1 :> pwr_ca_x86_cf $end -$var wire 1 ;> pwr_ca32_x86_af $end -$var wire 1 <> pwr_ov_x86_of $end -$var wire 1 => pwr_ov32_x86_df $end -$var wire 1 >> pwr_cr_lt_x86_sf $end -$var wire 1 ?> pwr_cr_gt_x86_pf $end -$var wire 1 @> pwr_cr_eq_x86_zf $end -$var wire 1 A> pwr_so $end +$var wire 1 bB pwr_ca_x86_cf $end +$var wire 1 cB pwr_ca32_x86_af $end +$var wire 1 dB pwr_ov_x86_of $end +$var wire 1 eB pwr_ov32_x86_df $end +$var wire 1 fB pwr_cr_lt_x86_sf $end +$var wire 1 gB pwr_cr_gt_x86_pf $end +$var wire 1 hB pwr_cr_eq_x86_zf $end +$var wire 1 iB pwr_so $end $upscope $end $upscope $end $upscope $end @@ -9381,112 +10581,115 @@ $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end +$scope struct input $end $scope struct data $end -$var string 1 B> \$tag $end +$var string 1 jB \$tag $end $scope struct HdlSome $end -$var string 1 C> \$tag $end +$scope struct mop $end +$var string 1 kB \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 D> prefix_pad $end +$var string 0 lB prefix_pad $end $scope struct dest $end -$var wire 4 E> value $end +$var wire 4 mB value $end $upscope $end $scope struct src $end -$var wire 6 F> \[0] $end -$var wire 6 G> \[1] $end -$var wire 6 H> \[2] $end +$var wire 6 nB \[0] $end +$var wire 6 oB \[1] $end +$var wire 6 pB \[2] $end $upscope $end -$var wire 25 I> imm_low $end -$var wire 1 J> imm_sign $end +$var wire 25 qB imm_low $end +$var wire 1 rB imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 K> output_integer_mode $end +$var string 1 sB output_integer_mode $end $upscope $end -$var wire 1 L> invert_src0 $end -$var wire 1 M> invert_carry_in $end -$var wire 1 N> invert_carry_out $end -$var wire 1 O> add_pc $end +$var wire 1 tB invert_src0 $end +$var wire 1 uB src1_is_carry_in $end +$var wire 1 vB invert_carry_in $end +$var wire 1 wB add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 P> prefix_pad $end +$var string 0 xB prefix_pad $end $scope struct dest $end -$var wire 4 Q> value $end +$var wire 4 yB value $end $upscope $end $scope struct src $end -$var wire 6 R> \[0] $end -$var wire 6 S> \[1] $end -$var wire 6 T> \[2] $end +$var wire 6 zB \[0] $end +$var wire 6 {B \[1] $end +$var wire 6 |B \[2] $end $upscope $end -$var wire 25 U> imm_low $end -$var wire 1 V> imm_sign $end +$var wire 25 }B imm_low $end +$var wire 1 ~B imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 W> output_integer_mode $end +$var string 1 !C output_integer_mode $end $upscope $end -$var wire 1 X> invert_src0 $end -$var wire 1 Y> invert_carry_in $end -$var wire 1 Z> invert_carry_out $end -$var wire 1 [> add_pc $end +$var wire 1 "C invert_src0 $end +$var wire 1 #C src1_is_carry_in $end +$var wire 1 $C invert_carry_in $end +$var wire 1 %C add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 \> prefix_pad $end +$var string 0 &C prefix_pad $end $scope struct dest $end -$var wire 4 ]> value $end +$var wire 4 'C value $end $upscope $end $scope struct src $end -$var wire 6 ^> \[0] $end -$var wire 6 _> \[1] $end -$var wire 6 `> \[2] $end +$var wire 6 (C \[0] $end +$var wire 6 )C \[1] $end +$var wire 6 *C \[2] $end $upscope $end -$var wire 25 a> imm_low $end -$var wire 1 b> imm_sign $end +$var wire 25 +C imm_low $end +$var wire 1 ,C imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 c> output_integer_mode $end +$var string 1 -C output_integer_mode $end $upscope $end -$var wire 4 d> lut $end +$var wire 4 .C lut $end $upscope $end $upscope $end +$var wire 64 /C pc $end $upscope $end -$var wire 1 e> ready $end +$upscope $end +$var wire 1 0C ready $end $upscope $end $scope struct cancel_input $end -$var string 1 f> \$tag $end +$var string 1 1C \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 g> value $end +$var wire 4 2C value $end $upscope $end $upscope $end $upscope $end $scope struct output $end -$var string 1 h> \$tag $end +$var string 1 3C \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 i> value $end +$var wire 4 4C value $end $upscope $end $scope struct result $end -$var string 1 j> \$tag $end +$var string 1 5C \$tag $end $scope struct Completed $end $scope struct value $end -$var wire 64 k> int_fp $end +$var wire 64 6C int_fp $end $scope struct flags $end -$var wire 1 l> pwr_ca_x86_cf $end -$var wire 1 m> pwr_ca32_x86_af $end -$var wire 1 n> pwr_ov_x86_of $end -$var wire 1 o> pwr_ov32_x86_df $end -$var wire 1 p> pwr_cr_lt_x86_sf $end -$var wire 1 q> pwr_cr_gt_x86_pf $end -$var wire 1 r> pwr_cr_eq_x86_zf $end -$var wire 1 s> pwr_so $end +$var wire 1 7C pwr_ca_x86_cf $end +$var wire 1 8C pwr_ca32_x86_af $end +$var wire 1 9C pwr_ov_x86_of $end +$var wire 1 :C pwr_ov32_x86_df $end +$var wire 1 ;C pwr_cr_lt_x86_sf $end +$var wire 1 C pwr_so $end $upscope $end $upscope $end $scope struct extra_out $end @@ -9498,52 +10701,61 @@ $upscope $end $upscope $end $upscope $end $upscope $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 ?C \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end $scope struct unit_base $end $scope struct cd $end -$var wire 1 nK clk $end -$var wire 1 oK rst $end +$var wire 1 *R clk $end +$var wire 1 +R rst $end $upscope $end $scope struct unit_to_reg_alloc $end $scope struct unit_forwarding_info $end $scope struct unit_output_writes $end $scope struct \[0] $end -$var string 1 pK \$tag $end +$var string 1 ,R \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 qK value $end +$var wire 4 -R value $end $upscope $end $scope struct value $end -$var wire 64 rK int_fp $end +$var wire 64 .R int_fp $end $scope struct flags $end -$var wire 1 sK pwr_ca_x86_cf $end -$var wire 1 tK pwr_ca32_x86_af $end -$var wire 1 uK pwr_ov_x86_of $end -$var wire 1 vK pwr_ov32_x86_df $end -$var wire 1 wK pwr_cr_lt_x86_sf $end -$var wire 1 xK pwr_cr_gt_x86_pf $end -$var wire 1 yK pwr_cr_eq_x86_zf $end -$var wire 1 zK pwr_so $end +$var wire 1 /R pwr_ca_x86_cf $end +$var wire 1 0R pwr_ca32_x86_af $end +$var wire 1 1R pwr_ov_x86_of $end +$var wire 1 2R pwr_ov32_x86_df $end +$var wire 1 3R pwr_cr_lt_x86_sf $end +$var wire 1 4R pwr_cr_gt_x86_pf $end +$var wire 1 5R pwr_cr_eq_x86_zf $end +$var wire 1 6R pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end -$var string 1 {K \$tag $end +$var string 1 7R \$tag $end $scope struct HdlSome $end $scope struct which $end -$var wire 4 |K value $end +$var wire 4 8R value $end $upscope $end $scope struct value $end -$var wire 64 }K int_fp $end +$var wire 64 9R int_fp $end $scope struct flags $end -$var wire 1 ~K pwr_ca_x86_cf $end -$var wire 1 !L pwr_ca32_x86_af $end -$var wire 1 "L pwr_ov_x86_of $end -$var wire 1 #L pwr_ov32_x86_df $end -$var wire 1 $L pwr_cr_lt_x86_sf $end -$var wire 1 %L pwr_cr_gt_x86_pf $end -$var wire 1 &L pwr_cr_eq_x86_zf $end -$var wire 1 'L pwr_so $end +$var wire 1 :R pwr_ca_x86_cf $end +$var wire 1 ;R pwr_ca32_x86_af $end +$var wire 1 R pwr_cr_lt_x86_sf $end +$var wire 1 ?R pwr_cr_gt_x86_pf $end +$var wire 1 @R pwr_cr_eq_x86_zf $end +$var wire 1 AR pwr_so $end $upscope $end $upscope $end $upscope $end @@ -9552,38 +10764,2418 @@ $upscope $end $scope struct _phantom $end $upscope $end $upscope $end -$scope struct input_insn $end +$scope struct input $end $scope struct data $end -$var string 1 (L \$tag $end +$var string 1 BR \$tag $end $scope struct HdlSome $end -$var string 1 )L \$tag $end +$scope struct mop $end +$var string 1 CR \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 *L prefix_pad $end +$var string 0 DR prefix_pad $end $scope struct dest $end -$var wire 4 +L value $end +$var wire 4 ER value $end $upscope $end $scope struct src $end -$var wire 6 ,L \[0] $end -$var wire 6 -L \[1] $end -$var wire 6 .L \[2] $end +$var wire 6 FR \[0] $end +$var wire 6 GR \[1] $end +$var wire 6 HR \[2] $end $upscope $end -$var wire 25 /L imm_low $end -$var wire 1 0L imm_sign $end +$var wire 25 IR imm_low $end +$var wire 1 JR imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 1L output_integer_mode $end +$var string 1 KR output_integer_mode $end $upscope $end -$var wire 1 2L invert_src0 $end -$var wire 1 3L invert_carry_in $end -$var wire 1 4L invert_carry_out $end -$var wire 1 5L add_pc $end +$var wire 1 LR invert_src0 $end +$var wire 1 MR src1_is_carry_in $end +$var wire 1 NR invert_carry_in $end +$var wire 1 OR add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end +$var string 0 PR prefix_pad $end +$scope struct dest $end +$var wire 4 QR value $end +$upscope $end +$scope struct src $end +$var wire 6 RR \[0] $end +$var wire 6 SR \[1] $end +$var wire 6 TR \[2] $end +$upscope $end +$var wire 25 UR imm_low $end +$var wire 1 VR imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 WR output_integer_mode $end +$upscope $end +$var wire 1 XR invert_src0 $end +$var wire 1 YR src1_is_carry_in $end +$var wire 1 ZR invert_carry_in $end +$var wire 1 [R add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 \R prefix_pad $end +$scope struct dest $end +$var wire 4 ]R value $end +$upscope $end +$scope struct src $end +$var wire 6 ^R \[0] $end +$var wire 6 _R \[1] $end +$var wire 6 `R \[2] $end +$upscope $end +$var wire 25 aR imm_low $end +$var wire 1 bR imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 cR output_integer_mode $end +$upscope $end +$var wire 4 dR lut $end +$upscope $end +$upscope $end +$var wire 64 eR pc $end +$upscope $end +$upscope $end +$var wire 1 fR ready $end +$upscope $end +$scope struct cancel_input $end +$var string 1 gR \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 hR value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct output $end +$var string 1 iR \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 jR value $end +$upscope $end +$scope struct result $end +$var string 1 kR \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 lR int_fp $end +$scope struct flags $end +$var wire 1 mR pwr_ca_x86_cf $end +$var wire 1 nR pwr_ca32_x86_af $end +$var wire 1 oR pwr_ov_x86_of $end +$var wire 1 pR pwr_ov32_x86_df $end +$var wire 1 qR pwr_cr_lt_x86_sf $end +$var wire 1 rR pwr_cr_gt_x86_pf $end +$var wire 1 sR pwr_cr_eq_x86_zf $end +$var wire 1 tR pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct execute_start $end +$scope struct data $end +$var string 1 uR \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 vR \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 wR prefix_pad $end +$scope struct dest $end +$var wire 4 xR value $end +$upscope $end +$scope struct src $end +$var wire 6 yR \[0] $end +$var wire 6 zR \[1] $end +$var wire 6 {R \[2] $end +$upscope $end +$var wire 25 |R imm_low $end +$var wire 1 }R imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ~R output_integer_mode $end +$upscope $end +$var wire 1 !S invert_src0 $end +$var wire 1 "S src1_is_carry_in $end +$var wire 1 #S invert_carry_in $end +$var wire 1 $S add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 %S prefix_pad $end +$scope struct dest $end +$var wire 4 &S value $end +$upscope $end +$scope struct src $end +$var wire 6 'S \[0] $end +$var wire 6 (S \[1] $end +$var wire 6 )S \[2] $end +$upscope $end +$var wire 25 *S imm_low $end +$var wire 1 +S imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ,S output_integer_mode $end +$upscope $end +$var wire 1 -S invert_src0 $end +$var wire 1 .S src1_is_carry_in $end +$var wire 1 /S invert_carry_in $end +$var wire 1 0S add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 1S prefix_pad $end +$scope struct dest $end +$var wire 4 2S value $end +$upscope $end +$scope struct src $end +$var wire 6 3S \[0] $end +$var wire 6 4S \[1] $end +$var wire 6 5S \[2] $end +$upscope $end +$var wire 25 6S imm_low $end +$var wire 1 7S imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 8S output_integer_mode $end +$upscope $end +$var wire 4 9S lut $end +$upscope $end +$upscope $end +$var wire 64 :S pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 ;S int_fp $end +$scope struct flags $end +$var wire 1 S pwr_ov_x86_of $end +$var wire 1 ?S pwr_ov32_x86_df $end +$var wire 1 @S pwr_cr_lt_x86_sf $end +$var wire 1 AS pwr_cr_gt_x86_pf $end +$var wire 1 BS pwr_cr_eq_x86_zf $end +$var wire 1 CS pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 DS int_fp $end +$scope struct flags $end +$var wire 1 ES pwr_ca_x86_cf $end +$var wire 1 FS pwr_ca32_x86_af $end +$var wire 1 GS pwr_ov_x86_of $end +$var wire 1 HS pwr_ov32_x86_df $end +$var wire 1 IS pwr_cr_lt_x86_sf $end +$var wire 1 JS pwr_cr_gt_x86_pf $end +$var wire 1 KS pwr_cr_eq_x86_zf $end +$var wire 1 LS pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 MS int_fp $end +$scope struct flags $end +$var wire 1 NS pwr_ca_x86_cf $end +$var wire 1 OS pwr_ca32_x86_af $end +$var wire 1 PS pwr_ov_x86_of $end +$var wire 1 QS pwr_ov32_x86_df $end +$var wire 1 RS pwr_cr_lt_x86_sf $end +$var wire 1 SS pwr_cr_gt_x86_pf $end +$var wire 1 TS pwr_cr_eq_x86_zf $end +$var wire 1 US pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 VS ready $end +$upscope $end +$scope struct execute_end $end +$var string 1 WS \$tag $end +$scope struct HdlSome $end +$scope struct unit_output $end +$scope struct which $end +$var wire 4 XS value $end +$upscope $end +$scope struct result $end +$var string 1 YS \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 ZS int_fp $end +$scope struct flags $end +$var wire 1 [S pwr_ca_x86_cf $end +$var wire 1 \S pwr_ca32_x86_af $end +$var wire 1 ]S pwr_ov_x86_of $end +$var wire 1 ^S pwr_ov32_x86_df $end +$var wire 1 _S pwr_cr_lt_x86_sf $end +$var wire 1 `S pwr_cr_gt_x86_pf $end +$var wire 1 aS pwr_cr_eq_x86_zf $end +$var wire 1 bS pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_base_2 $end +$scope struct cd $end +$var wire 1 @C clk $end +$var wire 1 AC rst $end +$upscope $end +$scope struct unit_to_reg_alloc $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 BC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 CC value $end +$upscope $end +$scope struct value $end +$var wire 64 DC int_fp $end +$scope struct flags $end +$var wire 1 EC pwr_ca_x86_cf $end +$var wire 1 FC pwr_ca32_x86_af $end +$var wire 1 GC pwr_ov_x86_of $end +$var wire 1 HC pwr_ov32_x86_df $end +$var wire 1 IC pwr_cr_lt_x86_sf $end +$var wire 1 JC pwr_cr_gt_x86_pf $end +$var wire 1 KC pwr_cr_eq_x86_zf $end +$var wire 1 LC pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 MC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 NC value $end +$upscope $end +$scope struct value $end +$var wire 64 OC int_fp $end +$scope struct flags $end +$var wire 1 PC pwr_ca_x86_cf $end +$var wire 1 QC pwr_ca32_x86_af $end +$var wire 1 RC pwr_ov_x86_of $end +$var wire 1 SC pwr_ov32_x86_df $end +$var wire 1 TC pwr_cr_lt_x86_sf $end +$var wire 1 UC pwr_cr_gt_x86_pf $end +$var wire 1 VC pwr_cr_eq_x86_zf $end +$var wire 1 WC pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input $end +$scope struct data $end +$var string 1 XC \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 YC \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ZC prefix_pad $end +$scope struct dest $end +$var wire 4 [C value $end +$upscope $end +$scope struct src $end +$var wire 6 \C \[0] $end +$var wire 6 ]C \[1] $end +$var wire 6 ^C \[2] $end +$upscope $end +$var wire 25 _C imm_low $end +$var wire 1 `C imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 aC output_integer_mode $end +$upscope $end +$var wire 1 bC invert_src0 $end +$var wire 1 cC src1_is_carry_in $end +$var wire 1 dC invert_carry_in $end +$var wire 1 eC add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 fC prefix_pad $end +$scope struct dest $end +$var wire 4 gC value $end +$upscope $end +$scope struct src $end +$var wire 6 hC \[0] $end +$var wire 6 iC \[1] $end +$var wire 6 jC \[2] $end +$upscope $end +$var wire 25 kC imm_low $end +$var wire 1 lC imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 mC output_integer_mode $end +$upscope $end +$var wire 1 nC invert_src0 $end +$var wire 1 oC src1_is_carry_in $end +$var wire 1 pC invert_carry_in $end +$var wire 1 qC add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 rC prefix_pad $end +$scope struct dest $end +$var wire 4 sC value $end +$upscope $end +$scope struct src $end +$var wire 6 tC \[0] $end +$var wire 6 uC \[1] $end +$var wire 6 vC \[2] $end +$upscope $end +$var wire 25 wC imm_low $end +$var wire 1 xC imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 yC output_integer_mode $end +$upscope $end +$var wire 4 zC lut $end +$upscope $end +$upscope $end +$var wire 64 {C pc $end +$upscope $end +$upscope $end +$var wire 1 |C ready $end +$upscope $end +$scope struct cancel_input $end +$var string 1 }C \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ~C value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct output $end +$var string 1 !D \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 "D value $end +$upscope $end +$scope struct result $end +$var string 1 #D \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 $D int_fp $end +$scope struct flags $end +$var wire 1 %D pwr_ca_x86_cf $end +$var wire 1 &D pwr_ca32_x86_af $end +$var wire 1 'D pwr_ov_x86_of $end +$var wire 1 (D pwr_ov32_x86_df $end +$var wire 1 )D pwr_cr_lt_x86_sf $end +$var wire 1 *D pwr_cr_gt_x86_pf $end +$var wire 1 +D pwr_cr_eq_x86_zf $end +$var wire 1 ,D pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct execute_start $end +$scope struct data $end +$var string 1 -D \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 .D \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 /D prefix_pad $end +$scope struct dest $end +$var wire 4 0D value $end +$upscope $end +$scope struct src $end +$var wire 6 1D \[0] $end +$var wire 6 2D \[1] $end +$var wire 6 3D \[2] $end +$upscope $end +$var wire 25 4D imm_low $end +$var wire 1 5D imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 6D output_integer_mode $end +$upscope $end +$var wire 1 7D invert_src0 $end +$var wire 1 8D src1_is_carry_in $end +$var wire 1 9D invert_carry_in $end +$var wire 1 :D add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ;D prefix_pad $end +$scope struct dest $end +$var wire 4 D \[1] $end +$var wire 6 ?D \[2] $end +$upscope $end +$var wire 25 @D imm_low $end +$var wire 1 AD imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 BD output_integer_mode $end +$upscope $end +$var wire 1 CD invert_src0 $end +$var wire 1 DD src1_is_carry_in $end +$var wire 1 ED invert_carry_in $end +$var wire 1 FD add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 GD prefix_pad $end +$scope struct dest $end +$var wire 4 HD value $end +$upscope $end +$scope struct src $end +$var wire 6 ID \[0] $end +$var wire 6 JD \[1] $end +$var wire 6 KD \[2] $end +$upscope $end +$var wire 25 LD imm_low $end +$var wire 1 MD imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ND output_integer_mode $end +$upscope $end +$var wire 4 OD lut $end +$upscope $end +$upscope $end +$var wire 64 PD pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 QD int_fp $end +$scope struct flags $end +$var wire 1 RD pwr_ca_x86_cf $end +$var wire 1 SD pwr_ca32_x86_af $end +$var wire 1 TD pwr_ov_x86_of $end +$var wire 1 UD pwr_ov32_x86_df $end +$var wire 1 VD pwr_cr_lt_x86_sf $end +$var wire 1 WD pwr_cr_gt_x86_pf $end +$var wire 1 XD pwr_cr_eq_x86_zf $end +$var wire 1 YD pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 ZD int_fp $end +$scope struct flags $end +$var wire 1 [D pwr_ca_x86_cf $end +$var wire 1 \D pwr_ca32_x86_af $end +$var wire 1 ]D pwr_ov_x86_of $end +$var wire 1 ^D pwr_ov32_x86_df $end +$var wire 1 _D pwr_cr_lt_x86_sf $end +$var wire 1 `D pwr_cr_gt_x86_pf $end +$var wire 1 aD pwr_cr_eq_x86_zf $end +$var wire 1 bD pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 cD int_fp $end +$scope struct flags $end +$var wire 1 dD pwr_ca_x86_cf $end +$var wire 1 eD pwr_ca32_x86_af $end +$var wire 1 fD pwr_ov_x86_of $end +$var wire 1 gD pwr_ov32_x86_df $end +$var wire 1 hD pwr_cr_lt_x86_sf $end +$var wire 1 iD pwr_cr_gt_x86_pf $end +$var wire 1 jD pwr_cr_eq_x86_zf $end +$var wire 1 kD pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 lD ready $end +$upscope $end +$scope struct execute_end $end +$var string 1 mD \$tag $end +$scope struct HdlSome $end +$scope struct unit_output $end +$scope struct which $end +$var wire 4 nD value $end +$upscope $end +$scope struct result $end +$var string 1 oD \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 pD int_fp $end +$scope struct flags $end +$var wire 1 qD pwr_ca_x86_cf $end +$var wire 1 rD pwr_ca32_x86_af $end +$var wire 1 sD pwr_ov_x86_of $end +$var wire 1 tD pwr_ov32_x86_df $end +$var wire 1 uD pwr_cr_lt_x86_sf $end +$var wire 1 vD pwr_cr_gt_x86_pf $end +$var wire 1 wD pwr_cr_eq_x86_zf $end +$var wire 1 xD pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_0_output_regs $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct unit_0_output_regs $end +$var reg 64 [a int_fp $end +$scope struct flags $end +$var reg 1 ka pwr_ca_x86_cf $end +$var reg 1 {a pwr_ca32_x86_af $end +$var reg 1 -b pwr_ov_x86_of $end +$var reg 1 =b pwr_ov32_x86_df $end +$var reg 1 Mb pwr_cr_lt_x86_sf $end +$var reg 1 ]b pwr_cr_gt_x86_pf $end +$var reg 1 mb pwr_cr_eq_x86_zf $end +$var reg 1 }b pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct unit_0_output_regs $end +$var reg 64 \a int_fp $end +$scope struct flags $end +$var reg 1 la pwr_ca_x86_cf $end +$var reg 1 |a pwr_ca32_x86_af $end +$var reg 1 .b pwr_ov_x86_of $end +$var reg 1 >b pwr_ov32_x86_df $end +$var reg 1 Nb pwr_cr_lt_x86_sf $end +$var reg 1 ^b pwr_cr_gt_x86_pf $end +$var reg 1 nb pwr_cr_eq_x86_zf $end +$var reg 1 ~b pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$scope struct unit_0_output_regs $end +$var reg 64 ]a int_fp $end +$scope struct flags $end +$var reg 1 ma pwr_ca_x86_cf $end +$var reg 1 }a pwr_ca32_x86_af $end +$var reg 1 /b pwr_ov_x86_of $end +$var reg 1 ?b pwr_ov32_x86_df $end +$var reg 1 Ob pwr_cr_lt_x86_sf $end +$var reg 1 _b pwr_cr_gt_x86_pf $end +$var reg 1 ob pwr_cr_eq_x86_zf $end +$var reg 1 !c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$scope struct unit_0_output_regs $end +$var reg 64 ^a int_fp $end +$scope struct flags $end +$var reg 1 na pwr_ca_x86_cf $end +$var reg 1 ~a pwr_ca32_x86_af $end +$var reg 1 0b pwr_ov_x86_of $end +$var reg 1 @b pwr_ov32_x86_df $end +$var reg 1 Pb pwr_cr_lt_x86_sf $end +$var reg 1 `b pwr_cr_gt_x86_pf $end +$var reg 1 pb pwr_cr_eq_x86_zf $end +$var reg 1 "c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$scope struct unit_0_output_regs $end +$var reg 64 _a int_fp $end +$scope struct flags $end +$var reg 1 oa pwr_ca_x86_cf $end +$var reg 1 !b pwr_ca32_x86_af $end +$var reg 1 1b pwr_ov_x86_of $end +$var reg 1 Ab pwr_ov32_x86_df $end +$var reg 1 Qb pwr_cr_lt_x86_sf $end +$var reg 1 ab pwr_cr_gt_x86_pf $end +$var reg 1 qb pwr_cr_eq_x86_zf $end +$var reg 1 #c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$scope struct unit_0_output_regs $end +$var reg 64 `a int_fp $end +$scope struct flags $end +$var reg 1 pa pwr_ca_x86_cf $end +$var reg 1 "b pwr_ca32_x86_af $end +$var reg 1 2b pwr_ov_x86_of $end +$var reg 1 Bb pwr_ov32_x86_df $end +$var reg 1 Rb pwr_cr_lt_x86_sf $end +$var reg 1 bb pwr_cr_gt_x86_pf $end +$var reg 1 rb pwr_cr_eq_x86_zf $end +$var reg 1 $c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$scope struct unit_0_output_regs $end +$var reg 64 aa int_fp $end +$scope struct flags $end +$var reg 1 qa pwr_ca_x86_cf $end +$var reg 1 #b pwr_ca32_x86_af $end +$var reg 1 3b pwr_ov_x86_of $end +$var reg 1 Cb pwr_ov32_x86_df $end +$var reg 1 Sb pwr_cr_lt_x86_sf $end +$var reg 1 cb pwr_cr_gt_x86_pf $end +$var reg 1 sb pwr_cr_eq_x86_zf $end +$var reg 1 %c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$scope struct unit_0_output_regs $end +$var reg 64 ba int_fp $end +$scope struct flags $end +$var reg 1 ra pwr_ca_x86_cf $end +$var reg 1 $b pwr_ca32_x86_af $end +$var reg 1 4b pwr_ov_x86_of $end +$var reg 1 Db pwr_ov32_x86_df $end +$var reg 1 Tb pwr_cr_lt_x86_sf $end +$var reg 1 db pwr_cr_gt_x86_pf $end +$var reg 1 tb pwr_cr_eq_x86_zf $end +$var reg 1 &c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$scope struct unit_0_output_regs $end +$var reg 64 ca int_fp $end +$scope struct flags $end +$var reg 1 sa pwr_ca_x86_cf $end +$var reg 1 %b pwr_ca32_x86_af $end +$var reg 1 5b pwr_ov_x86_of $end +$var reg 1 Eb pwr_ov32_x86_df $end +$var reg 1 Ub pwr_cr_lt_x86_sf $end +$var reg 1 eb pwr_cr_gt_x86_pf $end +$var reg 1 ub pwr_cr_eq_x86_zf $end +$var reg 1 'c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$scope struct unit_0_output_regs $end +$var reg 64 da int_fp $end +$scope struct flags $end +$var reg 1 ta pwr_ca_x86_cf $end +$var reg 1 &b pwr_ca32_x86_af $end +$var reg 1 6b pwr_ov_x86_of $end +$var reg 1 Fb pwr_ov32_x86_df $end +$var reg 1 Vb pwr_cr_lt_x86_sf $end +$var reg 1 fb pwr_cr_gt_x86_pf $end +$var reg 1 vb pwr_cr_eq_x86_zf $end +$var reg 1 (c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$scope struct unit_0_output_regs $end +$var reg 64 ea int_fp $end +$scope struct flags $end +$var reg 1 ua pwr_ca_x86_cf $end +$var reg 1 'b pwr_ca32_x86_af $end +$var reg 1 7b pwr_ov_x86_of $end +$var reg 1 Gb pwr_ov32_x86_df $end +$var reg 1 Wb pwr_cr_lt_x86_sf $end +$var reg 1 gb pwr_cr_gt_x86_pf $end +$var reg 1 wb pwr_cr_eq_x86_zf $end +$var reg 1 )c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$scope struct unit_0_output_regs $end +$var reg 64 fa int_fp $end +$scope struct flags $end +$var reg 1 va pwr_ca_x86_cf $end +$var reg 1 (b pwr_ca32_x86_af $end +$var reg 1 8b pwr_ov_x86_of $end +$var reg 1 Hb pwr_ov32_x86_df $end +$var reg 1 Xb pwr_cr_lt_x86_sf $end +$var reg 1 hb pwr_cr_gt_x86_pf $end +$var reg 1 xb pwr_cr_eq_x86_zf $end +$var reg 1 *c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$scope struct unit_0_output_regs $end +$var reg 64 ga int_fp $end +$scope struct flags $end +$var reg 1 wa pwr_ca_x86_cf $end +$var reg 1 )b pwr_ca32_x86_af $end +$var reg 1 9b pwr_ov_x86_of $end +$var reg 1 Ib pwr_ov32_x86_df $end +$var reg 1 Yb pwr_cr_lt_x86_sf $end +$var reg 1 ib pwr_cr_gt_x86_pf $end +$var reg 1 yb pwr_cr_eq_x86_zf $end +$var reg 1 +c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$scope struct unit_0_output_regs $end +$var reg 64 ha int_fp $end +$scope struct flags $end +$var reg 1 xa pwr_ca_x86_cf $end +$var reg 1 *b pwr_ca32_x86_af $end +$var reg 1 :b pwr_ov_x86_of $end +$var reg 1 Jb pwr_ov32_x86_df $end +$var reg 1 Zb pwr_cr_lt_x86_sf $end +$var reg 1 jb pwr_cr_gt_x86_pf $end +$var reg 1 zb pwr_cr_eq_x86_zf $end +$var reg 1 ,c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$scope struct unit_0_output_regs $end +$var reg 64 ia int_fp $end +$scope struct flags $end +$var reg 1 ya pwr_ca_x86_cf $end +$var reg 1 +b pwr_ca32_x86_af $end +$var reg 1 ;b pwr_ov_x86_of $end +$var reg 1 Kb pwr_ov32_x86_df $end +$var reg 1 [b pwr_cr_lt_x86_sf $end +$var reg 1 kb pwr_cr_gt_x86_pf $end +$var reg 1 {b pwr_cr_eq_x86_zf $end +$var reg 1 -c pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$scope struct unit_0_output_regs $end +$var reg 64 ja int_fp $end +$scope struct flags $end +$var reg 1 za pwr_ca_x86_cf $end +$var reg 1 ,b pwr_ca32_x86_af $end +$var reg 1 E pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct w3 $end +$var wire 4 ?E addr $end +$var wire 1 @E en $end +$var wire 1 AE clk $end +$scope struct data $end +$var wire 64 BE int_fp $end +$scope struct flags $end +$var wire 1 CE pwr_ca_x86_cf $end +$var wire 1 DE pwr_ca32_x86_af $end +$var wire 1 EE pwr_ov_x86_of $end +$var wire 1 FE pwr_ov32_x86_df $end +$var wire 1 GE pwr_cr_lt_x86_sf $end +$var wire 1 HE pwr_cr_gt_x86_pf $end +$var wire 1 IE pwr_cr_eq_x86_zf $end +$var wire 1 JE pwr_so $end +$upscope $end +$upscope $end +$scope struct mask $end +$var wire 1 KE int_fp $end +$scope struct flags $end +$var wire 1 LE pwr_ca_x86_cf $end +$var wire 1 ME pwr_ca32_x86_af $end +$var wire 1 NE pwr_ov_x86_of $end +$var wire 1 OE pwr_ov32_x86_df $end +$var wire 1 PE pwr_cr_lt_x86_sf $end +$var wire 1 QE pwr_cr_gt_x86_pf $end +$var wire 1 RE pwr_cr_eq_x86_zf $end +$var wire 1 SE pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_1_output_regs $end +$scope struct contents $end +$scope struct \[0] $end +$scope struct unit_1_output_regs $end +$var reg 64 /c int_fp $end +$scope struct flags $end +$var reg 1 ?c pwr_ca_x86_cf $end +$var reg 1 Oc pwr_ca32_x86_af $end +$var reg 1 _c pwr_ov_x86_of $end +$var reg 1 oc pwr_ov32_x86_df $end +$var reg 1 !d pwr_cr_lt_x86_sf $end +$var reg 1 1d pwr_cr_gt_x86_pf $end +$var reg 1 Ad pwr_cr_eq_x86_zf $end +$var reg 1 Qd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$scope struct unit_1_output_regs $end +$var reg 64 0c int_fp $end +$scope struct flags $end +$var reg 1 @c pwr_ca_x86_cf $end +$var reg 1 Pc pwr_ca32_x86_af $end +$var reg 1 `c pwr_ov_x86_of $end +$var reg 1 pc pwr_ov32_x86_df $end +$var reg 1 "d pwr_cr_lt_x86_sf $end +$var reg 1 2d pwr_cr_gt_x86_pf $end +$var reg 1 Bd pwr_cr_eq_x86_zf $end +$var reg 1 Rd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$scope struct unit_1_output_regs $end +$var reg 64 1c int_fp $end +$scope struct flags $end +$var reg 1 Ac pwr_ca_x86_cf $end +$var reg 1 Qc pwr_ca32_x86_af $end +$var reg 1 ac pwr_ov_x86_of $end +$var reg 1 qc pwr_ov32_x86_df $end +$var reg 1 #d pwr_cr_lt_x86_sf $end +$var reg 1 3d pwr_cr_gt_x86_pf $end +$var reg 1 Cd pwr_cr_eq_x86_zf $end +$var reg 1 Sd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$scope struct unit_1_output_regs $end +$var reg 64 2c int_fp $end +$scope struct flags $end +$var reg 1 Bc pwr_ca_x86_cf $end +$var reg 1 Rc pwr_ca32_x86_af $end +$var reg 1 bc pwr_ov_x86_of $end +$var reg 1 rc pwr_ov32_x86_df $end +$var reg 1 $d pwr_cr_lt_x86_sf $end +$var reg 1 4d pwr_cr_gt_x86_pf $end +$var reg 1 Dd pwr_cr_eq_x86_zf $end +$var reg 1 Td pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$scope struct unit_1_output_regs $end +$var reg 64 3c int_fp $end +$scope struct flags $end +$var reg 1 Cc pwr_ca_x86_cf $end +$var reg 1 Sc pwr_ca32_x86_af $end +$var reg 1 cc pwr_ov_x86_of $end +$var reg 1 sc pwr_ov32_x86_df $end +$var reg 1 %d pwr_cr_lt_x86_sf $end +$var reg 1 5d pwr_cr_gt_x86_pf $end +$var reg 1 Ed pwr_cr_eq_x86_zf $end +$var reg 1 Ud pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$scope struct unit_1_output_regs $end +$var reg 64 4c int_fp $end +$scope struct flags $end +$var reg 1 Dc pwr_ca_x86_cf $end +$var reg 1 Tc pwr_ca32_x86_af $end +$var reg 1 dc pwr_ov_x86_of $end +$var reg 1 tc pwr_ov32_x86_df $end +$var reg 1 &d pwr_cr_lt_x86_sf $end +$var reg 1 6d pwr_cr_gt_x86_pf $end +$var reg 1 Fd pwr_cr_eq_x86_zf $end +$var reg 1 Vd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$scope struct unit_1_output_regs $end +$var reg 64 5c int_fp $end +$scope struct flags $end +$var reg 1 Ec pwr_ca_x86_cf $end +$var reg 1 Uc pwr_ca32_x86_af $end +$var reg 1 ec pwr_ov_x86_of $end +$var reg 1 uc pwr_ov32_x86_df $end +$var reg 1 'd pwr_cr_lt_x86_sf $end +$var reg 1 7d pwr_cr_gt_x86_pf $end +$var reg 1 Gd pwr_cr_eq_x86_zf $end +$var reg 1 Wd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$scope struct unit_1_output_regs $end +$var reg 64 6c int_fp $end +$scope struct flags $end +$var reg 1 Fc pwr_ca_x86_cf $end +$var reg 1 Vc pwr_ca32_x86_af $end +$var reg 1 fc pwr_ov_x86_of $end +$var reg 1 vc pwr_ov32_x86_df $end +$var reg 1 (d pwr_cr_lt_x86_sf $end +$var reg 1 8d pwr_cr_gt_x86_pf $end +$var reg 1 Hd pwr_cr_eq_x86_zf $end +$var reg 1 Xd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$scope struct unit_1_output_regs $end +$var reg 64 7c int_fp $end +$scope struct flags $end +$var reg 1 Gc pwr_ca_x86_cf $end +$var reg 1 Wc pwr_ca32_x86_af $end +$var reg 1 gc pwr_ov_x86_of $end +$var reg 1 wc pwr_ov32_x86_df $end +$var reg 1 )d pwr_cr_lt_x86_sf $end +$var reg 1 9d pwr_cr_gt_x86_pf $end +$var reg 1 Id pwr_cr_eq_x86_zf $end +$var reg 1 Yd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$scope struct unit_1_output_regs $end +$var reg 64 8c int_fp $end +$scope struct flags $end +$var reg 1 Hc pwr_ca_x86_cf $end +$var reg 1 Xc pwr_ca32_x86_af $end +$var reg 1 hc pwr_ov_x86_of $end +$var reg 1 xc pwr_ov32_x86_df $end +$var reg 1 *d pwr_cr_lt_x86_sf $end +$var reg 1 :d pwr_cr_gt_x86_pf $end +$var reg 1 Jd pwr_cr_eq_x86_zf $end +$var reg 1 Zd pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$scope struct unit_1_output_regs $end +$var reg 64 9c int_fp $end +$scope struct flags $end +$var reg 1 Ic pwr_ca_x86_cf $end +$var reg 1 Yc pwr_ca32_x86_af $end +$var reg 1 ic pwr_ov_x86_of $end +$var reg 1 yc pwr_ov32_x86_df $end +$var reg 1 +d pwr_cr_lt_x86_sf $end +$var reg 1 ;d pwr_cr_gt_x86_pf $end +$var reg 1 Kd pwr_cr_eq_x86_zf $end +$var reg 1 [d pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$scope struct unit_1_output_regs $end +$var reg 64 :c int_fp $end +$scope struct flags $end +$var reg 1 Jc pwr_ca_x86_cf $end +$var reg 1 Zc pwr_ca32_x86_af $end +$var reg 1 jc pwr_ov_x86_of $end +$var reg 1 zc pwr_ov32_x86_df $end +$var reg 1 ,d pwr_cr_lt_x86_sf $end +$var reg 1 d pwr_cr_gt_x86_pf $end +$var reg 1 Nd pwr_cr_eq_x86_zf $end +$var reg 1 ^d pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$scope struct unit_1_output_regs $end +$var reg 64 =c int_fp $end +$scope struct flags $end +$var reg 1 Mc pwr_ca_x86_cf $end +$var reg 1 ]c pwr_ca32_x86_af $end +$var reg 1 mc pwr_ov_x86_of $end +$var reg 1 }c pwr_ov32_x86_df $end +$var reg 1 /d pwr_cr_lt_x86_sf $end +$var reg 1 ?d pwr_cr_gt_x86_pf $end +$var reg 1 Od pwr_cr_eq_x86_zf $end +$var reg 1 _d pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$scope struct unit_1_output_regs $end +$var reg 64 >c int_fp $end +$scope struct flags $end +$var reg 1 Nc pwr_ca_x86_cf $end +$var reg 1 ^c pwr_ca32_x86_af $end +$var reg 1 nc pwr_ov_x86_of $end +$var reg 1 ~c pwr_ov32_x86_df $end +$var reg 1 0d pwr_cr_lt_x86_sf $end +$var reg 1 @d pwr_cr_gt_x86_pf $end +$var reg 1 Pd pwr_cr_eq_x86_zf $end +$var reg 1 `d pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 TE addr $end +$var wire 1 UE en $end +$var wire 1 VE clk $end +$scope struct data $end +$var wire 64 WE int_fp $end +$scope struct flags $end +$var wire 1 XE pwr_ca_x86_cf $end +$var wire 1 YE pwr_ca32_x86_af $end +$var wire 1 ZE pwr_ov_x86_of $end +$var wire 1 [E pwr_ov32_x86_df $end +$var wire 1 \E pwr_cr_lt_x86_sf $end +$var wire 1 ]E pwr_cr_gt_x86_pf $end +$var wire 1 ^E pwr_cr_eq_x86_zf $end +$var wire 1 _E pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r1 $end +$var wire 4 `E addr $end +$var wire 1 aE en $end +$var wire 1 bE clk $end +$scope struct data $end +$var wire 64 cE int_fp $end +$scope struct flags $end +$var wire 1 dE pwr_ca_x86_cf $end +$var wire 1 eE pwr_ca32_x86_af $end +$var wire 1 fE pwr_ov_x86_of $end +$var wire 1 gE pwr_ov32_x86_df $end +$var wire 1 hE pwr_cr_lt_x86_sf $end +$var wire 1 iE pwr_cr_gt_x86_pf $end +$var wire 1 jE pwr_cr_eq_x86_zf $end +$var wire 1 kE pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r2 $end +$var wire 4 lE addr $end +$var wire 1 mE en $end +$var wire 1 nE clk $end +$scope struct data $end +$var wire 64 oE int_fp $end +$scope struct flags $end +$var wire 1 pE pwr_ca_x86_cf $end +$var wire 1 qE pwr_ca32_x86_af $end +$var wire 1 rE pwr_ov_x86_of $end +$var wire 1 sE pwr_ov32_x86_df $end +$var wire 1 tE pwr_cr_lt_x86_sf $end +$var wire 1 uE pwr_cr_gt_x86_pf $end +$var wire 1 vE pwr_cr_eq_x86_zf $end +$var wire 1 wE pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct w3 $end +$var wire 4 xE addr $end +$var wire 1 yE en $end +$var wire 1 zE clk $end +$scope struct data $end +$var wire 64 {E int_fp $end +$scope struct flags $end +$var wire 1 |E pwr_ca_x86_cf $end +$var wire 1 }E pwr_ca32_x86_af $end +$var wire 1 ~E pwr_ov_x86_of $end +$var wire 1 !F pwr_ov32_x86_df $end +$var wire 1 "F pwr_cr_lt_x86_sf $end +$var wire 1 #F pwr_cr_gt_x86_pf $end +$var wire 1 $F pwr_cr_eq_x86_zf $end +$var wire 1 %F pwr_so $end +$upscope $end +$upscope $end +$scope struct mask $end +$var wire 1 &F int_fp $end +$scope struct flags $end +$var wire 1 'F pwr_ca_x86_cf $end +$var wire 1 (F pwr_ca32_x86_af $end +$var wire 1 )F pwr_ov_x86_of $end +$var wire 1 *F pwr_ov32_x86_df $end +$var wire 1 +F pwr_cr_lt_x86_sf $end +$var wire 1 ,F pwr_cr_gt_x86_pf $end +$var wire 1 -F pwr_cr_eq_x86_zf $end +$var wire 1 .F pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct in_flight_ops $end +$scope struct \[0] $end +$var string 1 /F \$tag $end +$scope struct HdlSome $end +$var string 1 0F state $end +$scope struct mop $end +$var string 1 1F \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 2F prefix_pad $end +$scope struct dest $end +$var reg 4 3F value $end +$upscope $end +$scope struct src $end +$var reg 6 4F \[0] $end +$var reg 6 5F \[1] $end +$var reg 6 6F \[2] $end +$upscope $end +$var reg 25 7F imm_low $end +$var reg 1 8F imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 9F output_integer_mode $end +$upscope $end +$var reg 1 :F invert_src0 $end +$var reg 1 ;F src1_is_carry_in $end +$var reg 1 F prefix_pad $end +$scope struct dest $end +$var reg 4 ?F value $end +$upscope $end +$scope struct src $end +$var reg 6 @F \[0] $end +$var reg 6 AF \[1] $end +$var reg 6 BF \[2] $end +$upscope $end +$var reg 25 CF imm_low $end +$var reg 1 DF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 EF output_integer_mode $end +$upscope $end +$var reg 1 FF invert_src0 $end +$var reg 1 GF src1_is_carry_in $end +$var reg 1 HF invert_carry_in $end +$var reg 1 IF add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 JF prefix_pad $end +$scope struct dest $end +$var reg 4 KF value $end +$upscope $end +$scope struct src $end +$var reg 6 LF \[0] $end +$var reg 6 MF \[1] $end +$var reg 6 NF \[2] $end +$upscope $end +$var reg 25 OF imm_low $end +$var reg 1 PF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 QF output_integer_mode $end +$upscope $end +$var reg 4 RF lut $end +$upscope $end +$upscope $end +$var reg 64 SF pc $end +$scope struct src_ready_flags $end +$var reg 1 TF \[0] $end +$var reg 1 UF \[1] $end +$var reg 1 VF \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 WF \$tag $end +$scope struct HdlSome $end +$var string 1 XF state $end +$scope struct mop $end +$var string 1 YF \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ZF prefix_pad $end +$scope struct dest $end +$var reg 4 [F value $end +$upscope $end +$scope struct src $end +$var reg 6 \F \[0] $end +$var reg 6 ]F \[1] $end +$var reg 6 ^F \[2] $end +$upscope $end +$var reg 25 _F imm_low $end +$var reg 1 `F imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 aF output_integer_mode $end +$upscope $end +$var reg 1 bF invert_src0 $end +$var reg 1 cF src1_is_carry_in $end +$var reg 1 dF invert_carry_in $end +$var reg 1 eF add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 fF prefix_pad $end +$scope struct dest $end +$var reg 4 gF value $end +$upscope $end +$scope struct src $end +$var reg 6 hF \[0] $end +$var reg 6 iF \[1] $end +$var reg 6 jF \[2] $end +$upscope $end +$var reg 25 kF imm_low $end +$var reg 1 lF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 mF output_integer_mode $end +$upscope $end +$var reg 1 nF invert_src0 $end +$var reg 1 oF src1_is_carry_in $end +$var reg 1 pF invert_carry_in $end +$var reg 1 qF add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 rF prefix_pad $end +$scope struct dest $end +$var reg 4 sF value $end +$upscope $end +$scope struct src $end +$var reg 6 tF \[0] $end +$var reg 6 uF \[1] $end +$var reg 6 vF \[2] $end +$upscope $end +$var reg 25 wF imm_low $end +$var reg 1 xF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 yF output_integer_mode $end +$upscope $end +$var reg 4 zF lut $end +$upscope $end +$upscope $end +$var reg 64 {F pc $end +$scope struct src_ready_flags $end +$var reg 1 |F \[0] $end +$var reg 1 }F \[1] $end +$var reg 1 ~F \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 !G \$tag $end +$scope struct HdlSome $end +$var string 1 "G state $end +$scope struct mop $end +$var string 1 #G \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 $G prefix_pad $end +$scope struct dest $end +$var reg 4 %G value $end +$upscope $end +$scope struct src $end +$var reg 6 &G \[0] $end +$var reg 6 'G \[1] $end +$var reg 6 (G \[2] $end +$upscope $end +$var reg 25 )G imm_low $end +$var reg 1 *G imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 +G output_integer_mode $end +$upscope $end +$var reg 1 ,G invert_src0 $end +$var reg 1 -G src1_is_carry_in $end +$var reg 1 .G invert_carry_in $end +$var reg 1 /G add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 0G prefix_pad $end +$scope struct dest $end +$var reg 4 1G value $end +$upscope $end +$scope struct src $end +$var reg 6 2G \[0] $end +$var reg 6 3G \[1] $end +$var reg 6 4G \[2] $end +$upscope $end +$var reg 25 5G imm_low $end +$var reg 1 6G imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 7G output_integer_mode $end +$upscope $end +$var reg 1 8G invert_src0 $end +$var reg 1 9G src1_is_carry_in $end +$var reg 1 :G invert_carry_in $end +$var reg 1 ;G add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 G \[0] $end +$var reg 6 ?G \[1] $end +$var reg 6 @G \[2] $end +$upscope $end +$var reg 25 AG imm_low $end +$var reg 1 BG imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 CG output_integer_mode $end +$upscope $end +$var reg 4 DG lut $end +$upscope $end +$upscope $end +$var reg 64 EG pc $end +$scope struct src_ready_flags $end +$var reg 1 FG \[0] $end +$var reg 1 GG \[1] $end +$var reg 1 HG \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 IG \$tag $end +$scope struct HdlSome $end +$var string 1 JG state $end +$scope struct mop $end +$var string 1 KG \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 LG prefix_pad $end +$scope struct dest $end +$var reg 4 MG value $end +$upscope $end +$scope struct src $end +$var reg 6 NG \[0] $end +$var reg 6 OG \[1] $end +$var reg 6 PG \[2] $end +$upscope $end +$var reg 25 QG imm_low $end +$var reg 1 RG imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 SG output_integer_mode $end +$upscope $end +$var reg 1 TG invert_src0 $end +$var reg 1 UG src1_is_carry_in $end +$var reg 1 VG invert_carry_in $end +$var reg 1 WG add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 XG prefix_pad $end +$scope struct dest $end +$var reg 4 YG value $end +$upscope $end +$scope struct src $end +$var reg 6 ZG \[0] $end +$var reg 6 [G \[1] $end +$var reg 6 \G \[2] $end +$upscope $end +$var reg 25 ]G imm_low $end +$var reg 1 ^G imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 _G output_integer_mode $end +$upscope $end +$var reg 1 `G invert_src0 $end +$var reg 1 aG src1_is_carry_in $end +$var reg 1 bG invert_carry_in $end +$var reg 1 cG add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 dG prefix_pad $end +$scope struct dest $end +$var reg 4 eG value $end +$upscope $end +$scope struct src $end +$var reg 6 fG \[0] $end +$var reg 6 gG \[1] $end +$var reg 6 hG \[2] $end +$upscope $end +$var reg 25 iG imm_low $end +$var reg 1 jG imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 kG output_integer_mode $end +$upscope $end +$var reg 4 lG lut $end +$upscope $end +$upscope $end +$var reg 64 mG pc $end +$scope struct src_ready_flags $end +$var reg 1 nG \[0] $end +$var reg 1 oG \[1] $end +$var reg 1 pG \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 qG \$tag $end +$scope struct HdlSome $end +$var string 1 rG state $end +$scope struct mop $end +$var string 1 sG \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 tG prefix_pad $end +$scope struct dest $end +$var reg 4 uG value $end +$upscope $end +$scope struct src $end +$var reg 6 vG \[0] $end +$var reg 6 wG \[1] $end +$var reg 6 xG \[2] $end +$upscope $end +$var reg 25 yG imm_low $end +$var reg 1 zG imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 {G output_integer_mode $end +$upscope $end +$var reg 1 |G invert_src0 $end +$var reg 1 }G src1_is_carry_in $end +$var reg 1 ~G invert_carry_in $end +$var reg 1 !H add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 "H prefix_pad $end +$scope struct dest $end +$var reg 4 #H value $end +$upscope $end +$scope struct src $end +$var reg 6 $H \[0] $end +$var reg 6 %H \[1] $end +$var reg 6 &H \[2] $end +$upscope $end +$var reg 25 'H imm_low $end +$var reg 1 (H imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 )H output_integer_mode $end +$upscope $end +$var reg 1 *H invert_src0 $end +$var reg 1 +H src1_is_carry_in $end +$var reg 1 ,H invert_carry_in $end +$var reg 1 -H add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 .H prefix_pad $end +$scope struct dest $end +$var reg 4 /H value $end +$upscope $end +$scope struct src $end +$var reg 6 0H \[0] $end +$var reg 6 1H \[1] $end +$var reg 6 2H \[2] $end +$upscope $end +$var reg 25 3H imm_low $end +$var reg 1 4H imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 5H output_integer_mode $end +$upscope $end +$var reg 4 6H lut $end +$upscope $end +$upscope $end +$var reg 64 7H pc $end +$scope struct src_ready_flags $end +$var reg 1 8H \[0] $end +$var reg 1 9H \[1] $end +$var reg 1 :H \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 ;H \$tag $end +$scope struct HdlSome $end +$var string 1 H prefix_pad $end +$scope struct dest $end +$var reg 4 ?H value $end +$upscope $end +$scope struct src $end +$var reg 6 @H \[0] $end +$var reg 6 AH \[1] $end +$var reg 6 BH \[2] $end +$upscope $end +$var reg 25 CH imm_low $end +$var reg 1 DH imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 EH output_integer_mode $end +$upscope $end +$var reg 1 FH invert_src0 $end +$var reg 1 GH src1_is_carry_in $end +$var reg 1 HH invert_carry_in $end +$var reg 1 IH add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 JH prefix_pad $end +$scope struct dest $end +$var reg 4 KH value $end +$upscope $end +$scope struct src $end +$var reg 6 LH \[0] $end +$var reg 6 MH \[1] $end +$var reg 6 NH \[2] $end +$upscope $end +$var reg 25 OH imm_low $end +$var reg 1 PH imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 QH output_integer_mode $end +$upscope $end +$var reg 1 RH invert_src0 $end +$var reg 1 SH src1_is_carry_in $end +$var reg 1 TH invert_carry_in $end +$var reg 1 UH add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 VH prefix_pad $end +$scope struct dest $end +$var reg 4 WH value $end +$upscope $end +$scope struct src $end +$var reg 6 XH \[0] $end +$var reg 6 YH \[1] $end +$var reg 6 ZH \[2] $end +$upscope $end +$var reg 25 [H imm_low $end +$var reg 1 \H imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ]H output_integer_mode $end +$upscope $end +$var reg 4 ^H lut $end +$upscope $end +$upscope $end +$var reg 64 _H pc $end +$scope struct src_ready_flags $end +$var reg 1 `H \[0] $end +$var reg 1 aH \[1] $end +$var reg 1 bH \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 cH \$tag $end +$scope struct HdlSome $end +$var string 1 dH state $end +$scope struct mop $end +$var string 1 eH \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 fH prefix_pad $end +$scope struct dest $end +$var reg 4 gH value $end +$upscope $end +$scope struct src $end +$var reg 6 hH \[0] $end +$var reg 6 iH \[1] $end +$var reg 6 jH \[2] $end +$upscope $end +$var reg 25 kH imm_low $end +$var reg 1 lH imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 mH output_integer_mode $end +$upscope $end +$var reg 1 nH invert_src0 $end +$var reg 1 oH src1_is_carry_in $end +$var reg 1 pH invert_carry_in $end +$var reg 1 qH add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 rH prefix_pad $end +$scope struct dest $end +$var reg 4 sH value $end +$upscope $end +$scope struct src $end +$var reg 6 tH \[0] $end +$var reg 6 uH \[1] $end +$var reg 6 vH \[2] $end +$upscope $end +$var reg 25 wH imm_low $end +$var reg 1 xH imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 yH output_integer_mode $end +$upscope $end +$var reg 1 zH invert_src0 $end +$var reg 1 {H src1_is_carry_in $end +$var reg 1 |H invert_carry_in $end +$var reg 1 }H add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ~H prefix_pad $end +$scope struct dest $end +$var reg 4 !I value $end +$upscope $end +$scope struct src $end +$var reg 6 "I \[0] $end +$var reg 6 #I \[1] $end +$var reg 6 $I \[2] $end +$upscope $end +$var reg 25 %I imm_low $end +$var reg 1 &I imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 'I output_integer_mode $end +$upscope $end +$var reg 4 (I lut $end +$upscope $end +$upscope $end +$var reg 64 )I pc $end +$scope struct src_ready_flags $end +$var reg 1 *I \[0] $end +$var reg 1 +I \[1] $end +$var reg 1 ,I \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 -I \$tag $end +$scope struct HdlSome $end +$var string 1 .I state $end +$scope struct mop $end +$var string 1 /I \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 0I prefix_pad $end +$scope struct dest $end +$var reg 4 1I value $end +$upscope $end +$scope struct src $end +$var reg 6 2I \[0] $end +$var reg 6 3I \[1] $end +$var reg 6 4I \[2] $end +$upscope $end +$var reg 25 5I imm_low $end +$var reg 1 6I imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 7I output_integer_mode $end +$upscope $end +$var reg 1 8I invert_src0 $end +$var reg 1 9I src1_is_carry_in $end +$var reg 1 :I invert_carry_in $end +$var reg 1 ;I add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 I \[0] $end +$var reg 6 ?I \[1] $end +$var reg 6 @I \[2] $end +$upscope $end +$var reg 25 AI imm_low $end +$var reg 1 BI imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 CI output_integer_mode $end +$upscope $end +$var reg 1 DI invert_src0 $end +$var reg 1 EI src1_is_carry_in $end +$var reg 1 FI invert_carry_in $end +$var reg 1 GI add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 HI prefix_pad $end +$scope struct dest $end +$var reg 4 II value $end +$upscope $end +$scope struct src $end +$var reg 6 JI \[0] $end +$var reg 6 KI \[1] $end +$var reg 6 LI \[2] $end +$upscope $end +$var reg 25 MI imm_low $end +$var reg 1 NI imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 OI output_integer_mode $end +$upscope $end +$var reg 4 PI lut $end +$upscope $end +$upscope $end +$var reg 64 QI pc $end +$scope struct src_ready_flags $end +$var reg 1 RI \[0] $end +$var reg 1 SI \[1] $end +$var reg 1 TI \[2] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct empty_op_index_0 $end +$var string 1 UI \$tag $end +$var wire 3 VI HdlSome $end +$upscope $end +$scope struct ready_op_index_0 $end +$var string 1 WI \$tag $end +$var wire 3 XI HdlSome $end +$upscope $end +$scope struct empty_op_index_1 $end +$var string 1 YI \$tag $end +$var wire 3 ZI HdlSome $end +$upscope $end +$scope struct ready_op_index_1 $end +$var string 1 [I \$tag $end +$var wire 3 \I HdlSome $end +$upscope $end +$scope struct or_out $end +$var string 1 ]I \$tag $end +$var wire 3 ^I HdlSome $end +$upscope $end +$scope struct or_out_2 $end +$var string 1 _I \$tag $end +$var wire 3 `I HdlSome $end +$upscope $end +$scope struct empty_op_index_2 $end +$var string 1 aI \$tag $end +$var wire 3 bI HdlSome $end +$upscope $end +$scope struct ready_op_index_2 $end +$var string 1 cI \$tag $end +$var wire 3 dI HdlSome $end +$upscope $end +$scope struct empty_op_index_3 $end +$var string 1 eI \$tag $end +$var wire 3 fI HdlSome $end +$upscope $end +$scope struct ready_op_index_3 $end +$var string 1 gI \$tag $end +$var wire 3 hI HdlSome $end +$upscope $end +$scope struct or_out_3 $end +$var string 1 iI \$tag $end +$var wire 3 jI HdlSome $end +$upscope $end +$scope struct or_out_4 $end +$var string 1 kI \$tag $end +$var wire 3 lI HdlSome $end +$upscope $end +$scope struct or_out_5 $end +$var string 1 mI \$tag $end +$var wire 3 nI HdlSome $end +$upscope $end +$scope struct or_out_6 $end +$var string 1 oI \$tag $end +$var wire 3 pI HdlSome $end +$upscope $end +$scope struct empty_op_index_4 $end +$var string 1 qI \$tag $end +$var wire 3 rI HdlSome $end +$upscope $end +$scope struct ready_op_index_4 $end +$var string 1 sI \$tag $end +$var wire 3 tI HdlSome $end +$upscope $end +$scope struct empty_op_index_5 $end +$var string 1 uI \$tag $end +$var wire 3 vI HdlSome $end +$upscope $end +$scope struct ready_op_index_5 $end +$var string 1 wI \$tag $end +$var wire 3 xI HdlSome $end +$upscope $end +$scope struct or_out_7 $end +$var string 1 yI \$tag $end +$var wire 3 zI HdlSome $end +$upscope $end +$scope struct or_out_8 $end +$var string 1 {I \$tag $end +$var wire 3 |I HdlSome $end +$upscope $end +$scope struct empty_op_index_6 $end +$var string 1 }I \$tag $end +$var wire 3 ~I HdlSome $end +$upscope $end +$scope struct ready_op_index_6 $end +$var string 1 !J \$tag $end +$var wire 3 "J HdlSome $end +$upscope $end +$scope struct empty_op_index_7 $end +$var string 1 #J \$tag $end +$var wire 3 $J HdlSome $end +$upscope $end +$scope struct ready_op_index_7 $end +$var string 1 %J \$tag $end +$var wire 3 &J HdlSome $end +$upscope $end +$scope struct or_out_9 $end +$var string 1 'J \$tag $end +$var wire 3 (J HdlSome $end +$upscope $end +$scope struct or_out_10 $end +$var string 1 )J \$tag $end +$var wire 3 *J HdlSome $end +$upscope $end +$scope struct or_out_11 $end +$var string 1 +J \$tag $end +$var wire 3 ,J HdlSome $end +$upscope $end +$scope struct or_out_12 $end +$var string 1 -J \$tag $end +$var wire 3 .J HdlSome $end +$upscope $end +$scope struct or_out_13 $end +$var string 1 /J \$tag $end +$var wire 3 0J HdlSome $end +$upscope $end +$scope struct or_out_14 $end +$var string 1 1J \$tag $end +$var wire 3 2J HdlSome $end +$upscope $end +$scope struct in_flight_ops_summary $end +$scope struct empty_op_index $end +$var string 1 3J \$tag $end +$var wire 3 4J HdlSome $end +$upscope $end +$scope struct ready_op_index $end +$var string 1 5J \$tag $end +$var wire 3 6J HdlSome $end +$upscope $end +$upscope $end +$var wire 1 7J is_some_out $end +$scope struct read_src_regs $end +$var wire 6 8J \[0] $end +$var wire 6 9J \[1] $end +$var wire 6 :J \[2] $end +$upscope $end +$scope struct read_src_values $end +$scope struct \[0] $end +$var wire 64 ;J int_fp $end +$scope struct flags $end +$var wire 1 J pwr_ov_x86_of $end +$var wire 1 ?J pwr_ov32_x86_df $end +$var wire 1 @J pwr_cr_lt_x86_sf $end +$var wire 1 AJ pwr_cr_gt_x86_pf $end +$var wire 1 BJ pwr_cr_eq_x86_zf $end +$var wire 1 CJ pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 DJ int_fp $end +$scope struct flags $end +$var wire 1 EJ pwr_ca_x86_cf $end +$var wire 1 FJ pwr_ca32_x86_af $end +$var wire 1 GJ pwr_ov_x86_of $end +$var wire 1 HJ pwr_ov32_x86_df $end +$var wire 1 IJ pwr_cr_lt_x86_sf $end +$var wire 1 JJ pwr_cr_gt_x86_pf $end +$var wire 1 KJ pwr_cr_eq_x86_zf $end +$var wire 1 LJ pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 MJ int_fp $end +$scope struct flags $end +$var wire 1 NJ pwr_ca_x86_cf $end +$var wire 1 OJ pwr_ca32_x86_af $end +$var wire 1 PJ pwr_ov_x86_of $end +$var wire 1 QJ pwr_ov32_x86_df $end +$var wire 1 RJ pwr_cr_lt_x86_sf $end +$var wire 1 SJ pwr_cr_gt_x86_pf $end +$var wire 1 TJ pwr_cr_eq_x86_zf $end +$var wire 1 UJ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct input_in_flight_op $end +$var string 1 VJ \$tag $end +$scope struct HdlSome $end +$var string 1 WJ state $end +$scope struct mop $end +$var string 1 XJ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 YJ prefix_pad $end +$scope struct dest $end +$var wire 4 ZJ value $end +$upscope $end +$scope struct src $end +$var wire 6 [J \[0] $end +$var wire 6 \J \[1] $end +$var wire 6 ]J \[2] $end +$upscope $end +$var wire 25 ^J imm_low $end +$var wire 1 _J imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 `J output_integer_mode $end +$upscope $end +$var wire 1 aJ invert_src0 $end +$var wire 1 bJ src1_is_carry_in $end +$var wire 1 cJ invert_carry_in $end +$var wire 1 dJ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 eJ prefix_pad $end +$scope struct dest $end +$var wire 4 fJ value $end +$upscope $end +$scope struct src $end +$var wire 6 gJ \[0] $end +$var wire 6 hJ \[1] $end +$var wire 6 iJ \[2] $end +$upscope $end +$var wire 25 jJ imm_low $end +$var wire 1 kJ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 lJ output_integer_mode $end +$upscope $end +$var wire 1 mJ invert_src0 $end +$var wire 1 nJ src1_is_carry_in $end +$var wire 1 oJ invert_carry_in $end +$var wire 1 pJ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 qJ prefix_pad $end +$scope struct dest $end +$var wire 4 rJ value $end +$upscope $end +$scope struct src $end +$var wire 6 sJ \[0] $end +$var wire 6 tJ \[1] $end +$var wire 6 uJ \[2] $end +$upscope $end +$var wire 25 vJ imm_low $end +$var wire 1 wJ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 xJ output_integer_mode $end +$upscope $end +$var wire 4 yJ lut $end +$upscope $end +$upscope $end +$var wire 64 zJ pc $end +$scope struct src_ready_flags $end +$var wire 1 {J \[0] $end +$var wire 1 |J \[1] $end +$var wire 1 }J \[2] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct firing_data $end +$var string 1 ~J \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 !K \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 "K prefix_pad $end +$scope struct dest $end +$var wire 4 #K value $end +$upscope $end +$scope struct src $end +$var wire 6 $K \[0] $end +$var wire 6 %K \[1] $end +$var wire 6 &K \[2] $end +$upscope $end +$var wire 25 'K imm_low $end +$var wire 1 (K imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 )K output_integer_mode $end +$upscope $end +$var wire 1 *K invert_src0 $end +$var wire 1 +K src1_is_carry_in $end +$var wire 1 ,K invert_carry_in $end +$var wire 1 -K add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 .K prefix_pad $end +$scope struct dest $end +$var wire 4 /K value $end +$upscope $end +$scope struct src $end +$var wire 6 0K \[0] $end +$var wire 6 1K \[1] $end +$var wire 6 2K \[2] $end +$upscope $end +$var wire 25 3K imm_low $end +$var wire 1 4K imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 5K output_integer_mode $end +$upscope $end +$var wire 1 6K invert_src0 $end +$var wire 1 7K src1_is_carry_in $end +$var wire 1 8K invert_carry_in $end +$var wire 1 9K add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 :K prefix_pad $end +$scope struct dest $end +$var wire 4 ;K value $end +$upscope $end +$scope struct src $end +$var wire 6 K \[2] $end +$upscope $end +$var wire 25 ?K imm_low $end +$var wire 1 @K imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 AK output_integer_mode $end +$upscope $end +$var wire 4 BK lut $end +$upscope $end +$upscope $end +$var wire 64 CK pc $end +$upscope $end +$upscope $end +$scope struct input_mop_src_regs $end +$var wire 6 DK \[0] $end +$var wire 6 EK \[1] $end +$var wire 6 FK \[2] $end +$upscope $end +$scope struct input_in_flight_op_src_ready_flags $end +$var wire 1 GK \[0] $end +$var wire 1 HK \[1] $end +$var wire 1 IK \[2] $end +$upscope $end +$scope struct dest_reg $end +$var wire 4 JK value $end +$upscope $end +$var wire 1 KK cmp_ne $end +$scope struct in_flight_op_next_state $end +$scope struct \[0] $end +$var string 1 LK \$tag $end +$var string 1 MK HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 NK \$tag $end +$var string 1 OK HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 PK \$tag $end +$var string 1 QK HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 RK \$tag $end +$var string 1 SK HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 TK \$tag $end +$var string 1 UK HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 VK \$tag $end +$var string 1 WK HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 XK \$tag $end +$var string 1 YK HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 ZK \$tag $end +$var string 1 [K HdlSome $end +$upscope $end +$upscope $end +$scope struct in_flight_op_next_src_ready_flags $end +$scope struct \[0] $end +$var wire 1 \K \[0] $end +$var wire 1 ]K \[1] $end +$var wire 1 ^K \[2] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 _K \[0] $end +$var wire 1 `K \[1] $end +$var wire 1 aK \[2] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 bK \[0] $end +$var wire 1 cK \[1] $end +$var wire 1 dK \[2] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 eK \[0] $end +$var wire 1 fK \[1] $end +$var wire 1 gK \[2] $end +$upscope $end +$scope struct \[4] $end +$var wire 1 hK \[0] $end +$var wire 1 iK \[1] $end +$var wire 1 jK \[2] $end +$upscope $end +$scope struct \[5] $end +$var wire 1 kK \[0] $end +$var wire 1 lK \[1] $end +$var wire 1 mK \[2] $end +$upscope $end +$scope struct \[6] $end +$var wire 1 nK \[0] $end +$var wire 1 oK \[1] $end +$var wire 1 pK \[2] $end +$upscope $end +$scope struct \[7] $end +$var wire 1 qK \[0] $end +$var wire 1 rK \[1] $end +$var wire 1 sK \[2] $end +$upscope $end +$upscope $end +$scope struct in_flight_op_canceling $end +$var wire 1 tK \[0] $end +$var wire 1 uK \[1] $end +$var wire 1 vK \[2] $end +$var wire 1 wK \[3] $end +$var wire 1 xK \[4] $end +$var wire 1 yK \[5] $end +$var wire 1 zK \[6] $end +$var wire 1 {K \[7] $end +$upscope $end +$scope struct in_flight_op_execute_starting $end +$var wire 1 |K \[0] $end +$var wire 1 }K \[1] $end +$var wire 1 ~K \[2] $end +$var wire 1 !L \[3] $end +$var wire 1 "L \[4] $end +$var wire 1 #L \[5] $end +$var wire 1 $L \[6] $end +$var wire 1 %L \[7] $end +$upscope $end +$scope struct in_flight_op_execute_ending $end +$var wire 1 &L \[0] $end +$var wire 1 'L \[1] $end +$var wire 1 (L \[2] $end +$var wire 1 )L \[3] $end +$var wire 1 *L \[4] $end +$var wire 1 +L \[5] $end +$var wire 1 ,L \[6] $end +$var wire 1 -L \[7] $end +$upscope $end +$scope struct dest_reg_2 $end +$var wire 4 .L value $end +$upscope $end +$scope struct in_flight_op_src_regs_0 $end +$var wire 6 /L \[0] $end +$var wire 6 0L \[1] $end +$var wire 6 1L \[2] $end +$upscope $end +$var wire 1 2L cmp_eq $end +$var wire 1 3L cmp_eq_2 $end +$scope struct firing_data_2 $end +$var string 1 4L \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 5L \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end $var string 0 6L prefix_pad $end $scope struct dest $end $var wire 4 7L value $end @@ -9601,11 +13193,11 @@ $upscope $end $var string 1 =L output_integer_mode $end $upscope $end $var wire 1 >L invert_src0 $end -$var wire 1 ?L invert_carry_in $end -$var wire 1 @L invert_carry_out $end +$var wire 1 ?L src1_is_carry_in $end +$var wire 1 @L invert_carry_in $end $var wire 1 AL add_pc $end $upscope $end -$scope struct Logical $end +$scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end $var string 0 BL prefix_pad $end @@ -9624,2826 +13216,494 @@ $upscope $end $upscope $end $var string 1 IL output_integer_mode $end $upscope $end -$var wire 4 JL lut $end +$var wire 1 JL invert_src0 $end +$var wire 1 KL src1_is_carry_in $end +$var wire 1 LL invert_carry_in $end +$var wire 1 ML add_pc $end $upscope $end -$upscope $end -$upscope $end -$var wire 1 KL ready $end -$upscope $end -$scope struct cancel_input $end -$var string 1 LL \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 ML value $end -$upscope $end -$upscope $end -$upscope $end -$scope struct output $end -$var string 1 NL \$tag $end -$scope struct HdlSome $end -$scope struct which $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 NL prefix_pad $end +$scope struct dest $end $var wire 4 OL value $end $upscope $end -$scope struct result $end -$var string 1 PL \$tag $end -$scope struct Completed $end -$scope struct value $end -$var wire 64 QL int_fp $end -$scope struct flags $end -$var wire 1 RL pwr_ca_x86_cf $end -$var wire 1 SL pwr_ca32_x86_af $end -$var wire 1 TL pwr_ov_x86_of $end -$var wire 1 UL pwr_ov32_x86_df $end -$var wire 1 VL pwr_cr_lt_x86_sf $end -$var wire 1 WL pwr_cr_gt_x86_pf $end -$var wire 1 XL pwr_cr_eq_x86_zf $end -$var wire 1 YL pwr_so $end -$upscope $end -$upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct execute_start $end -$scope struct data $end -$var string 1 ZL \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 [L \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 \L prefix_pad $end -$scope struct dest $end -$var wire 4 ]L value $end -$upscope $end $scope struct src $end -$var wire 6 ^L \[0] $end -$var wire 6 _L \[1] $end -$var wire 6 `L \[2] $end +$var wire 6 PL \[0] $end +$var wire 6 QL \[1] $end +$var wire 6 RL \[2] $end $upscope $end -$var wire 25 aL imm_low $end -$var wire 1 bL imm_sign $end +$var wire 25 SL imm_low $end +$var wire 1 TL imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 cL output_integer_mode $end +$var string 1 UL output_integer_mode $end $upscope $end -$var wire 1 dL invert_src0 $end -$var wire 1 eL invert_carry_in $end -$var wire 1 fL invert_carry_out $end -$var wire 1 gL add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 hL prefix_pad $end -$scope struct dest $end -$var wire 4 iL value $end -$upscope $end -$scope struct src $end -$var wire 6 jL \[0] $end -$var wire 6 kL \[1] $end -$var wire 6 lL \[2] $end -$upscope $end -$var wire 25 mL imm_low $end -$var wire 1 nL imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 oL output_integer_mode $end -$upscope $end -$var wire 1 pL invert_src0 $end -$var wire 1 qL invert_carry_in $end -$var wire 1 rL invert_carry_out $end -$var wire 1 sL add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 tL prefix_pad $end -$scope struct dest $end -$var wire 4 uL value $end -$upscope $end -$scope struct src $end -$var wire 6 vL \[0] $end -$var wire 6 wL \[1] $end -$var wire 6 xL \[2] $end -$upscope $end -$var wire 25 yL imm_low $end -$var wire 1 zL imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 {L output_integer_mode $end -$upscope $end -$var wire 4 |L lut $end +$var wire 4 VL lut $end $upscope $end $upscope $end +$var wire 64 WL pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 }L int_fp $end +$var wire 64 XL int_fp $end $scope struct flags $end -$var wire 1 ~L pwr_ca_x86_cf $end -$var wire 1 !M pwr_ca32_x86_af $end -$var wire 1 "M pwr_ov_x86_of $end -$var wire 1 #M pwr_ov32_x86_df $end -$var wire 1 $M pwr_cr_lt_x86_sf $end -$var wire 1 %M pwr_cr_gt_x86_pf $end -$var wire 1 &M pwr_cr_eq_x86_zf $end -$var wire 1 'M pwr_so $end +$var wire 1 YL pwr_ca_x86_cf $end +$var wire 1 ZL pwr_ca32_x86_af $end +$var wire 1 [L pwr_ov_x86_of $end +$var wire 1 \L pwr_ov32_x86_df $end +$var wire 1 ]L pwr_cr_lt_x86_sf $end +$var wire 1 ^L pwr_cr_gt_x86_pf $end +$var wire 1 _L pwr_cr_eq_x86_zf $end +$var wire 1 `L pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 (M int_fp $end +$var wire 64 aL int_fp $end $scope struct flags $end -$var wire 1 )M pwr_ca_x86_cf $end -$var wire 1 *M pwr_ca32_x86_af $end -$var wire 1 +M pwr_ov_x86_of $end -$var wire 1 ,M pwr_ov32_x86_df $end -$var wire 1 -M pwr_cr_lt_x86_sf $end -$var wire 1 .M pwr_cr_gt_x86_pf $end -$var wire 1 /M pwr_cr_eq_x86_zf $end -$var wire 1 0M pwr_so $end +$var wire 1 bL pwr_ca_x86_cf $end +$var wire 1 cL pwr_ca32_x86_af $end +$var wire 1 dL pwr_ov_x86_of $end +$var wire 1 eL pwr_ov32_x86_df $end +$var wire 1 fL pwr_cr_lt_x86_sf $end +$var wire 1 gL pwr_cr_gt_x86_pf $end +$var wire 1 hL pwr_cr_eq_x86_zf $end +$var wire 1 iL pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 1M int_fp $end +$var wire 64 jL int_fp $end $scope struct flags $end -$var wire 1 2M pwr_ca_x86_cf $end -$var wire 1 3M pwr_ca32_x86_af $end -$var wire 1 4M pwr_ov_x86_of $end -$var wire 1 5M pwr_ov32_x86_df $end -$var wire 1 6M pwr_cr_lt_x86_sf $end -$var wire 1 7M pwr_cr_gt_x86_pf $end -$var wire 1 8M pwr_cr_eq_x86_zf $end -$var wire 1 9M pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 :M ready $end -$upscope $end -$scope struct execute_end $end -$var string 1 ;M \$tag $end -$scope struct HdlSome $end -$scope struct unit_output $end -$scope struct which $end -$var wire 4 M int_fp $end -$scope struct flags $end -$var wire 1 ?M pwr_ca_x86_cf $end -$var wire 1 @M pwr_ca32_x86_af $end -$var wire 1 AM pwr_ov_x86_of $end -$var wire 1 BM pwr_ov32_x86_df $end -$var wire 1 CM pwr_cr_lt_x86_sf $end -$var wire 1 DM pwr_cr_gt_x86_pf $end -$var wire 1 EM pwr_cr_eq_x86_zf $end -$var wire 1 FM pwr_so $end -$upscope $end -$upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unit_base_2 $end -$scope struct cd $end -$var wire 1 t> clk $end -$var wire 1 u> rst $end -$upscope $end -$scope struct unit_to_reg_alloc $end -$scope struct unit_forwarding_info $end -$scope struct unit_output_writes $end -$scope struct \[0] $end -$var string 1 v> \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 w> value $end -$upscope $end -$scope struct value $end -$var wire 64 x> int_fp $end -$scope struct flags $end -$var wire 1 y> pwr_ca_x86_cf $end -$var wire 1 z> pwr_ca32_x86_af $end -$var wire 1 {> pwr_ov_x86_of $end -$var wire 1 |> pwr_ov32_x86_df $end -$var wire 1 }> pwr_cr_lt_x86_sf $end -$var wire 1 ~> pwr_cr_gt_x86_pf $end -$var wire 1 !? pwr_cr_eq_x86_zf $end -$var wire 1 "? pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var string 1 #? \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 $? value $end -$upscope $end -$scope struct value $end -$var wire 64 %? int_fp $end -$scope struct flags $end -$var wire 1 &? pwr_ca_x86_cf $end -$var wire 1 '? pwr_ca32_x86_af $end -$var wire 1 (? pwr_ov_x86_of $end -$var wire 1 )? pwr_ov32_x86_df $end -$var wire 1 *? pwr_cr_lt_x86_sf $end -$var wire 1 +? pwr_cr_gt_x86_pf $end -$var wire 1 ,? pwr_cr_eq_x86_zf $end -$var wire 1 -? pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$scope struct input_insn $end -$scope struct data $end -$var string 1 .? \$tag $end -$scope struct HdlSome $end -$var string 1 /? \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 0? prefix_pad $end -$scope struct dest $end -$var wire 4 1? value $end -$upscope $end -$scope struct src $end -$var wire 6 2? \[0] $end -$var wire 6 3? \[1] $end -$var wire 6 4? \[2] $end -$upscope $end -$var wire 25 5? imm_low $end -$var wire 1 6? imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 7? output_integer_mode $end -$upscope $end -$var wire 1 8? invert_src0 $end -$var wire 1 9? invert_carry_in $end -$var wire 1 :? invert_carry_out $end -$var wire 1 ;? add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ? \[0] $end -$var wire 6 ?? \[1] $end -$var wire 6 @? \[2] $end -$upscope $end -$var wire 25 A? imm_low $end -$var wire 1 B? imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 C? output_integer_mode $end -$upscope $end -$var wire 1 D? invert_src0 $end -$var wire 1 E? invert_carry_in $end -$var wire 1 F? invert_carry_out $end -$var wire 1 G? add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 H? prefix_pad $end -$scope struct dest $end -$var wire 4 I? value $end -$upscope $end -$scope struct src $end -$var wire 6 J? \[0] $end -$var wire 6 K? \[1] $end -$var wire 6 L? \[2] $end -$upscope $end -$var wire 25 M? imm_low $end -$var wire 1 N? imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 O? output_integer_mode $end -$upscope $end -$var wire 4 P? lut $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 Q? ready $end -$upscope $end -$scope struct cancel_input $end -$var string 1 R? \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 S? value $end -$upscope $end -$upscope $end -$upscope $end -$scope struct output $end -$var string 1 T? \$tag $end -$scope struct HdlSome $end -$scope struct which $end -$var wire 4 U? value $end -$upscope $end -$scope struct result $end -$var string 1 V? \$tag $end -$scope struct Completed $end -$scope struct value $end -$var wire 64 W? int_fp $end -$scope struct flags $end -$var wire 1 X? pwr_ca_x86_cf $end -$var wire 1 Y? pwr_ca32_x86_af $end -$var wire 1 Z? pwr_ov_x86_of $end -$var wire 1 [? pwr_ov32_x86_df $end -$var wire 1 \? pwr_cr_lt_x86_sf $end -$var wire 1 ]? pwr_cr_gt_x86_pf $end -$var wire 1 ^? pwr_cr_eq_x86_zf $end -$var wire 1 _? pwr_so $end -$upscope $end -$upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct execute_start $end -$scope struct data $end -$var string 1 `? \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 a? \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 b? prefix_pad $end -$scope struct dest $end -$var wire 4 c? value $end -$upscope $end -$scope struct src $end -$var wire 6 d? \[0] $end -$var wire 6 e? \[1] $end -$var wire 6 f? \[2] $end -$upscope $end -$var wire 25 g? imm_low $end -$var wire 1 h? imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 i? output_integer_mode $end -$upscope $end -$var wire 1 j? invert_src0 $end -$var wire 1 k? invert_carry_in $end -$var wire 1 l? invert_carry_out $end -$var wire 1 m? add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 n? prefix_pad $end -$scope struct dest $end -$var wire 4 o? value $end -$upscope $end -$scope struct src $end -$var wire 6 p? \[0] $end -$var wire 6 q? \[1] $end -$var wire 6 r? \[2] $end -$upscope $end -$var wire 25 s? imm_low $end -$var wire 1 t? imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 u? output_integer_mode $end -$upscope $end -$var wire 1 v? invert_src0 $end -$var wire 1 w? invert_carry_in $end -$var wire 1 x? invert_carry_out $end -$var wire 1 y? add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 z? prefix_pad $end -$scope struct dest $end -$var wire 4 {? value $end -$upscope $end -$scope struct src $end -$var wire 6 |? \[0] $end -$var wire 6 }? \[1] $end -$var wire 6 ~? \[2] $end -$upscope $end -$var wire 25 !@ imm_low $end -$var wire 1 "@ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 #@ output_integer_mode $end -$upscope $end -$var wire 4 $@ lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 %@ int_fp $end -$scope struct flags $end -$var wire 1 &@ pwr_ca_x86_cf $end -$var wire 1 '@ pwr_ca32_x86_af $end -$var wire 1 (@ pwr_ov_x86_of $end -$var wire 1 )@ pwr_ov32_x86_df $end -$var wire 1 *@ pwr_cr_lt_x86_sf $end -$var wire 1 +@ pwr_cr_gt_x86_pf $end -$var wire 1 ,@ pwr_cr_eq_x86_zf $end -$var wire 1 -@ pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 .@ int_fp $end -$scope struct flags $end -$var wire 1 /@ pwr_ca_x86_cf $end -$var wire 1 0@ pwr_ca32_x86_af $end -$var wire 1 1@ pwr_ov_x86_of $end -$var wire 1 2@ pwr_ov32_x86_df $end -$var wire 1 3@ pwr_cr_lt_x86_sf $end -$var wire 1 4@ pwr_cr_gt_x86_pf $end -$var wire 1 5@ pwr_cr_eq_x86_zf $end -$var wire 1 6@ pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 7@ int_fp $end -$scope struct flags $end -$var wire 1 8@ pwr_ca_x86_cf $end -$var wire 1 9@ pwr_ca32_x86_af $end -$var wire 1 :@ pwr_ov_x86_of $end -$var wire 1 ;@ pwr_ov32_x86_df $end -$var wire 1 <@ pwr_cr_lt_x86_sf $end -$var wire 1 =@ pwr_cr_gt_x86_pf $end -$var wire 1 >@ pwr_cr_eq_x86_zf $end -$var wire 1 ?@ pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 @@ ready $end -$upscope $end -$scope struct execute_end $end -$var string 1 A@ \$tag $end -$scope struct HdlSome $end -$scope struct unit_output $end -$scope struct which $end -$var wire 4 B@ value $end -$upscope $end -$scope struct result $end -$var string 1 C@ \$tag $end -$scope struct Completed $end -$scope struct value $end -$var wire 64 D@ int_fp $end -$scope struct flags $end -$var wire 1 E@ pwr_ca_x86_cf $end -$var wire 1 F@ pwr_ca32_x86_af $end -$var wire 1 G@ pwr_ov_x86_of $end -$var wire 1 H@ pwr_ov32_x86_df $end -$var wire 1 I@ pwr_cr_lt_x86_sf $end -$var wire 1 J@ pwr_cr_gt_x86_pf $end -$var wire 1 K@ pwr_cr_eq_x86_zf $end -$var wire 1 L@ pwr_so $end -$upscope $end -$upscope $end -$scope struct extra_out $end -$upscope $end -$upscope $end -$scope struct Trap $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct in_flight_ops $end -$scope struct \[0] $end -$var string 1 M@ \$tag $end -$scope struct HdlSome $end -$var string 1 N@ state $end -$scope struct mop $end -$var string 1 O@ \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 P@ prefix_pad $end -$scope struct dest $end -$var reg 4 Q@ value $end -$upscope $end -$scope struct src $end -$var reg 6 R@ \[0] $end -$var reg 6 S@ \[1] $end -$var reg 6 T@ \[2] $end -$upscope $end -$var reg 25 U@ imm_low $end -$var reg 1 V@ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 W@ output_integer_mode $end -$upscope $end -$var reg 1 X@ invert_src0 $end -$var reg 1 Y@ invert_carry_in $end -$var reg 1 Z@ invert_carry_out $end -$var reg 1 [@ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 \@ prefix_pad $end -$scope struct dest $end -$var reg 4 ]@ value $end -$upscope $end -$scope struct src $end -$var reg 6 ^@ \[0] $end -$var reg 6 _@ \[1] $end -$var reg 6 `@ \[2] $end -$upscope $end -$var reg 25 a@ imm_low $end -$var reg 1 b@ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 c@ output_integer_mode $end -$upscope $end -$var reg 1 d@ invert_src0 $end -$var reg 1 e@ invert_carry_in $end -$var reg 1 f@ invert_carry_out $end -$var reg 1 g@ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 h@ prefix_pad $end -$scope struct dest $end -$var reg 4 i@ value $end -$upscope $end -$scope struct src $end -$var reg 6 j@ \[0] $end -$var reg 6 k@ \[1] $end -$var reg 6 l@ \[2] $end -$upscope $end -$var reg 25 m@ imm_low $end -$var reg 1 n@ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 o@ output_integer_mode $end -$upscope $end -$var reg 4 p@ lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 q@ \[0] $end -$var reg 1 r@ \[1] $end -$var reg 1 s@ \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var string 1 t@ \$tag $end -$scope struct HdlSome $end -$var string 1 u@ state $end -$scope struct mop $end -$var string 1 v@ \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 w@ prefix_pad $end -$scope struct dest $end -$var reg 4 x@ value $end -$upscope $end -$scope struct src $end -$var reg 6 y@ \[0] $end -$var reg 6 z@ \[1] $end -$var reg 6 {@ \[2] $end -$upscope $end -$var reg 25 |@ imm_low $end -$var reg 1 }@ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ~@ output_integer_mode $end -$upscope $end -$var reg 1 !A invert_src0 $end -$var reg 1 "A invert_carry_in $end -$var reg 1 #A invert_carry_out $end -$var reg 1 $A add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 %A prefix_pad $end -$scope struct dest $end -$var reg 4 &A value $end -$upscope $end -$scope struct src $end -$var reg 6 'A \[0] $end -$var reg 6 (A \[1] $end -$var reg 6 )A \[2] $end -$upscope $end -$var reg 25 *A imm_low $end -$var reg 1 +A imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ,A output_integer_mode $end -$upscope $end -$var reg 1 -A invert_src0 $end -$var reg 1 .A invert_carry_in $end -$var reg 1 /A invert_carry_out $end -$var reg 1 0A add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 1A prefix_pad $end -$scope struct dest $end -$var reg 4 2A value $end -$upscope $end -$scope struct src $end -$var reg 6 3A \[0] $end -$var reg 6 4A \[1] $end -$var reg 6 5A \[2] $end -$upscope $end -$var reg 25 6A imm_low $end -$var reg 1 7A imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 8A output_integer_mode $end -$upscope $end -$var reg 4 9A lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 :A \[0] $end -$var reg 1 ;A \[1] $end -$var reg 1 A state $end -$scope struct mop $end -$var string 1 ?A \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 @A prefix_pad $end -$scope struct dest $end -$var reg 4 AA value $end -$upscope $end -$scope struct src $end -$var reg 6 BA \[0] $end -$var reg 6 CA \[1] $end -$var reg 6 DA \[2] $end -$upscope $end -$var reg 25 EA imm_low $end -$var reg 1 FA imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 GA output_integer_mode $end -$upscope $end -$var reg 1 HA invert_src0 $end -$var reg 1 IA invert_carry_in $end -$var reg 1 JA invert_carry_out $end -$var reg 1 KA add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 LA prefix_pad $end -$scope struct dest $end -$var reg 4 MA value $end -$upscope $end -$scope struct src $end -$var reg 6 NA \[0] $end -$var reg 6 OA \[1] $end -$var reg 6 PA \[2] $end -$upscope $end -$var reg 25 QA imm_low $end -$var reg 1 RA imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 SA output_integer_mode $end -$upscope $end -$var reg 1 TA invert_src0 $end -$var reg 1 UA invert_carry_in $end -$var reg 1 VA invert_carry_out $end -$var reg 1 WA add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 XA prefix_pad $end -$scope struct dest $end -$var reg 4 YA value $end -$upscope $end -$scope struct src $end -$var reg 6 ZA \[0] $end -$var reg 6 [A \[1] $end -$var reg 6 \A \[2] $end -$upscope $end -$var reg 25 ]A imm_low $end -$var reg 1 ^A imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 _A output_integer_mode $end -$upscope $end -$var reg 4 `A lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 aA \[0] $end -$var reg 1 bA \[1] $end -$var reg 1 cA \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[3] $end -$var string 1 dA \$tag $end -$scope struct HdlSome $end -$var string 1 eA state $end -$scope struct mop $end -$var string 1 fA \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 gA prefix_pad $end -$scope struct dest $end -$var reg 4 hA value $end -$upscope $end -$scope struct src $end -$var reg 6 iA \[0] $end -$var reg 6 jA \[1] $end -$var reg 6 kA \[2] $end -$upscope $end -$var reg 25 lA imm_low $end -$var reg 1 mA imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 nA output_integer_mode $end -$upscope $end -$var reg 1 oA invert_src0 $end -$var reg 1 pA invert_carry_in $end -$var reg 1 qA invert_carry_out $end -$var reg 1 rA add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 sA prefix_pad $end -$scope struct dest $end -$var reg 4 tA value $end -$upscope $end -$scope struct src $end -$var reg 6 uA \[0] $end -$var reg 6 vA \[1] $end -$var reg 6 wA \[2] $end -$upscope $end -$var reg 25 xA imm_low $end -$var reg 1 yA imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 zA output_integer_mode $end -$upscope $end -$var reg 1 {A invert_src0 $end -$var reg 1 |A invert_carry_in $end -$var reg 1 }A invert_carry_out $end -$var reg 1 ~A add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 !B prefix_pad $end -$scope struct dest $end -$var reg 4 "B value $end -$upscope $end -$scope struct src $end -$var reg 6 #B \[0] $end -$var reg 6 $B \[1] $end -$var reg 6 %B \[2] $end -$upscope $end -$var reg 25 &B imm_low $end -$var reg 1 'B imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 (B output_integer_mode $end -$upscope $end -$var reg 4 )B lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 *B \[0] $end -$var reg 1 +B \[1] $end -$var reg 1 ,B \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[4] $end -$var string 1 -B \$tag $end -$scope struct HdlSome $end -$var string 1 .B state $end -$scope struct mop $end -$var string 1 /B \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 0B prefix_pad $end -$scope struct dest $end -$var reg 4 1B value $end -$upscope $end -$scope struct src $end -$var reg 6 2B \[0] $end -$var reg 6 3B \[1] $end -$var reg 6 4B \[2] $end -$upscope $end -$var reg 25 5B imm_low $end -$var reg 1 6B imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 7B output_integer_mode $end -$upscope $end -$var reg 1 8B invert_src0 $end -$var reg 1 9B invert_carry_in $end -$var reg 1 :B invert_carry_out $end -$var reg 1 ;B add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 B \[0] $end -$var reg 6 ?B \[1] $end -$var reg 6 @B \[2] $end -$upscope $end -$var reg 25 AB imm_low $end -$var reg 1 BB imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 CB output_integer_mode $end -$upscope $end -$var reg 1 DB invert_src0 $end -$var reg 1 EB invert_carry_in $end -$var reg 1 FB invert_carry_out $end -$var reg 1 GB add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 HB prefix_pad $end -$scope struct dest $end -$var reg 4 IB value $end -$upscope $end -$scope struct src $end -$var reg 6 JB \[0] $end -$var reg 6 KB \[1] $end -$var reg 6 LB \[2] $end -$upscope $end -$var reg 25 MB imm_low $end -$var reg 1 NB imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 OB output_integer_mode $end -$upscope $end -$var reg 4 PB lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 QB \[0] $end -$var reg 1 RB \[1] $end -$var reg 1 SB \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[5] $end -$var string 1 TB \$tag $end -$scope struct HdlSome $end -$var string 1 UB state $end -$scope struct mop $end -$var string 1 VB \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 WB prefix_pad $end -$scope struct dest $end -$var reg 4 XB value $end -$upscope $end -$scope struct src $end -$var reg 6 YB \[0] $end -$var reg 6 ZB \[1] $end -$var reg 6 [B \[2] $end -$upscope $end -$var reg 25 \B imm_low $end -$var reg 1 ]B imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ^B output_integer_mode $end -$upscope $end -$var reg 1 _B invert_src0 $end -$var reg 1 `B invert_carry_in $end -$var reg 1 aB invert_carry_out $end -$var reg 1 bB add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 cB prefix_pad $end -$scope struct dest $end -$var reg 4 dB value $end -$upscope $end -$scope struct src $end -$var reg 6 eB \[0] $end -$var reg 6 fB \[1] $end -$var reg 6 gB \[2] $end -$upscope $end -$var reg 25 hB imm_low $end -$var reg 1 iB imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 jB output_integer_mode $end -$upscope $end -$var reg 1 kB invert_src0 $end -$var reg 1 lB invert_carry_in $end -$var reg 1 mB invert_carry_out $end -$var reg 1 nB add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 oB prefix_pad $end -$scope struct dest $end -$var reg 4 pB value $end -$upscope $end -$scope struct src $end -$var reg 6 qB \[0] $end -$var reg 6 rB \[1] $end -$var reg 6 sB \[2] $end -$upscope $end -$var reg 25 tB imm_low $end -$var reg 1 uB imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 vB output_integer_mode $end -$upscope $end -$var reg 4 wB lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 xB \[0] $end -$var reg 1 yB \[1] $end -$var reg 1 zB \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[6] $end -$var string 1 {B \$tag $end -$scope struct HdlSome $end -$var string 1 |B state $end -$scope struct mop $end -$var string 1 }B \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ~B prefix_pad $end -$scope struct dest $end -$var reg 4 !C value $end -$upscope $end -$scope struct src $end -$var reg 6 "C \[0] $end -$var reg 6 #C \[1] $end -$var reg 6 $C \[2] $end -$upscope $end -$var reg 25 %C imm_low $end -$var reg 1 &C imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 'C output_integer_mode $end -$upscope $end -$var reg 1 (C invert_src0 $end -$var reg 1 )C invert_carry_in $end -$var reg 1 *C invert_carry_out $end -$var reg 1 +C add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ,C prefix_pad $end -$scope struct dest $end -$var reg 4 -C value $end -$upscope $end -$scope struct src $end -$var reg 6 .C \[0] $end -$var reg 6 /C \[1] $end -$var reg 6 0C \[2] $end -$upscope $end -$var reg 25 1C imm_low $end -$var reg 1 2C imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 3C output_integer_mode $end -$upscope $end -$var reg 1 4C invert_src0 $end -$var reg 1 5C invert_carry_in $end -$var reg 1 6C invert_carry_out $end -$var reg 1 7C add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 8C prefix_pad $end -$scope struct dest $end -$var reg 4 9C value $end -$upscope $end -$scope struct src $end -$var reg 6 :C \[0] $end -$var reg 6 ;C \[1] $end -$var reg 6 C imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ?C output_integer_mode $end -$upscope $end -$var reg 4 @C lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 AC \[0] $end -$var reg 1 BC \[1] $end -$var reg 1 CC \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct \[7] $end -$var string 1 DC \$tag $end -$scope struct HdlSome $end -$var string 1 EC state $end -$scope struct mop $end -$var string 1 FC \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 GC prefix_pad $end -$scope struct dest $end -$var reg 4 HC value $end -$upscope $end -$scope struct src $end -$var reg 6 IC \[0] $end -$var reg 6 JC \[1] $end -$var reg 6 KC \[2] $end -$upscope $end -$var reg 25 LC imm_low $end -$var reg 1 MC imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 NC output_integer_mode $end -$upscope $end -$var reg 1 OC invert_src0 $end -$var reg 1 PC invert_carry_in $end -$var reg 1 QC invert_carry_out $end -$var reg 1 RC add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 SC prefix_pad $end -$scope struct dest $end -$var reg 4 TC value $end -$upscope $end -$scope struct src $end -$var reg 6 UC \[0] $end -$var reg 6 VC \[1] $end -$var reg 6 WC \[2] $end -$upscope $end -$var reg 25 XC imm_low $end -$var reg 1 YC imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ZC output_integer_mode $end -$upscope $end -$var reg 1 [C invert_src0 $end -$var reg 1 \C invert_carry_in $end -$var reg 1 ]C invert_carry_out $end -$var reg 1 ^C add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 _C prefix_pad $end -$scope struct dest $end -$var reg 4 `C value $end -$upscope $end -$scope struct src $end -$var reg 6 aC \[0] $end -$var reg 6 bC \[1] $end -$var reg 6 cC \[2] $end -$upscope $end -$var reg 25 dC imm_low $end -$var reg 1 eC imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 fC output_integer_mode $end -$upscope $end -$var reg 4 gC lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var reg 1 hC \[0] $end -$var reg 1 iC \[1] $end -$var reg 1 jC \[2] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct empty_op_index_0 $end -$var string 1 kC \$tag $end -$var wire 3 lC HdlSome $end -$upscope $end -$scope struct ready_op_index_0 $end -$var string 1 mC \$tag $end -$var wire 3 nC HdlSome $end -$upscope $end -$scope struct empty_op_index_1 $end -$var string 1 oC \$tag $end -$var wire 3 pC HdlSome $end -$upscope $end -$scope struct ready_op_index_1 $end -$var string 1 qC \$tag $end -$var wire 3 rC HdlSome $end -$upscope $end -$scope struct or_out $end -$var string 1 sC \$tag $end -$var wire 3 tC HdlSome $end -$upscope $end -$scope struct or_out_2 $end -$var string 1 uC \$tag $end -$var wire 3 vC HdlSome $end -$upscope $end -$scope struct empty_op_index_2 $end -$var string 1 wC \$tag $end -$var wire 3 xC HdlSome $end -$upscope $end -$scope struct ready_op_index_2 $end -$var string 1 yC \$tag $end -$var wire 3 zC HdlSome $end -$upscope $end -$scope struct empty_op_index_3 $end -$var string 1 {C \$tag $end -$var wire 3 |C HdlSome $end -$upscope $end -$scope struct ready_op_index_3 $end -$var string 1 }C \$tag $end -$var wire 3 ~C HdlSome $end -$upscope $end -$scope struct or_out_3 $end -$var string 1 !D \$tag $end -$var wire 3 "D HdlSome $end -$upscope $end -$scope struct or_out_4 $end -$var string 1 #D \$tag $end -$var wire 3 $D HdlSome $end -$upscope $end -$scope struct or_out_5 $end -$var string 1 %D \$tag $end -$var wire 3 &D HdlSome $end -$upscope $end -$scope struct or_out_6 $end -$var string 1 'D \$tag $end -$var wire 3 (D HdlSome $end -$upscope $end -$scope struct empty_op_index_4 $end -$var string 1 )D \$tag $end -$var wire 3 *D HdlSome $end -$upscope $end -$scope struct ready_op_index_4 $end -$var string 1 +D \$tag $end -$var wire 3 ,D HdlSome $end -$upscope $end -$scope struct empty_op_index_5 $end -$var string 1 -D \$tag $end -$var wire 3 .D HdlSome $end -$upscope $end -$scope struct ready_op_index_5 $end -$var string 1 /D \$tag $end -$var wire 3 0D HdlSome $end -$upscope $end -$scope struct or_out_7 $end -$var string 1 1D \$tag $end -$var wire 3 2D HdlSome $end -$upscope $end -$scope struct or_out_8 $end -$var string 1 3D \$tag $end -$var wire 3 4D HdlSome $end -$upscope $end -$scope struct empty_op_index_6 $end -$var string 1 5D \$tag $end -$var wire 3 6D HdlSome $end -$upscope $end -$scope struct ready_op_index_6 $end -$var string 1 7D \$tag $end -$var wire 3 8D HdlSome $end -$upscope $end -$scope struct empty_op_index_7 $end -$var string 1 9D \$tag $end -$var wire 3 :D HdlSome $end -$upscope $end -$scope struct ready_op_index_7 $end -$var string 1 ;D \$tag $end -$var wire 3 D HdlSome $end -$upscope $end -$scope struct or_out_10 $end -$var string 1 ?D \$tag $end -$var wire 3 @D HdlSome $end -$upscope $end -$scope struct or_out_11 $end -$var string 1 AD \$tag $end -$var wire 3 BD HdlSome $end -$upscope $end -$scope struct or_out_12 $end -$var string 1 CD \$tag $end -$var wire 3 DD HdlSome $end -$upscope $end -$scope struct or_out_13 $end -$var string 1 ED \$tag $end -$var wire 3 FD HdlSome $end -$upscope $end -$scope struct or_out_14 $end -$var string 1 GD \$tag $end -$var wire 3 HD HdlSome $end -$upscope $end -$scope struct in_flight_ops_summary $end -$scope struct empty_op_index $end -$var string 1 ID \$tag $end -$var wire 3 JD HdlSome $end -$upscope $end -$scope struct ready_op_index $end -$var string 1 KD \$tag $end -$var wire 3 LD HdlSome $end -$upscope $end -$upscope $end -$var wire 1 MD is_some_out $end -$scope struct input_in_flight_op $end -$var string 1 ND \$tag $end -$scope struct HdlSome $end -$var string 1 OD state $end -$scope struct mop $end -$var string 1 PD \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 QD prefix_pad $end -$scope struct dest $end -$var wire 4 RD value $end -$upscope $end -$scope struct src $end -$var wire 6 SD \[0] $end -$var wire 6 TD \[1] $end -$var wire 6 UD \[2] $end -$upscope $end -$var wire 25 VD imm_low $end -$var wire 1 WD imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 XD output_integer_mode $end -$upscope $end -$var wire 1 YD invert_src0 $end -$var wire 1 ZD invert_carry_in $end -$var wire 1 [D invert_carry_out $end -$var wire 1 \D add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ]D prefix_pad $end -$scope struct dest $end -$var wire 4 ^D value $end -$upscope $end -$scope struct src $end -$var wire 6 _D \[0] $end -$var wire 6 `D \[1] $end -$var wire 6 aD \[2] $end -$upscope $end -$var wire 25 bD imm_low $end -$var wire 1 cD imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 dD output_integer_mode $end -$upscope $end -$var wire 1 eD invert_src0 $end -$var wire 1 fD invert_carry_in $end -$var wire 1 gD invert_carry_out $end -$var wire 1 hD add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 iD prefix_pad $end -$scope struct dest $end -$var wire 4 jD value $end -$upscope $end -$scope struct src $end -$var wire 6 kD \[0] $end -$var wire 6 lD \[1] $end -$var wire 6 mD \[2] $end -$upscope $end -$var wire 25 nD imm_low $end -$var wire 1 oD imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 pD output_integer_mode $end -$upscope $end -$var wire 4 qD lut $end -$upscope $end -$upscope $end -$scope struct src_ready_flags $end -$var wire 1 rD \[0] $end -$var wire 1 sD \[1] $end -$var wire 1 tD \[2] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct firing_data $end -$var string 1 uD \$tag $end -$scope struct HdlSome $end -$var string 1 vD \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 wD prefix_pad $end -$scope struct dest $end -$var wire 4 xD value $end -$upscope $end -$scope struct src $end -$var wire 6 yD \[0] $end -$var wire 6 zD \[1] $end -$var wire 6 {D \[2] $end -$upscope $end -$var wire 25 |D imm_low $end -$var wire 1 }D imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ~D output_integer_mode $end -$upscope $end -$var wire 1 !E invert_src0 $end -$var wire 1 "E invert_carry_in $end -$var wire 1 #E invert_carry_out $end -$var wire 1 $E add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 %E prefix_pad $end -$scope struct dest $end -$var wire 4 &E value $end -$upscope $end -$scope struct src $end -$var wire 6 'E \[0] $end -$var wire 6 (E \[1] $end -$var wire 6 )E \[2] $end -$upscope $end -$var wire 25 *E imm_low $end -$var wire 1 +E imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ,E output_integer_mode $end -$upscope $end -$var wire 1 -E invert_src0 $end -$var wire 1 .E invert_carry_in $end -$var wire 1 /E invert_carry_out $end -$var wire 1 0E add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 1E prefix_pad $end -$scope struct dest $end -$var wire 4 2E value $end -$upscope $end -$scope struct src $end -$var wire 6 3E \[0] $end -$var wire 6 4E \[1] $end -$var wire 6 5E \[2] $end -$upscope $end -$var wire 25 6E imm_low $end -$var wire 1 7E imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 8E output_integer_mode $end -$upscope $end -$var wire 4 9E lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct input_mop_src_regs $end -$var wire 6 :E \[0] $end -$var wire 6 ;E \[1] $end -$var wire 6 E \[1] $end -$var wire 1 ?E \[2] $end -$upscope $end -$scope struct dest_reg $end -$var wire 4 @E value $end -$upscope $end -$var wire 1 AE cmp_ne $end -$scope struct in_flight_op_next_state $end -$scope struct \[0] $end -$var string 1 BE \$tag $end -$var string 1 CE HdlSome $end -$upscope $end -$scope struct \[1] $end -$var string 1 DE \$tag $end -$var string 1 EE HdlSome $end -$upscope $end -$scope struct \[2] $end -$var string 1 FE \$tag $end -$var string 1 GE HdlSome $end -$upscope $end -$scope struct \[3] $end -$var string 1 HE \$tag $end -$var string 1 IE HdlSome $end -$upscope $end -$scope struct \[4] $end -$var string 1 JE \$tag $end -$var string 1 KE HdlSome $end -$upscope $end -$scope struct \[5] $end -$var string 1 LE \$tag $end -$var string 1 ME HdlSome $end -$upscope $end -$scope struct \[6] $end -$var string 1 NE \$tag $end -$var string 1 OE HdlSome $end -$upscope $end -$scope struct \[7] $end -$var string 1 PE \$tag $end -$var string 1 QE HdlSome $end -$upscope $end -$upscope $end -$scope struct in_flight_op_next_src_ready_flags $end -$scope struct \[0] $end -$var wire 1 RE \[0] $end -$var wire 1 SE \[1] $end -$var wire 1 TE \[2] $end -$upscope $end -$scope struct \[1] $end -$var wire 1 UE \[0] $end -$var wire 1 VE \[1] $end -$var wire 1 WE \[2] $end -$upscope $end -$scope struct \[2] $end -$var wire 1 XE \[0] $end -$var wire 1 YE \[1] $end -$var wire 1 ZE \[2] $end -$upscope $end -$scope struct \[3] $end -$var wire 1 [E \[0] $end -$var wire 1 \E \[1] $end -$var wire 1 ]E \[2] $end -$upscope $end -$scope struct \[4] $end -$var wire 1 ^E \[0] $end -$var wire 1 _E \[1] $end -$var wire 1 `E \[2] $end -$upscope $end -$scope struct \[5] $end -$var wire 1 aE \[0] $end -$var wire 1 bE \[1] $end -$var wire 1 cE \[2] $end -$upscope $end -$scope struct \[6] $end -$var wire 1 dE \[0] $end -$var wire 1 eE \[1] $end -$var wire 1 fE \[2] $end -$upscope $end -$scope struct \[7] $end -$var wire 1 gE \[0] $end -$var wire 1 hE \[1] $end -$var wire 1 iE \[2] $end -$upscope $end -$upscope $end -$scope struct in_flight_op_canceling $end -$var wire 1 jE \[0] $end -$var wire 1 kE \[1] $end -$var wire 1 lE \[2] $end -$var wire 1 mE \[3] $end -$var wire 1 nE \[4] $end -$var wire 1 oE \[5] $end -$var wire 1 pE \[6] $end -$var wire 1 qE \[7] $end -$upscope $end -$scope struct in_flight_op_execute_starting $end -$var wire 1 rE \[0] $end -$var wire 1 sE \[1] $end -$var wire 1 tE \[2] $end -$var wire 1 uE \[3] $end -$var wire 1 vE \[4] $end -$var wire 1 wE \[5] $end -$var wire 1 xE \[6] $end -$var wire 1 yE \[7] $end -$upscope $end -$scope struct in_flight_op_execute_ending $end -$var wire 1 zE \[0] $end -$var wire 1 {E \[1] $end -$var wire 1 |E \[2] $end -$var wire 1 }E \[3] $end -$var wire 1 ~E \[4] $end -$var wire 1 !F \[5] $end -$var wire 1 "F \[6] $end -$var wire 1 #F \[7] $end -$upscope $end -$scope struct dest_reg_2 $end -$var wire 4 $F value $end -$upscope $end -$scope struct in_flight_op_src_regs_0 $end -$var wire 6 %F \[0] $end -$var wire 6 &F \[1] $end -$var wire 6 'F \[2] $end -$upscope $end -$var wire 1 (F cmp_eq $end -$scope struct firing_data_2 $end -$var string 1 )F \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 *F \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 +F prefix_pad $end -$scope struct dest $end -$var wire 4 ,F value $end -$upscope $end -$scope struct src $end -$var wire 6 -F \[0] $end -$var wire 6 .F \[1] $end -$var wire 6 /F \[2] $end -$upscope $end -$var wire 25 0F imm_low $end -$var wire 1 1F imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 2F output_integer_mode $end -$upscope $end -$var wire 1 3F invert_src0 $end -$var wire 1 4F invert_carry_in $end -$var wire 1 5F invert_carry_out $end -$var wire 1 6F add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 7F prefix_pad $end -$scope struct dest $end -$var wire 4 8F value $end -$upscope $end -$scope struct src $end -$var wire 6 9F \[0] $end -$var wire 6 :F \[1] $end -$var wire 6 ;F \[2] $end -$upscope $end -$var wire 25 F output_integer_mode $end -$upscope $end -$var wire 1 ?F invert_src0 $end -$var wire 1 @F invert_carry_in $end -$var wire 1 AF invert_carry_out $end -$var wire 1 BF add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 CF prefix_pad $end -$scope struct dest $end -$var wire 4 DF value $end -$upscope $end -$scope struct src $end -$var wire 6 EF \[0] $end -$var wire 6 FF \[1] $end -$var wire 6 GF \[2] $end -$upscope $end -$var wire 25 HF imm_low $end -$var wire 1 IF imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 JF output_integer_mode $end -$upscope $end -$var wire 4 KF lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 LF int_fp $end -$scope struct flags $end -$var wire 1 MF pwr_ca_x86_cf $end -$var wire 1 NF pwr_ca32_x86_af $end -$var wire 1 OF pwr_ov_x86_of $end -$var wire 1 PF pwr_ov32_x86_df $end -$var wire 1 QF pwr_cr_lt_x86_sf $end -$var wire 1 RF pwr_cr_gt_x86_pf $end -$var wire 1 SF pwr_cr_eq_x86_zf $end -$var wire 1 TF pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 UF int_fp $end -$scope struct flags $end -$var wire 1 VF pwr_ca_x86_cf $end -$var wire 1 WF pwr_ca32_x86_af $end -$var wire 1 XF pwr_ov_x86_of $end -$var wire 1 YF pwr_ov32_x86_df $end -$var wire 1 ZF pwr_cr_lt_x86_sf $end -$var wire 1 [F pwr_cr_gt_x86_pf $end -$var wire 1 \F pwr_cr_eq_x86_zf $end -$var wire 1 ]F pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 ^F int_fp $end -$scope struct flags $end -$var wire 1 _F pwr_ca_x86_cf $end -$var wire 1 `F pwr_ca32_x86_af $end -$var wire 1 aF pwr_ov_x86_of $end -$var wire 1 bF pwr_ov32_x86_df $end -$var wire 1 cF pwr_cr_lt_x86_sf $end -$var wire 1 dF pwr_cr_gt_x86_pf $end -$var wire 1 eF pwr_cr_eq_x86_zf $end -$var wire 1 fF pwr_so $end +$var wire 1 kL pwr_ca_x86_cf $end +$var wire 1 lL pwr_ca32_x86_af $end +$var wire 1 mL pwr_ov_x86_of $end +$var wire 1 nL pwr_ov32_x86_df $end +$var wire 1 oL pwr_cr_lt_x86_sf $end +$var wire 1 pL pwr_cr_gt_x86_pf $end +$var wire 1 qL pwr_cr_eq_x86_zf $end +$var wire 1 rL pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_3 $end -$var wire 4 gF value $end +$var wire 4 sL value $end $upscope $end $scope struct dest_reg_4 $end -$var wire 4 hF value $end +$var wire 4 tL value $end $upscope $end $scope struct in_flight_op_src_regs_1 $end -$var wire 6 iF \[0] $end -$var wire 6 jF \[1] $end -$var wire 6 kF \[2] $end +$var wire 6 uL \[0] $end +$var wire 6 vL \[1] $end +$var wire 6 wL \[2] $end $upscope $end -$var wire 1 lF cmp_eq_2 $end +$var wire 1 xL cmp_eq_3 $end +$var wire 1 yL cmp_eq_4 $end $scope struct firing_data_3 $end -$var string 1 mF \$tag $end +$var string 1 zL \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 nF \$tag $end +$var string 1 {L \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 oF prefix_pad $end +$var string 0 |L prefix_pad $end $scope struct dest $end -$var wire 4 pF value $end +$var wire 4 }L value $end $upscope $end $scope struct src $end -$var wire 6 qF \[0] $end -$var wire 6 rF \[1] $end -$var wire 6 sF \[2] $end +$var wire 6 ~L \[0] $end +$var wire 6 !M \[1] $end +$var wire 6 "M \[2] $end $upscope $end -$var wire 25 tF imm_low $end -$var wire 1 uF imm_sign $end +$var wire 25 #M imm_low $end +$var wire 1 $M imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 vF output_integer_mode $end +$var string 1 %M output_integer_mode $end $upscope $end -$var wire 1 wF invert_src0 $end -$var wire 1 xF invert_carry_in $end -$var wire 1 yF invert_carry_out $end -$var wire 1 zF add_pc $end +$var wire 1 &M invert_src0 $end +$var wire 1 'M src1_is_carry_in $end +$var wire 1 (M invert_carry_in $end +$var wire 1 )M add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 {F prefix_pad $end +$var string 0 *M prefix_pad $end $scope struct dest $end -$var wire 4 |F value $end +$var wire 4 +M value $end $upscope $end $scope struct src $end -$var wire 6 }F \[0] $end -$var wire 6 ~F \[1] $end -$var wire 6 !G \[2] $end +$var wire 6 ,M \[0] $end +$var wire 6 -M \[1] $end +$var wire 6 .M \[2] $end $upscope $end -$var wire 25 "G imm_low $end -$var wire 1 #G imm_sign $end +$var wire 25 /M imm_low $end +$var wire 1 0M imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 $G output_integer_mode $end +$var string 1 1M output_integer_mode $end $upscope $end -$var wire 1 %G invert_src0 $end -$var wire 1 &G invert_carry_in $end -$var wire 1 'G invert_carry_out $end -$var wire 1 (G add_pc $end +$var wire 1 2M invert_src0 $end +$var wire 1 3M src1_is_carry_in $end +$var wire 1 4M invert_carry_in $end +$var wire 1 5M add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 )G prefix_pad $end +$var string 0 6M prefix_pad $end $scope struct dest $end -$var wire 4 *G value $end +$var wire 4 7M value $end $upscope $end $scope struct src $end -$var wire 6 +G \[0] $end -$var wire 6 ,G \[1] $end -$var wire 6 -G \[2] $end +$var wire 6 8M \[0] $end +$var wire 6 9M \[1] $end +$var wire 6 :M \[2] $end $upscope $end -$var wire 25 .G imm_low $end -$var wire 1 /G imm_sign $end +$var wire 25 ;M imm_low $end +$var wire 1 M lut $end $upscope $end $upscope $end +$var wire 64 ?M pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 2G int_fp $end +$var wire 64 @M int_fp $end $scope struct flags $end -$var wire 1 3G pwr_ca_x86_cf $end -$var wire 1 4G pwr_ca32_x86_af $end -$var wire 1 5G pwr_ov_x86_of $end -$var wire 1 6G pwr_ov32_x86_df $end -$var wire 1 7G pwr_cr_lt_x86_sf $end -$var wire 1 8G pwr_cr_gt_x86_pf $end -$var wire 1 9G pwr_cr_eq_x86_zf $end -$var wire 1 :G pwr_so $end +$var wire 1 AM pwr_ca_x86_cf $end +$var wire 1 BM pwr_ca32_x86_af $end +$var wire 1 CM pwr_ov_x86_of $end +$var wire 1 DM pwr_ov32_x86_df $end +$var wire 1 EM pwr_cr_lt_x86_sf $end +$var wire 1 FM pwr_cr_gt_x86_pf $end +$var wire 1 GM pwr_cr_eq_x86_zf $end +$var wire 1 HM pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 ;G int_fp $end +$var wire 64 IM int_fp $end $scope struct flags $end -$var wire 1 G pwr_ov_x86_of $end -$var wire 1 ?G pwr_ov32_x86_df $end -$var wire 1 @G pwr_cr_lt_x86_sf $end -$var wire 1 AG pwr_cr_gt_x86_pf $end -$var wire 1 BG pwr_cr_eq_x86_zf $end -$var wire 1 CG pwr_so $end +$var wire 1 JM pwr_ca_x86_cf $end +$var wire 1 KM pwr_ca32_x86_af $end +$var wire 1 LM pwr_ov_x86_of $end +$var wire 1 MM pwr_ov32_x86_df $end +$var wire 1 NM pwr_cr_lt_x86_sf $end +$var wire 1 OM pwr_cr_gt_x86_pf $end +$var wire 1 PM pwr_cr_eq_x86_zf $end +$var wire 1 QM pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 DG int_fp $end +$var wire 64 RM int_fp $end $scope struct flags $end -$var wire 1 EG pwr_ca_x86_cf $end -$var wire 1 FG pwr_ca32_x86_af $end -$var wire 1 GG pwr_ov_x86_of $end -$var wire 1 HG pwr_ov32_x86_df $end -$var wire 1 IG pwr_cr_lt_x86_sf $end -$var wire 1 JG pwr_cr_gt_x86_pf $end -$var wire 1 KG pwr_cr_eq_x86_zf $end -$var wire 1 LG pwr_so $end +$var wire 1 SM pwr_ca_x86_cf $end +$var wire 1 TM pwr_ca32_x86_af $end +$var wire 1 UM pwr_ov_x86_of $end +$var wire 1 VM pwr_ov32_x86_df $end +$var wire 1 WM pwr_cr_lt_x86_sf $end +$var wire 1 XM pwr_cr_gt_x86_pf $end +$var wire 1 YM pwr_cr_eq_x86_zf $end +$var wire 1 ZM pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_5 $end -$var wire 4 MG value $end +$var wire 4 [M value $end $upscope $end $scope struct dest_reg_6 $end -$var wire 4 NG value $end +$var wire 4 \M value $end $upscope $end $scope struct in_flight_op_src_regs_2 $end -$var wire 6 OG \[0] $end -$var wire 6 PG \[1] $end -$var wire 6 QG \[2] $end +$var wire 6 ]M \[0] $end +$var wire 6 ^M \[1] $end +$var wire 6 _M \[2] $end $upscope $end -$var wire 1 RG cmp_eq_3 $end +$var wire 1 `M cmp_eq_5 $end +$var wire 1 aM cmp_eq_6 $end $scope struct firing_data_4 $end -$var string 1 SG \$tag $end +$var string 1 bM \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 TG \$tag $end +$var string 1 cM \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 UG prefix_pad $end +$var string 0 dM prefix_pad $end $scope struct dest $end -$var wire 4 VG value $end +$var wire 4 eM value $end $upscope $end $scope struct src $end -$var wire 6 WG \[0] $end -$var wire 6 XG \[1] $end -$var wire 6 YG \[2] $end +$var wire 6 fM \[0] $end +$var wire 6 gM \[1] $end +$var wire 6 hM \[2] $end $upscope $end -$var wire 25 ZG imm_low $end -$var wire 1 [G imm_sign $end +$var wire 25 iM imm_low $end +$var wire 1 jM imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 \G output_integer_mode $end +$var string 1 kM output_integer_mode $end $upscope $end -$var wire 1 ]G invert_src0 $end -$var wire 1 ^G invert_carry_in $end -$var wire 1 _G invert_carry_out $end -$var wire 1 `G add_pc $end +$var wire 1 lM invert_src0 $end +$var wire 1 mM src1_is_carry_in $end +$var wire 1 nM invert_carry_in $end +$var wire 1 oM add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 aG prefix_pad $end +$var string 0 pM prefix_pad $end $scope struct dest $end -$var wire 4 bG value $end +$var wire 4 qM value $end $upscope $end $scope struct src $end -$var wire 6 cG \[0] $end -$var wire 6 dG \[1] $end -$var wire 6 eG \[2] $end +$var wire 6 rM \[0] $end +$var wire 6 sM \[1] $end +$var wire 6 tM \[2] $end $upscope $end -$var wire 25 fG imm_low $end -$var wire 1 gG imm_sign $end +$var wire 25 uM imm_low $end +$var wire 1 vM imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 hG output_integer_mode $end +$var string 1 wM output_integer_mode $end $upscope $end -$var wire 1 iG invert_src0 $end -$var wire 1 jG invert_carry_in $end -$var wire 1 kG invert_carry_out $end -$var wire 1 lG add_pc $end +$var wire 1 xM invert_src0 $end +$var wire 1 yM src1_is_carry_in $end +$var wire 1 zM invert_carry_in $end +$var wire 1 {M add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 mG prefix_pad $end +$var string 0 |M prefix_pad $end $scope struct dest $end -$var wire 4 nG value $end +$var wire 4 }M value $end $upscope $end $scope struct src $end -$var wire 6 oG \[0] $end -$var wire 6 pG \[1] $end -$var wire 6 qG \[2] $end +$var wire 6 ~M \[0] $end +$var wire 6 !N \[1] $end +$var wire 6 "N \[2] $end $upscope $end -$var wire 25 rG imm_low $end -$var wire 1 sG imm_sign $end +$var wire 25 #N imm_low $end +$var wire 1 $N imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 tG output_integer_mode $end +$var string 1 %N output_integer_mode $end $upscope $end -$var wire 4 uG lut $end +$var wire 4 &N lut $end $upscope $end $upscope $end +$var wire 64 'N pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 vG int_fp $end +$var wire 64 (N int_fp $end $scope struct flags $end -$var wire 1 wG pwr_ca_x86_cf $end -$var wire 1 xG pwr_ca32_x86_af $end -$var wire 1 yG pwr_ov_x86_of $end -$var wire 1 zG pwr_ov32_x86_df $end -$var wire 1 {G pwr_cr_lt_x86_sf $end -$var wire 1 |G pwr_cr_gt_x86_pf $end -$var wire 1 }G pwr_cr_eq_x86_zf $end -$var wire 1 ~G pwr_so $end +$var wire 1 )N pwr_ca_x86_cf $end +$var wire 1 *N pwr_ca32_x86_af $end +$var wire 1 +N pwr_ov_x86_of $end +$var wire 1 ,N pwr_ov32_x86_df $end +$var wire 1 -N pwr_cr_lt_x86_sf $end +$var wire 1 .N pwr_cr_gt_x86_pf $end +$var wire 1 /N pwr_cr_eq_x86_zf $end +$var wire 1 0N pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 !H int_fp $end +$var wire 64 1N int_fp $end $scope struct flags $end -$var wire 1 "H pwr_ca_x86_cf $end -$var wire 1 #H pwr_ca32_x86_af $end -$var wire 1 $H pwr_ov_x86_of $end -$var wire 1 %H pwr_ov32_x86_df $end -$var wire 1 &H pwr_cr_lt_x86_sf $end -$var wire 1 'H pwr_cr_gt_x86_pf $end -$var wire 1 (H pwr_cr_eq_x86_zf $end -$var wire 1 )H pwr_so $end +$var wire 1 2N pwr_ca_x86_cf $end +$var wire 1 3N pwr_ca32_x86_af $end +$var wire 1 4N pwr_ov_x86_of $end +$var wire 1 5N pwr_ov32_x86_df $end +$var wire 1 6N pwr_cr_lt_x86_sf $end +$var wire 1 7N pwr_cr_gt_x86_pf $end +$var wire 1 8N pwr_cr_eq_x86_zf $end +$var wire 1 9N pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 *H int_fp $end +$var wire 64 :N int_fp $end $scope struct flags $end -$var wire 1 +H pwr_ca_x86_cf $end -$var wire 1 ,H pwr_ca32_x86_af $end -$var wire 1 -H pwr_ov_x86_of $end -$var wire 1 .H pwr_ov32_x86_df $end -$var wire 1 /H pwr_cr_lt_x86_sf $end -$var wire 1 0H pwr_cr_gt_x86_pf $end -$var wire 1 1H pwr_cr_eq_x86_zf $end -$var wire 1 2H pwr_so $end +$var wire 1 ;N pwr_ca_x86_cf $end +$var wire 1 N pwr_ov32_x86_df $end +$var wire 1 ?N pwr_cr_lt_x86_sf $end +$var wire 1 @N pwr_cr_gt_x86_pf $end +$var wire 1 AN pwr_cr_eq_x86_zf $end +$var wire 1 BN pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_7 $end -$var wire 4 3H value $end +$var wire 4 CN value $end $upscope $end $scope struct dest_reg_8 $end -$var wire 4 4H value $end +$var wire 4 DN value $end $upscope $end $scope struct in_flight_op_src_regs_3 $end -$var wire 6 5H \[0] $end -$var wire 6 6H \[1] $end -$var wire 6 7H \[2] $end +$var wire 6 EN \[0] $end +$var wire 6 FN \[1] $end +$var wire 6 GN \[2] $end $upscope $end -$var wire 1 8H cmp_eq_4 $end +$var wire 1 HN cmp_eq_7 $end +$var wire 1 IN cmp_eq_8 $end $scope struct firing_data_5 $end -$var string 1 9H \$tag $end +$var string 1 JN \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 :H \$tag $end +$var string 1 KN \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 ;H prefix_pad $end +$var string 0 LN prefix_pad $end $scope struct dest $end -$var wire 4 H \[1] $end -$var wire 6 ?H \[2] $end +$var wire 6 NN \[0] $end +$var wire 6 ON \[1] $end +$var wire 6 PN \[2] $end $upscope $end -$var wire 25 @H imm_low $end -$var wire 1 AH imm_sign $end +$var wire 25 QN imm_low $end +$var wire 1 RN imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 BH output_integer_mode $end +$var string 1 SN output_integer_mode $end $upscope $end -$var wire 1 CH invert_src0 $end -$var wire 1 DH invert_carry_in $end -$var wire 1 EH invert_carry_out $end -$var wire 1 FH add_pc $end +$var wire 1 TN invert_src0 $end +$var wire 1 UN src1_is_carry_in $end +$var wire 1 VN invert_carry_in $end +$var wire 1 WN add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 GH prefix_pad $end +$var string 0 XN prefix_pad $end $scope struct dest $end -$var wire 4 HH value $end +$var wire 4 YN value $end $upscope $end $scope struct src $end -$var wire 6 IH \[0] $end -$var wire 6 JH \[1] $end -$var wire 6 KH \[2] $end +$var wire 6 ZN \[0] $end +$var wire 6 [N \[1] $end +$var wire 6 \N \[2] $end $upscope $end -$var wire 25 LH imm_low $end -$var wire 1 MH imm_sign $end +$var wire 25 ]N imm_low $end +$var wire 1 ^N imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 NH output_integer_mode $end +$var string 1 _N output_integer_mode $end $upscope $end -$var wire 1 OH invert_src0 $end -$var wire 1 PH invert_carry_in $end -$var wire 1 QH invert_carry_out $end -$var wire 1 RH add_pc $end +$var wire 1 `N invert_src0 $end +$var wire 1 aN src1_is_carry_in $end +$var wire 1 bN invert_carry_in $end +$var wire 1 cN add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 SH prefix_pad $end +$var string 0 dN prefix_pad $end $scope struct dest $end -$var wire 4 TH value $end +$var wire 4 eN value $end $upscope $end $scope struct src $end -$var wire 6 UH \[0] $end -$var wire 6 VH \[1] $end -$var wire 6 WH \[2] $end +$var wire 6 fN \[0] $end +$var wire 6 gN \[1] $end +$var wire 6 hN \[2] $end $upscope $end -$var wire 25 XH imm_low $end -$var wire 1 YH imm_sign $end +$var wire 25 iN imm_low $end +$var wire 1 jN imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 ZH output_integer_mode $end +$var string 1 kN output_integer_mode $end $upscope $end -$var wire 4 [H lut $end +$var wire 4 lN lut $end $upscope $end $upscope $end +$var wire 64 mN pc $end $scope struct src_values $end $scope struct \[0] $end -$var wire 64 \H int_fp $end +$var wire 64 nN int_fp $end $scope struct flags $end -$var wire 1 ]H pwr_ca_x86_cf $end -$var wire 1 ^H pwr_ca32_x86_af $end -$var wire 1 _H pwr_ov_x86_of $end -$var wire 1 `H pwr_ov32_x86_df $end -$var wire 1 aH pwr_cr_lt_x86_sf $end -$var wire 1 bH pwr_cr_gt_x86_pf $end -$var wire 1 cH pwr_cr_eq_x86_zf $end -$var wire 1 dH pwr_so $end +$var wire 1 oN pwr_ca_x86_cf $end +$var wire 1 pN pwr_ca32_x86_af $end +$var wire 1 qN pwr_ov_x86_of $end +$var wire 1 rN pwr_ov32_x86_df $end +$var wire 1 sN pwr_cr_lt_x86_sf $end +$var wire 1 tN pwr_cr_gt_x86_pf $end +$var wire 1 uN pwr_cr_eq_x86_zf $end +$var wire 1 vN pwr_so $end $upscope $end $upscope $end $scope struct \[1] $end -$var wire 64 eH int_fp $end +$var wire 64 wN int_fp $end $scope struct flags $end -$var wire 1 fH pwr_ca_x86_cf $end -$var wire 1 gH pwr_ca32_x86_af $end -$var wire 1 hH pwr_ov_x86_of $end -$var wire 1 iH pwr_ov32_x86_df $end -$var wire 1 jH pwr_cr_lt_x86_sf $end -$var wire 1 kH pwr_cr_gt_x86_pf $end -$var wire 1 lH pwr_cr_eq_x86_zf $end -$var wire 1 mH pwr_so $end +$var wire 1 xN pwr_ca_x86_cf $end +$var wire 1 yN pwr_ca32_x86_af $end +$var wire 1 zN pwr_ov_x86_of $end +$var wire 1 {N pwr_ov32_x86_df $end +$var wire 1 |N pwr_cr_lt_x86_sf $end +$var wire 1 }N pwr_cr_gt_x86_pf $end +$var wire 1 ~N pwr_cr_eq_x86_zf $end +$var wire 1 !O pwr_so $end $upscope $end $upscope $end $scope struct \[2] $end -$var wire 64 nH int_fp $end +$var wire 64 "O int_fp $end $scope struct flags $end -$var wire 1 oH pwr_ca_x86_cf $end -$var wire 1 pH pwr_ca32_x86_af $end -$var wire 1 qH pwr_ov_x86_of $end -$var wire 1 rH pwr_ov32_x86_df $end -$var wire 1 sH pwr_cr_lt_x86_sf $end -$var wire 1 tH pwr_cr_gt_x86_pf $end -$var wire 1 uH pwr_cr_eq_x86_zf $end -$var wire 1 vH pwr_so $end +$var wire 1 #O pwr_ca_x86_cf $end +$var wire 1 $O pwr_ca32_x86_af $end +$var wire 1 %O pwr_ov_x86_of $end +$var wire 1 &O pwr_ov32_x86_df $end +$var wire 1 'O pwr_cr_lt_x86_sf $end +$var wire 1 (O pwr_cr_gt_x86_pf $end +$var wire 1 )O pwr_cr_eq_x86_zf $end +$var wire 1 *O pwr_so $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct dest_reg_9 $end -$var wire 4 wH value $end +$var wire 4 +O value $end $upscope $end $scope struct dest_reg_10 $end -$var wire 4 xH value $end +$var wire 4 ,O value $end $upscope $end $scope struct in_flight_op_src_regs_4 $end -$var wire 6 yH \[0] $end -$var wire 6 zH \[1] $end -$var wire 6 {H \[2] $end +$var wire 6 -O \[0] $end +$var wire 6 .O \[1] $end +$var wire 6 /O \[2] $end $upscope $end -$var wire 1 |H cmp_eq_5 $end +$var wire 1 0O cmp_eq_9 $end +$var wire 1 1O cmp_eq_10 $end $scope struct firing_data_6 $end -$var string 1 }H \$tag $end +$var string 1 2O \$tag $end $scope struct HdlSome $end $scope struct mop $end -$var string 1 ~H \$tag $end +$var string 1 3O \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 !I prefix_pad $end -$scope struct dest $end -$var wire 4 "I value $end -$upscope $end -$scope struct src $end -$var wire 6 #I \[0] $end -$var wire 6 $I \[1] $end -$var wire 6 %I \[2] $end -$upscope $end -$var wire 25 &I imm_low $end -$var wire 1 'I imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 (I output_integer_mode $end -$upscope $end -$var wire 1 )I invert_src0 $end -$var wire 1 *I invert_carry_in $end -$var wire 1 +I invert_carry_out $end -$var wire 1 ,I add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 -I prefix_pad $end -$scope struct dest $end -$var wire 4 .I value $end -$upscope $end -$scope struct src $end -$var wire 6 /I \[0] $end -$var wire 6 0I \[1] $end -$var wire 6 1I \[2] $end -$upscope $end -$var wire 25 2I imm_low $end -$var wire 1 3I imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 4I output_integer_mode $end -$upscope $end -$var wire 1 5I invert_src0 $end -$var wire 1 6I invert_carry_in $end -$var wire 1 7I invert_carry_out $end -$var wire 1 8I add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 9I prefix_pad $end -$scope struct dest $end -$var wire 4 :I value $end -$upscope $end -$scope struct src $end -$var wire 6 ;I \[0] $end -$var wire 6 I imm_low $end -$var wire 1 ?I imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 @I output_integer_mode $end -$upscope $end -$var wire 4 AI lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 BI int_fp $end -$scope struct flags $end -$var wire 1 CI pwr_ca_x86_cf $end -$var wire 1 DI pwr_ca32_x86_af $end -$var wire 1 EI pwr_ov_x86_of $end -$var wire 1 FI pwr_ov32_x86_df $end -$var wire 1 GI pwr_cr_lt_x86_sf $end -$var wire 1 HI pwr_cr_gt_x86_pf $end -$var wire 1 II pwr_cr_eq_x86_zf $end -$var wire 1 JI pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 KI int_fp $end -$scope struct flags $end -$var wire 1 LI pwr_ca_x86_cf $end -$var wire 1 MI pwr_ca32_x86_af $end -$var wire 1 NI pwr_ov_x86_of $end -$var wire 1 OI pwr_ov32_x86_df $end -$var wire 1 PI pwr_cr_lt_x86_sf $end -$var wire 1 QI pwr_cr_gt_x86_pf $end -$var wire 1 RI pwr_cr_eq_x86_zf $end -$var wire 1 SI pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 TI int_fp $end -$scope struct flags $end -$var wire 1 UI pwr_ca_x86_cf $end -$var wire 1 VI pwr_ca32_x86_af $end -$var wire 1 WI pwr_ov_x86_of $end -$var wire 1 XI pwr_ov32_x86_df $end -$var wire 1 YI pwr_cr_lt_x86_sf $end -$var wire 1 ZI pwr_cr_gt_x86_pf $end -$var wire 1 [I pwr_cr_eq_x86_zf $end -$var wire 1 \I pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_11 $end -$var wire 4 ]I value $end -$upscope $end -$scope struct dest_reg_12 $end -$var wire 4 ^I value $end -$upscope $end -$scope struct in_flight_op_src_regs_5 $end -$var wire 6 _I \[0] $end -$var wire 6 `I \[1] $end -$var wire 6 aI \[2] $end -$upscope $end -$var wire 1 bI cmp_eq_6 $end -$scope struct firing_data_7 $end -$var string 1 cI \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 dI \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 eI prefix_pad $end -$scope struct dest $end -$var wire 4 fI value $end -$upscope $end -$scope struct src $end -$var wire 6 gI \[0] $end -$var wire 6 hI \[1] $end -$var wire 6 iI \[2] $end -$upscope $end -$var wire 25 jI imm_low $end -$var wire 1 kI imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 lI output_integer_mode $end -$upscope $end -$var wire 1 mI invert_src0 $end -$var wire 1 nI invert_carry_in $end -$var wire 1 oI invert_carry_out $end -$var wire 1 pI add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 qI prefix_pad $end -$scope struct dest $end -$var wire 4 rI value $end -$upscope $end -$scope struct src $end -$var wire 6 sI \[0] $end -$var wire 6 tI \[1] $end -$var wire 6 uI \[2] $end -$upscope $end -$var wire 25 vI imm_low $end -$var wire 1 wI imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 xI output_integer_mode $end -$upscope $end -$var wire 1 yI invert_src0 $end -$var wire 1 zI invert_carry_in $end -$var wire 1 {I invert_carry_out $end -$var wire 1 |I add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 }I prefix_pad $end -$scope struct dest $end -$var wire 4 ~I value $end -$upscope $end -$scope struct src $end -$var wire 6 !J \[0] $end -$var wire 6 "J \[1] $end -$var wire 6 #J \[2] $end -$upscope $end -$var wire 25 $J imm_low $end -$var wire 1 %J imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 &J output_integer_mode $end -$upscope $end -$var wire 4 'J lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 (J int_fp $end -$scope struct flags $end -$var wire 1 )J pwr_ca_x86_cf $end -$var wire 1 *J pwr_ca32_x86_af $end -$var wire 1 +J pwr_ov_x86_of $end -$var wire 1 ,J pwr_ov32_x86_df $end -$var wire 1 -J pwr_cr_lt_x86_sf $end -$var wire 1 .J pwr_cr_gt_x86_pf $end -$var wire 1 /J pwr_cr_eq_x86_zf $end -$var wire 1 0J pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 1J int_fp $end -$scope struct flags $end -$var wire 1 2J pwr_ca_x86_cf $end -$var wire 1 3J pwr_ca32_x86_af $end -$var wire 1 4J pwr_ov_x86_of $end -$var wire 1 5J pwr_ov32_x86_df $end -$var wire 1 6J pwr_cr_lt_x86_sf $end -$var wire 1 7J pwr_cr_gt_x86_pf $end -$var wire 1 8J pwr_cr_eq_x86_zf $end -$var wire 1 9J pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 :J int_fp $end -$scope struct flags $end -$var wire 1 ;J pwr_ca_x86_cf $end -$var wire 1 J pwr_ov32_x86_df $end -$var wire 1 ?J pwr_cr_lt_x86_sf $end -$var wire 1 @J pwr_cr_gt_x86_pf $end -$var wire 1 AJ pwr_cr_eq_x86_zf $end -$var wire 1 BJ pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_13 $end -$var wire 4 CJ value $end -$upscope $end -$scope struct dest_reg_14 $end -$var wire 4 DJ value $end -$upscope $end -$scope struct in_flight_op_src_regs_6 $end -$var wire 6 EJ \[0] $end -$var wire 6 FJ \[1] $end -$var wire 6 GJ \[2] $end -$upscope $end -$var wire 1 HJ cmp_eq_7 $end -$scope struct firing_data_8 $end -$var string 1 IJ \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 JJ \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 KJ prefix_pad $end -$scope struct dest $end -$var wire 4 LJ value $end -$upscope $end -$scope struct src $end -$var wire 6 MJ \[0] $end -$var wire 6 NJ \[1] $end -$var wire 6 OJ \[2] $end -$upscope $end -$var wire 25 PJ imm_low $end -$var wire 1 QJ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 RJ output_integer_mode $end -$upscope $end -$var wire 1 SJ invert_src0 $end -$var wire 1 TJ invert_carry_in $end -$var wire 1 UJ invert_carry_out $end -$var wire 1 VJ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 WJ prefix_pad $end -$scope struct dest $end -$var wire 4 XJ value $end -$upscope $end -$scope struct src $end -$var wire 6 YJ \[0] $end -$var wire 6 ZJ \[1] $end -$var wire 6 [J \[2] $end -$upscope $end -$var wire 25 \J imm_low $end -$var wire 1 ]J imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ^J output_integer_mode $end -$upscope $end -$var wire 1 _J invert_src0 $end -$var wire 1 `J invert_carry_in $end -$var wire 1 aJ invert_carry_out $end -$var wire 1 bJ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 cJ prefix_pad $end -$scope struct dest $end -$var wire 4 dJ value $end -$upscope $end -$scope struct src $end -$var wire 6 eJ \[0] $end -$var wire 6 fJ \[1] $end -$var wire 6 gJ \[2] $end -$upscope $end -$var wire 25 hJ imm_low $end -$var wire 1 iJ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 jJ output_integer_mode $end -$upscope $end -$var wire 4 kJ lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 lJ int_fp $end -$scope struct flags $end -$var wire 1 mJ pwr_ca_x86_cf $end -$var wire 1 nJ pwr_ca32_x86_af $end -$var wire 1 oJ pwr_ov_x86_of $end -$var wire 1 pJ pwr_ov32_x86_df $end -$var wire 1 qJ pwr_cr_lt_x86_sf $end -$var wire 1 rJ pwr_cr_gt_x86_pf $end -$var wire 1 sJ pwr_cr_eq_x86_zf $end -$var wire 1 tJ pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 uJ int_fp $end -$scope struct flags $end -$var wire 1 vJ pwr_ca_x86_cf $end -$var wire 1 wJ pwr_ca32_x86_af $end -$var wire 1 xJ pwr_ov_x86_of $end -$var wire 1 yJ pwr_ov32_x86_df $end -$var wire 1 zJ pwr_cr_lt_x86_sf $end -$var wire 1 {J pwr_cr_gt_x86_pf $end -$var wire 1 |J pwr_cr_eq_x86_zf $end -$var wire 1 }J pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 ~J int_fp $end -$scope struct flags $end -$var wire 1 !K pwr_ca_x86_cf $end -$var wire 1 "K pwr_ca32_x86_af $end -$var wire 1 #K pwr_ov_x86_of $end -$var wire 1 $K pwr_ov32_x86_df $end -$var wire 1 %K pwr_cr_lt_x86_sf $end -$var wire 1 &K pwr_cr_gt_x86_pf $end -$var wire 1 'K pwr_cr_eq_x86_zf $end -$var wire 1 (K pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_15 $end -$var wire 4 )K value $end -$upscope $end -$scope struct dest_reg_16 $end -$var wire 4 *K value $end -$upscope $end -$scope struct in_flight_op_src_regs_7 $end -$var wire 6 +K \[0] $end -$var wire 6 ,K \[1] $end -$var wire 6 -K \[2] $end -$upscope $end -$var wire 1 .K cmp_eq_8 $end -$scope struct firing_data_9 $end -$var string 1 /K \$tag $end -$scope struct HdlSome $end -$scope struct mop $end -$var string 1 0K \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 1K prefix_pad $end -$scope struct dest $end -$var wire 4 2K value $end -$upscope $end -$scope struct src $end -$var wire 6 3K \[0] $end -$var wire 6 4K \[1] $end -$var wire 6 5K \[2] $end -$upscope $end -$var wire 25 6K imm_low $end -$var wire 1 7K imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 8K output_integer_mode $end -$upscope $end -$var wire 1 9K invert_src0 $end -$var wire 1 :K invert_carry_in $end -$var wire 1 ;K invert_carry_out $end -$var wire 1 K value $end -$upscope $end -$scope struct src $end -$var wire 6 ?K \[0] $end -$var wire 6 @K \[1] $end -$var wire 6 AK \[2] $end -$upscope $end -$var wire 25 BK imm_low $end -$var wire 1 CK imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 DK output_integer_mode $end -$upscope $end -$var wire 1 EK invert_src0 $end -$var wire 1 FK invert_carry_in $end -$var wire 1 GK invert_carry_out $end -$var wire 1 HK add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 IK prefix_pad $end -$scope struct dest $end -$var wire 4 JK value $end -$upscope $end -$scope struct src $end -$var wire 6 KK \[0] $end -$var wire 6 LK \[1] $end -$var wire 6 MK \[2] $end -$upscope $end -$var wire 25 NK imm_low $end -$var wire 1 OK imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 PK output_integer_mode $end -$upscope $end -$var wire 4 QK lut $end -$upscope $end -$upscope $end -$scope struct src_values $end -$scope struct \[0] $end -$var wire 64 RK int_fp $end -$scope struct flags $end -$var wire 1 SK pwr_ca_x86_cf $end -$var wire 1 TK pwr_ca32_x86_af $end -$var wire 1 UK pwr_ov_x86_of $end -$var wire 1 VK pwr_ov32_x86_df $end -$var wire 1 WK pwr_cr_lt_x86_sf $end -$var wire 1 XK pwr_cr_gt_x86_pf $end -$var wire 1 YK pwr_cr_eq_x86_zf $end -$var wire 1 ZK pwr_so $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$var wire 64 [K int_fp $end -$scope struct flags $end -$var wire 1 \K pwr_ca_x86_cf $end -$var wire 1 ]K pwr_ca32_x86_af $end -$var wire 1 ^K pwr_ov_x86_of $end -$var wire 1 _K pwr_ov32_x86_df $end -$var wire 1 `K pwr_cr_lt_x86_sf $end -$var wire 1 aK pwr_cr_gt_x86_pf $end -$var wire 1 bK pwr_cr_eq_x86_zf $end -$var wire 1 cK pwr_so $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$var wire 64 dK int_fp $end -$scope struct flags $end -$var wire 1 eK pwr_ca_x86_cf $end -$var wire 1 fK pwr_ca32_x86_af $end -$var wire 1 gK pwr_ov_x86_of $end -$var wire 1 hK pwr_ov32_x86_df $end -$var wire 1 iK pwr_cr_lt_x86_sf $end -$var wire 1 jK pwr_cr_gt_x86_pf $end -$var wire 1 kK pwr_cr_eq_x86_zf $end -$var wire 1 lK pwr_so $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope struct dest_reg_17 $end -$var wire 4 mK value $end -$upscope $end -$upscope $end -$upscope $end -$scope struct unit_1_free_regs_tracker $end -$scope struct cd $end -$var wire 1 |N clk $end -$var wire 1 }N rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 ~N \$tag $end -$var wire 4 !O HdlSome $end -$upscope $end -$var wire 1 "O ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 #O \$tag $end -$var wire 4 $O HdlSome $end -$upscope $end -$var wire 1 %O ready $end -$upscope $end -$upscope $end -$upscope $end -$scope module unit_free_regs_tracker_2 $end -$scope struct cd $end -$var wire 1 3N clk $end -$var wire 1 4N rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 5N \$tag $end -$var wire 4 6N HdlSome $end -$upscope $end -$var wire 1 7N ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 8N \$tag $end -$var wire 4 9N HdlSome $end -$upscope $end -$var wire 1 :N ready $end -$upscope $end -$upscope $end -$scope struct allocated_reg $end -$var reg 1 ;N \[0] $end -$var reg 1 N \[3] $end -$var reg 1 ?N \[4] $end -$var reg 1 @N \[5] $end -$var reg 1 AN \[6] $end -$var reg 1 BN \[7] $end -$var reg 1 CN \[8] $end -$var reg 1 DN \[9] $end -$var reg 1 EN \[10] $end -$var reg 1 FN \[11] $end -$var reg 1 GN \[12] $end -$var reg 1 HN \[13] $end -$var reg 1 IN \[14] $end -$var reg 1 JN \[15] $end -$upscope $end -$scope struct firing_data $end -$var string 1 KN \$tag $end -$var wire 4 LN HdlSome $end -$upscope $end -$var wire 1 MN reduced_count_0_2 $end -$var wire 1 NN reduced_count_overflowed_0_2 $end -$scope struct reduced_alloc_nums_0_2 $end -$var wire 1 ON \[0] $end -$upscope $end -$var wire 1 PN reduced_count_2_4 $end -$var wire 1 QN reduced_count_overflowed_2_4 $end -$scope struct reduced_alloc_nums_2_4 $end -$var wire 1 RN \[0] $end -$upscope $end -$var wire 1 SN reduced_count_0_4 $end -$var wire 1 TN reduced_count_overflowed_0_4 $end -$scope struct reduced_alloc_nums_0_4 $end -$var wire 2 UN \[0] $end -$upscope $end -$var wire 1 VN reduced_count_4_6 $end -$var wire 1 WN reduced_count_overflowed_4_6 $end -$scope struct reduced_alloc_nums_4_6 $end -$var wire 1 XN \[0] $end -$upscope $end -$var wire 1 YN reduced_count_6_8 $end -$var wire 1 ZN reduced_count_overflowed_6_8 $end -$scope struct reduced_alloc_nums_6_8 $end -$var wire 1 [N \[0] $end -$upscope $end -$var wire 1 \N reduced_count_4_8 $end -$var wire 1 ]N reduced_count_overflowed_4_8 $end -$scope struct reduced_alloc_nums_4_8 $end -$var wire 2 ^N \[0] $end -$upscope $end -$var wire 1 _N reduced_count_0_8 $end -$var wire 1 `N reduced_count_overflowed_0_8 $end -$scope struct reduced_alloc_nums_0_8 $end -$var wire 3 aN \[0] $end -$upscope $end -$var wire 1 bN reduced_count_8_10 $end -$var wire 1 cN reduced_count_overflowed_8_10 $end -$scope struct reduced_alloc_nums_8_10 $end -$var wire 1 dN \[0] $end -$upscope $end -$var wire 1 eN reduced_count_10_12 $end -$var wire 1 fN reduced_count_overflowed_10_12 $end -$scope struct reduced_alloc_nums_10_12 $end -$var wire 1 gN \[0] $end -$upscope $end -$var wire 1 hN reduced_count_8_12 $end -$var wire 1 iN reduced_count_overflowed_8_12 $end -$scope struct reduced_alloc_nums_8_12 $end -$var wire 2 jN \[0] $end -$upscope $end -$var wire 1 kN reduced_count_12_14 $end -$var wire 1 lN reduced_count_overflowed_12_14 $end -$scope struct reduced_alloc_nums_12_14 $end -$var wire 1 mN \[0] $end -$upscope $end -$var wire 1 nN reduced_count_14_16 $end -$var wire 1 oN reduced_count_overflowed_14_16 $end -$scope struct reduced_alloc_nums_14_16 $end -$var wire 1 pN \[0] $end -$upscope $end -$var wire 1 qN reduced_count_12_16 $end -$var wire 1 rN reduced_count_overflowed_12_16 $end -$scope struct reduced_alloc_nums_12_16 $end -$var wire 2 sN \[0] $end -$upscope $end -$var wire 1 tN reduced_count_8_16 $end -$var wire 1 uN reduced_count_overflowed_8_16 $end -$scope struct reduced_alloc_nums_8_16 $end -$var wire 3 vN \[0] $end -$upscope $end -$var wire 1 wN reduced_count_0_16 $end -$var wire 1 xN reduced_count_overflowed_0_16 $end -$scope struct reduced_alloc_nums_0_16 $end -$var wire 4 yN \[0] $end -$upscope $end -$scope struct firing_data_2 $end -$var string 1 zN \$tag $end -$var wire 4 {N HdlSome $end -$upscope $end -$upscope $end -$scope struct and_then_out_3 $end -$var string 1 &O \$tag $end -$scope struct HdlSome $end -$var string 1 'O \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 (O prefix_pad $end -$scope struct dest $end -$var wire 4 )O value $end -$upscope $end -$scope struct src $end -$var wire 6 *O \[0] $end -$var wire 6 +O \[1] $end -$var wire 6 ,O \[2] $end -$upscope $end -$var wire 25 -O imm_low $end -$var wire 1 .O imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 /O output_integer_mode $end -$upscope $end -$var wire 1 0O invert_src0 $end -$var wire 1 1O invert_carry_in $end -$var wire 1 2O invert_carry_out $end -$var wire 1 3O add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end $var string 0 4O prefix_pad $end $scope struct dest $end $var wire 4 5O value $end @@ -12461,11 +13721,11 @@ $upscope $end $var string 1 ;O output_integer_mode $end $upscope $end $var wire 1 O invert_carry_out $end +$var wire 1 =O src1_is_carry_in $end +$var wire 1 >O invert_carry_in $end $var wire 1 ?O add_pc $end $upscope $end -$scope struct Logical $end +$scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end $var string 0 @O prefix_pad $end @@ -12484,116 +13744,98 @@ $upscope $end $upscope $end $var string 1 GO output_integer_mode $end $upscope $end -$var wire 4 HO lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct alu_branch_mop_3 $end -$var string 1 IO \$tag $end -$scope struct HdlSome $end -$var string 1 JO \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 KO prefix_pad $end -$scope struct dest $end -$var wire 4 LO value $end -$upscope $end -$scope struct src $end -$var wire 6 MO \[0] $end -$var wire 6 NO \[1] $end -$var wire 6 OO \[2] $end -$upscope $end -$var wire 25 PO imm_low $end -$var wire 1 QO imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 RO output_integer_mode $end -$upscope $end -$var wire 1 SO invert_src0 $end -$var wire 1 TO invert_carry_in $end -$var wire 1 UO invert_carry_out $end -$var wire 1 VO add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 WO prefix_pad $end -$scope struct dest $end -$var wire 4 XO value $end -$upscope $end -$scope struct src $end -$var wire 6 YO \[0] $end -$var wire 6 ZO \[1] $end -$var wire 6 [O \[2] $end -$upscope $end -$var wire 25 \O imm_low $end -$var wire 1 ]O imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 ^O output_integer_mode $end -$upscope $end -$var wire 1 _O invert_src0 $end -$var wire 1 `O invert_carry_in $end -$var wire 1 aO invert_carry_out $end -$var wire 1 bO add_pc $end +$var wire 1 HO invert_src0 $end +$var wire 1 IO src1_is_carry_in $end +$var wire 1 JO invert_carry_in $end +$var wire 1 KO add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 cO prefix_pad $end +$var string 0 LO prefix_pad $end $scope struct dest $end -$var wire 4 dO value $end +$var wire 4 MO value $end $upscope $end $scope struct src $end -$var wire 6 eO \[0] $end -$var wire 6 fO \[1] $end -$var wire 6 gO \[2] $end +$var wire 6 NO \[0] $end +$var wire 6 OO \[1] $end +$var wire 6 PO \[2] $end $upscope $end -$var wire 25 hO imm_low $end -$var wire 1 iO imm_sign $end +$var wire 25 QO imm_low $end +$var wire 1 RO imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 jO output_integer_mode $end +$var string 1 SO output_integer_mode $end $upscope $end -$var wire 4 kO lut $end +$var wire 4 TO lut $end +$upscope $end +$upscope $end +$var wire 64 UO pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 VO int_fp $end +$scope struct flags $end +$var wire 1 WO pwr_ca_x86_cf $end +$var wire 1 XO pwr_ca32_x86_af $end +$var wire 1 YO pwr_ov_x86_of $end +$var wire 1 ZO pwr_ov32_x86_df $end +$var wire 1 [O pwr_cr_lt_x86_sf $end +$var wire 1 \O pwr_cr_gt_x86_pf $end +$var wire 1 ]O pwr_cr_eq_x86_zf $end +$var wire 1 ^O pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 _O int_fp $end +$scope struct flags $end +$var wire 1 `O pwr_ca_x86_cf $end +$var wire 1 aO pwr_ca32_x86_af $end +$var wire 1 bO pwr_ov_x86_of $end +$var wire 1 cO pwr_ov32_x86_df $end +$var wire 1 dO pwr_cr_lt_x86_sf $end +$var wire 1 eO pwr_cr_gt_x86_pf $end +$var wire 1 fO pwr_cr_eq_x86_zf $end +$var wire 1 gO pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 hO int_fp $end +$scope struct flags $end +$var wire 1 iO pwr_ca_x86_cf $end +$var wire 1 jO pwr_ca32_x86_af $end +$var wire 1 kO pwr_ov_x86_of $end +$var wire 1 lO pwr_ov32_x86_df $end +$var wire 1 mO pwr_cr_lt_x86_sf $end +$var wire 1 nO pwr_cr_gt_x86_pf $end +$var wire 1 oO pwr_cr_eq_x86_zf $end +$var wire 1 pO pwr_so $end $upscope $end $upscope $end $upscope $end -$scope struct and_then_out_4 $end -$var string 1 lO \$tag $end +$upscope $end +$upscope $end +$scope struct dest_reg_11 $end +$var wire 4 qO value $end +$upscope $end +$scope struct dest_reg_12 $end +$var wire 4 rO value $end +$upscope $end +$scope struct in_flight_op_src_regs_5 $end +$var wire 6 sO \[0] $end +$var wire 6 tO \[1] $end +$var wire 6 uO \[2] $end +$upscope $end +$var wire 1 vO cmp_eq_11 $end +$var wire 1 wO cmp_eq_12 $end +$scope struct firing_data_7 $end +$var string 1 xO \$tag $end $scope struct HdlSome $end -$var string 1 mO \$tag $end +$scope struct mop $end +$var string 1 yO \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 nO prefix_pad $end -$scope struct dest $end -$var wire 4 oO value $end -$upscope $end -$scope struct src $end -$var wire 6 pO \[0] $end -$var wire 6 qO \[1] $end -$var wire 6 rO \[2] $end -$upscope $end -$var wire 25 sO imm_low $end -$var wire 1 tO imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 uO output_integer_mode $end -$upscope $end -$var wire 1 vO invert_src0 $end -$var wire 1 wO invert_carry_in $end -$var wire 1 xO invert_carry_out $end -$var wire 1 yO add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end $var string 0 zO prefix_pad $end $scope struct dest $end $var wire 4 {O value $end @@ -12611,11 +13853,11 @@ $upscope $end $var string 1 #P output_integer_mode $end $upscope $end $var wire 1 $P invert_src0 $end -$var wire 1 %P invert_carry_in $end -$var wire 1 &P invert_carry_out $end +$var wire 1 %P src1_is_carry_in $end +$var wire 1 &P invert_carry_in $end $var wire 1 'P add_pc $end $upscope $end -$scope struct Logical $end +$scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end $var string 0 (P prefix_pad $end @@ -12634,598 +13876,2245 @@ $upscope $end $upscope $end $var string 1 /P output_integer_mode $end $upscope $end -$var wire 4 0P lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct alu_branch_mop_4 $end -$var string 1 1P \$tag $end -$scope struct HdlSome $end -$var string 1 2P \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 3P prefix_pad $end -$scope struct dest $end -$var wire 4 4P value $end -$upscope $end -$scope struct src $end -$var wire 6 5P \[0] $end -$var wire 6 6P \[1] $end -$var wire 6 7P \[2] $end -$upscope $end -$var wire 25 8P imm_low $end -$var wire 1 9P imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 :P output_integer_mode $end -$upscope $end -$var wire 1 ;P invert_src0 $end -$var wire 1

P add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ?P prefix_pad $end -$scope struct dest $end -$var wire 4 @P value $end -$upscope $end -$scope struct src $end -$var wire 6 AP \[0] $end -$var wire 6 BP \[1] $end -$var wire 6 CP \[2] $end -$upscope $end -$var wire 25 DP imm_low $end -$var wire 1 EP imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 FP output_integer_mode $end -$upscope $end -$var wire 1 GP invert_src0 $end -$var wire 1 HP invert_carry_in $end -$var wire 1 IP invert_carry_out $end -$var wire 1 JP add_pc $end +$var wire 1 0P invert_src0 $end +$var wire 1 1P src1_is_carry_in $end +$var wire 1 2P invert_carry_in $end +$var wire 1 3P add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 KP prefix_pad $end +$var string 0 4P prefix_pad $end $scope struct dest $end -$var wire 4 LP value $end +$var wire 4 5P value $end $upscope $end $scope struct src $end -$var wire 6 MP \[0] $end -$var wire 6 NP \[1] $end -$var wire 6 OP \[2] $end +$var wire 6 6P \[0] $end +$var wire 6 7P \[1] $end +$var wire 6 8P \[2] $end $upscope $end -$var wire 25 PP imm_low $end -$var wire 1 QP imm_sign $end +$var wire 25 9P imm_low $end +$var wire 1 :P imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 RP output_integer_mode $end +$var string 1 ;P output_integer_mode $end $upscope $end -$var wire 4 SP lut $end +$var wire 4

P -s0 ?P -b0 @P -b0 AP -b0 BP -b0 CP -b0 DP +b0 9P +0:P +sFull64\x20(0) ;P +b0

P +0?P +0@P +0AP +0BP +0CP +0DP 0EP -sFull64\x20(0) FP -0GP -1HP -1IP +0FP +b0 GP +0HP +0IP 0JP -s0 KP -b0 LP -b0 MP -b0 NP -b0 OP +0KP +0LP +0MP +0NP +0OP b0 PP 0QP -sFull64\x20(0) RP -b110 SP +0RP +0SP +0TP +0UP +0VP +0WP +0XP +b0 YP +b0 ZP +b0 [P +b0 \P +b0 ]P +0^P +0_P +sHdlNone\x20(0) `P +sAddSub\x20(0) aP +s0 bP +b0 cP +b0 dP +b0 eP +b0 fP +b0 gP +0hP +sFull64\x20(0) iP +0jP +0kP +0lP +0mP +s0 nP +b0 oP +b0 pP +b0 qP +b0 rP +b0 sP +0tP +sFull64\x20(0) uP +0vP +0wP +0xP +0yP +s0 zP +b0 {P +b0 |P +b0 }P +b0 ~P +b0 !Q +0"Q +sFull64\x20(0) #Q +b0 $Q +b0 %Q +b0 &Q +0'Q +0(Q +0)Q +0*Q +0+Q +0,Q +0-Q +0.Q +b0 /Q +00Q +01Q +02Q +03Q +04Q +05Q +06Q +07Q +b0 8Q +09Q +0:Q +0;Q +0Q +0?Q +0@Q +b0 AQ +b0 BQ +b0 CQ +b0 DQ +b0 EQ +0FQ +0GQ +sHdlNone\x20(0) HQ +sAddSub\x20(0) IQ +s0 JQ +b0 KQ +b0 LQ +b0 MQ +b0 NQ +b0 OQ +0PQ +sFull64\x20(0) QQ +0RQ +0SQ +0TQ +0UQ +s0 VQ +b0 WQ +b0 XQ +b0 YQ +b0 ZQ +b0 [Q +0\Q +sFull64\x20(0) ]Q +0^Q +0_Q +0`Q +0aQ +s0 bQ +b0 cQ +b0 dQ +b0 eQ +b0 fQ +b0 gQ +0hQ +sFull64\x20(0) iQ +b0 jQ +b0 kQ +b0 lQ +0mQ +0nQ +0oQ +0pQ +0qQ +0rQ +0sQ +0tQ +b0 uQ +0vQ +0wQ +0xQ +0yQ +0zQ +0{Q +0|Q +0}Q +b0 ~Q +0!R +0"R +0#R +0$R +0%R +0&R +0'R +0(R +b0 )R +0*R +1+R +sHdlNone\x20(0) ,R +b0 -R +b0 .R +0/R +00R +01R +02R +03R +04R +05R +06R +sHdlNone\x20(0) 7R +b0 8R +b0 9R +0:R +0;R +0R +0?R +0@R +0AR +sHdlSome\x20(1) BR +sLogical\x20(2) CR +s0 DR +b0 ER +b0 FR +b0 GR +b0 HR +b0 IR +0JR +sFull64\x20(0) KR +0LR +1MR +1NR +0OR +s0 PR +b0 QR +b0 RR +b0 SR +b0 TR +b0 UR +0VR +sFull64\x20(0) WR +0XR +1YR +1ZR +0[R +s0 \R +b0 ]R +b0 ^R +b0 _R +b0 `R +b0 aR +0bR +sFull64\x20(0) cR +b110 dR +b1000000000100 eR +1fR +sHdlNone\x20(0) gR +b0 hR +sHdlNone\x20(0) iR +b0 jR +sCompleted\x20(0) kR +b0 lR +0mR +0nR +0oR +0pR +0qR +0rR +0sR +0tR +sHdlNone\x20(0) uR +sAddSub\x20(0) vR +s0 wR +b0 xR +b0 yR +b0 zR +b0 {R +b0 |R +0}R +sFull64\x20(0) ~R +0!S +0"S +0#S +0$S +s0 %S +b0 &S +b0 'S +b0 (S +b0 )S +b0 *S +0+S +sFull64\x20(0) ,S +0-S +0.S +0/S +00S +s0 1S +b0 2S +b0 3S +b0 4S +b0 5S +b0 6S +07S +sFull64\x20(0) 8S +b0 9S +b0 :S +b0 ;S +0S +0?S +0@S +0AS +0BS +0CS +b0 DS +0ES +0FS +0GS +0HS +0IS +0JS +0KS +0LS +b0 MS +0NS +0OS +0PS +0QS +0RS +0SS +0TS +0US +1VS +sHdlNone\x20(0) WS +b0 XS +sCompleted\x20(0) YS +b0 ZS +0[S +0\S +0]S +0^S +0_S +0`S +0aS +0bS +sHdlNone\x20(0) cS +sAddSub\x20(0) dS +s0 eS +b0 fS +b0 gS +b0 hS +b0 iS +b0 jS +0kS +sFull64\x20(0) lS +0mS +0nS +0oS +0pS +s0 qS +b0 rS +b0 sS +b0 tS +b0 uS +b0 vS +0wS +sFull64\x20(0) xS +0yS +0zS +0{S +0|S +s0 }S +b0 ~S +b0 !T +b0 "T +b0 #T +b0 $T +0%T +sFull64\x20(0) &T +b0 'T +b0 (T +b0 )T +0*T +0+T +0,T +0-T +0.T +0/T +00T +01T +b0 2T +03T +04T +05T +06T +07T +08T +09T +0:T +b0 ;T +0T +0?T +0@T +0AT +0BT +0CT +0DT +b0 ET +0FT +b0 GT +b0 HT +b0 IT +0JT +0KT +0LT +0MT +0NT +0OT +0PT +0QT +0RT +b0 ST +0TT +0UT +0VT +0WT +1XT +1YT +0ZT +0[T +0\T +0]T +0^T +1_T +0`T +0aT +0bT +0cT +0dT +0eT +0fT +0gT +1hT +0iT +0jT +b0 kT +0lT +b0 mT +b0 nT +b0 oT +0pT +0qT +0rT +0sT +0tT +0uT +0vT +0wT +0xT +b0 yT +0zT +0{T +0|T +0}T +1~T +1!U +0"U +0#U +0$U +0%U +0&U +1'U +0(U +0)U +0*U +0+U +0,U +0-U +0.U +0/U +10U +01U +02U +13U +sHdlNone\x20(0) 4U +b0 5U +b0 6U +07U +08U +09U +0:U +0;U +0U +sHdlNone\x20(0) ?U +b0 @U +b0 AU +0BU +0CU +0DU +0EU +0FU +0GU +0HU +0IU +sHdlSome\x20(1) JU +sLogical\x20(2) KU +s0 LU +b0 MU +b0 NU +b0 OU +b0 PU +b0 QU +0RU +sFull64\x20(0) SU +0TU +1UU +1VU +0WU +s0 XU +b0 YU +b0 ZU +b0 [U +b0 \U +b0 ]U +0^U +sFull64\x20(0) _U +0`U +1aU +1bU +0cU +s0 dU +b0 eU +b0 fU +b0 gU +b0 hU +b0 iU +0jU +sFull64\x20(0) kU +b110 lU +b1000000000100 mU +1nU +sHdlNone\x20(0) oU +b0 pU +sHdlNone\x20(0) qU +b0 rU +sCompleted\x20(0) sU +b0 tU +0uU +0vU +0wU +0xU +0yU +0zU +0{U +0|U +sPowerISA\x20(0) }U +0~U +1!V +sHdlNone\x20(0) "V +b0 #V +1$V +sHdlSome\x20(1) %V +b0 &V +1'V +0(V +0)V +0*V +0+V +0,V +0-V +0.V +0/V +00V +01V +02V +03V +04V +05V +06V +07V +sHdlNone\x20(0) 8V +b0 9V +0:V +1;V +0V +0?V +0@V +1AV +b0 BV +0CV +1DV +0EV +0FV +1GV +0HV +0IV +1JV +b0 KV +0LV +1MV +b0 NV +0OV +1PV +0QV +0RV +1SV +0TV +0UV +1VV +b0 WV +0XV +1YV +0ZV +0[V +1\V +0]V +0^V +1_V +b0 `V +0aV +1bV +b0 cV +0dV +1eV +b0 fV +sHdlSome\x20(1) gV +b0 hV +0iV +1jV +sHdlNone\x20(0) kV +b0 lV +1mV +sHdlSome\x20(1) nV +b0 oV +1pV +sHdlSome\x20(1) qV +sAddSub\x20(0) rV +s0 sV +b0 tV +b0 uV +b0 vV +b0 wV +b1001000110100 xV +0yV +sFull64\x20(0) zV +1{V +1|V +1}V +1~V +s0 !W +b0 "W +b0 #W +b0 $W +b0 %W +b1001000110100 &W +0'W +sFull64\x20(0) (W +1)W +1*W +1+W +1,W +s0 -W +b0 .W +b0 /W +b0 0W +b0 1W +b1001000110100 2W +03W +sFull64\x20(0) 4W +b1111 5W +b1000000000000 6W +sHdlSome\x20(1) 7W +sAddSub\x20(0) 8W +s0 9W +b0 :W +b0 ;W +b0 W +0?W +sFull64\x20(0) @W +1AW +1BW +1CW +1DW +s0 EW +b0 FW +b0 GW +b0 HW +b0 IW +b1001000110100 JW +0KW +sFull64\x20(0) LW +1MW +1NW +1OW +1PW +s0 QW +b0 RW +b0 SW +b0 TW +b0 UW +b1001000110100 VW +0WW +sFull64\x20(0) XW +b1111 YW +b1000000000000 ZW +sHdlSome\x20(1) [W +sAddSub\x20(0) \W +s0 ]W +b0 ^W +b0 _W +b0 `W +b0 aW +b1001000110100 bW +0cW +sFull64\x20(0) dW +1eW +1fW +1gW +1hW +s0 iW +b0 jW +b0 kW +b0 lW +b0 mW +b1001000110100 nW +0oW +sFull64\x20(0) pW +1qW +1rW +1sW +1tW +s0 uW +b0 vW +b0 wW +b0 xW +b0 yW +b1001000110100 zW +0{W +sFull64\x20(0) |W +b1111 }W +sHdlSome\x20(1) ~W +sLogical\x20(2) !X +s0 "X +b0 #X +b0 $X +b0 %X +b0 &X +b0 'X +0(X +sFull64\x20(0) )X +0*X +1+X +1,X +0-X +s0 .X +b0 /X +b0 0X +b0 1X +b0 2X +b0 3X +04X +sFull64\x20(0) 5X +06X +17X +18X +09X +s0 :X +b0 ;X +b0 X +b0 ?X +0@X +sFull64\x20(0) AX +b110 BX +b1000000000100 CX +sHdlSome\x20(1) DX +sLogical\x20(2) EX +s0 FX +b0 GX +b0 HX +b0 IX +b0 JX +b0 KX +0LX +sFull64\x20(0) MX +0NX +1OX +1PX +0QX +s0 RX +b0 SX +b0 TX +b0 UX +b0 VX +b0 WX +0XX +sFull64\x20(0) YX +0ZX +1[X +1\X +0]X +s0 ^X +b0 _X +b0 `X +b0 aX +b0 bX +b0 cX +0dX +sFull64\x20(0) eX +b110 fX +b1000000000100 gX +sHdlSome\x20(1) hX +sLogical\x20(2) iX +s0 jX +b0 kX +b0 lX +b0 mX +b0 nX +b0 oX +0pX +sFull64\x20(0) qX +0rX +1sX +1tX +0uX +s0 vX +b0 wX +b0 xX +b0 yX +b0 zX +b0 {X +0|X +sFull64\x20(0) }X +0~X +1!Y +1"Y +0#Y +s0 $Y +b0 %Y +b0 &Y +b0 'Y +b0 (Y +b0 )Y +0*Y +sFull64\x20(0) +Y +b110 ,Y $end #500000 -b1 TP -b0 7S -b10 UP -b0 8S -b1 xU -b0 zU -b10 yU -b0 {U +b1 -Y +b0 n[ +b10 .Y +b0 o[ +b1 Q^ +b0 S^ +b10 R^ +b0 T^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N -b10 !# -b10 ]$ -b10 i$ -b10 u$ -b10 !% -b10 (% -b10 0% -b10 7% -b10 '& -b10 p& -b10 |& -b10 *' -b10 4' -b10 ;' -b10 C' -b10 J' -b10 R' -b10 ^' -b10 j' -b10 z+ -b10 (, -b10 4, -b10 f, -b10 r, -b10 ~, -b10 )2 -b10 52 -b10 A2 -0H2 -b10 O2 -b10 [2 -b10 g2 -b10 n2 -0q2 -b10 `9 -b10 l9 -b10 x9 -b10 9; -b10 E; -b10 Q; -b10 ^< -b10 j< -b10 v< -b10 #= -b10 /= -b10 ;= -b10 *O -b10 6O -b10 BO -b10 MO -b10 YO -b10 eO +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1iV +b10 "# +b10 ^$ +b10 j$ +b10 v$ +b10 "% +b10 )% +b10 1% +b10 8% +b10 *& +b10 s& +b10 !' +b10 -' +b10 7' +b10 >' +b10 F' +b10 M' +b10 U' +b10 a' +b10 m' +b10 5, +b10 A, +b10 M, +b10 #- +b10 /- +b10 ;- +b10 "4 +b10 .4 +b10 :4 +0B4 +b10 I4 +b10 U4 +b10 a4 +b10 i4 +0l4 +b10 k; +b10 w; +b10 %< +b10 s> +b10 !? +b10 -? +b10 <@ +b10 H@ +b10 T@ +b10 `@ +b10 l@ +b10 x@ +b10 &A +b10 2A +b10 >A +b10 uV +b10 #W +b10 /W +b10 ;W +b10 GW +b10 SW +b10 _W +b10 kW +b10 wW #1000000 0! 0" -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0_+ -0J, -0K, -0D9 -0E9 -0{: -0|: -0g; -0h; -0R< -0S< -0*> -0+> -0t> -0u> -0nK -0oK -0GM -0HM -03N -04N -0|N -0}N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0x+ +0e, +0f, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0P; +0W> +0X> +0E? +0F? +00@ +01@ +0RB +0SB +0@C +0AC +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +0+R +02U +03U +0~U +0!V +0iV +0jV #1500000 -b1 TP -b0 7S -b10 UP -b0 8S -b1 xU -b0 zU -b10 yU -b0 {U +b1 -Y +b0 n[ +b10 .Y +b0 o[ +b1 Q^ +b0 S^ +b10 R^ +b0 T^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1o; -1R< -1*> -1t> -1nK -1GM -13N -1;N -1|N -b1 1# -b1 N# -b1 y# -b1 M$ -b1 \$ -b1 h$ -b1 t$ -b1 ~$ -b1 '% -b1 /% -b1 6% -b1 @% -b1 L% -b1 X% -b1 b% -b1 i% -b1 q% -b1 x% -b1 "& -b1 %& -b1 3& -b1 O& -b1 o& -b1 {& -b1 )' -b1 3' -b1 :' -b1 B' -b1 I' -b1 Q' -b1 ]' -b1 i' -b1 s' -b1 z' -b1 $( -b1 +( -b1 V) -b1 y) -b1 4* -b1 @* -b1 L* -b1 V* -b1 ]* -b1 e* -b1 l* -b1 t* -b1 "+ -b1 .+ -b1 8+ -b1 ?+ -b1 G+ -b1 N+ -b1 y+ -b1 ', -b1 3, -b1 e, -b1 q, -b1 }, -sHdlSome\x20(1) #. -b10 (. -b1001000110100 +. -1.. -1/. -10. -11. -b10 4. -b1001000110100 7. -1:. -1;. -1<. -1=. -b10 @. -b1001000110100 C. -b1111 F. -1H. -1I. -sHdlNone\x20(0) A1 -b1 J1 -b1 Z1 -b1 z1 -b1 ~1 -b1 (2 -b1 42 -b1 @2 -b1 N2 -b1 Z2 -b1 f2 -b1 t2 -sHdlSome\x20(1) v2 -1)3 -1*3 -b10 Y3 -b1 _9 -b1 k9 -b1 w9 -b1 8; -b1 D; -b1 P; -b1 m; -1#< -0$< -1%< -1)< -b1 +< -15< -b1 7< -1M< -b1 O< -b1 Q< -b1 X< -b1 ]< -b1 i< -b1 u< -b1 "= -b1 .= -b1 := -b1 E= -b1 Q= -b1 ]= -b1 h= -b1 t= -b1 "> -b1 E> -b1 Q> -b1 ]> -b1 1? -b1 =? -b1 I? -sHdlSome\x20(1) M@ -sLogical\x20(2) O@ -1Y@ -1Z@ -1e@ -1f@ -b110 p@ -1q@ -1r@ -1s@ -sHdlNone\x20(0) kC -sHdlSome\x20(1) mC -b1 tC -sHdlSome\x20(1) uC -b1 &D -sHdlSome\x20(1) 'D -b1 FD -sHdlSome\x20(1) GD -b1 JD -sHdlSome\x20(1) KD -b1 RD -b1 ^D -b1 jD -b1 xD -b1 &E -b1 2E -b1 @E -sHdlSome\x20(1) BE -1RE -1SE -1TE -b1 +L -b1 7L -b1 CL -b1 bM -b1 nM -b1 zM -b1 9N -1MN -0NN -1ON -1SN -b1 UN -1_N -b1 aN -1wN -b1 yN -b1 {N -b1 $O -b1 )O -b1 5O -b1 AO -b1 LO -b1 XO -b1 dO -b1 oO -b1 {O -b1 )P -b1 4P -b1 @P -b1 LP -#2000000 -0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#2500000 -b1 TP -b1 7S -b10 UP -b1 8S -b1 xU -b1 zU -b10 yU -b1 {U -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1p; -1R< -1*> -1t> -1nK -1GM -13N -14 -b10 ?4 -b10 _9 -b110 `9 -b10 k9 -b110 l9 -b10 w9 -b110 x9 -b10 8; -b110 9; -b10 D; -b110 E; -b10 P; -b110 Q; -b10 m; -0#< -0)< -b10 +< -05< -b10 7< -0M< -b10 O< -b10 Q< -b10 X< -b10 ]< -b110 ^< -b10 i< -b110 j< -b10 u< -b110 v< -b10 "= -b110 #= -b10 .= -b110 /= -b10 := -b110 ;= -b10 E= -b10 Q= -b10 ]= -b10 h= -b10 t= -b10 "> -b10 E> -b10 Q> -b10 ]> -b10 1? -b10 =? -b10 I? -sHdlSome\x20(1) t@ -sLogical\x20(2) v@ -b1 x@ -1"A -1#A -b1 &A -1.A -1/A -b1 2A -b110 9A -1:A -1;A -1# +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1M? +10@ +1RB +1@C +1{D +1)E +15E +1AE 1VE -1WE -b1 hF -b10 +L -b10 7L -b10 CL -b10 bM -b10 nM -b10 zM -b10 9N -0MN -0SN -b10 UN -0_N -b10 aN -0wN -b10 yN -b10 {N -b10 $O -b10 )O -b110 *O -b10 5O -b110 6O -b10 AO -b110 BO -b10 LO -b110 MO -b10 XO -b110 YO -b10 dO -b110 eO -b10 oO -b10 {O -b10 )P -b10 4P -b10 @P -b10 LP -#3000000 -0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#3500000 -b1 TP -b10 7S -b10 UP -b10 8S -b1 xU -b10 zU -b10 yU -b10 {U -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1q; -1R< -1*> -1t> -1nK -1GM -13N -1=N -1|N -b10 "# -b11 1# -b11 N# -b11 y# -b11 M$ -b11 \$ -b1010 ]$ -b11 h$ -b1010 i$ -b11 t$ -b1010 u$ -b11 ~$ -b1010 !% -b11 '% -b1010 (% -b11 /% -b1010 0% -b11 6% -b1010 7% -b11 @% -b11 L% -b11 X% -b11 b% -b11 i% -b11 q% -b11 x% -b11 "& -b11 %& -b10 (& -b11 3& -b11 O& -b11 o& -b1010 p& -b11 {& -b1010 |& -b11 )' -b1010 *' -b11 3' -b1010 4' -b11 :' -b1010 ;' -b11 B' -b1010 C' -b11 I' -b1010 J' -b11 Q' -b1010 R' -b11 ]' -b1010 ^' -b11 i' -b1010 j' -b11 s' -b11 z' -b11 $( -b11 +( -b11 V) -b11 y) -b11 4* -b11 @* -b11 L* -b11 V* -b11 ]* -b11 e* -b11 l* -b11 t* -b11 "+ -b11 .+ -b11 8+ -b11 ?+ -b11 G+ -b11 N+ -b11 y+ -b1010 z+ -b11 ', -b1010 (, -b11 3, -b1010 4, -b11 e, -b1010 f, -b11 q, -b1010 r, -b11 }, -b1010 ~, -sHdlSome\x20(1) q. -b10 u. -b110 v. -b1001000110100 y. -1|. -1}. -1~. -1!/ -b10 #/ -b110 $/ -b1001000110100 '/ -1*/ -1+/ -1,/ -1-/ -b10 // -b110 0/ -b1001000110100 3/ -b1111 6/ -18/ -19/ -sHdlNone\x20(0) M1 -b0 N1 -b11 V1 -b11 Z1 -b11 z1 -b11 ~1 -b11 (2 -b1010 )2 -b11 42 -b1010 52 -b11 @2 -b1010 A2 -b11 N2 -b1010 O2 -b11 Z2 -b1010 [2 -b11 f2 -b1010 g2 -b1010 n2 -b11 t2 -sHdlSome\x20(1) z2 -1/3 -103 -b10 $5 -b110 %5 -b11 _9 -b1010 `9 -b11 k9 -b1010 l9 -b11 w9 -b1010 x9 -b11 8; -b1010 9; -b11 D; -b1010 E; -b11 P; -b1010 Q; -b11 m; -1&< -0'< -1(< -1)< -0*< -b11 +< -15< -b11 7< -1M< -b11 O< -b11 Q< -b11 X< -b11 ]< -b1010 ^< -b11 i< -b1010 j< -b11 u< -b1010 v< -b11 "= -b1010 #= -b11 .= -b1010 /= -b11 := -b1010 ;= -b11 E= -b11 Q= -b11 ]= -b11 h= -b11 t= -b11 "> -b11 E> -b11 Q> -b11 ]> -b11 1? -b11 =? -b11 I? -sHdlSome\x20(1) =A -sLogical\x20(2) ?A -b10 AA -1IA -1JA -b10 MA -1UA -1VA -b10 YA -b110 `A -1aA -1bA -1cA -sHdlNone\x20(0) wC -b0 xC -sHdlSome\x20(1) yC -b10 zC -b11 "D -sHdlSome\x20(1) #D -b10 $D -b11 &D -b11 FD -b11 JD -b11 RD -b11 ^D -b11 jD -b11 xD -b11 &E -b11 2E -b11 @E -sHdlSome\x20(1) FE -1XE -1YE -1ZE -b10 NG -b11 +L -b11 7L -b11 CL -b11 bM -b11 nM -b11 zM -b11 9N -1PN -0QN -1RN -1SN -0TN -b11 UN -1_N -b11 aN -1wN -b11 yN -b11 {N -b11 $O -b11 )O -b1010 *O -b11 5O -b1010 6O -b11 AO -b1010 BO -b11 LO -b1010 MO -b11 XO -b1010 YO -b11 dO -b1010 eO -b11 oO -b11 {O -b11 )P -b11 4P -b11 @P -b11 LP -#4000000 -0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#4500000 -b1 TP -b11 7S -b10 UP -b11 8S -b1 xU -b11 zU -b10 yU -b11 {U -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1r; -1R< -1*> -1t> -1nK -1GM -13N -1>N -1|N -b11 "# -b100 1# -b100 N# -b100 y# -b100 M$ -b100 \$ -b1110 ]$ -b100 h$ -b1110 i$ -b100 t$ -b1110 u$ -b100 ~$ -b1110 !% -b100 '% -b1110 (% -b100 /% -b1110 0% -b100 6% -b1110 7% -b100 @% -b100 L% -b100 X% -b100 b% -b100 i% -b100 q% -b100 x% -b100 "& -b100 %& -b11 (& -b100 3& -b100 O& -b100 o& -b1110 p& -b100 {& -b1110 |& -b100 )' -b1110 *' -b100 3' -b1110 4' -b100 :' -b1110 ;' -b100 B' -b1110 C' -b100 I' -b1110 J' -b100 Q' -b1110 R' -b100 ]' -b1110 ^' -b100 i' -b1110 j' -b100 s' -b100 z' -b100 $( -b100 +( -b100 V) -b100 y) -b100 4* -b100 @* -b100 L* -b100 V* -b100 ]* -b100 e* -b100 l* -b100 t* -b100 "+ -b100 .+ -b100 8+ -b100 ?+ -b100 G+ -b100 N+ -b100 y+ -b1110 z+ -b100 ', -b1110 (, -b100 3, -b1110 4, -b100 e, -b1110 f, -b100 q, -b1110 r, -b100 }, -b1110 ~, -sHdlSome\x20(1) :/ -b11 >/ -b1010 ?/ -b1001000110100 B/ -1E/ -1F/ -1G/ -1H/ -b11 J/ -b1010 K/ -b1001000110100 N/ -1Q/ -1R/ -1S/ -1T/ -b11 V/ -b1010 W/ -b1001000110100 Z/ -b1111 ]/ +1bE +1nE +1zE +1*R +12U +1~U +1(V +1iV +b1 2# +b1 O# +b1 z# +b1 N$ +b1 ]$ +b1 i$ +b1 u$ +b1 !% +b1 (% +b1 0% +b1 7% +b1 B% +b1 N% +b1 Z% +b1 d% +b1 k% +b1 s% +b1 z% +b1 %& +b1 (& +b1 6& +b1 R& +b1 r& +b1 ~& +b1 ,' +b1 6' +b1 =' +b1 E' +b1 L' +b1 T' +b1 `' +b1 l' +b1 v' +b1 }' +b1 '( +b1 .( +b1 Y) +b1 |) +b1 7* +b1 C* +b1 O* +b1 Y* +b1 `* +b1 h* +b1 o* +b1 w* +b1 %+ +b1 1+ +b1 ;+ +b1 B+ +b1 J+ +b1 Q+ +b1 4, +b1 @, +b1 L, +b1 "- +b1 .- +b1 :- +sHdlSome\x20(1) T/ +b10 Y/ +b1001000110100 \/ 1_/ 1`/ -sHdlNone\x20(0) Q1 -b0 R1 -sHdlNone\x20(0) U1 -b0 V1 -sHdlNone\x20(0) Y1 -b0 Z1 -b100 z1 -b100 ~1 -b100 (2 -b1110 )2 -b100 42 -b1110 52 -b100 @2 -b1110 A2 -b100 N2 -b1110 O2 -b100 Z2 -b1110 [2 -b100 f2 -b1110 g2 -b1110 n2 -b100 t2 -sHdlSome\x20(1) |2 -123 -133 -b11 h5 -b1010 i5 -b100 _9 -b1110 `9 -b100 k9 -b1110 l9 -b100 w9 -b1110 x9 -b100 8; -b1110 9; -b100 D; -b1110 E; -b100 P; -b1110 Q; -b100 m; -0&< -0)< -05< -b100 7< -0M< -b100 O< -b100 Q< -b100 X< -b100 ]< -b1110 ^< -b100 i< -b1110 j< -b100 u< -b1110 v< -b100 "= -b1110 #= -b100 .= -b1110 /= -b100 := -b1110 ;= -b100 E= -b100 Q= -b100 ]= -b100 h= -b100 t= -b100 "> -b100 E> -b100 Q> -b100 ]> -b100 1? -b100 =? -b100 I? -sHdlSome\x20(1) dA -sLogical\x20(2) fA -b11 hA -1pA -1qA -b11 tA -1|A -1}A -b11 "B -b110 )B -1*B -1+B -1,B -sHdlNone\x20(0) {C -b0 |C -sHdlSome\x20(1) }C -b11 ~C -sHdlNone\x20(0) !D -b0 "D -sHdlNone\x20(0) %D -b0 &D -b100 FD -b100 JD -b100 RD -b100 ^D -b100 jD -b100 xD -b100 &E -b100 2E -b100 @E -sHdlSome\x20(1) HE -1[E -1\E -1]E -b11 4H -b100 +L -b100 7L -b100 CL -b100 bM -b100 nM -b100 zM -b100 9N -0PN -0SN -0_N -b100 aN -0wN -b100 yN -b100 {N -b100 $O -b100 )O -b1110 *O -b100 5O -b1110 6O -b100 AO -b1110 BO -b100 LO -b1110 MO -b100 XO -b1110 YO -b100 dO -b1110 eO -b100 oO -b100 {O -b100 )P -b100 4P -b100 @P -b100 LP -#5000000 -0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#5500000 -b1 TP -b100 7S -b10 UP -b100 8S -b1 xU -b100 zU -b10 yU -b100 {U -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1s; -1R< -1*> -1t> -1nK -1GM -13N -1?N -1|N -b100 "# -b101 1# -b101 N# -b101 y# -b101 M$ -b101 \$ -b10010 ]$ -b101 h$ -b10010 i$ -b101 t$ -b10010 u$ -b101 ~$ -b10010 !% -b101 '% -b10010 (% -b101 /% -b10010 0% -b101 6% -b10010 7% -b101 @% -b101 L% -b101 X% -b101 b% -b101 i% -b101 q% -b101 x% -b101 "& -b101 %& -b100 (& -b101 3& -b101 O& -b101 o& -b10010 p& -b101 {& -b10010 |& -b101 )' -b10010 *' -b101 3' -b10010 4' -b101 :' -b10010 ;' -b101 B' -b10010 C' -b101 I' -b10010 J' -b101 Q' -b10010 R' -b101 ]' -b10010 ^' -b101 i' -b10010 j' -b101 s' -b101 z' -b101 $( -b101 +( -b101 V) -b101 y) -b101 4* -b101 @* -b101 L* -b101 V* -b101 ]* -b101 e* -b101 l* -b101 t* -b101 "+ -b101 .+ -b101 8+ -b101 ?+ -b101 G+ -b101 N+ -b101 y+ -b10010 z+ -b101 ', -b10010 (, -b101 3, -b10010 4, -b101 e, -b10010 f, -b101 q, -b10010 r, -b101 }, -b10010 ~, -sHdlSome\x20(1) a/ -b100 e/ -b1110 f/ -b1001000110100 i/ +1a/ +1b/ +b10 e/ +b1001000110100 h/ +1k/ 1l/ 1m/ 1n/ -1o/ -b100 q/ -b1110 r/ -b1001000110100 u/ -1x/ -1y/ +b10 q/ +b1001000110100 t/ +b1111 w/ +b1000000000000 x/ 1z/ 1{/ -b100 }/ -b1110 ~/ -b1001000110100 #0 -b1111 &0 -1(0 -1)0 -sHdlNone\x20(0) ]1 -b0 ^1 -b101 f1 -b101 v1 -b101 z1 -b101 ~1 -b101 (2 -b10010 )2 -b101 42 -b10010 52 -b101 @2 -b10010 A2 -b101 N2 -b10010 O2 -b101 Z2 -b10010 [2 -b101 f2 -b10010 g2 -b10010 n2 -b101 t2 -sHdlSome\x20(1) ~2 -153 -163 -b100 N6 -b1110 O6 -b101 _9 -b10010 `9 -b101 k9 -b10010 l9 -b101 w9 -b10010 x9 -b101 8; -b10010 9; -b101 D; -b10010 E; -b101 P; -b10010 Q; -b101 m; -1,< -0-< -1.< -12< -b1 4< -15< -b101 7< -1M< -b101 O< -b101 Q< -b101 X< -b101 ]< -b10010 ^< -b101 i< -b10010 j< -b101 u< -b10010 v< -b101 "= -b10010 #= -b101 .= -b10010 /= -b101 := -b10010 ;= -b101 E= -b101 Q= -b101 ]= -b101 h= -b101 t= -b101 "> -b101 E> -b101 Q> -b101 ]> -b101 1? -b101 =? -b101 I? -sHdlSome\x20(1) -B -sLogical\x20(2) /B -b100 1B -19B -1:B -b100 =B -1EB -1FB -b100 IB -b110 PB -1QB -1RB -1SB -sHdlNone\x20(0) )D -b0 *D -sHdlSome\x20(1) +D -b100 ,D -b101 2D -sHdlSome\x20(1) 3D -b100 4D -b101 BD -sHdlSome\x20(1) CD -b100 DD -b101 FD -b101 JD -b101 RD -b101 ^D -b101 jD -b101 xD -b101 &E -b101 2E -b101 @E -sHdlSome\x20(1) JE -1^E -1_E -1`E -b100 xH -b101 +L -b101 7L -b101 CL -b101 bM -b101 nM -b101 zM -b101 9N +sHdlNone\x20(0) z2 +b1 %3 +b1 53 +b1 U3 +b1 Y3 +b1 !4 +b1 -4 +b1 94 +b1 H4 +b1 T4 +b1 `4 +b1 o4 +sHdlSome\x20(1) q4 +1$5 +1%5 +b10 T5 +b1 j; +b1 v; +b1 $< +b1 r> +b1 ~> +b1 ,? +b1 K? +1_? +0`? +1a? +1e? +b1 g? +1q? +b1 s? +1+@ +b1 -@ +b1 /@ +b1 6@ +b1 ;@ +b1 G@ +b1 S@ +b1 _@ +b1 k@ +b1 w@ +b1 %A +b1 1A +b1 =A +b1 HA +b1 TA +b1 `A +b1 lA +b1 xA +b1 &B +b1 2B +b1 >B +b1 JB +b1 mB +b1 yB +b1 'C +b1 [C +b1 gC +b1 sC +sHdlSome\x20(1) -D +sLogical\x20(2) .D +18D +19D +1DD +1ED +b110 OD +b1000000000100 PD +sHdlSome\x20(1) mD +sHdlSome\x20(1) /F +sLogical\x20(2) 1F +1;F +1M +b1000000000100 ?M +sHdlSome\x20(1) bM +sLogical\x20(2) cM +1mM +1nM +1yM +1zM +b110 &N +b1000000000100 'N +sHdlSome\x20(1) JN +sLogical\x20(2) KN +1UN 1VN -0WN -1XN -1\N -b1 ^N -1_N -b101 aN -1wN -b101 yN -b101 {N -b101 $O -b101 )O -b10010 *O -b101 5O -b10010 6O -b101 AO -b10010 BO -b101 LO -b10010 MO -b101 XO -b10010 YO -b101 dO -b10010 eO -b101 oO -b101 {O -b101 )P -b101 4P -b101 @P -b101 LP -#6000000 +1aN +1bN +b110 lN +b1000000000100 mN +sHdlSome\x20(1) 2O +sLogical\x20(2) 3O +1=O +1>O +1IO +1JO +b110 TO +b1000000000100 UO +sHdlSome\x20(1) xO +sLogical\x20(2) yO +1%P +1&P +11P +12P +b110

-0t> -0nK -0GM -03N -0|N -#6500000 -b1 TP -b101 7S -b10 UP -b101 8S -b1 xU -b101 zU -b10 yU -b101 {U +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#2500000 +b1 -Y +b1 n[ +b10 .Y +b1 o[ +b1 Q^ +b1 S^ +b10 R^ +b1 T^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1t; -1R< -1*> -1t> -1nK -1GM -13N -1@N -1|N -b101 "# -b110 1# -b110 N# -b110 y# -b110 M$ -b110 \$ -b10110 ]$ -b110 h$ -b10110 i$ -b110 t$ -b10110 u$ -b110 ~$ -b10110 !% -b110 '% -b10110 (% -b110 /% -b10110 0% -b110 6% -b10110 7% -b110 @% -b110 L% -b110 X% -b110 b% -b110 i% -b110 q% -b110 x% -b110 "& -b110 %& -b101 (& -b110 3& -b110 O& -b110 o& -b10110 p& -b110 {& -b10110 |& -b110 )' -b10110 *' -b110 3' -b10110 4' -b110 :' -b10110 ;' -b110 B' -b10110 C' -b110 I' -b10110 J' -b110 Q' -b10110 R' -b110 ]' -b10110 ^' -b110 i' -b10110 j' -b110 s' -b110 z' -b110 $( -b110 +( -b110 V) -b110 y) -b110 4* -b110 @* -b110 L* -b110 V* -b110 ]* -b110 e* -b110 l* -b110 t* -b110 "+ -b110 .+ -b110 8+ -b110 ?+ -b110 G+ -b110 N+ -b110 y+ -b10110 z+ -b110 ', -b10110 (, -b110 3, -b10110 4, -b110 e, -b10110 f, -b110 q, -b10110 r, -b110 }, -b10110 ~, -sHdlSome\x20(1) *0 -b101 .0 -b10010 /0 +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1N? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1)V +1iV +b1 ## +b10 2# +b10 O# +b10 z# +b10 N$ +b10 ]$ +b110 ^$ +b10 i$ +b110 j$ +b10 u$ +b110 v$ +b10 !% +b110 "% +b10 (% +b110 )% +b10 0% +b110 1% +b10 7% +b110 8% +b10 B% +b10 N% +b10 Z% +b10 d% +b10 k% +b10 s% +b10 z% +b10 %& +b10 (& +b1 +& +b10 6& +b10 R& +b10 r& +b110 s& +b10 ~& +b110 !' +b10 ,' +b110 -' +b10 6' +b110 7' +b10 =' +b110 >' +b10 E' +b110 F' +b10 L' +b110 M' +b10 T' +b110 U' +b10 `' +b110 a' +b10 l' +b110 m' +b10 v' +b10 }' +b10 '( +b10 .( +b10 Y) +b10 |) +b10 7* +b10 C* +b10 O* +b10 Y* +b10 `* +b10 h* +b10 o* +b10 w* +b10 %+ +b10 1+ +b10 ;+ +b10 B+ +b10 J+ +b10 Q+ +b10 4, +b110 5, +b10 @, +b110 A, +b10 L, +b110 M, +b10 "- +b110 #- +b10 .- +b110 /- +b10 :- +b110 ;- +sHdlSome\x20(1) |/ +b1 "0 +b10 #0 +b1001000110100 &0 +1)0 +1*0 +1+0 +1,0 +b1 .0 +b10 /0 b1001000110100 20 150 160 170 180 -b101 :0 -b10010 ;0 +b1 :0 +b10 ;0 b1001000110100 >0 -1A0 -1B0 -1C0 +b1111 A0 +b1000000000000 B0 1D0 -b101 F0 -b10010 G0 -b1001000110100 J0 -b1111 M0 -1O0 -1P0 -sHdlNone\x20(0) a1 -b0 b1 -sHdlNone\x20(0) e1 -b0 f1 -b110 v1 -b110 z1 -b110 ~1 -b110 (2 -b10110 )2 -b110 42 -b10110 52 -b110 @2 -b10110 A2 -b110 N2 -b10110 O2 -b110 Z2 -b10110 [2 -b110 f2 -b10110 g2 -b10110 n2 -b110 t2 -sHdlSome\x20(1) "3 -183 -193 -b101 47 -b10010 57 -b110 _9 -b10110 `9 -b110 k9 -b10110 l9 -b110 w9 -b10110 x9 -b110 8; -b10110 9; -b110 D; -b10110 E; -b110 P; -b10110 Q; -b110 m; -0,< -02< -b10 4< -05< -b110 7< -0M< -b110 O< -b110 Q< -b110 X< -b110 ]< -b10110 ^< -b110 i< -b10110 j< -b110 u< -b10110 v< -b110 "= -b10110 #= -b110 .= -b10110 /= -b110 := -b10110 ;= -b110 E= -b110 Q= -b110 ]= -b110 h= -b110 t= -b110 "> -b110 E> -b110 Q> -b110 ]> -b110 1? -b110 =? -b110 I? -sHdlSome\x20(1) TB -sLogical\x20(2) VB -b101 XB -1`B -1aB -b101 dB -1lB -1mB -b101 pB -b110 wB -1xB -1yB -1zB -sHdlNone\x20(0) -D -b0 .D -sHdlSome\x20(1) /D -b101 0D -sHdlNone\x20(0) 1D -b0 2D -b110 BD -b110 FD -b110 JD -b110 RD -b110 ^D -b110 jD -b110 xD -b110 &E -b110 2E -b110 @E -sHdlSome\x20(1) LE -1aE -1bE -1cE -b101 ^I -b110 +L -b110 7L -b110 CL -b110 bM -b110 nM -b110 zM -b110 9N -0VN -0\N -b10 ^N -0_N -b110 aN -0wN -b110 yN -b110 {N -b110 $O -b110 )O -b10110 *O -b110 5O -b10110 6O -b110 AO -b10110 BO -b110 LO -b10110 MO -b110 XO -b10110 YO -b110 dO -b10110 eO -b110 oO -b110 {O -b110 )P -b110 4P -b110 @P -b110 LP -#7000000 +1E0 +sHdlNone\x20(0) ~2 +b0 !3 +sHdlNone\x20(0) $3 +b0 %3 +b10 53 +b10 U3 +b10 Y3 +b10 !4 +b110 "4 +b10 -4 +b110 .4 +b10 94 +b110 :4 +b10 H4 +b110 I4 +b10 T4 +b110 U4 +b10 `4 +b110 a4 +b110 i4 +b10 o4 +sHdlSome\x20(1) s4 +1'5 +1(5 +b1 ;6 +b10 <6 +b10 j; +b110 k; +b10 v; +b110 w; +b10 $< +b110 %< +b10 r> +b110 s> +b10 ~> +b110 !? +b10 ,? +b110 -? +b10 K? +0_? +0e? +b10 g? +0q? +b10 s? +0+@ +b10 -@ +b10 /@ +b10 6@ +b10 ;@ +b110 <@ +b10 G@ +b110 H@ +b10 S@ +b110 T@ +b10 _@ +b110 `@ +b10 k@ +b110 l@ +b10 w@ +b110 x@ +b10 %A +b110 &A +b10 1A +b110 2A +b10 =A +b110 >A +b10 HA +b10 TA +b10 `A +b10 lA +b10 xA +b10 &B +b10 2B +b10 >B +b10 JB +b10 mB +b10 yB +b10 'C +b10 [C +b10 gC +b10 sC +b1 0D +b1 -0t> -0nK -0GM -03N -0|N -#7500000 -b1 TP -b110 7S -b10 UP -b110 8S -b1 xU -b110 zU -b10 yU -b110 {U +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#3500000 +b1 -Y +b10 n[ +b10 .Y +b10 o[ +b1 Q^ +b10 S^ +b10 R^ +b10 T^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1u; -1R< -1*> -1t> -1nK -1GM -13N -1AN -1|N -b110 "# -b111 1# -b111 N# -b111 y# -b111 M$ -b111 \$ -b11010 ]$ -b111 h$ -b11010 i$ -b111 t$ -b11010 u$ -b111 ~$ -b11010 !% -b111 '% -b11010 (% -b111 /% -b11010 0% -b111 6% -b11010 7% -b111 @% -b111 L% -b111 X% -b111 b% -b111 i% -b111 q% -b111 x% -b111 "& -b111 %& -b110 (& -b111 3& -b111 O& -b111 o& -b11010 p& -b111 {& -b11010 |& -b111 )' -b11010 *' -b111 3' -b11010 4' -b111 :' -b11010 ;' -b111 B' -b11010 C' -b111 I' -b11010 J' -b111 Q' -b11010 R' -b111 ]' -b11010 ^' -b111 i' -b11010 j' -b111 s' -b111 z' -b111 $( -b111 +( -b111 V) -b111 y) -b111 4* -b111 @* -b111 L* -b111 V* -b111 ]* -b111 e* -b111 l* -b111 t* -b111 "+ -b111 .+ -b111 8+ -b111 ?+ -b111 G+ -b111 N+ -b111 y+ -b11010 z+ -b111 ', -b11010 (, -b111 3, -b11010 4, -b111 e, -b11010 f, -b111 q, -b11010 r, -b111 }, -b11010 ~, -sHdlSome\x20(1) Q0 -b110 U0 -b10110 V0 -b1001000110100 Y0 -1\0 +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1O? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1*V +1iV +b10 ## +b11 2# +b11 O# +b11 z# +b11 N$ +b11 ]$ +b1010 ^$ +b11 i$ +b1010 j$ +b11 u$ +b1010 v$ +b11 !% +b1010 "% +b11 (% +b1010 )% +b11 0% +b1010 1% +b11 7% +b1010 8% +b11 B% +b11 N% +b11 Z% +b11 d% +b11 k% +b11 s% +b11 z% +b11 %& +b11 (& +b10 +& +b11 6& +b11 R& +b11 r& +b1010 s& +b11 ~& +b1010 !' +b11 ,' +b1010 -' +b11 6' +b1010 7' +b11 =' +b1010 >' +b11 E' +b1010 F' +b11 L' +b1010 M' +b11 T' +b1010 U' +b11 `' +b1010 a' +b11 l' +b1010 m' +b11 v' +b11 }' +b11 '( +b11 .( +b11 Y) +b11 |) +b11 7* +b11 C* +b11 O* +b11 Y* +b11 `* +b11 h* +b11 o* +b11 w* +b11 %+ +b11 1+ +b11 ;+ +b11 B+ +b11 J+ +b11 Q+ +b11 4, +b1010 5, +b11 @, +b1010 A, +b11 L, +b1010 M, +b11 "- +b1010 #- +b11 .- +b1010 /- +b11 :- +b1010 ;- +sHdlSome\x20(1) F0 +b10 J0 +b110 K0 +b1001000110100 N0 +1Q0 +1R0 +1S0 +1T0 +b10 V0 +b110 W0 +b1001000110100 Z0 1]0 1^0 1_0 -b110 a0 -b10110 b0 -b1001000110100 e0 -1h0 -1i0 -1j0 -1k0 -b110 m0 -b10110 n0 -b1001000110100 q0 -b1111 t0 -1v0 -1w0 -sHdlNone\x20(0) i1 -b0 j1 -b111 r1 -b111 v1 -b111 z1 -b111 ~1 -b111 (2 -b11010 )2 -b111 42 -b11010 52 -b111 @2 -b11010 A2 -b111 N2 -b11010 O2 -b111 Z2 -b11010 [2 -b111 f2 -b11010 g2 -b11010 n2 -b111 t2 -sHdlSome\x20(1) $3 -1;3 -1<3 -b110 x7 -b10110 y7 -b111 _9 -b11010 `9 -b111 k9 -b11010 l9 -b111 w9 -b11010 x9 -b111 8; -b11010 9; -b111 D; -b11010 E; -b111 P; -b11010 Q; -b111 m; -1/< -00< -11< -12< -03< -b11 4< -15< -06< -b111 7< -1M< -b111 O< -b111 Q< -b111 X< -b111 ]< -b11010 ^< -b111 i< -b11010 j< -b111 u< -b11010 v< -b111 "= -b11010 #= -b111 .= -b11010 /= -b111 := -b11010 ;= -b111 E= -b111 Q= -b111 ]= -b111 h= -b111 t= -b111 "> -b111 E> -b111 Q> -b111 ]> -b111 1? -b111 =? -b111 I? -sHdlSome\x20(1) {B -sLogical\x20(2) }B -b110 !C -1)C -1*C -b110 -C -15C -16C -b110 9C -b110 @C -1AC -1BC -1CC -sHdlNone\x20(0) 5D -b0 6D -sHdlSome\x20(1) 7D -b110 8D -b111 >D -sHdlSome\x20(1) ?D -b110 @D -b111 BD -b111 FD -b111 JD -b111 RD -b111 ^D -b111 jD -b111 xD -b111 &E -b111 2E -b111 @E -sHdlSome\x20(1) NE -1dE -1eE -1fE -b110 DJ -b111 +L -b111 7L -b111 CL -b111 bM -b111 nM -b111 zM -b111 9N -1YN -0ZN -1[N -1\N -0]N -b11 ^N -1_N -0`N -b111 aN -1wN -b111 yN -b111 {N -b111 $O -b111 )O -b11010 *O -b111 5O -b11010 6O -b111 AO -b11010 BO -b111 LO -b11010 MO -b111 XO -b11010 YO -b111 dO -b11010 eO -b111 oO -b111 {O -b111 )P -b111 4P -b111 @P -b111 LP -#8000000 +1`0 +b10 b0 +b110 c0 +b1001000110100 f0 +b1111 i0 +b1000000000000 j0 +1l0 +1m0 +sHdlNone\x20(0) (3 +b0 )3 +b11 13 +b11 53 +b11 U3 +b11 Y3 +b11 !4 +b1010 "4 +b11 -4 +b1010 .4 +b11 94 +b1010 :4 +b11 H4 +b1010 I4 +b11 T4 +b1010 U4 +b11 `4 +b1010 a4 +b1010 i4 +b11 o4 +sHdlSome\x20(1) u4 +1*5 +1+5 +b10 #7 +b110 $7 +b11 j; +b1010 k; +b11 v; +b1010 w; +b11 $< +b1010 %< +b11 r> +b1010 s> +b11 ~> +b1010 !? +b11 ,? +b1010 -? +b11 K? +1b? +0c? +1d? +1e? +0f? +b11 g? +1q? +b11 s? +1+@ +b11 -@ +b11 /@ +b11 6@ +b11 ;@ +b1010 <@ +b11 G@ +b1010 H@ +b11 S@ +b1010 T@ +b11 _@ +b1010 `@ +b11 k@ +b1010 l@ +b11 w@ +b1010 x@ +b11 %A +b1010 &A +b11 1A +b1010 2A +b11 =A +b1010 >A +b11 HA +b11 TA +b11 `A +b11 lA +b11 xA +b11 &B +b11 2B +b11 >B +b11 JB +b11 mB +b11 yB +b11 'C +b11 [C +b11 gC +b11 sC +b10 0D +b10 V +1?V +1@V +0AV +b11 BV +1LV +b11 NV +1dV +b11 fV +b11 hV +b11 oV +b11 tV +b1010 uV +b11 "W +b1010 #W +b11 .W +b1010 /W +b11 :W +b1010 ;W +b11 FW +b1010 GW +b11 RW +b1010 SW +b11 ^W +b1010 _W +b11 jW +b1010 kW +b11 vW +b1010 wW +b11 #X +b11 /X +b11 ;X +b11 GX +b11 SX +b11 _X +b11 kX +b11 wX +b11 %Y +#4000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#8500000 -b1 TP -b111 7S -b10 UP -b111 8S -b1 xU -b111 zU -b10 yU -b111 {U +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#4500000 +b1 -Y +b11 n[ +b10 .Y +b11 o[ +b1 Q^ +b11 S^ +b10 R^ +b11 T^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1v; -1R< -1*> -1t> -1nK -1GM -13N -1BN -1|N -b0 |" -0}" -b0 !# -b0 "# -b0 ## -0$# -b0 (# -0)# -0.# -b0 0# -b0 1# -b0 ;# -0<# -b0 @# -0A# -b0 J# -0K# -b0 M# -b0 N# -0v# -b0 x# -b0 y# -0I$ -0J$ -b0 L$ -b0 M$ -0P$ -0Q$ -0S$ -sHdlNone\x20(0) T$ -sHdlNone\x20(0) V$ -b0 W$ -sHdlNone\x20(0) X$ -b0 \$ -b0 ]$ -b0 `$ -0c$ -0d$ -0e$ -0f$ -b0 h$ -b0 i$ -b0 l$ -0o$ -0p$ -0q$ -0r$ -b0 t$ -b0 u$ -b0 x$ -b0 {$ -b0 ~$ -b0 !% -b0 $% -b0 '% -b0 (% -b0 +% -b0 /% -b0 0% -b0 3% -b0 6% -b0 7% -b0 :% -sHdlNone\x20(0) <% -sAddSub\x20(0) >% -b0 @% -0H% -0I% -b0 L% -0T% -0U% -b0 X% -b0 _% -0a% -b0 b% -0h% -b0 i% -0p% -b0 q% -0w% -b0 x% -sHdlNone\x20(0) ~% -b0 !& -b0 "& -sHdlNone\x20(0) #& -b0 $& -b0 %& -b0 && -b0 '& -b0 (& -b0 )& -b0 ,& -00& -b0 2& -b0 3& -0L& -b0 N& -b0 O& -b0 o& -b0 p& -b0 {& -b0 |& -b0 )' -b0 *' -b0 3' -b0 4' -b0 :' -b0 ;' -b0 B' -b0 C' -b0 I' -b0 J' -b0 Q' -b0 R' -b0 ]' -b0 ^' -b0 i' -b0 j' -b0 s' -b0 z' -b0 $( -b0 +( -sHdlNone\x20(0) 3( -sHdlNone\x20(0) 6( -b0 7( -sHdlNone\x20(0) 9( -b0 ;( -b0 b( -b0 R) -0S) -b0 U) -b0 V) -0u) -0v) -b0 x) -b0 y) -b0 4* -b0 @* -b0 L* -b0 V* -b0 ]* -b0 e* -b0 l* -b0 t* -b0 "+ -b0 .+ -b0 8+ -b0 ?+ -b0 G+ -b0 N+ -sHdlNone\x20(0) Y+ -b0 Z+ -sHdlNone\x20(0) \+ -b0 ]+ -sHdlNone\x20(0) v+ -b0 y+ -b0 z+ -b0 }+ -0", -0#, -0$, -0%, -b0 ', -b0 (, -b0 +, -0., -0/, -00, -01, -b0 3, -b0 4, -b0 7, -b0 :, -0;, -sHdlNone\x20(0) b, -b0 e, -b0 f, -b0 i, -0l, -0m, -0n, -0o, -b0 q, -b0 r, -b0 u, -0x, -0y, -0z, -0{, -b0 }, -b0 ~, -b0 #- -b0 &- -0'- -sHdlSome\x20(1) x0 -b111 |0 -b11010 }0 -b1001000110100 "1 -1%1 -1&1 +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1P? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1+V +1iV +b11 ## +b100 2# +b100 O# +b100 z# +b100 N$ +b100 ]$ +b1110 ^$ +b100 i$ +b1110 j$ +b100 u$ +b1110 v$ +b100 !% +b1110 "% +b100 (% +b1110 )% +b100 0% +b1110 1% +b100 7% +b1110 8% +b100 B% +b100 N% +b100 Z% +b100 d% +b100 k% +b100 s% +b100 z% +b100 %& +b100 (& +b11 +& +b100 6& +b100 R& +b100 r& +b1110 s& +b100 ~& +b1110 !' +b100 ,' +b1110 -' +b100 6' +b1110 7' +b100 =' +b1110 >' +b100 E' +b1110 F' +b100 L' +b1110 M' +b100 T' +b1110 U' +b100 `' +b1110 a' +b100 l' +b1110 m' +b100 v' +b100 }' +b100 '( +b100 .( +b100 Y) +b100 |) +b100 7* +b100 C* +b100 O* +b100 Y* +b100 `* +b100 h* +b100 o* +b100 w* +b100 %+ +b100 1+ +b100 ;+ +b100 B+ +b100 J+ +b100 Q+ +b100 4, +b1110 5, +b100 @, +b1110 A, +b100 L, +b1110 M, +b100 "- +b1110 #- +b100 .- +b1110 /- +b100 :- +b1110 ;- +sHdlSome\x20(1) n0 +b11 r0 +b1010 s0 +b1001000110100 v0 +1y0 +1z0 +1{0 +1|0 +b11 ~0 +b1010 !1 +b1001000110100 $1 1'1 1(1 -b111 *1 -b11010 +1 -b1001000110100 .1 -111 -121 -131 -141 -b111 61 -b11010 71 -b1001000110100 :1 -b1111 =1 -1?1 -1@1 -sHdlNone\x20(0) m1 -b0 n1 -sHdlNone\x20(0) q1 -b0 r1 -sHdlNone\x20(0) u1 -b0 v1 -sHdlNone\x20(0) y1 -b0 z1 -sHdlNone\x20(0) }1 -b0 ~1 -0#2 -sHdlNone\x20(0) $2 -b0 (2 -b0 )2 -b0 ,2 -0/2 -002 -012 -022 -b0 42 -b0 52 -b0 82 -0;2 -0<2 -0=2 -0>2 -b0 @2 -b0 A2 -b0 D2 -b0 G2 -0I2 -0J2 -sHdlNone\x20(0) K2 -b0 N2 -b0 O2 -b0 R2 -0U2 -0V2 -0W2 -0X2 -b0 Z2 -b0 [2 -b0 ^2 -0a2 -0b2 -0c2 -0d2 -b0 f2 -b0 g2 -b0 j2 -b0 m2 -b0 n2 -1q2 -b0 t2 -sHdlSome\x20(1) &3 -1>3 -1?3 -b111 ^8 -b11010 _8 -sHdlNone\x20(0) \9 -b0 _9 -b0 `9 -b0 c9 -0f9 -0g9 -0h9 -0i9 -b0 k9 -b0 l9 -b0 o9 -0r9 -0s9 -0t9 -0u9 -b0 w9 -b0 x9 -b0 {9 -b0 ~9 -0!: -sHdlNone\x20(0) 5; -b0 8; -b0 9; -b0 <; -0?; -0@; -0A; -0B; -b0 D; -b0 E; -b0 H; -0K; -0L; -0M; -0N; -b0 P; -b0 Q; -b0 T; -b0 W; -0X; -b1000 m; -0n; -0/< -02< -05< -0M< -b1000 O< -sHdlNone\x20(0) P< -b0 Q< -b1000 X< -0Y< -sHdlNone\x20(0) Z< -b0 ]< -b0 ^< -b0 a< -0d< -0e< -0f< -0g< -b0 i< -b0 j< -b0 m< -0p< -0q< -0r< -0s< -b0 u< -b0 v< -b0 y< -b0 |< -b0 "= -b0 #= -b0 &= -0)= -0*= -0+= -0,= -b0 .= -b0 /= -b0 2= -05= -06= -07= -08= -b0 := -b0 ;= -b0 >= -b0 A= -sHdlNone\x20(0) B= -sAddSub\x20(0) C= -b0 E= -0M= -0N= -b0 Q= -0Y= -0Z= -b0 ]= -b0 d= -sAddSub\x20(0) f= -b0 h= -0p= -0q= -b0 t= -0|= -0}= -b0 "> -b0 )> -sHdlNone\x20(0) B> -sAddSub\x20(0) C> -b0 E> -0M> -0N> -b0 Q> -0Y> -0Z> -b0 ]> -b0 d> -0e> -sHdlNone\x20(0) .? -sAddSub\x20(0) /? -b0 1? -09? -0:? -b0 =? +1)1 +1*1 +b11 ,1 +b1010 -1 +b1001000110100 01 +b1111 31 +b1000000000000 41 +161 +171 +sHdlNone\x20(0) ,3 +b0 -3 +sHdlNone\x20(0) 03 +b0 13 +sHdlNone\x20(0) 43 +b0 53 +b100 U3 +b100 Y3 +b100 !4 +b1110 "4 +b100 -4 +b1110 .4 +b100 94 +b1110 :4 +b100 H4 +b1110 I4 +b100 T4 +b1110 U4 +b100 `4 +b1110 a4 +b1110 i4 +b100 o4 +sHdlSome\x20(1) w4 +1-5 +1.5 +b11 i7 +b1010 j7 +b100 j; +b1110 k; +b100 v; +b1110 w; +b100 $< +b1110 %< +b100 r> +b1110 s> +b100 ~> +b1110 !? +b100 ,? +b1110 -? +b100 K? +0b? +0e? +0q? +b100 s? +0+@ +b100 -@ +b100 /@ +b100 6@ +b100 ;@ +b1110 <@ +b100 G@ +b1110 H@ +b100 S@ +b1110 T@ +b100 _@ +b1110 `@ +b100 k@ +b1110 l@ +b100 w@ +b1110 x@ +b100 %A +b1110 &A +b100 1A +b1110 2A +b100 =A +b1110 >A +b100 HA +b100 TA +b100 `A +b100 lA +b100 xA +b100 &B +b100 2B +b100 >B +b100 JB +b100 mB +b100 yB +b100 'C +b100 [C +b100 gC +b100 sC +b11 0D +b11 # +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> 0E? -0F? -b0 I? -b0 P? -0Q? -sHdlSome\x20(1) DC -sLogical\x20(2) FC -b111 HC -1PC -1QC -b111 TC -1\C -1]C -b111 `C +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#5500000 +b1 -Y +b100 n[ +b10 .Y +b100 o[ +b1 Q^ +b100 S^ +b10 R^ +b100 T^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1Q? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1,V +1iV +b100 ## +b101 2# +b101 O# +b101 z# +b101 N$ +b101 ]$ +b10010 ^$ +b101 i$ +b10010 j$ +b101 u$ +b10010 v$ +b101 !% +b10010 "% +b101 (% +b10010 )% +b101 0% +b10010 1% +b101 7% +b10010 8% +b101 B% +b101 N% +b101 Z% +b101 d% +b101 k% +b101 s% +b101 z% +b101 %& +b101 (& +b100 +& +b101 6& +b101 R& +b101 r& +b10010 s& +b101 ~& +b10010 !' +b101 ,' +b10010 -' +b101 6' +b10010 7' +b101 =' +b10010 >' +b101 E' +b10010 F' +b101 L' +b10010 M' +b101 T' +b10010 U' +b101 `' +b10010 a' +b101 l' +b10010 m' +b101 v' +b101 }' +b101 '( +b101 .( +b101 Y) +b101 |) +b101 7* +b101 C* +b101 O* +b101 Y* +b101 `* +b101 h* +b101 o* +b101 w* +b101 %+ +b101 1+ +b101 ;+ +b101 B+ +b101 J+ +b101 Q+ +b101 4, +b10010 5, +b101 @, +b10010 A, +b101 L, +b10010 M, +b101 "- +b10010 #- +b101 .- +b10010 /- +b101 :- +b10010 ;- +sHdlSome\x20(1) 81 +b100 <1 +b1110 =1 +b1001000110100 @1 +1C1 +1D1 +1E1 +1F1 +b100 H1 +b1110 I1 +b1001000110100 L1 +1O1 +1P1 +1Q1 +1R1 +b100 T1 +b1110 U1 +b1001000110100 X1 +b1111 [1 +b1000000000000 \1 +1^1 +1_1 +sHdlNone\x20(0) 83 +b0 93 +b101 A3 +b101 Q3 +b101 U3 +b101 Y3 +b101 !4 +b10010 "4 +b101 -4 +b10010 .4 +b101 94 +b10010 :4 +b101 H4 +b10010 I4 +b101 T4 +b10010 U4 +b101 `4 +b10010 a4 +b10010 i4 +b101 o4 +sHdlSome\x20(1) y4 +105 +115 +b100 Q8 +b1110 R8 +b101 j; +b10010 k; +b101 v; +b10010 w; +b101 $< +b10010 %< +b101 r> +b10010 s> +b101 ~> +b10010 !? +b101 ,? +b10010 -? +b101 K? +1h? +0i? +1j? +1n? +b1 p? +1q? +b101 s? +1+@ +b101 -@ +b101 /@ +b101 6@ +b101 ;@ +b10010 <@ +b101 G@ +b10010 H@ +b101 S@ +b10010 T@ +b101 _@ +b10010 `@ +b101 k@ +b10010 l@ +b101 w@ +b10010 x@ +b101 %A +b10010 &A +b101 1A +b10010 2A +b101 =A +b10010 >A +b101 HA +b101 TA +b101 `A +b101 lA +b101 xA +b101 &B +b101 2B +b101 >B +b101 JB +b101 mB +b101 yB +b101 'C +b101 [C +b101 gC +b101 sC +b100 0D +b100 # +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#6500000 +b1 -Y +b101 n[ +b10 .Y +b101 o[ +b1 Q^ +b101 S^ +b10 R^ +b101 T^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1R? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1-V +1iV +b101 ## +b110 2# +b110 O# +b110 z# +b110 N$ +b110 ]$ +b10110 ^$ +b110 i$ +b10110 j$ +b110 u$ +b10110 v$ +b110 !% +b10110 "% +b110 (% +b10110 )% +b110 0% +b10110 1% +b110 7% +b10110 8% +b110 B% +b110 N% +b110 Z% +b110 d% +b110 k% +b110 s% +b110 z% +b110 %& +b110 (& +b101 +& +b110 6& +b110 R& +b110 r& +b10110 s& +b110 ~& +b10110 !' +b110 ,' +b10110 -' +b110 6' +b10110 7' +b110 =' +b10110 >' +b110 E' +b10110 F' +b110 L' +b10110 M' +b110 T' +b10110 U' +b110 `' +b10110 a' +b110 l' +b10110 m' +b110 v' +b110 }' +b110 '( +b110 .( +b110 Y) +b110 |) +b110 7* +b110 C* +b110 O* +b110 Y* +b110 `* +b110 h* +b110 o* +b110 w* +b110 %+ +b110 1+ +b110 ;+ +b110 B+ +b110 J+ +b110 Q+ +b110 4, +b10110 5, +b110 @, +b10110 A, +b110 L, +b10110 M, +b110 "- +b10110 #- +b110 .- +b10110 /- +b110 :- +b10110 ;- +sHdlSome\x20(1) `1 +b101 d1 +b10010 e1 +b1001000110100 h1 +1k1 +1l1 +1m1 +1n1 +b101 p1 +b10010 q1 +b1001000110100 t1 +1w1 +1x1 +1y1 +1z1 +b101 |1 +b10010 }1 +b1001000110100 "2 +b1111 %2 +b1000000000000 &2 +1(2 +1)2 +sHdlNone\x20(0) <3 +b0 =3 +sHdlNone\x20(0) @3 +b0 A3 +b110 Q3 +b110 U3 +b110 Y3 +b110 !4 +b10110 "4 +b110 -4 +b10110 .4 +b110 94 +b10110 :4 +b110 H4 +b10110 I4 +b110 T4 +b10110 U4 +b110 `4 +b10110 a4 +b10110 i4 +b110 o4 +sHdlSome\x20(1) {4 +135 +145 +b101 99 +b10010 :9 +b110 j; +b10110 k; +b110 v; +b10110 w; +b110 $< +b10110 %< +b110 r> +b10110 s> +b110 ~> +b10110 !? +b110 ,? +b10110 -? +b110 K? +0h? +0n? +b10 p? +0q? +b110 s? +0+@ +b110 -@ +b110 /@ +b110 6@ +b110 ;@ +b10110 <@ +b110 G@ +b10110 H@ +b110 S@ +b10110 T@ +b110 _@ +b10110 `@ +b110 k@ +b10110 l@ +b110 w@ +b10110 x@ +b110 %A +b10110 &A +b110 1A +b10110 2A +b110 =A +b10110 >A +b110 HA +b110 TA +b110 `A +b110 lA +b110 xA +b110 &B +b110 2B +b110 >B +b110 JB +b110 mB +b110 yB +b110 'C +b110 [C b110 gC -1hC -1iC -1jC -sHdlNone\x20(0) 9D -b0 :D -sHdlSome\x20(1) ;D +b110 sC +b101 0D +b101 # +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#7500000 +b1 -Y +b110 n[ +b10 .Y +b110 o[ +b1 Q^ +b110 S^ +b10 R^ +b110 T^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1S? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1.V +1iV +b110 ## +b111 2# +b111 O# +b111 z# +b111 N$ +b111 ]$ +b11010 ^$ +b111 i$ +b11010 j$ +b111 u$ +b11010 v$ +b111 !% +b11010 "% +b111 (% +b11010 )% +b111 0% +b11010 1% +b111 7% +b11010 8% +b111 B% +b111 N% +b111 Z% +b111 d% +b111 k% +b111 s% +b111 z% +b111 %& +b111 (& +b110 +& +b111 6& +b111 R& +b111 r& +b11010 s& +b111 ~& +b11010 !' +b111 ,' +b11010 -' +b111 6' +b11010 7' +b111 =' +b11010 >' +b111 E' +b11010 F' +b111 L' +b11010 M' +b111 T' +b11010 U' +b111 `' +b11010 a' +b111 l' +b11010 m' +b111 v' +b111 }' +b111 '( +b111 .( +b111 Y) +b111 |) +b111 7* +b111 C* +b111 O* +b111 Y* +b111 `* +b111 h* +b111 o* +b111 w* +b111 %+ +b111 1+ +b111 ;+ +b111 B+ +b111 J+ +b111 Q+ +b111 4, +b11010 5, +b111 @, +b11010 A, +b111 L, +b11010 M, +b111 "- +b11010 #- +b111 .- +b11010 /- +b111 :- +b11010 ;- +sHdlSome\x20(1) *2 +b110 .2 +b10110 /2 +b1001000110100 22 +152 +162 +172 +182 +b110 :2 +b10110 ;2 +b1001000110100 >2 +1A2 +1B2 +1C2 +1D2 +b110 F2 +b10110 G2 +b1001000110100 J2 +b1111 M2 +b1000000000000 N2 +1P2 +1Q2 +sHdlNone\x20(0) D3 +b0 E3 +b111 M3 +b111 Q3 +b111 U3 +b111 Y3 +b111 !4 +b11010 "4 +b111 -4 +b11010 .4 +b111 94 +b11010 :4 +b111 H4 +b11010 I4 +b111 T4 +b11010 U4 +b111 `4 +b11010 a4 +b11010 i4 +b111 o4 +sHdlSome\x20(1) }4 +165 +175 +b110 !: +b10110 ": +b111 j; +b11010 k; +b111 v; +b11010 w; +b111 $< +b11010 %< +b111 r> +b11010 s> +b111 ~> +b11010 !? +b111 ,? +b11010 -? +b111 K? +1k? +0l? +1m? +1n? +0o? +b11 p? +1q? +0r? +b111 s? +1+@ +b111 -@ +b111 /@ +b111 6@ +b111 ;@ +b11010 <@ +b111 G@ +b11010 H@ +b111 S@ +b11010 T@ +b111 _@ +b11010 `@ +b111 k@ +b11010 l@ +b111 w@ +b11010 x@ +b111 %A +b11010 &A +b111 1A +b11010 2A +b111 =A +b11010 >A +b111 HA +b111 TA +b111 `A +b111 lA +b111 xA +b111 &B +b111 2B +b111 >B +b111 JB +b111 mB +b111 yB +b111 'C +b111 [C +b111 gC +b111 sC +b110 0D +b110 # +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#8500000 +b1 -Y +b111 n[ +b10 .Y +b111 o[ +b1 Q^ +b111 S^ +b10 R^ +b111 T^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +1T? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1/V +1iV +b111 ## +b10 1# +b1000 2# +b0 <# +0=# +b0 A# +0B# +b0 K# +0L# +b0 N# +b0 O# +b10 y# +b1000 z# +0J$ +0K$ +b0 M$ +b0 N$ +0Q$ +0T$ +b1 V$ +sHdlNone\x20(0) W$ +b0 X$ +b1000 ]$ +b11110 ^$ +b1000 i$ +b11110 j$ +b1000 u$ +b11110 v$ +b1000 !% +b11110 "% +b1000 (% +b11110 )% +b1000 0% +b11110 1% +b1000 7% +b11110 8% +sHdlNone\x20(0) >% +sAddSub\x20(0) @% +b0 B% +0J% +0K% +b0 N% +0V% +0W% +b0 Z% +b0 a% +0c% +b0 d% +0j% +b0 k% +0r% +b0 s% +0y% +b0 z% +b0 "& +b10 $& +b1000 %& +sHdlNone\x20(0) && +b0 '& +b0 (& +b111 +& +b10 5& +b1000 6& +b10 Q& +b1000 R& +b1000 r& +b11110 s& +b1000 ~& +b11110 !' +b1000 ,' +b11110 -' +b1000 6' +b11110 7' +b1000 =' +b11110 >' +b1000 E' +b11110 F' +b1000 L' +b11110 M' +b1000 T' +b11110 U' +b1000 `' +b11110 a' +b1000 l' +b11110 m' +b1000 v' +b1000 }' +b1000 '( +b1000 .( +sHdlNone\x20(0) 6( +b1 =( +b0 >( +b0 e( +b0 U) +0V) +b0 X) +b0 Y) +0x) +0y) +b0 {) +b0 |) +b0 7* +b0 C* +b0 O* +b0 Y* +b0 `* +b0 h* +b0 o* +b0 w* +b0 %+ +b0 1+ +b0 ;+ +b0 B+ +b0 J+ +b0 Q+ +sHdlNone\x20(0) \+ +b0 ]+ +sHdlNone\x20(0) _+ +b0 `+ +sHdlNone\x20(0) 1, +b0 4, +b0 5, +b0 8, +0;, +0<, +0=, +0>, +b0 @, +b0 A, +b0 D, +0G, +0H, +0I, +0J, +b0 L, +b0 M, +b0 P, +b0 S, +b0 T, +0U, +sHdlNone\x20(0) }, +b0 "- +b0 #- +b0 &- +0)- +0*- +0+- +0,- +b0 .- +b0 /- +b0 2- +05- +06- +07- +08- +b0 :- +b0 ;- +b0 >- +b0 A- +b0 B- +0C- +sHdlSome\x20(1) R2 +b111 V2 +b11010 W2 +b1001000110100 Z2 +1]2 +1^2 +1_2 +1`2 +b111 b2 +b11010 c2 +b1001000110100 f2 +1i2 +1j2 +1k2 +1l2 +b111 n2 +b11010 o2 +b1001000110100 r2 +b1111 u2 +b1000000000000 v2 +1x2 +1y2 +sHdlNone\x20(0) H3 +b0 I3 +sHdlNone\x20(0) L3 +b0 M3 +sHdlNone\x20(0) P3 +b0 Q3 +sHdlNone\x20(0) T3 +b0 U3 +sHdlNone\x20(0) X3 +b0 Y3 +0\3 +sHdlNone\x20(0) {3 +b0 !4 +b0 "4 +b0 %4 +0(4 +0)4 +0*4 +0+4 +b0 -4 +b0 .4 +b0 14 +044 +054 +064 +074 +b0 94 +b0 :4 +b0 =4 +b0 @4 +b0 A4 +0C4 +0D4 +sHdlNone\x20(0) E4 +b0 H4 +b0 I4 +b0 L4 +0O4 +0P4 +0Q4 +0R4 +b0 T4 +b0 U4 +b0 X4 +0[4 +0\4 +0]4 +0^4 +b0 `4 +b0 a4 +b0 d4 +b0 g4 +b0 h4 +b0 i4 +1l4 +b0 o4 +sHdlSome\x20(1) !5 +195 +1:5 +b111 g: +b11010 h: +sHdlNone\x20(0) g; +b0 j; +b0 k; +b0 n; +0q; +0r; +0s; +0t; +b0 v; +b0 w; +b0 z; +0}; +0~; +0!< +0"< +b0 $< +b0 %< +b0 (< +b0 +< +b0 ,< +0-< +sHdlNone\x20(0) o> +b0 r> +b0 s> +b0 v> +0y> +0z> +0{> +0|> +b0 ~> +b0 !? +b0 $? +0'? +0(? +0)? +0*? +b0 ,? +b0 -? +b0 0? +b0 3? +b0 4? +05? +b1000 K? +0L? +0k? +0n? +0q? +0+@ +b1000 -@ +sHdlNone\x20(0) .@ +b0 /@ +b1000 6@ +07@ +b1000 ;@ +b11110 <@ +b1000 G@ +b11110 H@ +b1000 S@ +b11110 T@ +b1000 _@ +b11110 `@ +b1000 k@ +b11110 l@ +b1000 w@ +b11110 x@ +b1000 %A +b11110 &A +b1000 1A +b11110 2A +b1000 =A +b11110 >A +sHdlNone\x20(0) EA +sAddSub\x20(0) FA +b0 HA +0PA +0QA +b0 TA +0\A +0]A +b0 `A +b0 gA +b0 hA +sAddSub\x20(0) jA +b0 lA +0tA +0uA +b0 xA +0"B +0#B +b0 &B +b0 -B +b0 .B +sAddSub\x20(0) 0B +b0 2B +0:B +0;B +b0 >B +0FB +0GB +b0 JB +b0 QB +sAddSub\x20(0) kB +b1000 mB +b11110 nB +b1001000110100 qB +1tB +1wB +b1000 yB +b11110 zB +b1001000110100 }B +1"C +1%C +b1000 'C +b11110 (C +b1001000110100 +C +b1111 .C +b1000000000000 /C +sAddSub\x20(0) YC +b1000 [C +b11110 \C +b1001000110100 _C +1bC +1eC +b1000 gC +b11110 hC +b1001000110100 kC +1nC +1qC +b1000 sC +b11110 tC +b1001000110100 wC +b1111 zC +b1000000000000 {C +b111 0D b111 D -sHdlNone\x20(0) AD -b0 BD -sHdlNone\x20(0) ED -b0 FD -sHdlNone\x20(0) ID -b0 JD -0MD -sHdlNone\x20(0) ND -sAddSub\x20(0) PD -b0 RD -0ZD -0[D -b0 ^D -0fD -0gD -b0 jD -b0 qD -0rD -0sD -0tD -sHdlNone\x20(0) uD -sAddSub\x20(0) vD -b0 xD -0"E -0#E -b0 &E -0.E -0/E -b0 2E -b0 9E -b0 @E -sHdlSome\x20(1) PE -1gE -1hE -1iE -b111 *K -sHdlNone\x20(0) (L -sAddSub\x20(0) )L -b0 +L -03L -04L +b111 HD +b111 nD +sHdlNone\x20(0) /F +sAddSub\x20(0) 1F +b0 3F +0;F +0# +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#9500000 +b10 -Y +b1000 n[ +b10 Q^ +b1000 S^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +10V +1iV +b1001 2# +b1001 z# +b1001 ]$ +b1001 i$ +b1001 u$ +b1001 !% +b1001 (% +b1001 0% +b1001 7% +b1001 %& +b1001 6& +b1001 R& +b1001 r& +b1001 ~& +b1001 ,' +b1001 6' +b1001 =' +b1001 E' +b1001 L' +b1001 T' +b1001 `' +b1001 l' +b1001 v' +b1001 }' +b1001 '( +b1001 .( +b1001 ;@ +b1001 G@ +b1001 S@ +b1001 _@ +b1001 k@ +b1001 w@ +b1001 %A +b1001 1A +b1001 =A +b1001 mB +b1001 yB +b1001 'C +b1001 [C +b1001 gC +b1001 sC +sHdlNone\x20(0) -D +sAddSub\x20(0) .D +b0 0D +08D +09D +b0 M +b0 ?M +b0 [M +sHdlNone\x20(0) bM +sAddSub\x20(0) cM +b0 eM +0mM +0nM +b0 qM +0yM +0zM +b0 }M +b0 &N +b0 'N +b0 CN +sHdlNone\x20(0) JN +sAddSub\x20(0) KN +b0 MN +0UN +0VN +b0 YN +0aN +0bN +b0 eN +b0 lN +b0 mN +b0 +O +sHdlNone\x20(0) 2O +sAddSub\x20(0) 3O b0 5O -b0 6O -b0 9O -0O -0?O b0 AO -b0 BO -b0 EO -b0 HO -b0 LO +0IO +0JO b0 MO -b0 PO -0SO -0TO -0UO -0VO -b0 XO -b0 YO -b0 \O -0_O -0`O -0aO -0bO -b0 dO -b0 eO -b0 hO -b0 kO -sHdlNone\x20(0) lO -sAddSub\x20(0) mO -b0 oO -0wO -0xO +b0 TO +b0 UO +b0 qO +sHdlNone\x20(0) xO +sAddSub\x20(0) yO b0 {O 0%P 0&P b0 )P -b0 0P -sAddSub\x20(0) 2P -b0 4P -0

-0t> -0nK -0GM -03N -0|N -#9500000 -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +01P +02P +b0 5P +b0

-0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #10500000 +b10 -Y +b1001 n[ +b10 Q^ +b1001 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +11V +1iV +b1010 2# +b1010 z# +b1010 ]$ +b1010 i$ +b1010 u$ +b1010 !% +b1010 (% +b1010 0% +b1010 7% +b1010 %& +b1010 6& +b1010 R& +b1010 r& +b1010 ~& +b1010 ,' +b1010 6' +b1010 =' +b1010 E' +b1010 L' +b1010 T' +b1010 `' +b1010 l' +b1010 v' +b1010 }' +b1010 '( +b1010 .( +b1010 ;@ +b1010 G@ +b1010 S@ +b1010 _@ +b1010 k@ +b1010 w@ +b1010 %A +b1010 1A +b1010 =A +b1010 mB +b1010 yB +b1010 'C +b1010 [C +b1010 gC +b1010 sC +sHdlSome\x20(1) WF +b1001 [F +b11110 \F +b1001000110100 _F +1bF +1cF +1dF +1eF +b1001 gF +b11110 hF +b1001000110100 kF +1nF +1oF +1pF +1qF +b1001 sF +b11110 tF +b1001000110100 wF +b1111 zF +b1000000000000 {F +1}F +1~F +sHdlNone\x20(0) YI +b0 ZI +sHdlNone\x20(0) ]I +b0 ^I +b10 nI +b10 0J +b10 4J +b1010 ZJ +b1010 fJ +b1010 rJ +b1010 #K +b1010 /K +b1010 ;K +b1010 JK +sHdlSome\x20(1) NK +1`K +1aK +b1001 tL +b11110 uL +b1010 ER +b1010 QR +b1010 ]R +b1010 MU +b1010 YU +b1010 eU +b1010 &V +0OV +0UV +b10 WV +0aV +b10 cV +0dV +b1010 fV +b1010 hV +b1010 oV +b1010 tV +b1010 "W +b1010 .W +b1010 :W +b1010 FW +b1010 RW +b1010 ^W +b1010 jW +b1010 vW #11000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #11500000 +b10 -Y +b1010 n[ +b10 Q^ +b1010 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +12V +1iV +b1011 2# +b1011 z# +b1011 ]$ +b1011 i$ +b1011 u$ +b1011 !% +b1011 (% +b1011 0% +b1011 7% +b1011 %& +b1011 6& +b1011 R& +b1011 r& +b1011 ~& +b1011 ,' +b1011 6' +b1011 =' +b1011 E' +b1011 L' +b1011 T' +b1011 `' +b1011 l' +b1011 v' +b1011 }' +b1011 '( +b1011 .( +b1011 ;@ +b1011 G@ +b1011 S@ +b1011 _@ +b1011 k@ +b1011 w@ +b1011 %A +b1011 1A +b1011 =A +b1011 mB +b1011 yB +b1011 'C +b1011 [C +b1011 gC +b1011 sC +sHdlSome\x20(1) !G +b1010 %G +b11110 &G +b1001000110100 )G +1,G +1-G +1.G +1/G +b1010 1G +b11110 2G +b1001000110100 5G +18G +19G +1:G +1;G +b1010 =G +b11110 >G +b1001000110100 AG +b1111 DG +b1000000000000 EG +1GG +1HG +sHdlNone\x20(0) aI +b0 bI +b11 jI +b11 nI +b11 0J +b11 4J +b1011 ZJ +b1011 fJ +b1011 rJ +b1011 #K +b1011 /K +b1011 ;K +b1011 JK +sHdlSome\x20(1) PK +1cK +1dK +b1010 \M +b11110 ]M +b1011 ER +b1011 QR +b1011 ]R +b1011 MU +b1011 YU +b1011 eU +b1011 &V +1RV +0SV +1TV +1UV +0VV +b11 WV +1aV +b11 cV +1dV +b1011 fV +b1011 hV +b1011 oV +b1011 tV +b1011 "W +b1011 .W +b1011 :W +b1011 FW +b1011 RW +b1011 ^W +b1011 jW +b1011 vW #12000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #12500000 +b10 -Y +b1011 n[ +b10 Q^ +b1011 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +13V +1iV +b1100 2# +b1100 z# +b1100 ]$ +b1100 i$ +b1100 u$ +b1100 !% +b1100 (% +b1100 0% +b1100 7% +b1100 %& +b1100 6& +b1100 R& +b1100 r& +b1100 ~& +b1100 ,' +b1100 6' +b1100 =' +b1100 E' +b1100 L' +b1100 T' +b1100 `' +b1100 l' +b1100 v' +b1100 }' +b1100 '( +b1100 .( +b1100 ;@ +b1100 G@ +b1100 S@ +b1100 _@ +b1100 k@ +b1100 w@ +b1100 %A +b1100 1A +b1100 =A +b1100 mB +b1100 yB +b1100 'C +b1100 [C +b1100 gC +b1100 sC +sHdlSome\x20(1) IG +b1011 MG +b11110 NG +b1001000110100 QG +1TG +1UG +1VG +1WG +b1011 YG +b11110 ZG +b1001000110100 ]G +1`G +1aG +1bG +1cG +b1011 eG +b11110 fG +b1001000110100 iG +b1111 lG +b1000000000000 mG +1oG +1pG +sHdlNone\x20(0) eI +b0 fI +sHdlNone\x20(0) iI +b0 jI +sHdlNone\x20(0) mI +b0 nI +b100 0J +b100 4J +b1100 ZJ +b1100 fJ +b1100 rJ +b1100 #K +b1100 /K +b1100 ;K +b1100 JK +sHdlSome\x20(1) RK +1fK +1gK +b1011 DN +b11110 EN +b1100 ER +b1100 QR +b1100 ]R +b1100 MU +b1100 YU +b1100 eU +b1100 &V +0RV +0UV +0aV +b100 cV +0dV +b1100 fV +b1100 hV +b1100 oV +b1100 tV +b1100 "W +b1100 .W +b1100 :W +b1100 FW +b1100 RW +b1100 ^W +b1100 jW +b1100 vW #13000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #13500000 +b10 -Y +b1100 n[ +b10 Q^ +b1100 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +14V +1iV +b1101 2# +b1101 z# +b1101 ]$ +b1101 i$ +b1101 u$ +b1101 !% +b1101 (% +b1101 0% +b1101 7% +b1101 %& +b1101 6& +b1101 R& +b1101 r& +b1101 ~& +b1101 ,' +b1101 6' +b1101 =' +b1101 E' +b1101 L' +b1101 T' +b1101 `' +b1101 l' +b1101 v' +b1101 }' +b1101 '( +b1101 .( +b1101 ;@ +b1101 G@ +b1101 S@ +b1101 _@ +b1101 k@ +b1101 w@ +b1101 %A +b1101 1A +b1101 =A +b1101 mB +b1101 yB +b1101 'C +b1101 [C +b1101 gC +b1101 sC +sHdlSome\x20(1) qG +b1100 uG +b11110 vG +b1001000110100 yG +1|G +1}G +1~G +1!H +b1100 #H +b11110 $H +b1001000110100 'H +1*H +1+H +1,H +1-H +b1100 /H +b11110 0H +b1001000110100 3H +b1111 6H +b1000000000000 7H +19H +1:H +sHdlNone\x20(0) qI +b0 rI +b101 zI +b101 ,J +b101 0J +b101 4J +b1101 ZJ +b1101 fJ +b1101 rJ +b1101 #K +b1101 /K +b1101 ;K +b1101 JK +sHdlSome\x20(1) TK +1iK +1jK +b1100 ,O +b11110 -O +b1101 ER +b1101 QR +b1101 ]R +b1101 MU +b1101 YU +b1101 eU +b1101 &V +1XV +0YV +1ZV +1^V +b1 `V +1aV +b101 cV +1dV +b1101 fV +b1101 hV +b1101 oV +b1101 tV +b1101 "W +b1101 .W +b1101 :W +b1101 FW +b1101 RW +b1101 ^W +b1101 jW +b1101 vW #14000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #14500000 +b10 -Y +b1101 n[ +b10 Q^ +b1101 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +15V +1iV +b1110 2# +b1110 z# +b1110 ]$ +b1110 i$ +b1110 u$ +b1110 !% +b1110 (% +b1110 0% +b1110 7% +b1110 %& +b1110 6& +b1110 R& +b1110 r& +b1110 ~& +b1110 ,' +b1110 6' +b1110 =' +b1110 E' +b1110 L' +b1110 T' +b1110 `' +b1110 l' +b1110 v' +b1110 }' +b1110 '( +b1110 .( +b1110 ;@ +b1110 G@ +b1110 S@ +b1110 _@ +b1110 k@ +b1110 w@ +b1110 %A +b1110 1A +b1110 =A +b1110 mB +b1110 yB +b1110 'C +b1110 [C +b1110 gC +b1110 sC +sHdlSome\x20(1) ;H +b1101 ?H +b11110 @H +b1001000110100 CH +1FH +1GH +1HH +1IH +b1101 KH +b11110 LH +b1001000110100 OH +1RH +1SH +1TH +1UH +b1101 WH +b11110 XH +b1001000110100 [H +b1111 ^H +b1000000000000 _H +1aH +1bH +sHdlNone\x20(0) uI +b0 vI +sHdlNone\x20(0) yI +b0 zI +b110 ,J +b110 0J +b110 4J +b1110 ZJ +b1110 fJ +b1110 rJ +b1110 #K +b1110 /K +b1110 ;K +b1110 JK +sHdlSome\x20(1) VK +1lK +1mK +b1101 rO +b11110 sO +b1110 ER +b1110 QR +b1110 ]R +b1110 MU +b1110 YU +b1110 eU +b1110 &V +0XV +0^V +b10 `V +0aV +b110 cV +0dV +b1110 fV +b1110 hV +b1110 oV +b1110 tV +b1110 "W +b1110 .W +b1110 :W +b1110 FW +b1110 RW +b1110 ^W +b1110 jW +b1110 vW #15000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #15500000 +b10 -Y +b1110 n[ +b10 Q^ +b1110 S^ 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +16V +1iV +b1111 2# +b1111 z# +b1111 ]$ +b1111 i$ +b1111 u$ +b1111 !% +b1111 (% +b1111 0% +b1111 7% +b1111 %& +b1111 6& +b1111 R& +b1111 r& +b1111 ~& +b1111 ,' +b1111 6' +b1111 =' +b1111 E' +b1111 L' +b1111 T' +b1111 `' +b1111 l' +b1111 v' +b1111 }' +b1111 '( +b1111 .( +b1111 ;@ +b1111 G@ +b1111 S@ +b1111 _@ +b1111 k@ +b1111 w@ +b1111 %A +b1111 1A +b1111 =A +b1111 mB +b1111 yB +b1111 'C +b1111 [C +b1111 gC +b1111 sC +sHdlSome\x20(1) cH +b1110 gH +b11110 hH +b1001000110100 kH +1nH +1oH +1pH +1qH +b1110 sH +b11110 tH +b1001000110100 wH +1zH +1{H +1|H +1}H +b1110 !I +b11110 "I +b1001000110100 %I +b1111 (I +b1000000000000 )I +1+I +1,I +sHdlNone\x20(0) }I +b0 ~I +b111 (J +b111 ,J +b111 0J +b111 4J +b1111 ZJ +b1111 fJ +b1111 rJ +b1111 #K +b1111 /K +b1111 ;K +b1111 JK +sHdlSome\x20(1) XK +1oK +1pK +b1110 ZP +b11110 [P +b1111 ER +b1111 QR +b1111 ]R +b1111 MU +b1111 YU +b1111 eU +b1111 &V +1[V +0\V +1]V +1^V +0_V +b11 `V +1aV +0bV +b111 cV +1dV +0eV +b1111 fV +b1111 hV +b1111 oV +b1111 tV +b1111 "W +b1111 .W +b1111 :W +b1111 FW +b1111 RW +b1111 ^W +b1111 jW +b1111 vW #16000000 0! +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV +#16500000 +b10 -Y +b1111 n[ +b10 Q^ +b1111 S^ +1! +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +17V +1iV +b0 }" 0~" +b0 "# +b0 ## +b0 $# 0%# +b0 )# 0*# 0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# +b0 1# +b0 2# 0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N -#16500000 -1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +b0 y# +b0 z# +0R$ +sHdlNone\x20(0) U$ +b0 V$ +sHdlNone\x20(0) Y$ +b0 ]$ +b0 ^$ +b0 a$ +0d$ +0e$ +0f$ +0g$ +b0 i$ +b0 j$ +b0 m$ +0p$ +0q$ +0r$ +0s$ +b0 u$ +b0 v$ +b0 y$ +b0 |$ +b0 !% +b0 "% +b0 %% +b0 (% +b0 )% +b0 ,% +b0 0% +b0 1% +b0 4% +b0 7% +b0 8% +b0 ;% +b0 =% +sHdlNone\x20(0) #& +b0 $& +b0 %& +b0 )& +b0 *& +b0 +& +b0 ,& +b0 /& +03& +b0 5& +b0 6& +0O& +b0 Q& +b0 R& +b0 r& +b0 s& +b0 ~& +b0 !' +b0 ,' +b0 -' +b0 6' +b0 7' +b0 =' +b0 >' +b0 E' +b0 F' +b0 L' +b0 M' +b0 T' +b0 U' +b0 `' +b0 a' +b0 l' +b0 m' +b0 v' +b0 }' +b0 '( +b0 .( +sHdlNone\x20(0) 9( +b0 :( +sHdlNone\x20(0) <( +b0 =( +sHdlNone\x20(0) 8@ +b0 ;@ +b0 <@ +b0 ?@ +0B@ +0C@ +0D@ +0E@ +b0 G@ +b0 H@ +b0 K@ +0N@ +0O@ +0P@ +0Q@ +b0 S@ +b0 T@ +b0 W@ +b0 Z@ +b0 [@ +b0 _@ +b0 `@ +b0 c@ +0f@ +0g@ +0h@ +0i@ +b0 k@ +b0 l@ +b0 o@ +0r@ +0s@ +0t@ +0u@ +b0 w@ +b0 x@ +b0 {@ +b0 ~@ +b0 !A +b0 %A +b0 &A +b0 )A +0,A +0-A +0.A +0/A +b0 1A +b0 2A +b0 5A +08A +09A +0:A +0;A +b0 =A +b0 >A +b0 AA +b0 DA +sHdlNone\x20(0) jB +b0 mB +b0 nB +b0 qB +0tB +0uB +0vB +0wB +b0 yB +b0 zB +b0 }B +0"C +0#C +0$C +0%C +b0 'C +b0 (C +b0 +C +b0 .C +b0 /C +00C +sHdlNone\x20(0) XC +b0 [C +b0 \C +b0 _C +0bC +0cC +0dC +0eC +b0 gC +b0 hC +b0 kC +0nC +0oC +0pC +0qC +b0 sC +b0 tC +b0 wC +b0 zC +b0 {C +0|C +sHdlSome\x20(1) -I +b1111 1I +b11110 2I +b1001000110100 5I +18I +19I +1:I +1;I +b1111 =I +b11110 >I +b1001000110100 AI +1DI +1EI +1FI +1GI +b1111 II +b11110 JI +b1001000110100 MI +b1111 PI +b1000000000000 QI +1SI +1TI +sHdlNone\x20(0) #J +b0 $J +sHdlNone\x20(0) 'J +b0 (J +sHdlNone\x20(0) +J +b0 ,J +sHdlNone\x20(0) /J +b0 0J +sHdlNone\x20(0) 3J +b0 4J +07J +sHdlNone\x20(0) VJ +b0 ZJ +b0 [J +b0 ^J +0aJ +0bJ +0cJ +0dJ +b0 fJ +b0 gJ +b0 jJ +0mJ +0nJ +0oJ +0pJ +b0 rJ +b0 sJ +b0 vJ +b0 yJ +b0 zJ +0|J +0}J +sHdlNone\x20(0) ~J +b0 #K +b0 $K +b0 'K +0*K +0+K +0,K +0-K +b0 /K +b0 0K +b0 3K +06K +07K +08K +09K +b0 ;K +b0 W +0AW +0BW +0CW +0DW +b0 FW +b0 GW +b0 JW +0MW +0NW +0OW +0PW +b0 RW +b0 SW +b0 VW +b0 YW +b0 ZW +b0 ^W +b0 _W +b0 bW +0eW +0fW +0gW +0hW +b0 jW +b0 kW +b0 nW +0qW +0rW +0sW +0tW +b0 vW +b0 wW +b0 zW +b0 }W #17000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #17500000 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1iV #18000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #18500000 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1iV #19000000 0! -0~" -0%# -0*# -0/# -06# -0=# -0B# -0G# -0L# -0S# -0Z# -0_# -0d# -0i# -0p# -0w# -0~# -0'$ -0,$ -01$ -06$ -0=$ -0D$ -0K$ -01& -08& -0?& -0F& -0M& -0T& -0T) -0[) -0b) -0i) -0p) -0w) -0^+ -0J, -0D9 -0{: -0g; -0R< -0*> -0t> -0nK -0GM -03N -0|N +0!# +0&# +0+# +00# +07# +0># +0C# +0H# +0M# +0T# +0[# +0`# +0e# +0j# +0q# +0x# +0!$ +0($ +0-$ +02$ +07$ +0>$ +0E$ +0L$ +04& +0;& +0B& +0I& +0P& +0W& +0W) +0^) +0e) +0l) +0s) +0z) +0w+ +0e, +0B. +0N. +0Z. +0f. +0{. +0)/ +05/ +0A/ +0O; +0W> +0E? +00@ +0RB +0@C +0{D +0)E +05E +0AE +0VE +0bE +0nE +0zE +0*R +02U +0~U +0iV #19500000 1! -1~" -1%# -1*# -1/# -16# -1=# -1B# -1G# -1L# -1S# -1Z# -1_# -1d# -1i# -1p# -1w# -1~# -1'$ -1,$ -11$ -16$ -1=$ -1D$ -1K$ -11& -18& -1?& -1F& -1M& -1T& -1T) -1[) -1b) -1i) -1p) -1w) -1^+ -1J, -1D9 -1{: -1g; -1R< -1*> -1t> -1nK -1GM -13N -1|N +1!# +1&# +1+# +10# +17# +1># +1C# +1H# +1M# +1T# +1[# +1`# +1e# +1j# +1q# +1x# +1!$ +1($ +1-$ +12$ +17$ +1>$ +1E$ +1L$ +14& +1;& +1B& +1I& +1P& +1W& +1W) +1^) +1e) +1l) +1s) +1z) +1w+ +1e, +1B. +1N. +1Z. +1f. +1{. +1)/ +15/ +1A/ +1O; +1W> +1E? +10@ +1RB +1@C +1{D +1)E +15E +1AE +1VE +1bE +1nE +1zE +1*R +12U +1~U +1iV #20000000 diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs index 0c0a3cd..e055232 100644 --- a/crates/cpu/tests/reg_alloc.rs +++ b/crates/cpu/tests/reg_alloc.rs @@ -8,7 +8,8 @@ use cpu::{ OutputIntegerMode, COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH, }, reg_alloc::{reg_alloc, FetchedDecodedMOp}, - unit::UnitKind, + register::{FlagsMode, PRegFlagsPowerISA}, + unit::{GlobalState, UnitKind}, }; use fayalite::{ assert_export_firrtl, @@ -36,6 +37,16 @@ fn test_reg_alloc() { sim.write_clock(sim.io().cd.clk, false); sim.write_reset(sim.io().cd.rst, true); sim.write_bool(fetch_decode_interface.fetch_decode_special_op.ready, true); + sim.write( + sim.io().global_state, + #[hdl] + GlobalState { + flags_mode: FlagsMode.PowerISA( + #[hdl] + PRegFlagsPowerISA {}, + ), + }, + ); sim.write( fetch_decode_interface.decoded_insns[0].data, HdlSome( @@ -65,8 +76,8 @@ fn test_reg_alloc() { output_integer_mode: OutputIntegerMode.Full64(), }, invert_src0: true, + src1_is_carry_in: true, invert_carry_in: true, - invert_carry_out: true, add_pc: true, }, )), @@ -122,9438 +133,15 @@ fn test_reg_alloc() { if vcd != include_str!("expected/reg_alloc.vcd") { panic!(); } - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_enums: None, - ..ExportOptions::default() - }, - "/test/reg_alloc.fir": r"FIRRTL version 3.2.0 -circuit reg_alloc: - type Ty0 = {clk: Clock, rst: Reset} - type Ty1 = {value: UInt<8>} - type Ty2 = {} - type Ty3 = {|HdlNone, HdlSome: Ty2|} - type Ty4 = {normal_regs: Ty1[2], flag_regs: Ty3[2]} - type Ty5 = {prefix_pad: UInt<0>, dest: Ty4, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} - type Ty6 = {|Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8|} - type Ty7 = {common: Ty5, output_integer_mode: Ty6} - type Ty8 = {alu_common: Ty7, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} - type Ty9 = {alu_common: Ty7, lut: UInt<4>} - type Ty10 = {|AddSub: Ty8, AddSubI: Ty8, Logical: Ty9|} - type Ty11 = {prefix_pad: UInt<1>, dest: Ty4, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} - type Ty12 = {common: Ty11} - type Ty13 = {|ReadL2Reg: Ty12, WriteL2Reg: Ty12|} - type Ty14 = {|Load: Ty11, Store: Ty11|} - type Ty15 = {|AluBranch: Ty10, L2RegisterFile: Ty13, LoadStore: Ty14|} - type Ty16 = {mop: Ty15, is_unrelated_pc: UInt<1>, pc: UInt<64>} - type Ty17 = {|HdlNone, HdlSome: Ty16|} - type Ty18 = {data: Ty17, flip ready: UInt<1>} - type Ty19 = {|Trap: Ty2, ICacheFlush|} - type Ty20 = {|HdlNone, HdlSome: Ty19|} - type Ty21 = {data: Ty20, flip ready: UInt<1>} - type Ty22 = {decoded_insns: Ty18[2], flip fetch_decode_special_op: Ty21} - type Ty23 = {adj_value: UInt<2>} - type Ty24 = {value: UInt<4>} - type Ty25 = {unit_num: Ty23, unit_out_reg: Ty24} - type Ty26 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty25} - type Ty27 = {adj_value: UInt<1>} - type Ty28 = {value: UInt<1>} - type Ty29 = {unit_num: Ty27, unit_out_reg: Ty28} - type Ty30 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29} - type Ty31 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<2>} - type Ty32 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: UInt<2>, mask: UInt<1>} - type Ty33 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<4>} - type Ty34 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: UInt<4>, mask: UInt<1>} - type Ty35 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: Ty25} - type Ty36 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29} - type Ty37 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<2>} - type Ty38 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: UInt<2>, mask: UInt<1>} - type Ty39 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<4>} - type Ty40 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: UInt<4>, mask: UInt<1>} - type Ty41 = {|HdlNone, HdlSome: UInt<2>|} - type Ty42 = {prefix_pad: UInt<0>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} - type Ty43 = {common: Ty42, output_integer_mode: Ty6} - type Ty44 = {alu_common: Ty43, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} - type Ty45 = {alu_common: Ty43, lut: UInt<4>} - type Ty46 = {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|} - type Ty47 = {prefix_pad: UInt<1>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2} - type Ty48 = {common: Ty47} - type Ty49 = {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|} - type Ty50 = {|Load: Ty47, Store: Ty47|} - type Ty51 = {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|} - type Ty52 = {|HdlNone, HdlSome: Ty51|} - type Ty53 = {|HdlNone, HdlSome: Ty25|} - type Ty54 = {addr: Ty1, flip data: Ty25} - type Ty55 = {addr: UInt<0>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29} - type Ty56 = {|AluBranch, L2RegisterFile, LoadStore|} - type Ty57 = {unit_num: UInt<2>, unit_out_reg: UInt<4>} - type Ty58 = {imm_low: UInt<25>, reversed_src: UInt<8>[0], imm_sign: SInt<1>} - type Ty59 = {imm_low: UInt<25>, reversed_src: UInt<0>, imm_sign: UInt<1>} - type Ty60 = {imm_low: UInt<25>, reversed_src: UInt<8>[1], imm_sign: SInt<1>} - type Ty61 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>} - type Ty62 = {pwr_ca_x86_cf: UInt<1>, pwr_ca32_x86_af: UInt<1>, pwr_ov_x86_of: UInt<1>, pwr_ov32_x86_df: UInt<1>, pwr_cr_lt_x86_sf: UInt<1>, pwr_cr_gt_x86_pf: UInt<1>, pwr_cr_eq_x86_zf: UInt<1>, pwr_so: UInt<1>} - type Ty63 = {int_fp: UInt<64>, flags: Ty62} - type Ty64 = {which: Ty24, value: Ty63} - type Ty65 = {|HdlNone, HdlSome: Ty64|} - type Ty66 = {unit_output_writes: Ty65[2], _phantom: Ty2} - type Ty67 = {|HdlNone, HdlSome: Ty46|} - type Ty68 = {data: Ty67, flip ready: UInt<1>} - type Ty69 = {which: Ty24} - type Ty70 = {|HdlNone, HdlSome: Ty69|} - type Ty71 = {value: Ty63, extra_out: Ty2} - type Ty72 = {|Completed: Ty71, Trap: Ty2|} - type Ty73 = {which: Ty24, result: Ty72} - type Ty74 = {|HdlNone, HdlSome: Ty73|} - type Ty75 = {flip unit_forwarding_info: Ty66, flip input_insn: Ty68, flip cancel_input: Ty70, `output`: Ty74} - type Ty76 = {flip cd: Ty0, unit_to_reg_alloc: Ty75} - type Ty77 = {|HdlNone, HdlSome: UInt<4>|} - type Ty78 = {data: Ty77, flip ready: UInt<1>} - type Ty79 = {flip cd: Ty0, flip free_in: Ty78[1], alloc_out: Ty78[1]} - type Ty80 = {mop: Ty46, src_values: Ty63[3]} - type Ty81 = {|HdlNone, HdlSome: Ty80|} - type Ty82 = {data: Ty81, flip ready: UInt<1>} - type Ty83 = {unit_output: Ty73} - type Ty84 = {|HdlNone, HdlSome: Ty83|} - type Ty85 = {flip cd: Ty0, unit_to_reg_alloc: Ty75, execute_start: Ty82, flip execute_end: Ty84} - type Ty86 = {|Ready, Running, CanceledAndRunning|} - type Ty87 = {state: Ty86, mop: Ty46, src_ready_flags: UInt<1>[3]} - type Ty88 = {|HdlNone, HdlSome: Ty87|} - type Ty89 = {|HdlNone, HdlSome: UInt<3>|} - type Ty90 = {empty_op_index: Ty89, ready_op_index: Ty89} - type Ty91 = {|HdlNone, HdlSome: Ty86|} - module reg_alloc: @[reg_alloc.rs 49:1] - input cd: Ty0 @[reg_alloc.rs 53:29] - input fetch_decode_interface: Ty22 @[reg_alloc.rs 56:11] - mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 74:25] - data-type => UInt<2> - depth => 253 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - reader => r1 - reader => r2 - reader => r5 - reader => r6 - reader => r7 - writer => w3 - writer => w4 - writer => w8 - writer => w9 - mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 74:25] - data-type => UInt<4> - depth => 253 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - reader => r1 - reader => r2 - reader => r5 - reader => r6 - reader => r7 - writer => w3 - writer => w4 - writer => w8 - writer => w9 - mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 74:25] - data-type => UInt<2> - depth => 2 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - reader => r1 - reader => r2 - reader => r7 - reader => r8 - reader => r9 - writer => w3 - writer => w4 - writer => w5 - writer => w6 - writer => w10 - writer => w11 - writer => w12 - writer => w13 - mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 74:25] - data-type => UInt<4> - depth => 2 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - reader => r1 - reader => r2 - reader => r7 - reader => r8 - reader => r9 - writer => w3 - writer => w4 - writer => w5 - writer => w6 - writer => w10 - writer => w11 - writer => w12 - writer => w13 - wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_w3: Ty30 @[reg_alloc.rs 166:39] - wire rename_table_normal_mem_w4: Ty30 @[reg_alloc.rs 166:39] - wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_r6: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_r7: Ty26 @[reg_alloc.rs 119:37] - wire rename_table_normal_mem_w8: Ty30 @[reg_alloc.rs 166:39] - wire rename_table_normal_mem_w9: Ty30 @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.w3.data, rename_table_normal_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.mask, rename_table_normal_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.data, rename_table_normal_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.mask, rename_table_normal_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r6.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r6.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r7.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.w8.data, rename_table_normal_mem_w8.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.mask, rename_table_normal_mem_w8.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.data, rename_table_normal_mem_w9.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.mask, rename_table_normal_mem_w9.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_num_adj_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.w3.data, rename_table_normal_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.mask, rename_table_normal_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.data, rename_table_normal_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.mask, rename_table_normal_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r6.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r6.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_r7.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.w8.data, rename_table_normal_mem_w8.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.mask, rename_table_normal_mem_w8.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.data, rename_table_normal_mem_w9.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.mask, rename_table_normal_mem_w9.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 119:37] - connect rename_table_normal_mem_unit_out_reg_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 166:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 166:39] - wire rename_table_special_mem_r0: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_r1: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_r2: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_w3: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w4: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w5: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w6: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_r7: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_r8: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_r9: Ty35 @[reg_alloc.rs 119:37] - wire rename_table_special_mem_w10: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w11: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w12: Ty36 @[reg_alloc.rs 166:39] - wire rename_table_special_mem_w13: Ty36 @[reg_alloc.rs 166:39] - connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.w3.data, rename_table_special_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w3.mask, rename_table_special_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w4.data, rename_table_special_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w4.mask, rename_table_special_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w5.data, rename_table_special_mem_w5.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w5.mask, rename_table_special_mem_w5.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w6.data, rename_table_special_mem_w6.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w6.mask, rename_table_special_mem_w6.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_r7.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r8.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r8.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r9.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r9.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.w10.data, rename_table_special_mem_w10.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w10.mask, rename_table_special_mem_w10.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w11.data, rename_table_special_mem_w11.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w11.mask, rename_table_special_mem_w11.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w12.data, rename_table_special_mem_w12.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w12.mask, rename_table_special_mem_w12.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w13.data, rename_table_special_mem_w13.data.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w13.mask, rename_table_special_mem_w13.mask.unit_num.adj_value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_num_adj_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_num_adj_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.w3.data, rename_table_special_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w3.mask, rename_table_special_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w4.data, rename_table_special_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w4.mask, rename_table_special_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w5.data, rename_table_special_mem_w5.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w5.mask, rename_table_special_mem_w5.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w6.data, rename_table_special_mem_w6.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w6.mask, rename_table_special_mem_w6.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_r7.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r8.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r8.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_r9.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r9.data @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.w10.data, rename_table_special_mem_w10.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w10.mask, rename_table_special_mem_w10.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w11.data, rename_table_special_mem_w11.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w11.mask, rename_table_special_mem_w11.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w12.data, rename_table_special_mem_w12.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w12.mask, rename_table_special_mem_w12.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w13.data, rename_table_special_mem_w13.data.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w13.mask, rename_table_special_mem_w13.mask.unit_out_reg.value @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 119:37] - connect rename_table_special_mem_unit_out_reg_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 166:39] - connect rename_table_special_mem_unit_out_reg_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 166:39] - connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 58:5] - wire available_units: UInt<1>[2][2] @[reg_alloc.rs 83:27] - wire selected_unit_indexes: Ty41[2] @[reg_alloc.rs 86:9] - wire renamed_mops: Ty52[2] @[reg_alloc.rs 88:24] - wire renamed_mops_out_reg: Ty53[2] @[reg_alloc.rs 90:32] - connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 92:9] - wire _array_literal_expr: UInt<1>[2] - connect _array_literal_expr[0], UInt<1>(0h0) - connect _array_literal_expr[1], UInt<1>(0h0) - connect available_units[0], _array_literal_expr @[reg_alloc.rs 96:9] - connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlNone) @[reg_alloc.rs 100:9] - wire rename_0_src_0: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr: Ty1 - connect _bundle_literal_expr.value, tail(UInt<32>(0h0), 24) - connect rename_0_src_0.addr, _bundle_literal_expr @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_1: Ty25 - wire _bundle_literal_expr_2: Ty23 - connect _bundle_literal_expr_2.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_1.unit_num, _bundle_literal_expr_2 - wire _bundle_literal_expr_3: Ty24 - connect _bundle_literal_expr_3.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_1.unit_out_reg, _bundle_literal_expr_3 - connect rename_0_src_0.data, _bundle_literal_expr_1 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_0.data, rename_table_normal_mem_r0.data @[reg_alloc.rs 128:21] - connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_0.data, rename_table_special_mem_r0.data @[reg_alloc.rs 128:21] - wire rename_0_src_1: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr_4: Ty1 - connect _bundle_literal_expr_4.value, tail(UInt<32>(0h0), 24) - connect rename_0_src_1.addr, _bundle_literal_expr_4 @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_5: Ty25 - wire _bundle_literal_expr_6: Ty23 - connect _bundle_literal_expr_6.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_5.unit_num, _bundle_literal_expr_6 - wire _bundle_literal_expr_7: Ty24 - connect _bundle_literal_expr_7.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_5.unit_out_reg, _bundle_literal_expr_7 - connect rename_0_src_1.data, _bundle_literal_expr_5 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_1.data, rename_table_normal_mem_r1.data @[reg_alloc.rs 128:21] - connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_1.data, rename_table_special_mem_r1.data @[reg_alloc.rs 128:21] - wire rename_0_src_2: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr_8: Ty1 - connect _bundle_literal_expr_8.value, tail(UInt<32>(0h0), 24) - connect rename_0_src_2.addr, _bundle_literal_expr_8 @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_9: Ty25 - wire _bundle_literal_expr_10: Ty23 - connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10 - wire _bundle_literal_expr_11: Ty24 - connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11 - connect rename_0_src_2.data, _bundle_literal_expr_9 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_2.data, rename_table_normal_mem_r2.data @[reg_alloc.rs 128:21] - connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_0_src_2.data, rename_table_special_mem_r2.data @[reg_alloc.rs 128:21] - wire rename_table_normal_0_dest0: Ty30 @[reg_alloc.rs 170:21] - connect rename_table_normal_mem_w3, rename_table_normal_0_dest0 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_12: Ty55 - connect _bundle_literal_expr_12.addr, UInt<0>(0h0) - connect _bundle_literal_expr_12.en, UInt<1>(0h0) - connect _bundle_literal_expr_12.clk, cd.clk - wire _uninit_expr: Ty25 - invalidate _uninit_expr - connect _bundle_literal_expr_12.data, _uninit_expr - wire _bundle_literal_expr_13: Ty29 - wire _bundle_literal_expr_14: Ty27 - connect _bundle_literal_expr_14.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_13.unit_num, _bundle_literal_expr_14 - wire _bundle_literal_expr_15: Ty28 - connect _bundle_literal_expr_15.value, UInt<1>(0h1) - connect _bundle_literal_expr_13.unit_out_reg, _bundle_literal_expr_15 - connect _bundle_literal_expr_12.mask, _bundle_literal_expr_13 - ; connect different types: - ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_0_dest0, _bundle_literal_expr_12 @[reg_alloc.rs 175:17] - wire rename_table_special_0_dest0: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w3, rename_table_special_0_dest0 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_16: Ty55 - connect _bundle_literal_expr_16.addr, UInt<0>(0h0) - connect _bundle_literal_expr_16.en, UInt<1>(0h0) - connect _bundle_literal_expr_16.clk, cd.clk - wire _uninit_expr_1: Ty25 - invalidate _uninit_expr_1 - connect _bundle_literal_expr_16.data, _uninit_expr_1 - wire _bundle_literal_expr_17: Ty29 - wire _bundle_literal_expr_18: Ty27 - connect _bundle_literal_expr_18.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_17.unit_num, _bundle_literal_expr_18 - wire _bundle_literal_expr_19: Ty28 - connect _bundle_literal_expr_19.value, UInt<1>(0h1) - connect _bundle_literal_expr_17.unit_out_reg, _bundle_literal_expr_19 - connect _bundle_literal_expr_16.mask, _bundle_literal_expr_17 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_dest0, _bundle_literal_expr_16 @[reg_alloc.rs 175:17] - wire rename_table_normal_0_dest1: Ty30 @[reg_alloc.rs 170:21] - connect rename_table_normal_mem_w4, rename_table_normal_0_dest1 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_20: Ty55 - connect _bundle_literal_expr_20.addr, UInt<0>(0h0) - connect _bundle_literal_expr_20.en, UInt<1>(0h0) - connect _bundle_literal_expr_20.clk, cd.clk - wire _uninit_expr_2: Ty25 - invalidate _uninit_expr_2 - connect _bundle_literal_expr_20.data, _uninit_expr_2 - wire _bundle_literal_expr_21: Ty29 - wire _bundle_literal_expr_22: Ty27 - connect _bundle_literal_expr_22.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22 - wire _bundle_literal_expr_23: Ty28 - connect _bundle_literal_expr_23.value, UInt<1>(0h1) - connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23 - connect _bundle_literal_expr_20.mask, _bundle_literal_expr_21 - ; connect different types: - ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_0_dest1, _bundle_literal_expr_20 @[reg_alloc.rs 175:17] - wire rename_table_special_0_dest1: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w4, rename_table_special_0_dest1 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_24: Ty55 - connect _bundle_literal_expr_24.addr, UInt<0>(0h0) - connect _bundle_literal_expr_24.en, UInt<1>(0h0) - connect _bundle_literal_expr_24.clk, cd.clk - wire _uninit_expr_3: Ty25 - invalidate _uninit_expr_3 - connect _bundle_literal_expr_24.data, _uninit_expr_3 - wire _bundle_literal_expr_25: Ty29 - wire _bundle_literal_expr_26: Ty27 - connect _bundle_literal_expr_26.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_25.unit_num, _bundle_literal_expr_26 - wire _bundle_literal_expr_27: Ty28 - connect _bundle_literal_expr_27.value, UInt<1>(0h1) - connect _bundle_literal_expr_25.unit_out_reg, _bundle_literal_expr_27 - connect _bundle_literal_expr_24.mask, _bundle_literal_expr_25 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_dest1, _bundle_literal_expr_24 @[reg_alloc.rs 175:17] - wire rename_table_special_0_flag0_rFE: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w5, rename_table_special_0_flag0_rFE @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_28: Ty55 - connect _bundle_literal_expr_28.addr, UInt<0>(0h0) - connect _bundle_literal_expr_28.en, UInt<1>(0h0) - connect _bundle_literal_expr_28.clk, cd.clk - wire _uninit_expr_4: Ty25 - invalidate _uninit_expr_4 - connect _bundle_literal_expr_28.data, _uninit_expr_4 - wire _bundle_literal_expr_29: Ty29 - wire _bundle_literal_expr_30: Ty27 - connect _bundle_literal_expr_30.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_29.unit_num, _bundle_literal_expr_30 - wire _bundle_literal_expr_31: Ty28 - connect _bundle_literal_expr_31.value, UInt<1>(0h1) - connect _bundle_literal_expr_29.unit_out_reg, _bundle_literal_expr_31 - connect _bundle_literal_expr_28.mask, _bundle_literal_expr_29 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_flag0_rFE, _bundle_literal_expr_28 @[reg_alloc.rs 175:17] - wire rename_table_special_0_flag1_rFF: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w6, rename_table_special_0_flag1_rFF @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_32: Ty55 - connect _bundle_literal_expr_32.addr, UInt<0>(0h0) - connect _bundle_literal_expr_32.en, UInt<1>(0h0) - connect _bundle_literal_expr_32.clk, cd.clk - wire _uninit_expr_5: Ty25 - invalidate _uninit_expr_5 - connect _bundle_literal_expr_32.data, _uninit_expr_5 - wire _bundle_literal_expr_33: Ty29 - wire _bundle_literal_expr_34: Ty27 - connect _bundle_literal_expr_34.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_33.unit_num, _bundle_literal_expr_34 - wire _bundle_literal_expr_35: Ty28 - connect _bundle_literal_expr_35.value, UInt<1>(0h1) - connect _bundle_literal_expr_33.unit_out_reg, _bundle_literal_expr_35 - connect _bundle_literal_expr_32.mask, _bundle_literal_expr_33 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_flag1_rFF, _bundle_literal_expr_32 @[reg_alloc.rs 175:17] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 189:9] - HdlNone: - skip - HdlSome(_match_arm_value): - wire unit_kind: Ty56 @[unit.rs 128:1] - match _match_arm_value.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_1): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_2): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 128:1] - LoadStore(_match_arm_value_3): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 128:1] - wire available_units_for_kind: UInt<1>[2] @[unit.rs 128:1] - match unit_kind: @[unit.rs 128:1] - AluBranch: - connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 128:1] - connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 128:1] - L2RegisterFile: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 128:1] - LoadStore: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units[0], available_units_for_kind @[reg_alloc.rs 190:13] - match renamed_mops_out_reg[0]: @[reg_alloc.rs 195:13] - HdlNone: - skip - HdlSome(_match_arm_value_4): - wire dest_reg: Ty4 @[unit.rs 128:1] - match _match_arm_value.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_5): - wire dest_reg_1: Ty4 @[instruction.rs 538:1] - match _match_arm_value_5: @[instruction.rs 538:1] - AddSub(_match_arm_value_6): - connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_7): - connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_8): - connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg, dest_reg_1 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_9): - wire dest_reg_2: Ty4 @[instruction.rs 565:1] - match _match_arm_value_9: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_10): - connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_11): - connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 565:1] - connect dest_reg, dest_reg_2 @[unit.rs 128:1] - LoadStore(_match_arm_value_12): - wire dest_reg_3: Ty4 @[instruction.rs 600:1] - match _match_arm_value_12: @[instruction.rs 600:1] - Load(_match_arm_value_13): - connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 600:1] - Store(_match_arm_value_14): - connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 600:1] - connect dest_reg, dest_reg_3 @[unit.rs 128:1] - wire mapped_regs: Ty51 @[unit.rs 128:1] - match _match_arm_value.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_15): - wire mapped_regs_1: Ty46 @[instruction.rs 538:1] - match _match_arm_value_15: @[instruction.rs 538:1] - AddSub(_match_arm_value_16): - wire _bundle_literal_expr_36: Ty1 - connect _bundle_literal_expr_36.value, _match_arm_value_16.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_36 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_37: Ty1 - connect _bundle_literal_expr_37.value, _match_arm_value_16.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_37 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_38: Ty1 - connect _bundle_literal_expr_38.value, _match_arm_value_16.alu_common.common.src[2] - connect rename_0_src_2.addr, _bundle_literal_expr_38 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_39: Ty44 - wire _bundle_literal_expr_40: Ty43 - wire _bundle_literal_expr_41: Ty42 - connect _bundle_literal_expr_41.prefix_pad, _match_arm_value_16.alu_common.common.prefix_pad - connect _bundle_literal_expr_41.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_1: UInt<6>[3] - wire _array_literal_expr_2: UInt<6>[3] - wire _cast_bundle_to_bits_expr: Ty57 - connect _cast_bundle_to_bits_expr.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr: UInt<6> - connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) - connect _array_literal_expr_2[0], _cast_to_bits_expr - wire _cast_bundle_to_bits_expr_1: Ty57 - connect _cast_bundle_to_bits_expr_1.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_1.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_1: UInt<6> - connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) - connect _array_literal_expr_2[1], _cast_to_bits_expr_1 - wire _cast_bundle_to_bits_expr_2: Ty57 - connect _cast_bundle_to_bits_expr_2.unit_num, rename_0_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_2.unit_out_reg, rename_0_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_2: UInt<6> - connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) - connect _array_literal_expr_2[2], _cast_to_bits_expr_2 - connect _array_literal_expr_1[0], _array_literal_expr_2[0] - wire _array_literal_expr_3: UInt<6>[3] - wire _cast_bundle_to_bits_expr_3: Ty57 - connect _cast_bundle_to_bits_expr_3.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_3.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_3: UInt<6> - connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) - connect _array_literal_expr_3[0], _cast_to_bits_expr_3 - wire _cast_bundle_to_bits_expr_4: Ty57 - connect _cast_bundle_to_bits_expr_4.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_4.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_4: UInt<6> - connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) - connect _array_literal_expr_3[1], _cast_to_bits_expr_4 - wire _cast_bundle_to_bits_expr_5: Ty57 - connect _cast_bundle_to_bits_expr_5.unit_num, rename_0_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_5.unit_out_reg, rename_0_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_5: UInt<6> - connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) - connect _array_literal_expr_3[2], _cast_to_bits_expr_5 - connect _array_literal_expr_1[1], _array_literal_expr_3[1] - wire _array_literal_expr_4: UInt<6>[3] - wire _cast_bundle_to_bits_expr_6: Ty57 - connect _cast_bundle_to_bits_expr_6.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_6.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_6: UInt<6> - connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) - connect _array_literal_expr_4[0], _cast_to_bits_expr_6 - wire _cast_bundle_to_bits_expr_7: Ty57 - connect _cast_bundle_to_bits_expr_7.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_7.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_7: UInt<6> - connect _cast_to_bits_expr_7, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num) - connect _array_literal_expr_4[1], _cast_to_bits_expr_7 - wire _cast_bundle_to_bits_expr_8: Ty57 - connect _cast_bundle_to_bits_expr_8.unit_num, rename_0_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_8.unit_out_reg, rename_0_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_8: UInt<6> - connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num) - connect _array_literal_expr_4[2], _cast_to_bits_expr_8 - connect _array_literal_expr_1[2], _array_literal_expr_4[2] - connect _bundle_literal_expr_41.src, _array_literal_expr_1 - wire _bundle_literal_expr_42: Ty58 - connect _bundle_literal_expr_42.imm_low, _match_arm_value_16.alu_common.common.imm_low - wire _array_literal_expr_5: UInt<8>[0] - invalidate _array_literal_expr_5 - connect _bundle_literal_expr_42.reversed_src, _array_literal_expr_5 - connect _bundle_literal_expr_42.imm_sign, _match_arm_value_16.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_9: Ty59 - connect _cast_bundle_to_bits_expr_9.imm_low, _bundle_literal_expr_42.imm_low - connect _cast_bundle_to_bits_expr_9.reversed_src, UInt<0>(0) - connect _cast_bundle_to_bits_expr_9.imm_sign, asUInt(_bundle_literal_expr_42.imm_sign) - wire _cast_to_bits_expr_9: UInt<26> - connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_9.imm_sign, cat(_cast_bundle_to_bits_expr_9.reversed_src, _cast_bundle_to_bits_expr_9.imm_low)) - connect _bundle_literal_expr_41.imm_low, bits(asSInt(_cast_to_bits_expr_9), 24, 0) - wire _bundle_literal_expr_43: Ty58 - connect _bundle_literal_expr_43.imm_low, _match_arm_value_16.alu_common.common.imm_low - wire _array_literal_expr_6: UInt<8>[0] - invalidate _array_literal_expr_6 - connect _bundle_literal_expr_43.reversed_src, _array_literal_expr_6 - connect _bundle_literal_expr_43.imm_sign, _match_arm_value_16.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_10: Ty59 - connect _cast_bundle_to_bits_expr_10.imm_low, _bundle_literal_expr_43.imm_low - connect _cast_bundle_to_bits_expr_10.reversed_src, UInt<0>(0) - connect _cast_bundle_to_bits_expr_10.imm_sign, asUInt(_bundle_literal_expr_43.imm_sign) - wire _cast_to_bits_expr_10: UInt<26> - connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_10.imm_sign, cat(_cast_bundle_to_bits_expr_10.reversed_src, _cast_bundle_to_bits_expr_10.imm_low)) - connect _bundle_literal_expr_41.imm_sign, shr(asSInt(_cast_to_bits_expr_10), 25) - wire _bundle_literal_expr_44: Ty2 - invalidate _bundle_literal_expr_44 - connect _bundle_literal_expr_41._phantom, _bundle_literal_expr_44 - connect _bundle_literal_expr_40.common, _bundle_literal_expr_41 - connect _bundle_literal_expr_40.output_integer_mode, _match_arm_value_16.alu_common.output_integer_mode - connect _bundle_literal_expr_39.alu_common, _bundle_literal_expr_40 - connect _bundle_literal_expr_39.invert_src0, _match_arm_value_16.invert_src0 - connect _bundle_literal_expr_39.invert_carry_in, _match_arm_value_16.invert_carry_in - connect _bundle_literal_expr_39.invert_carry_out, _match_arm_value_16.invert_carry_out - connect _bundle_literal_expr_39.add_pc, _match_arm_value_16.add_pc - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 538:1] - AddSubI(_match_arm_value_17): - wire _bundle_literal_expr_45: Ty1 - connect _bundle_literal_expr_45.value, _match_arm_value_17.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_46: Ty1 - connect _bundle_literal_expr_46.value, _match_arm_value_17.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_46 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_47: Ty44 - wire _bundle_literal_expr_48: Ty43 - wire _bundle_literal_expr_49: Ty42 - connect _bundle_literal_expr_49.prefix_pad, _match_arm_value_17.alu_common.common.prefix_pad - connect _bundle_literal_expr_49.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_7: UInt<6>[3] - wire _array_literal_expr_8: UInt<6>[2] - wire _cast_bundle_to_bits_expr_11: Ty57 - connect _cast_bundle_to_bits_expr_11.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_11.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_11: UInt<6> - connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num) - connect _array_literal_expr_8[0], _cast_to_bits_expr_11 - wire _cast_bundle_to_bits_expr_12: Ty57 - connect _cast_bundle_to_bits_expr_12.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_12.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_12: UInt<6> - connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num) - connect _array_literal_expr_8[1], _cast_to_bits_expr_12 - connect _array_literal_expr_7[0], _array_literal_expr_8[0] - wire _array_literal_expr_9: UInt<6>[2] - wire _cast_bundle_to_bits_expr_13: Ty57 - connect _cast_bundle_to_bits_expr_13.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_13.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_13: UInt<6> - connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num) - connect _array_literal_expr_9[0], _cast_to_bits_expr_13 - wire _cast_bundle_to_bits_expr_14: Ty57 - connect _cast_bundle_to_bits_expr_14.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_14.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_14: UInt<6> - connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num) - connect _array_literal_expr_9[1], _cast_to_bits_expr_14 - connect _array_literal_expr_7[1], _array_literal_expr_9[1] - wire _bundle_literal_expr_50: Ty60 - connect _bundle_literal_expr_50.imm_low, _match_arm_value_17.alu_common.common.imm_low - wire _array_literal_expr_10: UInt<8>[1] - connect _array_literal_expr_10[0], _match_arm_value_17.alu_common.common.src[2] - connect _bundle_literal_expr_50.reversed_src, _array_literal_expr_10 - connect _bundle_literal_expr_50.imm_sign, _match_arm_value_17.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_15: Ty61 - connect _cast_bundle_to_bits_expr_15.imm_low, _bundle_literal_expr_50.imm_low - connect _cast_bundle_to_bits_expr_15.reversed_src, _bundle_literal_expr_50.reversed_src[0] - connect _cast_bundle_to_bits_expr_15.imm_sign, asUInt(_bundle_literal_expr_50.imm_sign) - wire _cast_to_bits_expr_15: UInt<34> - connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_15.imm_sign, cat(_cast_bundle_to_bits_expr_15.reversed_src, _cast_bundle_to_bits_expr_15.imm_low)) - wire _cast_bits_to_bundle_expr: Ty60 - wire _cast_bits_to_bundle_expr_flattened: Ty61 - connect _cast_bits_to_bundle_expr_flattened.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 24, 0) - connect _cast_bits_to_bundle_expr.imm_low, _cast_bits_to_bundle_expr_flattened.imm_low - connect _cast_bits_to_bundle_expr_flattened.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 32, 25) - wire _cast_bits_to_array_expr: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened[0], bits(_cast_bits_to_bundle_expr_flattened.reversed_src, 7, 0) - connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] - connect _cast_bits_to_bundle_expr.reversed_src, _cast_bits_to_array_expr - connect _cast_bits_to_bundle_expr_flattened.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 33, 33) - connect _cast_bits_to_bundle_expr.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened.imm_sign) - connect _array_literal_expr_7[2], tail(_cast_bits_to_bundle_expr.reversed_src[0], 2) - connect _bundle_literal_expr_49.src, _array_literal_expr_7 - wire _bundle_literal_expr_51: Ty60 - connect _bundle_literal_expr_51.imm_low, _match_arm_value_17.alu_common.common.imm_low - wire _array_literal_expr_11: UInt<8>[1] - connect _array_literal_expr_11[0], _match_arm_value_17.alu_common.common.src[2] - connect _bundle_literal_expr_51.reversed_src, _array_literal_expr_11 - connect _bundle_literal_expr_51.imm_sign, _match_arm_value_17.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_16: Ty61 - connect _cast_bundle_to_bits_expr_16.imm_low, _bundle_literal_expr_51.imm_low - connect _cast_bundle_to_bits_expr_16.reversed_src, _bundle_literal_expr_51.reversed_src[0] - connect _cast_bundle_to_bits_expr_16.imm_sign, asUInt(_bundle_literal_expr_51.imm_sign) - wire _cast_to_bits_expr_16: UInt<34> - connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_16.imm_sign, cat(_cast_bundle_to_bits_expr_16.reversed_src, _cast_bundle_to_bits_expr_16.imm_low)) - connect _bundle_literal_expr_49.imm_low, bits(asSInt(_cast_to_bits_expr_16), 24, 0) - wire _bundle_literal_expr_52: Ty60 - connect _bundle_literal_expr_52.imm_low, _match_arm_value_17.alu_common.common.imm_low - wire _array_literal_expr_12: UInt<8>[1] - connect _array_literal_expr_12[0], _match_arm_value_17.alu_common.common.src[2] - connect _bundle_literal_expr_52.reversed_src, _array_literal_expr_12 - connect _bundle_literal_expr_52.imm_sign, _match_arm_value_17.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_17: Ty61 - connect _cast_bundle_to_bits_expr_17.imm_low, _bundle_literal_expr_52.imm_low - connect _cast_bundle_to_bits_expr_17.reversed_src, _bundle_literal_expr_52.reversed_src[0] - connect _cast_bundle_to_bits_expr_17.imm_sign, asUInt(_bundle_literal_expr_52.imm_sign) - wire _cast_to_bits_expr_17: UInt<34> - connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_17.imm_sign, cat(_cast_bundle_to_bits_expr_17.reversed_src, _cast_bundle_to_bits_expr_17.imm_low)) - connect _bundle_literal_expr_49.imm_sign, shr(asSInt(_cast_to_bits_expr_17), 33) - wire _bundle_literal_expr_53: Ty2 - invalidate _bundle_literal_expr_53 - connect _bundle_literal_expr_49._phantom, _bundle_literal_expr_53 - connect _bundle_literal_expr_48.common, _bundle_literal_expr_49 - connect _bundle_literal_expr_48.output_integer_mode, _match_arm_value_17.alu_common.output_integer_mode - connect _bundle_literal_expr_47.alu_common, _bundle_literal_expr_48 - connect _bundle_literal_expr_47.invert_src0, _match_arm_value_17.invert_src0 - connect _bundle_literal_expr_47.invert_carry_in, _match_arm_value_17.invert_carry_in - connect _bundle_literal_expr_47.invert_carry_out, _match_arm_value_17.invert_carry_out - connect _bundle_literal_expr_47.add_pc, _match_arm_value_17.add_pc - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 538:1] - Logical(_match_arm_value_18): - wire _bundle_literal_expr_54: Ty1 - connect _bundle_literal_expr_54.value, _match_arm_value_18.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_54 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_55: Ty1 - connect _bundle_literal_expr_55.value, _match_arm_value_18.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_55 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_56: Ty45 - wire _bundle_literal_expr_57: Ty43 - wire _bundle_literal_expr_58: Ty42 - connect _bundle_literal_expr_58.prefix_pad, _match_arm_value_18.alu_common.common.prefix_pad - connect _bundle_literal_expr_58.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_13: UInt<6>[3] - wire _array_literal_expr_14: UInt<6>[2] - wire _cast_bundle_to_bits_expr_18: Ty57 - connect _cast_bundle_to_bits_expr_18.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_18.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_18: UInt<6> - connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num) - connect _array_literal_expr_14[0], _cast_to_bits_expr_18 - wire _cast_bundle_to_bits_expr_19: Ty57 - connect _cast_bundle_to_bits_expr_19.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_19.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_19: UInt<6> - connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num) - connect _array_literal_expr_14[1], _cast_to_bits_expr_19 - connect _array_literal_expr_13[0], _array_literal_expr_14[0] - wire _array_literal_expr_15: UInt<6>[2] - wire _cast_bundle_to_bits_expr_20: Ty57 - connect _cast_bundle_to_bits_expr_20.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_20.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_20: UInt<6> - connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num) - connect _array_literal_expr_15[0], _cast_to_bits_expr_20 - wire _cast_bundle_to_bits_expr_21: Ty57 - connect _cast_bundle_to_bits_expr_21.unit_num, rename_0_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_21.unit_out_reg, rename_0_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_21: UInt<6> - connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num) - connect _array_literal_expr_15[1], _cast_to_bits_expr_21 - connect _array_literal_expr_13[1], _array_literal_expr_15[1] - wire _bundle_literal_expr_59: Ty60 - connect _bundle_literal_expr_59.imm_low, _match_arm_value_18.alu_common.common.imm_low - wire _array_literal_expr_16: UInt<8>[1] - connect _array_literal_expr_16[0], _match_arm_value_18.alu_common.common.src[2] - connect _bundle_literal_expr_59.reversed_src, _array_literal_expr_16 - connect _bundle_literal_expr_59.imm_sign, _match_arm_value_18.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_22: Ty61 - connect _cast_bundle_to_bits_expr_22.imm_low, _bundle_literal_expr_59.imm_low - connect _cast_bundle_to_bits_expr_22.reversed_src, _bundle_literal_expr_59.reversed_src[0] - connect _cast_bundle_to_bits_expr_22.imm_sign, asUInt(_bundle_literal_expr_59.imm_sign) - wire _cast_to_bits_expr_22: UInt<34> - connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_22.imm_sign, cat(_cast_bundle_to_bits_expr_22.reversed_src, _cast_bundle_to_bits_expr_22.imm_low)) - wire _cast_bits_to_bundle_expr_1: Ty60 - wire _cast_bits_to_bundle_expr_flattened_1: Ty61 - connect _cast_bits_to_bundle_expr_flattened_1.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 24, 0) - connect _cast_bits_to_bundle_expr_1.imm_low, _cast_bits_to_bundle_expr_flattened_1.imm_low - connect _cast_bits_to_bundle_expr_flattened_1.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 32, 25) - wire _cast_bits_to_array_expr_1: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_1: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_1[0], bits(_cast_bits_to_bundle_expr_flattened_1.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] - connect _cast_bits_to_bundle_expr_1.reversed_src, _cast_bits_to_array_expr_1 - connect _cast_bits_to_bundle_expr_flattened_1.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 33, 33) - connect _cast_bits_to_bundle_expr_1.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_1.imm_sign) - connect _array_literal_expr_13[2], tail(_cast_bits_to_bundle_expr_1.reversed_src[0], 2) - connect _bundle_literal_expr_58.src, _array_literal_expr_13 - wire _bundle_literal_expr_60: Ty60 - connect _bundle_literal_expr_60.imm_low, _match_arm_value_18.alu_common.common.imm_low - wire _array_literal_expr_17: UInt<8>[1] - connect _array_literal_expr_17[0], _match_arm_value_18.alu_common.common.src[2] - connect _bundle_literal_expr_60.reversed_src, _array_literal_expr_17 - connect _bundle_literal_expr_60.imm_sign, _match_arm_value_18.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_23: Ty61 - connect _cast_bundle_to_bits_expr_23.imm_low, _bundle_literal_expr_60.imm_low - connect _cast_bundle_to_bits_expr_23.reversed_src, _bundle_literal_expr_60.reversed_src[0] - connect _cast_bundle_to_bits_expr_23.imm_sign, asUInt(_bundle_literal_expr_60.imm_sign) - wire _cast_to_bits_expr_23: UInt<34> - connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_23.imm_sign, cat(_cast_bundle_to_bits_expr_23.reversed_src, _cast_bundle_to_bits_expr_23.imm_low)) - connect _bundle_literal_expr_58.imm_low, bits(asSInt(_cast_to_bits_expr_23), 24, 0) - wire _bundle_literal_expr_61: Ty60 - connect _bundle_literal_expr_61.imm_low, _match_arm_value_18.alu_common.common.imm_low - wire _array_literal_expr_18: UInt<8>[1] - connect _array_literal_expr_18[0], _match_arm_value_18.alu_common.common.src[2] - connect _bundle_literal_expr_61.reversed_src, _array_literal_expr_18 - connect _bundle_literal_expr_61.imm_sign, _match_arm_value_18.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_24: Ty61 - connect _cast_bundle_to_bits_expr_24.imm_low, _bundle_literal_expr_61.imm_low - connect _cast_bundle_to_bits_expr_24.reversed_src, _bundle_literal_expr_61.reversed_src[0] - connect _cast_bundle_to_bits_expr_24.imm_sign, asUInt(_bundle_literal_expr_61.imm_sign) - wire _cast_to_bits_expr_24: UInt<34> - connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_24.imm_sign, cat(_cast_bundle_to_bits_expr_24.reversed_src, _cast_bundle_to_bits_expr_24.imm_low)) - connect _bundle_literal_expr_58.imm_sign, shr(asSInt(_cast_to_bits_expr_24), 33) - wire _bundle_literal_expr_62: Ty2 - invalidate _bundle_literal_expr_62 - connect _bundle_literal_expr_58._phantom, _bundle_literal_expr_62 - connect _bundle_literal_expr_57.common, _bundle_literal_expr_58 - connect _bundle_literal_expr_57.output_integer_mode, _match_arm_value_18.alu_common.output_integer_mode - connect _bundle_literal_expr_56.alu_common, _bundle_literal_expr_57 - connect _bundle_literal_expr_56.lut, _match_arm_value_18.lut - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 538:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_19): - wire mapped_regs_2: Ty49 @[instruction.rs 565:1] - match _match_arm_value_19: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_20): - wire _bundle_literal_expr_63: Ty48 - wire _bundle_literal_expr_64: Ty47 - connect _bundle_literal_expr_64.prefix_pad, _match_arm_value_20.common.prefix_pad - connect _bundle_literal_expr_64.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_19: UInt<6>[3] - connect _array_literal_expr_19[0], pad(UInt<0>(0h0), 6) - connect _array_literal_expr_19[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_65: Ty60 - connect _bundle_literal_expr_65.imm_low, _match_arm_value_20.common.imm_low - wire _array_literal_expr_20: UInt<8>[1] - connect _array_literal_expr_20[0], _match_arm_value_20.common.src[2] - connect _bundle_literal_expr_65.reversed_src, _array_literal_expr_20 - connect _bundle_literal_expr_65.imm_sign, _match_arm_value_20.common.imm_sign - wire _cast_bundle_to_bits_expr_25: Ty61 - connect _cast_bundle_to_bits_expr_25.imm_low, _bundle_literal_expr_65.imm_low - connect _cast_bundle_to_bits_expr_25.reversed_src, _bundle_literal_expr_65.reversed_src[0] - connect _cast_bundle_to_bits_expr_25.imm_sign, asUInt(_bundle_literal_expr_65.imm_sign) - wire _cast_to_bits_expr_25: UInt<34> - connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_25.imm_sign, cat(_cast_bundle_to_bits_expr_25.reversed_src, _cast_bundle_to_bits_expr_25.imm_low)) - wire _cast_bits_to_bundle_expr_2: Ty60 - wire _cast_bits_to_bundle_expr_flattened_2: Ty61 - connect _cast_bits_to_bundle_expr_flattened_2.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 24, 0) - connect _cast_bits_to_bundle_expr_2.imm_low, _cast_bits_to_bundle_expr_flattened_2.imm_low - connect _cast_bits_to_bundle_expr_flattened_2.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 32, 25) - wire _cast_bits_to_array_expr_2: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_2: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_2[0], bits(_cast_bits_to_bundle_expr_flattened_2.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] - connect _cast_bits_to_bundle_expr_2.reversed_src, _cast_bits_to_array_expr_2 - connect _cast_bits_to_bundle_expr_flattened_2.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 33, 33) - connect _cast_bits_to_bundle_expr_2.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_2.imm_sign) - connect _array_literal_expr_19[2], tail(_cast_bits_to_bundle_expr_2.reversed_src[0], 2) - connect _bundle_literal_expr_64.src, _array_literal_expr_19 - wire _bundle_literal_expr_66: Ty60 - connect _bundle_literal_expr_66.imm_low, _match_arm_value_20.common.imm_low - wire _array_literal_expr_21: UInt<8>[1] - connect _array_literal_expr_21[0], _match_arm_value_20.common.src[2] - connect _bundle_literal_expr_66.reversed_src, _array_literal_expr_21 - connect _bundle_literal_expr_66.imm_sign, _match_arm_value_20.common.imm_sign - wire _cast_bundle_to_bits_expr_26: Ty61 - connect _cast_bundle_to_bits_expr_26.imm_low, _bundle_literal_expr_66.imm_low - connect _cast_bundle_to_bits_expr_26.reversed_src, _bundle_literal_expr_66.reversed_src[0] - connect _cast_bundle_to_bits_expr_26.imm_sign, asUInt(_bundle_literal_expr_66.imm_sign) - wire _cast_to_bits_expr_26: UInt<34> - connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_26.imm_sign, cat(_cast_bundle_to_bits_expr_26.reversed_src, _cast_bundle_to_bits_expr_26.imm_low)) - connect _bundle_literal_expr_64.imm_low, bits(asSInt(_cast_to_bits_expr_26), 24, 0) - wire _bundle_literal_expr_67: Ty60 - connect _bundle_literal_expr_67.imm_low, _match_arm_value_20.common.imm_low - wire _array_literal_expr_22: UInt<8>[1] - connect _array_literal_expr_22[0], _match_arm_value_20.common.src[2] - connect _bundle_literal_expr_67.reversed_src, _array_literal_expr_22 - connect _bundle_literal_expr_67.imm_sign, _match_arm_value_20.common.imm_sign - wire _cast_bundle_to_bits_expr_27: Ty61 - connect _cast_bundle_to_bits_expr_27.imm_low, _bundle_literal_expr_67.imm_low - connect _cast_bundle_to_bits_expr_27.reversed_src, _bundle_literal_expr_67.reversed_src[0] - connect _cast_bundle_to_bits_expr_27.imm_sign, asUInt(_bundle_literal_expr_67.imm_sign) - wire _cast_to_bits_expr_27: UInt<34> - connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_27.imm_sign, cat(_cast_bundle_to_bits_expr_27.reversed_src, _cast_bundle_to_bits_expr_27.imm_low)) - connect _bundle_literal_expr_64.imm_sign, shr(asSInt(_cast_to_bits_expr_27), 33) - wire _bundle_literal_expr_68: Ty2 - invalidate _bundle_literal_expr_68 - connect _bundle_literal_expr_64._phantom, _bundle_literal_expr_68 - connect _bundle_literal_expr_63.common, _bundle_literal_expr_64 - connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_21): - wire _bundle_literal_expr_69: Ty1 - connect _bundle_literal_expr_69.value, _match_arm_value_21.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_69 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_70: Ty48 - wire _bundle_literal_expr_71: Ty47 - connect _bundle_literal_expr_71.prefix_pad, _match_arm_value_21.common.prefix_pad - connect _bundle_literal_expr_71.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_23: UInt<6>[3] - wire _array_literal_expr_24: UInt<6>[1] - wire _cast_bundle_to_bits_expr_28: Ty57 - connect _cast_bundle_to_bits_expr_28.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_28.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_28: UInt<6> - connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num) - connect _array_literal_expr_24[0], _cast_to_bits_expr_28 - connect _array_literal_expr_23[0], _array_literal_expr_24[0] - connect _array_literal_expr_23[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_72: Ty60 - connect _bundle_literal_expr_72.imm_low, _match_arm_value_21.common.imm_low - wire _array_literal_expr_25: UInt<8>[1] - connect _array_literal_expr_25[0], _match_arm_value_21.common.src[2] - connect _bundle_literal_expr_72.reversed_src, _array_literal_expr_25 - connect _bundle_literal_expr_72.imm_sign, _match_arm_value_21.common.imm_sign - wire _cast_bundle_to_bits_expr_29: Ty61 - connect _cast_bundle_to_bits_expr_29.imm_low, _bundle_literal_expr_72.imm_low - connect _cast_bundle_to_bits_expr_29.reversed_src, _bundle_literal_expr_72.reversed_src[0] - connect _cast_bundle_to_bits_expr_29.imm_sign, asUInt(_bundle_literal_expr_72.imm_sign) - wire _cast_to_bits_expr_29: UInt<34> - connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_29.imm_sign, cat(_cast_bundle_to_bits_expr_29.reversed_src, _cast_bundle_to_bits_expr_29.imm_low)) - wire _cast_bits_to_bundle_expr_3: Ty60 - wire _cast_bits_to_bundle_expr_flattened_3: Ty61 - connect _cast_bits_to_bundle_expr_flattened_3.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 24, 0) - connect _cast_bits_to_bundle_expr_3.imm_low, _cast_bits_to_bundle_expr_flattened_3.imm_low - connect _cast_bits_to_bundle_expr_flattened_3.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 32, 25) - wire _cast_bits_to_array_expr_3: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_3: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_3[0], bits(_cast_bits_to_bundle_expr_flattened_3.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] - connect _cast_bits_to_bundle_expr_3.reversed_src, _cast_bits_to_array_expr_3 - connect _cast_bits_to_bundle_expr_flattened_3.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 33, 33) - connect _cast_bits_to_bundle_expr_3.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_3.imm_sign) - connect _array_literal_expr_23[2], tail(_cast_bits_to_bundle_expr_3.reversed_src[0], 2) - connect _bundle_literal_expr_71.src, _array_literal_expr_23 - wire _bundle_literal_expr_73: Ty60 - connect _bundle_literal_expr_73.imm_low, _match_arm_value_21.common.imm_low - wire _array_literal_expr_26: UInt<8>[1] - connect _array_literal_expr_26[0], _match_arm_value_21.common.src[2] - connect _bundle_literal_expr_73.reversed_src, _array_literal_expr_26 - connect _bundle_literal_expr_73.imm_sign, _match_arm_value_21.common.imm_sign - wire _cast_bundle_to_bits_expr_30: Ty61 - connect _cast_bundle_to_bits_expr_30.imm_low, _bundle_literal_expr_73.imm_low - connect _cast_bundle_to_bits_expr_30.reversed_src, _bundle_literal_expr_73.reversed_src[0] - connect _cast_bundle_to_bits_expr_30.imm_sign, asUInt(_bundle_literal_expr_73.imm_sign) - wire _cast_to_bits_expr_30: UInt<34> - connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_30.imm_sign, cat(_cast_bundle_to_bits_expr_30.reversed_src, _cast_bundle_to_bits_expr_30.imm_low)) - connect _bundle_literal_expr_71.imm_low, bits(asSInt(_cast_to_bits_expr_30), 24, 0) - wire _bundle_literal_expr_74: Ty60 - connect _bundle_literal_expr_74.imm_low, _match_arm_value_21.common.imm_low - wire _array_literal_expr_27: UInt<8>[1] - connect _array_literal_expr_27[0], _match_arm_value_21.common.src[2] - connect _bundle_literal_expr_74.reversed_src, _array_literal_expr_27 - connect _bundle_literal_expr_74.imm_sign, _match_arm_value_21.common.imm_sign - wire _cast_bundle_to_bits_expr_31: Ty61 - connect _cast_bundle_to_bits_expr_31.imm_low, _bundle_literal_expr_74.imm_low - connect _cast_bundle_to_bits_expr_31.reversed_src, _bundle_literal_expr_74.reversed_src[0] - connect _cast_bundle_to_bits_expr_31.imm_sign, asUInt(_bundle_literal_expr_74.imm_sign) - wire _cast_to_bits_expr_31: UInt<34> - connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_31.imm_sign, cat(_cast_bundle_to_bits_expr_31.reversed_src, _cast_bundle_to_bits_expr_31.imm_low)) - connect _bundle_literal_expr_71.imm_sign, shr(asSInt(_cast_to_bits_expr_31), 33) - wire _bundle_literal_expr_75: Ty2 - invalidate _bundle_literal_expr_75 - connect _bundle_literal_expr_71._phantom, _bundle_literal_expr_75 - connect _bundle_literal_expr_70.common, _bundle_literal_expr_71 - connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 565:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 128:1] - LoadStore(_match_arm_value_22): - wire mapped_regs_3: Ty50 @[instruction.rs 600:1] - match _match_arm_value_22: @[instruction.rs 600:1] - Load(_match_arm_value_23): - wire _bundle_literal_expr_76: Ty47 - connect _bundle_literal_expr_76.prefix_pad, _match_arm_value_23.prefix_pad - connect _bundle_literal_expr_76.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_28: UInt<6>[3] - connect _array_literal_expr_28[0], pad(UInt<0>(0h0), 6) - connect _array_literal_expr_28[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_77: Ty60 - connect _bundle_literal_expr_77.imm_low, _match_arm_value_23.imm_low - wire _array_literal_expr_29: UInt<8>[1] - connect _array_literal_expr_29[0], _match_arm_value_23.src[2] - connect _bundle_literal_expr_77.reversed_src, _array_literal_expr_29 - connect _bundle_literal_expr_77.imm_sign, _match_arm_value_23.imm_sign - wire _cast_bundle_to_bits_expr_32: Ty61 - connect _cast_bundle_to_bits_expr_32.imm_low, _bundle_literal_expr_77.imm_low - connect _cast_bundle_to_bits_expr_32.reversed_src, _bundle_literal_expr_77.reversed_src[0] - connect _cast_bundle_to_bits_expr_32.imm_sign, asUInt(_bundle_literal_expr_77.imm_sign) - wire _cast_to_bits_expr_32: UInt<34> - connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_32.imm_sign, cat(_cast_bundle_to_bits_expr_32.reversed_src, _cast_bundle_to_bits_expr_32.imm_low)) - wire _cast_bits_to_bundle_expr_4: Ty60 - wire _cast_bits_to_bundle_expr_flattened_4: Ty61 - connect _cast_bits_to_bundle_expr_flattened_4.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 24, 0) - connect _cast_bits_to_bundle_expr_4.imm_low, _cast_bits_to_bundle_expr_flattened_4.imm_low - connect _cast_bits_to_bundle_expr_flattened_4.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 32, 25) - wire _cast_bits_to_array_expr_4: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_4: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_4[0], bits(_cast_bits_to_bundle_expr_flattened_4.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] - connect _cast_bits_to_bundle_expr_4.reversed_src, _cast_bits_to_array_expr_4 - connect _cast_bits_to_bundle_expr_flattened_4.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 33, 33) - connect _cast_bits_to_bundle_expr_4.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_4.imm_sign) - connect _array_literal_expr_28[2], tail(_cast_bits_to_bundle_expr_4.reversed_src[0], 2) - connect _bundle_literal_expr_76.src, _array_literal_expr_28 - wire _bundle_literal_expr_78: Ty60 - connect _bundle_literal_expr_78.imm_low, _match_arm_value_23.imm_low - wire _array_literal_expr_30: UInt<8>[1] - connect _array_literal_expr_30[0], _match_arm_value_23.src[2] - connect _bundle_literal_expr_78.reversed_src, _array_literal_expr_30 - connect _bundle_literal_expr_78.imm_sign, _match_arm_value_23.imm_sign - wire _cast_bundle_to_bits_expr_33: Ty61 - connect _cast_bundle_to_bits_expr_33.imm_low, _bundle_literal_expr_78.imm_low - connect _cast_bundle_to_bits_expr_33.reversed_src, _bundle_literal_expr_78.reversed_src[0] - connect _cast_bundle_to_bits_expr_33.imm_sign, asUInt(_bundle_literal_expr_78.imm_sign) - wire _cast_to_bits_expr_33: UInt<34> - connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_33.imm_sign, cat(_cast_bundle_to_bits_expr_33.reversed_src, _cast_bundle_to_bits_expr_33.imm_low)) - connect _bundle_literal_expr_76.imm_low, bits(asSInt(_cast_to_bits_expr_33), 24, 0) - wire _bundle_literal_expr_79: Ty60 - connect _bundle_literal_expr_79.imm_low, _match_arm_value_23.imm_low - wire _array_literal_expr_31: UInt<8>[1] - connect _array_literal_expr_31[0], _match_arm_value_23.src[2] - connect _bundle_literal_expr_79.reversed_src, _array_literal_expr_31 - connect _bundle_literal_expr_79.imm_sign, _match_arm_value_23.imm_sign - wire _cast_bundle_to_bits_expr_34: Ty61 - connect _cast_bundle_to_bits_expr_34.imm_low, _bundle_literal_expr_79.imm_low - connect _cast_bundle_to_bits_expr_34.reversed_src, _bundle_literal_expr_79.reversed_src[0] - connect _cast_bundle_to_bits_expr_34.imm_sign, asUInt(_bundle_literal_expr_79.imm_sign) - wire _cast_to_bits_expr_34: UInt<34> - connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_34.imm_sign, cat(_cast_bundle_to_bits_expr_34.reversed_src, _cast_bundle_to_bits_expr_34.imm_low)) - connect _bundle_literal_expr_76.imm_sign, shr(asSInt(_cast_to_bits_expr_34), 33) - wire _bundle_literal_expr_80: Ty2 - invalidate _bundle_literal_expr_80 - connect _bundle_literal_expr_76._phantom, _bundle_literal_expr_80 - connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 600:1] - Store(_match_arm_value_24): - wire _bundle_literal_expr_81: Ty1 - connect _bundle_literal_expr_81.value, _match_arm_value_24.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_81 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_82: Ty47 - connect _bundle_literal_expr_82.prefix_pad, _match_arm_value_24.prefix_pad - connect _bundle_literal_expr_82.dest, _match_arm_value_4.unit_out_reg - wire _array_literal_expr_32: UInt<6>[3] - wire _array_literal_expr_33: UInt<6>[1] - wire _cast_bundle_to_bits_expr_35: Ty57 - connect _cast_bundle_to_bits_expr_35.unit_num, rename_0_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_35.unit_out_reg, rename_0_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_35: UInt<6> - connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num) - connect _array_literal_expr_33[0], _cast_to_bits_expr_35 - connect _array_literal_expr_32[0], _array_literal_expr_33[0] - connect _array_literal_expr_32[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_83: Ty60 - connect _bundle_literal_expr_83.imm_low, _match_arm_value_24.imm_low - wire _array_literal_expr_34: UInt<8>[1] - connect _array_literal_expr_34[0], _match_arm_value_24.src[2] - connect _bundle_literal_expr_83.reversed_src, _array_literal_expr_34 - connect _bundle_literal_expr_83.imm_sign, _match_arm_value_24.imm_sign - wire _cast_bundle_to_bits_expr_36: Ty61 - connect _cast_bundle_to_bits_expr_36.imm_low, _bundle_literal_expr_83.imm_low - connect _cast_bundle_to_bits_expr_36.reversed_src, _bundle_literal_expr_83.reversed_src[0] - connect _cast_bundle_to_bits_expr_36.imm_sign, asUInt(_bundle_literal_expr_83.imm_sign) - wire _cast_to_bits_expr_36: UInt<34> - connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_36.imm_sign, cat(_cast_bundle_to_bits_expr_36.reversed_src, _cast_bundle_to_bits_expr_36.imm_low)) - wire _cast_bits_to_bundle_expr_5: Ty60 - wire _cast_bits_to_bundle_expr_flattened_5: Ty61 - connect _cast_bits_to_bundle_expr_flattened_5.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 24, 0) - connect _cast_bits_to_bundle_expr_5.imm_low, _cast_bits_to_bundle_expr_flattened_5.imm_low - connect _cast_bits_to_bundle_expr_flattened_5.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 32, 25) - wire _cast_bits_to_array_expr_5: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_5: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_5[0], bits(_cast_bits_to_bundle_expr_flattened_5.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] - connect _cast_bits_to_bundle_expr_5.reversed_src, _cast_bits_to_array_expr_5 - connect _cast_bits_to_bundle_expr_flattened_5.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 33, 33) - connect _cast_bits_to_bundle_expr_5.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_5.imm_sign) - connect _array_literal_expr_32[2], tail(_cast_bits_to_bundle_expr_5.reversed_src[0], 2) - connect _bundle_literal_expr_82.src, _array_literal_expr_32 - wire _bundle_literal_expr_84: Ty60 - connect _bundle_literal_expr_84.imm_low, _match_arm_value_24.imm_low - wire _array_literal_expr_35: UInt<8>[1] - connect _array_literal_expr_35[0], _match_arm_value_24.src[2] - connect _bundle_literal_expr_84.reversed_src, _array_literal_expr_35 - connect _bundle_literal_expr_84.imm_sign, _match_arm_value_24.imm_sign - wire _cast_bundle_to_bits_expr_37: Ty61 - connect _cast_bundle_to_bits_expr_37.imm_low, _bundle_literal_expr_84.imm_low - connect _cast_bundle_to_bits_expr_37.reversed_src, _bundle_literal_expr_84.reversed_src[0] - connect _cast_bundle_to_bits_expr_37.imm_sign, asUInt(_bundle_literal_expr_84.imm_sign) - wire _cast_to_bits_expr_37: UInt<34> - connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_37.imm_sign, cat(_cast_bundle_to_bits_expr_37.reversed_src, _cast_bundle_to_bits_expr_37.imm_low)) - connect _bundle_literal_expr_82.imm_low, bits(asSInt(_cast_to_bits_expr_37), 24, 0) - wire _bundle_literal_expr_85: Ty60 - connect _bundle_literal_expr_85.imm_low, _match_arm_value_24.imm_low - wire _array_literal_expr_36: UInt<8>[1] - connect _array_literal_expr_36[0], _match_arm_value_24.src[2] - connect _bundle_literal_expr_85.reversed_src, _array_literal_expr_36 - connect _bundle_literal_expr_85.imm_sign, _match_arm_value_24.imm_sign - wire _cast_bundle_to_bits_expr_38: Ty61 - connect _cast_bundle_to_bits_expr_38.imm_low, _bundle_literal_expr_85.imm_low - connect _cast_bundle_to_bits_expr_38.reversed_src, _bundle_literal_expr_85.reversed_src[0] - connect _cast_bundle_to_bits_expr_38.imm_sign, asUInt(_bundle_literal_expr_85.imm_sign) - wire _cast_to_bits_expr_38: UInt<34> - connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_38.imm_sign, cat(_cast_bundle_to_bits_expr_38.reversed_src, _cast_bundle_to_bits_expr_38.imm_low)) - connect _bundle_literal_expr_82.imm_sign, shr(asSInt(_cast_to_bits_expr_38), 33) - wire _bundle_literal_expr_86: Ty2 - invalidate _bundle_literal_expr_86 - connect _bundle_literal_expr_82._phantom, _bundle_literal_expr_86 - connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 600:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 128:1] - connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs) @[reg_alloc.rs 197:17] - wire flag_reg: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_87: Ty1 - connect _bundle_literal_expr_87.value, tail(UInt<32>(0h0), 24) - connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 868:17] - match dest_reg.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_25): - wire _bundle_literal_expr_88: Ty1 - connect _bundle_literal_expr_88.value, tail(UInt<32>(0hFE), 24) - connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 872:21] - wire flag_reg_1: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_89: Ty1 - connect _bundle_literal_expr_89.value, tail(UInt<32>(0h0), 24) - connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 868:17] - match dest_reg.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_26): - wire _bundle_literal_expr_90: Ty1 - connect _bundle_literal_expr_90.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 872:21] - when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] - connect rename_table_normal_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] - connect rename_table_normal_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] - connect rename_table_special_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] - connect rename_table_normal_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] - connect rename_table_normal_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] - connect rename_table_special_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(flag_reg.value, UInt<32>(0hFE)), lt(flag_reg.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_0_flag0_rFE.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<32> - connect rename_table_special_0_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 231:33] - connect rename_table_special_0_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(flag_reg_1.value, UInt<32>(0hFE)), lt(flag_reg_1.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_0_flag1_rFF.data, _match_arm_value_4 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<32> - connect rename_table_special_0_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 231:33] - connect rename_table_special_0_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - wire selected_unit_index_leaf_0_0: Ty41 @[reg_alloc.rs 249:25] - connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] - wire unit_index_0_0: UInt<2> @[reg_alloc.rs 258:25] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<64> - connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 261:21] - when available_units[0][0]: @[reg_alloc.rs 263:21] - connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 264:25] - wire selected_unit_index_leaf_0_1: Ty41 @[reg_alloc.rs 249:25] - connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] - wire unit_index_0_1: UInt<2> @[reg_alloc.rs 258:25] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<64> - connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 261:21] - when available_units[0][1]: @[reg_alloc.rs 263:21] - connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 264:25] - wire selected_unit_index_node_0_0: Ty41 @[reg_alloc.rs 271:25] - connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 275:21] - match selected_unit_index_leaf_0_0: @[reg_alloc.rs 277:21] - HdlNone: - connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 278:25] - HdlSome(_match_arm_value_27): - skip - connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 241:9] - connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 92:9] - wire _array_literal_expr_37: UInt<1>[2] - connect _array_literal_expr_37[0], UInt<1>(0h0) - connect _array_literal_expr_37[1], UInt<1>(0h0) - connect available_units[1], _array_literal_expr_37 @[reg_alloc.rs 96:9] - connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlNone) @[reg_alloc.rs 100:9] - wire rename_1_src_0: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr_91: Ty1 - connect _bundle_literal_expr_91.value, tail(UInt<32>(0h0), 24) - connect rename_1_src_0.addr, _bundle_literal_expr_91 @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_92: Ty25 - wire _bundle_literal_expr_93: Ty23 - connect _bundle_literal_expr_93.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_92.unit_num, _bundle_literal_expr_93 - wire _bundle_literal_expr_94: Ty24 - connect _bundle_literal_expr_94.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_92.unit_out_reg, _bundle_literal_expr_94 - connect rename_1_src_0.data, _bundle_literal_expr_92 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r5.addr, sub(rename_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_0.data, rename_table_normal_mem_r5.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_28): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_29): - wire dest_reg_4: Ty4 @[unit.rs 128:1] - match _match_arm_value_28.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_30): - wire dest_reg_5: Ty4 @[instruction.rs 538:1] - match _match_arm_value_30: @[instruction.rs 538:1] - AddSub(_match_arm_value_31): - connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_32): - connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_33): - connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_4, dest_reg_5 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_34): - wire dest_reg_6: Ty4 @[instruction.rs 565:1] - match _match_arm_value_34: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_35): - connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_36): - connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 565:1] - connect dest_reg_4, dest_reg_6 @[unit.rs 128:1] - LoadStore(_match_arm_value_37): - wire dest_reg_7: Ty4 @[instruction.rs 600:1] - match _match_arm_value_37: @[instruction.rs 600:1] - Load(_match_arm_value_38): - connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 600:1] - Store(_match_arm_value_39): - connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 600:1] - connect dest_reg_4, dest_reg_7 @[unit.rs 128:1] - wire flag_reg_2: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_95: Ty1 - connect _bundle_literal_expr_95.value, tail(UInt<32>(0h0), 24) - connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 868:17] - match dest_reg_4.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_40): - wire _bundle_literal_expr_96: Ty1 - connect _bundle_literal_expr_96.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 872:21] - wire flag_reg_3: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_97: Ty1 - connect _bundle_literal_expr_97.value, tail(UInt<32>(0h0), 24) - connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 868:17] - match dest_reg_4.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_41): - wire _bundle_literal_expr_98: Ty1 - connect _bundle_literal_expr_98.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 872:21] - when eq(dest_reg_4.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 146:45] - when eq(dest_reg_4.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 146:45] - connect rename_table_special_mem_r7.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r7.addr, sub(rename_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_0.data, rename_table_special_mem_r7.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_42): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_43): - wire dest_reg_8: Ty4 @[unit.rs 128:1] - match _match_arm_value_42.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_44): - wire dest_reg_9: Ty4 @[instruction.rs 538:1] - match _match_arm_value_44: @[instruction.rs 538:1] - AddSub(_match_arm_value_45): - connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_46): - connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_47): - connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_8, dest_reg_9 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_48): - wire dest_reg_10: Ty4 @[instruction.rs 565:1] - match _match_arm_value_48: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_49): - connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_50): - connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 565:1] - connect dest_reg_8, dest_reg_10 @[unit.rs 128:1] - LoadStore(_match_arm_value_51): - wire dest_reg_11: Ty4 @[instruction.rs 600:1] - match _match_arm_value_51: @[instruction.rs 600:1] - Load(_match_arm_value_52): - connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 600:1] - Store(_match_arm_value_53): - connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 600:1] - connect dest_reg_8, dest_reg_11 @[unit.rs 128:1] - wire flag_reg_4: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_99: Ty1 - connect _bundle_literal_expr_99.value, tail(UInt<32>(0h0), 24) - connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 868:17] - match dest_reg_8.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_54): - wire _bundle_literal_expr_100: Ty1 - connect _bundle_literal_expr_100.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 872:21] - wire flag_reg_5: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_101: Ty1 - connect _bundle_literal_expr_101.value, tail(UInt<32>(0h0), 24) - connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 868:17] - match dest_reg_8.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_55): - wire _bundle_literal_expr_102: Ty1 - connect _bundle_literal_expr_102.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 872:21] - when eq(dest_reg_8.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] - when eq(dest_reg_8.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] - when eq(flag_reg_4.value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] - when eq(flag_reg_5.value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] - wire rename_1_src_1: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr_103: Ty1 - connect _bundle_literal_expr_103.value, tail(UInt<32>(0h0), 24) - connect rename_1_src_1.addr, _bundle_literal_expr_103 @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_104: Ty25 - wire _bundle_literal_expr_105: Ty23 - connect _bundle_literal_expr_105.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_104.unit_num, _bundle_literal_expr_105 - wire _bundle_literal_expr_106: Ty24 - connect _bundle_literal_expr_106.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_104.unit_out_reg, _bundle_literal_expr_106 - connect rename_1_src_1.data, _bundle_literal_expr_104 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r6.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r6.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r6.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r6.addr, sub(rename_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r6.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_1.data, rename_table_normal_mem_r6.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_56): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_57): - wire dest_reg_12: Ty4 @[unit.rs 128:1] - match _match_arm_value_56.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_58): - wire dest_reg_13: Ty4 @[instruction.rs 538:1] - match _match_arm_value_58: @[instruction.rs 538:1] - AddSub(_match_arm_value_59): - connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_60): - connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_61): - connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_12, dest_reg_13 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_62): - wire dest_reg_14: Ty4 @[instruction.rs 565:1] - match _match_arm_value_62: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_63): - connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_64): - connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 565:1] - connect dest_reg_12, dest_reg_14 @[unit.rs 128:1] - LoadStore(_match_arm_value_65): - wire dest_reg_15: Ty4 @[instruction.rs 600:1] - match _match_arm_value_65: @[instruction.rs 600:1] - Load(_match_arm_value_66): - connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 600:1] - Store(_match_arm_value_67): - connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 600:1] - connect dest_reg_12, dest_reg_15 @[unit.rs 128:1] - wire flag_reg_6: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_107: Ty1 - connect _bundle_literal_expr_107.value, tail(UInt<32>(0h0), 24) - connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 868:17] - match dest_reg_12.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_68): - wire _bundle_literal_expr_108: Ty1 - connect _bundle_literal_expr_108.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 872:21] - wire flag_reg_7: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_109: Ty1 - connect _bundle_literal_expr_109.value, tail(UInt<32>(0h0), 24) - connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 868:17] - match dest_reg_12.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_69): - wire _bundle_literal_expr_110: Ty1 - connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 872:21] - when eq(dest_reg_12.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 146:45] - when eq(dest_reg_12.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 146:45] - connect rename_table_special_mem_r8.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r8.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r8.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r8.addr, sub(rename_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r8.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_1.data, rename_table_special_mem_r8.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_70): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_71): - wire dest_reg_16: Ty4 @[unit.rs 128:1] - match _match_arm_value_70.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_72): - wire dest_reg_17: Ty4 @[instruction.rs 538:1] - match _match_arm_value_72: @[instruction.rs 538:1] - AddSub(_match_arm_value_73): - connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_74): - connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_75): - connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_16, dest_reg_17 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_76): - wire dest_reg_18: Ty4 @[instruction.rs 565:1] - match _match_arm_value_76: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_77): - connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_78): - connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 565:1] - connect dest_reg_16, dest_reg_18 @[unit.rs 128:1] - LoadStore(_match_arm_value_79): - wire dest_reg_19: Ty4 @[instruction.rs 600:1] - match _match_arm_value_79: @[instruction.rs 600:1] - Load(_match_arm_value_80): - connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 600:1] - Store(_match_arm_value_81): - connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 600:1] - connect dest_reg_16, dest_reg_19 @[unit.rs 128:1] - wire flag_reg_8: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_111: Ty1 - connect _bundle_literal_expr_111.value, tail(UInt<32>(0h0), 24) - connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 868:17] - match dest_reg_16.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_82): - wire _bundle_literal_expr_112: Ty1 - connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 872:21] - wire flag_reg_9: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_113: Ty1 - connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24) - connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 868:17] - match dest_reg_16.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_83): - wire _bundle_literal_expr_114: Ty1 - connect _bundle_literal_expr_114.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 872:21] - when eq(dest_reg_16.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] - when eq(dest_reg_16.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] - when eq(flag_reg_8.value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] - when eq(flag_reg_9.value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] - wire rename_1_src_2: Ty54 @[reg_alloc.rs 113:17] - wire _bundle_literal_expr_115: Ty1 - connect _bundle_literal_expr_115.value, tail(UInt<32>(0h0), 24) - connect rename_1_src_2.addr, _bundle_literal_expr_115 @[reg_alloc.rs 116:13] - wire _bundle_literal_expr_116: Ty25 - wire _bundle_literal_expr_117: Ty23 - connect _bundle_literal_expr_117.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_116.unit_num, _bundle_literal_expr_117 - wire _bundle_literal_expr_118: Ty24 - connect _bundle_literal_expr_118.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_116.unit_out_reg, _bundle_literal_expr_118 - connect rename_1_src_2.data, _bundle_literal_expr_116 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r7.clk, cd.clk @[reg_alloc.rs 120:17] - connect rename_table_normal_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_mem_r7.addr, sub(rename_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] - connect rename_table_normal_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_2.data, rename_table_normal_mem_r7.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_84): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_85): - wire dest_reg_20: Ty4 @[unit.rs 128:1] - match _match_arm_value_84.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_86): - wire dest_reg_21: Ty4 @[instruction.rs 538:1] - match _match_arm_value_86: @[instruction.rs 538:1] - AddSub(_match_arm_value_87): - connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_88): - connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_89): - connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_20, dest_reg_21 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_90): - wire dest_reg_22: Ty4 @[instruction.rs 565:1] - match _match_arm_value_90: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_91): - connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_92): - connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 565:1] - connect dest_reg_20, dest_reg_22 @[unit.rs 128:1] - LoadStore(_match_arm_value_93): - wire dest_reg_23: Ty4 @[instruction.rs 600:1] - match _match_arm_value_93: @[instruction.rs 600:1] - Load(_match_arm_value_94): - connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 600:1] - Store(_match_arm_value_95): - connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 600:1] - connect dest_reg_20, dest_reg_23 @[unit.rs 128:1] - wire flag_reg_10: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_119: Ty1 - connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24) - connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 868:17] - match dest_reg_20.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_96): - wire _bundle_literal_expr_120: Ty1 - connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 872:21] - wire flag_reg_11: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_121: Ty1 - connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24) - connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 868:17] - match dest_reg_20.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_97): - wire _bundle_literal_expr_122: Ty1 - connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 872:21] - when eq(dest_reg_20.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 146:45] - when eq(dest_reg_20.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 146:45] - connect rename_table_special_mem_r9.clk, cd.clk @[reg_alloc.rs 120:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<8> - connect rename_table_special_mem_r9.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] - connect rename_table_special_mem_r9.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] - when and(geq(rename_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_mem_r9.addr, sub(rename_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] - connect rename_table_special_mem_r9.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] - connect rename_1_src_2.data, rename_table_special_mem_r9.data @[reg_alloc.rs 128:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] - HdlNone: - skip - HdlSome(_match_arm_value_98): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] - HdlNone: - skip - HdlSome(_match_arm_value_99): - wire dest_reg_24: Ty4 @[unit.rs 128:1] - match _match_arm_value_98.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_100): - wire dest_reg_25: Ty4 @[instruction.rs 538:1] - match _match_arm_value_100: @[instruction.rs 538:1] - AddSub(_match_arm_value_101): - connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_102): - connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_103): - connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_24, dest_reg_25 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_104): - wire dest_reg_26: Ty4 @[instruction.rs 565:1] - match _match_arm_value_104: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_105): - connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_106): - connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 565:1] - connect dest_reg_24, dest_reg_26 @[unit.rs 128:1] - LoadStore(_match_arm_value_107): - wire dest_reg_27: Ty4 @[instruction.rs 600:1] - match _match_arm_value_107: @[instruction.rs 600:1] - Load(_match_arm_value_108): - connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 600:1] - Store(_match_arm_value_109): - connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 600:1] - connect dest_reg_24, dest_reg_27 @[unit.rs 128:1] - wire flag_reg_12: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_123: Ty1 - connect _bundle_literal_expr_123.value, tail(UInt<32>(0h0), 24) - connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 868:17] - match dest_reg_24.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_110): - wire _bundle_literal_expr_124: Ty1 - connect _bundle_literal_expr_124.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 872:21] - wire flag_reg_13: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_125: Ty1 - connect _bundle_literal_expr_125.value, tail(UInt<32>(0h0), 24) - connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 868:17] - match dest_reg_24.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_111): - wire _bundle_literal_expr_126: Ty1 - connect _bundle_literal_expr_126.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 872:21] - when eq(dest_reg_24.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] - when eq(dest_reg_24.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] - when eq(flag_reg_12.value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] - when eq(flag_reg_13.value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] - wire rename_table_normal_1_dest0: Ty30 @[reg_alloc.rs 170:21] - connect rename_table_normal_mem_w8, rename_table_normal_1_dest0 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_127: Ty55 - connect _bundle_literal_expr_127.addr, UInt<0>(0h0) - connect _bundle_literal_expr_127.en, UInt<1>(0h0) - connect _bundle_literal_expr_127.clk, cd.clk - wire _uninit_expr_6: Ty25 - invalidate _uninit_expr_6 - connect _bundle_literal_expr_127.data, _uninit_expr_6 - wire _bundle_literal_expr_128: Ty29 - wire _bundle_literal_expr_129: Ty27 - connect _bundle_literal_expr_129.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_128.unit_num, _bundle_literal_expr_129 - wire _bundle_literal_expr_130: Ty28 - connect _bundle_literal_expr_130.value, UInt<1>(0h1) - connect _bundle_literal_expr_128.unit_out_reg, _bundle_literal_expr_130 - connect _bundle_literal_expr_127.mask, _bundle_literal_expr_128 - ; connect different types: - ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_1_dest0, _bundle_literal_expr_127 @[reg_alloc.rs 175:17] - wire rename_table_special_1_dest0: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w10, rename_table_special_1_dest0 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_131: Ty55 - connect _bundle_literal_expr_131.addr, UInt<0>(0h0) - connect _bundle_literal_expr_131.en, UInt<1>(0h0) - connect _bundle_literal_expr_131.clk, cd.clk - wire _uninit_expr_7: Ty25 - invalidate _uninit_expr_7 - connect _bundle_literal_expr_131.data, _uninit_expr_7 - wire _bundle_literal_expr_132: Ty29 - wire _bundle_literal_expr_133: Ty27 - connect _bundle_literal_expr_133.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_132.unit_num, _bundle_literal_expr_133 - wire _bundle_literal_expr_134: Ty28 - connect _bundle_literal_expr_134.value, UInt<1>(0h1) - connect _bundle_literal_expr_132.unit_out_reg, _bundle_literal_expr_134 - connect _bundle_literal_expr_131.mask, _bundle_literal_expr_132 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_dest0, _bundle_literal_expr_131 @[reg_alloc.rs 175:17] - wire rename_table_normal_1_dest1: Ty30 @[reg_alloc.rs 170:21] - connect rename_table_normal_mem_w9, rename_table_normal_1_dest1 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_135: Ty55 - connect _bundle_literal_expr_135.addr, UInt<0>(0h0) - connect _bundle_literal_expr_135.en, UInt<1>(0h0) - connect _bundle_literal_expr_135.clk, cd.clk - wire _uninit_expr_8: Ty25 - invalidate _uninit_expr_8 - connect _bundle_literal_expr_135.data, _uninit_expr_8 - wire _bundle_literal_expr_136: Ty29 - wire _bundle_literal_expr_137: Ty27 - connect _bundle_literal_expr_137.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137 - wire _bundle_literal_expr_138: Ty28 - connect _bundle_literal_expr_138.value, UInt<1>(0h1) - connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138 - connect _bundle_literal_expr_135.mask, _bundle_literal_expr_136 - ; connect different types: - ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_1_dest1, _bundle_literal_expr_135 @[reg_alloc.rs 175:17] - wire rename_table_special_1_dest1: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w11, rename_table_special_1_dest1 @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_139: Ty55 - connect _bundle_literal_expr_139.addr, UInt<0>(0h0) - connect _bundle_literal_expr_139.en, UInt<1>(0h0) - connect _bundle_literal_expr_139.clk, cd.clk - wire _uninit_expr_9: Ty25 - invalidate _uninit_expr_9 - connect _bundle_literal_expr_139.data, _uninit_expr_9 - wire _bundle_literal_expr_140: Ty29 - wire _bundle_literal_expr_141: Ty27 - connect _bundle_literal_expr_141.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_140.unit_num, _bundle_literal_expr_141 - wire _bundle_literal_expr_142: Ty28 - connect _bundle_literal_expr_142.value, UInt<1>(0h1) - connect _bundle_literal_expr_140.unit_out_reg, _bundle_literal_expr_142 - connect _bundle_literal_expr_139.mask, _bundle_literal_expr_140 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_dest1, _bundle_literal_expr_139 @[reg_alloc.rs 175:17] - wire rename_table_special_1_flag0_rFE: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w12, rename_table_special_1_flag0_rFE @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_143: Ty55 - connect _bundle_literal_expr_143.addr, UInt<0>(0h0) - connect _bundle_literal_expr_143.en, UInt<1>(0h0) - connect _bundle_literal_expr_143.clk, cd.clk - wire _uninit_expr_10: Ty25 - invalidate _uninit_expr_10 - connect _bundle_literal_expr_143.data, _uninit_expr_10 - wire _bundle_literal_expr_144: Ty29 - wire _bundle_literal_expr_145: Ty27 - connect _bundle_literal_expr_145.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_144.unit_num, _bundle_literal_expr_145 - wire _bundle_literal_expr_146: Ty28 - connect _bundle_literal_expr_146.value, UInt<1>(0h1) - connect _bundle_literal_expr_144.unit_out_reg, _bundle_literal_expr_146 - connect _bundle_literal_expr_143.mask, _bundle_literal_expr_144 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_flag0_rFE, _bundle_literal_expr_143 @[reg_alloc.rs 175:17] - wire rename_table_special_1_flag1_rFF: Ty36 @[reg_alloc.rs 170:21] - connect rename_table_special_mem_w13, rename_table_special_1_flag1_rFF @[reg_alloc.rs 173:17] - wire _bundle_literal_expr_147: Ty55 - connect _bundle_literal_expr_147.addr, UInt<0>(0h0) - connect _bundle_literal_expr_147.en, UInt<1>(0h0) - connect _bundle_literal_expr_147.clk, cd.clk - wire _uninit_expr_11: Ty25 - invalidate _uninit_expr_11 - connect _bundle_literal_expr_147.data, _uninit_expr_11 - wire _bundle_literal_expr_148: Ty29 - wire _bundle_literal_expr_149: Ty27 - connect _bundle_literal_expr_149.adj_value, UInt<1>(0h1) - connect _bundle_literal_expr_148.unit_num, _bundle_literal_expr_149 - wire _bundle_literal_expr_150: Ty28 - connect _bundle_literal_expr_150.value, UInt<1>(0h1) - connect _bundle_literal_expr_148.unit_out_reg, _bundle_literal_expr_150 - connect _bundle_literal_expr_147.mask, _bundle_literal_expr_148 - ; connect different types: - ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_flag1_rFF, _bundle_literal_expr_147 @[reg_alloc.rs 175:17] - match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 189:9] - HdlNone: - skip - HdlSome(_match_arm_value_112): - wire unit_kind_1: Ty56 @[unit.rs 128:1] - match _match_arm_value_112.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_113): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_114): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 128:1] - LoadStore(_match_arm_value_115): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 128:1] - wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 128:1] - match unit_kind_1: @[unit.rs 128:1] - AluBranch: - connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 128:1] - connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 128:1] - L2RegisterFile: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 128:1] - LoadStore: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 128:1] - connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 190:13] - match renamed_mops_out_reg[1]: @[reg_alloc.rs 195:13] - HdlNone: - skip - HdlSome(_match_arm_value_116): - wire dest_reg_28: Ty4 @[unit.rs 128:1] - match _match_arm_value_112.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_117): - wire dest_reg_29: Ty4 @[instruction.rs 538:1] - match _match_arm_value_117: @[instruction.rs 538:1] - AddSub(_match_arm_value_118): - connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_119): - connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_120): - connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1] - connect dest_reg_28, dest_reg_29 @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_121): - wire dest_reg_30: Ty4 @[instruction.rs 565:1] - match _match_arm_value_121: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_122): - connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_123): - connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 565:1] - connect dest_reg_28, dest_reg_30 @[unit.rs 128:1] - LoadStore(_match_arm_value_124): - wire dest_reg_31: Ty4 @[instruction.rs 600:1] - match _match_arm_value_124: @[instruction.rs 600:1] - Load(_match_arm_value_125): - connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 600:1] - Store(_match_arm_value_126): - connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 600:1] - connect dest_reg_28, dest_reg_31 @[unit.rs 128:1] - wire mapped_regs_4: Ty51 @[unit.rs 128:1] - match _match_arm_value_112.mop: @[unit.rs 128:1] - AluBranch(_match_arm_value_127): - wire mapped_regs_5: Ty46 @[instruction.rs 538:1] - match _match_arm_value_127: @[instruction.rs 538:1] - AddSub(_match_arm_value_128): - wire _bundle_literal_expr_151: Ty1 - connect _bundle_literal_expr_151.value, _match_arm_value_128.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_151 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_152: Ty1 - connect _bundle_literal_expr_152.value, _match_arm_value_128.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_152 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_153: Ty1 - connect _bundle_literal_expr_153.value, _match_arm_value_128.alu_common.common.src[2] - connect rename_1_src_2.addr, _bundle_literal_expr_153 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_154: Ty44 - wire _bundle_literal_expr_155: Ty43 - wire _bundle_literal_expr_156: Ty42 - connect _bundle_literal_expr_156.prefix_pad, _match_arm_value_128.alu_common.common.prefix_pad - connect _bundle_literal_expr_156.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_38: UInt<6>[3] - wire _array_literal_expr_39: UInt<6>[3] - wire _cast_bundle_to_bits_expr_39: Ty57 - connect _cast_bundle_to_bits_expr_39.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_39.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_39: UInt<6> - connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num) - connect _array_literal_expr_39[0], _cast_to_bits_expr_39 - wire _cast_bundle_to_bits_expr_40: Ty57 - connect _cast_bundle_to_bits_expr_40.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_40.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_40: UInt<6> - connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num) - connect _array_literal_expr_39[1], _cast_to_bits_expr_40 - wire _cast_bundle_to_bits_expr_41: Ty57 - connect _cast_bundle_to_bits_expr_41.unit_num, rename_1_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_41.unit_out_reg, rename_1_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_41: UInt<6> - connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num) - connect _array_literal_expr_39[2], _cast_to_bits_expr_41 - connect _array_literal_expr_38[0], _array_literal_expr_39[0] - wire _array_literal_expr_40: UInt<6>[3] - wire _cast_bundle_to_bits_expr_42: Ty57 - connect _cast_bundle_to_bits_expr_42.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_42.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_42: UInt<6> - connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num) - connect _array_literal_expr_40[0], _cast_to_bits_expr_42 - wire _cast_bundle_to_bits_expr_43: Ty57 - connect _cast_bundle_to_bits_expr_43.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_43.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_43: UInt<6> - connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num) - connect _array_literal_expr_40[1], _cast_to_bits_expr_43 - wire _cast_bundle_to_bits_expr_44: Ty57 - connect _cast_bundle_to_bits_expr_44.unit_num, rename_1_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_44.unit_out_reg, rename_1_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_44: UInt<6> - connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num) - connect _array_literal_expr_40[2], _cast_to_bits_expr_44 - connect _array_literal_expr_38[1], _array_literal_expr_40[1] - wire _array_literal_expr_41: UInt<6>[3] - wire _cast_bundle_to_bits_expr_45: Ty57 - connect _cast_bundle_to_bits_expr_45.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_45.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_45: UInt<6> - connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num) - connect _array_literal_expr_41[0], _cast_to_bits_expr_45 - wire _cast_bundle_to_bits_expr_46: Ty57 - connect _cast_bundle_to_bits_expr_46.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_46.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_46: UInt<6> - connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num) - connect _array_literal_expr_41[1], _cast_to_bits_expr_46 - wire _cast_bundle_to_bits_expr_47: Ty57 - connect _cast_bundle_to_bits_expr_47.unit_num, rename_1_src_2.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_47.unit_out_reg, rename_1_src_2.data.unit_out_reg.value - wire _cast_to_bits_expr_47: UInt<6> - connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num) - connect _array_literal_expr_41[2], _cast_to_bits_expr_47 - connect _array_literal_expr_38[2], _array_literal_expr_41[2] - connect _bundle_literal_expr_156.src, _array_literal_expr_38 - wire _bundle_literal_expr_157: Ty58 - connect _bundle_literal_expr_157.imm_low, _match_arm_value_128.alu_common.common.imm_low - wire _array_literal_expr_42: UInt<8>[0] - invalidate _array_literal_expr_42 - connect _bundle_literal_expr_157.reversed_src, _array_literal_expr_42 - connect _bundle_literal_expr_157.imm_sign, _match_arm_value_128.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_48: Ty59 - connect _cast_bundle_to_bits_expr_48.imm_low, _bundle_literal_expr_157.imm_low - connect _cast_bundle_to_bits_expr_48.reversed_src, UInt<0>(0) - connect _cast_bundle_to_bits_expr_48.imm_sign, asUInt(_bundle_literal_expr_157.imm_sign) - wire _cast_to_bits_expr_48: UInt<26> - connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_48.imm_sign, cat(_cast_bundle_to_bits_expr_48.reversed_src, _cast_bundle_to_bits_expr_48.imm_low)) - connect _bundle_literal_expr_156.imm_low, bits(asSInt(_cast_to_bits_expr_48), 24, 0) - wire _bundle_literal_expr_158: Ty58 - connect _bundle_literal_expr_158.imm_low, _match_arm_value_128.alu_common.common.imm_low - wire _array_literal_expr_43: UInt<8>[0] - invalidate _array_literal_expr_43 - connect _bundle_literal_expr_158.reversed_src, _array_literal_expr_43 - connect _bundle_literal_expr_158.imm_sign, _match_arm_value_128.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_49: Ty59 - connect _cast_bundle_to_bits_expr_49.imm_low, _bundle_literal_expr_158.imm_low - connect _cast_bundle_to_bits_expr_49.reversed_src, UInt<0>(0) - connect _cast_bundle_to_bits_expr_49.imm_sign, asUInt(_bundle_literal_expr_158.imm_sign) - wire _cast_to_bits_expr_49: UInt<26> - connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_49.imm_sign, cat(_cast_bundle_to_bits_expr_49.reversed_src, _cast_bundle_to_bits_expr_49.imm_low)) - connect _bundle_literal_expr_156.imm_sign, shr(asSInt(_cast_to_bits_expr_49), 25) - wire _bundle_literal_expr_159: Ty2 - invalidate _bundle_literal_expr_159 - connect _bundle_literal_expr_156._phantom, _bundle_literal_expr_159 - connect _bundle_literal_expr_155.common, _bundle_literal_expr_156 - connect _bundle_literal_expr_155.output_integer_mode, _match_arm_value_128.alu_common.output_integer_mode - connect _bundle_literal_expr_154.alu_common, _bundle_literal_expr_155 - connect _bundle_literal_expr_154.invert_src0, _match_arm_value_128.invert_src0 - connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_128.invert_carry_in - connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_128.invert_carry_out - connect _bundle_literal_expr_154.add_pc, _match_arm_value_128.add_pc - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 538:1] - AddSubI(_match_arm_value_129): - wire _bundle_literal_expr_160: Ty1 - connect _bundle_literal_expr_160.value, _match_arm_value_129.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_160 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_161: Ty1 - connect _bundle_literal_expr_161.value, _match_arm_value_129.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_161 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_162: Ty44 - wire _bundle_literal_expr_163: Ty43 - wire _bundle_literal_expr_164: Ty42 - connect _bundle_literal_expr_164.prefix_pad, _match_arm_value_129.alu_common.common.prefix_pad - connect _bundle_literal_expr_164.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_44: UInt<6>[3] - wire _array_literal_expr_45: UInt<6>[2] - wire _cast_bundle_to_bits_expr_50: Ty57 - connect _cast_bundle_to_bits_expr_50.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_50.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_50: UInt<6> - connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num) - connect _array_literal_expr_45[0], _cast_to_bits_expr_50 - wire _cast_bundle_to_bits_expr_51: Ty57 - connect _cast_bundle_to_bits_expr_51.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_51.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_51: UInt<6> - connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num) - connect _array_literal_expr_45[1], _cast_to_bits_expr_51 - connect _array_literal_expr_44[0], _array_literal_expr_45[0] - wire _array_literal_expr_46: UInt<6>[2] - wire _cast_bundle_to_bits_expr_52: Ty57 - connect _cast_bundle_to_bits_expr_52.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_52.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_52: UInt<6> - connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num) - connect _array_literal_expr_46[0], _cast_to_bits_expr_52 - wire _cast_bundle_to_bits_expr_53: Ty57 - connect _cast_bundle_to_bits_expr_53.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_53.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_53: UInt<6> - connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num) - connect _array_literal_expr_46[1], _cast_to_bits_expr_53 - connect _array_literal_expr_44[1], _array_literal_expr_46[1] - wire _bundle_literal_expr_165: Ty60 - connect _bundle_literal_expr_165.imm_low, _match_arm_value_129.alu_common.common.imm_low - wire _array_literal_expr_47: UInt<8>[1] - connect _array_literal_expr_47[0], _match_arm_value_129.alu_common.common.src[2] - connect _bundle_literal_expr_165.reversed_src, _array_literal_expr_47 - connect _bundle_literal_expr_165.imm_sign, _match_arm_value_129.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_54: Ty61 - connect _cast_bundle_to_bits_expr_54.imm_low, _bundle_literal_expr_165.imm_low - connect _cast_bundle_to_bits_expr_54.reversed_src, _bundle_literal_expr_165.reversed_src[0] - connect _cast_bundle_to_bits_expr_54.imm_sign, asUInt(_bundle_literal_expr_165.imm_sign) - wire _cast_to_bits_expr_54: UInt<34> - connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_54.imm_sign, cat(_cast_bundle_to_bits_expr_54.reversed_src, _cast_bundle_to_bits_expr_54.imm_low)) - wire _cast_bits_to_bundle_expr_6: Ty60 - wire _cast_bits_to_bundle_expr_flattened_6: Ty61 - connect _cast_bits_to_bundle_expr_flattened_6.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 24, 0) - connect _cast_bits_to_bundle_expr_6.imm_low, _cast_bits_to_bundle_expr_flattened_6.imm_low - connect _cast_bits_to_bundle_expr_flattened_6.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 32, 25) - wire _cast_bits_to_array_expr_6: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_6: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_6[0], bits(_cast_bits_to_bundle_expr_flattened_6.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_6[0], _cast_bits_to_array_expr_flattened_6[0] - connect _cast_bits_to_bundle_expr_6.reversed_src, _cast_bits_to_array_expr_6 - connect _cast_bits_to_bundle_expr_flattened_6.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 33, 33) - connect _cast_bits_to_bundle_expr_6.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_6.imm_sign) - connect _array_literal_expr_44[2], tail(_cast_bits_to_bundle_expr_6.reversed_src[0], 2) - connect _bundle_literal_expr_164.src, _array_literal_expr_44 - wire _bundle_literal_expr_166: Ty60 - connect _bundle_literal_expr_166.imm_low, _match_arm_value_129.alu_common.common.imm_low - wire _array_literal_expr_48: UInt<8>[1] - connect _array_literal_expr_48[0], _match_arm_value_129.alu_common.common.src[2] - connect _bundle_literal_expr_166.reversed_src, _array_literal_expr_48 - connect _bundle_literal_expr_166.imm_sign, _match_arm_value_129.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_55: Ty61 - connect _cast_bundle_to_bits_expr_55.imm_low, _bundle_literal_expr_166.imm_low - connect _cast_bundle_to_bits_expr_55.reversed_src, _bundle_literal_expr_166.reversed_src[0] - connect _cast_bundle_to_bits_expr_55.imm_sign, asUInt(_bundle_literal_expr_166.imm_sign) - wire _cast_to_bits_expr_55: UInt<34> - connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_55.imm_sign, cat(_cast_bundle_to_bits_expr_55.reversed_src, _cast_bundle_to_bits_expr_55.imm_low)) - connect _bundle_literal_expr_164.imm_low, bits(asSInt(_cast_to_bits_expr_55), 24, 0) - wire _bundle_literal_expr_167: Ty60 - connect _bundle_literal_expr_167.imm_low, _match_arm_value_129.alu_common.common.imm_low - wire _array_literal_expr_49: UInt<8>[1] - connect _array_literal_expr_49[0], _match_arm_value_129.alu_common.common.src[2] - connect _bundle_literal_expr_167.reversed_src, _array_literal_expr_49 - connect _bundle_literal_expr_167.imm_sign, _match_arm_value_129.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_56: Ty61 - connect _cast_bundle_to_bits_expr_56.imm_low, _bundle_literal_expr_167.imm_low - connect _cast_bundle_to_bits_expr_56.reversed_src, _bundle_literal_expr_167.reversed_src[0] - connect _cast_bundle_to_bits_expr_56.imm_sign, asUInt(_bundle_literal_expr_167.imm_sign) - wire _cast_to_bits_expr_56: UInt<34> - connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_56.imm_sign, cat(_cast_bundle_to_bits_expr_56.reversed_src, _cast_bundle_to_bits_expr_56.imm_low)) - connect _bundle_literal_expr_164.imm_sign, shr(asSInt(_cast_to_bits_expr_56), 33) - wire _bundle_literal_expr_168: Ty2 - invalidate _bundle_literal_expr_168 - connect _bundle_literal_expr_164._phantom, _bundle_literal_expr_168 - connect _bundle_literal_expr_163.common, _bundle_literal_expr_164 - connect _bundle_literal_expr_163.output_integer_mode, _match_arm_value_129.alu_common.output_integer_mode - connect _bundle_literal_expr_162.alu_common, _bundle_literal_expr_163 - connect _bundle_literal_expr_162.invert_src0, _match_arm_value_129.invert_src0 - connect _bundle_literal_expr_162.invert_carry_in, _match_arm_value_129.invert_carry_in - connect _bundle_literal_expr_162.invert_carry_out, _match_arm_value_129.invert_carry_out - connect _bundle_literal_expr_162.add_pc, _match_arm_value_129.add_pc - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 538:1] - Logical(_match_arm_value_130): - wire _bundle_literal_expr_169: Ty1 - connect _bundle_literal_expr_169.value, _match_arm_value_130.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_169 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_170: Ty1 - connect _bundle_literal_expr_170.value, _match_arm_value_130.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_170 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_171: Ty45 - wire _bundle_literal_expr_172: Ty43 - wire _bundle_literal_expr_173: Ty42 - connect _bundle_literal_expr_173.prefix_pad, _match_arm_value_130.alu_common.common.prefix_pad - connect _bundle_literal_expr_173.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_50: UInt<6>[3] - wire _array_literal_expr_51: UInt<6>[2] - wire _cast_bundle_to_bits_expr_57: Ty57 - connect _cast_bundle_to_bits_expr_57.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_57.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_57: UInt<6> - connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num) - connect _array_literal_expr_51[0], _cast_to_bits_expr_57 - wire _cast_bundle_to_bits_expr_58: Ty57 - connect _cast_bundle_to_bits_expr_58.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_58.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_58: UInt<6> - connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num) - connect _array_literal_expr_51[1], _cast_to_bits_expr_58 - connect _array_literal_expr_50[0], _array_literal_expr_51[0] - wire _array_literal_expr_52: UInt<6>[2] - wire _cast_bundle_to_bits_expr_59: Ty57 - connect _cast_bundle_to_bits_expr_59.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_59.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_59: UInt<6> - connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num) - connect _array_literal_expr_52[0], _cast_to_bits_expr_59 - wire _cast_bundle_to_bits_expr_60: Ty57 - connect _cast_bundle_to_bits_expr_60.unit_num, rename_1_src_1.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_60.unit_out_reg, rename_1_src_1.data.unit_out_reg.value - wire _cast_to_bits_expr_60: UInt<6> - connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num) - connect _array_literal_expr_52[1], _cast_to_bits_expr_60 - connect _array_literal_expr_50[1], _array_literal_expr_52[1] - wire _bundle_literal_expr_174: Ty60 - connect _bundle_literal_expr_174.imm_low, _match_arm_value_130.alu_common.common.imm_low - wire _array_literal_expr_53: UInt<8>[1] - connect _array_literal_expr_53[0], _match_arm_value_130.alu_common.common.src[2] - connect _bundle_literal_expr_174.reversed_src, _array_literal_expr_53 - connect _bundle_literal_expr_174.imm_sign, _match_arm_value_130.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_61: Ty61 - connect _cast_bundle_to_bits_expr_61.imm_low, _bundle_literal_expr_174.imm_low - connect _cast_bundle_to_bits_expr_61.reversed_src, _bundle_literal_expr_174.reversed_src[0] - connect _cast_bundle_to_bits_expr_61.imm_sign, asUInt(_bundle_literal_expr_174.imm_sign) - wire _cast_to_bits_expr_61: UInt<34> - connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_61.imm_sign, cat(_cast_bundle_to_bits_expr_61.reversed_src, _cast_bundle_to_bits_expr_61.imm_low)) - wire _cast_bits_to_bundle_expr_7: Ty60 - wire _cast_bits_to_bundle_expr_flattened_7: Ty61 - connect _cast_bits_to_bundle_expr_flattened_7.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 24, 0) - connect _cast_bits_to_bundle_expr_7.imm_low, _cast_bits_to_bundle_expr_flattened_7.imm_low - connect _cast_bits_to_bundle_expr_flattened_7.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 32, 25) - wire _cast_bits_to_array_expr_7: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_7: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_7[0], bits(_cast_bits_to_bundle_expr_flattened_7.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_7[0], _cast_bits_to_array_expr_flattened_7[0] - connect _cast_bits_to_bundle_expr_7.reversed_src, _cast_bits_to_array_expr_7 - connect _cast_bits_to_bundle_expr_flattened_7.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 33, 33) - connect _cast_bits_to_bundle_expr_7.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_7.imm_sign) - connect _array_literal_expr_50[2], tail(_cast_bits_to_bundle_expr_7.reversed_src[0], 2) - connect _bundle_literal_expr_173.src, _array_literal_expr_50 - wire _bundle_literal_expr_175: Ty60 - connect _bundle_literal_expr_175.imm_low, _match_arm_value_130.alu_common.common.imm_low - wire _array_literal_expr_54: UInt<8>[1] - connect _array_literal_expr_54[0], _match_arm_value_130.alu_common.common.src[2] - connect _bundle_literal_expr_175.reversed_src, _array_literal_expr_54 - connect _bundle_literal_expr_175.imm_sign, _match_arm_value_130.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_62: Ty61 - connect _cast_bundle_to_bits_expr_62.imm_low, _bundle_literal_expr_175.imm_low - connect _cast_bundle_to_bits_expr_62.reversed_src, _bundle_literal_expr_175.reversed_src[0] - connect _cast_bundle_to_bits_expr_62.imm_sign, asUInt(_bundle_literal_expr_175.imm_sign) - wire _cast_to_bits_expr_62: UInt<34> - connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_62.imm_sign, cat(_cast_bundle_to_bits_expr_62.reversed_src, _cast_bundle_to_bits_expr_62.imm_low)) - connect _bundle_literal_expr_173.imm_low, bits(asSInt(_cast_to_bits_expr_62), 24, 0) - wire _bundle_literal_expr_176: Ty60 - connect _bundle_literal_expr_176.imm_low, _match_arm_value_130.alu_common.common.imm_low - wire _array_literal_expr_55: UInt<8>[1] - connect _array_literal_expr_55[0], _match_arm_value_130.alu_common.common.src[2] - connect _bundle_literal_expr_176.reversed_src, _array_literal_expr_55 - connect _bundle_literal_expr_176.imm_sign, _match_arm_value_130.alu_common.common.imm_sign - wire _cast_bundle_to_bits_expr_63: Ty61 - connect _cast_bundle_to_bits_expr_63.imm_low, _bundle_literal_expr_176.imm_low - connect _cast_bundle_to_bits_expr_63.reversed_src, _bundle_literal_expr_176.reversed_src[0] - connect _cast_bundle_to_bits_expr_63.imm_sign, asUInt(_bundle_literal_expr_176.imm_sign) - wire _cast_to_bits_expr_63: UInt<34> - connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_63.imm_sign, cat(_cast_bundle_to_bits_expr_63.reversed_src, _cast_bundle_to_bits_expr_63.imm_low)) - connect _bundle_literal_expr_173.imm_sign, shr(asSInt(_cast_to_bits_expr_63), 33) - wire _bundle_literal_expr_177: Ty2 - invalidate _bundle_literal_expr_177 - connect _bundle_literal_expr_173._phantom, _bundle_literal_expr_177 - connect _bundle_literal_expr_172.common, _bundle_literal_expr_173 - connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_130.alu_common.output_integer_mode - connect _bundle_literal_expr_171.alu_common, _bundle_literal_expr_172 - connect _bundle_literal_expr_171.lut, _match_arm_value_130.lut - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 538:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_131): - wire mapped_regs_6: Ty49 @[instruction.rs 565:1] - match _match_arm_value_131: @[instruction.rs 565:1] - ReadL2Reg(_match_arm_value_132): - wire _bundle_literal_expr_178: Ty48 - wire _bundle_literal_expr_179: Ty47 - connect _bundle_literal_expr_179.prefix_pad, _match_arm_value_132.common.prefix_pad - connect _bundle_literal_expr_179.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_56: UInt<6>[3] - connect _array_literal_expr_56[0], pad(UInt<0>(0h0), 6) - connect _array_literal_expr_56[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_180: Ty60 - connect _bundle_literal_expr_180.imm_low, _match_arm_value_132.common.imm_low - wire _array_literal_expr_57: UInt<8>[1] - connect _array_literal_expr_57[0], _match_arm_value_132.common.src[2] - connect _bundle_literal_expr_180.reversed_src, _array_literal_expr_57 - connect _bundle_literal_expr_180.imm_sign, _match_arm_value_132.common.imm_sign - wire _cast_bundle_to_bits_expr_64: Ty61 - connect _cast_bundle_to_bits_expr_64.imm_low, _bundle_literal_expr_180.imm_low - connect _cast_bundle_to_bits_expr_64.reversed_src, _bundle_literal_expr_180.reversed_src[0] - connect _cast_bundle_to_bits_expr_64.imm_sign, asUInt(_bundle_literal_expr_180.imm_sign) - wire _cast_to_bits_expr_64: UInt<34> - connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_64.imm_sign, cat(_cast_bundle_to_bits_expr_64.reversed_src, _cast_bundle_to_bits_expr_64.imm_low)) - wire _cast_bits_to_bundle_expr_8: Ty60 - wire _cast_bits_to_bundle_expr_flattened_8: Ty61 - connect _cast_bits_to_bundle_expr_flattened_8.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 24, 0) - connect _cast_bits_to_bundle_expr_8.imm_low, _cast_bits_to_bundle_expr_flattened_8.imm_low - connect _cast_bits_to_bundle_expr_flattened_8.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 32, 25) - wire _cast_bits_to_array_expr_8: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_8: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_8[0], bits(_cast_bits_to_bundle_expr_flattened_8.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_8[0], _cast_bits_to_array_expr_flattened_8[0] - connect _cast_bits_to_bundle_expr_8.reversed_src, _cast_bits_to_array_expr_8 - connect _cast_bits_to_bundle_expr_flattened_8.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 33, 33) - connect _cast_bits_to_bundle_expr_8.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_8.imm_sign) - connect _array_literal_expr_56[2], tail(_cast_bits_to_bundle_expr_8.reversed_src[0], 2) - connect _bundle_literal_expr_179.src, _array_literal_expr_56 - wire _bundle_literal_expr_181: Ty60 - connect _bundle_literal_expr_181.imm_low, _match_arm_value_132.common.imm_low - wire _array_literal_expr_58: UInt<8>[1] - connect _array_literal_expr_58[0], _match_arm_value_132.common.src[2] - connect _bundle_literal_expr_181.reversed_src, _array_literal_expr_58 - connect _bundle_literal_expr_181.imm_sign, _match_arm_value_132.common.imm_sign - wire _cast_bundle_to_bits_expr_65: Ty61 - connect _cast_bundle_to_bits_expr_65.imm_low, _bundle_literal_expr_181.imm_low - connect _cast_bundle_to_bits_expr_65.reversed_src, _bundle_literal_expr_181.reversed_src[0] - connect _cast_bundle_to_bits_expr_65.imm_sign, asUInt(_bundle_literal_expr_181.imm_sign) - wire _cast_to_bits_expr_65: UInt<34> - connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_65.imm_sign, cat(_cast_bundle_to_bits_expr_65.reversed_src, _cast_bundle_to_bits_expr_65.imm_low)) - connect _bundle_literal_expr_179.imm_low, bits(asSInt(_cast_to_bits_expr_65), 24, 0) - wire _bundle_literal_expr_182: Ty60 - connect _bundle_literal_expr_182.imm_low, _match_arm_value_132.common.imm_low - wire _array_literal_expr_59: UInt<8>[1] - connect _array_literal_expr_59[0], _match_arm_value_132.common.src[2] - connect _bundle_literal_expr_182.reversed_src, _array_literal_expr_59 - connect _bundle_literal_expr_182.imm_sign, _match_arm_value_132.common.imm_sign - wire _cast_bundle_to_bits_expr_66: Ty61 - connect _cast_bundle_to_bits_expr_66.imm_low, _bundle_literal_expr_182.imm_low - connect _cast_bundle_to_bits_expr_66.reversed_src, _bundle_literal_expr_182.reversed_src[0] - connect _cast_bundle_to_bits_expr_66.imm_sign, asUInt(_bundle_literal_expr_182.imm_sign) - wire _cast_to_bits_expr_66: UInt<34> - connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_66.imm_sign, cat(_cast_bundle_to_bits_expr_66.reversed_src, _cast_bundle_to_bits_expr_66.imm_low)) - connect _bundle_literal_expr_179.imm_sign, shr(asSInt(_cast_to_bits_expr_66), 33) - wire _bundle_literal_expr_183: Ty2 - invalidate _bundle_literal_expr_183 - connect _bundle_literal_expr_179._phantom, _bundle_literal_expr_183 - connect _bundle_literal_expr_178.common, _bundle_literal_expr_179 - connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 565:1] - WriteL2Reg(_match_arm_value_133): - wire _bundle_literal_expr_184: Ty1 - connect _bundle_literal_expr_184.value, _match_arm_value_133.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_185: Ty48 - wire _bundle_literal_expr_186: Ty47 - connect _bundle_literal_expr_186.prefix_pad, _match_arm_value_133.common.prefix_pad - connect _bundle_literal_expr_186.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_60: UInt<6>[3] - wire _array_literal_expr_61: UInt<6>[1] - wire _cast_bundle_to_bits_expr_67: Ty57 - connect _cast_bundle_to_bits_expr_67.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_67.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_67: UInt<6> - connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num) - connect _array_literal_expr_61[0], _cast_to_bits_expr_67 - connect _array_literal_expr_60[0], _array_literal_expr_61[0] - connect _array_literal_expr_60[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_187: Ty60 - connect _bundle_literal_expr_187.imm_low, _match_arm_value_133.common.imm_low - wire _array_literal_expr_62: UInt<8>[1] - connect _array_literal_expr_62[0], _match_arm_value_133.common.src[2] - connect _bundle_literal_expr_187.reversed_src, _array_literal_expr_62 - connect _bundle_literal_expr_187.imm_sign, _match_arm_value_133.common.imm_sign - wire _cast_bundle_to_bits_expr_68: Ty61 - connect _cast_bundle_to_bits_expr_68.imm_low, _bundle_literal_expr_187.imm_low - connect _cast_bundle_to_bits_expr_68.reversed_src, _bundle_literal_expr_187.reversed_src[0] - connect _cast_bundle_to_bits_expr_68.imm_sign, asUInt(_bundle_literal_expr_187.imm_sign) - wire _cast_to_bits_expr_68: UInt<34> - connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_68.imm_sign, cat(_cast_bundle_to_bits_expr_68.reversed_src, _cast_bundle_to_bits_expr_68.imm_low)) - wire _cast_bits_to_bundle_expr_9: Ty60 - wire _cast_bits_to_bundle_expr_flattened_9: Ty61 - connect _cast_bits_to_bundle_expr_flattened_9.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 24, 0) - connect _cast_bits_to_bundle_expr_9.imm_low, _cast_bits_to_bundle_expr_flattened_9.imm_low - connect _cast_bits_to_bundle_expr_flattened_9.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 32, 25) - wire _cast_bits_to_array_expr_9: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_9: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_9[0], bits(_cast_bits_to_bundle_expr_flattened_9.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_9[0], _cast_bits_to_array_expr_flattened_9[0] - connect _cast_bits_to_bundle_expr_9.reversed_src, _cast_bits_to_array_expr_9 - connect _cast_bits_to_bundle_expr_flattened_9.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 33, 33) - connect _cast_bits_to_bundle_expr_9.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_9.imm_sign) - connect _array_literal_expr_60[2], tail(_cast_bits_to_bundle_expr_9.reversed_src[0], 2) - connect _bundle_literal_expr_186.src, _array_literal_expr_60 - wire _bundle_literal_expr_188: Ty60 - connect _bundle_literal_expr_188.imm_low, _match_arm_value_133.common.imm_low - wire _array_literal_expr_63: UInt<8>[1] - connect _array_literal_expr_63[0], _match_arm_value_133.common.src[2] - connect _bundle_literal_expr_188.reversed_src, _array_literal_expr_63 - connect _bundle_literal_expr_188.imm_sign, _match_arm_value_133.common.imm_sign - wire _cast_bundle_to_bits_expr_69: Ty61 - connect _cast_bundle_to_bits_expr_69.imm_low, _bundle_literal_expr_188.imm_low - connect _cast_bundle_to_bits_expr_69.reversed_src, _bundle_literal_expr_188.reversed_src[0] - connect _cast_bundle_to_bits_expr_69.imm_sign, asUInt(_bundle_literal_expr_188.imm_sign) - wire _cast_to_bits_expr_69: UInt<34> - connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_69.imm_sign, cat(_cast_bundle_to_bits_expr_69.reversed_src, _cast_bundle_to_bits_expr_69.imm_low)) - connect _bundle_literal_expr_186.imm_low, bits(asSInt(_cast_to_bits_expr_69), 24, 0) - wire _bundle_literal_expr_189: Ty60 - connect _bundle_literal_expr_189.imm_low, _match_arm_value_133.common.imm_low - wire _array_literal_expr_64: UInt<8>[1] - connect _array_literal_expr_64[0], _match_arm_value_133.common.src[2] - connect _bundle_literal_expr_189.reversed_src, _array_literal_expr_64 - connect _bundle_literal_expr_189.imm_sign, _match_arm_value_133.common.imm_sign - wire _cast_bundle_to_bits_expr_70: Ty61 - connect _cast_bundle_to_bits_expr_70.imm_low, _bundle_literal_expr_189.imm_low - connect _cast_bundle_to_bits_expr_70.reversed_src, _bundle_literal_expr_189.reversed_src[0] - connect _cast_bundle_to_bits_expr_70.imm_sign, asUInt(_bundle_literal_expr_189.imm_sign) - wire _cast_to_bits_expr_70: UInt<34> - connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_70.imm_sign, cat(_cast_bundle_to_bits_expr_70.reversed_src, _cast_bundle_to_bits_expr_70.imm_low)) - connect _bundle_literal_expr_186.imm_sign, shr(asSInt(_cast_to_bits_expr_70), 33) - wire _bundle_literal_expr_190: Ty2 - invalidate _bundle_literal_expr_190 - connect _bundle_literal_expr_186._phantom, _bundle_literal_expr_190 - connect _bundle_literal_expr_185.common, _bundle_literal_expr_186 - connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 565:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 128:1] - LoadStore(_match_arm_value_134): - wire mapped_regs_7: Ty50 @[instruction.rs 600:1] - match _match_arm_value_134: @[instruction.rs 600:1] - Load(_match_arm_value_135): - wire _bundle_literal_expr_191: Ty47 - connect _bundle_literal_expr_191.prefix_pad, _match_arm_value_135.prefix_pad - connect _bundle_literal_expr_191.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_65: UInt<6>[3] - connect _array_literal_expr_65[0], pad(UInt<0>(0h0), 6) - connect _array_literal_expr_65[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_192: Ty60 - connect _bundle_literal_expr_192.imm_low, _match_arm_value_135.imm_low - wire _array_literal_expr_66: UInt<8>[1] - connect _array_literal_expr_66[0], _match_arm_value_135.src[2] - connect _bundle_literal_expr_192.reversed_src, _array_literal_expr_66 - connect _bundle_literal_expr_192.imm_sign, _match_arm_value_135.imm_sign - wire _cast_bundle_to_bits_expr_71: Ty61 - connect _cast_bundle_to_bits_expr_71.imm_low, _bundle_literal_expr_192.imm_low - connect _cast_bundle_to_bits_expr_71.reversed_src, _bundle_literal_expr_192.reversed_src[0] - connect _cast_bundle_to_bits_expr_71.imm_sign, asUInt(_bundle_literal_expr_192.imm_sign) - wire _cast_to_bits_expr_71: UInt<34> - connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_71.imm_sign, cat(_cast_bundle_to_bits_expr_71.reversed_src, _cast_bundle_to_bits_expr_71.imm_low)) - wire _cast_bits_to_bundle_expr_10: Ty60 - wire _cast_bits_to_bundle_expr_flattened_10: Ty61 - connect _cast_bits_to_bundle_expr_flattened_10.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 24, 0) - connect _cast_bits_to_bundle_expr_10.imm_low, _cast_bits_to_bundle_expr_flattened_10.imm_low - connect _cast_bits_to_bundle_expr_flattened_10.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 32, 25) - wire _cast_bits_to_array_expr_10: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_10: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_10[0], bits(_cast_bits_to_bundle_expr_flattened_10.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_10[0], _cast_bits_to_array_expr_flattened_10[0] - connect _cast_bits_to_bundle_expr_10.reversed_src, _cast_bits_to_array_expr_10 - connect _cast_bits_to_bundle_expr_flattened_10.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 33, 33) - connect _cast_bits_to_bundle_expr_10.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_10.imm_sign) - connect _array_literal_expr_65[2], tail(_cast_bits_to_bundle_expr_10.reversed_src[0], 2) - connect _bundle_literal_expr_191.src, _array_literal_expr_65 - wire _bundle_literal_expr_193: Ty60 - connect _bundle_literal_expr_193.imm_low, _match_arm_value_135.imm_low - wire _array_literal_expr_67: UInt<8>[1] - connect _array_literal_expr_67[0], _match_arm_value_135.src[2] - connect _bundle_literal_expr_193.reversed_src, _array_literal_expr_67 - connect _bundle_literal_expr_193.imm_sign, _match_arm_value_135.imm_sign - wire _cast_bundle_to_bits_expr_72: Ty61 - connect _cast_bundle_to_bits_expr_72.imm_low, _bundle_literal_expr_193.imm_low - connect _cast_bundle_to_bits_expr_72.reversed_src, _bundle_literal_expr_193.reversed_src[0] - connect _cast_bundle_to_bits_expr_72.imm_sign, asUInt(_bundle_literal_expr_193.imm_sign) - wire _cast_to_bits_expr_72: UInt<34> - connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_72.imm_sign, cat(_cast_bundle_to_bits_expr_72.reversed_src, _cast_bundle_to_bits_expr_72.imm_low)) - connect _bundle_literal_expr_191.imm_low, bits(asSInt(_cast_to_bits_expr_72), 24, 0) - wire _bundle_literal_expr_194: Ty60 - connect _bundle_literal_expr_194.imm_low, _match_arm_value_135.imm_low - wire _array_literal_expr_68: UInt<8>[1] - connect _array_literal_expr_68[0], _match_arm_value_135.src[2] - connect _bundle_literal_expr_194.reversed_src, _array_literal_expr_68 - connect _bundle_literal_expr_194.imm_sign, _match_arm_value_135.imm_sign - wire _cast_bundle_to_bits_expr_73: Ty61 - connect _cast_bundle_to_bits_expr_73.imm_low, _bundle_literal_expr_194.imm_low - connect _cast_bundle_to_bits_expr_73.reversed_src, _bundle_literal_expr_194.reversed_src[0] - connect _cast_bundle_to_bits_expr_73.imm_sign, asUInt(_bundle_literal_expr_194.imm_sign) - wire _cast_to_bits_expr_73: UInt<34> - connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_73.imm_sign, cat(_cast_bundle_to_bits_expr_73.reversed_src, _cast_bundle_to_bits_expr_73.imm_low)) - connect _bundle_literal_expr_191.imm_sign, shr(asSInt(_cast_to_bits_expr_73), 33) - wire _bundle_literal_expr_195: Ty2 - invalidate _bundle_literal_expr_195 - connect _bundle_literal_expr_191._phantom, _bundle_literal_expr_195 - connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 600:1] - Store(_match_arm_value_136): - wire _bundle_literal_expr_196: Ty1 - connect _bundle_literal_expr_196.value, _match_arm_value_136.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_196 @[reg_alloc.rs 204:29] - wire _bundle_literal_expr_197: Ty47 - connect _bundle_literal_expr_197.prefix_pad, _match_arm_value_136.prefix_pad - connect _bundle_literal_expr_197.dest, _match_arm_value_116.unit_out_reg - wire _array_literal_expr_69: UInt<6>[3] - wire _array_literal_expr_70: UInt<6>[1] - wire _cast_bundle_to_bits_expr_74: Ty57 - connect _cast_bundle_to_bits_expr_74.unit_num, rename_1_src_0.data.unit_num.adj_value - connect _cast_bundle_to_bits_expr_74.unit_out_reg, rename_1_src_0.data.unit_out_reg.value - wire _cast_to_bits_expr_74: UInt<6> - connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num) - connect _array_literal_expr_70[0], _cast_to_bits_expr_74 - connect _array_literal_expr_69[0], _array_literal_expr_70[0] - connect _array_literal_expr_69[1], pad(UInt<0>(0h0), 6) - wire _bundle_literal_expr_198: Ty60 - connect _bundle_literal_expr_198.imm_low, _match_arm_value_136.imm_low - wire _array_literal_expr_71: UInt<8>[1] - connect _array_literal_expr_71[0], _match_arm_value_136.src[2] - connect _bundle_literal_expr_198.reversed_src, _array_literal_expr_71 - connect _bundle_literal_expr_198.imm_sign, _match_arm_value_136.imm_sign - wire _cast_bundle_to_bits_expr_75: Ty61 - connect _cast_bundle_to_bits_expr_75.imm_low, _bundle_literal_expr_198.imm_low - connect _cast_bundle_to_bits_expr_75.reversed_src, _bundle_literal_expr_198.reversed_src[0] - connect _cast_bundle_to_bits_expr_75.imm_sign, asUInt(_bundle_literal_expr_198.imm_sign) - wire _cast_to_bits_expr_75: UInt<34> - connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_75.imm_sign, cat(_cast_bundle_to_bits_expr_75.reversed_src, _cast_bundle_to_bits_expr_75.imm_low)) - wire _cast_bits_to_bundle_expr_11: Ty60 - wire _cast_bits_to_bundle_expr_flattened_11: Ty61 - connect _cast_bits_to_bundle_expr_flattened_11.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 24, 0) - connect _cast_bits_to_bundle_expr_11.imm_low, _cast_bits_to_bundle_expr_flattened_11.imm_low - connect _cast_bits_to_bundle_expr_flattened_11.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 32, 25) - wire _cast_bits_to_array_expr_11: UInt<8>[1] - wire _cast_bits_to_array_expr_flattened_11: UInt<8>[1] - connect _cast_bits_to_array_expr_flattened_11[0], bits(_cast_bits_to_bundle_expr_flattened_11.reversed_src, 7, 0) - connect _cast_bits_to_array_expr_11[0], _cast_bits_to_array_expr_flattened_11[0] - connect _cast_bits_to_bundle_expr_11.reversed_src, _cast_bits_to_array_expr_11 - connect _cast_bits_to_bundle_expr_flattened_11.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 33, 33) - connect _cast_bits_to_bundle_expr_11.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_11.imm_sign) - connect _array_literal_expr_69[2], tail(_cast_bits_to_bundle_expr_11.reversed_src[0], 2) - connect _bundle_literal_expr_197.src, _array_literal_expr_69 - wire _bundle_literal_expr_199: Ty60 - connect _bundle_literal_expr_199.imm_low, _match_arm_value_136.imm_low - wire _array_literal_expr_72: UInt<8>[1] - connect _array_literal_expr_72[0], _match_arm_value_136.src[2] - connect _bundle_literal_expr_199.reversed_src, _array_literal_expr_72 - connect _bundle_literal_expr_199.imm_sign, _match_arm_value_136.imm_sign - wire _cast_bundle_to_bits_expr_76: Ty61 - connect _cast_bundle_to_bits_expr_76.imm_low, _bundle_literal_expr_199.imm_low - connect _cast_bundle_to_bits_expr_76.reversed_src, _bundle_literal_expr_199.reversed_src[0] - connect _cast_bundle_to_bits_expr_76.imm_sign, asUInt(_bundle_literal_expr_199.imm_sign) - wire _cast_to_bits_expr_76: UInt<34> - connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_76.imm_sign, cat(_cast_bundle_to_bits_expr_76.reversed_src, _cast_bundle_to_bits_expr_76.imm_low)) - connect _bundle_literal_expr_197.imm_low, bits(asSInt(_cast_to_bits_expr_76), 24, 0) - wire _bundle_literal_expr_200: Ty60 - connect _bundle_literal_expr_200.imm_low, _match_arm_value_136.imm_low - wire _array_literal_expr_73: UInt<8>[1] - connect _array_literal_expr_73[0], _match_arm_value_136.src[2] - connect _bundle_literal_expr_200.reversed_src, _array_literal_expr_73 - connect _bundle_literal_expr_200.imm_sign, _match_arm_value_136.imm_sign - wire _cast_bundle_to_bits_expr_77: Ty61 - connect _cast_bundle_to_bits_expr_77.imm_low, _bundle_literal_expr_200.imm_low - connect _cast_bundle_to_bits_expr_77.reversed_src, _bundle_literal_expr_200.reversed_src[0] - connect _cast_bundle_to_bits_expr_77.imm_sign, asUInt(_bundle_literal_expr_200.imm_sign) - wire _cast_to_bits_expr_77: UInt<34> - connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_77.imm_sign, cat(_cast_bundle_to_bits_expr_77.reversed_src, _cast_bundle_to_bits_expr_77.imm_low)) - connect _bundle_literal_expr_197.imm_sign, shr(asSInt(_cast_to_bits_expr_77), 33) - wire _bundle_literal_expr_201: Ty2 - invalidate _bundle_literal_expr_201 - connect _bundle_literal_expr_197._phantom, _bundle_literal_expr_201 - connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 600:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 128:1] - connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 197:17] - wire flag_reg_14: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_202: Ty1 - connect _bundle_literal_expr_202.value, tail(UInt<32>(0h0), 24) - connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 868:17] - match dest_reg_28.flag_regs[0]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_137): - wire _bundle_literal_expr_203: Ty1 - connect _bundle_literal_expr_203.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 872:21] - wire flag_reg_15: Ty1 @[instruction.rs 867:32] - wire _bundle_literal_expr_204: Ty1 - connect _bundle_literal_expr_204.value, tail(UInt<32>(0h0), 24) - connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 868:17] - match dest_reg_28.flag_regs[1]: @[instruction.rs 870:17] - HdlNone: - skip - HdlSome(_match_arm_value_138): - wire _bundle_literal_expr_205: Ty1 - connect _bundle_literal_expr_205.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 872:21] - when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] - connect rename_table_normal_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] - connect rename_table_normal_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] - connect rename_table_special_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] - connect rename_table_normal_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<8> - ; rhs: UInt<33> - connect rename_table_normal_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] - connect rename_table_normal_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<33> - connect rename_table_special_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] - connect rename_table_special_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(flag_reg_14.value, UInt<32>(0hFE)), lt(flag_reg_14.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_1_flag0_rFE.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<32> - connect rename_table_special_1_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 231:33] - connect rename_table_special_1_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - when and(geq(flag_reg_15.value, UInt<32>(0hFE)), lt(flag_reg_15.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] - connect rename_table_special_1_flag1_rFF.data, _match_arm_value_116 @[reg_alloc.rs 229:29] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<32> - connect rename_table_special_1_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 231:33] - connect rename_table_special_1_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] - wire selected_unit_index_leaf_1_0: Ty41 @[reg_alloc.rs 249:25] - connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] - wire unit_index_1_0: UInt<2> @[reg_alloc.rs 258:25] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<64> - connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 261:21] - when available_units[1][0]: @[reg_alloc.rs 263:21] - connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 264:25] - wire selected_unit_index_leaf_1_1: Ty41 @[reg_alloc.rs 249:25] - connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] - wire unit_index_1_1: UInt<2> @[reg_alloc.rs 258:25] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<64> - connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 261:21] - when available_units[1][1]: @[reg_alloc.rs 263:21] - connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 264:25] - wire selected_unit_index_node_1_0: Ty41 @[reg_alloc.rs 271:25] - connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 275:21] - match selected_unit_index_leaf_1_0: @[reg_alloc.rs 277:21] - HdlNone: - connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 278:25] - HdlSome(_match_arm_value_139): - skip - connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 241:9] - match selected_unit_indexes[0]: @[reg_alloc.rs 291:13] - HdlNone: - skip - HdlSome(_match_arm_value_140): - connect available_units[1][_match_arm_value_140], UInt<1>(0h0) @[reg_alloc.rs 292:17] - wire _array_literal_expr_74: Ty53[2] - connect _array_literal_expr_74[0], {|HdlNone, HdlSome: Ty25|}(HdlNone) - connect _array_literal_expr_74[1], {|HdlNone, HdlSome: Ty25|}(HdlNone) - connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 299:5] - inst unit_0 of alu_branch @[reg_alloc.rs 311:13] - connect unit_0.cd, cd @[reg_alloc.rs 313:9] - inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 326:13] - connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9] - wire _uninit_expr_12: Ty77 - invalidate _uninit_expr_12 - connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr_12 @[reg_alloc.rs 330:9] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9] - connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] - HdlNone: - connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 343:17] - HdlSome(_match_arm_value_141): - skip - when not(unit_0.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13] - connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 348:17] - match selected_unit_indexes[0]: @[reg_alloc.rs 351:13] - HdlNone: - skip - HdlSome(_match_arm_value_142): - when eq(_match_arm_value_142, UInt<64>(0h0)): @[reg_alloc.rs 353:17] - wire and_then_out: Ty67 @[reg_alloc.rs 357:25] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] - match renamed_mops[0]: @[reg_alloc.rs 357:25] - HdlNone: - connect and_then_out, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] - HdlSome(_match_arm_value_143): - wire alu_branch_mop: Ty67 @[unit.rs 128:1] - connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1] - match _match_arm_value_143: @[unit.rs 128:1] - AluBranch(_match_arm_value_144): - connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_145): - skip - LoadStore(_match_arm_value_146): - skip - connect and_then_out, alu_branch_mop @[reg_alloc.rs 357:25] - match and_then_out: @[reg_alloc.rs 356:21] - HdlNone: - wire _uninit_expr_13: Ty46 - invalidate _uninit_expr_13 - connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 361:25] - HdlSome(_match_arm_value_147): - connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 359:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] - HdlNone: - skip - HdlSome(_match_arm_value_148): - wire _bundle_literal_expr_206: Ty25 - wire _bundle_literal_expr_207: Ty23 - connect _bundle_literal_expr_207.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_206.unit_num, _bundle_literal_expr_207 - wire _bundle_literal_expr_208: Ty24 - connect _bundle_literal_expr_208.value, _match_arm_value_148 - connect _bundle_literal_expr_206.unit_out_reg, _bundle_literal_expr_208 - connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_206) @[reg_alloc.rs 374:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] - HdlNone: - connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 343:17] - HdlSome(_match_arm_value_149): - skip - when not(unit_0.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13] - connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 348:17] - match selected_unit_indexes[1]: @[reg_alloc.rs 351:13] - HdlNone: - skip - HdlSome(_match_arm_value_150): - when eq(_match_arm_value_150, UInt<64>(0h0)): @[reg_alloc.rs 353:17] - wire and_then_out_1: Ty67 @[reg_alloc.rs 357:25] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] - match renamed_mops[1]: @[reg_alloc.rs 357:25] - HdlNone: - connect and_then_out_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] - HdlSome(_match_arm_value_151): - wire alu_branch_mop_1: Ty67 @[unit.rs 128:1] - connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1] - match _match_arm_value_151: @[unit.rs 128:1] - AluBranch(_match_arm_value_152): - connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_153): - skip - LoadStore(_match_arm_value_154): - skip - connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 357:25] - match and_then_out_1: @[reg_alloc.rs 356:21] - HdlNone: - wire _uninit_expr_14: Ty46 - invalidate _uninit_expr_14 - connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 361:25] - HdlSome(_match_arm_value_155): - connect unit_0.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 359:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] - HdlNone: - skip - HdlSome(_match_arm_value_156): - wire _bundle_literal_expr_209: Ty25 - wire _bundle_literal_expr_210: Ty23 - connect _bundle_literal_expr_210.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_209.unit_num, _bundle_literal_expr_210 - wire _bundle_literal_expr_211: Ty24 - connect _bundle_literal_expr_211.value, _match_arm_value_156 - connect _bundle_literal_expr_209.unit_out_reg, _bundle_literal_expr_211 - connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_209) @[reg_alloc.rs 374:25] - wire _bundle_literal_expr_212: Ty66 - wire _array_literal_expr_75: Ty65[2] - connect _array_literal_expr_75[0], {|HdlNone, HdlSome: Ty64|}(HdlNone) - connect _array_literal_expr_75[1], {|HdlNone, HdlSome: Ty64|}(HdlNone) - connect _bundle_literal_expr_212.unit_output_writes, _array_literal_expr_75 - wire _bundle_literal_expr_213: Ty2 - invalidate _bundle_literal_expr_213 - connect _bundle_literal_expr_212._phantom, _bundle_literal_expr_213 - connect unit_0.unit_to_reg_alloc.unit_forwarding_info, _bundle_literal_expr_212 @[reg_alloc.rs 389:9] - connect unit_0.unit_to_reg_alloc.cancel_input, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 401:9] - inst unit_1 of alu_branch_1 @[reg_alloc.rs 311:13] - connect unit_1.cd, cd @[reg_alloc.rs 313:9] - inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 326:13] - connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9] - wire _uninit_expr_15: Ty77 - invalidate _uninit_expr_15 - connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_15 @[reg_alloc.rs 330:9] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9] - connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] - HdlNone: - connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 343:17] - HdlSome(_match_arm_value_157): - skip - when not(unit_1.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13] - connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 348:17] - match selected_unit_indexes[0]: @[reg_alloc.rs 351:13] - HdlNone: - skip - HdlSome(_match_arm_value_158): - when eq(_match_arm_value_158, UInt<64>(0h1)): @[reg_alloc.rs 353:17] - wire and_then_out_2: Ty67 @[reg_alloc.rs 357:25] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] - match renamed_mops[0]: @[reg_alloc.rs 357:25] - HdlNone: - connect and_then_out_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] - HdlSome(_match_arm_value_159): - wire alu_branch_mop_2: Ty67 @[unit.rs 128:1] - connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1] - match _match_arm_value_159: @[unit.rs 128:1] - AluBranch(_match_arm_value_160): - connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_161): - skip - LoadStore(_match_arm_value_162): - skip - connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 357:25] - match and_then_out_2: @[reg_alloc.rs 356:21] - HdlNone: - wire _uninit_expr_16: Ty46 - invalidate _uninit_expr_16 - connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 361:25] - HdlSome(_match_arm_value_163): - connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 359:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] - HdlNone: - skip - HdlSome(_match_arm_value_164): - wire _bundle_literal_expr_214: Ty25 - wire _bundle_literal_expr_215: Ty23 - connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215 - wire _bundle_literal_expr_216: Ty24 - connect _bundle_literal_expr_216.value, _match_arm_value_164 - connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216 - connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_214) @[reg_alloc.rs 374:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] - HdlNone: - connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 343:17] - HdlSome(_match_arm_value_165): - skip - when not(unit_1.unit_to_reg_alloc.input_insn.ready): @[reg_alloc.rs 346:13] - connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 348:17] - match selected_unit_indexes[1]: @[reg_alloc.rs 351:13] - HdlNone: - skip - HdlSome(_match_arm_value_166): - when eq(_match_arm_value_166, UInt<64>(0h1)): @[reg_alloc.rs 353:17] - wire and_then_out_3: Ty67 @[reg_alloc.rs 357:25] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] - match renamed_mops[1]: @[reg_alloc.rs 357:25] - HdlNone: - connect and_then_out_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] - HdlSome(_match_arm_value_167): - wire alu_branch_mop_3: Ty67 @[unit.rs 128:1] - connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 128:1] - match _match_arm_value_167: @[unit.rs 128:1] - AluBranch(_match_arm_value_168): - connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 128:1] - L2RegisterFile(_match_arm_value_169): - skip - LoadStore(_match_arm_value_170): - skip - connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 357:25] - match and_then_out_3: @[reg_alloc.rs 356:21] - HdlNone: - wire _uninit_expr_17: Ty46 - invalidate _uninit_expr_17 - connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 361:25] - HdlSome(_match_arm_value_171): - connect unit_1.unit_to_reg_alloc.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 359:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] - HdlNone: - skip - HdlSome(_match_arm_value_172): - wire _bundle_literal_expr_217: Ty25 - wire _bundle_literal_expr_218: Ty23 - connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218 - wire _bundle_literal_expr_219: Ty24 - connect _bundle_literal_expr_219.value, _match_arm_value_172 - connect _bundle_literal_expr_217.unit_out_reg, _bundle_literal_expr_219 - connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_217) @[reg_alloc.rs 374:25] - wire _bundle_literal_expr_220: Ty66 - wire _array_literal_expr_76: Ty65[2] - connect _array_literal_expr_76[0], {|HdlNone, HdlSome: Ty64|}(HdlNone) - connect _array_literal_expr_76[1], {|HdlNone, HdlSome: Ty64|}(HdlNone) - connect _bundle_literal_expr_220.unit_output_writes, _array_literal_expr_76 - wire _bundle_literal_expr_221: Ty2 - invalidate _bundle_literal_expr_221 - connect _bundle_literal_expr_220._phantom, _bundle_literal_expr_221 - connect unit_1.unit_to_reg_alloc.unit_forwarding_info, _bundle_literal_expr_220 @[reg_alloc.rs 389:9] - connect unit_1.unit_to_reg_alloc.cancel_input, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 401:9] - module alu_branch: @[alu_branch.rs 17:1] - input cd: Ty0 @[alu_branch.rs 20:29] - output unit_to_reg_alloc: Ty75 @[alu_branch.rs 28:11] - inst unit_base of unit_base @[alu_branch.rs 33:21] - connect unit_to_reg_alloc, unit_base.unit_to_reg_alloc @[alu_branch.rs 39:5] - connect unit_base.cd, cd @[alu_branch.rs 40:5] - connect unit_base.execute_start.ready, UInt<1>(0h1) @[alu_branch.rs 41:5] - connect unit_base.execute_end, {|HdlNone, HdlSome: Ty83|}(HdlNone) @[alu_branch.rs 42:5] - module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1] - input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] - input free_in: Ty78[1] @[unit_free_regs_tracker.rs 17:11] - output alloc_out: Ty78[1] @[unit_free_regs_tracker.rs 20:11] - wire _array_literal_expr: UInt<1>[16] - connect _array_literal_expr[0], UInt<1>(0h0) - connect _array_literal_expr[1], UInt<1>(0h0) - connect _array_literal_expr[2], UInt<1>(0h0) - connect _array_literal_expr[3], UInt<1>(0h0) - connect _array_literal_expr[4], UInt<1>(0h0) - connect _array_literal_expr[5], UInt<1>(0h0) - connect _array_literal_expr[6], UInt<1>(0h0) - connect _array_literal_expr[7], UInt<1>(0h0) - connect _array_literal_expr[8], UInt<1>(0h0) - connect _array_literal_expr[9], UInt<1>(0h0) - connect _array_literal_expr[10], UInt<1>(0h0) - connect _array_literal_expr[11], UInt<1>(0h0) - connect _array_literal_expr[12], UInt<1>(0h0) - connect _array_literal_expr[13], UInt<1>(0h0) - connect _array_literal_expr[14], UInt<1>(0h0) - connect _array_literal_expr[15], UInt<1>(0h0) - regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] - connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] - wire firing_data: Ty77 @[ready_valid.rs 30:27] - connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] - when free_in[0].ready: @[ready_valid.rs 33:9] - connect firing_data, free_in[0].data @[ready_valid.rs 34:13] - match firing_data: @[unit_free_regs_tracker.rs 31:9] - HdlNone: - skip - HdlSome(_match_arm_value): - connect allocated_reg[_match_arm_value], UInt<1>(0h0) @[unit_free_regs_tracker.rs 32:13] - wire reduced_count_0_2: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_2, add(not(allocated_reg[0]), not(allocated_reg[1])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_2: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_2, or(or(neq(add(not(allocated_reg[0]), not(allocated_reg[1])), reduced_count_0_2), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_2: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[0]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_1: UInt<0>[1] - connect _array_literal_expr_1[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_0_2[0], _array_literal_expr_1[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_2: UInt<0>[1] - connect _array_literal_expr_2[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_2[0], add(_array_literal_expr_2[sub(UInt<64>(0h0), not(allocated_reg[0]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_2_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_2_4, add(not(allocated_reg[2]), not(allocated_reg[3])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_2_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_2_4, or(or(neq(add(not(allocated_reg[2]), not(allocated_reg[3])), reduced_count_2_4), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_2_4: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[2]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_3: UInt<0>[1] - connect _array_literal_expr_3[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_2_4[0], _array_literal_expr_3[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_4: UInt<0>[1] - connect _array_literal_expr_4[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_2_4[0], add(_array_literal_expr_4[sub(UInt<64>(0h0), not(allocated_reg[2]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_4, add(reduced_count_0_2, reduced_count_2_4) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_4, or(or(neq(add(reduced_count_0_2, reduced_count_2_4), reduced_count_0_4), reduced_count_overflowed_0_2), reduced_count_overflowed_2_4) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_4: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_2, gt(reduced_count_0_2, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_0_4[0], reduced_alloc_nums_0_2[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_4[0], add(reduced_alloc_nums_2_4[sub(UInt<64>(0h0), reduced_count_0_2)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_4_6: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_4_6, add(not(allocated_reg[4]), not(allocated_reg[5])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_4_6: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_4_6, or(or(neq(add(not(allocated_reg[4]), not(allocated_reg[5])), reduced_count_4_6), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_4_6: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[4]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_5: UInt<0>[1] - connect _array_literal_expr_5[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_4_6[0], _array_literal_expr_5[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_6: UInt<0>[1] - connect _array_literal_expr_6[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_4_6[0], add(_array_literal_expr_6[sub(UInt<64>(0h0), not(allocated_reg[4]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_6_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_6_8, add(not(allocated_reg[6]), not(allocated_reg[7])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_6_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_6_8, or(or(neq(add(not(allocated_reg[6]), not(allocated_reg[7])), reduced_count_6_8), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_6_8: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[6]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_7: UInt<0>[1] - connect _array_literal_expr_7[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_6_8[0], _array_literal_expr_7[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_8: UInt<0>[1] - connect _array_literal_expr_8[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_6_8[0], add(_array_literal_expr_8[sub(UInt<64>(0h0), not(allocated_reg[6]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_4_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_4_8, add(reduced_count_4_6, reduced_count_6_8) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_4_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_4_8, or(or(neq(add(reduced_count_4_6, reduced_count_6_8), reduced_count_4_8), reduced_count_overflowed_4_6), reduced_count_overflowed_6_8) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_4_8: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_4_6, gt(reduced_count_4_6, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_4_8[0], reduced_alloc_nums_4_6[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_4_8[0], add(reduced_alloc_nums_6_8[sub(UInt<64>(0h0), reduced_count_4_6)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_8, add(reduced_count_0_4, reduced_count_4_8) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_8, or(or(neq(add(reduced_count_0_4, reduced_count_4_8), reduced_count_0_8), reduced_count_overflowed_0_4), reduced_count_overflowed_4_8) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_8: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_4, gt(reduced_count_0_4, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<2> - connect reduced_alloc_nums_0_8[0], reduced_alloc_nums_0_4[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_8[0], add(reduced_alloc_nums_4_8[sub(UInt<64>(0h0), reduced_count_0_4)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_10: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_10, add(not(allocated_reg[8]), not(allocated_reg[9])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_10: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_10, or(or(neq(add(not(allocated_reg[8]), not(allocated_reg[9])), reduced_count_8_10), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_10: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[8]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_9: UInt<0>[1] - connect _array_literal_expr_9[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_8_10[0], _array_literal_expr_9[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_10: UInt<0>[1] - connect _array_literal_expr_10[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_10[0], add(_array_literal_expr_10[sub(UInt<64>(0h0), not(allocated_reg[8]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_10_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_10_12, add(not(allocated_reg[10]), not(allocated_reg[11])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_10_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_10_12, or(or(neq(add(not(allocated_reg[10]), not(allocated_reg[11])), reduced_count_10_12), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_10_12: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[10]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_11: UInt<0>[1] - connect _array_literal_expr_11[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_10_12[0], _array_literal_expr_11[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_12: UInt<0>[1] - connect _array_literal_expr_12[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_10_12[0], add(_array_literal_expr_12[sub(UInt<64>(0h0), not(allocated_reg[10]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_12, add(reduced_count_8_10, reduced_count_10_12) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_12, or(or(neq(add(reduced_count_8_10, reduced_count_10_12), reduced_count_8_12), reduced_count_overflowed_8_10), reduced_count_overflowed_10_12) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_12: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_8_10, gt(reduced_count_8_10, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_8_12[0], reduced_alloc_nums_8_10[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_12[0], add(reduced_alloc_nums_10_12[sub(UInt<64>(0h0), reduced_count_8_10)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_12_14: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_12_14, add(not(allocated_reg[12]), not(allocated_reg[13])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_12_14: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_12_14, or(or(neq(add(not(allocated_reg[12]), not(allocated_reg[13])), reduced_count_12_14), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_12_14: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[12]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_13: UInt<0>[1] - connect _array_literal_expr_13[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_12_14[0], _array_literal_expr_13[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_14: UInt<0>[1] - connect _array_literal_expr_14[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_12_14[0], add(_array_literal_expr_14[sub(UInt<64>(0h0), not(allocated_reg[12]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_14_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_14_16, add(not(allocated_reg[14]), not(allocated_reg[15])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_14_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_14_16, or(or(neq(add(not(allocated_reg[14]), not(allocated_reg[15])), reduced_count_14_16), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_14_16: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[14]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_15: UInt<0>[1] - connect _array_literal_expr_15[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_14_16[0], _array_literal_expr_15[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_16: UInt<0>[1] - connect _array_literal_expr_16[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_14_16[0], add(_array_literal_expr_16[sub(UInt<64>(0h0), not(allocated_reg[14]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_12_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_12_16, add(reduced_count_12_14, reduced_count_14_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_12_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_12_16, or(or(neq(add(reduced_count_12_14, reduced_count_14_16), reduced_count_12_16), reduced_count_overflowed_12_14), reduced_count_overflowed_14_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_12_16: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_12_14, gt(reduced_count_12_14, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_12_16[0], reduced_alloc_nums_12_14[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_12_16[0], add(reduced_alloc_nums_14_16[sub(UInt<64>(0h0), reduced_count_12_14)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_16, add(reduced_count_8_12, reduced_count_12_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_16, or(or(neq(add(reduced_count_8_12, reduced_count_12_16), reduced_count_8_16), reduced_count_overflowed_8_12), reduced_count_overflowed_12_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_16: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_8_12, gt(reduced_count_8_12, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<2> - connect reduced_alloc_nums_8_16[0], reduced_alloc_nums_8_12[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_16[0], add(reduced_alloc_nums_12_16[sub(UInt<64>(0h0), reduced_count_8_12)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_16, add(reduced_count_0_8, reduced_count_8_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_16, or(or(neq(add(reduced_count_0_8, reduced_count_8_16), reduced_count_0_16), reduced_count_overflowed_0_8), reduced_count_overflowed_8_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_16: UInt<4>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_8, gt(reduced_count_0_8, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<4> - ; rhs: UInt<3> - connect reduced_alloc_nums_0_16[0], reduced_alloc_nums_0_8[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<4> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] - wire firing_data_1: Ty77 @[ready_valid.rs 30:27] - connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] - when alloc_out[0].ready: @[ready_valid.rs 33:9] - connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] - match firing_data_1: @[unit_free_regs_tracker.rs 102:9] - HdlNone: - skip - HdlSome(_match_arm_value_1): - connect allocated_reg[_match_arm_value_1], UInt<1>(0h1) @[unit_free_regs_tracker.rs 103:13] - when or(reduced_count_overflowed_0_16, gt(reduced_count_0_16, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 106:9] - connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] - else: - connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] - module alu_branch_1: @[alu_branch.rs 17:1] - input cd: Ty0 @[alu_branch.rs 20:29] - output unit_to_reg_alloc: Ty75 @[alu_branch.rs 28:11] - inst unit_base of unit_base_1 @[alu_branch.rs 33:21] - connect unit_to_reg_alloc, unit_base.unit_to_reg_alloc @[alu_branch.rs 39:5] - connect unit_base.cd, cd @[alu_branch.rs 40:5] - connect unit_base.execute_start.ready, UInt<1>(0h1) @[alu_branch.rs 41:5] - connect unit_base.execute_end, {|HdlNone, HdlSome: Ty83|}(HdlNone) @[alu_branch.rs 42:5] - module unit_free_regs_tracker_1: @[unit_free_regs_tracker.rs 7:1] - input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] - input free_in: Ty78[1] @[unit_free_regs_tracker.rs 17:11] - output alloc_out: Ty78[1] @[unit_free_regs_tracker.rs 20:11] - wire _array_literal_expr: UInt<1>[16] - connect _array_literal_expr[0], UInt<1>(0h0) - connect _array_literal_expr[1], UInt<1>(0h0) - connect _array_literal_expr[2], UInt<1>(0h0) - connect _array_literal_expr[3], UInt<1>(0h0) - connect _array_literal_expr[4], UInt<1>(0h0) - connect _array_literal_expr[5], UInt<1>(0h0) - connect _array_literal_expr[6], UInt<1>(0h0) - connect _array_literal_expr[7], UInt<1>(0h0) - connect _array_literal_expr[8], UInt<1>(0h0) - connect _array_literal_expr[9], UInt<1>(0h0) - connect _array_literal_expr[10], UInt<1>(0h0) - connect _array_literal_expr[11], UInt<1>(0h0) - connect _array_literal_expr[12], UInt<1>(0h0) - connect _array_literal_expr[13], UInt<1>(0h0) - connect _array_literal_expr[14], UInt<1>(0h0) - connect _array_literal_expr[15], UInt<1>(0h0) - regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] - connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] - wire firing_data: Ty77 @[ready_valid.rs 30:27] - connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] - when free_in[0].ready: @[ready_valid.rs 33:9] - connect firing_data, free_in[0].data @[ready_valid.rs 34:13] - match firing_data: @[unit_free_regs_tracker.rs 31:9] - HdlNone: - skip - HdlSome(_match_arm_value): - connect allocated_reg[_match_arm_value], UInt<1>(0h0) @[unit_free_regs_tracker.rs 32:13] - wire reduced_count_0_2: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_2, add(not(allocated_reg[0]), not(allocated_reg[1])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_2: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_2, or(or(neq(add(not(allocated_reg[0]), not(allocated_reg[1])), reduced_count_0_2), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_2: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[0]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_1: UInt<0>[1] - connect _array_literal_expr_1[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_0_2[0], _array_literal_expr_1[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_2: UInt<0>[1] - connect _array_literal_expr_2[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_2[0], add(_array_literal_expr_2[sub(UInt<64>(0h0), not(allocated_reg[0]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_2_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_2_4, add(not(allocated_reg[2]), not(allocated_reg[3])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_2_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_2_4, or(or(neq(add(not(allocated_reg[2]), not(allocated_reg[3])), reduced_count_2_4), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_2_4: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[2]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_3: UInt<0>[1] - connect _array_literal_expr_3[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_2_4[0], _array_literal_expr_3[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_4: UInt<0>[1] - connect _array_literal_expr_4[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_2_4[0], add(_array_literal_expr_4[sub(UInt<64>(0h0), not(allocated_reg[2]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_4, add(reduced_count_0_2, reduced_count_2_4) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_4, or(or(neq(add(reduced_count_0_2, reduced_count_2_4), reduced_count_0_4), reduced_count_overflowed_0_2), reduced_count_overflowed_2_4) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_4: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_2, gt(reduced_count_0_2, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_0_4[0], reduced_alloc_nums_0_2[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_4[0], add(reduced_alloc_nums_2_4[sub(UInt<64>(0h0), reduced_count_0_2)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_4_6: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_4_6, add(not(allocated_reg[4]), not(allocated_reg[5])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_4_6: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_4_6, or(or(neq(add(not(allocated_reg[4]), not(allocated_reg[5])), reduced_count_4_6), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_4_6: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[4]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_5: UInt<0>[1] - connect _array_literal_expr_5[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_4_6[0], _array_literal_expr_5[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_6: UInt<0>[1] - connect _array_literal_expr_6[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_4_6[0], add(_array_literal_expr_6[sub(UInt<64>(0h0), not(allocated_reg[4]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_6_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_6_8, add(not(allocated_reg[6]), not(allocated_reg[7])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_6_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_6_8, or(or(neq(add(not(allocated_reg[6]), not(allocated_reg[7])), reduced_count_6_8), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_6_8: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[6]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_7: UInt<0>[1] - connect _array_literal_expr_7[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_6_8[0], _array_literal_expr_7[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_8: UInt<0>[1] - connect _array_literal_expr_8[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_6_8[0], add(_array_literal_expr_8[sub(UInt<64>(0h0), not(allocated_reg[6]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_4_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_4_8, add(reduced_count_4_6, reduced_count_6_8) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_4_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_4_8, or(or(neq(add(reduced_count_4_6, reduced_count_6_8), reduced_count_4_8), reduced_count_overflowed_4_6), reduced_count_overflowed_6_8) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_4_8: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_4_6, gt(reduced_count_4_6, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_4_8[0], reduced_alloc_nums_4_6[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_4_8[0], add(reduced_alloc_nums_6_8[sub(UInt<64>(0h0), reduced_count_4_6)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_8, add(reduced_count_0_4, reduced_count_4_8) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_8, or(or(neq(add(reduced_count_0_4, reduced_count_4_8), reduced_count_0_8), reduced_count_overflowed_0_4), reduced_count_overflowed_4_8) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_8: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_4, gt(reduced_count_0_4, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<2> - connect reduced_alloc_nums_0_8[0], reduced_alloc_nums_0_4[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_8[0], add(reduced_alloc_nums_4_8[sub(UInt<64>(0h0), reduced_count_0_4)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_10: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_10, add(not(allocated_reg[8]), not(allocated_reg[9])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_10: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_10, or(or(neq(add(not(allocated_reg[8]), not(allocated_reg[9])), reduced_count_8_10), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_10: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[8]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_9: UInt<0>[1] - connect _array_literal_expr_9[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_8_10[0], _array_literal_expr_9[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_10: UInt<0>[1] - connect _array_literal_expr_10[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_10[0], add(_array_literal_expr_10[sub(UInt<64>(0h0), not(allocated_reg[8]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_10_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_10_12, add(not(allocated_reg[10]), not(allocated_reg[11])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_10_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_10_12, or(or(neq(add(not(allocated_reg[10]), not(allocated_reg[11])), reduced_count_10_12), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_10_12: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[10]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_11: UInt<0>[1] - connect _array_literal_expr_11[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_10_12[0], _array_literal_expr_11[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_12: UInt<0>[1] - connect _array_literal_expr_12[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_10_12[0], add(_array_literal_expr_12[sub(UInt<64>(0h0), not(allocated_reg[10]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_12, add(reduced_count_8_10, reduced_count_10_12) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_12, or(or(neq(add(reduced_count_8_10, reduced_count_10_12), reduced_count_8_12), reduced_count_overflowed_8_10), reduced_count_overflowed_10_12) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_12: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_8_10, gt(reduced_count_8_10, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_8_12[0], reduced_alloc_nums_8_10[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_12[0], add(reduced_alloc_nums_10_12[sub(UInt<64>(0h0), reduced_count_8_10)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_12_14: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_12_14, add(not(allocated_reg[12]), not(allocated_reg[13])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_12_14: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_12_14, or(or(neq(add(not(allocated_reg[12]), not(allocated_reg[13])), reduced_count_12_14), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_12_14: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[12]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_13: UInt<0>[1] - connect _array_literal_expr_13[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_12_14[0], _array_literal_expr_13[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_14: UInt<0>[1] - connect _array_literal_expr_14[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_12_14[0], add(_array_literal_expr_14[sub(UInt<64>(0h0), not(allocated_reg[12]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_14_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_14_16, add(not(allocated_reg[14]), not(allocated_reg[15])) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_14_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_14_16, or(or(neq(add(not(allocated_reg[14]), not(allocated_reg[15])), reduced_count_14_16), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_14_16: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] - when or(UInt<1>(0h0), gt(not(allocated_reg[14]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - wire _array_literal_expr_15: UInt<0>[1] - connect _array_literal_expr_15[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<0> - connect reduced_alloc_nums_14_16[0], _array_literal_expr_15[0] @[unit_free_regs_tracker.rs 81:21] - else: - wire _array_literal_expr_16: UInt<0>[1] - connect _array_literal_expr_16[0], UInt<0>(0h0) - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<65> - connect reduced_alloc_nums_14_16[0], add(_array_literal_expr_16[sub(UInt<64>(0h0), not(allocated_reg[14]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_12_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_12_16, add(reduced_count_12_14, reduced_count_14_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_12_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_12_16, or(or(neq(add(reduced_count_12_14, reduced_count_14_16), reduced_count_12_16), reduced_count_overflowed_12_14), reduced_count_overflowed_14_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_12_16: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_12_14, gt(reduced_count_12_14, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<1> - connect reduced_alloc_nums_12_16[0], reduced_alloc_nums_12_14[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<65> - connect reduced_alloc_nums_12_16[0], add(reduced_alloc_nums_14_16[sub(UInt<64>(0h0), reduced_count_12_14)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_8_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_8_16, add(reduced_count_8_12, reduced_count_12_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_8_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_8_16, or(or(neq(add(reduced_count_8_12, reduced_count_12_16), reduced_count_8_16), reduced_count_overflowed_8_12), reduced_count_overflowed_12_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_8_16: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_8_12, gt(reduced_count_8_12, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<2> - connect reduced_alloc_nums_8_16[0], reduced_alloc_nums_8_12[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<3> - ; rhs: UInt<65> - connect reduced_alloc_nums_8_16[0], add(reduced_alloc_nums_12_16[sub(UInt<64>(0h0), reduced_count_8_12)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] - wire reduced_count_0_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] - ; connect different types: - ; lhs: UInt<1> - ; rhs: UInt<2> - connect reduced_count_0_16, add(reduced_count_0_8, reduced_count_8_16) @[unit_free_regs_tracker.rs 63:13] - wire reduced_count_overflowed_0_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] - connect reduced_count_overflowed_0_16, or(or(neq(add(reduced_count_0_8, reduced_count_8_16), reduced_count_0_16), reduced_count_overflowed_0_8), reduced_count_overflowed_8_16) @[unit_free_regs_tracker.rs 69:13] - wire reduced_alloc_nums_0_16: UInt<4>[1] @[unit_free_regs_tracker.rs 75:17] - when or(reduced_count_overflowed_0_8, gt(reduced_count_0_8, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] - ; connect different types: - ; lhs: UInt<4> - ; rhs: UInt<3> - connect reduced_alloc_nums_0_16[0], reduced_alloc_nums_0_8[0] @[unit_free_regs_tracker.rs 81:21] - else: - ; connect different types: - ; lhs: UInt<4> - ; rhs: UInt<65> - connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] - wire firing_data_1: Ty77 @[ready_valid.rs 30:27] - connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] - when alloc_out[0].ready: @[ready_valid.rs 33:9] - connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] - match firing_data_1: @[unit_free_regs_tracker.rs 102:9] - HdlNone: - skip - HdlSome(_match_arm_value_1): - connect allocated_reg[_match_arm_value_1], UInt<1>(0h1) @[unit_free_regs_tracker.rs 103:13] - when or(reduced_count_overflowed_0_16, gt(reduced_count_0_16, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 106:9] - connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] - else: - connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] - module unit_base: @[unit_base.rs 225:1] - input cd: Ty0 @[unit_base.rs 236:29] - output unit_to_reg_alloc: Ty75 @[unit_base.rs 239:11] - output execute_start: Ty82 @[unit_base.rs 241:58] - input execute_end: Ty84 @[unit_base.rs 244:11] - connect execute_start.data, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[unit_base.rs 246:5] - wire _array_literal_expr: Ty88[8] - connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) - regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 251:25] - wire empty_op_index_0: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_0: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[0]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value): - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_1: UInt<1>[3] - wire _array_literal_expr_2: UInt<1>[3] - connect _array_literal_expr_2[0], UInt<1>(0h1) - connect _array_literal_expr_2[1], UInt<1>(0h1) - connect _array_literal_expr_2[2], UInt<1>(0h1) - connect _array_literal_expr_1[0], eq(_match_arm_value.src_ready_flags[0], _array_literal_expr_2[0]) - wire _array_literal_expr_3: UInt<1>[3] - connect _array_literal_expr_3[0], UInt<1>(0h1) - connect _array_literal_expr_3[1], UInt<1>(0h1) - connect _array_literal_expr_3[2], UInt<1>(0h1) - connect _array_literal_expr_1[1], eq(_match_arm_value.src_ready_flags[1], _array_literal_expr_3[1]) - wire _array_literal_expr_4: UInt<1>[3] - connect _array_literal_expr_4[0], UInt<1>(0h1) - connect _array_literal_expr_4[1], UInt<1>(0h1) - connect _array_literal_expr_4[2], UInt<1>(0h1) - connect _array_literal_expr_1[2], eq(_match_arm_value.src_ready_flags[2], _array_literal_expr_4[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr_1[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr_1[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr_1[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - when andr(_cast_to_bits_expr): @[unit_base.rs 182:21] - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_1: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_1: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[1]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_1): - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_1.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_5: UInt<1>[3] - wire _array_literal_expr_6: UInt<1>[3] - connect _array_literal_expr_6[0], UInt<1>(0h1) - connect _array_literal_expr_6[1], UInt<1>(0h1) - connect _array_literal_expr_6[2], UInt<1>(0h1) - connect _array_literal_expr_5[0], eq(_match_arm_value_1.src_ready_flags[0], _array_literal_expr_6[0]) - wire _array_literal_expr_7: UInt<1>[3] - connect _array_literal_expr_7[0], UInt<1>(0h1) - connect _array_literal_expr_7[1], UInt<1>(0h1) - connect _array_literal_expr_7[2], UInt<1>(0h1) - connect _array_literal_expr_5[1], eq(_match_arm_value_1.src_ready_flags[1], _array_literal_expr_7[1]) - wire _array_literal_expr_8: UInt<1>[3] - connect _array_literal_expr_8[0], UInt<1>(0h1) - connect _array_literal_expr_8[1], UInt<1>(0h1) - connect _array_literal_expr_8[2], UInt<1>(0h1) - connect _array_literal_expr_5[2], eq(_match_arm_value_1.src_ready_flags[2], _array_literal_expr_8[2]) - wire _cast_array_to_bits_expr_1: UInt<1>[3] - connect _cast_array_to_bits_expr_1[0], _array_literal_expr_5[0] - connect _cast_array_to_bits_expr_1[1], _array_literal_expr_5[1] - connect _cast_array_to_bits_expr_1[2], _array_literal_expr_5[2] - wire _cast_to_bits_expr_1: UInt<3> - connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0])) - when andr(_cast_to_bits_expr_1): @[unit_base.rs 182:21] - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr: Ty90 - connect _bundle_literal_expr.empty_op_index, empty_op_index_1 - connect _bundle_literal_expr.ready_op_index, ready_op_index_1 - connect or_out, _bundle_literal_expr.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_1: Ty90 - connect _bundle_literal_expr_1.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_1.ready_op_index, ready_op_index_0 - match _bundle_literal_expr_1.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_2): - wire _bundle_literal_expr_2: Ty90 - connect _bundle_literal_expr_2.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_2.ready_op_index, ready_op_index_0 - connect or_out, _bundle_literal_expr_2.empty_op_index @[unit_base.rs 203:29] - wire or_out_1: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_3: Ty90 - connect _bundle_literal_expr_3.empty_op_index, empty_op_index_1 - connect _bundle_literal_expr_3.ready_op_index, ready_op_index_1 - connect or_out_1, _bundle_literal_expr_3.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_4: Ty90 - connect _bundle_literal_expr_4.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_4.ready_op_index, ready_op_index_0 - match _bundle_literal_expr_4.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_3): - wire _bundle_literal_expr_5: Ty90 - connect _bundle_literal_expr_5.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_5.ready_op_index, ready_op_index_0 - connect or_out_1, _bundle_literal_expr_5.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_2: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_2: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[2]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_4): - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_4.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_9: UInt<1>[3] - wire _array_literal_expr_10: UInt<1>[3] - connect _array_literal_expr_10[0], UInt<1>(0h1) - connect _array_literal_expr_10[1], UInt<1>(0h1) - connect _array_literal_expr_10[2], UInt<1>(0h1) - connect _array_literal_expr_9[0], eq(_match_arm_value_4.src_ready_flags[0], _array_literal_expr_10[0]) - wire _array_literal_expr_11: UInt<1>[3] - connect _array_literal_expr_11[0], UInt<1>(0h1) - connect _array_literal_expr_11[1], UInt<1>(0h1) - connect _array_literal_expr_11[2], UInt<1>(0h1) - connect _array_literal_expr_9[1], eq(_match_arm_value_4.src_ready_flags[1], _array_literal_expr_11[1]) - wire _array_literal_expr_12: UInt<1>[3] - connect _array_literal_expr_12[0], UInt<1>(0h1) - connect _array_literal_expr_12[1], UInt<1>(0h1) - connect _array_literal_expr_12[2], UInt<1>(0h1) - connect _array_literal_expr_9[2], eq(_match_arm_value_4.src_ready_flags[2], _array_literal_expr_12[2]) - wire _cast_array_to_bits_expr_2: UInt<1>[3] - connect _cast_array_to_bits_expr_2[0], _array_literal_expr_9[0] - connect _cast_array_to_bits_expr_2[1], _array_literal_expr_9[1] - connect _cast_array_to_bits_expr_2[2], _array_literal_expr_9[2] - wire _cast_to_bits_expr_2: UInt<3> - connect _cast_to_bits_expr_2, cat(_cast_array_to_bits_expr_2[2], cat(_cast_array_to_bits_expr_2[1], _cast_array_to_bits_expr_2[0])) - when andr(_cast_to_bits_expr_2): @[unit_base.rs 182:21] - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_3: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_3: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[3]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_5): - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_5.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_13: UInt<1>[3] - wire _array_literal_expr_14: UInt<1>[3] - connect _array_literal_expr_14[0], UInt<1>(0h1) - connect _array_literal_expr_14[1], UInt<1>(0h1) - connect _array_literal_expr_14[2], UInt<1>(0h1) - connect _array_literal_expr_13[0], eq(_match_arm_value_5.src_ready_flags[0], _array_literal_expr_14[0]) - wire _array_literal_expr_15: UInt<1>[3] - connect _array_literal_expr_15[0], UInt<1>(0h1) - connect _array_literal_expr_15[1], UInt<1>(0h1) - connect _array_literal_expr_15[2], UInt<1>(0h1) - connect _array_literal_expr_13[1], eq(_match_arm_value_5.src_ready_flags[1], _array_literal_expr_15[1]) - wire _array_literal_expr_16: UInt<1>[3] - connect _array_literal_expr_16[0], UInt<1>(0h1) - connect _array_literal_expr_16[1], UInt<1>(0h1) - connect _array_literal_expr_16[2], UInt<1>(0h1) - connect _array_literal_expr_13[2], eq(_match_arm_value_5.src_ready_flags[2], _array_literal_expr_16[2]) - wire _cast_array_to_bits_expr_3: UInt<1>[3] - connect _cast_array_to_bits_expr_3[0], _array_literal_expr_13[0] - connect _cast_array_to_bits_expr_3[1], _array_literal_expr_13[1] - connect _cast_array_to_bits_expr_3[2], _array_literal_expr_13[2] - wire _cast_to_bits_expr_3: UInt<3> - connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr_3[2], cat(_cast_array_to_bits_expr_3[1], _cast_array_to_bits_expr_3[0])) - when andr(_cast_to_bits_expr_3): @[unit_base.rs 182:21] - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_2: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_6: Ty90 - connect _bundle_literal_expr_6.empty_op_index, empty_op_index_3 - connect _bundle_literal_expr_6.ready_op_index, ready_op_index_3 - connect or_out_2, _bundle_literal_expr_6.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_7: Ty90 - connect _bundle_literal_expr_7.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_7.ready_op_index, ready_op_index_2 - match _bundle_literal_expr_7.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_6): - wire _bundle_literal_expr_8: Ty90 - connect _bundle_literal_expr_8.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_8.ready_op_index, ready_op_index_2 - connect or_out_2, _bundle_literal_expr_8.empty_op_index @[unit_base.rs 203:29] - wire or_out_3: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_9: Ty90 - connect _bundle_literal_expr_9.empty_op_index, empty_op_index_3 - connect _bundle_literal_expr_9.ready_op_index, ready_op_index_3 - connect or_out_3, _bundle_literal_expr_9.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_10: Ty90 - connect _bundle_literal_expr_10.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_10.ready_op_index, ready_op_index_2 - match _bundle_literal_expr_10.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_7): - wire _bundle_literal_expr_11: Ty90 - connect _bundle_literal_expr_11.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_11.ready_op_index, ready_op_index_2 - connect or_out_3, _bundle_literal_expr_11.ready_op_index @[unit_base.rs 204:29] - wire or_out_4: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_12: Ty90 - connect _bundle_literal_expr_12.empty_op_index, or_out_2 - connect _bundle_literal_expr_12.ready_op_index, or_out_3 - connect or_out_4, _bundle_literal_expr_12.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_13: Ty90 - connect _bundle_literal_expr_13.empty_op_index, or_out - connect _bundle_literal_expr_13.ready_op_index, or_out_1 - match _bundle_literal_expr_13.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_8): - wire _bundle_literal_expr_14: Ty90 - connect _bundle_literal_expr_14.empty_op_index, or_out - connect _bundle_literal_expr_14.ready_op_index, or_out_1 - connect or_out_4, _bundle_literal_expr_14.empty_op_index @[unit_base.rs 203:29] - wire or_out_5: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_15: Ty90 - connect _bundle_literal_expr_15.empty_op_index, or_out_2 - connect _bundle_literal_expr_15.ready_op_index, or_out_3 - connect or_out_5, _bundle_literal_expr_15.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_16: Ty90 - connect _bundle_literal_expr_16.empty_op_index, or_out - connect _bundle_literal_expr_16.ready_op_index, or_out_1 - match _bundle_literal_expr_16.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_9): - wire _bundle_literal_expr_17: Ty90 - connect _bundle_literal_expr_17.empty_op_index, or_out - connect _bundle_literal_expr_17.ready_op_index, or_out_1 - connect or_out_5, _bundle_literal_expr_17.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_4: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_4: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[4]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_10): - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_10.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_17: UInt<1>[3] - wire _array_literal_expr_18: UInt<1>[3] - connect _array_literal_expr_18[0], UInt<1>(0h1) - connect _array_literal_expr_18[1], UInt<1>(0h1) - connect _array_literal_expr_18[2], UInt<1>(0h1) - connect _array_literal_expr_17[0], eq(_match_arm_value_10.src_ready_flags[0], _array_literal_expr_18[0]) - wire _array_literal_expr_19: UInt<1>[3] - connect _array_literal_expr_19[0], UInt<1>(0h1) - connect _array_literal_expr_19[1], UInt<1>(0h1) - connect _array_literal_expr_19[2], UInt<1>(0h1) - connect _array_literal_expr_17[1], eq(_match_arm_value_10.src_ready_flags[1], _array_literal_expr_19[1]) - wire _array_literal_expr_20: UInt<1>[3] - connect _array_literal_expr_20[0], UInt<1>(0h1) - connect _array_literal_expr_20[1], UInt<1>(0h1) - connect _array_literal_expr_20[2], UInt<1>(0h1) - connect _array_literal_expr_17[2], eq(_match_arm_value_10.src_ready_flags[2], _array_literal_expr_20[2]) - wire _cast_array_to_bits_expr_4: UInt<1>[3] - connect _cast_array_to_bits_expr_4[0], _array_literal_expr_17[0] - connect _cast_array_to_bits_expr_4[1], _array_literal_expr_17[1] - connect _cast_array_to_bits_expr_4[2], _array_literal_expr_17[2] - wire _cast_to_bits_expr_4: UInt<3> - connect _cast_to_bits_expr_4, cat(_cast_array_to_bits_expr_4[2], cat(_cast_array_to_bits_expr_4[1], _cast_array_to_bits_expr_4[0])) - when andr(_cast_to_bits_expr_4): @[unit_base.rs 182:21] - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_5: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_5: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[5]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_11): - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_11.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_21: UInt<1>[3] - wire _array_literal_expr_22: UInt<1>[3] - connect _array_literal_expr_22[0], UInt<1>(0h1) - connect _array_literal_expr_22[1], UInt<1>(0h1) - connect _array_literal_expr_22[2], UInt<1>(0h1) - connect _array_literal_expr_21[0], eq(_match_arm_value_11.src_ready_flags[0], _array_literal_expr_22[0]) - wire _array_literal_expr_23: UInt<1>[3] - connect _array_literal_expr_23[0], UInt<1>(0h1) - connect _array_literal_expr_23[1], UInt<1>(0h1) - connect _array_literal_expr_23[2], UInt<1>(0h1) - connect _array_literal_expr_21[1], eq(_match_arm_value_11.src_ready_flags[1], _array_literal_expr_23[1]) - wire _array_literal_expr_24: UInt<1>[3] - connect _array_literal_expr_24[0], UInt<1>(0h1) - connect _array_literal_expr_24[1], UInt<1>(0h1) - connect _array_literal_expr_24[2], UInt<1>(0h1) - connect _array_literal_expr_21[2], eq(_match_arm_value_11.src_ready_flags[2], _array_literal_expr_24[2]) - wire _cast_array_to_bits_expr_5: UInt<1>[3] - connect _cast_array_to_bits_expr_5[0], _array_literal_expr_21[0] - connect _cast_array_to_bits_expr_5[1], _array_literal_expr_21[1] - connect _cast_array_to_bits_expr_5[2], _array_literal_expr_21[2] - wire _cast_to_bits_expr_5: UInt<3> - connect _cast_to_bits_expr_5, cat(_cast_array_to_bits_expr_5[2], cat(_cast_array_to_bits_expr_5[1], _cast_array_to_bits_expr_5[0])) - when andr(_cast_to_bits_expr_5): @[unit_base.rs 182:21] - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_6: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_18: Ty90 - connect _bundle_literal_expr_18.empty_op_index, empty_op_index_5 - connect _bundle_literal_expr_18.ready_op_index, ready_op_index_5 - connect or_out_6, _bundle_literal_expr_18.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_19: Ty90 - connect _bundle_literal_expr_19.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_19.ready_op_index, ready_op_index_4 - match _bundle_literal_expr_19.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_12): - wire _bundle_literal_expr_20: Ty90 - connect _bundle_literal_expr_20.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_20.ready_op_index, ready_op_index_4 - connect or_out_6, _bundle_literal_expr_20.empty_op_index @[unit_base.rs 203:29] - wire or_out_7: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_21: Ty90 - connect _bundle_literal_expr_21.empty_op_index, empty_op_index_5 - connect _bundle_literal_expr_21.ready_op_index, ready_op_index_5 - connect or_out_7, _bundle_literal_expr_21.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_22: Ty90 - connect _bundle_literal_expr_22.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_22.ready_op_index, ready_op_index_4 - match _bundle_literal_expr_22.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_13): - wire _bundle_literal_expr_23: Ty90 - connect _bundle_literal_expr_23.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_23.ready_op_index, ready_op_index_4 - connect or_out_7, _bundle_literal_expr_23.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_6: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_6: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[6]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_14): - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_14.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_25: UInt<1>[3] - wire _array_literal_expr_26: UInt<1>[3] - connect _array_literal_expr_26[0], UInt<1>(0h1) - connect _array_literal_expr_26[1], UInt<1>(0h1) - connect _array_literal_expr_26[2], UInt<1>(0h1) - connect _array_literal_expr_25[0], eq(_match_arm_value_14.src_ready_flags[0], _array_literal_expr_26[0]) - wire _array_literal_expr_27: UInt<1>[3] - connect _array_literal_expr_27[0], UInt<1>(0h1) - connect _array_literal_expr_27[1], UInt<1>(0h1) - connect _array_literal_expr_27[2], UInt<1>(0h1) - connect _array_literal_expr_25[1], eq(_match_arm_value_14.src_ready_flags[1], _array_literal_expr_27[1]) - wire _array_literal_expr_28: UInt<1>[3] - connect _array_literal_expr_28[0], UInt<1>(0h1) - connect _array_literal_expr_28[1], UInt<1>(0h1) - connect _array_literal_expr_28[2], UInt<1>(0h1) - connect _array_literal_expr_25[2], eq(_match_arm_value_14.src_ready_flags[2], _array_literal_expr_28[2]) - wire _cast_array_to_bits_expr_6: UInt<1>[3] - connect _cast_array_to_bits_expr_6[0], _array_literal_expr_25[0] - connect _cast_array_to_bits_expr_6[1], _array_literal_expr_25[1] - connect _cast_array_to_bits_expr_6[2], _array_literal_expr_25[2] - wire _cast_to_bits_expr_6: UInt<3> - connect _cast_to_bits_expr_6, cat(_cast_array_to_bits_expr_6[2], cat(_cast_array_to_bits_expr_6[1], _cast_array_to_bits_expr_6[0])) - when andr(_cast_to_bits_expr_6): @[unit_base.rs 182:21] - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_7: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_7: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[7]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_15): - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_15.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_29: UInt<1>[3] - wire _array_literal_expr_30: UInt<1>[3] - connect _array_literal_expr_30[0], UInt<1>(0h1) - connect _array_literal_expr_30[1], UInt<1>(0h1) - connect _array_literal_expr_30[2], UInt<1>(0h1) - connect _array_literal_expr_29[0], eq(_match_arm_value_15.src_ready_flags[0], _array_literal_expr_30[0]) - wire _array_literal_expr_31: UInt<1>[3] - connect _array_literal_expr_31[0], UInt<1>(0h1) - connect _array_literal_expr_31[1], UInt<1>(0h1) - connect _array_literal_expr_31[2], UInt<1>(0h1) - connect _array_literal_expr_29[1], eq(_match_arm_value_15.src_ready_flags[1], _array_literal_expr_31[1]) - wire _array_literal_expr_32: UInt<1>[3] - connect _array_literal_expr_32[0], UInt<1>(0h1) - connect _array_literal_expr_32[1], UInt<1>(0h1) - connect _array_literal_expr_32[2], UInt<1>(0h1) - connect _array_literal_expr_29[2], eq(_match_arm_value_15.src_ready_flags[2], _array_literal_expr_32[2]) - wire _cast_array_to_bits_expr_7: UInt<1>[3] - connect _cast_array_to_bits_expr_7[0], _array_literal_expr_29[0] - connect _cast_array_to_bits_expr_7[1], _array_literal_expr_29[1] - connect _cast_array_to_bits_expr_7[2], _array_literal_expr_29[2] - wire _cast_to_bits_expr_7: UInt<3> - connect _cast_to_bits_expr_7, cat(_cast_array_to_bits_expr_7[2], cat(_cast_array_to_bits_expr_7[1], _cast_array_to_bits_expr_7[0])) - when andr(_cast_to_bits_expr_7): @[unit_base.rs 182:21] - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_8: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_24: Ty90 - connect _bundle_literal_expr_24.empty_op_index, empty_op_index_7 - connect _bundle_literal_expr_24.ready_op_index, ready_op_index_7 - connect or_out_8, _bundle_literal_expr_24.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_25: Ty90 - connect _bundle_literal_expr_25.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_25.ready_op_index, ready_op_index_6 - match _bundle_literal_expr_25.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_16): - wire _bundle_literal_expr_26: Ty90 - connect _bundle_literal_expr_26.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_26.ready_op_index, ready_op_index_6 - connect or_out_8, _bundle_literal_expr_26.empty_op_index @[unit_base.rs 203:29] - wire or_out_9: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_27: Ty90 - connect _bundle_literal_expr_27.empty_op_index, empty_op_index_7 - connect _bundle_literal_expr_27.ready_op_index, ready_op_index_7 - connect or_out_9, _bundle_literal_expr_27.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_28: Ty90 - connect _bundle_literal_expr_28.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_28.ready_op_index, ready_op_index_6 - match _bundle_literal_expr_28.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_17): - wire _bundle_literal_expr_29: Ty90 - connect _bundle_literal_expr_29.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_29.ready_op_index, ready_op_index_6 - connect or_out_9, _bundle_literal_expr_29.ready_op_index @[unit_base.rs 204:29] - wire or_out_10: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_30: Ty90 - connect _bundle_literal_expr_30.empty_op_index, or_out_8 - connect _bundle_literal_expr_30.ready_op_index, or_out_9 - connect or_out_10, _bundle_literal_expr_30.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_31: Ty90 - connect _bundle_literal_expr_31.empty_op_index, or_out_6 - connect _bundle_literal_expr_31.ready_op_index, or_out_7 - match _bundle_literal_expr_31.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_18): - wire _bundle_literal_expr_32: Ty90 - connect _bundle_literal_expr_32.empty_op_index, or_out_6 - connect _bundle_literal_expr_32.ready_op_index, or_out_7 - connect or_out_10, _bundle_literal_expr_32.empty_op_index @[unit_base.rs 203:29] - wire or_out_11: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_33: Ty90 - connect _bundle_literal_expr_33.empty_op_index, or_out_8 - connect _bundle_literal_expr_33.ready_op_index, or_out_9 - connect or_out_11, _bundle_literal_expr_33.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_34: Ty90 - connect _bundle_literal_expr_34.empty_op_index, or_out_6 - connect _bundle_literal_expr_34.ready_op_index, or_out_7 - match _bundle_literal_expr_34.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_19): - wire _bundle_literal_expr_35: Ty90 - connect _bundle_literal_expr_35.empty_op_index, or_out_6 - connect _bundle_literal_expr_35.ready_op_index, or_out_7 - connect or_out_11, _bundle_literal_expr_35.ready_op_index @[unit_base.rs 204:29] - wire or_out_12: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_36: Ty90 - connect _bundle_literal_expr_36.empty_op_index, or_out_10 - connect _bundle_literal_expr_36.ready_op_index, or_out_11 - connect or_out_12, _bundle_literal_expr_36.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_37: Ty90 - connect _bundle_literal_expr_37.empty_op_index, or_out_4 - connect _bundle_literal_expr_37.ready_op_index, or_out_5 - match _bundle_literal_expr_37.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_20): - wire _bundle_literal_expr_38: Ty90 - connect _bundle_literal_expr_38.empty_op_index, or_out_4 - connect _bundle_literal_expr_38.ready_op_index, or_out_5 - connect or_out_12, _bundle_literal_expr_38.empty_op_index @[unit_base.rs 203:29] - wire or_out_13: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_39: Ty90 - connect _bundle_literal_expr_39.empty_op_index, or_out_10 - connect _bundle_literal_expr_39.ready_op_index, or_out_11 - connect or_out_13, _bundle_literal_expr_39.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_40: Ty90 - connect _bundle_literal_expr_40.empty_op_index, or_out_4 - connect _bundle_literal_expr_40.ready_op_index, or_out_5 - match _bundle_literal_expr_40.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_21): - wire _bundle_literal_expr_41: Ty90 - connect _bundle_literal_expr_41.empty_op_index, or_out_4 - connect _bundle_literal_expr_41.ready_op_index, or_out_5 - connect or_out_13, _bundle_literal_expr_41.ready_op_index @[unit_base.rs 204:29] - wire in_flight_ops_summary: Ty90 @[unit_base.rs 257:33] - wire _bundle_literal_expr_42: Ty90 - connect _bundle_literal_expr_42.empty_op_index, or_out_12 - connect _bundle_literal_expr_42.ready_op_index, or_out_13 - connect in_flight_ops_summary, _bundle_literal_expr_42 @[unit_base.rs 258:5] - wire is_some_out: UInt<1> @[unit_base.rs 262:9] - connect is_some_out, UInt<1>(0h0) @[unit_base.rs 262:9] - match in_flight_ops_summary.empty_op_index: @[unit_base.rs 262:9] - HdlNone: - skip - HdlSome(_match_arm_value_22): - connect is_some_out, UInt<1>(0h1) @[unit_base.rs 262:9] - connect unit_to_reg_alloc.input_insn.ready, is_some_out @[unit_base.rs 260:5] - connect unit_to_reg_alloc.`output`, {|HdlNone, HdlSome: Ty73|}(HdlNone) @[unit_base.rs 266:5] - wire input_in_flight_op: Ty88 @[unit_base.rs 272:30] - connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 273:5] - wire firing_data: Ty67 @[ready_valid.rs 30:27] - connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9] - when unit_to_reg_alloc.input_insn.ready: @[ready_valid.rs 33:9] - connect firing_data, unit_to_reg_alloc.input_insn.data @[ready_valid.rs 34:13] - match firing_data: @[unit_base.rs 275:5] - HdlNone: - skip - HdlSome(_match_arm_value_23): - wire input_mop_src_regs: UInt<6>[3] @[unit_base.rs 277:34] - wire _array_literal_expr_33: UInt<6>[3] - wire _bundle_literal_expr_43: Ty25 - wire _bundle_literal_expr_44: Ty23 - connect _bundle_literal_expr_44.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_43.unit_num, _bundle_literal_expr_44 - wire _bundle_literal_expr_45: Ty24 - connect _bundle_literal_expr_45.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_43.unit_out_reg, _bundle_literal_expr_45 - wire _cast_bundle_to_bits_expr: Ty57 - connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_43.unit_num.adj_value - connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_43.unit_out_reg.value - wire _cast_to_bits_expr_8: UInt<6> - connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) - connect _array_literal_expr_33[0], _cast_to_bits_expr_8 - wire _bundle_literal_expr_46: Ty25 - wire _bundle_literal_expr_47: Ty23 - connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47 - wire _bundle_literal_expr_48: Ty24 - connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48 - wire _cast_bundle_to_bits_expr_1: Ty57 - connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_46.unit_num.adj_value - connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_46.unit_out_reg.value - wire _cast_to_bits_expr_9: UInt<6> - connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) - connect _array_literal_expr_33[1], _cast_to_bits_expr_9 - wire _bundle_literal_expr_49: Ty25 - wire _bundle_literal_expr_50: Ty23 - connect _bundle_literal_expr_50.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_49.unit_num, _bundle_literal_expr_50 - wire _bundle_literal_expr_51: Ty24 - connect _bundle_literal_expr_51.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_49.unit_out_reg, _bundle_literal_expr_51 - wire _cast_bundle_to_bits_expr_2: Ty57 - connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_49.unit_num.adj_value - connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_49.unit_out_reg.value - wire _cast_to_bits_expr_10: UInt<6> - connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) - connect _array_literal_expr_33[2], _cast_to_bits_expr_10 - connect input_mop_src_regs, _array_literal_expr_33 @[unit_base.rs 278:9] - match _match_arm_value_23: @[instruction.rs 538:1] - AddSub(_match_arm_value_24): - connect input_mop_src_regs[0], _match_arm_value_24.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_24.alu_common.common.src[1] @[instruction.rs 36:13] - connect input_mop_src_regs[2], _match_arm_value_24.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_25): - connect input_mop_src_regs[0], _match_arm_value_25.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_25.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_26): - connect input_mop_src_regs[0], _match_arm_value_26.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_26.alu_common.common.src[1] @[instruction.rs 36:13] - wire input_in_flight_op_src_ready_flags: UInt<1>[3] @[unit_base.rs 285:13] - wire _bundle_literal_expr_52: Ty25 - wire _bundle_literal_expr_53: Ty23 - connect _bundle_literal_expr_53.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_52.unit_num, _bundle_literal_expr_53 - wire _bundle_literal_expr_54: Ty24 - connect _bundle_literal_expr_54.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_52.unit_out_reg, _bundle_literal_expr_54 - wire _cast_bundle_to_bits_expr_3: Ty57 - connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_52.unit_num.adj_value - connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_52.unit_out_reg.value - wire _cast_to_bits_expr_11: UInt<6> - connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) - connect input_in_flight_op_src_ready_flags[0], eq(_cast_to_bits_expr_11, input_mop_src_regs[0]) @[unit_base.rs 289:13] - wire _bundle_literal_expr_55: Ty25 - wire _bundle_literal_expr_56: Ty23 - connect _bundle_literal_expr_56.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_55.unit_num, _bundle_literal_expr_56 - wire _bundle_literal_expr_57: Ty24 - connect _bundle_literal_expr_57.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_55.unit_out_reg, _bundle_literal_expr_57 - wire _cast_bundle_to_bits_expr_4: Ty57 - connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_55.unit_num.adj_value - connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_55.unit_out_reg.value - wire _cast_to_bits_expr_12: UInt<6> - connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) - connect input_in_flight_op_src_ready_flags[1], eq(_cast_to_bits_expr_12, input_mop_src_regs[1]) @[unit_base.rs 289:13] - wire _bundle_literal_expr_58: Ty25 - wire _bundle_literal_expr_59: Ty23 - connect _bundle_literal_expr_59.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_58.unit_num, _bundle_literal_expr_59 - wire _bundle_literal_expr_60: Ty24 - connect _bundle_literal_expr_60.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_58.unit_out_reg, _bundle_literal_expr_60 - wire _cast_bundle_to_bits_expr_5: Ty57 - connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_58.unit_num.adj_value - connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_58.unit_out_reg.value - wire _cast_to_bits_expr_13: UInt<6> - connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) - connect input_in_flight_op_src_ready_flags[2], eq(_cast_to_bits_expr_13, input_mop_src_regs[2]) @[unit_base.rs 289:13] - wire dest_reg: Ty24 @[instruction.rs 538:1] - match _match_arm_value_23: @[instruction.rs 538:1] - AddSub(_match_arm_value_27): - connect dest_reg, _match_arm_value_27.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_28): - connect dest_reg, _match_arm_value_28.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_29): - connect dest_reg, _match_arm_value_29.alu_common.common.dest @[instruction.rs 538:1] - wire cmp_ne: UInt<1> @[enum_.rs 396:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 398:9] - HdlNone: - wire _bundle_literal_expr_61: Ty69 - connect _bundle_literal_expr_61.which, dest_reg - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_61): @[enum_.rs 410:17] - HdlNone: - connect cmp_ne, UInt<1>(0h0) @[enum_.rs 412:32] - HdlSome(_match_arm_value_30): - connect cmp_ne, UInt<1>(0h1) @[enum_.rs 411:35] - HdlSome(_match_arm_value_31): - wire _bundle_literal_expr_62: Ty69 - connect _bundle_literal_expr_62.which, dest_reg - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_62): @[enum_.rs 402:17] - HdlNone: - connect cmp_ne, UInt<1>(0h1) @[enum_.rs 404:32] - HdlSome(_match_arm_value_32): - connect cmp_ne, neq(_match_arm_value_31.which.value, _match_arm_value_32.which.value) @[enum_.rs 403:37] - when cmp_ne: @[unit_base.rs 299:9] - wire _bundle_literal_expr_63: Ty87 - connect _bundle_literal_expr_63.state, {|Ready, Running, CanceledAndRunning|}(Ready) - connect _bundle_literal_expr_63.mop, _match_arm_value_23 - connect _bundle_literal_expr_63.src_ready_flags, input_in_flight_op_src_ready_flags - connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_63) @[unit_base.rs 305:13] - match in_flight_ops_summary.empty_op_index: @[unit_base.rs 318:9] - HdlNone: - skip - HdlSome(_match_arm_value_33): - connect in_flight_ops[_match_arm_value_33], input_in_flight_op @[unit_base.rs 319:13] - wire in_flight_op_next_state: Ty91[8] @[unit_base.rs 324:35] - wire in_flight_op_next_src_ready_flags: UInt<1>[3][8] @[unit_base.rs 327:9] - wire in_flight_op_canceling: UInt<1>[8] @[unit_base.rs 329:34] - wire in_flight_op_execute_starting: UInt<1>[8] @[unit_base.rs 331:41] - wire in_flight_op_execute_ending: UInt<1>[8] @[unit_base.rs 333:39] - wire _array_literal_expr_34: UInt<1>[3] - connect _array_literal_expr_34[0], UInt<1>(0h0) - connect _array_literal_expr_34[1], UInt<1>(0h0) - connect _array_literal_expr_34[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[0], _array_literal_expr_34 @[unit_base.rs 335:9] - connect in_flight_op_canceling[0], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[0], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[0], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[0]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_34): - wire dest_reg_1: Ty24 @[instruction.rs 538:1] - match _match_arm_value_34.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_35): - connect dest_reg_1, _match_arm_value_35.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_36): - connect dest_reg_1, _match_arm_value_36.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_37): - connect dest_reg_1, _match_arm_value_37.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_0: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_35: UInt<6>[3] - wire _bundle_literal_expr_64: Ty25 - wire _bundle_literal_expr_65: Ty23 - connect _bundle_literal_expr_65.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_64.unit_num, _bundle_literal_expr_65 - wire _bundle_literal_expr_66: Ty24 - connect _bundle_literal_expr_66.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_64.unit_out_reg, _bundle_literal_expr_66 - wire _cast_bundle_to_bits_expr_6: Ty57 - connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_64.unit_num.adj_value - connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_64.unit_out_reg.value - wire _cast_to_bits_expr_14: UInt<6> - connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) - connect _array_literal_expr_35[0], _cast_to_bits_expr_14 - wire _bundle_literal_expr_67: Ty25 - wire _bundle_literal_expr_68: Ty23 - connect _bundle_literal_expr_68.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_67.unit_num, _bundle_literal_expr_68 - wire _bundle_literal_expr_69: Ty24 - connect _bundle_literal_expr_69.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_67.unit_out_reg, _bundle_literal_expr_69 - wire _cast_bundle_to_bits_expr_7: Ty57 - connect _cast_bundle_to_bits_expr_7.unit_num, _bundle_literal_expr_67.unit_num.adj_value - connect _cast_bundle_to_bits_expr_7.unit_out_reg, _bundle_literal_expr_67.unit_out_reg.value - wire _cast_to_bits_expr_15: UInt<6> - connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num) - connect _array_literal_expr_35[1], _cast_to_bits_expr_15 - wire _bundle_literal_expr_70: Ty25 - wire _bundle_literal_expr_71: Ty23 - connect _bundle_literal_expr_71.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_70.unit_num, _bundle_literal_expr_71 - wire _bundle_literal_expr_72: Ty24 - connect _bundle_literal_expr_72.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_70.unit_out_reg, _bundle_literal_expr_72 - wire _cast_bundle_to_bits_expr_8: Ty57 - connect _cast_bundle_to_bits_expr_8.unit_num, _bundle_literal_expr_70.unit_num.adj_value - connect _cast_bundle_to_bits_expr_8.unit_out_reg, _bundle_literal_expr_70.unit_out_reg.value - wire _cast_to_bits_expr_16: UInt<6> - connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num) - connect _array_literal_expr_35[2], _cast_to_bits_expr_16 - connect in_flight_op_src_regs_0, _array_literal_expr_35 @[unit_base.rs 356:13] - match _match_arm_value_34.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_38): - connect in_flight_op_src_regs_0[0], _match_arm_value_38.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_38.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[2], _match_arm_value_38.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_39): - connect in_flight_op_src_regs_0[0], _match_arm_value_39.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_39.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_40): - connect in_flight_op_src_regs_0[0], _match_arm_value_40.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_40.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[0], _match_arm_value_34.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_41): - wire _bundle_literal_expr_73: Ty25 - wire _bundle_literal_expr_74: Ty23 - connect _bundle_literal_expr_74.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_73.unit_num, _bundle_literal_expr_74 - connect _bundle_literal_expr_73.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_9: Ty57 - connect _cast_bundle_to_bits_expr_9.unit_num, _bundle_literal_expr_73.unit_num.adj_value - connect _cast_bundle_to_bits_expr_9.unit_out_reg, _bundle_literal_expr_73.unit_out_reg.value - wire _cast_to_bits_expr_17: UInt<6> - connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_9.unit_out_reg, _cast_bundle_to_bits_expr_9.unit_num) - when eq(_cast_to_bits_expr_17, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_75: Ty25 - wire _bundle_literal_expr_76: Ty23 - connect _bundle_literal_expr_76.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_75.unit_num, _bundle_literal_expr_76 - connect _bundle_literal_expr_75.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_10: Ty57 - connect _cast_bundle_to_bits_expr_10.unit_num, _bundle_literal_expr_75.unit_num.adj_value - connect _cast_bundle_to_bits_expr_10.unit_out_reg, _bundle_literal_expr_75.unit_out_reg.value - wire _cast_to_bits_expr_18: UInt<6> - connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_10.unit_out_reg, _cast_bundle_to_bits_expr_10.unit_num) - when eq(_cast_to_bits_expr_18, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_77: Ty25 - wire _bundle_literal_expr_78: Ty23 - connect _bundle_literal_expr_78.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_77.unit_num, _bundle_literal_expr_78 - connect _bundle_literal_expr_77.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_11: Ty57 - connect _cast_bundle_to_bits_expr_11.unit_num, _bundle_literal_expr_77.unit_num.adj_value - connect _cast_bundle_to_bits_expr_11.unit_out_reg, _bundle_literal_expr_77.unit_out_reg.value - wire _cast_to_bits_expr_19: UInt<6> - connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num) - when eq(_cast_to_bits_expr_19, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_42): - wire _bundle_literal_expr_79: Ty25 - wire _bundle_literal_expr_80: Ty23 - connect _bundle_literal_expr_80.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_79.unit_num, _bundle_literal_expr_80 - connect _bundle_literal_expr_79.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_12: Ty57 - connect _cast_bundle_to_bits_expr_12.unit_num, _bundle_literal_expr_79.unit_num.adj_value - connect _cast_bundle_to_bits_expr_12.unit_out_reg, _bundle_literal_expr_79.unit_out_reg.value - wire _cast_to_bits_expr_20: UInt<6> - connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num) - when eq(_cast_to_bits_expr_20, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_81: Ty25 - wire _bundle_literal_expr_82: Ty23 - connect _bundle_literal_expr_82.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_81.unit_num, _bundle_literal_expr_82 - connect _bundle_literal_expr_81.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_13: Ty57 - connect _cast_bundle_to_bits_expr_13.unit_num, _bundle_literal_expr_81.unit_num.adj_value - connect _cast_bundle_to_bits_expr_13.unit_out_reg, _bundle_literal_expr_81.unit_out_reg.value - wire _cast_to_bits_expr_21: UInt<6> - connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num) - when eq(_cast_to_bits_expr_21, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_83: Ty25 - wire _bundle_literal_expr_84: Ty23 - connect _bundle_literal_expr_84.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_83.unit_num, _bundle_literal_expr_84 - connect _bundle_literal_expr_83.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_14: Ty57 - connect _cast_bundle_to_bits_expr_14.unit_num, _bundle_literal_expr_83.unit_num.adj_value - connect _cast_bundle_to_bits_expr_14.unit_out_reg, _bundle_literal_expr_83.unit_out_reg.value - wire _cast_to_bits_expr_22: UInt<6> - connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num) - when eq(_cast_to_bits_expr_22, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_85: Ty69 - connect _bundle_literal_expr_85.which, dest_reg_1 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_85): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_43): - connect cmp_eq, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_44): - wire _bundle_literal_expr_86: Ty69 - connect _bundle_literal_expr_86.which, dest_reg_1 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_86): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_45): - connect cmp_eq, eq(_match_arm_value_44.which.value, _match_arm_value_45.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[0], cmp_eq @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_46): - when eq(dest_reg_1.value, _match_arm_value_46.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[0], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_1: Ty81 @[ready_valid.rs 30:27] - connect firing_data_1, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_1, execute_start.data @[ready_valid.rs 34:13] - match firing_data_1: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_47): - wire dest_reg_2: Ty24 @[instruction.rs 538:1] - match _match_arm_value_47.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_48): - connect dest_reg_2, _match_arm_value_48.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_49): - connect dest_reg_2, _match_arm_value_49.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_50): - connect dest_reg_2, _match_arm_value_50.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_1.value, dest_reg_2.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[0], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_34.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[0]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_51): - wire _bundle_literal_expr_87: Ty87 - connect _bundle_literal_expr_87.state, _match_arm_value_51 - connect _bundle_literal_expr_87.mop, _match_arm_value_34.mop - connect _bundle_literal_expr_87.src_ready_flags, _match_arm_value_34.src_ready_flags - connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_87) @[unit_base.rs 435:17] - wire _array_literal_expr_36: UInt<1>[3] - connect _array_literal_expr_36[0], UInt<1>(0h0) - connect _array_literal_expr_36[1], UInt<1>(0h0) - connect _array_literal_expr_36[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[1], _array_literal_expr_36 @[unit_base.rs 335:9] - connect in_flight_op_canceling[1], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[1], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[1], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[1]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_52): - wire dest_reg_3: Ty24 @[instruction.rs 538:1] - match _match_arm_value_52.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_53): - connect dest_reg_3, _match_arm_value_53.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_54): - connect dest_reg_3, _match_arm_value_54.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_55): - connect dest_reg_3, _match_arm_value_55.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_1: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_37: UInt<6>[3] - wire _bundle_literal_expr_88: Ty25 - wire _bundle_literal_expr_89: Ty23 - connect _bundle_literal_expr_89.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_88.unit_num, _bundle_literal_expr_89 - wire _bundle_literal_expr_90: Ty24 - connect _bundle_literal_expr_90.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_88.unit_out_reg, _bundle_literal_expr_90 - wire _cast_bundle_to_bits_expr_15: Ty57 - connect _cast_bundle_to_bits_expr_15.unit_num, _bundle_literal_expr_88.unit_num.adj_value - connect _cast_bundle_to_bits_expr_15.unit_out_reg, _bundle_literal_expr_88.unit_out_reg.value - wire _cast_to_bits_expr_23: UInt<6> - connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_15.unit_out_reg, _cast_bundle_to_bits_expr_15.unit_num) - connect _array_literal_expr_37[0], _cast_to_bits_expr_23 - wire _bundle_literal_expr_91: Ty25 - wire _bundle_literal_expr_92: Ty23 - connect _bundle_literal_expr_92.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_91.unit_num, _bundle_literal_expr_92 - wire _bundle_literal_expr_93: Ty24 - connect _bundle_literal_expr_93.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_91.unit_out_reg, _bundle_literal_expr_93 - wire _cast_bundle_to_bits_expr_16: Ty57 - connect _cast_bundle_to_bits_expr_16.unit_num, _bundle_literal_expr_91.unit_num.adj_value - connect _cast_bundle_to_bits_expr_16.unit_out_reg, _bundle_literal_expr_91.unit_out_reg.value - wire _cast_to_bits_expr_24: UInt<6> - connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_16.unit_out_reg, _cast_bundle_to_bits_expr_16.unit_num) - connect _array_literal_expr_37[1], _cast_to_bits_expr_24 - wire _bundle_literal_expr_94: Ty25 - wire _bundle_literal_expr_95: Ty23 - connect _bundle_literal_expr_95.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_94.unit_num, _bundle_literal_expr_95 - wire _bundle_literal_expr_96: Ty24 - connect _bundle_literal_expr_96.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_94.unit_out_reg, _bundle_literal_expr_96 - wire _cast_bundle_to_bits_expr_17: Ty57 - connect _cast_bundle_to_bits_expr_17.unit_num, _bundle_literal_expr_94.unit_num.adj_value - connect _cast_bundle_to_bits_expr_17.unit_out_reg, _bundle_literal_expr_94.unit_out_reg.value - wire _cast_to_bits_expr_25: UInt<6> - connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_17.unit_out_reg, _cast_bundle_to_bits_expr_17.unit_num) - connect _array_literal_expr_37[2], _cast_to_bits_expr_25 - connect in_flight_op_src_regs_1, _array_literal_expr_37 @[unit_base.rs 356:13] - match _match_arm_value_52.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_56): - connect in_flight_op_src_regs_1[0], _match_arm_value_56.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_56.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[2], _match_arm_value_56.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_57): - connect in_flight_op_src_regs_1[0], _match_arm_value_57.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_57.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_58): - connect in_flight_op_src_regs_1[0], _match_arm_value_58.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_58.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[1], _match_arm_value_52.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_59): - wire _bundle_literal_expr_97: Ty25 - wire _bundle_literal_expr_98: Ty23 - connect _bundle_literal_expr_98.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_97.unit_num, _bundle_literal_expr_98 - connect _bundle_literal_expr_97.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_18: Ty57 - connect _cast_bundle_to_bits_expr_18.unit_num, _bundle_literal_expr_97.unit_num.adj_value - connect _cast_bundle_to_bits_expr_18.unit_out_reg, _bundle_literal_expr_97.unit_out_reg.value - wire _cast_to_bits_expr_26: UInt<6> - connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num) - when eq(_cast_to_bits_expr_26, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_99: Ty25 - wire _bundle_literal_expr_100: Ty23 - connect _bundle_literal_expr_100.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_99.unit_num, _bundle_literal_expr_100 - connect _bundle_literal_expr_99.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_19: Ty57 - connect _cast_bundle_to_bits_expr_19.unit_num, _bundle_literal_expr_99.unit_num.adj_value - connect _cast_bundle_to_bits_expr_19.unit_out_reg, _bundle_literal_expr_99.unit_out_reg.value - wire _cast_to_bits_expr_27: UInt<6> - connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num) - when eq(_cast_to_bits_expr_27, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_101: Ty25 - wire _bundle_literal_expr_102: Ty23 - connect _bundle_literal_expr_102.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_101.unit_num, _bundle_literal_expr_102 - connect _bundle_literal_expr_101.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_20: Ty57 - connect _cast_bundle_to_bits_expr_20.unit_num, _bundle_literal_expr_101.unit_num.adj_value - connect _cast_bundle_to_bits_expr_20.unit_out_reg, _bundle_literal_expr_101.unit_out_reg.value - wire _cast_to_bits_expr_28: UInt<6> - connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num) - when eq(_cast_to_bits_expr_28, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_60): - wire _bundle_literal_expr_103: Ty25 - wire _bundle_literal_expr_104: Ty23 - connect _bundle_literal_expr_104.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_103.unit_num, _bundle_literal_expr_104 - connect _bundle_literal_expr_103.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_21: Ty57 - connect _cast_bundle_to_bits_expr_21.unit_num, _bundle_literal_expr_103.unit_num.adj_value - connect _cast_bundle_to_bits_expr_21.unit_out_reg, _bundle_literal_expr_103.unit_out_reg.value - wire _cast_to_bits_expr_29: UInt<6> - connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num) - when eq(_cast_to_bits_expr_29, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_105: Ty25 - wire _bundle_literal_expr_106: Ty23 - connect _bundle_literal_expr_106.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_105.unit_num, _bundle_literal_expr_106 - connect _bundle_literal_expr_105.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_22: Ty57 - connect _cast_bundle_to_bits_expr_22.unit_num, _bundle_literal_expr_105.unit_num.adj_value - connect _cast_bundle_to_bits_expr_22.unit_out_reg, _bundle_literal_expr_105.unit_out_reg.value - wire _cast_to_bits_expr_30: UInt<6> - connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_22.unit_out_reg, _cast_bundle_to_bits_expr_22.unit_num) - when eq(_cast_to_bits_expr_30, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_107: Ty25 - wire _bundle_literal_expr_108: Ty23 - connect _bundle_literal_expr_108.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_107.unit_num, _bundle_literal_expr_108 - connect _bundle_literal_expr_107.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_23: Ty57 - connect _cast_bundle_to_bits_expr_23.unit_num, _bundle_literal_expr_107.unit_num.adj_value - connect _cast_bundle_to_bits_expr_23.unit_out_reg, _bundle_literal_expr_107.unit_out_reg.value - wire _cast_to_bits_expr_31: UInt<6> - connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_23.unit_out_reg, _cast_bundle_to_bits_expr_23.unit_num) - when eq(_cast_to_bits_expr_31, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_1: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_109: Ty69 - connect _bundle_literal_expr_109.which, dest_reg_3 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_109): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_1, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_61): - connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_62): - wire _bundle_literal_expr_110: Ty69 - connect _bundle_literal_expr_110.which, dest_reg_3 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_110): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_63): - connect cmp_eq_1, eq(_match_arm_value_62.which.value, _match_arm_value_63.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[1], cmp_eq_1 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_64): - when eq(dest_reg_3.value, _match_arm_value_64.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[1], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_2: Ty81 @[ready_valid.rs 30:27] - connect firing_data_2, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_2, execute_start.data @[ready_valid.rs 34:13] - match firing_data_2: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_65): - wire dest_reg_4: Ty24 @[instruction.rs 538:1] - match _match_arm_value_65.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_66): - connect dest_reg_4, _match_arm_value_66.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_67): - connect dest_reg_4, _match_arm_value_67.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_68): - connect dest_reg_4, _match_arm_value_68.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_3.value, dest_reg_4.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[1], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_52.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[1]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_69): - wire _bundle_literal_expr_111: Ty87 - connect _bundle_literal_expr_111.state, _match_arm_value_69 - connect _bundle_literal_expr_111.mop, _match_arm_value_52.mop - connect _bundle_literal_expr_111.src_ready_flags, _match_arm_value_52.src_ready_flags - connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_111) @[unit_base.rs 435:17] - wire _array_literal_expr_38: UInt<1>[3] - connect _array_literal_expr_38[0], UInt<1>(0h0) - connect _array_literal_expr_38[1], UInt<1>(0h0) - connect _array_literal_expr_38[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[2], _array_literal_expr_38 @[unit_base.rs 335:9] - connect in_flight_op_canceling[2], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[2], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[2], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[2]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_70): - wire dest_reg_5: Ty24 @[instruction.rs 538:1] - match _match_arm_value_70.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_71): - connect dest_reg_5, _match_arm_value_71.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_72): - connect dest_reg_5, _match_arm_value_72.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_73): - connect dest_reg_5, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_2: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_39: UInt<6>[3] - wire _bundle_literal_expr_112: Ty25 - wire _bundle_literal_expr_113: Ty23 - connect _bundle_literal_expr_113.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_112.unit_num, _bundle_literal_expr_113 - wire _bundle_literal_expr_114: Ty24 - connect _bundle_literal_expr_114.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_112.unit_out_reg, _bundle_literal_expr_114 - wire _cast_bundle_to_bits_expr_24: Ty57 - connect _cast_bundle_to_bits_expr_24.unit_num, _bundle_literal_expr_112.unit_num.adj_value - connect _cast_bundle_to_bits_expr_24.unit_out_reg, _bundle_literal_expr_112.unit_out_reg.value - wire _cast_to_bits_expr_32: UInt<6> - connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_24.unit_out_reg, _cast_bundle_to_bits_expr_24.unit_num) - connect _array_literal_expr_39[0], _cast_to_bits_expr_32 - wire _bundle_literal_expr_115: Ty25 - wire _bundle_literal_expr_116: Ty23 - connect _bundle_literal_expr_116.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_115.unit_num, _bundle_literal_expr_116 - wire _bundle_literal_expr_117: Ty24 - connect _bundle_literal_expr_117.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_115.unit_out_reg, _bundle_literal_expr_117 - wire _cast_bundle_to_bits_expr_25: Ty57 - connect _cast_bundle_to_bits_expr_25.unit_num, _bundle_literal_expr_115.unit_num.adj_value - connect _cast_bundle_to_bits_expr_25.unit_out_reg, _bundle_literal_expr_115.unit_out_reg.value - wire _cast_to_bits_expr_33: UInt<6> - connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_25.unit_out_reg, _cast_bundle_to_bits_expr_25.unit_num) - connect _array_literal_expr_39[1], _cast_to_bits_expr_33 - wire _bundle_literal_expr_118: Ty25 - wire _bundle_literal_expr_119: Ty23 - connect _bundle_literal_expr_119.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_118.unit_num, _bundle_literal_expr_119 - wire _bundle_literal_expr_120: Ty24 - connect _bundle_literal_expr_120.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_118.unit_out_reg, _bundle_literal_expr_120 - wire _cast_bundle_to_bits_expr_26: Ty57 - connect _cast_bundle_to_bits_expr_26.unit_num, _bundle_literal_expr_118.unit_num.adj_value - connect _cast_bundle_to_bits_expr_26.unit_out_reg, _bundle_literal_expr_118.unit_out_reg.value - wire _cast_to_bits_expr_34: UInt<6> - connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_26.unit_out_reg, _cast_bundle_to_bits_expr_26.unit_num) - connect _array_literal_expr_39[2], _cast_to_bits_expr_34 - connect in_flight_op_src_regs_2, _array_literal_expr_39 @[unit_base.rs 356:13] - match _match_arm_value_70.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_74): - connect in_flight_op_src_regs_2[0], _match_arm_value_74.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_74.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[2], _match_arm_value_74.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_75): - connect in_flight_op_src_regs_2[0], _match_arm_value_75.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_75.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_76): - connect in_flight_op_src_regs_2[0], _match_arm_value_76.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_76.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[2], _match_arm_value_70.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_77): - wire _bundle_literal_expr_121: Ty25 - wire _bundle_literal_expr_122: Ty23 - connect _bundle_literal_expr_122.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_121.unit_num, _bundle_literal_expr_122 - connect _bundle_literal_expr_121.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_27: Ty57 - connect _cast_bundle_to_bits_expr_27.unit_num, _bundle_literal_expr_121.unit_num.adj_value - connect _cast_bundle_to_bits_expr_27.unit_out_reg, _bundle_literal_expr_121.unit_out_reg.value - wire _cast_to_bits_expr_35: UInt<6> - connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_27.unit_out_reg, _cast_bundle_to_bits_expr_27.unit_num) - when eq(_cast_to_bits_expr_35, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_123: Ty25 - wire _bundle_literal_expr_124: Ty23 - connect _bundle_literal_expr_124.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_123.unit_num, _bundle_literal_expr_124 - connect _bundle_literal_expr_123.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_28: Ty57 - connect _cast_bundle_to_bits_expr_28.unit_num, _bundle_literal_expr_123.unit_num.adj_value - connect _cast_bundle_to_bits_expr_28.unit_out_reg, _bundle_literal_expr_123.unit_out_reg.value - wire _cast_to_bits_expr_36: UInt<6> - connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num) - when eq(_cast_to_bits_expr_36, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_125: Ty25 - wire _bundle_literal_expr_126: Ty23 - connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126 - connect _bundle_literal_expr_125.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_29: Ty57 - connect _cast_bundle_to_bits_expr_29.unit_num, _bundle_literal_expr_125.unit_num.adj_value - connect _cast_bundle_to_bits_expr_29.unit_out_reg, _bundle_literal_expr_125.unit_out_reg.value - wire _cast_to_bits_expr_37: UInt<6> - connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_29.unit_out_reg, _cast_bundle_to_bits_expr_29.unit_num) - when eq(_cast_to_bits_expr_37, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_78): - wire _bundle_literal_expr_127: Ty25 - wire _bundle_literal_expr_128: Ty23 - connect _bundle_literal_expr_128.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_127.unit_num, _bundle_literal_expr_128 - connect _bundle_literal_expr_127.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_30: Ty57 - connect _cast_bundle_to_bits_expr_30.unit_num, _bundle_literal_expr_127.unit_num.adj_value - connect _cast_bundle_to_bits_expr_30.unit_out_reg, _bundle_literal_expr_127.unit_out_reg.value - wire _cast_to_bits_expr_38: UInt<6> - connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_30.unit_out_reg, _cast_bundle_to_bits_expr_30.unit_num) - when eq(_cast_to_bits_expr_38, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_129: Ty25 - wire _bundle_literal_expr_130: Ty23 - connect _bundle_literal_expr_130.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_129.unit_num, _bundle_literal_expr_130 - connect _bundle_literal_expr_129.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_31: Ty57 - connect _cast_bundle_to_bits_expr_31.unit_num, _bundle_literal_expr_129.unit_num.adj_value - connect _cast_bundle_to_bits_expr_31.unit_out_reg, _bundle_literal_expr_129.unit_out_reg.value - wire _cast_to_bits_expr_39: UInt<6> - connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_31.unit_out_reg, _cast_bundle_to_bits_expr_31.unit_num) - when eq(_cast_to_bits_expr_39, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_131: Ty25 - wire _bundle_literal_expr_132: Ty23 - connect _bundle_literal_expr_132.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_131.unit_num, _bundle_literal_expr_132 - connect _bundle_literal_expr_131.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_32: Ty57 - connect _cast_bundle_to_bits_expr_32.unit_num, _bundle_literal_expr_131.unit_num.adj_value - connect _cast_bundle_to_bits_expr_32.unit_out_reg, _bundle_literal_expr_131.unit_out_reg.value - wire _cast_to_bits_expr_40: UInt<6> - connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_32.unit_out_reg, _cast_bundle_to_bits_expr_32.unit_num) - when eq(_cast_to_bits_expr_40, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_2: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_133: Ty69 - connect _bundle_literal_expr_133.which, dest_reg_5 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_133): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_2, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_79): - connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_80): - wire _bundle_literal_expr_134: Ty69 - connect _bundle_literal_expr_134.which, dest_reg_5 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_134): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_81): - connect cmp_eq_2, eq(_match_arm_value_80.which.value, _match_arm_value_81.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[2], cmp_eq_2 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_82): - when eq(dest_reg_5.value, _match_arm_value_82.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[2], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_3: Ty81 @[ready_valid.rs 30:27] - connect firing_data_3, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_3, execute_start.data @[ready_valid.rs 34:13] - match firing_data_3: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_83): - wire dest_reg_6: Ty24 @[instruction.rs 538:1] - match _match_arm_value_83.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_84): - connect dest_reg_6, _match_arm_value_84.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_85): - connect dest_reg_6, _match_arm_value_85.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_86): - connect dest_reg_6, _match_arm_value_86.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_5.value, dest_reg_6.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[2], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_70.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[2]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_87): - wire _bundle_literal_expr_135: Ty87 - connect _bundle_literal_expr_135.state, _match_arm_value_87 - connect _bundle_literal_expr_135.mop, _match_arm_value_70.mop - connect _bundle_literal_expr_135.src_ready_flags, _match_arm_value_70.src_ready_flags - connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_135) @[unit_base.rs 435:17] - wire _array_literal_expr_40: UInt<1>[3] - connect _array_literal_expr_40[0], UInt<1>(0h0) - connect _array_literal_expr_40[1], UInt<1>(0h0) - connect _array_literal_expr_40[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[3], _array_literal_expr_40 @[unit_base.rs 335:9] - connect in_flight_op_canceling[3], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[3], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[3], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[3]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_88): - wire dest_reg_7: Ty24 @[instruction.rs 538:1] - match _match_arm_value_88.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_89): - connect dest_reg_7, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_90): - connect dest_reg_7, _match_arm_value_90.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_91): - connect dest_reg_7, _match_arm_value_91.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_3: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_41: UInt<6>[3] - wire _bundle_literal_expr_136: Ty25 - wire _bundle_literal_expr_137: Ty23 - connect _bundle_literal_expr_137.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137 - wire _bundle_literal_expr_138: Ty24 - connect _bundle_literal_expr_138.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138 - wire _cast_bundle_to_bits_expr_33: Ty57 - connect _cast_bundle_to_bits_expr_33.unit_num, _bundle_literal_expr_136.unit_num.adj_value - connect _cast_bundle_to_bits_expr_33.unit_out_reg, _bundle_literal_expr_136.unit_out_reg.value - wire _cast_to_bits_expr_41: UInt<6> - connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_33.unit_out_reg, _cast_bundle_to_bits_expr_33.unit_num) - connect _array_literal_expr_41[0], _cast_to_bits_expr_41 - wire _bundle_literal_expr_139: Ty25 - wire _bundle_literal_expr_140: Ty23 - connect _bundle_literal_expr_140.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_139.unit_num, _bundle_literal_expr_140 - wire _bundle_literal_expr_141: Ty24 - connect _bundle_literal_expr_141.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_139.unit_out_reg, _bundle_literal_expr_141 - wire _cast_bundle_to_bits_expr_34: Ty57 - connect _cast_bundle_to_bits_expr_34.unit_num, _bundle_literal_expr_139.unit_num.adj_value - connect _cast_bundle_to_bits_expr_34.unit_out_reg, _bundle_literal_expr_139.unit_out_reg.value - wire _cast_to_bits_expr_42: UInt<6> - connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_34.unit_out_reg, _cast_bundle_to_bits_expr_34.unit_num) - connect _array_literal_expr_41[1], _cast_to_bits_expr_42 - wire _bundle_literal_expr_142: Ty25 - wire _bundle_literal_expr_143: Ty23 - connect _bundle_literal_expr_143.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_142.unit_num, _bundle_literal_expr_143 - wire _bundle_literal_expr_144: Ty24 - connect _bundle_literal_expr_144.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_142.unit_out_reg, _bundle_literal_expr_144 - wire _cast_bundle_to_bits_expr_35: Ty57 - connect _cast_bundle_to_bits_expr_35.unit_num, _bundle_literal_expr_142.unit_num.adj_value - connect _cast_bundle_to_bits_expr_35.unit_out_reg, _bundle_literal_expr_142.unit_out_reg.value - wire _cast_to_bits_expr_43: UInt<6> - connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num) - connect _array_literal_expr_41[2], _cast_to_bits_expr_43 - connect in_flight_op_src_regs_3, _array_literal_expr_41 @[unit_base.rs 356:13] - match _match_arm_value_88.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_92): - connect in_flight_op_src_regs_3[0], _match_arm_value_92.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_92.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[2], _match_arm_value_92.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_93): - connect in_flight_op_src_regs_3[0], _match_arm_value_93.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_93.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_94): - connect in_flight_op_src_regs_3[0], _match_arm_value_94.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_94.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[3], _match_arm_value_88.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_95): - wire _bundle_literal_expr_145: Ty25 - wire _bundle_literal_expr_146: Ty23 - connect _bundle_literal_expr_146.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_145.unit_num, _bundle_literal_expr_146 - connect _bundle_literal_expr_145.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_36: Ty57 - connect _cast_bundle_to_bits_expr_36.unit_num, _bundle_literal_expr_145.unit_num.adj_value - connect _cast_bundle_to_bits_expr_36.unit_out_reg, _bundle_literal_expr_145.unit_out_reg.value - wire _cast_to_bits_expr_44: UInt<6> - connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_36.unit_out_reg, _cast_bundle_to_bits_expr_36.unit_num) - when eq(_cast_to_bits_expr_44, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_147: Ty25 - wire _bundle_literal_expr_148: Ty23 - connect _bundle_literal_expr_148.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_147.unit_num, _bundle_literal_expr_148 - connect _bundle_literal_expr_147.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_37: Ty57 - connect _cast_bundle_to_bits_expr_37.unit_num, _bundle_literal_expr_147.unit_num.adj_value - connect _cast_bundle_to_bits_expr_37.unit_out_reg, _bundle_literal_expr_147.unit_out_reg.value - wire _cast_to_bits_expr_45: UInt<6> - connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_37.unit_out_reg, _cast_bundle_to_bits_expr_37.unit_num) - when eq(_cast_to_bits_expr_45, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_149: Ty25 - wire _bundle_literal_expr_150: Ty23 - connect _bundle_literal_expr_150.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_149.unit_num, _bundle_literal_expr_150 - connect _bundle_literal_expr_149.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_38: Ty57 - connect _cast_bundle_to_bits_expr_38.unit_num, _bundle_literal_expr_149.unit_num.adj_value - connect _cast_bundle_to_bits_expr_38.unit_out_reg, _bundle_literal_expr_149.unit_out_reg.value - wire _cast_to_bits_expr_46: UInt<6> - connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_38.unit_out_reg, _cast_bundle_to_bits_expr_38.unit_num) - when eq(_cast_to_bits_expr_46, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_96): - wire _bundle_literal_expr_151: Ty25 - wire _bundle_literal_expr_152: Ty23 - connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152 - connect _bundle_literal_expr_151.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_39: Ty57 - connect _cast_bundle_to_bits_expr_39.unit_num, _bundle_literal_expr_151.unit_num.adj_value - connect _cast_bundle_to_bits_expr_39.unit_out_reg, _bundle_literal_expr_151.unit_out_reg.value - wire _cast_to_bits_expr_47: UInt<6> - connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num) - when eq(_cast_to_bits_expr_47, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_153: Ty25 - wire _bundle_literal_expr_154: Ty23 - connect _bundle_literal_expr_154.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_153.unit_num, _bundle_literal_expr_154 - connect _bundle_literal_expr_153.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_40: Ty57 - connect _cast_bundle_to_bits_expr_40.unit_num, _bundle_literal_expr_153.unit_num.adj_value - connect _cast_bundle_to_bits_expr_40.unit_out_reg, _bundle_literal_expr_153.unit_out_reg.value - wire _cast_to_bits_expr_48: UInt<6> - connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num) - when eq(_cast_to_bits_expr_48, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_155: Ty25 - wire _bundle_literal_expr_156: Ty23 - connect _bundle_literal_expr_156.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_155.unit_num, _bundle_literal_expr_156 - connect _bundle_literal_expr_155.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_41: Ty57 - connect _cast_bundle_to_bits_expr_41.unit_num, _bundle_literal_expr_155.unit_num.adj_value - connect _cast_bundle_to_bits_expr_41.unit_out_reg, _bundle_literal_expr_155.unit_out_reg.value - wire _cast_to_bits_expr_49: UInt<6> - connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num) - when eq(_cast_to_bits_expr_49, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_3: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_157: Ty69 - connect _bundle_literal_expr_157.which, dest_reg_7 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_157): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_3, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_97): - connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_98): - wire _bundle_literal_expr_158: Ty69 - connect _bundle_literal_expr_158.which, dest_reg_7 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_158): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_99): - connect cmp_eq_3, eq(_match_arm_value_98.which.value, _match_arm_value_99.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[3], cmp_eq_3 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_100): - when eq(dest_reg_7.value, _match_arm_value_100.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[3], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_4: Ty81 @[ready_valid.rs 30:27] - connect firing_data_4, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_4, execute_start.data @[ready_valid.rs 34:13] - match firing_data_4: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_101): - wire dest_reg_8: Ty24 @[instruction.rs 538:1] - match _match_arm_value_101.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_102): - connect dest_reg_8, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_103): - connect dest_reg_8, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_104): - connect dest_reg_8, _match_arm_value_104.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_7.value, dest_reg_8.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[3], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_88.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[3]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_105): - wire _bundle_literal_expr_159: Ty87 - connect _bundle_literal_expr_159.state, _match_arm_value_105 - connect _bundle_literal_expr_159.mop, _match_arm_value_88.mop - connect _bundle_literal_expr_159.src_ready_flags, _match_arm_value_88.src_ready_flags - connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_159) @[unit_base.rs 435:17] - wire _array_literal_expr_42: UInt<1>[3] - connect _array_literal_expr_42[0], UInt<1>(0h0) - connect _array_literal_expr_42[1], UInt<1>(0h0) - connect _array_literal_expr_42[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[4], _array_literal_expr_42 @[unit_base.rs 335:9] - connect in_flight_op_canceling[4], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[4], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[4], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[4]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_106): - wire dest_reg_9: Ty24 @[instruction.rs 538:1] - match _match_arm_value_106.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_107): - connect dest_reg_9, _match_arm_value_107.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_108): - connect dest_reg_9, _match_arm_value_108.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_109): - connect dest_reg_9, _match_arm_value_109.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_4: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_43: UInt<6>[3] - wire _bundle_literal_expr_160: Ty25 - wire _bundle_literal_expr_161: Ty23 - connect _bundle_literal_expr_161.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_160.unit_num, _bundle_literal_expr_161 - wire _bundle_literal_expr_162: Ty24 - connect _bundle_literal_expr_162.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_160.unit_out_reg, _bundle_literal_expr_162 - wire _cast_bundle_to_bits_expr_42: Ty57 - connect _cast_bundle_to_bits_expr_42.unit_num, _bundle_literal_expr_160.unit_num.adj_value - connect _cast_bundle_to_bits_expr_42.unit_out_reg, _bundle_literal_expr_160.unit_out_reg.value - wire _cast_to_bits_expr_50: UInt<6> - connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num) - connect _array_literal_expr_43[0], _cast_to_bits_expr_50 - wire _bundle_literal_expr_163: Ty25 - wire _bundle_literal_expr_164: Ty23 - connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164 - wire _bundle_literal_expr_165: Ty24 - connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165 - wire _cast_bundle_to_bits_expr_43: Ty57 - connect _cast_bundle_to_bits_expr_43.unit_num, _bundle_literal_expr_163.unit_num.adj_value - connect _cast_bundle_to_bits_expr_43.unit_out_reg, _bundle_literal_expr_163.unit_out_reg.value - wire _cast_to_bits_expr_51: UInt<6> - connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num) - connect _array_literal_expr_43[1], _cast_to_bits_expr_51 - wire _bundle_literal_expr_166: Ty25 - wire _bundle_literal_expr_167: Ty23 - connect _bundle_literal_expr_167.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_166.unit_num, _bundle_literal_expr_167 - wire _bundle_literal_expr_168: Ty24 - connect _bundle_literal_expr_168.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_166.unit_out_reg, _bundle_literal_expr_168 - wire _cast_bundle_to_bits_expr_44: Ty57 - connect _cast_bundle_to_bits_expr_44.unit_num, _bundle_literal_expr_166.unit_num.adj_value - connect _cast_bundle_to_bits_expr_44.unit_out_reg, _bundle_literal_expr_166.unit_out_reg.value - wire _cast_to_bits_expr_52: UInt<6> - connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num) - connect _array_literal_expr_43[2], _cast_to_bits_expr_52 - connect in_flight_op_src_regs_4, _array_literal_expr_43 @[unit_base.rs 356:13] - match _match_arm_value_106.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_110): - connect in_flight_op_src_regs_4[0], _match_arm_value_110.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_110.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[2], _match_arm_value_110.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_111): - connect in_flight_op_src_regs_4[0], _match_arm_value_111.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_111.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_112): - connect in_flight_op_src_regs_4[0], _match_arm_value_112.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_112.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[4], _match_arm_value_106.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_113): - wire _bundle_literal_expr_169: Ty25 - wire _bundle_literal_expr_170: Ty23 - connect _bundle_literal_expr_170.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_169.unit_num, _bundle_literal_expr_170 - connect _bundle_literal_expr_169.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_45: Ty57 - connect _cast_bundle_to_bits_expr_45.unit_num, _bundle_literal_expr_169.unit_num.adj_value - connect _cast_bundle_to_bits_expr_45.unit_out_reg, _bundle_literal_expr_169.unit_out_reg.value - wire _cast_to_bits_expr_53: UInt<6> - connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num) - when eq(_cast_to_bits_expr_53, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_171: Ty25 - wire _bundle_literal_expr_172: Ty23 - connect _bundle_literal_expr_172.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_171.unit_num, _bundle_literal_expr_172 - connect _bundle_literal_expr_171.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_46: Ty57 - connect _cast_bundle_to_bits_expr_46.unit_num, _bundle_literal_expr_171.unit_num.adj_value - connect _cast_bundle_to_bits_expr_46.unit_out_reg, _bundle_literal_expr_171.unit_out_reg.value - wire _cast_to_bits_expr_54: UInt<6> - connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num) - when eq(_cast_to_bits_expr_54, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_173: Ty25 - wire _bundle_literal_expr_174: Ty23 - connect _bundle_literal_expr_174.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_173.unit_num, _bundle_literal_expr_174 - connect _bundle_literal_expr_173.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_47: Ty57 - connect _cast_bundle_to_bits_expr_47.unit_num, _bundle_literal_expr_173.unit_num.adj_value - connect _cast_bundle_to_bits_expr_47.unit_out_reg, _bundle_literal_expr_173.unit_out_reg.value - wire _cast_to_bits_expr_55: UInt<6> - connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num) - when eq(_cast_to_bits_expr_55, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_114): - wire _bundle_literal_expr_175: Ty25 - wire _bundle_literal_expr_176: Ty23 - connect _bundle_literal_expr_176.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_175.unit_num, _bundle_literal_expr_176 - connect _bundle_literal_expr_175.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_48: Ty57 - connect _cast_bundle_to_bits_expr_48.unit_num, _bundle_literal_expr_175.unit_num.adj_value - connect _cast_bundle_to_bits_expr_48.unit_out_reg, _bundle_literal_expr_175.unit_out_reg.value - wire _cast_to_bits_expr_56: UInt<6> - connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_48.unit_out_reg, _cast_bundle_to_bits_expr_48.unit_num) - when eq(_cast_to_bits_expr_56, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_177: Ty25 - wire _bundle_literal_expr_178: Ty23 - connect _bundle_literal_expr_178.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_177.unit_num, _bundle_literal_expr_178 - connect _bundle_literal_expr_177.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_49: Ty57 - connect _cast_bundle_to_bits_expr_49.unit_num, _bundle_literal_expr_177.unit_num.adj_value - connect _cast_bundle_to_bits_expr_49.unit_out_reg, _bundle_literal_expr_177.unit_out_reg.value - wire _cast_to_bits_expr_57: UInt<6> - connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_49.unit_out_reg, _cast_bundle_to_bits_expr_49.unit_num) - when eq(_cast_to_bits_expr_57, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_179: Ty25 - wire _bundle_literal_expr_180: Ty23 - connect _bundle_literal_expr_180.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_179.unit_num, _bundle_literal_expr_180 - connect _bundle_literal_expr_179.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_50: Ty57 - connect _cast_bundle_to_bits_expr_50.unit_num, _bundle_literal_expr_179.unit_num.adj_value - connect _cast_bundle_to_bits_expr_50.unit_out_reg, _bundle_literal_expr_179.unit_out_reg.value - wire _cast_to_bits_expr_58: UInt<6> - connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num) - when eq(_cast_to_bits_expr_58, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_4: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_181: Ty69 - connect _bundle_literal_expr_181.which, dest_reg_9 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_181): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_4, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_115): - connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_116): - wire _bundle_literal_expr_182: Ty69 - connect _bundle_literal_expr_182.which, dest_reg_9 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_182): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_117): - connect cmp_eq_4, eq(_match_arm_value_116.which.value, _match_arm_value_117.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[4], cmp_eq_4 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_118): - when eq(dest_reg_9.value, _match_arm_value_118.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[4], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_5: Ty81 @[ready_valid.rs 30:27] - connect firing_data_5, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_5, execute_start.data @[ready_valid.rs 34:13] - match firing_data_5: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_119): - wire dest_reg_10: Ty24 @[instruction.rs 538:1] - match _match_arm_value_119.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_120): - connect dest_reg_10, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_121): - connect dest_reg_10, _match_arm_value_121.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_122): - connect dest_reg_10, _match_arm_value_122.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_9.value, dest_reg_10.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[4], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_106.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[4]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_123): - wire _bundle_literal_expr_183: Ty87 - connect _bundle_literal_expr_183.state, _match_arm_value_123 - connect _bundle_literal_expr_183.mop, _match_arm_value_106.mop - connect _bundle_literal_expr_183.src_ready_flags, _match_arm_value_106.src_ready_flags - connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_183) @[unit_base.rs 435:17] - wire _array_literal_expr_44: UInt<1>[3] - connect _array_literal_expr_44[0], UInt<1>(0h0) - connect _array_literal_expr_44[1], UInt<1>(0h0) - connect _array_literal_expr_44[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[5], _array_literal_expr_44 @[unit_base.rs 335:9] - connect in_flight_op_canceling[5], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[5], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[5], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[5]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_124): - wire dest_reg_11: Ty24 @[instruction.rs 538:1] - match _match_arm_value_124.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_125): - connect dest_reg_11, _match_arm_value_125.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_126): - connect dest_reg_11, _match_arm_value_126.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_127): - connect dest_reg_11, _match_arm_value_127.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_5: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_45: UInt<6>[3] - wire _bundle_literal_expr_184: Ty25 - wire _bundle_literal_expr_185: Ty23 - connect _bundle_literal_expr_185.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_184.unit_num, _bundle_literal_expr_185 - wire _bundle_literal_expr_186: Ty24 - connect _bundle_literal_expr_186.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_184.unit_out_reg, _bundle_literal_expr_186 - wire _cast_bundle_to_bits_expr_51: Ty57 - connect _cast_bundle_to_bits_expr_51.unit_num, _bundle_literal_expr_184.unit_num.adj_value - connect _cast_bundle_to_bits_expr_51.unit_out_reg, _bundle_literal_expr_184.unit_out_reg.value - wire _cast_to_bits_expr_59: UInt<6> - connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num) - connect _array_literal_expr_45[0], _cast_to_bits_expr_59 - wire _bundle_literal_expr_187: Ty25 - wire _bundle_literal_expr_188: Ty23 - connect _bundle_literal_expr_188.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_187.unit_num, _bundle_literal_expr_188 - wire _bundle_literal_expr_189: Ty24 - connect _bundle_literal_expr_189.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_187.unit_out_reg, _bundle_literal_expr_189 - wire _cast_bundle_to_bits_expr_52: Ty57 - connect _cast_bundle_to_bits_expr_52.unit_num, _bundle_literal_expr_187.unit_num.adj_value - connect _cast_bundle_to_bits_expr_52.unit_out_reg, _bundle_literal_expr_187.unit_out_reg.value - wire _cast_to_bits_expr_60: UInt<6> - connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num) - connect _array_literal_expr_45[1], _cast_to_bits_expr_60 - wire _bundle_literal_expr_190: Ty25 - wire _bundle_literal_expr_191: Ty23 - connect _bundle_literal_expr_191.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_190.unit_num, _bundle_literal_expr_191 - wire _bundle_literal_expr_192: Ty24 - connect _bundle_literal_expr_192.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_190.unit_out_reg, _bundle_literal_expr_192 - wire _cast_bundle_to_bits_expr_53: Ty57 - connect _cast_bundle_to_bits_expr_53.unit_num, _bundle_literal_expr_190.unit_num.adj_value - connect _cast_bundle_to_bits_expr_53.unit_out_reg, _bundle_literal_expr_190.unit_out_reg.value - wire _cast_to_bits_expr_61: UInt<6> - connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num) - connect _array_literal_expr_45[2], _cast_to_bits_expr_61 - connect in_flight_op_src_regs_5, _array_literal_expr_45 @[unit_base.rs 356:13] - match _match_arm_value_124.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_128): - connect in_flight_op_src_regs_5[0], _match_arm_value_128.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_128.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[2], _match_arm_value_128.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_129): - connect in_flight_op_src_regs_5[0], _match_arm_value_129.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_129.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_130): - connect in_flight_op_src_regs_5[0], _match_arm_value_130.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_130.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[5], _match_arm_value_124.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_131): - wire _bundle_literal_expr_193: Ty25 - wire _bundle_literal_expr_194: Ty23 - connect _bundle_literal_expr_194.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_193.unit_num, _bundle_literal_expr_194 - connect _bundle_literal_expr_193.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_54: Ty57 - connect _cast_bundle_to_bits_expr_54.unit_num, _bundle_literal_expr_193.unit_num.adj_value - connect _cast_bundle_to_bits_expr_54.unit_out_reg, _bundle_literal_expr_193.unit_out_reg.value - wire _cast_to_bits_expr_62: UInt<6> - connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_54.unit_out_reg, _cast_bundle_to_bits_expr_54.unit_num) - when eq(_cast_to_bits_expr_62, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_195: Ty25 - wire _bundle_literal_expr_196: Ty23 - connect _bundle_literal_expr_196.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_195.unit_num, _bundle_literal_expr_196 - connect _bundle_literal_expr_195.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_55: Ty57 - connect _cast_bundle_to_bits_expr_55.unit_num, _bundle_literal_expr_195.unit_num.adj_value - connect _cast_bundle_to_bits_expr_55.unit_out_reg, _bundle_literal_expr_195.unit_out_reg.value - wire _cast_to_bits_expr_63: UInt<6> - connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_55.unit_out_reg, _cast_bundle_to_bits_expr_55.unit_num) - when eq(_cast_to_bits_expr_63, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_197: Ty25 - wire _bundle_literal_expr_198: Ty23 - connect _bundle_literal_expr_198.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_197.unit_num, _bundle_literal_expr_198 - connect _bundle_literal_expr_197.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_56: Ty57 - connect _cast_bundle_to_bits_expr_56.unit_num, _bundle_literal_expr_197.unit_num.adj_value - connect _cast_bundle_to_bits_expr_56.unit_out_reg, _bundle_literal_expr_197.unit_out_reg.value - wire _cast_to_bits_expr_64: UInt<6> - connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_56.unit_out_reg, _cast_bundle_to_bits_expr_56.unit_num) - when eq(_cast_to_bits_expr_64, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_132): - wire _bundle_literal_expr_199: Ty25 - wire _bundle_literal_expr_200: Ty23 - connect _bundle_literal_expr_200.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_199.unit_num, _bundle_literal_expr_200 - connect _bundle_literal_expr_199.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_57: Ty57 - connect _cast_bundle_to_bits_expr_57.unit_num, _bundle_literal_expr_199.unit_num.adj_value - connect _cast_bundle_to_bits_expr_57.unit_out_reg, _bundle_literal_expr_199.unit_out_reg.value - wire _cast_to_bits_expr_65: UInt<6> - connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num) - when eq(_cast_to_bits_expr_65, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_201: Ty25 - wire _bundle_literal_expr_202: Ty23 - connect _bundle_literal_expr_202.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_201.unit_num, _bundle_literal_expr_202 - connect _bundle_literal_expr_201.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_58: Ty57 - connect _cast_bundle_to_bits_expr_58.unit_num, _bundle_literal_expr_201.unit_num.adj_value - connect _cast_bundle_to_bits_expr_58.unit_out_reg, _bundle_literal_expr_201.unit_out_reg.value - wire _cast_to_bits_expr_66: UInt<6> - connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num) - when eq(_cast_to_bits_expr_66, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_203: Ty25 - wire _bundle_literal_expr_204: Ty23 - connect _bundle_literal_expr_204.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_203.unit_num, _bundle_literal_expr_204 - connect _bundle_literal_expr_203.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_59: Ty57 - connect _cast_bundle_to_bits_expr_59.unit_num, _bundle_literal_expr_203.unit_num.adj_value - connect _cast_bundle_to_bits_expr_59.unit_out_reg, _bundle_literal_expr_203.unit_out_reg.value - wire _cast_to_bits_expr_67: UInt<6> - connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num) - when eq(_cast_to_bits_expr_67, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_5: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_205: Ty69 - connect _bundle_literal_expr_205.which, dest_reg_11 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_205): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_5, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_133): - connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_134): - wire _bundle_literal_expr_206: Ty69 - connect _bundle_literal_expr_206.which, dest_reg_11 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_206): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_135): - connect cmp_eq_5, eq(_match_arm_value_134.which.value, _match_arm_value_135.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[5], cmp_eq_5 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_136): - when eq(dest_reg_11.value, _match_arm_value_136.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[5], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_6: Ty81 @[ready_valid.rs 30:27] - connect firing_data_6, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_6, execute_start.data @[ready_valid.rs 34:13] - match firing_data_6: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_137): - wire dest_reg_12: Ty24 @[instruction.rs 538:1] - match _match_arm_value_137.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_138): - connect dest_reg_12, _match_arm_value_138.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_139): - connect dest_reg_12, _match_arm_value_139.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_140): - connect dest_reg_12, _match_arm_value_140.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_11.value, dest_reg_12.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[5], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_124.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[5]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_141): - wire _bundle_literal_expr_207: Ty87 - connect _bundle_literal_expr_207.state, _match_arm_value_141 - connect _bundle_literal_expr_207.mop, _match_arm_value_124.mop - connect _bundle_literal_expr_207.src_ready_flags, _match_arm_value_124.src_ready_flags - connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_207) @[unit_base.rs 435:17] - wire _array_literal_expr_46: UInt<1>[3] - connect _array_literal_expr_46[0], UInt<1>(0h0) - connect _array_literal_expr_46[1], UInt<1>(0h0) - connect _array_literal_expr_46[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[6], _array_literal_expr_46 @[unit_base.rs 335:9] - connect in_flight_op_canceling[6], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[6], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[6], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[6]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_142): - wire dest_reg_13: Ty24 @[instruction.rs 538:1] - match _match_arm_value_142.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_143): - connect dest_reg_13, _match_arm_value_143.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_144): - connect dest_reg_13, _match_arm_value_144.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_145): - connect dest_reg_13, _match_arm_value_145.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_6: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_47: UInt<6>[3] - wire _bundle_literal_expr_208: Ty25 - wire _bundle_literal_expr_209: Ty23 - connect _bundle_literal_expr_209.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_208.unit_num, _bundle_literal_expr_209 - wire _bundle_literal_expr_210: Ty24 - connect _bundle_literal_expr_210.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_208.unit_out_reg, _bundle_literal_expr_210 - wire _cast_bundle_to_bits_expr_60: Ty57 - connect _cast_bundle_to_bits_expr_60.unit_num, _bundle_literal_expr_208.unit_num.adj_value - connect _cast_bundle_to_bits_expr_60.unit_out_reg, _bundle_literal_expr_208.unit_out_reg.value - wire _cast_to_bits_expr_68: UInt<6> - connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num) - connect _array_literal_expr_47[0], _cast_to_bits_expr_68 - wire _bundle_literal_expr_211: Ty25 - wire _bundle_literal_expr_212: Ty23 - connect _bundle_literal_expr_212.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_211.unit_num, _bundle_literal_expr_212 - wire _bundle_literal_expr_213: Ty24 - connect _bundle_literal_expr_213.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_211.unit_out_reg, _bundle_literal_expr_213 - wire _cast_bundle_to_bits_expr_61: Ty57 - connect _cast_bundle_to_bits_expr_61.unit_num, _bundle_literal_expr_211.unit_num.adj_value - connect _cast_bundle_to_bits_expr_61.unit_out_reg, _bundle_literal_expr_211.unit_out_reg.value - wire _cast_to_bits_expr_69: UInt<6> - connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_61.unit_out_reg, _cast_bundle_to_bits_expr_61.unit_num) - connect _array_literal_expr_47[1], _cast_to_bits_expr_69 - wire _bundle_literal_expr_214: Ty25 - wire _bundle_literal_expr_215: Ty23 - connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215 - wire _bundle_literal_expr_216: Ty24 - connect _bundle_literal_expr_216.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216 - wire _cast_bundle_to_bits_expr_62: Ty57 - connect _cast_bundle_to_bits_expr_62.unit_num, _bundle_literal_expr_214.unit_num.adj_value - connect _cast_bundle_to_bits_expr_62.unit_out_reg, _bundle_literal_expr_214.unit_out_reg.value - wire _cast_to_bits_expr_70: UInt<6> - connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_62.unit_out_reg, _cast_bundle_to_bits_expr_62.unit_num) - connect _array_literal_expr_47[2], _cast_to_bits_expr_70 - connect in_flight_op_src_regs_6, _array_literal_expr_47 @[unit_base.rs 356:13] - match _match_arm_value_142.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_146): - connect in_flight_op_src_regs_6[0], _match_arm_value_146.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_146.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[2], _match_arm_value_146.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_147): - connect in_flight_op_src_regs_6[0], _match_arm_value_147.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_147.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_148): - connect in_flight_op_src_regs_6[0], _match_arm_value_148.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_148.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[6], _match_arm_value_142.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_149): - wire _bundle_literal_expr_217: Ty25 - wire _bundle_literal_expr_218: Ty23 - connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218 - connect _bundle_literal_expr_217.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_63: Ty57 - connect _cast_bundle_to_bits_expr_63.unit_num, _bundle_literal_expr_217.unit_num.adj_value - connect _cast_bundle_to_bits_expr_63.unit_out_reg, _bundle_literal_expr_217.unit_out_reg.value - wire _cast_to_bits_expr_71: UInt<6> - connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_63.unit_out_reg, _cast_bundle_to_bits_expr_63.unit_num) - when eq(_cast_to_bits_expr_71, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_219: Ty25 - wire _bundle_literal_expr_220: Ty23 - connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220 - connect _bundle_literal_expr_219.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_64: Ty57 - connect _cast_bundle_to_bits_expr_64.unit_num, _bundle_literal_expr_219.unit_num.adj_value - connect _cast_bundle_to_bits_expr_64.unit_out_reg, _bundle_literal_expr_219.unit_out_reg.value - wire _cast_to_bits_expr_72: UInt<6> - connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_64.unit_out_reg, _cast_bundle_to_bits_expr_64.unit_num) - when eq(_cast_to_bits_expr_72, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_221: Ty25 - wire _bundle_literal_expr_222: Ty23 - connect _bundle_literal_expr_222.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_221.unit_num, _bundle_literal_expr_222 - connect _bundle_literal_expr_221.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_65: Ty57 - connect _cast_bundle_to_bits_expr_65.unit_num, _bundle_literal_expr_221.unit_num.adj_value - connect _cast_bundle_to_bits_expr_65.unit_out_reg, _bundle_literal_expr_221.unit_out_reg.value - wire _cast_to_bits_expr_73: UInt<6> - connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_65.unit_out_reg, _cast_bundle_to_bits_expr_65.unit_num) - when eq(_cast_to_bits_expr_73, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_150): - wire _bundle_literal_expr_223: Ty25 - wire _bundle_literal_expr_224: Ty23 - connect _bundle_literal_expr_224.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_223.unit_num, _bundle_literal_expr_224 - connect _bundle_literal_expr_223.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_66: Ty57 - connect _cast_bundle_to_bits_expr_66.unit_num, _bundle_literal_expr_223.unit_num.adj_value - connect _cast_bundle_to_bits_expr_66.unit_out_reg, _bundle_literal_expr_223.unit_out_reg.value - wire _cast_to_bits_expr_74: UInt<6> - connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_66.unit_out_reg, _cast_bundle_to_bits_expr_66.unit_num) - when eq(_cast_to_bits_expr_74, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_225: Ty25 - wire _bundle_literal_expr_226: Ty23 - connect _bundle_literal_expr_226.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_225.unit_num, _bundle_literal_expr_226 - connect _bundle_literal_expr_225.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_67: Ty57 - connect _cast_bundle_to_bits_expr_67.unit_num, _bundle_literal_expr_225.unit_num.adj_value - connect _cast_bundle_to_bits_expr_67.unit_out_reg, _bundle_literal_expr_225.unit_out_reg.value - wire _cast_to_bits_expr_75: UInt<6> - connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num) - when eq(_cast_to_bits_expr_75, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_227: Ty25 - wire _bundle_literal_expr_228: Ty23 - connect _bundle_literal_expr_228.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_227.unit_num, _bundle_literal_expr_228 - connect _bundle_literal_expr_227.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_68: Ty57 - connect _cast_bundle_to_bits_expr_68.unit_num, _bundle_literal_expr_227.unit_num.adj_value - connect _cast_bundle_to_bits_expr_68.unit_out_reg, _bundle_literal_expr_227.unit_out_reg.value - wire _cast_to_bits_expr_76: UInt<6> - connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_68.unit_out_reg, _cast_bundle_to_bits_expr_68.unit_num) - when eq(_cast_to_bits_expr_76, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_6: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_229: Ty69 - connect _bundle_literal_expr_229.which, dest_reg_13 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_229): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_6, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_151): - connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_152): - wire _bundle_literal_expr_230: Ty69 - connect _bundle_literal_expr_230.which, dest_reg_13 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_230): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_153): - connect cmp_eq_6, eq(_match_arm_value_152.which.value, _match_arm_value_153.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[6], cmp_eq_6 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_154): - when eq(dest_reg_13.value, _match_arm_value_154.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[6], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_7: Ty81 @[ready_valid.rs 30:27] - connect firing_data_7, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_7, execute_start.data @[ready_valid.rs 34:13] - match firing_data_7: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_155): - wire dest_reg_14: Ty24 @[instruction.rs 538:1] - match _match_arm_value_155.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_156): - connect dest_reg_14, _match_arm_value_156.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_157): - connect dest_reg_14, _match_arm_value_157.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_158): - connect dest_reg_14, _match_arm_value_158.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_13.value, dest_reg_14.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[6], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_142.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[6]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_159): - wire _bundle_literal_expr_231: Ty87 - connect _bundle_literal_expr_231.state, _match_arm_value_159 - connect _bundle_literal_expr_231.mop, _match_arm_value_142.mop - connect _bundle_literal_expr_231.src_ready_flags, _match_arm_value_142.src_ready_flags - connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_231) @[unit_base.rs 435:17] - wire _array_literal_expr_48: UInt<1>[3] - connect _array_literal_expr_48[0], UInt<1>(0h0) - connect _array_literal_expr_48[1], UInt<1>(0h0) - connect _array_literal_expr_48[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[7], _array_literal_expr_48 @[unit_base.rs 335:9] - connect in_flight_op_canceling[7], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[7], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[7], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[7]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_160): - wire dest_reg_15: Ty24 @[instruction.rs 538:1] - match _match_arm_value_160.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_161): - connect dest_reg_15, _match_arm_value_161.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_162): - connect dest_reg_15, _match_arm_value_162.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_163): - connect dest_reg_15, _match_arm_value_163.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_7: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_49: UInt<6>[3] - wire _bundle_literal_expr_232: Ty25 - wire _bundle_literal_expr_233: Ty23 - connect _bundle_literal_expr_233.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_232.unit_num, _bundle_literal_expr_233 - wire _bundle_literal_expr_234: Ty24 - connect _bundle_literal_expr_234.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_232.unit_out_reg, _bundle_literal_expr_234 - wire _cast_bundle_to_bits_expr_69: Ty57 - connect _cast_bundle_to_bits_expr_69.unit_num, _bundle_literal_expr_232.unit_num.adj_value - connect _cast_bundle_to_bits_expr_69.unit_out_reg, _bundle_literal_expr_232.unit_out_reg.value - wire _cast_to_bits_expr_77: UInt<6> - connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_69.unit_out_reg, _cast_bundle_to_bits_expr_69.unit_num) - connect _array_literal_expr_49[0], _cast_to_bits_expr_77 - wire _bundle_literal_expr_235: Ty25 - wire _bundle_literal_expr_236: Ty23 - connect _bundle_literal_expr_236.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_235.unit_num, _bundle_literal_expr_236 - wire _bundle_literal_expr_237: Ty24 - connect _bundle_literal_expr_237.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_235.unit_out_reg, _bundle_literal_expr_237 - wire _cast_bundle_to_bits_expr_70: Ty57 - connect _cast_bundle_to_bits_expr_70.unit_num, _bundle_literal_expr_235.unit_num.adj_value - connect _cast_bundle_to_bits_expr_70.unit_out_reg, _bundle_literal_expr_235.unit_out_reg.value - wire _cast_to_bits_expr_78: UInt<6> - connect _cast_to_bits_expr_78, cat(_cast_bundle_to_bits_expr_70.unit_out_reg, _cast_bundle_to_bits_expr_70.unit_num) - connect _array_literal_expr_49[1], _cast_to_bits_expr_78 - wire _bundle_literal_expr_238: Ty25 - wire _bundle_literal_expr_239: Ty23 - connect _bundle_literal_expr_239.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_238.unit_num, _bundle_literal_expr_239 - wire _bundle_literal_expr_240: Ty24 - connect _bundle_literal_expr_240.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_238.unit_out_reg, _bundle_literal_expr_240 - wire _cast_bundle_to_bits_expr_71: Ty57 - connect _cast_bundle_to_bits_expr_71.unit_num, _bundle_literal_expr_238.unit_num.adj_value - connect _cast_bundle_to_bits_expr_71.unit_out_reg, _bundle_literal_expr_238.unit_out_reg.value - wire _cast_to_bits_expr_79: UInt<6> - connect _cast_to_bits_expr_79, cat(_cast_bundle_to_bits_expr_71.unit_out_reg, _cast_bundle_to_bits_expr_71.unit_num) - connect _array_literal_expr_49[2], _cast_to_bits_expr_79 - connect in_flight_op_src_regs_7, _array_literal_expr_49 @[unit_base.rs 356:13] - match _match_arm_value_160.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_164): - connect in_flight_op_src_regs_7[0], _match_arm_value_164.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_164.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[2], _match_arm_value_164.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_165): - connect in_flight_op_src_regs_7[0], _match_arm_value_165.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_165.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_166): - connect in_flight_op_src_regs_7[0], _match_arm_value_166.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_166.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[7], _match_arm_value_160.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_167): - wire _bundle_literal_expr_241: Ty25 - wire _bundle_literal_expr_242: Ty23 - connect _bundle_literal_expr_242.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_241.unit_num, _bundle_literal_expr_242 - connect _bundle_literal_expr_241.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_72: Ty57 - connect _cast_bundle_to_bits_expr_72.unit_num, _bundle_literal_expr_241.unit_num.adj_value - connect _cast_bundle_to_bits_expr_72.unit_out_reg, _bundle_literal_expr_241.unit_out_reg.value - wire _cast_to_bits_expr_80: UInt<6> - connect _cast_to_bits_expr_80, cat(_cast_bundle_to_bits_expr_72.unit_out_reg, _cast_bundle_to_bits_expr_72.unit_num) - when eq(_cast_to_bits_expr_80, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_243: Ty25 - wire _bundle_literal_expr_244: Ty23 - connect _bundle_literal_expr_244.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_243.unit_num, _bundle_literal_expr_244 - connect _bundle_literal_expr_243.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_73: Ty57 - connect _cast_bundle_to_bits_expr_73.unit_num, _bundle_literal_expr_243.unit_num.adj_value - connect _cast_bundle_to_bits_expr_73.unit_out_reg, _bundle_literal_expr_243.unit_out_reg.value - wire _cast_to_bits_expr_81: UInt<6> - connect _cast_to_bits_expr_81, cat(_cast_bundle_to_bits_expr_73.unit_out_reg, _cast_bundle_to_bits_expr_73.unit_num) - when eq(_cast_to_bits_expr_81, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_245: Ty25 - wire _bundle_literal_expr_246: Ty23 - connect _bundle_literal_expr_246.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_245.unit_num, _bundle_literal_expr_246 - connect _bundle_literal_expr_245.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_74: Ty57 - connect _cast_bundle_to_bits_expr_74.unit_num, _bundle_literal_expr_245.unit_num.adj_value - connect _cast_bundle_to_bits_expr_74.unit_out_reg, _bundle_literal_expr_245.unit_out_reg.value - wire _cast_to_bits_expr_82: UInt<6> - connect _cast_to_bits_expr_82, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num) - when eq(_cast_to_bits_expr_82, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_168): - wire _bundle_literal_expr_247: Ty25 - wire _bundle_literal_expr_248: Ty23 - connect _bundle_literal_expr_248.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_247.unit_num, _bundle_literal_expr_248 - connect _bundle_literal_expr_247.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_75: Ty57 - connect _cast_bundle_to_bits_expr_75.unit_num, _bundle_literal_expr_247.unit_num.adj_value - connect _cast_bundle_to_bits_expr_75.unit_out_reg, _bundle_literal_expr_247.unit_out_reg.value - wire _cast_to_bits_expr_83: UInt<6> - connect _cast_to_bits_expr_83, cat(_cast_bundle_to_bits_expr_75.unit_out_reg, _cast_bundle_to_bits_expr_75.unit_num) - when eq(_cast_to_bits_expr_83, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_249: Ty25 - wire _bundle_literal_expr_250: Ty23 - connect _bundle_literal_expr_250.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_249.unit_num, _bundle_literal_expr_250 - connect _bundle_literal_expr_249.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_76: Ty57 - connect _cast_bundle_to_bits_expr_76.unit_num, _bundle_literal_expr_249.unit_num.adj_value - connect _cast_bundle_to_bits_expr_76.unit_out_reg, _bundle_literal_expr_249.unit_out_reg.value - wire _cast_to_bits_expr_84: UInt<6> - connect _cast_to_bits_expr_84, cat(_cast_bundle_to_bits_expr_76.unit_out_reg, _cast_bundle_to_bits_expr_76.unit_num) - when eq(_cast_to_bits_expr_84, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_251: Ty25 - wire _bundle_literal_expr_252: Ty23 - connect _bundle_literal_expr_252.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_251.unit_num, _bundle_literal_expr_252 - connect _bundle_literal_expr_251.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_77: Ty57 - connect _cast_bundle_to_bits_expr_77.unit_num, _bundle_literal_expr_251.unit_num.adj_value - connect _cast_bundle_to_bits_expr_77.unit_out_reg, _bundle_literal_expr_251.unit_out_reg.value - wire _cast_to_bits_expr_85: UInt<6> - connect _cast_to_bits_expr_85, cat(_cast_bundle_to_bits_expr_77.unit_out_reg, _cast_bundle_to_bits_expr_77.unit_num) - when eq(_cast_to_bits_expr_85, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_7: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_253: Ty69 - connect _bundle_literal_expr_253.which, dest_reg_15 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_253): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_7, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_169): - connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_170): - wire _bundle_literal_expr_254: Ty69 - connect _bundle_literal_expr_254.which, dest_reg_15 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_254): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_171): - connect cmp_eq_7, eq(_match_arm_value_170.which.value, _match_arm_value_171.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[7], cmp_eq_7 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_172): - when eq(dest_reg_15.value, _match_arm_value_172.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[7], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_8: Ty81 @[ready_valid.rs 30:27] - connect firing_data_8, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_8, execute_start.data @[ready_valid.rs 34:13] - match firing_data_8: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_173): - wire dest_reg_16: Ty24 @[instruction.rs 538:1] - match _match_arm_value_173.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_174): - connect dest_reg_16, _match_arm_value_174.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_175): - connect dest_reg_16, _match_arm_value_175.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_176): - connect dest_reg_16, _match_arm_value_176.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_15.value, dest_reg_16.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[7], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_160.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[7]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_177): - wire _bundle_literal_expr_255: Ty87 - connect _bundle_literal_expr_255.state, _match_arm_value_177 - connect _bundle_literal_expr_255.mop, _match_arm_value_160.mop - connect _bundle_literal_expr_255.src_ready_flags, _match_arm_value_160.src_ready_flags - connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_255) @[unit_base.rs 435:17] - module unit_base_1: @[unit_base.rs 225:1] - input cd: Ty0 @[unit_base.rs 236:29] - output unit_to_reg_alloc: Ty75 @[unit_base.rs 239:11] - output execute_start: Ty82 @[unit_base.rs 241:58] - input execute_end: Ty84 @[unit_base.rs 244:11] - connect execute_start.data, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[unit_base.rs 246:5] - wire _array_literal_expr: Ty88[8] - connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) - connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) - regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 251:25] - wire empty_op_index_0: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_0: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[0]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value): - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_1: UInt<1>[3] - wire _array_literal_expr_2: UInt<1>[3] - connect _array_literal_expr_2[0], UInt<1>(0h1) - connect _array_literal_expr_2[1], UInt<1>(0h1) - connect _array_literal_expr_2[2], UInt<1>(0h1) - connect _array_literal_expr_1[0], eq(_match_arm_value.src_ready_flags[0], _array_literal_expr_2[0]) - wire _array_literal_expr_3: UInt<1>[3] - connect _array_literal_expr_3[0], UInt<1>(0h1) - connect _array_literal_expr_3[1], UInt<1>(0h1) - connect _array_literal_expr_3[2], UInt<1>(0h1) - connect _array_literal_expr_1[1], eq(_match_arm_value.src_ready_flags[1], _array_literal_expr_3[1]) - wire _array_literal_expr_4: UInt<1>[3] - connect _array_literal_expr_4[0], UInt<1>(0h1) - connect _array_literal_expr_4[1], UInt<1>(0h1) - connect _array_literal_expr_4[2], UInt<1>(0h1) - connect _array_literal_expr_1[2], eq(_match_arm_value.src_ready_flags[2], _array_literal_expr_4[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr_1[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr_1[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr_1[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - when andr(_cast_to_bits_expr): @[unit_base.rs 182:21] - connect ready_op_index_0, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_1: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_1: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[1]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_1): - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_1.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_5: UInt<1>[3] - wire _array_literal_expr_6: UInt<1>[3] - connect _array_literal_expr_6[0], UInt<1>(0h1) - connect _array_literal_expr_6[1], UInt<1>(0h1) - connect _array_literal_expr_6[2], UInt<1>(0h1) - connect _array_literal_expr_5[0], eq(_match_arm_value_1.src_ready_flags[0], _array_literal_expr_6[0]) - wire _array_literal_expr_7: UInt<1>[3] - connect _array_literal_expr_7[0], UInt<1>(0h1) - connect _array_literal_expr_7[1], UInt<1>(0h1) - connect _array_literal_expr_7[2], UInt<1>(0h1) - connect _array_literal_expr_5[1], eq(_match_arm_value_1.src_ready_flags[1], _array_literal_expr_7[1]) - wire _array_literal_expr_8: UInt<1>[3] - connect _array_literal_expr_8[0], UInt<1>(0h1) - connect _array_literal_expr_8[1], UInt<1>(0h1) - connect _array_literal_expr_8[2], UInt<1>(0h1) - connect _array_literal_expr_5[2], eq(_match_arm_value_1.src_ready_flags[2], _array_literal_expr_8[2]) - wire _cast_array_to_bits_expr_1: UInt<1>[3] - connect _cast_array_to_bits_expr_1[0], _array_literal_expr_5[0] - connect _cast_array_to_bits_expr_1[1], _array_literal_expr_5[1] - connect _cast_array_to_bits_expr_1[2], _array_literal_expr_5[2] - wire _cast_to_bits_expr_1: UInt<3> - connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0])) - when andr(_cast_to_bits_expr_1): @[unit_base.rs 182:21] - connect ready_op_index_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr: Ty90 - connect _bundle_literal_expr.empty_op_index, empty_op_index_1 - connect _bundle_literal_expr.ready_op_index, ready_op_index_1 - connect or_out, _bundle_literal_expr.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_1: Ty90 - connect _bundle_literal_expr_1.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_1.ready_op_index, ready_op_index_0 - match _bundle_literal_expr_1.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_2): - wire _bundle_literal_expr_2: Ty90 - connect _bundle_literal_expr_2.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_2.ready_op_index, ready_op_index_0 - connect or_out, _bundle_literal_expr_2.empty_op_index @[unit_base.rs 203:29] - wire or_out_1: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_3: Ty90 - connect _bundle_literal_expr_3.empty_op_index, empty_op_index_1 - connect _bundle_literal_expr_3.ready_op_index, ready_op_index_1 - connect or_out_1, _bundle_literal_expr_3.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_4: Ty90 - connect _bundle_literal_expr_4.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_4.ready_op_index, ready_op_index_0 - match _bundle_literal_expr_4.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_3): - wire _bundle_literal_expr_5: Ty90 - connect _bundle_literal_expr_5.empty_op_index, empty_op_index_0 - connect _bundle_literal_expr_5.ready_op_index, ready_op_index_0 - connect or_out_1, _bundle_literal_expr_5.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_2: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_2: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[2]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_4): - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_4.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_9: UInt<1>[3] - wire _array_literal_expr_10: UInt<1>[3] - connect _array_literal_expr_10[0], UInt<1>(0h1) - connect _array_literal_expr_10[1], UInt<1>(0h1) - connect _array_literal_expr_10[2], UInt<1>(0h1) - connect _array_literal_expr_9[0], eq(_match_arm_value_4.src_ready_flags[0], _array_literal_expr_10[0]) - wire _array_literal_expr_11: UInt<1>[3] - connect _array_literal_expr_11[0], UInt<1>(0h1) - connect _array_literal_expr_11[1], UInt<1>(0h1) - connect _array_literal_expr_11[2], UInt<1>(0h1) - connect _array_literal_expr_9[1], eq(_match_arm_value_4.src_ready_flags[1], _array_literal_expr_11[1]) - wire _array_literal_expr_12: UInt<1>[3] - connect _array_literal_expr_12[0], UInt<1>(0h1) - connect _array_literal_expr_12[1], UInt<1>(0h1) - connect _array_literal_expr_12[2], UInt<1>(0h1) - connect _array_literal_expr_9[2], eq(_match_arm_value_4.src_ready_flags[2], _array_literal_expr_12[2]) - wire _cast_array_to_bits_expr_2: UInt<1>[3] - connect _cast_array_to_bits_expr_2[0], _array_literal_expr_9[0] - connect _cast_array_to_bits_expr_2[1], _array_literal_expr_9[1] - connect _cast_array_to_bits_expr_2[2], _array_literal_expr_9[2] - wire _cast_to_bits_expr_2: UInt<3> - connect _cast_to_bits_expr_2, cat(_cast_array_to_bits_expr_2[2], cat(_cast_array_to_bits_expr_2[1], _cast_array_to_bits_expr_2[0])) - when andr(_cast_to_bits_expr_2): @[unit_base.rs 182:21] - connect ready_op_index_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_3: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_3: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[3]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_5): - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_5.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_13: UInt<1>[3] - wire _array_literal_expr_14: UInt<1>[3] - connect _array_literal_expr_14[0], UInt<1>(0h1) - connect _array_literal_expr_14[1], UInt<1>(0h1) - connect _array_literal_expr_14[2], UInt<1>(0h1) - connect _array_literal_expr_13[0], eq(_match_arm_value_5.src_ready_flags[0], _array_literal_expr_14[0]) - wire _array_literal_expr_15: UInt<1>[3] - connect _array_literal_expr_15[0], UInt<1>(0h1) - connect _array_literal_expr_15[1], UInt<1>(0h1) - connect _array_literal_expr_15[2], UInt<1>(0h1) - connect _array_literal_expr_13[1], eq(_match_arm_value_5.src_ready_flags[1], _array_literal_expr_15[1]) - wire _array_literal_expr_16: UInt<1>[3] - connect _array_literal_expr_16[0], UInt<1>(0h1) - connect _array_literal_expr_16[1], UInt<1>(0h1) - connect _array_literal_expr_16[2], UInt<1>(0h1) - connect _array_literal_expr_13[2], eq(_match_arm_value_5.src_ready_flags[2], _array_literal_expr_16[2]) - wire _cast_array_to_bits_expr_3: UInt<1>[3] - connect _cast_array_to_bits_expr_3[0], _array_literal_expr_13[0] - connect _cast_array_to_bits_expr_3[1], _array_literal_expr_13[1] - connect _cast_array_to_bits_expr_3[2], _array_literal_expr_13[2] - wire _cast_to_bits_expr_3: UInt<3> - connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr_3[2], cat(_cast_array_to_bits_expr_3[1], _cast_array_to_bits_expr_3[0])) - when andr(_cast_to_bits_expr_3): @[unit_base.rs 182:21] - connect ready_op_index_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_2: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_6: Ty90 - connect _bundle_literal_expr_6.empty_op_index, empty_op_index_3 - connect _bundle_literal_expr_6.ready_op_index, ready_op_index_3 - connect or_out_2, _bundle_literal_expr_6.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_7: Ty90 - connect _bundle_literal_expr_7.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_7.ready_op_index, ready_op_index_2 - match _bundle_literal_expr_7.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_6): - wire _bundle_literal_expr_8: Ty90 - connect _bundle_literal_expr_8.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_8.ready_op_index, ready_op_index_2 - connect or_out_2, _bundle_literal_expr_8.empty_op_index @[unit_base.rs 203:29] - wire or_out_3: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_9: Ty90 - connect _bundle_literal_expr_9.empty_op_index, empty_op_index_3 - connect _bundle_literal_expr_9.ready_op_index, ready_op_index_3 - connect or_out_3, _bundle_literal_expr_9.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_10: Ty90 - connect _bundle_literal_expr_10.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_10.ready_op_index, ready_op_index_2 - match _bundle_literal_expr_10.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_7): - wire _bundle_literal_expr_11: Ty90 - connect _bundle_literal_expr_11.empty_op_index, empty_op_index_2 - connect _bundle_literal_expr_11.ready_op_index, ready_op_index_2 - connect or_out_3, _bundle_literal_expr_11.ready_op_index @[unit_base.rs 204:29] - wire or_out_4: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_12: Ty90 - connect _bundle_literal_expr_12.empty_op_index, or_out_2 - connect _bundle_literal_expr_12.ready_op_index, or_out_3 - connect or_out_4, _bundle_literal_expr_12.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_13: Ty90 - connect _bundle_literal_expr_13.empty_op_index, or_out - connect _bundle_literal_expr_13.ready_op_index, or_out_1 - match _bundle_literal_expr_13.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_8): - wire _bundle_literal_expr_14: Ty90 - connect _bundle_literal_expr_14.empty_op_index, or_out - connect _bundle_literal_expr_14.ready_op_index, or_out_1 - connect or_out_4, _bundle_literal_expr_14.empty_op_index @[unit_base.rs 203:29] - wire or_out_5: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_15: Ty90 - connect _bundle_literal_expr_15.empty_op_index, or_out_2 - connect _bundle_literal_expr_15.ready_op_index, or_out_3 - connect or_out_5, _bundle_literal_expr_15.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_16: Ty90 - connect _bundle_literal_expr_16.empty_op_index, or_out - connect _bundle_literal_expr_16.ready_op_index, or_out_1 - match _bundle_literal_expr_16.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_9): - wire _bundle_literal_expr_17: Ty90 - connect _bundle_literal_expr_17.empty_op_index, or_out - connect _bundle_literal_expr_17.ready_op_index, or_out_1 - connect or_out_5, _bundle_literal_expr_17.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_4: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_4: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[4]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_10): - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_10.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_17: UInt<1>[3] - wire _array_literal_expr_18: UInt<1>[3] - connect _array_literal_expr_18[0], UInt<1>(0h1) - connect _array_literal_expr_18[1], UInt<1>(0h1) - connect _array_literal_expr_18[2], UInt<1>(0h1) - connect _array_literal_expr_17[0], eq(_match_arm_value_10.src_ready_flags[0], _array_literal_expr_18[0]) - wire _array_literal_expr_19: UInt<1>[3] - connect _array_literal_expr_19[0], UInt<1>(0h1) - connect _array_literal_expr_19[1], UInt<1>(0h1) - connect _array_literal_expr_19[2], UInt<1>(0h1) - connect _array_literal_expr_17[1], eq(_match_arm_value_10.src_ready_flags[1], _array_literal_expr_19[1]) - wire _array_literal_expr_20: UInt<1>[3] - connect _array_literal_expr_20[0], UInt<1>(0h1) - connect _array_literal_expr_20[1], UInt<1>(0h1) - connect _array_literal_expr_20[2], UInt<1>(0h1) - connect _array_literal_expr_17[2], eq(_match_arm_value_10.src_ready_flags[2], _array_literal_expr_20[2]) - wire _cast_array_to_bits_expr_4: UInt<1>[3] - connect _cast_array_to_bits_expr_4[0], _array_literal_expr_17[0] - connect _cast_array_to_bits_expr_4[1], _array_literal_expr_17[1] - connect _cast_array_to_bits_expr_4[2], _array_literal_expr_17[2] - wire _cast_to_bits_expr_4: UInt<3> - connect _cast_to_bits_expr_4, cat(_cast_array_to_bits_expr_4[2], cat(_cast_array_to_bits_expr_4[1], _cast_array_to_bits_expr_4[0])) - when andr(_cast_to_bits_expr_4): @[unit_base.rs 182:21] - connect ready_op_index_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_5: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_5: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[5]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_11): - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_11.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_21: UInt<1>[3] - wire _array_literal_expr_22: UInt<1>[3] - connect _array_literal_expr_22[0], UInt<1>(0h1) - connect _array_literal_expr_22[1], UInt<1>(0h1) - connect _array_literal_expr_22[2], UInt<1>(0h1) - connect _array_literal_expr_21[0], eq(_match_arm_value_11.src_ready_flags[0], _array_literal_expr_22[0]) - wire _array_literal_expr_23: UInt<1>[3] - connect _array_literal_expr_23[0], UInt<1>(0h1) - connect _array_literal_expr_23[1], UInt<1>(0h1) - connect _array_literal_expr_23[2], UInt<1>(0h1) - connect _array_literal_expr_21[1], eq(_match_arm_value_11.src_ready_flags[1], _array_literal_expr_23[1]) - wire _array_literal_expr_24: UInt<1>[3] - connect _array_literal_expr_24[0], UInt<1>(0h1) - connect _array_literal_expr_24[1], UInt<1>(0h1) - connect _array_literal_expr_24[2], UInt<1>(0h1) - connect _array_literal_expr_21[2], eq(_match_arm_value_11.src_ready_flags[2], _array_literal_expr_24[2]) - wire _cast_array_to_bits_expr_5: UInt<1>[3] - connect _cast_array_to_bits_expr_5[0], _array_literal_expr_21[0] - connect _cast_array_to_bits_expr_5[1], _array_literal_expr_21[1] - connect _cast_array_to_bits_expr_5[2], _array_literal_expr_21[2] - wire _cast_to_bits_expr_5: UInt<3> - connect _cast_to_bits_expr_5, cat(_cast_array_to_bits_expr_5[2], cat(_cast_array_to_bits_expr_5[1], _cast_array_to_bits_expr_5[0])) - when andr(_cast_to_bits_expr_5): @[unit_base.rs 182:21] - connect ready_op_index_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_6: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_18: Ty90 - connect _bundle_literal_expr_18.empty_op_index, empty_op_index_5 - connect _bundle_literal_expr_18.ready_op_index, ready_op_index_5 - connect or_out_6, _bundle_literal_expr_18.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_19: Ty90 - connect _bundle_literal_expr_19.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_19.ready_op_index, ready_op_index_4 - match _bundle_literal_expr_19.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_12): - wire _bundle_literal_expr_20: Ty90 - connect _bundle_literal_expr_20.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_20.ready_op_index, ready_op_index_4 - connect or_out_6, _bundle_literal_expr_20.empty_op_index @[unit_base.rs 203:29] - wire or_out_7: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_21: Ty90 - connect _bundle_literal_expr_21.empty_op_index, empty_op_index_5 - connect _bundle_literal_expr_21.ready_op_index, ready_op_index_5 - connect or_out_7, _bundle_literal_expr_21.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_22: Ty90 - connect _bundle_literal_expr_22.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_22.ready_op_index, ready_op_index_4 - match _bundle_literal_expr_22.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_13): - wire _bundle_literal_expr_23: Ty90 - connect _bundle_literal_expr_23.empty_op_index, empty_op_index_4 - connect _bundle_literal_expr_23.ready_op_index, ready_op_index_4 - connect or_out_7, _bundle_literal_expr_23.ready_op_index @[unit_base.rs 204:29] - wire empty_op_index_6: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_6: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[6]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_14): - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_14.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_25: UInt<1>[3] - wire _array_literal_expr_26: UInt<1>[3] - connect _array_literal_expr_26[0], UInt<1>(0h1) - connect _array_literal_expr_26[1], UInt<1>(0h1) - connect _array_literal_expr_26[2], UInt<1>(0h1) - connect _array_literal_expr_25[0], eq(_match_arm_value_14.src_ready_flags[0], _array_literal_expr_26[0]) - wire _array_literal_expr_27: UInt<1>[3] - connect _array_literal_expr_27[0], UInt<1>(0h1) - connect _array_literal_expr_27[1], UInt<1>(0h1) - connect _array_literal_expr_27[2], UInt<1>(0h1) - connect _array_literal_expr_25[1], eq(_match_arm_value_14.src_ready_flags[1], _array_literal_expr_27[1]) - wire _array_literal_expr_28: UInt<1>[3] - connect _array_literal_expr_28[0], UInt<1>(0h1) - connect _array_literal_expr_28[1], UInt<1>(0h1) - connect _array_literal_expr_28[2], UInt<1>(0h1) - connect _array_literal_expr_25[2], eq(_match_arm_value_14.src_ready_flags[2], _array_literal_expr_28[2]) - wire _cast_array_to_bits_expr_6: UInt<1>[3] - connect _cast_array_to_bits_expr_6[0], _array_literal_expr_25[0] - connect _cast_array_to_bits_expr_6[1], _array_literal_expr_25[1] - connect _cast_array_to_bits_expr_6[2], _array_literal_expr_25[2] - wire _cast_to_bits_expr_6: UInt<3> - connect _cast_to_bits_expr_6, cat(_cast_array_to_bits_expr_6[2], cat(_cast_array_to_bits_expr_6[1], _cast_array_to_bits_expr_6[0])) - when andr(_cast_to_bits_expr_6): @[unit_base.rs 182:21] - connect ready_op_index_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire empty_op_index_7: Ty89 @[unit_base.rs 158:13] - connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 161:9] - wire ready_op_index_7: Ty89 @[unit_base.rs 164:13] - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 167:9] - match in_flight_ops[7]: @[unit_base.rs 169:9] - HdlNone: - connect empty_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 189:13] - HdlSome(_match_arm_value_15): - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 176:13] - match _match_arm_value_15.state: @[unit_base.rs 178:13] - Ready: - wire _array_literal_expr_29: UInt<1>[3] - wire _array_literal_expr_30: UInt<1>[3] - connect _array_literal_expr_30[0], UInt<1>(0h1) - connect _array_literal_expr_30[1], UInt<1>(0h1) - connect _array_literal_expr_30[2], UInt<1>(0h1) - connect _array_literal_expr_29[0], eq(_match_arm_value_15.src_ready_flags[0], _array_literal_expr_30[0]) - wire _array_literal_expr_31: UInt<1>[3] - connect _array_literal_expr_31[0], UInt<1>(0h1) - connect _array_literal_expr_31[1], UInt<1>(0h1) - connect _array_literal_expr_31[2], UInt<1>(0h1) - connect _array_literal_expr_29[1], eq(_match_arm_value_15.src_ready_flags[1], _array_literal_expr_31[1]) - wire _array_literal_expr_32: UInt<1>[3] - connect _array_literal_expr_32[0], UInt<1>(0h1) - connect _array_literal_expr_32[1], UInt<1>(0h1) - connect _array_literal_expr_32[2], UInt<1>(0h1) - connect _array_literal_expr_29[2], eq(_match_arm_value_15.src_ready_flags[2], _array_literal_expr_32[2]) - wire _cast_array_to_bits_expr_7: UInt<1>[3] - connect _cast_array_to_bits_expr_7[0], _array_literal_expr_29[0] - connect _cast_array_to_bits_expr_7[1], _array_literal_expr_29[1] - connect _cast_array_to_bits_expr_7[2], _array_literal_expr_29[2] - wire _cast_to_bits_expr_7: UInt<3> - connect _cast_to_bits_expr_7, cat(_cast_array_to_bits_expr_7[2], cat(_cast_array_to_bits_expr_7[1], _cast_array_to_bits_expr_7[0])) - when andr(_cast_to_bits_expr_7): @[unit_base.rs 182:21] - connect ready_op_index_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 183:25] - Running: - skip - CanceledAndRunning: - skip - wire or_out_8: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_24: Ty90 - connect _bundle_literal_expr_24.empty_op_index, empty_op_index_7 - connect _bundle_literal_expr_24.ready_op_index, ready_op_index_7 - connect or_out_8, _bundle_literal_expr_24.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_25: Ty90 - connect _bundle_literal_expr_25.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_25.ready_op_index, ready_op_index_6 - match _bundle_literal_expr_25.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_16): - wire _bundle_literal_expr_26: Ty90 - connect _bundle_literal_expr_26.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_26.ready_op_index, ready_op_index_6 - connect or_out_8, _bundle_literal_expr_26.empty_op_index @[unit_base.rs 203:29] - wire or_out_9: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_27: Ty90 - connect _bundle_literal_expr_27.empty_op_index, empty_op_index_7 - connect _bundle_literal_expr_27.ready_op_index, ready_op_index_7 - connect or_out_9, _bundle_literal_expr_27.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_28: Ty90 - connect _bundle_literal_expr_28.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_28.ready_op_index, ready_op_index_6 - match _bundle_literal_expr_28.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_17): - wire _bundle_literal_expr_29: Ty90 - connect _bundle_literal_expr_29.empty_op_index, empty_op_index_6 - connect _bundle_literal_expr_29.ready_op_index, ready_op_index_6 - connect or_out_9, _bundle_literal_expr_29.ready_op_index @[unit_base.rs 204:29] - wire or_out_10: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_30: Ty90 - connect _bundle_literal_expr_30.empty_op_index, or_out_8 - connect _bundle_literal_expr_30.ready_op_index, or_out_9 - connect or_out_10, _bundle_literal_expr_30.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_31: Ty90 - connect _bundle_literal_expr_31.empty_op_index, or_out_6 - connect _bundle_literal_expr_31.ready_op_index, or_out_7 - match _bundle_literal_expr_31.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_18): - wire _bundle_literal_expr_32: Ty90 - connect _bundle_literal_expr_32.empty_op_index, or_out_6 - connect _bundle_literal_expr_32.ready_op_index, or_out_7 - connect or_out_10, _bundle_literal_expr_32.empty_op_index @[unit_base.rs 203:29] - wire or_out_11: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_33: Ty90 - connect _bundle_literal_expr_33.empty_op_index, or_out_8 - connect _bundle_literal_expr_33.ready_op_index, or_out_9 - connect or_out_11, _bundle_literal_expr_33.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_34: Ty90 - connect _bundle_literal_expr_34.empty_op_index, or_out_6 - connect _bundle_literal_expr_34.ready_op_index, or_out_7 - match _bundle_literal_expr_34.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_19): - wire _bundle_literal_expr_35: Ty90 - connect _bundle_literal_expr_35.empty_op_index, or_out_6 - connect _bundle_literal_expr_35.ready_op_index, or_out_7 - connect or_out_11, _bundle_literal_expr_35.ready_op_index @[unit_base.rs 204:29] - wire or_out_12: Ty89 @[unit_base.rs 203:29] - wire _bundle_literal_expr_36: Ty90 - connect _bundle_literal_expr_36.empty_op_index, or_out_10 - connect _bundle_literal_expr_36.ready_op_index, or_out_11 - connect or_out_12, _bundle_literal_expr_36.empty_op_index @[unit_base.rs 203:29] - wire _bundle_literal_expr_37: Ty90 - connect _bundle_literal_expr_37.empty_op_index, or_out_4 - connect _bundle_literal_expr_37.ready_op_index, or_out_5 - match _bundle_literal_expr_37.empty_op_index: @[unit_base.rs 203:29] - HdlNone: - skip - HdlSome(_match_arm_value_20): - wire _bundle_literal_expr_38: Ty90 - connect _bundle_literal_expr_38.empty_op_index, or_out_4 - connect _bundle_literal_expr_38.ready_op_index, or_out_5 - connect or_out_12, _bundle_literal_expr_38.empty_op_index @[unit_base.rs 203:29] - wire or_out_13: Ty89 @[unit_base.rs 204:29] - wire _bundle_literal_expr_39: Ty90 - connect _bundle_literal_expr_39.empty_op_index, or_out_10 - connect _bundle_literal_expr_39.ready_op_index, or_out_11 - connect or_out_13, _bundle_literal_expr_39.ready_op_index @[unit_base.rs 204:29] - wire _bundle_literal_expr_40: Ty90 - connect _bundle_literal_expr_40.empty_op_index, or_out_4 - connect _bundle_literal_expr_40.ready_op_index, or_out_5 - match _bundle_literal_expr_40.ready_op_index: @[unit_base.rs 204:29] - HdlNone: - skip - HdlSome(_match_arm_value_21): - wire _bundle_literal_expr_41: Ty90 - connect _bundle_literal_expr_41.empty_op_index, or_out_4 - connect _bundle_literal_expr_41.ready_op_index, or_out_5 - connect or_out_13, _bundle_literal_expr_41.ready_op_index @[unit_base.rs 204:29] - wire in_flight_ops_summary: Ty90 @[unit_base.rs 257:33] - wire _bundle_literal_expr_42: Ty90 - connect _bundle_literal_expr_42.empty_op_index, or_out_12 - connect _bundle_literal_expr_42.ready_op_index, or_out_13 - connect in_flight_ops_summary, _bundle_literal_expr_42 @[unit_base.rs 258:5] - wire is_some_out: UInt<1> @[unit_base.rs 262:9] - connect is_some_out, UInt<1>(0h0) @[unit_base.rs 262:9] - match in_flight_ops_summary.empty_op_index: @[unit_base.rs 262:9] - HdlNone: - skip - HdlSome(_match_arm_value_22): - connect is_some_out, UInt<1>(0h1) @[unit_base.rs 262:9] - connect unit_to_reg_alloc.input_insn.ready, is_some_out @[unit_base.rs 260:5] - connect unit_to_reg_alloc.`output`, {|HdlNone, HdlSome: Ty73|}(HdlNone) @[unit_base.rs 266:5] - wire input_in_flight_op: Ty88 @[unit_base.rs 272:30] - connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 273:5] - wire firing_data: Ty67 @[ready_valid.rs 30:27] - connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9] - when unit_to_reg_alloc.input_insn.ready: @[ready_valid.rs 33:9] - connect firing_data, unit_to_reg_alloc.input_insn.data @[ready_valid.rs 34:13] - match firing_data: @[unit_base.rs 275:5] - HdlNone: - skip - HdlSome(_match_arm_value_23): - wire input_mop_src_regs: UInt<6>[3] @[unit_base.rs 277:34] - wire _array_literal_expr_33: UInt<6>[3] - wire _bundle_literal_expr_43: Ty25 - wire _bundle_literal_expr_44: Ty23 - connect _bundle_literal_expr_44.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_43.unit_num, _bundle_literal_expr_44 - wire _bundle_literal_expr_45: Ty24 - connect _bundle_literal_expr_45.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_43.unit_out_reg, _bundle_literal_expr_45 - wire _cast_bundle_to_bits_expr: Ty57 - connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_43.unit_num.adj_value - connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_43.unit_out_reg.value - wire _cast_to_bits_expr_8: UInt<6> - connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) - connect _array_literal_expr_33[0], _cast_to_bits_expr_8 - wire _bundle_literal_expr_46: Ty25 - wire _bundle_literal_expr_47: Ty23 - connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47 - wire _bundle_literal_expr_48: Ty24 - connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48 - wire _cast_bundle_to_bits_expr_1: Ty57 - connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_46.unit_num.adj_value - connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_46.unit_out_reg.value - wire _cast_to_bits_expr_9: UInt<6> - connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) - connect _array_literal_expr_33[1], _cast_to_bits_expr_9 - wire _bundle_literal_expr_49: Ty25 - wire _bundle_literal_expr_50: Ty23 - connect _bundle_literal_expr_50.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_49.unit_num, _bundle_literal_expr_50 - wire _bundle_literal_expr_51: Ty24 - connect _bundle_literal_expr_51.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_49.unit_out_reg, _bundle_literal_expr_51 - wire _cast_bundle_to_bits_expr_2: Ty57 - connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_49.unit_num.adj_value - connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_49.unit_out_reg.value - wire _cast_to_bits_expr_10: UInt<6> - connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) - connect _array_literal_expr_33[2], _cast_to_bits_expr_10 - connect input_mop_src_regs, _array_literal_expr_33 @[unit_base.rs 278:9] - match _match_arm_value_23: @[instruction.rs 538:1] - AddSub(_match_arm_value_24): - connect input_mop_src_regs[0], _match_arm_value_24.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_24.alu_common.common.src[1] @[instruction.rs 36:13] - connect input_mop_src_regs[2], _match_arm_value_24.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_25): - connect input_mop_src_regs[0], _match_arm_value_25.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_25.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_26): - connect input_mop_src_regs[0], _match_arm_value_26.alu_common.common.src[0] @[instruction.rs 36:13] - connect input_mop_src_regs[1], _match_arm_value_26.alu_common.common.src[1] @[instruction.rs 36:13] - wire input_in_flight_op_src_ready_flags: UInt<1>[3] @[unit_base.rs 285:13] - wire _bundle_literal_expr_52: Ty25 - wire _bundle_literal_expr_53: Ty23 - connect _bundle_literal_expr_53.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_52.unit_num, _bundle_literal_expr_53 - wire _bundle_literal_expr_54: Ty24 - connect _bundle_literal_expr_54.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_52.unit_out_reg, _bundle_literal_expr_54 - wire _cast_bundle_to_bits_expr_3: Ty57 - connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_52.unit_num.adj_value - connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_52.unit_out_reg.value - wire _cast_to_bits_expr_11: UInt<6> - connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) - connect input_in_flight_op_src_ready_flags[0], eq(_cast_to_bits_expr_11, input_mop_src_regs[0]) @[unit_base.rs 289:13] - wire _bundle_literal_expr_55: Ty25 - wire _bundle_literal_expr_56: Ty23 - connect _bundle_literal_expr_56.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_55.unit_num, _bundle_literal_expr_56 - wire _bundle_literal_expr_57: Ty24 - connect _bundle_literal_expr_57.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_55.unit_out_reg, _bundle_literal_expr_57 - wire _cast_bundle_to_bits_expr_4: Ty57 - connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_55.unit_num.adj_value - connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_55.unit_out_reg.value - wire _cast_to_bits_expr_12: UInt<6> - connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) - connect input_in_flight_op_src_ready_flags[1], eq(_cast_to_bits_expr_12, input_mop_src_regs[1]) @[unit_base.rs 289:13] - wire _bundle_literal_expr_58: Ty25 - wire _bundle_literal_expr_59: Ty23 - connect _bundle_literal_expr_59.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_58.unit_num, _bundle_literal_expr_59 - wire _bundle_literal_expr_60: Ty24 - connect _bundle_literal_expr_60.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_58.unit_out_reg, _bundle_literal_expr_60 - wire _cast_bundle_to_bits_expr_5: Ty57 - connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_58.unit_num.adj_value - connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_58.unit_out_reg.value - wire _cast_to_bits_expr_13: UInt<6> - connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) - connect input_in_flight_op_src_ready_flags[2], eq(_cast_to_bits_expr_13, input_mop_src_regs[2]) @[unit_base.rs 289:13] - wire dest_reg: Ty24 @[instruction.rs 538:1] - match _match_arm_value_23: @[instruction.rs 538:1] - AddSub(_match_arm_value_27): - connect dest_reg, _match_arm_value_27.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_28): - connect dest_reg, _match_arm_value_28.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_29): - connect dest_reg, _match_arm_value_29.alu_common.common.dest @[instruction.rs 538:1] - wire cmp_ne: UInt<1> @[enum_.rs 396:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 398:9] - HdlNone: - wire _bundle_literal_expr_61: Ty69 - connect _bundle_literal_expr_61.which, dest_reg - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_61): @[enum_.rs 410:17] - HdlNone: - connect cmp_ne, UInt<1>(0h0) @[enum_.rs 412:32] - HdlSome(_match_arm_value_30): - connect cmp_ne, UInt<1>(0h1) @[enum_.rs 411:35] - HdlSome(_match_arm_value_31): - wire _bundle_literal_expr_62: Ty69 - connect _bundle_literal_expr_62.which, dest_reg - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_62): @[enum_.rs 402:17] - HdlNone: - connect cmp_ne, UInt<1>(0h1) @[enum_.rs 404:32] - HdlSome(_match_arm_value_32): - connect cmp_ne, neq(_match_arm_value_31.which.value, _match_arm_value_32.which.value) @[enum_.rs 403:37] - when cmp_ne: @[unit_base.rs 299:9] - wire _bundle_literal_expr_63: Ty87 - connect _bundle_literal_expr_63.state, {|Ready, Running, CanceledAndRunning|}(Ready) - connect _bundle_literal_expr_63.mop, _match_arm_value_23 - connect _bundle_literal_expr_63.src_ready_flags, input_in_flight_op_src_ready_flags - connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_63) @[unit_base.rs 305:13] - match in_flight_ops_summary.empty_op_index: @[unit_base.rs 318:9] - HdlNone: - skip - HdlSome(_match_arm_value_33): - connect in_flight_ops[_match_arm_value_33], input_in_flight_op @[unit_base.rs 319:13] - wire in_flight_op_next_state: Ty91[8] @[unit_base.rs 324:35] - wire in_flight_op_next_src_ready_flags: UInt<1>[3][8] @[unit_base.rs 327:9] - wire in_flight_op_canceling: UInt<1>[8] @[unit_base.rs 329:34] - wire in_flight_op_execute_starting: UInt<1>[8] @[unit_base.rs 331:41] - wire in_flight_op_execute_ending: UInt<1>[8] @[unit_base.rs 333:39] - wire _array_literal_expr_34: UInt<1>[3] - connect _array_literal_expr_34[0], UInt<1>(0h0) - connect _array_literal_expr_34[1], UInt<1>(0h0) - connect _array_literal_expr_34[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[0], _array_literal_expr_34 @[unit_base.rs 335:9] - connect in_flight_op_canceling[0], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[0], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[0], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[0]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_34): - wire dest_reg_1: Ty24 @[instruction.rs 538:1] - match _match_arm_value_34.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_35): - connect dest_reg_1, _match_arm_value_35.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_36): - connect dest_reg_1, _match_arm_value_36.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_37): - connect dest_reg_1, _match_arm_value_37.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_0: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_35: UInt<6>[3] - wire _bundle_literal_expr_64: Ty25 - wire _bundle_literal_expr_65: Ty23 - connect _bundle_literal_expr_65.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_64.unit_num, _bundle_literal_expr_65 - wire _bundle_literal_expr_66: Ty24 - connect _bundle_literal_expr_66.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_64.unit_out_reg, _bundle_literal_expr_66 - wire _cast_bundle_to_bits_expr_6: Ty57 - connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_64.unit_num.adj_value - connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_64.unit_out_reg.value - wire _cast_to_bits_expr_14: UInt<6> - connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) - connect _array_literal_expr_35[0], _cast_to_bits_expr_14 - wire _bundle_literal_expr_67: Ty25 - wire _bundle_literal_expr_68: Ty23 - connect _bundle_literal_expr_68.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_67.unit_num, _bundle_literal_expr_68 - wire _bundle_literal_expr_69: Ty24 - connect _bundle_literal_expr_69.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_67.unit_out_reg, _bundle_literal_expr_69 - wire _cast_bundle_to_bits_expr_7: Ty57 - connect _cast_bundle_to_bits_expr_7.unit_num, _bundle_literal_expr_67.unit_num.adj_value - connect _cast_bundle_to_bits_expr_7.unit_out_reg, _bundle_literal_expr_67.unit_out_reg.value - wire _cast_to_bits_expr_15: UInt<6> - connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num) - connect _array_literal_expr_35[1], _cast_to_bits_expr_15 - wire _bundle_literal_expr_70: Ty25 - wire _bundle_literal_expr_71: Ty23 - connect _bundle_literal_expr_71.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_70.unit_num, _bundle_literal_expr_71 - wire _bundle_literal_expr_72: Ty24 - connect _bundle_literal_expr_72.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_70.unit_out_reg, _bundle_literal_expr_72 - wire _cast_bundle_to_bits_expr_8: Ty57 - connect _cast_bundle_to_bits_expr_8.unit_num, _bundle_literal_expr_70.unit_num.adj_value - connect _cast_bundle_to_bits_expr_8.unit_out_reg, _bundle_literal_expr_70.unit_out_reg.value - wire _cast_to_bits_expr_16: UInt<6> - connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num) - connect _array_literal_expr_35[2], _cast_to_bits_expr_16 - connect in_flight_op_src_regs_0, _array_literal_expr_35 @[unit_base.rs 356:13] - match _match_arm_value_34.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_38): - connect in_flight_op_src_regs_0[0], _match_arm_value_38.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_38.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[2], _match_arm_value_38.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_39): - connect in_flight_op_src_regs_0[0], _match_arm_value_39.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_39.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_40): - connect in_flight_op_src_regs_0[0], _match_arm_value_40.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_0[1], _match_arm_value_40.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[0], _match_arm_value_34.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_41): - wire _bundle_literal_expr_73: Ty25 - wire _bundle_literal_expr_74: Ty23 - connect _bundle_literal_expr_74.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_73.unit_num, _bundle_literal_expr_74 - connect _bundle_literal_expr_73.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_9: Ty57 - connect _cast_bundle_to_bits_expr_9.unit_num, _bundle_literal_expr_73.unit_num.adj_value - connect _cast_bundle_to_bits_expr_9.unit_out_reg, _bundle_literal_expr_73.unit_out_reg.value - wire _cast_to_bits_expr_17: UInt<6> - connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_9.unit_out_reg, _cast_bundle_to_bits_expr_9.unit_num) - when eq(_cast_to_bits_expr_17, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_75: Ty25 - wire _bundle_literal_expr_76: Ty23 - connect _bundle_literal_expr_76.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_75.unit_num, _bundle_literal_expr_76 - connect _bundle_literal_expr_75.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_10: Ty57 - connect _cast_bundle_to_bits_expr_10.unit_num, _bundle_literal_expr_75.unit_num.adj_value - connect _cast_bundle_to_bits_expr_10.unit_out_reg, _bundle_literal_expr_75.unit_out_reg.value - wire _cast_to_bits_expr_18: UInt<6> - connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_10.unit_out_reg, _cast_bundle_to_bits_expr_10.unit_num) - when eq(_cast_to_bits_expr_18, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_77: Ty25 - wire _bundle_literal_expr_78: Ty23 - connect _bundle_literal_expr_78.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_77.unit_num, _bundle_literal_expr_78 - connect _bundle_literal_expr_77.unit_out_reg, _match_arm_value_41.which - wire _cast_bundle_to_bits_expr_11: Ty57 - connect _cast_bundle_to_bits_expr_11.unit_num, _bundle_literal_expr_77.unit_num.adj_value - connect _cast_bundle_to_bits_expr_11.unit_out_reg, _bundle_literal_expr_77.unit_out_reg.value - wire _cast_to_bits_expr_19: UInt<6> - connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num) - when eq(_cast_to_bits_expr_19, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_42): - wire _bundle_literal_expr_79: Ty25 - wire _bundle_literal_expr_80: Ty23 - connect _bundle_literal_expr_80.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_79.unit_num, _bundle_literal_expr_80 - connect _bundle_literal_expr_79.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_12: Ty57 - connect _cast_bundle_to_bits_expr_12.unit_num, _bundle_literal_expr_79.unit_num.adj_value - connect _cast_bundle_to_bits_expr_12.unit_out_reg, _bundle_literal_expr_79.unit_out_reg.value - wire _cast_to_bits_expr_20: UInt<6> - connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num) - when eq(_cast_to_bits_expr_20, in_flight_op_src_regs_0[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_81: Ty25 - wire _bundle_literal_expr_82: Ty23 - connect _bundle_literal_expr_82.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_81.unit_num, _bundle_literal_expr_82 - connect _bundle_literal_expr_81.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_13: Ty57 - connect _cast_bundle_to_bits_expr_13.unit_num, _bundle_literal_expr_81.unit_num.adj_value - connect _cast_bundle_to_bits_expr_13.unit_out_reg, _bundle_literal_expr_81.unit_out_reg.value - wire _cast_to_bits_expr_21: UInt<6> - connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num) - when eq(_cast_to_bits_expr_21, in_flight_op_src_regs_0[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_83: Ty25 - wire _bundle_literal_expr_84: Ty23 - connect _bundle_literal_expr_84.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_83.unit_num, _bundle_literal_expr_84 - connect _bundle_literal_expr_83.unit_out_reg, _match_arm_value_42.which - wire _cast_bundle_to_bits_expr_14: Ty57 - connect _cast_bundle_to_bits_expr_14.unit_num, _bundle_literal_expr_83.unit_num.adj_value - connect _cast_bundle_to_bits_expr_14.unit_out_reg, _bundle_literal_expr_83.unit_out_reg.value - wire _cast_to_bits_expr_22: UInt<6> - connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num) - when eq(_cast_to_bits_expr_22, in_flight_op_src_regs_0[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[0][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_85: Ty69 - connect _bundle_literal_expr_85.which, dest_reg_1 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_85): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_43): - connect cmp_eq, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_44): - wire _bundle_literal_expr_86: Ty69 - connect _bundle_literal_expr_86.which, dest_reg_1 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_86): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_45): - connect cmp_eq, eq(_match_arm_value_44.which.value, _match_arm_value_45.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[0], cmp_eq @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_46): - when eq(dest_reg_1.value, _match_arm_value_46.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[0], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_1: Ty81 @[ready_valid.rs 30:27] - connect firing_data_1, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_1, execute_start.data @[ready_valid.rs 34:13] - match firing_data_1: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_47): - wire dest_reg_2: Ty24 @[instruction.rs 538:1] - match _match_arm_value_47.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_48): - connect dest_reg_2, _match_arm_value_48.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_49): - connect dest_reg_2, _match_arm_value_49.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_50): - connect dest_reg_2, _match_arm_value_50.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_1.value, dest_reg_2.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[0], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_34.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[0]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[0]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[0], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[0]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_51): - wire _bundle_literal_expr_87: Ty87 - connect _bundle_literal_expr_87.state, _match_arm_value_51 - connect _bundle_literal_expr_87.mop, _match_arm_value_34.mop - connect _bundle_literal_expr_87.src_ready_flags, _match_arm_value_34.src_ready_flags - connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_87) @[unit_base.rs 435:17] - wire _array_literal_expr_36: UInt<1>[3] - connect _array_literal_expr_36[0], UInt<1>(0h0) - connect _array_literal_expr_36[1], UInt<1>(0h0) - connect _array_literal_expr_36[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[1], _array_literal_expr_36 @[unit_base.rs 335:9] - connect in_flight_op_canceling[1], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[1], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[1], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[1]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_52): - wire dest_reg_3: Ty24 @[instruction.rs 538:1] - match _match_arm_value_52.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_53): - connect dest_reg_3, _match_arm_value_53.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_54): - connect dest_reg_3, _match_arm_value_54.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_55): - connect dest_reg_3, _match_arm_value_55.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_1: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_37: UInt<6>[3] - wire _bundle_literal_expr_88: Ty25 - wire _bundle_literal_expr_89: Ty23 - connect _bundle_literal_expr_89.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_88.unit_num, _bundle_literal_expr_89 - wire _bundle_literal_expr_90: Ty24 - connect _bundle_literal_expr_90.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_88.unit_out_reg, _bundle_literal_expr_90 - wire _cast_bundle_to_bits_expr_15: Ty57 - connect _cast_bundle_to_bits_expr_15.unit_num, _bundle_literal_expr_88.unit_num.adj_value - connect _cast_bundle_to_bits_expr_15.unit_out_reg, _bundle_literal_expr_88.unit_out_reg.value - wire _cast_to_bits_expr_23: UInt<6> - connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_15.unit_out_reg, _cast_bundle_to_bits_expr_15.unit_num) - connect _array_literal_expr_37[0], _cast_to_bits_expr_23 - wire _bundle_literal_expr_91: Ty25 - wire _bundle_literal_expr_92: Ty23 - connect _bundle_literal_expr_92.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_91.unit_num, _bundle_literal_expr_92 - wire _bundle_literal_expr_93: Ty24 - connect _bundle_literal_expr_93.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_91.unit_out_reg, _bundle_literal_expr_93 - wire _cast_bundle_to_bits_expr_16: Ty57 - connect _cast_bundle_to_bits_expr_16.unit_num, _bundle_literal_expr_91.unit_num.adj_value - connect _cast_bundle_to_bits_expr_16.unit_out_reg, _bundle_literal_expr_91.unit_out_reg.value - wire _cast_to_bits_expr_24: UInt<6> - connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_16.unit_out_reg, _cast_bundle_to_bits_expr_16.unit_num) - connect _array_literal_expr_37[1], _cast_to_bits_expr_24 - wire _bundle_literal_expr_94: Ty25 - wire _bundle_literal_expr_95: Ty23 - connect _bundle_literal_expr_95.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_94.unit_num, _bundle_literal_expr_95 - wire _bundle_literal_expr_96: Ty24 - connect _bundle_literal_expr_96.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_94.unit_out_reg, _bundle_literal_expr_96 - wire _cast_bundle_to_bits_expr_17: Ty57 - connect _cast_bundle_to_bits_expr_17.unit_num, _bundle_literal_expr_94.unit_num.adj_value - connect _cast_bundle_to_bits_expr_17.unit_out_reg, _bundle_literal_expr_94.unit_out_reg.value - wire _cast_to_bits_expr_25: UInt<6> - connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_17.unit_out_reg, _cast_bundle_to_bits_expr_17.unit_num) - connect _array_literal_expr_37[2], _cast_to_bits_expr_25 - connect in_flight_op_src_regs_1, _array_literal_expr_37 @[unit_base.rs 356:13] - match _match_arm_value_52.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_56): - connect in_flight_op_src_regs_1[0], _match_arm_value_56.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_56.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[2], _match_arm_value_56.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_57): - connect in_flight_op_src_regs_1[0], _match_arm_value_57.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_57.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_58): - connect in_flight_op_src_regs_1[0], _match_arm_value_58.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_1[1], _match_arm_value_58.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[1], _match_arm_value_52.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_59): - wire _bundle_literal_expr_97: Ty25 - wire _bundle_literal_expr_98: Ty23 - connect _bundle_literal_expr_98.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_97.unit_num, _bundle_literal_expr_98 - connect _bundle_literal_expr_97.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_18: Ty57 - connect _cast_bundle_to_bits_expr_18.unit_num, _bundle_literal_expr_97.unit_num.adj_value - connect _cast_bundle_to_bits_expr_18.unit_out_reg, _bundle_literal_expr_97.unit_out_reg.value - wire _cast_to_bits_expr_26: UInt<6> - connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num) - when eq(_cast_to_bits_expr_26, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_99: Ty25 - wire _bundle_literal_expr_100: Ty23 - connect _bundle_literal_expr_100.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_99.unit_num, _bundle_literal_expr_100 - connect _bundle_literal_expr_99.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_19: Ty57 - connect _cast_bundle_to_bits_expr_19.unit_num, _bundle_literal_expr_99.unit_num.adj_value - connect _cast_bundle_to_bits_expr_19.unit_out_reg, _bundle_literal_expr_99.unit_out_reg.value - wire _cast_to_bits_expr_27: UInt<6> - connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num) - when eq(_cast_to_bits_expr_27, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_101: Ty25 - wire _bundle_literal_expr_102: Ty23 - connect _bundle_literal_expr_102.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_101.unit_num, _bundle_literal_expr_102 - connect _bundle_literal_expr_101.unit_out_reg, _match_arm_value_59.which - wire _cast_bundle_to_bits_expr_20: Ty57 - connect _cast_bundle_to_bits_expr_20.unit_num, _bundle_literal_expr_101.unit_num.adj_value - connect _cast_bundle_to_bits_expr_20.unit_out_reg, _bundle_literal_expr_101.unit_out_reg.value - wire _cast_to_bits_expr_28: UInt<6> - connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num) - when eq(_cast_to_bits_expr_28, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_60): - wire _bundle_literal_expr_103: Ty25 - wire _bundle_literal_expr_104: Ty23 - connect _bundle_literal_expr_104.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_103.unit_num, _bundle_literal_expr_104 - connect _bundle_literal_expr_103.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_21: Ty57 - connect _cast_bundle_to_bits_expr_21.unit_num, _bundle_literal_expr_103.unit_num.adj_value - connect _cast_bundle_to_bits_expr_21.unit_out_reg, _bundle_literal_expr_103.unit_out_reg.value - wire _cast_to_bits_expr_29: UInt<6> - connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num) - when eq(_cast_to_bits_expr_29, in_flight_op_src_regs_1[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_105: Ty25 - wire _bundle_literal_expr_106: Ty23 - connect _bundle_literal_expr_106.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_105.unit_num, _bundle_literal_expr_106 - connect _bundle_literal_expr_105.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_22: Ty57 - connect _cast_bundle_to_bits_expr_22.unit_num, _bundle_literal_expr_105.unit_num.adj_value - connect _cast_bundle_to_bits_expr_22.unit_out_reg, _bundle_literal_expr_105.unit_out_reg.value - wire _cast_to_bits_expr_30: UInt<6> - connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_22.unit_out_reg, _cast_bundle_to_bits_expr_22.unit_num) - when eq(_cast_to_bits_expr_30, in_flight_op_src_regs_1[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_107: Ty25 - wire _bundle_literal_expr_108: Ty23 - connect _bundle_literal_expr_108.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_107.unit_num, _bundle_literal_expr_108 - connect _bundle_literal_expr_107.unit_out_reg, _match_arm_value_60.which - wire _cast_bundle_to_bits_expr_23: Ty57 - connect _cast_bundle_to_bits_expr_23.unit_num, _bundle_literal_expr_107.unit_num.adj_value - connect _cast_bundle_to_bits_expr_23.unit_out_reg, _bundle_literal_expr_107.unit_out_reg.value - wire _cast_to_bits_expr_31: UInt<6> - connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_23.unit_out_reg, _cast_bundle_to_bits_expr_23.unit_num) - when eq(_cast_to_bits_expr_31, in_flight_op_src_regs_1[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[1][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_1: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_109: Ty69 - connect _bundle_literal_expr_109.which, dest_reg_3 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_109): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_1, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_61): - connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_62): - wire _bundle_literal_expr_110: Ty69 - connect _bundle_literal_expr_110.which, dest_reg_3 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_110): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_1, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_63): - connect cmp_eq_1, eq(_match_arm_value_62.which.value, _match_arm_value_63.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[1], cmp_eq_1 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_64): - when eq(dest_reg_3.value, _match_arm_value_64.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[1], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_2: Ty81 @[ready_valid.rs 30:27] - connect firing_data_2, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_2, execute_start.data @[ready_valid.rs 34:13] - match firing_data_2: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_65): - wire dest_reg_4: Ty24 @[instruction.rs 538:1] - match _match_arm_value_65.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_66): - connect dest_reg_4, _match_arm_value_66.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_67): - connect dest_reg_4, _match_arm_value_67.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_68): - connect dest_reg_4, _match_arm_value_68.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_3.value, dest_reg_4.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[1], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_52.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[1]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[1]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[1], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[1]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_69): - wire _bundle_literal_expr_111: Ty87 - connect _bundle_literal_expr_111.state, _match_arm_value_69 - connect _bundle_literal_expr_111.mop, _match_arm_value_52.mop - connect _bundle_literal_expr_111.src_ready_flags, _match_arm_value_52.src_ready_flags - connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_111) @[unit_base.rs 435:17] - wire _array_literal_expr_38: UInt<1>[3] - connect _array_literal_expr_38[0], UInt<1>(0h0) - connect _array_literal_expr_38[1], UInt<1>(0h0) - connect _array_literal_expr_38[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[2], _array_literal_expr_38 @[unit_base.rs 335:9] - connect in_flight_op_canceling[2], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[2], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[2], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[2]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_70): - wire dest_reg_5: Ty24 @[instruction.rs 538:1] - match _match_arm_value_70.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_71): - connect dest_reg_5, _match_arm_value_71.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_72): - connect dest_reg_5, _match_arm_value_72.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_73): - connect dest_reg_5, _match_arm_value_73.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_2: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_39: UInt<6>[3] - wire _bundle_literal_expr_112: Ty25 - wire _bundle_literal_expr_113: Ty23 - connect _bundle_literal_expr_113.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_112.unit_num, _bundle_literal_expr_113 - wire _bundle_literal_expr_114: Ty24 - connect _bundle_literal_expr_114.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_112.unit_out_reg, _bundle_literal_expr_114 - wire _cast_bundle_to_bits_expr_24: Ty57 - connect _cast_bundle_to_bits_expr_24.unit_num, _bundle_literal_expr_112.unit_num.adj_value - connect _cast_bundle_to_bits_expr_24.unit_out_reg, _bundle_literal_expr_112.unit_out_reg.value - wire _cast_to_bits_expr_32: UInt<6> - connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_24.unit_out_reg, _cast_bundle_to_bits_expr_24.unit_num) - connect _array_literal_expr_39[0], _cast_to_bits_expr_32 - wire _bundle_literal_expr_115: Ty25 - wire _bundle_literal_expr_116: Ty23 - connect _bundle_literal_expr_116.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_115.unit_num, _bundle_literal_expr_116 - wire _bundle_literal_expr_117: Ty24 - connect _bundle_literal_expr_117.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_115.unit_out_reg, _bundle_literal_expr_117 - wire _cast_bundle_to_bits_expr_25: Ty57 - connect _cast_bundle_to_bits_expr_25.unit_num, _bundle_literal_expr_115.unit_num.adj_value - connect _cast_bundle_to_bits_expr_25.unit_out_reg, _bundle_literal_expr_115.unit_out_reg.value - wire _cast_to_bits_expr_33: UInt<6> - connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_25.unit_out_reg, _cast_bundle_to_bits_expr_25.unit_num) - connect _array_literal_expr_39[1], _cast_to_bits_expr_33 - wire _bundle_literal_expr_118: Ty25 - wire _bundle_literal_expr_119: Ty23 - connect _bundle_literal_expr_119.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_118.unit_num, _bundle_literal_expr_119 - wire _bundle_literal_expr_120: Ty24 - connect _bundle_literal_expr_120.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_118.unit_out_reg, _bundle_literal_expr_120 - wire _cast_bundle_to_bits_expr_26: Ty57 - connect _cast_bundle_to_bits_expr_26.unit_num, _bundle_literal_expr_118.unit_num.adj_value - connect _cast_bundle_to_bits_expr_26.unit_out_reg, _bundle_literal_expr_118.unit_out_reg.value - wire _cast_to_bits_expr_34: UInt<6> - connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_26.unit_out_reg, _cast_bundle_to_bits_expr_26.unit_num) - connect _array_literal_expr_39[2], _cast_to_bits_expr_34 - connect in_flight_op_src_regs_2, _array_literal_expr_39 @[unit_base.rs 356:13] - match _match_arm_value_70.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_74): - connect in_flight_op_src_regs_2[0], _match_arm_value_74.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_74.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[2], _match_arm_value_74.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_75): - connect in_flight_op_src_regs_2[0], _match_arm_value_75.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_75.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_76): - connect in_flight_op_src_regs_2[0], _match_arm_value_76.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_2[1], _match_arm_value_76.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[2], _match_arm_value_70.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_77): - wire _bundle_literal_expr_121: Ty25 - wire _bundle_literal_expr_122: Ty23 - connect _bundle_literal_expr_122.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_121.unit_num, _bundle_literal_expr_122 - connect _bundle_literal_expr_121.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_27: Ty57 - connect _cast_bundle_to_bits_expr_27.unit_num, _bundle_literal_expr_121.unit_num.adj_value - connect _cast_bundle_to_bits_expr_27.unit_out_reg, _bundle_literal_expr_121.unit_out_reg.value - wire _cast_to_bits_expr_35: UInt<6> - connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_27.unit_out_reg, _cast_bundle_to_bits_expr_27.unit_num) - when eq(_cast_to_bits_expr_35, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_123: Ty25 - wire _bundle_literal_expr_124: Ty23 - connect _bundle_literal_expr_124.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_123.unit_num, _bundle_literal_expr_124 - connect _bundle_literal_expr_123.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_28: Ty57 - connect _cast_bundle_to_bits_expr_28.unit_num, _bundle_literal_expr_123.unit_num.adj_value - connect _cast_bundle_to_bits_expr_28.unit_out_reg, _bundle_literal_expr_123.unit_out_reg.value - wire _cast_to_bits_expr_36: UInt<6> - connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num) - when eq(_cast_to_bits_expr_36, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_125: Ty25 - wire _bundle_literal_expr_126: Ty23 - connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126 - connect _bundle_literal_expr_125.unit_out_reg, _match_arm_value_77.which - wire _cast_bundle_to_bits_expr_29: Ty57 - connect _cast_bundle_to_bits_expr_29.unit_num, _bundle_literal_expr_125.unit_num.adj_value - connect _cast_bundle_to_bits_expr_29.unit_out_reg, _bundle_literal_expr_125.unit_out_reg.value - wire _cast_to_bits_expr_37: UInt<6> - connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_29.unit_out_reg, _cast_bundle_to_bits_expr_29.unit_num) - when eq(_cast_to_bits_expr_37, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_78): - wire _bundle_literal_expr_127: Ty25 - wire _bundle_literal_expr_128: Ty23 - connect _bundle_literal_expr_128.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_127.unit_num, _bundle_literal_expr_128 - connect _bundle_literal_expr_127.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_30: Ty57 - connect _cast_bundle_to_bits_expr_30.unit_num, _bundle_literal_expr_127.unit_num.adj_value - connect _cast_bundle_to_bits_expr_30.unit_out_reg, _bundle_literal_expr_127.unit_out_reg.value - wire _cast_to_bits_expr_38: UInt<6> - connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_30.unit_out_reg, _cast_bundle_to_bits_expr_30.unit_num) - when eq(_cast_to_bits_expr_38, in_flight_op_src_regs_2[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_129: Ty25 - wire _bundle_literal_expr_130: Ty23 - connect _bundle_literal_expr_130.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_129.unit_num, _bundle_literal_expr_130 - connect _bundle_literal_expr_129.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_31: Ty57 - connect _cast_bundle_to_bits_expr_31.unit_num, _bundle_literal_expr_129.unit_num.adj_value - connect _cast_bundle_to_bits_expr_31.unit_out_reg, _bundle_literal_expr_129.unit_out_reg.value - wire _cast_to_bits_expr_39: UInt<6> - connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_31.unit_out_reg, _cast_bundle_to_bits_expr_31.unit_num) - when eq(_cast_to_bits_expr_39, in_flight_op_src_regs_2[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_131: Ty25 - wire _bundle_literal_expr_132: Ty23 - connect _bundle_literal_expr_132.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_131.unit_num, _bundle_literal_expr_132 - connect _bundle_literal_expr_131.unit_out_reg, _match_arm_value_78.which - wire _cast_bundle_to_bits_expr_32: Ty57 - connect _cast_bundle_to_bits_expr_32.unit_num, _bundle_literal_expr_131.unit_num.adj_value - connect _cast_bundle_to_bits_expr_32.unit_out_reg, _bundle_literal_expr_131.unit_out_reg.value - wire _cast_to_bits_expr_40: UInt<6> - connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_32.unit_out_reg, _cast_bundle_to_bits_expr_32.unit_num) - when eq(_cast_to_bits_expr_40, in_flight_op_src_regs_2[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[2][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_2: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_133: Ty69 - connect _bundle_literal_expr_133.which, dest_reg_5 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_133): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_2, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_79): - connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_80): - wire _bundle_literal_expr_134: Ty69 - connect _bundle_literal_expr_134.which, dest_reg_5 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_134): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_2, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_81): - connect cmp_eq_2, eq(_match_arm_value_80.which.value, _match_arm_value_81.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[2], cmp_eq_2 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_82): - when eq(dest_reg_5.value, _match_arm_value_82.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[2], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_3: Ty81 @[ready_valid.rs 30:27] - connect firing_data_3, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_3, execute_start.data @[ready_valid.rs 34:13] - match firing_data_3: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_83): - wire dest_reg_6: Ty24 @[instruction.rs 538:1] - match _match_arm_value_83.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_84): - connect dest_reg_6, _match_arm_value_84.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_85): - connect dest_reg_6, _match_arm_value_85.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_86): - connect dest_reg_6, _match_arm_value_86.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_5.value, dest_reg_6.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[2], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_70.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[2]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[2]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[2], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[2]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_87): - wire _bundle_literal_expr_135: Ty87 - connect _bundle_literal_expr_135.state, _match_arm_value_87 - connect _bundle_literal_expr_135.mop, _match_arm_value_70.mop - connect _bundle_literal_expr_135.src_ready_flags, _match_arm_value_70.src_ready_flags - connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_135) @[unit_base.rs 435:17] - wire _array_literal_expr_40: UInt<1>[3] - connect _array_literal_expr_40[0], UInt<1>(0h0) - connect _array_literal_expr_40[1], UInt<1>(0h0) - connect _array_literal_expr_40[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[3], _array_literal_expr_40 @[unit_base.rs 335:9] - connect in_flight_op_canceling[3], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[3], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[3], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[3]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_88): - wire dest_reg_7: Ty24 @[instruction.rs 538:1] - match _match_arm_value_88.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_89): - connect dest_reg_7, _match_arm_value_89.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_90): - connect dest_reg_7, _match_arm_value_90.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_91): - connect dest_reg_7, _match_arm_value_91.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_3: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_41: UInt<6>[3] - wire _bundle_literal_expr_136: Ty25 - wire _bundle_literal_expr_137: Ty23 - connect _bundle_literal_expr_137.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137 - wire _bundle_literal_expr_138: Ty24 - connect _bundle_literal_expr_138.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138 - wire _cast_bundle_to_bits_expr_33: Ty57 - connect _cast_bundle_to_bits_expr_33.unit_num, _bundle_literal_expr_136.unit_num.adj_value - connect _cast_bundle_to_bits_expr_33.unit_out_reg, _bundle_literal_expr_136.unit_out_reg.value - wire _cast_to_bits_expr_41: UInt<6> - connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_33.unit_out_reg, _cast_bundle_to_bits_expr_33.unit_num) - connect _array_literal_expr_41[0], _cast_to_bits_expr_41 - wire _bundle_literal_expr_139: Ty25 - wire _bundle_literal_expr_140: Ty23 - connect _bundle_literal_expr_140.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_139.unit_num, _bundle_literal_expr_140 - wire _bundle_literal_expr_141: Ty24 - connect _bundle_literal_expr_141.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_139.unit_out_reg, _bundle_literal_expr_141 - wire _cast_bundle_to_bits_expr_34: Ty57 - connect _cast_bundle_to_bits_expr_34.unit_num, _bundle_literal_expr_139.unit_num.adj_value - connect _cast_bundle_to_bits_expr_34.unit_out_reg, _bundle_literal_expr_139.unit_out_reg.value - wire _cast_to_bits_expr_42: UInt<6> - connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_34.unit_out_reg, _cast_bundle_to_bits_expr_34.unit_num) - connect _array_literal_expr_41[1], _cast_to_bits_expr_42 - wire _bundle_literal_expr_142: Ty25 - wire _bundle_literal_expr_143: Ty23 - connect _bundle_literal_expr_143.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_142.unit_num, _bundle_literal_expr_143 - wire _bundle_literal_expr_144: Ty24 - connect _bundle_literal_expr_144.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_142.unit_out_reg, _bundle_literal_expr_144 - wire _cast_bundle_to_bits_expr_35: Ty57 - connect _cast_bundle_to_bits_expr_35.unit_num, _bundle_literal_expr_142.unit_num.adj_value - connect _cast_bundle_to_bits_expr_35.unit_out_reg, _bundle_literal_expr_142.unit_out_reg.value - wire _cast_to_bits_expr_43: UInt<6> - connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num) - connect _array_literal_expr_41[2], _cast_to_bits_expr_43 - connect in_flight_op_src_regs_3, _array_literal_expr_41 @[unit_base.rs 356:13] - match _match_arm_value_88.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_92): - connect in_flight_op_src_regs_3[0], _match_arm_value_92.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_92.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[2], _match_arm_value_92.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_93): - connect in_flight_op_src_regs_3[0], _match_arm_value_93.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_93.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_94): - connect in_flight_op_src_regs_3[0], _match_arm_value_94.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_3[1], _match_arm_value_94.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[3], _match_arm_value_88.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_95): - wire _bundle_literal_expr_145: Ty25 - wire _bundle_literal_expr_146: Ty23 - connect _bundle_literal_expr_146.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_145.unit_num, _bundle_literal_expr_146 - connect _bundle_literal_expr_145.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_36: Ty57 - connect _cast_bundle_to_bits_expr_36.unit_num, _bundle_literal_expr_145.unit_num.adj_value - connect _cast_bundle_to_bits_expr_36.unit_out_reg, _bundle_literal_expr_145.unit_out_reg.value - wire _cast_to_bits_expr_44: UInt<6> - connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_36.unit_out_reg, _cast_bundle_to_bits_expr_36.unit_num) - when eq(_cast_to_bits_expr_44, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_147: Ty25 - wire _bundle_literal_expr_148: Ty23 - connect _bundle_literal_expr_148.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_147.unit_num, _bundle_literal_expr_148 - connect _bundle_literal_expr_147.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_37: Ty57 - connect _cast_bundle_to_bits_expr_37.unit_num, _bundle_literal_expr_147.unit_num.adj_value - connect _cast_bundle_to_bits_expr_37.unit_out_reg, _bundle_literal_expr_147.unit_out_reg.value - wire _cast_to_bits_expr_45: UInt<6> - connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_37.unit_out_reg, _cast_bundle_to_bits_expr_37.unit_num) - when eq(_cast_to_bits_expr_45, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_149: Ty25 - wire _bundle_literal_expr_150: Ty23 - connect _bundle_literal_expr_150.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_149.unit_num, _bundle_literal_expr_150 - connect _bundle_literal_expr_149.unit_out_reg, _match_arm_value_95.which - wire _cast_bundle_to_bits_expr_38: Ty57 - connect _cast_bundle_to_bits_expr_38.unit_num, _bundle_literal_expr_149.unit_num.adj_value - connect _cast_bundle_to_bits_expr_38.unit_out_reg, _bundle_literal_expr_149.unit_out_reg.value - wire _cast_to_bits_expr_46: UInt<6> - connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_38.unit_out_reg, _cast_bundle_to_bits_expr_38.unit_num) - when eq(_cast_to_bits_expr_46, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_96): - wire _bundle_literal_expr_151: Ty25 - wire _bundle_literal_expr_152: Ty23 - connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152 - connect _bundle_literal_expr_151.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_39: Ty57 - connect _cast_bundle_to_bits_expr_39.unit_num, _bundle_literal_expr_151.unit_num.adj_value - connect _cast_bundle_to_bits_expr_39.unit_out_reg, _bundle_literal_expr_151.unit_out_reg.value - wire _cast_to_bits_expr_47: UInt<6> - connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num) - when eq(_cast_to_bits_expr_47, in_flight_op_src_regs_3[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_153: Ty25 - wire _bundle_literal_expr_154: Ty23 - connect _bundle_literal_expr_154.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_153.unit_num, _bundle_literal_expr_154 - connect _bundle_literal_expr_153.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_40: Ty57 - connect _cast_bundle_to_bits_expr_40.unit_num, _bundle_literal_expr_153.unit_num.adj_value - connect _cast_bundle_to_bits_expr_40.unit_out_reg, _bundle_literal_expr_153.unit_out_reg.value - wire _cast_to_bits_expr_48: UInt<6> - connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num) - when eq(_cast_to_bits_expr_48, in_flight_op_src_regs_3[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_155: Ty25 - wire _bundle_literal_expr_156: Ty23 - connect _bundle_literal_expr_156.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_155.unit_num, _bundle_literal_expr_156 - connect _bundle_literal_expr_155.unit_out_reg, _match_arm_value_96.which - wire _cast_bundle_to_bits_expr_41: Ty57 - connect _cast_bundle_to_bits_expr_41.unit_num, _bundle_literal_expr_155.unit_num.adj_value - connect _cast_bundle_to_bits_expr_41.unit_out_reg, _bundle_literal_expr_155.unit_out_reg.value - wire _cast_to_bits_expr_49: UInt<6> - connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num) - when eq(_cast_to_bits_expr_49, in_flight_op_src_regs_3[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[3][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_3: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_157: Ty69 - connect _bundle_literal_expr_157.which, dest_reg_7 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_157): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_3, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_97): - connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_98): - wire _bundle_literal_expr_158: Ty69 - connect _bundle_literal_expr_158.which, dest_reg_7 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_158): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_3, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_99): - connect cmp_eq_3, eq(_match_arm_value_98.which.value, _match_arm_value_99.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[3], cmp_eq_3 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_100): - when eq(dest_reg_7.value, _match_arm_value_100.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[3], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_4: Ty81 @[ready_valid.rs 30:27] - connect firing_data_4, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_4, execute_start.data @[ready_valid.rs 34:13] - match firing_data_4: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_101): - wire dest_reg_8: Ty24 @[instruction.rs 538:1] - match _match_arm_value_101.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_102): - connect dest_reg_8, _match_arm_value_102.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_103): - connect dest_reg_8, _match_arm_value_103.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_104): - connect dest_reg_8, _match_arm_value_104.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_7.value, dest_reg_8.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[3], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_88.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[3]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[3]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[3], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[3]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_105): - wire _bundle_literal_expr_159: Ty87 - connect _bundle_literal_expr_159.state, _match_arm_value_105 - connect _bundle_literal_expr_159.mop, _match_arm_value_88.mop - connect _bundle_literal_expr_159.src_ready_flags, _match_arm_value_88.src_ready_flags - connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_159) @[unit_base.rs 435:17] - wire _array_literal_expr_42: UInt<1>[3] - connect _array_literal_expr_42[0], UInt<1>(0h0) - connect _array_literal_expr_42[1], UInt<1>(0h0) - connect _array_literal_expr_42[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[4], _array_literal_expr_42 @[unit_base.rs 335:9] - connect in_flight_op_canceling[4], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[4], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[4], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[4]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_106): - wire dest_reg_9: Ty24 @[instruction.rs 538:1] - match _match_arm_value_106.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_107): - connect dest_reg_9, _match_arm_value_107.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_108): - connect dest_reg_9, _match_arm_value_108.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_109): - connect dest_reg_9, _match_arm_value_109.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_4: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_43: UInt<6>[3] - wire _bundle_literal_expr_160: Ty25 - wire _bundle_literal_expr_161: Ty23 - connect _bundle_literal_expr_161.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_160.unit_num, _bundle_literal_expr_161 - wire _bundle_literal_expr_162: Ty24 - connect _bundle_literal_expr_162.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_160.unit_out_reg, _bundle_literal_expr_162 - wire _cast_bundle_to_bits_expr_42: Ty57 - connect _cast_bundle_to_bits_expr_42.unit_num, _bundle_literal_expr_160.unit_num.adj_value - connect _cast_bundle_to_bits_expr_42.unit_out_reg, _bundle_literal_expr_160.unit_out_reg.value - wire _cast_to_bits_expr_50: UInt<6> - connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num) - connect _array_literal_expr_43[0], _cast_to_bits_expr_50 - wire _bundle_literal_expr_163: Ty25 - wire _bundle_literal_expr_164: Ty23 - connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164 - wire _bundle_literal_expr_165: Ty24 - connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165 - wire _cast_bundle_to_bits_expr_43: Ty57 - connect _cast_bundle_to_bits_expr_43.unit_num, _bundle_literal_expr_163.unit_num.adj_value - connect _cast_bundle_to_bits_expr_43.unit_out_reg, _bundle_literal_expr_163.unit_out_reg.value - wire _cast_to_bits_expr_51: UInt<6> - connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num) - connect _array_literal_expr_43[1], _cast_to_bits_expr_51 - wire _bundle_literal_expr_166: Ty25 - wire _bundle_literal_expr_167: Ty23 - connect _bundle_literal_expr_167.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_166.unit_num, _bundle_literal_expr_167 - wire _bundle_literal_expr_168: Ty24 - connect _bundle_literal_expr_168.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_166.unit_out_reg, _bundle_literal_expr_168 - wire _cast_bundle_to_bits_expr_44: Ty57 - connect _cast_bundle_to_bits_expr_44.unit_num, _bundle_literal_expr_166.unit_num.adj_value - connect _cast_bundle_to_bits_expr_44.unit_out_reg, _bundle_literal_expr_166.unit_out_reg.value - wire _cast_to_bits_expr_52: UInt<6> - connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num) - connect _array_literal_expr_43[2], _cast_to_bits_expr_52 - connect in_flight_op_src_regs_4, _array_literal_expr_43 @[unit_base.rs 356:13] - match _match_arm_value_106.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_110): - connect in_flight_op_src_regs_4[0], _match_arm_value_110.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_110.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[2], _match_arm_value_110.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_111): - connect in_flight_op_src_regs_4[0], _match_arm_value_111.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_111.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_112): - connect in_flight_op_src_regs_4[0], _match_arm_value_112.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_4[1], _match_arm_value_112.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[4], _match_arm_value_106.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_113): - wire _bundle_literal_expr_169: Ty25 - wire _bundle_literal_expr_170: Ty23 - connect _bundle_literal_expr_170.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_169.unit_num, _bundle_literal_expr_170 - connect _bundle_literal_expr_169.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_45: Ty57 - connect _cast_bundle_to_bits_expr_45.unit_num, _bundle_literal_expr_169.unit_num.adj_value - connect _cast_bundle_to_bits_expr_45.unit_out_reg, _bundle_literal_expr_169.unit_out_reg.value - wire _cast_to_bits_expr_53: UInt<6> - connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num) - when eq(_cast_to_bits_expr_53, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_171: Ty25 - wire _bundle_literal_expr_172: Ty23 - connect _bundle_literal_expr_172.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_171.unit_num, _bundle_literal_expr_172 - connect _bundle_literal_expr_171.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_46: Ty57 - connect _cast_bundle_to_bits_expr_46.unit_num, _bundle_literal_expr_171.unit_num.adj_value - connect _cast_bundle_to_bits_expr_46.unit_out_reg, _bundle_literal_expr_171.unit_out_reg.value - wire _cast_to_bits_expr_54: UInt<6> - connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num) - when eq(_cast_to_bits_expr_54, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_173: Ty25 - wire _bundle_literal_expr_174: Ty23 - connect _bundle_literal_expr_174.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_173.unit_num, _bundle_literal_expr_174 - connect _bundle_literal_expr_173.unit_out_reg, _match_arm_value_113.which - wire _cast_bundle_to_bits_expr_47: Ty57 - connect _cast_bundle_to_bits_expr_47.unit_num, _bundle_literal_expr_173.unit_num.adj_value - connect _cast_bundle_to_bits_expr_47.unit_out_reg, _bundle_literal_expr_173.unit_out_reg.value - wire _cast_to_bits_expr_55: UInt<6> - connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num) - when eq(_cast_to_bits_expr_55, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_114): - wire _bundle_literal_expr_175: Ty25 - wire _bundle_literal_expr_176: Ty23 - connect _bundle_literal_expr_176.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_175.unit_num, _bundle_literal_expr_176 - connect _bundle_literal_expr_175.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_48: Ty57 - connect _cast_bundle_to_bits_expr_48.unit_num, _bundle_literal_expr_175.unit_num.adj_value - connect _cast_bundle_to_bits_expr_48.unit_out_reg, _bundle_literal_expr_175.unit_out_reg.value - wire _cast_to_bits_expr_56: UInt<6> - connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_48.unit_out_reg, _cast_bundle_to_bits_expr_48.unit_num) - when eq(_cast_to_bits_expr_56, in_flight_op_src_regs_4[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_177: Ty25 - wire _bundle_literal_expr_178: Ty23 - connect _bundle_literal_expr_178.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_177.unit_num, _bundle_literal_expr_178 - connect _bundle_literal_expr_177.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_49: Ty57 - connect _cast_bundle_to_bits_expr_49.unit_num, _bundle_literal_expr_177.unit_num.adj_value - connect _cast_bundle_to_bits_expr_49.unit_out_reg, _bundle_literal_expr_177.unit_out_reg.value - wire _cast_to_bits_expr_57: UInt<6> - connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_49.unit_out_reg, _cast_bundle_to_bits_expr_49.unit_num) - when eq(_cast_to_bits_expr_57, in_flight_op_src_regs_4[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_179: Ty25 - wire _bundle_literal_expr_180: Ty23 - connect _bundle_literal_expr_180.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_179.unit_num, _bundle_literal_expr_180 - connect _bundle_literal_expr_179.unit_out_reg, _match_arm_value_114.which - wire _cast_bundle_to_bits_expr_50: Ty57 - connect _cast_bundle_to_bits_expr_50.unit_num, _bundle_literal_expr_179.unit_num.adj_value - connect _cast_bundle_to_bits_expr_50.unit_out_reg, _bundle_literal_expr_179.unit_out_reg.value - wire _cast_to_bits_expr_58: UInt<6> - connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num) - when eq(_cast_to_bits_expr_58, in_flight_op_src_regs_4[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[4][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_4: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_181: Ty69 - connect _bundle_literal_expr_181.which, dest_reg_9 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_181): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_4, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_115): - connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_116): - wire _bundle_literal_expr_182: Ty69 - connect _bundle_literal_expr_182.which, dest_reg_9 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_182): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_4, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_117): - connect cmp_eq_4, eq(_match_arm_value_116.which.value, _match_arm_value_117.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[4], cmp_eq_4 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_118): - when eq(dest_reg_9.value, _match_arm_value_118.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[4], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_5: Ty81 @[ready_valid.rs 30:27] - connect firing_data_5, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_5, execute_start.data @[ready_valid.rs 34:13] - match firing_data_5: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_119): - wire dest_reg_10: Ty24 @[instruction.rs 538:1] - match _match_arm_value_119.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_120): - connect dest_reg_10, _match_arm_value_120.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_121): - connect dest_reg_10, _match_arm_value_121.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_122): - connect dest_reg_10, _match_arm_value_122.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_9.value, dest_reg_10.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[4], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_106.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[4]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[4]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[4], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[4]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_123): - wire _bundle_literal_expr_183: Ty87 - connect _bundle_literal_expr_183.state, _match_arm_value_123 - connect _bundle_literal_expr_183.mop, _match_arm_value_106.mop - connect _bundle_literal_expr_183.src_ready_flags, _match_arm_value_106.src_ready_flags - connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_183) @[unit_base.rs 435:17] - wire _array_literal_expr_44: UInt<1>[3] - connect _array_literal_expr_44[0], UInt<1>(0h0) - connect _array_literal_expr_44[1], UInt<1>(0h0) - connect _array_literal_expr_44[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[5], _array_literal_expr_44 @[unit_base.rs 335:9] - connect in_flight_op_canceling[5], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[5], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[5], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[5]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_124): - wire dest_reg_11: Ty24 @[instruction.rs 538:1] - match _match_arm_value_124.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_125): - connect dest_reg_11, _match_arm_value_125.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_126): - connect dest_reg_11, _match_arm_value_126.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_127): - connect dest_reg_11, _match_arm_value_127.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_5: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_45: UInt<6>[3] - wire _bundle_literal_expr_184: Ty25 - wire _bundle_literal_expr_185: Ty23 - connect _bundle_literal_expr_185.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_184.unit_num, _bundle_literal_expr_185 - wire _bundle_literal_expr_186: Ty24 - connect _bundle_literal_expr_186.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_184.unit_out_reg, _bundle_literal_expr_186 - wire _cast_bundle_to_bits_expr_51: Ty57 - connect _cast_bundle_to_bits_expr_51.unit_num, _bundle_literal_expr_184.unit_num.adj_value - connect _cast_bundle_to_bits_expr_51.unit_out_reg, _bundle_literal_expr_184.unit_out_reg.value - wire _cast_to_bits_expr_59: UInt<6> - connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num) - connect _array_literal_expr_45[0], _cast_to_bits_expr_59 - wire _bundle_literal_expr_187: Ty25 - wire _bundle_literal_expr_188: Ty23 - connect _bundle_literal_expr_188.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_187.unit_num, _bundle_literal_expr_188 - wire _bundle_literal_expr_189: Ty24 - connect _bundle_literal_expr_189.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_187.unit_out_reg, _bundle_literal_expr_189 - wire _cast_bundle_to_bits_expr_52: Ty57 - connect _cast_bundle_to_bits_expr_52.unit_num, _bundle_literal_expr_187.unit_num.adj_value - connect _cast_bundle_to_bits_expr_52.unit_out_reg, _bundle_literal_expr_187.unit_out_reg.value - wire _cast_to_bits_expr_60: UInt<6> - connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num) - connect _array_literal_expr_45[1], _cast_to_bits_expr_60 - wire _bundle_literal_expr_190: Ty25 - wire _bundle_literal_expr_191: Ty23 - connect _bundle_literal_expr_191.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_190.unit_num, _bundle_literal_expr_191 - wire _bundle_literal_expr_192: Ty24 - connect _bundle_literal_expr_192.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_190.unit_out_reg, _bundle_literal_expr_192 - wire _cast_bundle_to_bits_expr_53: Ty57 - connect _cast_bundle_to_bits_expr_53.unit_num, _bundle_literal_expr_190.unit_num.adj_value - connect _cast_bundle_to_bits_expr_53.unit_out_reg, _bundle_literal_expr_190.unit_out_reg.value - wire _cast_to_bits_expr_61: UInt<6> - connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num) - connect _array_literal_expr_45[2], _cast_to_bits_expr_61 - connect in_flight_op_src_regs_5, _array_literal_expr_45 @[unit_base.rs 356:13] - match _match_arm_value_124.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_128): - connect in_flight_op_src_regs_5[0], _match_arm_value_128.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_128.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[2], _match_arm_value_128.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_129): - connect in_flight_op_src_regs_5[0], _match_arm_value_129.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_129.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_130): - connect in_flight_op_src_regs_5[0], _match_arm_value_130.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_5[1], _match_arm_value_130.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[5], _match_arm_value_124.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_131): - wire _bundle_literal_expr_193: Ty25 - wire _bundle_literal_expr_194: Ty23 - connect _bundle_literal_expr_194.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_193.unit_num, _bundle_literal_expr_194 - connect _bundle_literal_expr_193.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_54: Ty57 - connect _cast_bundle_to_bits_expr_54.unit_num, _bundle_literal_expr_193.unit_num.adj_value - connect _cast_bundle_to_bits_expr_54.unit_out_reg, _bundle_literal_expr_193.unit_out_reg.value - wire _cast_to_bits_expr_62: UInt<6> - connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_54.unit_out_reg, _cast_bundle_to_bits_expr_54.unit_num) - when eq(_cast_to_bits_expr_62, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_195: Ty25 - wire _bundle_literal_expr_196: Ty23 - connect _bundle_literal_expr_196.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_195.unit_num, _bundle_literal_expr_196 - connect _bundle_literal_expr_195.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_55: Ty57 - connect _cast_bundle_to_bits_expr_55.unit_num, _bundle_literal_expr_195.unit_num.adj_value - connect _cast_bundle_to_bits_expr_55.unit_out_reg, _bundle_literal_expr_195.unit_out_reg.value - wire _cast_to_bits_expr_63: UInt<6> - connect _cast_to_bits_expr_63, cat(_cast_bundle_to_bits_expr_55.unit_out_reg, _cast_bundle_to_bits_expr_55.unit_num) - when eq(_cast_to_bits_expr_63, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_197: Ty25 - wire _bundle_literal_expr_198: Ty23 - connect _bundle_literal_expr_198.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_197.unit_num, _bundle_literal_expr_198 - connect _bundle_literal_expr_197.unit_out_reg, _match_arm_value_131.which - wire _cast_bundle_to_bits_expr_56: Ty57 - connect _cast_bundle_to_bits_expr_56.unit_num, _bundle_literal_expr_197.unit_num.adj_value - connect _cast_bundle_to_bits_expr_56.unit_out_reg, _bundle_literal_expr_197.unit_out_reg.value - wire _cast_to_bits_expr_64: UInt<6> - connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_56.unit_out_reg, _cast_bundle_to_bits_expr_56.unit_num) - when eq(_cast_to_bits_expr_64, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_132): - wire _bundle_literal_expr_199: Ty25 - wire _bundle_literal_expr_200: Ty23 - connect _bundle_literal_expr_200.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_199.unit_num, _bundle_literal_expr_200 - connect _bundle_literal_expr_199.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_57: Ty57 - connect _cast_bundle_to_bits_expr_57.unit_num, _bundle_literal_expr_199.unit_num.adj_value - connect _cast_bundle_to_bits_expr_57.unit_out_reg, _bundle_literal_expr_199.unit_out_reg.value - wire _cast_to_bits_expr_65: UInt<6> - connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num) - when eq(_cast_to_bits_expr_65, in_flight_op_src_regs_5[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_201: Ty25 - wire _bundle_literal_expr_202: Ty23 - connect _bundle_literal_expr_202.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_201.unit_num, _bundle_literal_expr_202 - connect _bundle_literal_expr_201.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_58: Ty57 - connect _cast_bundle_to_bits_expr_58.unit_num, _bundle_literal_expr_201.unit_num.adj_value - connect _cast_bundle_to_bits_expr_58.unit_out_reg, _bundle_literal_expr_201.unit_out_reg.value - wire _cast_to_bits_expr_66: UInt<6> - connect _cast_to_bits_expr_66, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num) - when eq(_cast_to_bits_expr_66, in_flight_op_src_regs_5[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_203: Ty25 - wire _bundle_literal_expr_204: Ty23 - connect _bundle_literal_expr_204.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_203.unit_num, _bundle_literal_expr_204 - connect _bundle_literal_expr_203.unit_out_reg, _match_arm_value_132.which - wire _cast_bundle_to_bits_expr_59: Ty57 - connect _cast_bundle_to_bits_expr_59.unit_num, _bundle_literal_expr_203.unit_num.adj_value - connect _cast_bundle_to_bits_expr_59.unit_out_reg, _bundle_literal_expr_203.unit_out_reg.value - wire _cast_to_bits_expr_67: UInt<6> - connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num) - when eq(_cast_to_bits_expr_67, in_flight_op_src_regs_5[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[5][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_5: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_205: Ty69 - connect _bundle_literal_expr_205.which, dest_reg_11 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_205): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_5, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_133): - connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_134): - wire _bundle_literal_expr_206: Ty69 - connect _bundle_literal_expr_206.which, dest_reg_11 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_206): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_5, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_135): - connect cmp_eq_5, eq(_match_arm_value_134.which.value, _match_arm_value_135.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[5], cmp_eq_5 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_136): - when eq(dest_reg_11.value, _match_arm_value_136.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[5], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_6: Ty81 @[ready_valid.rs 30:27] - connect firing_data_6, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_6, execute_start.data @[ready_valid.rs 34:13] - match firing_data_6: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_137): - wire dest_reg_12: Ty24 @[instruction.rs 538:1] - match _match_arm_value_137.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_138): - connect dest_reg_12, _match_arm_value_138.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_139): - connect dest_reg_12, _match_arm_value_139.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_140): - connect dest_reg_12, _match_arm_value_140.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_11.value, dest_reg_12.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[5], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_124.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[5]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[5]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[5], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[5]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_141): - wire _bundle_literal_expr_207: Ty87 - connect _bundle_literal_expr_207.state, _match_arm_value_141 - connect _bundle_literal_expr_207.mop, _match_arm_value_124.mop - connect _bundle_literal_expr_207.src_ready_flags, _match_arm_value_124.src_ready_flags - connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_207) @[unit_base.rs 435:17] - wire _array_literal_expr_46: UInt<1>[3] - connect _array_literal_expr_46[0], UInt<1>(0h0) - connect _array_literal_expr_46[1], UInt<1>(0h0) - connect _array_literal_expr_46[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[6], _array_literal_expr_46 @[unit_base.rs 335:9] - connect in_flight_op_canceling[6], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[6], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[6], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[6]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_142): - wire dest_reg_13: Ty24 @[instruction.rs 538:1] - match _match_arm_value_142.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_143): - connect dest_reg_13, _match_arm_value_143.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_144): - connect dest_reg_13, _match_arm_value_144.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_145): - connect dest_reg_13, _match_arm_value_145.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_6: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_47: UInt<6>[3] - wire _bundle_literal_expr_208: Ty25 - wire _bundle_literal_expr_209: Ty23 - connect _bundle_literal_expr_209.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_208.unit_num, _bundle_literal_expr_209 - wire _bundle_literal_expr_210: Ty24 - connect _bundle_literal_expr_210.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_208.unit_out_reg, _bundle_literal_expr_210 - wire _cast_bundle_to_bits_expr_60: Ty57 - connect _cast_bundle_to_bits_expr_60.unit_num, _bundle_literal_expr_208.unit_num.adj_value - connect _cast_bundle_to_bits_expr_60.unit_out_reg, _bundle_literal_expr_208.unit_out_reg.value - wire _cast_to_bits_expr_68: UInt<6> - connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num) - connect _array_literal_expr_47[0], _cast_to_bits_expr_68 - wire _bundle_literal_expr_211: Ty25 - wire _bundle_literal_expr_212: Ty23 - connect _bundle_literal_expr_212.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_211.unit_num, _bundle_literal_expr_212 - wire _bundle_literal_expr_213: Ty24 - connect _bundle_literal_expr_213.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_211.unit_out_reg, _bundle_literal_expr_213 - wire _cast_bundle_to_bits_expr_61: Ty57 - connect _cast_bundle_to_bits_expr_61.unit_num, _bundle_literal_expr_211.unit_num.adj_value - connect _cast_bundle_to_bits_expr_61.unit_out_reg, _bundle_literal_expr_211.unit_out_reg.value - wire _cast_to_bits_expr_69: UInt<6> - connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_61.unit_out_reg, _cast_bundle_to_bits_expr_61.unit_num) - connect _array_literal_expr_47[1], _cast_to_bits_expr_69 - wire _bundle_literal_expr_214: Ty25 - wire _bundle_literal_expr_215: Ty23 - connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215 - wire _bundle_literal_expr_216: Ty24 - connect _bundle_literal_expr_216.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216 - wire _cast_bundle_to_bits_expr_62: Ty57 - connect _cast_bundle_to_bits_expr_62.unit_num, _bundle_literal_expr_214.unit_num.adj_value - connect _cast_bundle_to_bits_expr_62.unit_out_reg, _bundle_literal_expr_214.unit_out_reg.value - wire _cast_to_bits_expr_70: UInt<6> - connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_62.unit_out_reg, _cast_bundle_to_bits_expr_62.unit_num) - connect _array_literal_expr_47[2], _cast_to_bits_expr_70 - connect in_flight_op_src_regs_6, _array_literal_expr_47 @[unit_base.rs 356:13] - match _match_arm_value_142.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_146): - connect in_flight_op_src_regs_6[0], _match_arm_value_146.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_146.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[2], _match_arm_value_146.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_147): - connect in_flight_op_src_regs_6[0], _match_arm_value_147.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_147.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_148): - connect in_flight_op_src_regs_6[0], _match_arm_value_148.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_6[1], _match_arm_value_148.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[6], _match_arm_value_142.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_149): - wire _bundle_literal_expr_217: Ty25 - wire _bundle_literal_expr_218: Ty23 - connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218 - connect _bundle_literal_expr_217.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_63: Ty57 - connect _cast_bundle_to_bits_expr_63.unit_num, _bundle_literal_expr_217.unit_num.adj_value - connect _cast_bundle_to_bits_expr_63.unit_out_reg, _bundle_literal_expr_217.unit_out_reg.value - wire _cast_to_bits_expr_71: UInt<6> - connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_63.unit_out_reg, _cast_bundle_to_bits_expr_63.unit_num) - when eq(_cast_to_bits_expr_71, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_219: Ty25 - wire _bundle_literal_expr_220: Ty23 - connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220 - connect _bundle_literal_expr_219.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_64: Ty57 - connect _cast_bundle_to_bits_expr_64.unit_num, _bundle_literal_expr_219.unit_num.adj_value - connect _cast_bundle_to_bits_expr_64.unit_out_reg, _bundle_literal_expr_219.unit_out_reg.value - wire _cast_to_bits_expr_72: UInt<6> - connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_64.unit_out_reg, _cast_bundle_to_bits_expr_64.unit_num) - when eq(_cast_to_bits_expr_72, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_221: Ty25 - wire _bundle_literal_expr_222: Ty23 - connect _bundle_literal_expr_222.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_221.unit_num, _bundle_literal_expr_222 - connect _bundle_literal_expr_221.unit_out_reg, _match_arm_value_149.which - wire _cast_bundle_to_bits_expr_65: Ty57 - connect _cast_bundle_to_bits_expr_65.unit_num, _bundle_literal_expr_221.unit_num.adj_value - connect _cast_bundle_to_bits_expr_65.unit_out_reg, _bundle_literal_expr_221.unit_out_reg.value - wire _cast_to_bits_expr_73: UInt<6> - connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_65.unit_out_reg, _cast_bundle_to_bits_expr_65.unit_num) - when eq(_cast_to_bits_expr_73, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_150): - wire _bundle_literal_expr_223: Ty25 - wire _bundle_literal_expr_224: Ty23 - connect _bundle_literal_expr_224.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_223.unit_num, _bundle_literal_expr_224 - connect _bundle_literal_expr_223.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_66: Ty57 - connect _cast_bundle_to_bits_expr_66.unit_num, _bundle_literal_expr_223.unit_num.adj_value - connect _cast_bundle_to_bits_expr_66.unit_out_reg, _bundle_literal_expr_223.unit_out_reg.value - wire _cast_to_bits_expr_74: UInt<6> - connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_66.unit_out_reg, _cast_bundle_to_bits_expr_66.unit_num) - when eq(_cast_to_bits_expr_74, in_flight_op_src_regs_6[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_225: Ty25 - wire _bundle_literal_expr_226: Ty23 - connect _bundle_literal_expr_226.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_225.unit_num, _bundle_literal_expr_226 - connect _bundle_literal_expr_225.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_67: Ty57 - connect _cast_bundle_to_bits_expr_67.unit_num, _bundle_literal_expr_225.unit_num.adj_value - connect _cast_bundle_to_bits_expr_67.unit_out_reg, _bundle_literal_expr_225.unit_out_reg.value - wire _cast_to_bits_expr_75: UInt<6> - connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num) - when eq(_cast_to_bits_expr_75, in_flight_op_src_regs_6[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_227: Ty25 - wire _bundle_literal_expr_228: Ty23 - connect _bundle_literal_expr_228.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_227.unit_num, _bundle_literal_expr_228 - connect _bundle_literal_expr_227.unit_out_reg, _match_arm_value_150.which - wire _cast_bundle_to_bits_expr_68: Ty57 - connect _cast_bundle_to_bits_expr_68.unit_num, _bundle_literal_expr_227.unit_num.adj_value - connect _cast_bundle_to_bits_expr_68.unit_out_reg, _bundle_literal_expr_227.unit_out_reg.value - wire _cast_to_bits_expr_76: UInt<6> - connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_68.unit_out_reg, _cast_bundle_to_bits_expr_68.unit_num) - when eq(_cast_to_bits_expr_76, in_flight_op_src_regs_6[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[6][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_6: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_229: Ty69 - connect _bundle_literal_expr_229.which, dest_reg_13 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_229): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_6, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_151): - connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_152): - wire _bundle_literal_expr_230: Ty69 - connect _bundle_literal_expr_230.which, dest_reg_13 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_230): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_6, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_153): - connect cmp_eq_6, eq(_match_arm_value_152.which.value, _match_arm_value_153.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[6], cmp_eq_6 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_154): - when eq(dest_reg_13.value, _match_arm_value_154.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[6], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_7: Ty81 @[ready_valid.rs 30:27] - connect firing_data_7, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_7, execute_start.data @[ready_valid.rs 34:13] - match firing_data_7: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_155): - wire dest_reg_14: Ty24 @[instruction.rs 538:1] - match _match_arm_value_155.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_156): - connect dest_reg_14, _match_arm_value_156.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_157): - connect dest_reg_14, _match_arm_value_157.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_158): - connect dest_reg_14, _match_arm_value_158.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_13.value, dest_reg_14.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[6], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_142.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[6]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[6]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[6], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[6]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_159): - wire _bundle_literal_expr_231: Ty87 - connect _bundle_literal_expr_231.state, _match_arm_value_159 - connect _bundle_literal_expr_231.mop, _match_arm_value_142.mop - connect _bundle_literal_expr_231.src_ready_flags, _match_arm_value_142.src_ready_flags - connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_231) @[unit_base.rs 435:17] - wire _array_literal_expr_48: UInt<1>[3] - connect _array_literal_expr_48[0], UInt<1>(0h0) - connect _array_literal_expr_48[1], UInt<1>(0h0) - connect _array_literal_expr_48[2], UInt<1>(0h0) - connect in_flight_op_next_src_ready_flags[7], _array_literal_expr_48 @[unit_base.rs 335:9] - connect in_flight_op_canceling[7], UInt<1>(0h0) @[unit_base.rs 339:9] - connect in_flight_op_execute_starting[7], UInt<1>(0h0) @[unit_base.rs 340:9] - connect in_flight_op_execute_ending[7], UInt<1>(0h0) @[unit_base.rs 341:9] - match in_flight_ops[7]: @[unit_base.rs 343:9] - HdlNone: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 453:13] - HdlSome(_match_arm_value_160): - wire dest_reg_15: Ty24 @[instruction.rs 538:1] - match _match_arm_value_160.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_161): - connect dest_reg_15, _match_arm_value_161.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_162): - connect dest_reg_15, _match_arm_value_162.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_163): - connect dest_reg_15, _match_arm_value_163.alu_common.common.dest @[instruction.rs 538:1] - wire in_flight_op_src_regs_7: UInt<6>[3] @[unit_base.rs 353:17] - wire _array_literal_expr_49: UInt<6>[3] - wire _bundle_literal_expr_232: Ty25 - wire _bundle_literal_expr_233: Ty23 - connect _bundle_literal_expr_233.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_232.unit_num, _bundle_literal_expr_233 - wire _bundle_literal_expr_234: Ty24 - connect _bundle_literal_expr_234.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_232.unit_out_reg, _bundle_literal_expr_234 - wire _cast_bundle_to_bits_expr_69: Ty57 - connect _cast_bundle_to_bits_expr_69.unit_num, _bundle_literal_expr_232.unit_num.adj_value - connect _cast_bundle_to_bits_expr_69.unit_out_reg, _bundle_literal_expr_232.unit_out_reg.value - wire _cast_to_bits_expr_77: UInt<6> - connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_69.unit_out_reg, _cast_bundle_to_bits_expr_69.unit_num) - connect _array_literal_expr_49[0], _cast_to_bits_expr_77 - wire _bundle_literal_expr_235: Ty25 - wire _bundle_literal_expr_236: Ty23 - connect _bundle_literal_expr_236.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_235.unit_num, _bundle_literal_expr_236 - wire _bundle_literal_expr_237: Ty24 - connect _bundle_literal_expr_237.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_235.unit_out_reg, _bundle_literal_expr_237 - wire _cast_bundle_to_bits_expr_70: Ty57 - connect _cast_bundle_to_bits_expr_70.unit_num, _bundle_literal_expr_235.unit_num.adj_value - connect _cast_bundle_to_bits_expr_70.unit_out_reg, _bundle_literal_expr_235.unit_out_reg.value - wire _cast_to_bits_expr_78: UInt<6> - connect _cast_to_bits_expr_78, cat(_cast_bundle_to_bits_expr_70.unit_out_reg, _cast_bundle_to_bits_expr_70.unit_num) - connect _array_literal_expr_49[1], _cast_to_bits_expr_78 - wire _bundle_literal_expr_238: Ty25 - wire _bundle_literal_expr_239: Ty23 - connect _bundle_literal_expr_239.adj_value, tail(UInt<64>(0h0), 62) - connect _bundle_literal_expr_238.unit_num, _bundle_literal_expr_239 - wire _bundle_literal_expr_240: Ty24 - connect _bundle_literal_expr_240.value, tail(UInt<8>(0h0), 4) - connect _bundle_literal_expr_238.unit_out_reg, _bundle_literal_expr_240 - wire _cast_bundle_to_bits_expr_71: Ty57 - connect _cast_bundle_to_bits_expr_71.unit_num, _bundle_literal_expr_238.unit_num.adj_value - connect _cast_bundle_to_bits_expr_71.unit_out_reg, _bundle_literal_expr_238.unit_out_reg.value - wire _cast_to_bits_expr_79: UInt<6> - connect _cast_to_bits_expr_79, cat(_cast_bundle_to_bits_expr_71.unit_out_reg, _cast_bundle_to_bits_expr_71.unit_num) - connect _array_literal_expr_49[2], _cast_to_bits_expr_79 - connect in_flight_op_src_regs_7, _array_literal_expr_49 @[unit_base.rs 356:13] - match _match_arm_value_160.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_164): - connect in_flight_op_src_regs_7[0], _match_arm_value_164.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_164.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[2], _match_arm_value_164.alu_common.common.src[2] @[instruction.rs 36:13] - AddSubI(_match_arm_value_165): - connect in_flight_op_src_regs_7[0], _match_arm_value_165.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_165.alu_common.common.src[1] @[instruction.rs 36:13] - Logical(_match_arm_value_166): - connect in_flight_op_src_regs_7[0], _match_arm_value_166.alu_common.common.src[0] @[instruction.rs 36:13] - connect in_flight_op_src_regs_7[1], _match_arm_value_166.alu_common.common.src[1] @[instruction.rs 36:13] - connect in_flight_op_next_src_ready_flags[7], _match_arm_value_160.src_ready_flags @[unit_base.rs 362:13] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[0]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_167): - wire _bundle_literal_expr_241: Ty25 - wire _bundle_literal_expr_242: Ty23 - connect _bundle_literal_expr_242.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_241.unit_num, _bundle_literal_expr_242 - connect _bundle_literal_expr_241.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_72: Ty57 - connect _cast_bundle_to_bits_expr_72.unit_num, _bundle_literal_expr_241.unit_num.adj_value - connect _cast_bundle_to_bits_expr_72.unit_out_reg, _bundle_literal_expr_241.unit_out_reg.value - wire _cast_to_bits_expr_80: UInt<6> - connect _cast_to_bits_expr_80, cat(_cast_bundle_to_bits_expr_72.unit_out_reg, _cast_bundle_to_bits_expr_72.unit_num) - when eq(_cast_to_bits_expr_80, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_243: Ty25 - wire _bundle_literal_expr_244: Ty23 - connect _bundle_literal_expr_244.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_243.unit_num, _bundle_literal_expr_244 - connect _bundle_literal_expr_243.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_73: Ty57 - connect _cast_bundle_to_bits_expr_73.unit_num, _bundle_literal_expr_243.unit_num.adj_value - connect _cast_bundle_to_bits_expr_73.unit_out_reg, _bundle_literal_expr_243.unit_out_reg.value - wire _cast_to_bits_expr_81: UInt<6> - connect _cast_to_bits_expr_81, cat(_cast_bundle_to_bits_expr_73.unit_out_reg, _cast_bundle_to_bits_expr_73.unit_num) - when eq(_cast_to_bits_expr_81, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_245: Ty25 - wire _bundle_literal_expr_246: Ty23 - connect _bundle_literal_expr_246.adj_value, tail(UInt<64>(0h1), 62) - connect _bundle_literal_expr_245.unit_num, _bundle_literal_expr_246 - connect _bundle_literal_expr_245.unit_out_reg, _match_arm_value_167.which - wire _cast_bundle_to_bits_expr_74: Ty57 - connect _cast_bundle_to_bits_expr_74.unit_num, _bundle_literal_expr_245.unit_num.adj_value - connect _cast_bundle_to_bits_expr_74.unit_out_reg, _bundle_literal_expr_245.unit_out_reg.value - wire _cast_to_bits_expr_82: UInt<6> - connect _cast_to_bits_expr_82, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num) - when eq(_cast_to_bits_expr_82, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29] - match unit_to_reg_alloc.unit_forwarding_info.unit_output_writes[1]: @[unit_base.rs 369:17] - HdlNone: - skip - HdlSome(_match_arm_value_168): - wire _bundle_literal_expr_247: Ty25 - wire _bundle_literal_expr_248: Ty23 - connect _bundle_literal_expr_248.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_247.unit_num, _bundle_literal_expr_248 - connect _bundle_literal_expr_247.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_75: Ty57 - connect _cast_bundle_to_bits_expr_75.unit_num, _bundle_literal_expr_247.unit_num.adj_value - connect _cast_bundle_to_bits_expr_75.unit_out_reg, _bundle_literal_expr_247.unit_out_reg.value - wire _cast_to_bits_expr_83: UInt<6> - connect _cast_to_bits_expr_83, cat(_cast_bundle_to_bits_expr_75.unit_out_reg, _cast_bundle_to_bits_expr_75.unit_num) - when eq(_cast_to_bits_expr_83, in_flight_op_src_regs_7[0]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][0], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_249: Ty25 - wire _bundle_literal_expr_250: Ty23 - connect _bundle_literal_expr_250.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_249.unit_num, _bundle_literal_expr_250 - connect _bundle_literal_expr_249.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_76: Ty57 - connect _cast_bundle_to_bits_expr_76.unit_num, _bundle_literal_expr_249.unit_num.adj_value - connect _cast_bundle_to_bits_expr_76.unit_out_reg, _bundle_literal_expr_249.unit_out_reg.value - wire _cast_to_bits_expr_84: UInt<6> - connect _cast_to_bits_expr_84, cat(_cast_bundle_to_bits_expr_76.unit_out_reg, _cast_bundle_to_bits_expr_76.unit_num) - when eq(_cast_to_bits_expr_84, in_flight_op_src_regs_7[1]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][1], UInt<1>(0h1) @[unit_base.rs 383:29] - wire _bundle_literal_expr_251: Ty25 - wire _bundle_literal_expr_252: Ty23 - connect _bundle_literal_expr_252.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_251.unit_num, _bundle_literal_expr_252 - connect _bundle_literal_expr_251.unit_out_reg, _match_arm_value_168.which - wire _cast_bundle_to_bits_expr_77: Ty57 - connect _cast_bundle_to_bits_expr_77.unit_num, _bundle_literal_expr_251.unit_num.adj_value - connect _cast_bundle_to_bits_expr_77.unit_out_reg, _bundle_literal_expr_251.unit_out_reg.value - wire _cast_to_bits_expr_85: UInt<6> - connect _cast_to_bits_expr_85, cat(_cast_bundle_to_bits_expr_77.unit_out_reg, _cast_bundle_to_bits_expr_77.unit_num) - when eq(_cast_to_bits_expr_85, in_flight_op_src_regs_7[2]): @[unit_base.rs 382:25] - connect in_flight_op_next_src_ready_flags[7][2], UInt<1>(0h1) @[unit_base.rs 383:29] - wire cmp_eq_7: UInt<1> @[enum_.rs 370:22] - match unit_to_reg_alloc.cancel_input: @[enum_.rs 372:9] - HdlNone: - wire _bundle_literal_expr_253: Ty69 - connect _bundle_literal_expr_253.which, dest_reg_15 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_253): @[enum_.rs 384:17] - HdlNone: - connect cmp_eq_7, UInt<1>(0h1) @[enum_.rs 386:32] - HdlSome(_match_arm_value_169): - connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 385:35] - HdlSome(_match_arm_value_170): - wire _bundle_literal_expr_254: Ty69 - connect _bundle_literal_expr_254.which, dest_reg_15 - match {|HdlNone, HdlSome: Ty69|}(HdlSome, _bundle_literal_expr_254): @[enum_.rs 376:17] - HdlNone: - connect cmp_eq_7, UInt<1>(0h0) @[enum_.rs 378:32] - HdlSome(_match_arm_value_171): - connect cmp_eq_7, eq(_match_arm_value_170.which.value, _match_arm_value_171.which.value) @[enum_.rs 377:37] - connect in_flight_op_canceling[7], cmp_eq_7 @[unit_base.rs 392:13] - match execute_end: @[unit_base.rs 401:13] - HdlNone: - skip - HdlSome(_match_arm_value_172): - when eq(dest_reg_15.value, _match_arm_value_172.unit_output.which.value): @[unit_base.rs 405:17] - connect in_flight_op_execute_ending[7], UInt<1>(0h1) @[unit_base.rs 406:21] - wire firing_data_8: Ty81 @[ready_valid.rs 30:27] - connect firing_data_8, {|HdlNone, HdlSome: Ty80|}(HdlNone) @[ready_valid.rs 31:9] - when execute_start.ready: @[ready_valid.rs 33:9] - connect firing_data_8, execute_start.data @[ready_valid.rs 34:13] - match firing_data_8: @[unit_base.rs 410:13] - HdlNone: - skip - HdlSome(_match_arm_value_173): - wire dest_reg_16: Ty24 @[instruction.rs 538:1] - match _match_arm_value_173.mop: @[instruction.rs 538:1] - AddSub(_match_arm_value_174): - connect dest_reg_16, _match_arm_value_174.alu_common.common.dest @[instruction.rs 538:1] - AddSubI(_match_arm_value_175): - connect dest_reg_16, _match_arm_value_175.alu_common.common.dest @[instruction.rs 538:1] - Logical(_match_arm_value_176): - connect dest_reg_16, _match_arm_value_176.alu_common.common.dest @[instruction.rs 538:1] - when eq(dest_reg_15.value, dest_reg_16.value): @[unit_base.rs 412:17] - connect in_flight_op_execute_starting[7], UInt<1>(0h1) @[unit_base.rs 413:21] - match _match_arm_value_160.state: @[unit_base.rs 426:13] - Ready: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Ready)) @[unit_base.rs 129:17] - Running: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(Running)) @[unit_base.rs 129:17] - CanceledAndRunning: - when in_flight_op_canceling[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_starting[7]: @[unit_base.rs 114:17] - when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - else when in_flight_op_execute_ending[7]: @[unit_base.rs 114:17] - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlNone) @[unit_base.rs 129:17] - else: - connect in_flight_op_next_state[7], {|HdlNone, HdlSome: Ty86|}(HdlSome, {|Ready, Running, CanceledAndRunning|}(CanceledAndRunning)) @[unit_base.rs 129:17] - match in_flight_op_next_state[7]: @[unit_base.rs 434:13] - HdlNone: - connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 447:17] - HdlSome(_match_arm_value_177): - wire _bundle_literal_expr_255: Ty87 - connect _bundle_literal_expr_255.state, _match_arm_value_177 - connect _bundle_literal_expr_255.mop, _match_arm_value_160.mop - connect _bundle_literal_expr_255.src_ready_flags, _match_arm_value_160.src_ready_flags - connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_255) @[unit_base.rs 435:17] -", - }; + // #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + // assert_export_firrtl! { + // m => + // options: ExportOptions { + // simplify_enums: None, + // ..ExportOptions::default() + // }, + // "/test/reg_alloc.fir": "", + // }; // let sim_debug = format!("{sim:#?}"); // println!("#######\n{sim_debug}\n#######"); // if sim_debug != include_str!("expected/reg_alloc.txt") {

P int_fp $end +$scope struct flags $end +$var wire 1 ?P pwr_ca_x86_cf $end +$var wire 1 @P pwr_ca32_x86_af $end +$var wire 1 AP pwr_ov_x86_of $end +$var wire 1 BP pwr_ov32_x86_df $end +$var wire 1 CP pwr_cr_lt_x86_sf $end +$var wire 1 DP pwr_cr_gt_x86_pf $end +$var wire 1 EP pwr_cr_eq_x86_zf $end +$var wire 1 FP pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 GP int_fp $end +$scope struct flags $end +$var wire 1 HP pwr_ca_x86_cf $end +$var wire 1 IP pwr_ca32_x86_af $end +$var wire 1 JP pwr_ov_x86_of $end +$var wire 1 KP pwr_ov32_x86_df $end +$var wire 1 LP pwr_cr_lt_x86_sf $end +$var wire 1 MP pwr_cr_gt_x86_pf $end +$var wire 1 NP pwr_cr_eq_x86_zf $end +$var wire 1 OP pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 PP int_fp $end +$scope struct flags $end +$var wire 1 QP pwr_ca_x86_cf $end +$var wire 1 RP pwr_ca32_x86_af $end +$var wire 1 SP pwr_ov_x86_of $end +$var wire 1 TP pwr_ov32_x86_df $end +$var wire 1 UP pwr_cr_lt_x86_sf $end +$var wire 1 VP pwr_cr_gt_x86_pf $end +$var wire 1 WP pwr_cr_eq_x86_zf $end +$var wire 1 XP pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_13 $end +$var wire 4 YP value $end +$upscope $end +$scope struct dest_reg_14 $end +$var wire 4 ZP value $end +$upscope $end +$scope struct in_flight_op_src_regs_6 $end +$var wire 6 [P \[0] $end +$var wire 6 \P \[1] $end +$var wire 6 ]P \[2] $end +$upscope $end +$var wire 1 ^P cmp_eq_13 $end +$var wire 1 _P cmp_eq_14 $end +$scope struct firing_data_8 $end +$var string 1 `P \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 aP \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 bP prefix_pad $end +$scope struct dest $end +$var wire 4 cP value $end +$upscope $end +$scope struct src $end +$var wire 6 dP \[0] $end +$var wire 6 eP \[1] $end +$var wire 6 fP \[2] $end +$upscope $end +$var wire 25 gP imm_low $end +$var wire 1 hP imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 iP output_integer_mode $end +$upscope $end +$var wire 1 jP invert_src0 $end +$var wire 1 kP src1_is_carry_in $end +$var wire 1 lP invert_carry_in $end +$var wire 1 mP add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 nP prefix_pad $end +$scope struct dest $end +$var wire 4 oP value $end +$upscope $end +$scope struct src $end +$var wire 6 pP \[0] $end +$var wire 6 qP \[1] $end +$var wire 6 rP \[2] $end +$upscope $end +$var wire 25 sP imm_low $end +$var wire 1 tP imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 uP output_integer_mode $end +$upscope $end +$var wire 1 vP invert_src0 $end +$var wire 1 wP src1_is_carry_in $end +$var wire 1 xP invert_carry_in $end +$var wire 1 yP add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 zP prefix_pad $end +$scope struct dest $end +$var wire 4 {P value $end +$upscope $end +$scope struct src $end +$var wire 6 |P \[0] $end +$var wire 6 }P \[1] $end +$var wire 6 ~P \[2] $end +$upscope $end +$var wire 25 !Q imm_low $end +$var wire 1 "Q imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 #Q output_integer_mode $end +$upscope $end +$var wire 4 $Q lut $end +$upscope $end +$upscope $end +$var wire 64 %Q pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 &Q int_fp $end +$scope struct flags $end +$var wire 1 'Q pwr_ca_x86_cf $end +$var wire 1 (Q pwr_ca32_x86_af $end +$var wire 1 )Q pwr_ov_x86_of $end +$var wire 1 *Q pwr_ov32_x86_df $end +$var wire 1 +Q pwr_cr_lt_x86_sf $end +$var wire 1 ,Q pwr_cr_gt_x86_pf $end +$var wire 1 -Q pwr_cr_eq_x86_zf $end +$var wire 1 .Q pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 /Q int_fp $end +$scope struct flags $end +$var wire 1 0Q pwr_ca_x86_cf $end +$var wire 1 1Q pwr_ca32_x86_af $end +$var wire 1 2Q pwr_ov_x86_of $end +$var wire 1 3Q pwr_ov32_x86_df $end +$var wire 1 4Q pwr_cr_lt_x86_sf $end +$var wire 1 5Q pwr_cr_gt_x86_pf $end +$var wire 1 6Q pwr_cr_eq_x86_zf $end +$var wire 1 7Q pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 8Q int_fp $end +$scope struct flags $end +$var wire 1 9Q pwr_ca_x86_cf $end +$var wire 1 :Q pwr_ca32_x86_af $end +$var wire 1 ;Q pwr_ov_x86_of $end +$var wire 1 Q pwr_cr_gt_x86_pf $end +$var wire 1 ?Q pwr_cr_eq_x86_zf $end +$var wire 1 @Q pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_15 $end +$var wire 4 AQ value $end +$upscope $end +$scope struct dest_reg_16 $end +$var wire 4 BQ value $end +$upscope $end +$scope struct in_flight_op_src_regs_7 $end +$var wire 6 CQ \[0] $end +$var wire 6 DQ \[1] $end +$var wire 6 EQ \[2] $end +$upscope $end +$var wire 1 FQ cmp_eq_15 $end +$var wire 1 GQ cmp_eq_16 $end +$scope struct firing_data_9 $end +$var string 1 HQ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 IQ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 JQ prefix_pad $end +$scope struct dest $end +$var wire 4 KQ value $end +$upscope $end +$scope struct src $end +$var wire 6 LQ \[0] $end +$var wire 6 MQ \[1] $end +$var wire 6 NQ \[2] $end +$upscope $end +$var wire 25 OQ imm_low $end +$var wire 1 PQ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 QQ output_integer_mode $end +$upscope $end +$var wire 1 RQ invert_src0 $end +$var wire 1 SQ src1_is_carry_in $end +$var wire 1 TQ invert_carry_in $end +$var wire 1 UQ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 VQ prefix_pad $end +$scope struct dest $end +$var wire 4 WQ value $end +$upscope $end +$scope struct src $end +$var wire 6 XQ \[0] $end +$var wire 6 YQ \[1] $end +$var wire 6 ZQ \[2] $end +$upscope $end +$var wire 25 [Q imm_low $end +$var wire 1 \Q imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ]Q output_integer_mode $end +$upscope $end +$var wire 1 ^Q invert_src0 $end +$var wire 1 _Q src1_is_carry_in $end +$var wire 1 `Q invert_carry_in $end +$var wire 1 aQ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 bQ prefix_pad $end +$scope struct dest $end +$var wire 4 cQ value $end +$upscope $end +$scope struct src $end +$var wire 6 dQ \[0] $end +$var wire 6 eQ \[1] $end +$var wire 6 fQ \[2] $end +$upscope $end +$var wire 25 gQ imm_low $end +$var wire 1 hQ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 iQ output_integer_mode $end +$upscope $end +$var wire 4 jQ lut $end +$upscope $end +$upscope $end +$var wire 64 kQ pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 lQ int_fp $end +$scope struct flags $end +$var wire 1 mQ pwr_ca_x86_cf $end +$var wire 1 nQ pwr_ca32_x86_af $end +$var wire 1 oQ pwr_ov_x86_of $end +$var wire 1 pQ pwr_ov32_x86_df $end +$var wire 1 qQ pwr_cr_lt_x86_sf $end +$var wire 1 rQ pwr_cr_gt_x86_pf $end +$var wire 1 sQ pwr_cr_eq_x86_zf $end +$var wire 1 tQ pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 uQ int_fp $end +$scope struct flags $end +$var wire 1 vQ pwr_ca_x86_cf $end +$var wire 1 wQ pwr_ca32_x86_af $end +$var wire 1 xQ pwr_ov_x86_of $end +$var wire 1 yQ pwr_ov32_x86_df $end +$var wire 1 zQ pwr_cr_lt_x86_sf $end +$var wire 1 {Q pwr_cr_gt_x86_pf $end +$var wire 1 |Q pwr_cr_eq_x86_zf $end +$var wire 1 }Q pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 ~Q int_fp $end +$scope struct flags $end +$var wire 1 !R pwr_ca_x86_cf $end +$var wire 1 "R pwr_ca32_x86_af $end +$var wire 1 #R pwr_ov_x86_of $end +$var wire 1 $R pwr_ov32_x86_df $end +$var wire 1 %R pwr_cr_lt_x86_sf $end +$var wire 1 &R pwr_cr_gt_x86_pf $end +$var wire 1 'R pwr_cr_eq_x86_zf $end +$var wire 1 (R pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_17 $end +$var wire 4 )R value $end +$upscope $end +$upscope $end +$scope struct firing_data $end +$var string 1 cS \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 dS \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 eS prefix_pad $end +$scope struct dest $end +$var wire 4 fS value $end +$upscope $end +$scope struct src $end +$var wire 6 gS \[0] $end +$var wire 6 hS \[1] $end +$var wire 6 iS \[2] $end +$upscope $end +$var wire 25 jS imm_low $end +$var wire 1 kS imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 lS output_integer_mode $end +$upscope $end +$var wire 1 mS invert_src0 $end +$var wire 1 nS src1_is_carry_in $end +$var wire 1 oS invert_carry_in $end +$var wire 1 pS add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 qS prefix_pad $end +$scope struct dest $end +$var wire 4 rS value $end +$upscope $end +$scope struct src $end +$var wire 6 sS \[0] $end +$var wire 6 tS \[1] $end +$var wire 6 uS \[2] $end +$upscope $end +$var wire 25 vS imm_low $end +$var wire 1 wS imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 xS output_integer_mode $end +$upscope $end +$var wire 1 yS invert_src0 $end +$var wire 1 zS src1_is_carry_in $end +$var wire 1 {S invert_carry_in $end +$var wire 1 |S add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }S prefix_pad $end +$scope struct dest $end +$var wire 4 ~S value $end +$upscope $end +$scope struct src $end +$var wire 6 !T \[0] $end +$var wire 6 "T \[1] $end +$var wire 6 #T \[2] $end +$upscope $end +$var wire 25 $T imm_low $end +$var wire 1 %T imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &T output_integer_mode $end +$upscope $end +$var wire 4 'T lut $end +$upscope $end +$upscope $end +$var wire 64 (T pc $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 )T int_fp $end +$scope struct flags $end +$var wire 1 *T pwr_ca_x86_cf $end +$var wire 1 +T pwr_ca32_x86_af $end +$var wire 1 ,T pwr_ov_x86_of $end +$var wire 1 -T pwr_ov32_x86_df $end +$var wire 1 .T pwr_cr_lt_x86_sf $end +$var wire 1 /T pwr_cr_gt_x86_pf $end +$var wire 1 0T pwr_cr_eq_x86_zf $end +$var wire 1 1T pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 2T int_fp $end +$scope struct flags $end +$var wire 1 3T pwr_ca_x86_cf $end +$var wire 1 4T pwr_ca32_x86_af $end +$var wire 1 5T pwr_ov_x86_of $end +$var wire 1 6T pwr_ov32_x86_df $end +$var wire 1 7T pwr_cr_lt_x86_sf $end +$var wire 1 8T pwr_cr_gt_x86_pf $end +$var wire 1 9T pwr_cr_eq_x86_zf $end +$var wire 1 :T pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 ;T int_fp $end +$scope struct flags $end +$var wire 1 T pwr_ov_x86_of $end +$var wire 1 ?T pwr_ov32_x86_df $end +$var wire 1 @T pwr_cr_lt_x86_sf $end +$var wire 1 AT pwr_cr_gt_x86_pf $end +$var wire 1 BT pwr_cr_eq_x86_zf $end +$var wire 1 CT pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 DT carry_in_before_inversion $end +$var wire 64 ET src1 $end +$var wire 1 FT carry_in $end +$var wire 64 GT src0 $end +$var wire 64 HT pc_or_zero $end +$var wire 64 IT sum $end +$var wire 1 JT carry_at_4 $end +$var wire 1 KT carry_at_7 $end +$var wire 1 LT carry_at_8 $end +$var wire 1 MT carry_at_15 $end +$var wire 1 NT carry_at_16 $end +$var wire 1 OT carry_at_31 $end +$var wire 1 PT carry_at_32 $end +$var wire 1 QT carry_at_63 $end +$var wire 1 RT carry_at_64 $end +$var wire 64 ST int_fp $end +$var wire 1 TT x86_cf $end +$var wire 1 UT x86_af $end +$var wire 1 VT x86_of $end +$var wire 1 WT x86_sf $end +$var wire 1 XT x86_pf $end +$var wire 1 YT x86_zf $end +$var wire 1 ZT pwr_ca $end +$var wire 1 [T pwr_ca32 $end +$var wire 1 \T pwr_ov $end +$var wire 1 ]T pwr_ov32 $end +$var wire 1 ^T pwr_cr_lt $end +$var wire 1 _T pwr_cr_eq $end +$var wire 1 `T pwr_cr_gt $end +$var wire 1 aT pwr_so $end +$scope struct flags $end +$var wire 1 bT pwr_ca_x86_cf $end +$var wire 1 cT pwr_ca32_x86_af $end +$var wire 1 dT pwr_ov_x86_of $end +$var wire 1 eT pwr_ov32_x86_df $end +$var wire 1 fT pwr_cr_lt_x86_sf $end +$var wire 1 gT pwr_cr_gt_x86_pf $end +$var wire 1 hT pwr_cr_eq_x86_zf $end +$var wire 1 iT pwr_so $end +$upscope $end +$var wire 1 jT carry_in_before_inversion_2 $end +$var wire 64 kT src1_2 $end +$var wire 1 lT carry_in_2 $end +$var wire 64 mT src0_2 $end +$var wire 64 nT pc_or_zero_2 $end +$var wire 64 oT sum_2 $end +$var wire 1 pT carry_at_4_2 $end +$var wire 1 qT carry_at_7_2 $end +$var wire 1 rT carry_at_8_2 $end +$var wire 1 sT carry_at_15_2 $end +$var wire 1 tT carry_at_16_2 $end +$var wire 1 uT carry_at_31_2 $end +$var wire 1 vT carry_at_32_2 $end +$var wire 1 wT carry_at_63_2 $end +$var wire 1 xT carry_at_64_2 $end +$var wire 64 yT int_fp_2 $end +$var wire 1 zT x86_cf_2 $end +$var wire 1 {T x86_af_2 $end +$var wire 1 |T x86_of_2 $end +$var wire 1 }T x86_sf_2 $end +$var wire 1 ~T x86_pf_2 $end +$var wire 1 !U x86_zf_2 $end +$var wire 1 "U pwr_ca_2 $end +$var wire 1 #U pwr_ca32_2 $end +$var wire 1 $U pwr_ov_2 $end +$var wire 1 %U pwr_ov32_2 $end +$var wire 1 &U pwr_cr_lt_2 $end +$var wire 1 'U pwr_cr_eq_2 $end +$var wire 1 (U pwr_cr_gt_2 $end +$var wire 1 )U pwr_so_2 $end +$scope struct flags_2 $end +$var wire 1 *U pwr_ca_x86_cf $end +$var wire 1 +U pwr_ca32_x86_af $end +$var wire 1 ,U pwr_ov_x86_of $end +$var wire 1 -U pwr_ov32_x86_df $end +$var wire 1 .U pwr_cr_lt_x86_sf $end +$var wire 1 /U pwr_cr_gt_x86_pf $end +$var wire 1 0U pwr_cr_eq_x86_zf $end +$var wire 1 1U pwr_so $end +$upscope $end +$upscope $end +$scope struct unit_1_free_regs_tracker $end +$scope struct cd $end +$var wire 1 iV clk $end +$var wire 1 jV rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 kV \$tag $end +$var wire 4 lV HdlSome $end +$upscope $end +$var wire 1 mV ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 nV \$tag $end +$var wire 4 oV HdlSome $end +$upscope $end +$var wire 1 pV ready $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_free_regs_tracker_2 $end +$scope struct cd $end +$var wire 1 ~U clk $end +$var wire 1 !V rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 "V \$tag $end +$var wire 4 #V HdlSome $end +$upscope $end +$var wire 1 $V ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 %V \$tag $end +$var wire 4 &V HdlSome $end +$upscope $end +$var wire 1 'V ready $end +$upscope $end +$upscope $end +$scope struct allocated_reg $end +$var reg 1 (V \[0] $end +$var reg 1 )V \[1] $end +$var reg 1 *V \[2] $end +$var reg 1 +V \[3] $end +$var reg 1 ,V \[4] $end +$var reg 1 -V \[5] $end +$var reg 1 .V \[6] $end +$var reg 1 /V \[7] $end +$var reg 1 0V \[8] $end +$var reg 1 1V \[9] $end +$var reg 1 2V \[10] $end +$var reg 1 3V \[11] $end +$var reg 1 4V \[12] $end +$var reg 1 5V \[13] $end +$var reg 1 6V \[14] $end +$var reg 1 7V \[15] $end +$upscope $end +$scope struct firing_data $end +$var string 1 8V \$tag $end +$var wire 4 9V HdlSome $end +$upscope $end +$var wire 1 :V reduced_count_0_2 $end +$var wire 1 ;V reduced_count_overflowed_0_2 $end +$scope struct reduced_alloc_nums_0_2 $end +$var wire 1 V reduced_count_overflowed_2_4 $end +$scope struct reduced_alloc_nums_2_4 $end +$var wire 1 ?V \[0] $end +$upscope $end +$var wire 1 @V reduced_count_0_4 $end +$var wire 1 AV reduced_count_overflowed_0_4 $end +$scope struct reduced_alloc_nums_0_4 $end +$var wire 2 BV \[0] $end +$upscope $end +$var wire 1 CV reduced_count_4_6 $end +$var wire 1 DV reduced_count_overflowed_4_6 $end +$scope struct reduced_alloc_nums_4_6 $end +$var wire 1 EV \[0] $end +$upscope $end +$var wire 1 FV reduced_count_6_8 $end +$var wire 1 GV reduced_count_overflowed_6_8 $end +$scope struct reduced_alloc_nums_6_8 $end +$var wire 1 HV \[0] $end +$upscope $end +$var wire 1 IV reduced_count_4_8 $end +$var wire 1 JV reduced_count_overflowed_4_8 $end +$scope struct reduced_alloc_nums_4_8 $end +$var wire 2 KV \[0] $end +$upscope $end +$var wire 1 LV reduced_count_0_8 $end +$var wire 1 MV reduced_count_overflowed_0_8 $end +$scope struct reduced_alloc_nums_0_8 $end +$var wire 3 NV \[0] $end +$upscope $end +$var wire 1 OV reduced_count_8_10 $end +$var wire 1 PV reduced_count_overflowed_8_10 $end +$scope struct reduced_alloc_nums_8_10 $end +$var wire 1 QV \[0] $end +$upscope $end +$var wire 1 RV reduced_count_10_12 $end +$var wire 1 SV reduced_count_overflowed_10_12 $end +$scope struct reduced_alloc_nums_10_12 $end +$var wire 1 TV \[0] $end +$upscope $end +$var wire 1 UV reduced_count_8_12 $end +$var wire 1 VV reduced_count_overflowed_8_12 $end +$scope struct reduced_alloc_nums_8_12 $end +$var wire 2 WV \[0] $end +$upscope $end +$var wire 1 XV reduced_count_12_14 $end +$var wire 1 YV reduced_count_overflowed_12_14 $end +$scope struct reduced_alloc_nums_12_14 $end +$var wire 1 ZV \[0] $end +$upscope $end +$var wire 1 [V reduced_count_14_16 $end +$var wire 1 \V reduced_count_overflowed_14_16 $end +$scope struct reduced_alloc_nums_14_16 $end +$var wire 1 ]V \[0] $end +$upscope $end +$var wire 1 ^V reduced_count_12_16 $end +$var wire 1 _V reduced_count_overflowed_12_16 $end +$scope struct reduced_alloc_nums_12_16 $end +$var wire 2 `V \[0] $end +$upscope $end +$var wire 1 aV reduced_count_8_16 $end +$var wire 1 bV reduced_count_overflowed_8_16 $end +$scope struct reduced_alloc_nums_8_16 $end +$var wire 3 cV \[0] $end +$upscope $end +$var wire 1 dV reduced_count_0_16 $end +$var wire 1 eV reduced_count_overflowed_0_16 $end +$scope struct reduced_alloc_nums_0_16 $end +$var wire 4 fV \[0] $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 gV \$tag $end +$var wire 4 hV HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out_5 $end +$var string 1 qV \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 rV \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 sV prefix_pad $end +$scope struct dest $end +$var wire 4 tV value $end +$upscope $end +$scope struct src $end +$var wire 6 uV \[0] $end +$var wire 6 vV \[1] $end +$var wire 6 wV \[2] $end +$upscope $end +$var wire 25 xV imm_low $end +$var wire 1 yV imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 zV output_integer_mode $end +$upscope $end +$var wire 1 {V invert_src0 $end +$var wire 1 |V src1_is_carry_in $end +$var wire 1 }V invert_carry_in $end +$var wire 1 ~V add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 !W prefix_pad $end +$scope struct dest $end +$var wire 4 "W value $end +$upscope $end +$scope struct src $end +$var wire 6 #W \[0] $end +$var wire 6 $W \[1] $end +$var wire 6 %W \[2] $end +$upscope $end +$var wire 25 &W imm_low $end +$var wire 1 'W imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 (W output_integer_mode $end +$upscope $end +$var wire 1 )W invert_src0 $end +$var wire 1 *W src1_is_carry_in $end +$var wire 1 +W invert_carry_in $end +$var wire 1 ,W add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 -W prefix_pad $end +$scope struct dest $end +$var wire 4 .W value $end +$upscope $end +$scope struct src $end +$var wire 6 /W \[0] $end +$var wire 6 0W \[1] $end +$var wire 6 1W \[2] $end +$upscope $end +$var wire 25 2W imm_low $end +$var wire 1 3W imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 4W output_integer_mode $end +$upscope $end +$var wire 4 5W lut $end +$upscope $end +$upscope $end +$var wire 64 6W pc $end +$upscope $end +$upscope $end +$scope struct and_then_out_6 $end +$var string 1 7W \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 8W \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 9W prefix_pad $end +$scope struct dest $end +$var wire 4 :W value $end +$upscope $end +$scope struct src $end +$var wire 6 ;W \[0] $end +$var wire 6 W imm_low $end +$var wire 1 ?W imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 @W output_integer_mode $end +$upscope $end +$var wire 1 AW invert_src0 $end +$var wire 1 BW src1_is_carry_in $end +$var wire 1 CW invert_carry_in $end +$var wire 1 DW add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 EW prefix_pad $end +$scope struct dest $end +$var wire 4 FW value $end +$upscope $end +$scope struct src $end +$var wire 6 GW \[0] $end +$var wire 6 HW \[1] $end +$var wire 6 IW \[2] $end +$upscope $end +$var wire 25 JW imm_low $end +$var wire 1 KW imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 LW output_integer_mode $end +$upscope $end +$var wire 1 MW invert_src0 $end +$var wire 1 NW src1_is_carry_in $end +$var wire 1 OW invert_carry_in $end +$var wire 1 PW add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 QW prefix_pad $end +$scope struct dest $end +$var wire 4 RW value $end +$upscope $end +$scope struct src $end +$var wire 6 SW \[0] $end +$var wire 6 TW \[1] $end +$var wire 6 UW \[2] $end +$upscope $end +$var wire 25 VW imm_low $end +$var wire 1 WW imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 XW output_integer_mode $end +$upscope $end +$var wire 4 YW lut $end +$upscope $end +$upscope $end +$var wire 64 ZW pc $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_3 $end +$var string 1 [W \$tag $end +$scope struct HdlSome $end +$var string 1 \W \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ]W prefix_pad $end +$scope struct dest $end +$var wire 4 ^W value $end +$upscope $end +$scope struct src $end +$var wire 6 _W \[0] $end +$var wire 6 `W \[1] $end +$var wire 6 aW \[2] $end +$upscope $end +$var wire 25 bW imm_low $end +$var wire 1 cW imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 dW output_integer_mode $end +$upscope $end +$var wire 1 eW invert_src0 $end +$var wire 1 fW src1_is_carry_in $end +$var wire 1 gW invert_carry_in $end +$var wire 1 hW add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 iW prefix_pad $end +$scope struct dest $end +$var wire 4 jW value $end +$upscope $end +$scope struct src $end +$var wire 6 kW \[0] $end +$var wire 6 lW \[1] $end +$var wire 6 mW \[2] $end +$upscope $end +$var wire 25 nW imm_low $end +$var wire 1 oW imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 pW output_integer_mode $end +$upscope $end +$var wire 1 qW invert_src0 $end +$var wire 1 rW src1_is_carry_in $end +$var wire 1 sW invert_carry_in $end +$var wire 1 tW add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 uW prefix_pad $end +$scope struct dest $end +$var wire 4 vW value $end +$upscope $end +$scope struct src $end +$var wire 6 wW \[0] $end +$var wire 6 xW \[1] $end +$var wire 6 yW \[2] $end +$upscope $end +$var wire 25 zW imm_low $end +$var wire 1 {W imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 |W output_integer_mode $end +$upscope $end +$var wire 4 }W lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct and_then_out_7 $end +$var string 1 ~W \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 !X \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 "X prefix_pad $end +$scope struct dest $end +$var wire 4 #X value $end +$upscope $end +$scope struct src $end +$var wire 6 $X \[0] $end +$var wire 6 %X \[1] $end +$var wire 6 &X \[2] $end +$upscope $end +$var wire 25 'X imm_low $end +$var wire 1 (X imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 )X output_integer_mode $end +$upscope $end +$var wire 1 *X invert_src0 $end +$var wire 1 +X src1_is_carry_in $end +$var wire 1 ,X invert_carry_in $end +$var wire 1 -X add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 .X prefix_pad $end +$scope struct dest $end +$var wire 4 /X value $end +$upscope $end +$scope struct src $end +$var wire 6 0X \[0] $end +$var wire 6 1X \[1] $end +$var wire 6 2X \[2] $end +$upscope $end +$var wire 25 3X imm_low $end +$var wire 1 4X imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 5X output_integer_mode $end +$upscope $end +$var wire 1 6X invert_src0 $end +$var wire 1 7X src1_is_carry_in $end +$var wire 1 8X invert_carry_in $end +$var wire 1 9X add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 :X prefix_pad $end +$scope struct dest $end +$var wire 4 ;X value $end +$upscope $end +$scope struct src $end +$var wire 6 X \[2] $end +$upscope $end +$var wire 25 ?X imm_low $end +$var wire 1 @X imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 AX output_integer_mode $end +$upscope $end +$var wire 4 BX lut $end +$upscope $end +$upscope $end +$var wire 64 CX pc $end +$upscope $end +$upscope $end +$scope struct and_then_out_8 $end +$var string 1 DX \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 EX \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 FX prefix_pad $end +$scope struct dest $end +$var wire 4 GX value $end +$upscope $end +$scope struct src $end +$var wire 6 HX \[0] $end +$var wire 6 IX \[1] $end +$var wire 6 JX \[2] $end +$upscope $end +$var wire 25 KX imm_low $end +$var wire 1 LX imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 MX output_integer_mode $end +$upscope $end +$var wire 1 NX invert_src0 $end +$var wire 1 OX src1_is_carry_in $end +$var wire 1 PX invert_carry_in $end +$var wire 1 QX add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 RX prefix_pad $end +$scope struct dest $end +$var wire 4 SX value $end +$upscope $end +$scope struct src $end +$var wire 6 TX \[0] $end +$var wire 6 UX \[1] $end +$var wire 6 VX \[2] $end +$upscope $end +$var wire 25 WX imm_low $end +$var wire 1 XX imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 YX output_integer_mode $end +$upscope $end +$var wire 1 ZX invert_src0 $end +$var wire 1 [X src1_is_carry_in $end +$var wire 1 \X invert_carry_in $end +$var wire 1 ]X add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ^X prefix_pad $end +$scope struct dest $end +$var wire 4 _X value $end +$upscope $end +$scope struct src $end +$var wire 6 `X \[0] $end +$var wire 6 aX \[1] $end +$var wire 6 bX \[2] $end +$upscope $end +$var wire 25 cX imm_low $end +$var wire 1 dX imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 eX output_integer_mode $end +$upscope $end +$var wire 4 fX lut $end +$upscope $end +$upscope $end +$var wire 64 gX pc $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_4 $end +$var string 1 hX \$tag $end +$scope struct HdlSome $end +$var string 1 iX \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 jX prefix_pad $end +$scope struct dest $end +$var wire 4 kX value $end +$upscope $end +$scope struct src $end +$var wire 6 lX \[0] $end +$var wire 6 mX \[1] $end +$var wire 6 nX \[2] $end +$upscope $end +$var wire 25 oX imm_low $end +$var wire 1 pX imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 qX output_integer_mode $end +$upscope $end +$var wire 1 rX invert_src0 $end +$var wire 1 sX src1_is_carry_in $end +$var wire 1 tX invert_carry_in $end +$var wire 1 uX add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 vX prefix_pad $end +$scope struct dest $end +$var wire 4 wX value $end +$upscope $end +$scope struct src $end +$var wire 6 xX \[0] $end +$var wire 6 yX \[1] $end +$var wire 6 zX \[2] $end +$upscope $end +$var wire 25 {X imm_low $end +$var wire 1 |X imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 }X output_integer_mode $end +$upscope $end +$var wire 1 ~X invert_src0 $end +$var wire 1 !Y src1_is_carry_in $end +$var wire 1 "Y invert_carry_in $end +$var wire 1 #Y add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 $Y prefix_pad $end +$scope struct dest $end +$var wire 4 %Y value $end +$upscope $end +$scope struct src $end +$var wire 6 &Y \[0] $end +$var wire 6 'Y \[1] $end +$var wire 6 (Y \[2] $end +$upscope $end +$var wire 25 )Y imm_low $end +$var wire 1 *Y imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 +Y output_integer_mode $end +$upscope $end +$var wire 4 ,Y lut $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b0 TP -b0 7S -b0 UP -b0 8S -b0 VP -b0 9S -b0 WP -b0 :S -b0 XP -b0 ;S -b0 YP -b0 S -b0 \P -b0 ?S -b0 ]P -b0 @S -b0 ^P -b0 AS -b0 _P -b0 BS -b0 `P -b0 CS -b0 aP -b0 DS -b0 bP -b0 ES -b0 cP -b0 FS -b0 dP -b0 GS -b0 eP -b0 HS -b0 fP -b0 IS -b0 gP -b0 JS -b0 hP -b0 KS -b0 iP -b0 LS -b0 jP -b0 MS -b0 kP -b0 NS -b0 lP -b0 OS -b0 mP -b0 PS -b0 nP -b0 QS -b0 oP -b0 RS -b0 pP -b0 SS -b0 qP -b0 TS -b0 rP -b0 US -b0 sP -b0 VS -b0 tP -b0 WS -b0 uP -b0 XS -b0 vP -b0 YS -b0 wP -b0 ZS -b0 xP -b0 [S -b0 yP -b0 \S -b0 zP -b0 ]S -b0 {P -b0 ^S -b0 |P -b0 _S -b0 }P -b0 `S -b0 ~P -b0 aS -b0 !Q -b0 bS -b0 "Q -b0 cS -b0 #Q -b0 dS -b0 $Q -b0 eS -b0 %Q -b0 fS -b0 &Q -b0 gS -b0 'Q -b0 hS -b0 (Q -b0 iS -b0 )Q -b0 jS -b0 *Q -b0 kS -b0 +Q -b0 lS -b0 ,Q -b0 mS -b0 -Q -b0 nS -b0 .Q -b0 oS -b0 /Q -b0 pS -b0 0Q -b0 qS -b0 1Q -b0 rS -b0 2Q -b0 sS -b0 3Q -b0 tS -b0 4Q -b0 uS -b0 5Q -b0 vS -b0 6Q -b0 wS -b0 7Q -b0 xS -b0 8Q -b0 yS -b0 9Q -b0 zS -b0 :Q -b0 {S -b0 ;Q -b0 |S -b0 Q -b0 !T -b0 ?Q -b0 "T -b0 @Q -b0 #T -b0 AQ -b0 $T -b0 BQ -b0 %T -b0 CQ -b0 &T -b0 DQ -b0 'T -b0 EQ -b0 (T -b0 FQ -b0 )T -b0 GQ -b0 *T -b0 HQ -b0 +T -b0 IQ -b0 ,T -b0 JQ -b0 -T -b0 KQ -b0 .T -b0 LQ -b0 /T -b0 MQ -b0 0T -b0 NQ -b0 1T -b0 OQ -b0 2T -b0 PQ -b0 3T -b0 QQ -b0 4T -b0 RQ -b0 5T -b0 SQ -b0 6T -b0 TQ -b0 7T -b0 UQ -b0 8T -b0 VQ -b0 9T -b0 WQ -b0 :T -b0 XQ -b0 ;T -b0 YQ -b0 T -b0 \Q -b0 ?T -b0 ]Q -b0 @T -b0 ^Q -b0 AT -b0 _Q -b0 BT -b0 `Q -b0 CT -b0 aQ -b0 DT -b0 bQ -b0 ET -b0 cQ -b0 FT -b0 dQ -b0 GT -b0 eQ -b0 HT -b0 fQ -b0 IT -b0 gQ -b0 JT -b0 hQ -b0 KT -b0 iQ -b0 LT -b0 jQ -b0 MT -b0 kQ -b0 NT -b0 lQ -b0 OT -b0 mQ -b0 PT -b0 nQ -b0 QT -b0 oQ -b0 RT -b0 pQ -b0 ST -b0 qQ -b0 TT -b0 rQ -b0 UT -b0 sQ -b0 VT -b0 tQ -b0 WT -b0 uQ -b0 XT -b0 vQ -b0 YT -b0 wQ -b0 ZT -b0 xQ -b0 [T -b0 yQ -b0 \T -b0 zQ -b0 ]T -b0 {Q -b0 ^T -b0 |Q -b0 _T -b0 }Q -b0 `T -b0 ~Q -b0 aT -b0 !R -b0 bT -b0 "R -b0 cT -b0 #R -b0 dT -b0 $R -b0 eT -b0 %R -b0 fT -b0 &R -b0 gT -b0 'R -b0 hT -b0 (R -b0 iT -b0 )R -b0 jT -b0 *R -b0 kT -b0 +R -b0 lT -b0 ,R -b0 mT -b0 -R -b0 nT -b0 .R -b0 oT -b0 /R -b0 pT -b0 0R -b0 qT -b0 1R -b0 rT -b0 2R -b0 sT -b0 3R -b0 tT -b0 4R -b0 uT -b0 5R -b0 vT -b0 6R -b0 wT -b0 7R -b0 xT -b0 8R -b0 yT -b0 9R -b0 zT -b0 :R -b0 {T -b0 ;R -b0 |T -b0 R -b0 !U -b0 ?R -b0 "U -b0 @R -b0 #U -b0 AR -b0 $U -b0 BR -b0 %U -b0 CR -b0 &U -b0 DR -b0 'U -b0 ER -b0 (U -b0 FR -b0 )U -b0 GR -b0 *U -b0 HR -b0 +U -b0 IR -b0 ,U -b0 JR -b0 -U -b0 KR -b0 .U -b0 LR -b0 /U -b0 MR -b0 0U -b0 NR -b0 1U -b0 OR -b0 2U -b0 PR -b0 3U -b0 QR -b0 4U -b0 RR -b0 5U -b0 SR -b0 6U -b0 TR -b0 7U -b0 UR -b0 8U -b0 VR -b0 9U -b0 WR -b0 :U -b0 XR -b0 ;U -b0 YR -b0 U -b0 \R -b0 ?U -b0 ]R -b0 @U -b0 ^R -b0 AU -b0 _R -b0 BU -b0 `R -b0 CU -b0 aR -b0 DU -b0 bR -b0 EU -b0 cR -b0 FU -b0 dR -b0 GU -b0 eR -b0 HU -b0 fR -b0 IU -b0 gR -b0 JU -b0 hR -b0 KU -b0 iR -b0 LU -b0 jR -b0 MU -b0 kR -b0 NU -b0 lR -b0 OU -b0 mR -b0 PU -b0 nR -b0 QU -b0 oR -b0 RU -b0 pR -b0 SU -b0 qR -b0 TU -b0 rR -b0 UU -b0 sR -b0 VU -b0 tR -b0 WU -b0 uR -b0 XU -b0 vR -b0 YU -b0 wR -b0 ZU -b0 xR -b0 [U -b0 yR -b0 \U -b0 zR -b0 ]U -b0 {R -b0 ^U -b0 |R -b0 _U -b0 }R -b0 `U -b0 ~R -b0 aU -b0 !S -b0 bU -b0 "S -b0 cU -b0 #S -b0 dU -b0 $S -b0 eU -b0 %S -b0 fU -b0 &S -b0 gU -b0 'S -b0 hU -b0 (S -b0 iU -b0 )S -b0 jU -b0 *S -b0 kU -b0 +S -b0 lU -b0 ,S -b0 mU -b0 -S -b0 nU -b0 .S -b0 oU -b0 /S -b0 pU -b0 0S -b0 qU -b0 1S -b0 rU -b0 2S -b0 sU -b0 3S -b0 tU -b0 4S -b0 uU -b0 5S -b0 vU -b0 6S -b0 wU -b0 xU -b0 zU -b0 yU -b0 {U +b0 /c +0?c +0Oc +0_c +0oc +0!d +01d +0Ad +0Qd +b0 0c +0@c +0Pc +0`c +0pc +0"d +02d +0Bd +0Rd +b0 1c +0Ac +0Qc +0ac +0qc +0#d +03d +0Cd +0Sd +b0 2c +0Bc +0Rc +0bc +0rc +0$d +04d +0Dd +0Td +b0 3c +0Cc +0Sc +0cc +0sc +0%d +05d +0Ed +0Ud +b0 4c +0Dc +0Tc +0dc +0tc +0&d +06d +0Fd +0Vd +b0 5c +0Ec +0Uc +0ec +0uc +0'd +07d +0Gd +0Wd +b0 6c +0Fc +0Vc +0fc +0vc +0(d +08d +0Hd +0Xd +b0 7c +0Gc +0Wc +0gc +0wc +0)d +09d +0Id +0Yd +b0 8c +0Hc +0Xc +0hc +0xc +0*d +0:d +0Jd +0Zd +b0 9c +0Ic +0Yc +0ic +0yc +0+d +0;d +0Kd +0[d +b0 :c +0Jc +0Zc +0jc +0zc +0,d +0d +0Nd +0^d +b0 =c +0Mc +0]c +0mc +0}c +0/d +0?d +0Od +0_d +b0 >c +0Nc +0^c +0nc +0~c +00d +0@d +0Pd +0`d +b0 [a +0ka +0{a +0-b +0=b +0Mb +0]b +0mb +0}b +b0 \a +0la +0|a +0.b +0>b +0Nb +0^b +0nb +0~b +b0 ]a +0ma +0}a +0/b +0?b +0Ob +0_b +0ob +0!c +b0 ^a +0na +0~a +00b +0@b +0Pb +0`b +0pb +0"c +b0 _a +0oa +0!b +01b +0Ab +0Qb +0ab +0qb +0#c +b0 `a +0pa +0"b +02b +0Bb +0Rb +0bb +0rb +0$c +b0 aa +0qa +0#b +03b +0Cb +0Sb +0cb +0sb +0%c +b0 ba +0ra +0$b +04b +0Db +0Tb +0db +0tb +0&c +b0 ca +0sa +0%b +05b +0Eb +0Ub +0eb +0ub +0'c +b0 da +0ta +0&b +06b +0Fb +0Vb +0fb +0vb +0(c +b0 ea +0ua +0'b +07b +0Gb +0Wb +0gb +0wb +0)c +b0 fa +0va +0(b +08b +0Hb +0Xb +0hb +0xb +0*c +b0 ga +0wa +0)b +09b +0Ib +0Yb +0ib +0yb +0+c +b0 ha +0xa +0*b +0:b +0Jb +0Zb +0jb +0zb +0,c +b0 ia +0ya +0+b +0;b +0Kb +0[b +0kb +0{b +0-c +b0 ja +0za +0,b +0Y +b0 !\ +b0 ?Y +b0 "\ +b0 @Y +b0 #\ +b0 AY +b0 $\ +b0 BY +b0 %\ +b0 CY +b0 &\ +b0 DY +b0 '\ +b0 EY +b0 (\ +b0 FY +b0 )\ +b0 GY +b0 *\ +b0 HY +b0 +\ +b0 IY +b0 ,\ +b0 JY +b0 -\ +b0 KY +b0 .\ +b0 LY +b0 /\ +b0 MY +b0 0\ +b0 NY +b0 1\ +b0 OY +b0 2\ +b0 PY +b0 3\ +b0 QY +b0 4\ +b0 RY +b0 5\ +b0 SY +b0 6\ +b0 TY +b0 7\ +b0 UY +b0 8\ +b0 VY +b0 9\ +b0 WY +b0 :\ +b0 XY +b0 ;\ +b0 YY +b0 <\ +b0 ZY +b0 =\ +b0 [Y +b0 >\ +b0 \Y +b0 ?\ +b0 ]Y +b0 @\ +b0 ^Y +b0 A\ +b0 _Y +b0 B\ +b0 `Y +b0 C\ +b0 aY +b0 D\ +b0 bY +b0 E\ +b0 cY +b0 F\ +b0 dY +b0 G\ +b0 eY +b0 H\ +b0 fY +b0 I\ +b0 gY +b0 J\ +b0 hY +b0 K\ +b0 iY +b0 L\ +b0 jY +b0 M\ +b0 kY +b0 N\ +b0 lY +b0 O\ +b0 mY +b0 P\ +b0 nY +b0 Q\ +b0 oY +b0 R\ +b0 pY +b0 S\ +b0 qY +b0 T\ +b0 rY +b0 U\ +b0 sY +b0 V\ +b0 tY +b0 W\ +b0 uY +b0 X\ +b0 vY +b0 Y\ +b0 wY +b0 Z\ +b0 xY +b0 [\ +b0 yY +b0 \\ +b0 zY +b0 ]\ +b0 {Y +b0 ^\ +b0 |Y +b0 _\ +b0 }Y +b0 `\ +b0 ~Y +b0 a\ +b0 !Z +b0 b\ +b0 "Z +b0 c\ +b0 #Z +b0 d\ +b0 $Z +b0 e\ +b0 %Z +b0 f\ +b0 &Z +b0 g\ +b0 'Z +b0 h\ +b0 (Z +b0 i\ +b0 )Z +b0 j\ +b0 *Z +b0 k\ +b0 +Z +b0 l\ +b0 ,Z +b0 m\ +b0 -Z +b0 n\ +b0 .Z +b0 o\ +b0 /Z +b0 p\ +b0 0Z +b0 q\ +b0 1Z +b0 r\ +b0 2Z +b0 s\ +b0 3Z +b0 t\ +b0 4Z +b0 u\ +b0 5Z +b0 v\ +b0 6Z +b0 w\ +b0 7Z +b0 x\ +b0 8Z +b0 y\ +b0 9Z +b0 z\ +b0 :Z +b0 {\ +b0 ;Z +b0 |\ +b0 Z +b0 !] +b0 ?Z +b0 "] +b0 @Z +b0 #] +b0 AZ +b0 $] +b0 BZ +b0 %] +b0 CZ +b0 &] +b0 DZ +b0 '] +b0 EZ +b0 (] +b0 FZ +b0 )] +b0 GZ +b0 *] +b0 HZ +b0 +] +b0 IZ +b0 ,] +b0 JZ +b0 -] +b0 KZ +b0 .] +b0 LZ +b0 /] +b0 MZ +b0 0] +b0 NZ +b0 1] +b0 OZ +b0 2] +b0 PZ +b0 3] +b0 QZ +b0 4] +b0 RZ +b0 5] +b0 SZ +b0 6] +b0 TZ +b0 7] +b0 UZ +b0 8] +b0 VZ +b0 9] +b0 WZ +b0 :] +b0 XZ +b0 ;] +b0 YZ +b0 <] +b0 ZZ +b0 =] +b0 [Z +b0 >] +b0 \Z +b0 ?] +b0 ]Z +b0 @] +b0 ^Z +b0 A] +b0 _Z +b0 B] +b0 `Z +b0 C] +b0 aZ +b0 D] +b0 bZ +b0 E] +b0 cZ +b0 F] +b0 dZ +b0 G] +b0 eZ +b0 H] +b0 fZ +b0 I] +b0 gZ +b0 J] +b0 hZ +b0 K] +b0 iZ +b0 L] +b0 jZ +b0 M] +b0 kZ +b0 N] +b0 lZ +b0 O] +b0 mZ +b0 P] +b0 nZ +b0 Q] +b0 oZ +b0 R] +b0 pZ +b0 S] +b0 qZ +b0 T] +b0 rZ +b0 U] +b0 sZ +b0 V] +b0 tZ +b0 W] +b0 uZ +b0 X] +b0 vZ +b0 Y] +b0 wZ +b0 Z] +b0 xZ +b0 [] +b0 yZ +b0 \] +b0 zZ +b0 ]] +b0 {Z +b0 ^] +b0 |Z +b0 _] +b0 }Z +b0 `] +b0 ~Z +b0 a] +b0 ![ +b0 b] +b0 "[ +b0 c] +b0 #[ +b0 d] +b0 $[ +b0 e] +b0 %[ +b0 f] +b0 &[ +b0 g] +b0 '[ +b0 h] +b0 ([ +b0 i] +b0 )[ +b0 j] +b0 *[ +b0 k] +b0 +[ +b0 l] +b0 ,[ +b0 m] +b0 -[ +b0 n] +b0 .[ +b0 o] +b0 /[ +b0 p] +b0 0[ +b0 q] +b0 1[ +b0 r] +b0 2[ +b0 s] +b0 3[ +b0 t] +b0 4[ +b0 u] +b0 5[ +b0 v] +b0 6[ +b0 w] +b0 7[ +b0 x] +b0 8[ +b0 y] +b0 9[ +b0 z] +b0 :[ +b0 {] +b0 ;[ +b0 |] +b0 <[ +b0 }] +b0 =[ +b0 ~] +b0 >[ +b0 !^ +b0 ?[ +b0 "^ +b0 @[ +b0 #^ +b0 A[ +b0 $^ +b0 B[ +b0 %^ +b0 C[ +b0 &^ +b0 D[ +b0 '^ +b0 E[ +b0 (^ +b0 F[ +b0 )^ +b0 G[ +b0 *^ +b0 H[ +b0 +^ +b0 I[ +b0 ,^ +b0 J[ +b0 -^ +b0 K[ +b0 .^ +b0 L[ +b0 /^ +b0 M[ +b0 0^ +b0 N[ +b0 1^ +b0 O[ +b0 2^ +b0 P[ +b0 3^ +b0 Q[ +b0 4^ +b0 R[ +b0 5^ +b0 S[ +b0 6^ +b0 T[ +b0 7^ +b0 U[ +b0 8^ +b0 V[ +b0 9^ +b0 W[ +b0 :^ +b0 X[ +b0 ;^ +b0 Y[ +b0 <^ +b0 Z[ +b0 =^ +b0 [[ +b0 >^ +b0 \[ +b0 ?^ +b0 ][ +b0 @^ +b0 ^[ +b0 A^ +b0 _[ +b0 B^ +b0 `[ +b0 C^ +b0 a[ +b0 D^ +b0 b[ +b0 E^ +b0 c[ +b0 F^ +b0 d[ +b0 G^ +b0 e[ +b0 H^ +b0 f[ +b0 I^ +b0 g[ +b0 J^ +b0 h[ +b0 K^ +b0 i[ +b0 L^ +b0 j[ +b0 M^ +b0 k[ +b0 N^ +b0 l[ +b0 O^ +b0 m[ +b0 P^ +b0 U^ +0e^ +0u^ +0'_ +07_ +0G_ +0W_ +0g_ +0w_ +b0 V^ +0f^ +0v^ +0(_ +08_ +0H_ +0X_ +0h_ +0x_ +b0 W^ +0g^ +0w^ +0)_ +09_ +0I_ +0Y_ +0i_ +0y_ +b0 X^ +0h^ +0x^ +0*_ +0:_ +0J_ +0Z_ +0j_ +0z_ +b0 Y^ +0i^ +0y^ +0+_ +0;_ +0K_ +0[_ +0k_ +0{_ +b0 Z^ +0j^ +0z^ +0,_ +0<_ +0L_ +0\_ +0l_ +0|_ +b0 [^ +0k^ +0{^ +0-_ +0=_ +0M_ +0]_ +0m_ +0}_ +b0 \^ +0l^ +0|^ +0._ +0>_ +0N_ +0^_ +0n_ +0~_ +b0 ]^ +0m^ +0}^ +0/_ +0?_ +0O_ +0__ +0o_ +0!` +b0 ^^ +0n^ +0~^ +00_ +0@_ +0P_ +0`_ +0p_ +0"` +b0 _^ +0o^ +0!_ +01_ +0A_ +0Q_ +0a_ +0q_ +0#` +b0 `^ +0p^ +0"_ +02_ +0B_ +0R_ +0b_ +0r_ +0$` +b0 a^ +0q^ +0#_ +03_ +0C_ +0S_ +0c_ +0s_ +0%` +b0 b^ +0r^ +0$_ +04_ +0D_ +0T_ +0d_ +0t_ +0&` +b0 c^ +0s^ +0%_ +05_ +0E_ +0U_ +0e_ +0u_ +0'` +b0 d^ +0t^ +0&_ +06_ +0F_ +0V_ +0f_ +0v_ +0(` +b0 )` +09` +0I` +0Y` +0i` +0y` +0+a +0;a +0Ka +b0 *` +0:` +0J` +0Z` +0j` +0z` +0,a +0a +0Na +b0 -` +0=` +0M` +0]` +0m` +0}` +0/a +0?a +0Oa +b0 .` +0>` +0N` +0^` +0n` +0~` +00a +0@a +0Pa +b0 /` +0?` +0O` +0_` +0o` +0!a +01a +0Aa +0Qa +b0 0` +0@` +0P` +0`` +0p` +0"a +02a +0Ba +0Ra +b0 1` +0A` +0Q` +0a` +0q` +0#a +03a +0Ca +0Sa +b0 2` +0B` +0R` +0b` +0r` +0$a +04a +0Da +0Ta +b0 3` +0C` +0S` +0c` +0s` +0%a +05a +0Ea +0Ua +b0 4` +0D` +0T` +0d` +0t` +0&a +06a +0Fa +0Va +b0 5` +0E` +0U` +0e` +0u` +0'a +07a +0Ga +0Wa +b0 6` +0F` +0V` +0f` +0v` +0(a +08a +0Ha +0Xa +b0 7` +0G` +0W` +0g` +0w` +0)a +09a +0Ia +0Ya +b0 8` +0H` +0X` +0h` +0x` +0*a +0:a +0Ja +0Za +b0 Q^ +b0 S^ +b0 R^ +b0 T^ 0! 1" sHdlSome\x20(1) # @@ -13411,828 +16300,828 @@ b1000000000100 w" sHdlNone\x20(0) y" sTrap\x20(0) z" 1{" -b1 |" -1}" -0~" -b0 !# +sPowerISA\x20(0) |" +b1 }" +1~" +0!# b0 "# -b10 ## -1$# -0%# -b0 &# +b0 ## +b10 $# +1%# +0&# b0 '# -b11 (# -1)# -0*# -b0 +# +b0 (# +b11 )# +1*# +0+# b0 ,# b0 -# -1.# -0/# -b1 0# -b0 1# -12# +b0 .# +1/# +00# +b1 1# +b0 2# 13# -b0 4# -05# +14# +b0 5# 06# -b0 7# +07# b0 8# -19# +b0 9# 1:# -b10 ;# -1<# -0=# -b0 ># +1;# +b10 <# +1=# +0># b0 ?# -b11 @# -1A# -0B# -b0 C# +b0 @# +b11 A# +1B# +0C# b0 D# b0 E# -0F# +b0 F# 0G# -b0 H# +0H# b0 I# -b1 J# -1K# -0L# -b10 M# -b0 N# -1O# +b0 J# +b1 K# +1L# +0M# +b10 N# +b0 O# 1P# -b0 Q# -0R# +1Q# +b0 R# 0S# -b0 T# +0T# b0 U# -1V# +b0 V# 1W# -0X# +1X# 0Y# 0Z# -b0 [# +0[# b0 \# -0]# +b0 ]# 0^# 0_# -b0 `# +0`# b0 a# -0b# +b0 b# 0c# 0d# -b0 e# +0e# b0 f# -0g# +b0 g# 0h# 0i# -b0 j# +0j# b0 k# -1l# +b0 l# 1m# -0n# +1n# 0o# 0p# -b0 q# +0q# b0 r# -1s# +b0 s# 1t# -0u# -1v# -0w# -b1 x# -b0 y# -1z# +1u# +0v# +1w# +0x# +b1 y# +b0 z# 1{# -0|# +1|# 0}# 0~# -b0 !$ +0!$ b0 "$ -1#$ +b0 #$ 1$$ -0%$ +1%$ 0&$ 0'$ -b0 ($ +0($ b0 )$ -0*$ +b0 *$ 0+$ 0,$ -b0 -$ +0-$ b0 .$ -0/$ +b0 /$ 00$ 01$ -b0 2$ +02$ b0 3$ -04$ +b0 4$ 05$ 06$ -b0 7$ +07$ b0 8$ -19$ +b0 9$ 1:$ -0;$ +1;$ 0<$ 0=$ -b0 >$ +0>$ b0 ?$ -1@$ +b0 @$ 1A$ -0B$ +1B$ 0C$ 0D$ -b0 E$ +0E$ b0 F$ -1G$ +b0 G$ 1H$ 1I$ 1J$ -0K$ -b10 L$ -b0 M$ -1N$ +1K$ +0L$ +b10 M$ +b0 N$ 1O$ 1P$ 1Q$ -0R$ -1S$ -sHdlSome\x20(1) T$ -b0 U$ -sHdlSome\x20(1) V$ -b1 W$ -sHdlSome\x20(1) X$ -sAluBranch\x20(0) Y$ -sAddSub\x20(0) Z$ -s0 [$ -b0 \$ +1R$ +0S$ +1T$ +sHdlSome\x20(1) U$ +b0 V$ +sHdlSome\x20(1) W$ +b1 X$ +sHdlSome\x20(1) Y$ +sAluBranch\x20(0) Z$ +sAddSub\x20(0) [$ +s0 \$ b0 ]$ b0 ^$ b0 _$ -b1001000110100 `$ -0a$ -sFull64\x20(0) b$ -1c$ +b0 `$ +b1001000110100 a$ +0b$ +sFull64\x20(0) c$ 1d$ 1e$ 1f$ -s0 g$ -b0 h$ +1g$ +s0 h$ b0 i$ b0 j$ b0 k$ -b1001000110100 l$ -0m$ -sFull64\x20(0) n$ -1o$ +b0 l$ +b1001000110100 m$ +0n$ +sFull64\x20(0) o$ 1p$ 1q$ 1r$ -s0 s$ -b0 t$ +1s$ +s0 t$ b0 u$ b0 v$ b0 w$ -b1001000110100 x$ -0y$ -sFull64\x20(0) z$ -b1111 {$ -sReadL2Reg\x20(0) |$ -0}$ -b0 ~$ +b0 x$ +b1001000110100 y$ +0z$ +sFull64\x20(0) {$ +b1111 |$ +sReadL2Reg\x20(0) }$ +0~$ b0 !% b0 "% b0 #% -b1001000110100 $% -0%% +b0 $% +b1001000110100 %% 0&% -b0 '% +0'% b0 (% b0 )% b0 *% -b1001000110100 +% -0,% -sLoad\x20(0) -% -0.% -b0 /% +b0 +% +b1001000110100 ,% +0-% +sLoad\x20(0) .% +0/% b0 0% b0 1% b0 2% -b1001000110100 3% -04% +b0 3% +b1001000110100 4% 05% -b0 6% +06% b0 7% b0 8% b0 9% -b1001000110100 :% -0;% -sHdlSome\x20(1) <% -sAluBranch\x20(0) =% -sLogical\x20(2) >% -s0 ?% -b0 @% -b0 A% +b0 :% +b1001000110100 ;% +0<% +b1000000000000 =% +sHdlSome\x20(1) >% +sAluBranch\x20(0) ?% +sLogical\x20(2) @% +s0 A% b0 B% b0 C% b0 D% -0E% -sFull64\x20(0) F% +b0 E% +b0 F% 0G% -1H% -1I% -0J% -s0 K% -b0 L% -b0 M% +sFull64\x20(0) H% +0I% +1J% +1K% +0L% +s0 M% b0 N% b0 O% b0 P% -0Q% -sFull64\x20(0) R% +b0 Q% +b0 R% 0S% -1T% -1U% -0V% -s0 W% -b0 X% -b0 Y% +sFull64\x20(0) T% +0U% +1V% +1W% +0X% +s0 Y% b0 Z% b0 [% b0 \% -0]% -sFull64\x20(0) ^% -b110 _% -sReadL2Reg\x20(0) `% -1a% -b0 b% -b0 c% +b0 ]% +b0 ^% +0_% +sFull64\x20(0) `% +b110 a% +sReadL2Reg\x20(0) b% +1c% b0 d% b0 e% b0 f% -0g% -1h% -b0 i% -b0 j% +b0 g% +b0 h% +0i% +1j% b0 k% b0 l% b0 m% -0n% -sLoad\x20(0) o% -1p% -b0 q% -b0 r% +b0 n% +b0 o% +0p% +sLoad\x20(0) q% +1r% b0 s% b0 t% b0 u% -0v% -1w% -b0 x% -b0 y% +b0 v% +b0 w% +0x% +1y% b0 z% b0 {% b0 |% -0}% -sHdlSome\x20(1) ~% -b1 !& -b0 "& +b0 }% +b0 ~% +0!& +b1000000000100 "& sHdlSome\x20(1) #& -b10 $& +b1 $& b0 %& -b10 && -b0 '& +sHdlSome\x20(1) && +b10 '& b0 (& -b11 )& +b10 )& b0 *& b0 +& -b100 ,& +b11 ,& b0 -& b0 .& -b0 /& -10& -01& -b1 2& -b0 3& -14& -15& -06& -07& -08& -b0 9& -b0 :& -1;& -1<& +b100 /& +b0 0& +b0 1& +b0 2& +13& +04& +b1 5& +b0 6& +17& +18& +09& +0:& +0;& +b0 <& b0 =& -0>& -0?& +1>& +1?& b0 @& -b0 A& -1B& -1C& -0D& -0E& -0F& -b0 G& -b0 H& -1I& -1J& -0K& +0A& +0B& +b0 C& +b0 D& +1E& +1F& +0G& +0H& +0I& +b0 J& +b0 K& 1L& -0M& -b1 N& -b0 O& -1P& -1Q& -0R& -0S& -0T& -b0 U& -b0 V& -1W& -1X& -sAluBranch\x20(0) Y& +1M& +0N& +1O& +0P& +b1 Q& +b0 R& +1S& +1T& +0U& +0V& +0W& +b0 X& +b0 Y& 1Z& 1[& -b1 \& -b0 ]& -sHdlSome\x20(1) ^& -sHdlNone\x20(0) _& -b1 `& -b0 a& -sHdlSome\x20(1) b& -sHdlNone\x20(0) c& -b1 d& -b0 e& -sHdlSome\x20(1) f& -sHdlNone\x20(0) g& -b1 h& -b0 i& -sHdlSome\x20(1) j& -sHdlNone\x20(0) k& -sAluBranch\x20(0) l& -sAddSub\x20(0) m& -s0 n& -b0 o& -b0 p& -b0 q& +sAluBranch\x20(0) \& +1]& +1^& +b1 _& +b0 `& +sHdlSome\x20(1) a& +sHdlNone\x20(0) b& +b1 c& +b0 d& +sHdlSome\x20(1) e& +sHdlNone\x20(0) f& +b1 g& +b0 h& +sHdlSome\x20(1) i& +sHdlNone\x20(0) j& +b1 k& +b0 l& +sHdlSome\x20(1) m& +sHdlNone\x20(0) n& +sAluBranch\x20(0) o& +sAddSub\x20(0) p& +s0 q& b0 r& -b1001000110100 s& -0t& -sFull64\x20(0) u& -1v& -1w& -1x& +b0 s& +b0 t& +b0 u& +b1001000110100 v& +0w& +sFull64\x20(0) x& 1y& -s0 z& -b0 {& -b0 |& -b0 }& +1z& +1{& +1|& +s0 }& b0 ~& -b1001000110100 !' -0"' -sFull64\x20(0) #' -1$' -1%' -1&' +b0 !' +b0 "' +b0 #' +b1001000110100 $' +0%' +sFull64\x20(0) &' 1'' -s0 (' -b0 )' -b0 *' -b0 +' +1(' +1)' +1*' +s0 +' b0 ,' -b1001000110100 -' -0.' -sFull64\x20(0) /' -b1111 0' -sReadL2Reg\x20(0) 1' -02' -b0 3' -b0 4' -b0 5' +b0 -' +b0 .' +b0 /' +b1001000110100 0' +01' +sFull64\x20(0) 2' +b1111 3' +sReadL2Reg\x20(0) 4' +05' b0 6' -b1001000110100 7' -08' -09' -b0 :' -b0 ;' -b0 <' +b0 7' +b0 8' +b0 9' +b1001000110100 :' +0;' +0<' b0 =' -b1001000110100 >' -0?' -sLoad\x20(0) @' -0A' -b0 B' -b0 C' -b0 D' +b0 >' +b0 ?' +b0 @' +b1001000110100 A' +0B' +sLoad\x20(0) C' +0D' b0 E' -b1001000110100 F' -0G' -0H' -b0 I' -b0 J' -b0 K' +b0 F' +b0 G' +b0 H' +b1001000110100 I' +0J' +0K' b0 L' -b1001000110100 M' -0N' -sAddSub\x20(0) O' -s0 P' -b0 Q' -b0 R' -b0 S' +b0 M' +b0 N' +b0 O' +b1001000110100 P' +0Q' +sAddSub\x20(0) R' +s0 S' b0 T' -b1001000110100 U' -0V' -sFull64\x20(0) W' -1X' -1Y' -1Z' +b0 U' +b0 V' +b0 W' +b1001000110100 X' +0Y' +sFull64\x20(0) Z' 1[' -s0 \' -b0 ]' -b0 ^' -b0 _' +1\' +1]' +1^' +s0 _' b0 `' -b1001000110100 a' -0b' -sFull64\x20(0) c' -1d' -1e' -1f' +b0 a' +b0 b' +b0 c' +b1001000110100 d' +0e' +sFull64\x20(0) f' 1g' -s0 h' -b0 i' -b0 j' -b0 k' +1h' +1i' +1j' +s0 k' b0 l' -b1001000110100 m' -0n' -sFull64\x20(0) o' -b1111 p' -sReadL2Reg\x20(0) q' -0r' -b0 s' -b0 t' -b0 u' -b100 v' -b1001000110100 w' -0x' -0y' -b0 z' -b0 {' -b0 |' -b100 }' -b1001000110100 ~' -0!( -sLoad\x20(0) "( -0#( -b0 $( -b0 %( -b0 &( -b100 '( -b1001000110100 (( -0)( -0*( -b0 +( -b0 ,( -b0 -( -b100 .( -b1001000110100 /( -00( -b11111110 1( -b0 2( -sHdlSome\x20(1) 3( -b0 4( +b0 m' +b0 n' +b0 o' +b1001000110100 p' +0q' +sFull64\x20(0) r' +b1111 s' +sReadL2Reg\x20(0) t' +0u' +b0 v' +b0 w' +b0 x' +b100 y' +b1001000110100 z' +0{' +0|' +b0 }' +b0 ~' +b0 !( +b100 "( +b1001000110100 #( +0$( +sLoad\x20(0) %( +0&( +b0 '( +b0 (( +b0 )( +b100 *( +b1001000110100 +( +0,( +0-( +b0 .( +b0 /( +b0 0( +b100 1( +b1001000110100 2( +03( +b11111110 4( b0 5( sHdlSome\x20(1) 6( -b1 7( -b1 8( +b0 7( +b0 8( sHdlSome\x20(1) 9( -b0 :( -b11 ;( -b0 <( +b1 :( +b1 ;( +sHdlSome\x20(1) <( b0 =( -b1 >( +b11 >( b0 ?( -sHdlSome\x20(1) @( -sHdlNone\x20(0) A( -b1 B( -b0 C( -sHdlSome\x20(1) D( -sHdlNone\x20(0) E( -b1 F( -b0 G( -sHdlSome\x20(1) H( -sHdlNone\x20(0) I( -b1 J( -b0 K( -sHdlSome\x20(1) L( -sHdlNone\x20(0) M( -b11111110 N( -b0 O( -b1 P( -b0 Q( -sHdlSome\x20(1) R( -sHdlNone\x20(0) S( -b1 T( -b0 U( -sHdlSome\x20(1) V( -sHdlNone\x20(0) W( -b1 X( -b0 Y( -sHdlSome\x20(1) Z( -sHdlNone\x20(0) [( -b1 \( -b0 ]( -sHdlSome\x20(1) ^( -sHdlNone\x20(0) _( -b11111110 `( -b0 a( -b100 b( -b0 c( +b0 @( +b1 A( +b0 B( +sHdlSome\x20(1) C( +sHdlNone\x20(0) D( +b1 E( +b0 F( +sHdlSome\x20(1) G( +sHdlNone\x20(0) H( +b1 I( +b0 J( +sHdlSome\x20(1) K( +sHdlNone\x20(0) L( +b1 M( +b0 N( +sHdlSome\x20(1) O( +sHdlNone\x20(0) P( +b11111110 Q( +b0 R( +b1 S( +b0 T( +sHdlSome\x20(1) U( +sHdlNone\x20(0) V( +b1 W( +b0 X( +sHdlSome\x20(1) Y( +sHdlNone\x20(0) Z( +b1 [( +b0 \( +sHdlSome\x20(1) ]( +sHdlNone\x20(0) ^( +b1 _( +b0 `( +sHdlSome\x20(1) a( +sHdlNone\x20(0) b( +b11111110 c( b0 d( -b1 e( +b100 e( b0 f( -sHdlSome\x20(1) g( -sHdlNone\x20(0) h( -b1 i( -b0 j( -sHdlSome\x20(1) k( -sHdlNone\x20(0) l( -b1 m( -b0 n( -sHdlSome\x20(1) o( -sHdlNone\x20(0) p( -b1 q( -b0 r( -sHdlSome\x20(1) s( -sHdlNone\x20(0) t( -b11111110 u( -b0 v( -b1 w( -b0 x( -sHdlSome\x20(1) y( -sHdlNone\x20(0) z( -b1 {( -b0 |( -sHdlSome\x20(1) }( -sHdlNone\x20(0) ~( -b1 !) -b0 ") -sHdlSome\x20(1) #) -sHdlNone\x20(0) $) -b1 %) -b0 &) -sHdlSome\x20(1) ') -sHdlNone\x20(0) () -b11111110 )) -b0 *) -b0 +) -b0 ,) +b0 g( +b1 h( +b0 i( +sHdlSome\x20(1) j( +sHdlNone\x20(0) k( +b1 l( +b0 m( +sHdlSome\x20(1) n( +sHdlNone\x20(0) o( +b1 p( +b0 q( +sHdlSome\x20(1) r( +sHdlNone\x20(0) s( +b1 t( +b0 u( +sHdlSome\x20(1) v( +sHdlNone\x20(0) w( +b11111110 x( +b0 y( +b1 z( +b0 {( +sHdlSome\x20(1) |( +sHdlNone\x20(0) }( +b1 ~( +b0 !) +sHdlSome\x20(1) ") +sHdlNone\x20(0) #) +b1 $) +b0 %) +sHdlSome\x20(1) &) +sHdlNone\x20(0) ') +b1 () +b0 )) +sHdlSome\x20(1) *) +sHdlNone\x20(0) +) +b11111110 ,) b0 -) -b1 .) +b0 .) b0 /) -sHdlSome\x20(1) 0) -sHdlNone\x20(0) 1) -b1 2) -b0 3) -sHdlSome\x20(1) 4) -sHdlNone\x20(0) 5) -b1 6) -b0 7) -sHdlSome\x20(1) 8) -sHdlNone\x20(0) 9) -b1 :) -b0 ;) -sHdlSome\x20(1) <) -sHdlNone\x20(0) =) -b11111110 >) -b0 ?) -b1 @) -b0 A) -sHdlSome\x20(1) B) -sHdlNone\x20(0) C) -b1 D) -b0 E) -sHdlSome\x20(1) F) -sHdlNone\x20(0) G) -b1 H) -b0 I) -sHdlSome\x20(1) J) -sHdlNone\x20(0) K) -b1 L) -b0 M) -sHdlSome\x20(1) N) -sHdlNone\x20(0) O) -b11111110 P) -b0 Q) -b1 R) -1S) -0T) -b10 U) -b0 V) -1W) -1X) -0Y) -0Z) -0[) -b0 \) -b0 ]) -1^) -1_) +b0 0) +b1 1) +b0 2) +sHdlSome\x20(1) 3) +sHdlNone\x20(0) 4) +b1 5) +b0 6) +sHdlSome\x20(1) 7) +sHdlNone\x20(0) 8) +b1 9) +b0 :) +sHdlSome\x20(1) ;) +sHdlNone\x20(0) <) +b1 =) +b0 >) +sHdlSome\x20(1) ?) +sHdlNone\x20(0) @) +b11111110 A) +b0 B) +b1 C) +b0 D) +sHdlSome\x20(1) E) +sHdlNone\x20(0) F) +b1 G) +b0 H) +sHdlSome\x20(1) I) +sHdlNone\x20(0) J) +b1 K) +b0 L) +sHdlSome\x20(1) M) +sHdlNone\x20(0) N) +b1 O) +b0 P) +sHdlSome\x20(1) Q) +sHdlNone\x20(0) R) +b11111110 S) +b0 T) +b1 U) +1V) +0W) +b10 X) +b0 Y) +1Z) +1[) +0\) +0]) +0^) +b0 _) b0 `) -0a) -0b) +1a) +1b) b0 c) -b0 d) -1e) -1f) -0g) -0h) -0i) -b0 j) -b0 k) -1l) -1m) -0n) -0o) -0p) -b0 q) -b0 r) -1s) -1t) -1u) +0d) +0e) +b0 f) +b0 g) +1h) +1i) +0j) +0k) +0l) +b0 m) +b0 n) +1o) +1p) +0q) +0r) +0s) +b0 t) +b0 u) 1v) -0w) -b10 x) -b0 y) -1z) -1{) -sAluBranch\x20(0) |) +1w) +1x) +1y) +0z) +b10 {) +b0 |) 1}) 1~) -b10 !* -b0 "* -sHdlNone\x20(0) #* -sHdlSome\x20(1) $* -b10 %* -b0 &* -sHdlNone\x20(0) '* -sHdlSome\x20(1) (* -b10 )* -b0 ** -sHdlNone\x20(0) +* -sHdlSome\x20(1) ,* -b10 -* -b0 .* -sHdlNone\x20(0) /* -sHdlSome\x20(1) 0* -sAluBranch\x20(0) 1* -sLogical\x20(2) 2* -s0 3* -b0 4* -b0 5* -b0 6* +sAluBranch\x20(0) !* +1"* +1#* +b10 $* +b0 %* +sHdlNone\x20(0) &* +sHdlSome\x20(1) '* +b10 (* +b0 )* +sHdlNone\x20(0) ** +sHdlSome\x20(1) +* +b10 ,* +b0 -* +sHdlNone\x20(0) .* +sHdlSome\x20(1) /* +b10 0* +b0 1* +sHdlNone\x20(0) 2* +sHdlSome\x20(1) 3* +sAluBranch\x20(0) 4* +sLogical\x20(2) 5* +s0 6* b0 7* b0 8* -09* -sFull64\x20(0) :* -0;* -1<* -1=* +b0 9* +b0 :* +b0 ;* +0<* +sFull64\x20(0) =* 0>* -s0 ?* -b0 @* -b0 A* -b0 B* +1?* +1@* +0A* +s0 B* b0 C* b0 D* -0E* -sFull64\x20(0) F* -0G* -1H* -1I* +b0 E* +b0 F* +b0 G* +0H* +sFull64\x20(0) I* 0J* -s0 K* -b0 L* -b0 M* -b0 N* +1K* +1L* +0M* +s0 N* b0 O* b0 P* -0Q* -sFull64\x20(0) R* -b110 S* -sReadL2Reg\x20(0) T* -1U* -b0 V* -b0 W* -b0 X* +b0 Q* +b0 R* +b0 S* +0T* +sFull64\x20(0) U* +b110 V* +sReadL2Reg\x20(0) W* +1X* b0 Y* b0 Z* -0[* -1\* +b0 [* +b0 \* b0 ]* -b0 ^* -b0 _* +0^* +1_* b0 `* b0 a* -0b* -sLoad\x20(0) c* -1d* -b0 e* -b0 f* -b0 g* +b0 b* +b0 c* +b0 d* +0e* +sLoad\x20(0) f* +1g* b0 h* b0 i* -0j* -1k* +b0 j* +b0 k* b0 l* -b0 m* -b0 n* +0m* +1n* b0 o* b0 p* -0q* -sLogical\x20(2) r* -s0 s* -b0 t* -b0 u* -b0 v* +b0 q* +b0 r* +b0 s* +0t* +sLogical\x20(2) u* +s0 v* b0 w* b0 x* -0y* -sFull64\x20(0) z* -0{* -1|* -1}* +b0 y* +b0 z* +b0 {* +0|* +sFull64\x20(0) }* 0~* -s0 !+ -b0 "+ -b0 #+ -b0 $+ +1!+ +1"+ +0#+ +s0 $+ b0 %+ b0 &+ -0'+ -sFull64\x20(0) (+ -0)+ -1*+ -1++ +b0 '+ +b0 (+ +b0 )+ +0*+ +sFull64\x20(0) ++ 0,+ -s0 -+ -b0 .+ -b0 /+ -b0 0+ +1-+ +1.+ +0/+ +s0 0+ b0 1+ b0 2+ -03+ -sFull64\x20(0) 4+ -b110 5+ -sReadL2Reg\x20(0) 6+ -17+ -b0 8+ -b0 9+ -b0 :+ +b0 3+ +b0 4+ +b0 5+ +06+ +sFull64\x20(0) 7+ +b110 8+ +sReadL2Reg\x20(0) 9+ +1:+ b0 ;+ b0 <+ -0=+ -1>+ +b0 =+ +b0 >+ b0 ?+ -b0 @+ -b0 A+ +0@+ +1A+ b0 B+ b0 C+ -0D+ -sLoad\x20(0) E+ -1F+ -b0 G+ -b0 H+ -b0 I+ +b0 D+ +b0 E+ +b0 F+ +0G+ +sLoad\x20(0) H+ +1I+ b0 J+ b0 K+ -0L+ -1M+ +b0 L+ +b0 M+ b0 N+ -b0 O+ -b0 P+ +0O+ +1P+ b0 Q+ b0 R+ -0S+ +b0 S+ b0 T+ -b11111111 U+ -sHdlNone\x20(0) V+ +b0 U+ +0V+ b0 W+ -b0 X+ -sHdlSome\x20(1) Y+ -b1 Z+ -b1 [+ +b11111111 X+ +sHdlNone\x20(0) Y+ +b0 Z+ +b0 [+ sHdlSome\x20(1) \+ b1 ]+ -0^+ -1_+ -sHdlNone\x20(0) `+ -b0 a+ +b1 ^+ +sHdlSome\x20(1) _+ +b1 `+ +sHdlNone\x20(0) a+ b0 b+ -0c+ +b0 c+ 0d+ 0e+ 0f+ @@ -14240,10 +17129,10 @@ b0 b+ 0h+ 0i+ 0j+ -sHdlNone\x20(0) k+ -b0 l+ +0k+ +sHdlNone\x20(0) l+ b0 m+ -0n+ +b0 n+ 0o+ 0p+ 0q+ @@ -14251,403 +17140,403 @@ b0 m+ 0s+ 0t+ 0u+ -sHdlSome\x20(1) v+ -sAddSub\x20(0) w+ -s0 x+ -b0 y+ +0v+ +0w+ +1x+ +sHdlNone\x20(0) y+ b0 z+ b0 {+ -b0 |+ -b1001000110100 }+ +0|+ +0}+ 0~+ -sFull64\x20(0) !, -1", -1#, -1$, -1%, -s0 &, +0!, +0", +0#, +0$, +0%, +sHdlNone\x20(0) &, b0 ', b0 (, -b0 ), -b0 *, -b1001000110100 +, +0), +0*, +0+, 0,, -sFull64\x20(0) -, -1., -1/, -10, -11, -s0 2, -b0 3, +0-, +0., +0/, +00, +sHdlSome\x20(1) 1, +sAddSub\x20(0) 2, +s0 3, b0 4, b0 5, b0 6, -b1001000110100 7, -08, -sFull64\x20(0) 9, -b1111 :, +b0 7, +b1001000110100 8, +09, +sFull64\x20(0) :, 1;, -sHdlNone\x20(0) <, -b0 =, -sHdlNone\x20(0) >, -b0 ?, -sCompleted\x20(0) @, +1<, +1=, +1>, +s0 ?, +b0 @, b0 A, -0B, -0C, -0D, +b0 B, +b0 C, +b1001000110100 D, 0E, -0F, -0G, -0H, -0I, -0J, -1K, -sHdlNone\x20(0) L, +sFull64\x20(0) F, +1G, +1H, +1I, +1J, +s0 K, +b0 L, b0 M, b0 N, -0O, -0P, +b0 O, +b1001000110100 P, 0Q, -0R, -0S, -0T, -0U, -0V, -sHdlNone\x20(0) W, -b0 X, +sFull64\x20(0) R, +b1111 S, +b1000000000000 T, +1U, +sHdlNone\x20(0) V, +b0 W, +sHdlNone\x20(0) X, b0 Y, -0Z, -0[, +sCompleted\x20(0) Z, +b0 [, 0\, 0], 0^, 0_, 0`, 0a, -sHdlSome\x20(1) b, -sAddSub\x20(0) c, -s0 d, -b0 e, -b0 f, -b0 g, +0b, +0c, +sPowerISA\x20(0) d, +0e, +1f, +sHdlNone\x20(0) g, b0 h, -b1001000110100 i, +b0 i, 0j, -sFull64\x20(0) k, -1l, -1m, -1n, -1o, -s0 p, -b0 q, -b0 r, +0k, +0l, +0m, +0n, +0o, +0p, +0q, +sHdlNone\x20(0) r, b0 s, b0 t, -b1001000110100 u, +0u, 0v, -sFull64\x20(0) w, -1x, -1y, -1z, -1{, -s0 |, -b0 }, -b0 ~, -b0 !- +0w, +0x, +0y, +0z, +0{, +0|, +sHdlSome\x20(1) }, +sAddSub\x20(0) ~, +s0 !- b0 "- -b1001000110100 #- -0$- -sFull64\x20(0) %- -b1111 &- -1'- -sHdlNone\x20(0) (- -b0 )- -sHdlNone\x20(0) *- -b0 +- -sCompleted\x20(0) ,- -b0 -- -0.- -0/- -00- -01- -02- +b0 #- +b0 $- +b0 %- +b1001000110100 &- +0'- +sFull64\x20(0) (- +1)- +1*- +1+- +1,- +s0 -- +b0 .- +b0 /- +b0 0- +b0 1- +b1001000110100 2- 03- -04- -05- -sHdlNone\x20(0) 6- -sAddSub\x20(0) 7- -s0 8- -b0 9- +sFull64\x20(0) 4- +15- +16- +17- +18- +s0 9- b0 :- b0 ;- b0 <- b0 =- -0>- -sFull64\x20(0) ?- -0@- -0A- -0B- -0C- -s0 D- +b1001000110100 >- +0?- +sFull64\x20(0) @- +b1111 A- +b1000000000000 B- +1C- +sHdlNone\x20(0) D- b0 E- -b0 F- +sHdlNone\x20(0) F- b0 G- -b0 H- +sCompleted\x20(0) H- b0 I- 0J- -sFull64\x20(0) K- +0K- 0L- 0M- 0N- 0O- -s0 P- -b0 Q- -b0 R- -b0 S- -b0 T- +0P- +0Q- +sHdlNone\x20(0) R- +sAddSub\x20(0) S- +s0 T- b0 U- -0V- -sFull64\x20(0) W- +b0 V- +b0 W- b0 X- b0 Y- 0Z- -0[- +sFull64\x20(0) [- 0\- 0]- 0^- 0_- -0`- -0a- +s0 `- +b0 a- b0 b- -0c- -0d- -0e- +b0 c- +b0 d- +b0 e- 0f- -0g- +sFull64\x20(0) g- 0h- 0i- 0j- -b0 k- -0l- -0m- -0n- -0o- -0p- -0q- +0k- +s0 l- +b0 m- +b0 n- +b0 o- +b0 p- +b0 q- 0r- -0s- -1t- -sHdlNone\x20(0) u- +sFull64\x20(0) s- +b0 t- +b0 u- b0 v- -sCompleted\x20(0) w- -b0 x- +0w- +0x- 0y- 0z- 0{- 0|- 0}- 0~- -0!. +b0 !. 0". -sHdlNone\x20(0) #. -sReady\x20(0) $. -sAddSub\x20(0) %. -s0 &. -b0 '. -b0 (. -b0 ). +0#. +0$. +0%. +0&. +0'. +0(. +0). b0 *. -b0 +. +0+. 0,. -sFull64\x20(0) -. +0-. 0.. 0/. 00. 01. -s0 2. -b0 3. -b0 4. +02. +13. +sHdlNone\x20(0) 4. b0 5. -b0 6. +sCompleted\x20(0) 6. b0 7. 08. -sFull64\x20(0) 9. +09. 0:. 0;. 0<. 0=. -s0 >. -b0 ?. +0>. +0?. b0 @. -b0 A. -b0 B. +0A. +0B. b0 C. 0D. -sFull64\x20(0) E. -b0 F. +0E. +0F. 0G. 0H. 0I. -sHdlNone\x20(0) J. -sReady\x20(0) K. -sAddSub\x20(0) L. -s0 M. -b0 N. +0J. +0K. +b0 L. +0M. +0N. b0 O. -b0 P. -b0 Q. -b0 R. +0P. +0Q. +0R. 0S. -sFull64\x20(0) T. +0T. 0U. 0V. 0W. -0X. -s0 Y. -b0 Z. +b0 X. +0Y. +0Z. b0 [. -b0 \. -b0 ]. -b0 ^. +0\. +0]. +0^. 0_. -sFull64\x20(0) `. +0`. 0a. 0b. 0c. -0d. -s0 e. -b0 f. +b0 d. +0e. +0f. b0 g. -b0 h. -b0 i. -b0 j. +0h. +0i. +0j. 0k. -sFull64\x20(0) l. -b0 m. +0l. +0m. 0n. 0o. -0p. -sHdlNone\x20(0) q. -sReady\x20(0) r. -sAddSub\x20(0) s. -s0 t. -b0 u. -b0 v. -b0 w. -b0 x. +1p. +1q. +1r. +1s. +1t. +1u. +1v. +1w. +1x. b0 y. 0z. -sFull64\x20(0) {. -0|. +0{. +b0 |. 0}. 0~. 0!/ -s0 "/ -b0 #/ -b0 $/ -b0 %/ -b0 &/ +0"/ +0#/ +0$/ +0%/ +0&/ b0 '/ 0(/ -sFull64\x20(0) )/ -0*/ +0)/ +b0 */ 0+/ 0,/ 0-/ -s0 ./ -b0 // -b0 0/ -b0 1/ -b0 2/ +0./ +0// +00/ +01/ +02/ b0 3/ 04/ -sFull64\x20(0) 5/ +05/ b0 6/ 07/ 08/ 09/ -sHdlNone\x20(0) :/ -sReady\x20(0) ;/ -sAddSub\x20(0) / +0:/ +0;/ +0/ b0 ?/ -b0 @/ -b0 A/ +0@/ +0A/ b0 B/ 0C/ -sFull64\x20(0) D/ +0D/ 0E/ 0F/ 0G/ 0H/ -s0 I/ -b0 J/ -b0 K/ -b0 L/ -b0 M/ -b0 N/ -0O/ -sFull64\x20(0) P/ -0Q/ -0R/ -0S/ -0T/ -s0 U/ -b0 V/ -b0 W/ +0I/ +0J/ +1K/ +1L/ +1M/ +1N/ +1O/ +1P/ +1Q/ +1R/ +1S/ +sHdlNone\x20(0) T/ +sReady\x20(0) U/ +sAddSub\x20(0) V/ +s0 W/ b0 X/ b0 Y/ b0 Z/ -0[/ -sFull64\x20(0) \/ -b0 ]/ -0^/ +b0 [/ +b0 \/ +0]/ +sFull64\x20(0) ^/ 0_/ 0`/ -sHdlNone\x20(0) a/ -sReady\x20(0) b/ -sAddSub\x20(0) c/ -s0 d/ +0a/ +0b/ +s0 c/ +b0 d/ b0 e/ b0 f/ b0 g/ b0 h/ -b0 i/ -0j/ -sFull64\x20(0) k/ +0i/ +sFull64\x20(0) j/ +0k/ 0l/ 0m/ 0n/ -0o/ -s0 p/ +s0 o/ +b0 p/ b0 q/ b0 r/ b0 s/ b0 t/ -b0 u/ -0v/ -sFull64\x20(0) w/ -0x/ +0u/ +sFull64\x20(0) v/ +b0 w/ +b0 x/ 0y/ 0z/ 0{/ -s0 |/ -b0 }/ -b0 ~/ -b0 !0 +sHdlNone\x20(0) |/ +sReady\x20(0) }/ +sAddSub\x20(0) ~/ +s0 !0 b0 "0 b0 #0 -0$0 -sFull64\x20(0) %0 +b0 $0 +b0 %0 b0 &0 0'0 -0(0 +sFull64\x20(0) (0 0)0 -sHdlNone\x20(0) *0 -sReady\x20(0) +0 -sAddSub\x20(0) ,0 +0*0 +0+0 +0,0 s0 -0 b0 .0 b0 /0 @@ -14668,556 +17557,556 @@ b0 =0 b0 >0 0?0 sFull64\x20(0) @0 -0A0 -0B0 +b0 A0 +b0 B0 0C0 0D0 -s0 E0 -b0 F0 -b0 G0 -b0 H0 -b0 I0 +0E0 +sHdlNone\x20(0) F0 +sReady\x20(0) G0 +sAddSub\x20(0) H0 +s0 I0 b0 J0 -0K0 -sFull64\x20(0) L0 +b0 K0 +b0 L0 b0 M0 -0N0 +b0 N0 0O0 -0P0 -sHdlNone\x20(0) Q0 -sReady\x20(0) R0 -sAddSub\x20(0) S0 -s0 T0 -b0 U0 +sFull64\x20(0) P0 +0Q0 +0R0 +0S0 +0T0 +s0 U0 b0 V0 b0 W0 b0 X0 b0 Y0 -0Z0 -sFull64\x20(0) [0 -0\0 +b0 Z0 +0[0 +sFull64\x20(0) \0 0]0 0^0 0_0 -s0 `0 -b0 a0 +0`0 +s0 a0 b0 b0 b0 c0 b0 d0 b0 e0 -0f0 -sFull64\x20(0) g0 -0h0 -0i0 -0j0 +b0 f0 +0g0 +sFull64\x20(0) h0 +b0 i0 +b0 j0 0k0 -s0 l0 -b0 m0 -b0 n0 -b0 o0 -b0 p0 -b0 q0 -0r0 -sFull64\x20(0) s0 +0l0 +0m0 +sHdlNone\x20(0) n0 +sReady\x20(0) o0 +sAddSub\x20(0) p0 +s0 q0 +b0 r0 +b0 s0 b0 t0 -0u0 -0v0 +b0 u0 +b0 v0 0w0 -sHdlNone\x20(0) x0 -sReady\x20(0) y0 -sAddSub\x20(0) z0 -s0 {0 -b0 |0 -b0 }0 +sFull64\x20(0) x0 +0y0 +0z0 +0{0 +0|0 +s0 }0 b0 ~0 b0 !1 b0 "1 -0#1 -sFull64\x20(0) $1 +b0 #1 +b0 $1 0%1 -0&1 +sFull64\x20(0) &1 0'1 0(1 -s0 )1 -b0 *1 -b0 +1 +0)1 +0*1 +s0 +1 b0 ,1 b0 -1 b0 .1 -0/1 -sFull64\x20(0) 01 +b0 /1 +b0 01 011 -021 -031 -041 -s0 51 -b0 61 -b0 71 -b0 81 -b0 91 -b0 :1 -0;1 -sFull64\x20(0) <1 +sFull64\x20(0) 21 +b0 31 +b0 41 +051 +061 +071 +sHdlNone\x20(0) 81 +sReady\x20(0) 91 +sAddSub\x20(0) :1 +s0 ;1 +b0 <1 b0 =1 -0>1 -0?1 -0@1 -sHdlSome\x20(1) A1 -b0 B1 -sHdlNone\x20(0) C1 -b0 D1 -sHdlSome\x20(1) E1 -b1 F1 -sHdlNone\x20(0) G1 +b0 >1 +b0 ?1 +b0 @1 +0A1 +sFull64\x20(0) B1 +0C1 +0D1 +0E1 +0F1 +s0 G1 b0 H1 -sHdlSome\x20(1) I1 +b0 I1 b0 J1 -sHdlNone\x20(0) K1 +b0 K1 b0 L1 -sHdlSome\x20(1) M1 -b10 N1 -sHdlNone\x20(0) O1 -b0 P1 -sHdlSome\x20(1) Q1 -b11 R1 -sHdlNone\x20(0) S1 +0M1 +sFull64\x20(0) N1 +0O1 +0P1 +0Q1 +0R1 +s0 S1 b0 T1 -sHdlSome\x20(1) U1 -b10 V1 -sHdlNone\x20(0) W1 +b0 U1 +b0 V1 +b0 W1 b0 X1 -sHdlSome\x20(1) Y1 -b0 Z1 -sHdlNone\x20(0) [1 +0Y1 +sFull64\x20(0) Z1 +b0 [1 b0 \1 -sHdlSome\x20(1) ]1 -b100 ^1 -sHdlNone\x20(0) _1 -b0 `1 -sHdlSome\x20(1) a1 -b101 b1 -sHdlNone\x20(0) c1 +0]1 +0^1 +0_1 +sHdlNone\x20(0) `1 +sReady\x20(0) a1 +sAddSub\x20(0) b1 +s0 c1 b0 d1 -sHdlSome\x20(1) e1 -b100 f1 -sHdlNone\x20(0) g1 +b0 e1 +b0 f1 +b0 g1 b0 h1 -sHdlSome\x20(1) i1 -b110 j1 -sHdlNone\x20(0) k1 -b0 l1 -sHdlSome\x20(1) m1 -b111 n1 -sHdlNone\x20(0) o1 +0i1 +sFull64\x20(0) j1 +0k1 +0l1 +0m1 +0n1 +s0 o1 b0 p1 -sHdlSome\x20(1) q1 -b110 r1 -sHdlNone\x20(0) s1 +b0 q1 +b0 r1 +b0 s1 b0 t1 -sHdlSome\x20(1) u1 -b100 v1 -sHdlNone\x20(0) w1 -b0 x1 -sHdlSome\x20(1) y1 -b0 z1 -sHdlNone\x20(0) {1 +0u1 +sFull64\x20(0) v1 +0w1 +0x1 +0y1 +0z1 +s0 {1 b0 |1 -sHdlSome\x20(1) }1 +b0 }1 b0 ~1 -sHdlNone\x20(0) !2 +b0 !2 b0 "2 -1#2 -sHdlSome\x20(1) $2 -sReady\x20(0) %2 -sAddSub\x20(0) &2 -s0 '2 -b0 (2 -b0 )2 -b0 *2 -b0 +2 -b1001000110100 ,2 -0-2 -sFull64\x20(0) .2 -1/2 -102 -112 -122 -s0 32 -b0 42 -b0 52 -b0 62 -b0 72 -b1001000110100 82 -092 -sFull64\x20(0) :2 -1;2 -1<2 -1=2 -1>2 -s0 ?2 -b0 @2 -b0 A2 -b0 B2 -b0 C2 -b1001000110100 D2 -0E2 -sFull64\x20(0) F2 -b1111 G2 -1H2 -1I2 -1J2 -sHdlSome\x20(1) K2 -sAddSub\x20(0) L2 -s0 M2 +0#2 +sFull64\x20(0) $2 +b0 %2 +b0 &2 +0'2 +0(2 +0)2 +sHdlNone\x20(0) *2 +sReady\x20(0) +2 +sAddSub\x20(0) ,2 +s0 -2 +b0 .2 +b0 /2 +b0 02 +b0 12 +b0 22 +032 +sFull64\x20(0) 42 +052 +062 +072 +082 +s0 92 +b0 :2 +b0 ;2 +b0 <2 +b0 =2 +b0 >2 +0?2 +sFull64\x20(0) @2 +0A2 +0B2 +0C2 +0D2 +s0 E2 +b0 F2 +b0 G2 +b0 H2 +b0 I2 +b0 J2 +0K2 +sFull64\x20(0) L2 +b0 M2 b0 N2 -b0 O2 -b0 P2 -b0 Q2 -b1001000110100 R2 -0S2 -sFull64\x20(0) T2 -1U2 -1V2 -1W2 -1X2 -s0 Y2 +0O2 +0P2 +0Q2 +sHdlNone\x20(0) R2 +sReady\x20(0) S2 +sAddSub\x20(0) T2 +s0 U2 +b0 V2 +b0 W2 +b0 X2 +b0 Y2 b0 Z2 -b0 [2 -b0 \2 -b0 ]2 -b1001000110100 ^2 +0[2 +sFull64\x20(0) \2 +0]2 +0^2 0_2 -sFull64\x20(0) `2 -1a2 -1b2 -1c2 -1d2 -s0 e2 +0`2 +s0 a2 +b0 b2 +b0 c2 +b0 d2 +b0 e2 b0 f2 -b0 g2 -b0 h2 -b0 i2 -b1001000110100 j2 +0g2 +sFull64\x20(0) h2 +0i2 +0j2 0k2 -sFull64\x20(0) l2 -b1111 m2 +0l2 +s0 m2 b0 n2 b0 o2 b0 p2 -1q2 -1r2 -1s2 -b0 t2 -1u2 -sHdlNone\x20(0) v2 -sReady\x20(0) w2 -sHdlNone\x20(0) x2 -sReady\x20(0) y2 -sHdlNone\x20(0) z2 -sReady\x20(0) {2 +b0 q2 +b0 r2 +0s2 +sFull64\x20(0) t2 +b0 u2 +b0 v2 +0w2 +0x2 +0y2 +sHdlSome\x20(1) z2 +b0 {2 sHdlNone\x20(0) |2 -sReady\x20(0) }2 -sHdlNone\x20(0) ~2 -sReady\x20(0) !3 +b0 }2 +sHdlSome\x20(1) ~2 +b1 !3 sHdlNone\x20(0) "3 -sReady\x20(0) #3 -sHdlNone\x20(0) $3 -sReady\x20(0) %3 +b0 #3 +sHdlSome\x20(1) $3 +b0 %3 sHdlNone\x20(0) &3 -sReady\x20(0) '3 -0(3 -0)3 -0*3 -0+3 -0,3 -0-3 -0.3 -0/3 -003 -013 -023 -033 -043 -053 -063 -073 -083 -093 -0:3 -0;3 -0<3 -0=3 -0>3 -0?3 -0@3 -0A3 -0B3 -0C3 -0D3 -0E3 -0F3 -0G3 -0H3 -0I3 -0J3 -0K3 -0L3 -0M3 -0N3 -0O3 -0P3 -0Q3 -0R3 -0S3 -0T3 -0U3 -0V3 -0W3 -b0 X3 +b0 '3 +sHdlSome\x20(1) (3 +b10 )3 +sHdlNone\x20(0) *3 +b0 +3 +sHdlSome\x20(1) ,3 +b11 -3 +sHdlNone\x20(0) .3 +b0 /3 +sHdlSome\x20(1) 03 +b10 13 +sHdlNone\x20(0) 23 +b0 33 +sHdlSome\x20(1) 43 +b0 53 +sHdlNone\x20(0) 63 +b0 73 +sHdlSome\x20(1) 83 +b100 93 +sHdlNone\x20(0) :3 +b0 ;3 +sHdlSome\x20(1) <3 +b101 =3 +sHdlNone\x20(0) >3 +b0 ?3 +sHdlSome\x20(1) @3 +b100 A3 +sHdlNone\x20(0) B3 +b0 C3 +sHdlSome\x20(1) D3 +b110 E3 +sHdlNone\x20(0) F3 +b0 G3 +sHdlSome\x20(1) H3 +b111 I3 +sHdlNone\x20(0) J3 +b0 K3 +sHdlSome\x20(1) L3 +b110 M3 +sHdlNone\x20(0) N3 +b0 O3 +sHdlSome\x20(1) P3 +b100 Q3 +sHdlNone\x20(0) R3 +b0 S3 +sHdlSome\x20(1) T3 +b0 U3 +sHdlNone\x20(0) V3 +b0 W3 +sHdlSome\x20(1) X3 b0 Y3 -b0 Z3 +sHdlNone\x20(0) Z3 b0 [3 -0\3 -sHdlNone\x20(0) ]3 -sAddSub\x20(0) ^3 -s0 _3 +1\3 +b0 ]3 +b0 ^3 +b0 _3 b0 `3 -b0 a3 -b0 b3 -b0 c3 -b0 d3 +0a3 +0b3 +0c3 +0d3 0e3 -sFull64\x20(0) f3 +0f3 0g3 0h3 -0i3 +b0 i3 0j3 -s0 k3 -b0 l3 -b0 m3 -b0 n3 -b0 o3 -b0 p3 +0k3 +0l3 +0m3 +0n3 +0o3 +0p3 0q3 -sFull64\x20(0) r3 +b0 r3 0s3 0t3 0u3 0v3 -s0 w3 -b0 x3 -b0 y3 -b0 z3 -b0 {3 -b0 |3 -0}3 -sFull64\x20(0) ~3 +0w3 +0x3 +0y3 +0z3 +sHdlSome\x20(1) {3 +sReady\x20(0) |3 +sAddSub\x20(0) }3 +s0 ~3 b0 !4 b0 "4 -0#4 -0$4 -0%4 +b0 #4 +b0 $4 +b1001000110100 %4 0&4 -0'4 -0(4 -0)4 -0*4 -b0 +4 -0,4 -0-4 -0.4 -0/4 -004 -014 +sFull64\x20(0) '4 +1(4 +1)4 +1*4 +1+4 +s0 ,4 +b0 -4 +b0 .4 +b0 /4 +b0 04 +b1001000110100 14 024 -034 -b0 44 -054 -064 -074 -084 -094 -0:4 -0;4 -0<4 -b0 =4 -b0 >4 -b0 ?4 -b0 @4 -b0 A4 -0B4 -sHdlNone\x20(0) C4 -sAddSub\x20(0) D4 -s0 E4 -b0 F4 -b0 G4 +sFull64\x20(0) 34 +144 +154 +164 +174 +s0 84 +b0 94 +b0 :4 +b0 ;4 +b0 <4 +b1001000110100 =4 +0>4 +sFull64\x20(0) ?4 +b1111 @4 +b1000000000000 A4 +1B4 +1C4 +1D4 +sHdlSome\x20(1) E4 +sAddSub\x20(0) F4 +s0 G4 b0 H4 b0 I4 b0 J4 -0K4 -sFull64\x20(0) L4 +b0 K4 +b1001000110100 L4 0M4 -0N4 -0O4 -0P4 -s0 Q4 -b0 R4 -b0 S4 +sFull64\x20(0) N4 +1O4 +1P4 +1Q4 +1R4 +s0 S4 b0 T4 b0 U4 b0 V4 -0W4 -sFull64\x20(0) X4 +b0 W4 +b1001000110100 X4 0Y4 -0Z4 -0[4 -0\4 -s0 ]4 -b0 ^4 -b0 _4 +sFull64\x20(0) Z4 +1[4 +1\4 +1]4 +1^4 +s0 _4 b0 `4 b0 a4 b0 b4 -0c4 -sFull64\x20(0) d4 -b0 e4 -b0 f4 -0g4 -0h4 -0i4 -0j4 -0k4 -0l4 -0m4 -0n4 +b0 c4 +b1001000110100 d4 +0e4 +sFull64\x20(0) f4 +b1111 g4 +b1000000000000 h4 +b0 i4 +b0 j4 +b0 k4 +1l4 +1m4 +1n4 b0 o4 -0p4 -0q4 -0r4 -0s4 -0t4 -0u4 -0v4 -0w4 -b0 x4 -0y4 -0z4 -0{4 -0|4 -0}4 -0~4 -0!5 -0"5 -b0 #5 -b0 $5 -b0 %5 -b0 &5 -b0 '5 +1p4 +sHdlNone\x20(0) q4 +sReady\x20(0) r4 +sHdlNone\x20(0) s4 +sReady\x20(0) t4 +sHdlNone\x20(0) u4 +sReady\x20(0) v4 +sHdlNone\x20(0) w4 +sReady\x20(0) x4 +sHdlNone\x20(0) y4 +sReady\x20(0) z4 +sHdlNone\x20(0) {4 +sReady\x20(0) |4 +sHdlNone\x20(0) }4 +sReady\x20(0) ~4 +sHdlNone\x20(0) !5 +sReady\x20(0) "5 +0#5 +0$5 +0%5 +0&5 +0'5 0(5 -sHdlNone\x20(0) )5 -sAddSub\x20(0) *5 -s0 +5 -b0 ,5 -b0 -5 -b0 .5 -b0 /5 -b0 05 +0)5 +0*5 +0+5 +0,5 +0-5 +0.5 +0/5 +005 015 -sFull64\x20(0) 25 +025 035 045 055 065 -s0 75 -b0 85 -b0 95 -b0 :5 -b0 ;5 -b0 <5 +075 +085 +095 +0:5 +0;5 +0<5 0=5 -sFull64\x20(0) >5 +0>5 0?5 0@5 0A5 0B5 -s0 C5 -b0 D5 -b0 E5 -b0 F5 -b0 G5 -b0 H5 +0C5 +0D5 +0E5 +0F5 +0G5 +0H5 0I5 -sFull64\x20(0) J5 -b0 K5 -b0 L5 +0J5 +0K5 +0L5 0M5 0N5 0O5 0P5 0Q5 0R5 -0S5 -0T5 +b0 S5 +b0 T5 b0 U5 -0V5 +b0 V5 0W5 0X5 -0Y5 -0Z5 -0[5 -0\5 -0]5 +sHdlNone\x20(0) Y5 +sAddSub\x20(0) Z5 +s0 [5 +b0 \5 +b0 ]5 b0 ^5 -0_5 -0`5 +b0 _5 +b0 `5 0a5 -0b5 +sFull64\x20(0) b5 0c5 0d5 0e5 0f5 -b0 g5 +s0 g5 b0 h5 b0 i5 b0 j5 b0 k5 -0l5 -sHdlNone\x20(0) m5 -sAddSub\x20(0) n5 -s0 o5 -b0 p5 -b0 q5 -b0 r5 -b0 s5 +b0 l5 +0m5 +sFull64\x20(0) n5 +0o5 +0p5 +0q5 +0r5 +s0 s5 b0 t5 -0u5 -sFull64\x20(0) v5 -0w5 -0x5 +b0 u5 +b0 v5 +b0 w5 +b0 x5 0y5 -0z5 -s0 {5 +sFull64\x20(0) z5 +b0 {5 b0 |5 b0 }5 -b0 ~5 -b0 !6 -b0 "6 +0~5 +0!6 +0"6 0#6 -sFull64\x20(0) $6 +0$6 0%6 0&6 0'6 -0(6 -s0 )6 -b0 *6 -b0 +6 -b0 ,6 -b0 -6 -b0 .6 +b0 (6 +0)6 +0*6 +0+6 +0,6 +0-6 +0.6 0/6 -sFull64\x20(0) 06 +006 b0 16 -b0 26 +026 036 046 056 @@ -15225,68 +18114,68 @@ b0 26 076 086 096 -0:6 +b0 :6 b0 ;6 -0<6 -0=6 -0>6 +b0 <6 +b0 =6 +b0 >6 0?6 0@6 -0A6 -0B6 -0C6 +sHdlNone\x20(0) A6 +sAddSub\x20(0) B6 +s0 C6 b0 D6 -0E6 -0F6 -0G6 -0H6 +b0 E6 +b0 F6 +b0 G6 +b0 H6 0I6 -0J6 +sFull64\x20(0) J6 0K6 0L6 -b0 M6 -b0 N6 -b0 O6 +0M6 +0N6 +s0 O6 b0 P6 b0 Q6 -0R6 -sHdlNone\x20(0) S6 -sAddSub\x20(0) T6 -s0 U6 -b0 V6 -b0 W6 -b0 X6 -b0 Y6 -b0 Z6 -0[6 -sFull64\x20(0) \6 -0]6 -0^6 -0_6 -0`6 -s0 a6 -b0 b6 +b0 R6 +b0 S6 +b0 T6 +0U6 +sFull64\x20(0) V6 +0W6 +0X6 +0Y6 +0Z6 +s0 [6 +b0 \6 +b0 ]6 +b0 ^6 +b0 _6 +b0 `6 +0a6 +sFull64\x20(0) b6 b0 c6 b0 d6 b0 e6 -b0 f6 +0f6 0g6 -sFull64\x20(0) h6 +0h6 0i6 0j6 0k6 0l6 -s0 m6 +0m6 b0 n6 -b0 o6 -b0 p6 -b0 q6 -b0 r6 +0o6 +0p6 +0q6 +0r6 0s6 -sFull64\x20(0) t6 -b0 u6 -b0 v6 -0w6 +0t6 +0u6 +0v6 +b0 w6 0x6 0y6 0z6 @@ -15294,168 +18183,168 @@ b0 v6 0|6 0}6 0~6 -b0 !7 -0"7 -0#7 -0$7 -0%7 -0&7 +0!7 +b0 "7 +b0 #7 +b0 $7 +b0 %7 +b0 &7 0'7 0(7 -0)7 -b0 *7 -0+7 -0,7 -0-7 -0.7 -0/7 -007 +sHdlNone\x20(0) )7 +sAddSub\x20(0) *7 +s0 +7 +b0 ,7 +b0 -7 +b0 .7 +b0 /7 +b0 07 017 -027 -b0 37 -b0 47 -b0 57 -b0 67 -b0 77 -087 -sHdlNone\x20(0) 97 -sAddSub\x20(0) :7 -s0 ;7 +sFull64\x20(0) 27 +037 +047 +057 +067 +s0 77 +b0 87 +b0 97 +b0 :7 +b0 ;7 b0 <7 -b0 =7 -b0 >7 -b0 ?7 -b0 @7 +0=7 +sFull64\x20(0) >7 +0?7 +0@7 0A7 -sFull64\x20(0) B7 -0C7 -0D7 -0E7 -0F7 -s0 G7 +0B7 +s0 C7 +b0 D7 +b0 E7 +b0 F7 +b0 G7 b0 H7 -b0 I7 -b0 J7 +0I7 +sFull64\x20(0) J7 b0 K7 b0 L7 -0M7 -sFull64\x20(0) N7 +b0 M7 +0N7 0O7 0P7 0Q7 0R7 -s0 S7 -b0 T7 -b0 U7 +0S7 +0T7 +0U7 b0 V7 -b0 W7 -b0 X7 +0W7 +0X7 0Y7 -sFull64\x20(0) Z7 -b0 [7 -b0 \7 +0Z7 +0[7 +0\7 0]7 0^7 -0_7 +b0 _7 0`7 0a7 0b7 0c7 0d7 -b0 e7 +0e7 0f7 0g7 -0h7 -0i7 -0j7 -0k7 -0l7 +b0 h7 +b0 i7 +b0 j7 +b0 k7 +b0 l7 0m7 -b0 n7 -0o7 -0p7 -0q7 -0r7 -0s7 -0t7 -0u7 -0v7 -b0 w7 -b0 x7 -b0 y7 -b0 z7 -b0 {7 +0n7 +sHdlNone\x20(0) o7 +sAddSub\x20(0) p7 +s0 q7 +b0 r7 +b0 s7 +b0 t7 +b0 u7 +b0 v7 +0w7 +sFull64\x20(0) x7 +0y7 +0z7 +0{7 0|7 -sHdlNone\x20(0) }7 -sAddSub\x20(0) ~7 -s0 !8 +s0 }7 +b0 ~7 +b0 !8 b0 "8 b0 #8 b0 $8 -b0 %8 -b0 &8 +0%8 +sFull64\x20(0) &8 0'8 -sFull64\x20(0) (8 +0(8 0)8 0*8 -0+8 -0,8 -s0 -8 +s0 +8 +b0 ,8 +b0 -8 b0 .8 b0 /8 b0 08 -b0 18 -b0 28 -038 -sFull64\x20(0) 48 -058 +018 +sFull64\x20(0) 28 +b0 38 +b0 48 +b0 58 068 078 088 -s0 98 -b0 :8 -b0 ;8 -b0 <8 -b0 =8 +098 +0:8 +0;8 +0<8 +0=8 b0 >8 0?8 -sFull64\x20(0) @8 -b0 A8 -b0 B8 +0@8 +0A8 +0B8 0C8 0D8 0E8 0F8 -0G8 +b0 G8 0H8 0I8 0J8 -b0 K8 +0K8 0L8 0M8 0N8 0O8 -0P8 -0Q8 -0R8 -0S8 +b0 P8 +b0 Q8 +b0 R8 +b0 S8 b0 T8 0U8 0V8 -0W8 -0X8 -0Y8 -0Z8 -0[8 -0\8 +sHdlNone\x20(0) W8 +sAddSub\x20(0) X8 +s0 Y8 +b0 Z8 +b0 [8 +b0 \8 b0 ]8 b0 ^8 -b0 _8 -b0 `8 -b0 a8 +0_8 +sFull64\x20(0) `8 +0a8 0b8 -sHdlNone\x20(0) c8 -sAddSub\x20(0) d8 +0c8 +0d8 s0 e8 b0 f8 b0 g8 @@ -15476,158 +18365,158 @@ b0 u8 b0 v8 0w8 sFull64\x20(0) x8 -0y8 -0z8 -0{8 +b0 y8 +b0 z8 +b0 {8 0|8 -s0 }8 -b0 ~8 -b0 !9 -b0 "9 -b0 #9 -b0 $9 +0}8 +0~8 +0!9 +0"9 +0#9 +0$9 0%9 -sFull64\x20(0) &9 -b0 '9 -b0 (9 +b0 &9 +0'9 +0(9 0)9 0*9 0+9 0,9 0-9 0.9 -0/9 +b0 /9 009 -b0 19 +019 029 039 049 059 069 079 -089 -099 +b0 89 +b0 99 b0 :9 -0;9 -0<9 +b0 ;9 +b0 <9 0=9 0>9 -0?9 -0@9 -0A9 -0B9 +sHdlNone\x20(0) ?9 +sAddSub\x20(0) @9 +s0 A9 +b0 B9 b0 C9 -0D9 -1E9 -sHdlNone\x20(0) F9 -b0 G9 -b0 H9 +b0 D9 +b0 E9 +b0 F9 +0G9 +sFull64\x20(0) H9 0I9 0J9 0K9 0L9 -0M9 -0N9 -0O9 -0P9 -sHdlNone\x20(0) Q9 +s0 M9 +b0 N9 +b0 O9 +b0 P9 +b0 Q9 b0 R9 -b0 S9 -0T9 +0S9 +sFull64\x20(0) T9 0U9 0V9 0W9 0X9 -0Y9 -0Z9 -0[9 -sHdlSome\x20(1) \9 -sAddSub\x20(0) ]9 -s0 ^9 -b0 _9 -b0 `9 +s0 Y9 +b0 Z9 +b0 [9 +b0 \9 +b0 ]9 +b0 ^9 +0_9 +sFull64\x20(0) `9 b0 a9 b0 b9 -b1001000110100 c9 +b0 c9 0d9 -sFull64\x20(0) e9 -1f9 -1g9 -1h9 -1i9 -s0 j9 -b0 k9 +0e9 +0f9 +0g9 +0h9 +0i9 +0j9 +0k9 b0 l9 -b0 m9 -b0 n9 -b1001000110100 o9 +0m9 +0n9 +0o9 0p9 -sFull64\x20(0) q9 -1r9 -1s9 -1t9 -1u9 -s0 v9 -b0 w9 -b0 x9 -b0 y9 -b0 z9 -b1001000110100 {9 +0q9 +0r9 +0s9 +0t9 +b0 u9 +0v9 +0w9 +0x9 +0y9 +0z9 +0{9 0|9 -sFull64\x20(0) }9 -b1111 ~9 -1!: -sHdlNone\x20(0) ": +0}9 +b0 ~9 +b0 !: +b0 ": b0 #: -sHdlNone\x20(0) $: -b0 %: -sCompleted\x20(0) &: -b0 ': -0(: -0): -0*: -0+: -0,: -0-: -0.: +b0 $: +0%: +0&: +sHdlNone\x20(0) ': +sAddSub\x20(0) (: +s0 ): +b0 *: +b0 +: +b0 ,: +b0 -: +b0 .: 0/: -sHdlNone\x20(0) 0: -sAddSub\x20(0) 1: -s0 2: -b0 3: -b0 4: -b0 5: +sFull64\x20(0) 0: +01: +02: +03: +04: +s0 5: b0 6: b0 7: -08: -sFull64\x20(0) 9: -0:: +b0 8: +b0 9: +b0 :: 0;: -0<: +sFull64\x20(0) <: 0=: -s0 >: -b0 ?: -b0 @: -b0 A: +0>: +0?: +0@: +s0 A: b0 B: b0 C: -0D: -sFull64\x20(0) E: -0F: +b0 D: +b0 E: +b0 F: 0G: -0H: -0I: -s0 J: +sFull64\x20(0) H: +b0 I: +b0 J: b0 K: -b0 L: -b0 M: -b0 N: -b0 O: +0L: +0M: +0N: +0O: 0P: -sFull64\x20(0) Q: -b0 R: -b0 S: -0T: +0Q: +0R: +0S: +b0 T: 0U: 0V: 0W: @@ -15635,8 +18524,8 @@ b0 S: 0Y: 0Z: 0[: -b0 \: -0]: +0\: +b0 ]: 0^: 0_: 0`: @@ -15644,93 +18533,93 @@ b0 \: 0b: 0c: 0d: -b0 e: -0f: -0g: -0h: -0i: -0j: +0e: +b0 f: +b0 g: +b0 h: +b0 i: +b0 j: 0k: 0l: -0m: -1n: -sHdlNone\x20(0) o: +sHdlNone\x20(0) m: +sAddSub\x20(0) n: +s0 o: b0 p: -sCompleted\x20(0) q: +b0 q: b0 r: -0s: -0t: +b0 s: +b0 t: 0u: -0v: +sFull64\x20(0) v: 0w: 0x: 0y: 0z: -0{: -1|: -sHdlNone\x20(0) }: +s0 {: +b0 |: +b0 }: b0 ~: b0 !; -0"; +b0 "; 0#; -0$; +sFull64\x20(0) $; 0%; 0&; 0'; 0(; -0); -sHdlNone\x20(0) *; +s0 ); +b0 *; b0 +; b0 ,; -0-; -0.; +b0 -; +b0 .; 0/; -00; -01; -02; -03; +sFull64\x20(0) 0; +b0 1; +b0 2; +b0 3; 04; -sHdlSome\x20(1) 5; -sAddSub\x20(0) 6; -s0 7; -b0 8; -b0 9; -b0 :; -b0 ;; -b1001000110100 <; +05; +06; +07; +08; +09; +0:; +0;; +b0 <; 0=; -sFull64\x20(0) >; -1?; -1@; -1A; -1B; -s0 C; -b0 D; +0>; +0?; +0@; +0A; +0B; +0C; +0D; b0 E; -b0 F; -b0 G; -b1001000110100 H; +0F; +0G; +0H; 0I; -sFull64\x20(0) J; -1K; -1L; -1M; -1N; -s0 O; -b0 P; -b0 Q; +0J; +0K; +0L; +0M; +b0 N; +0O; +1P; +sHdlNone\x20(0) Q; b0 R; b0 S; -b1001000110100 T; +0T; 0U; -sFull64\x20(0) V; -b1111 W; -1X; -sHdlNone\x20(0) Y; -b0 Z; -sHdlNone\x20(0) [; -b0 \; -sCompleted\x20(0) ]; +0V; +0W; +0X; +0Y; +0Z; +0[; +sHdlNone\x20(0) \; +b0 ]; b0 ^; 0_; 0`; @@ -15740,159 +18629,159 @@ b0 ^; 0d; 0e; 0f; -0g; -1h; -sHdlNone\x20(0) i; +sHdlSome\x20(1) g; +sAddSub\x20(0) h; +s0 i; b0 j; -1k; -sHdlSome\x20(1) l; +b0 k; +b0 l; b0 m; -1n; +b1001000110100 n; 0o; -0p; -0q; -0r; -0s; -0t; -0u; -0v; -0w; -0x; -0y; -0z; +sFull64\x20(0) p; +1q; +1r; +1s; +1t; +s0 u; +b0 v; +b0 w; +b0 x; +b0 y; +b1001000110100 z; 0{; -0|; -0}; -0~; -sHdlNone\x20(0) !< -b0 "< -0#< -1$< -0%< -0&< -1'< -0(< +sFull64\x20(0) |; +1}; +1~; +1!< +1"< +s0 #< +b0 $< +b0 %< +b0 &< +b0 '< +b1001000110100 (< 0)< -1*< -b0 +< -0,< +sFull64\x20(0) *< +b1111 +< +b1000000000000 ,< 1-< -0.< -0/< -10< -01< -02< -13< -b0 4< +sHdlNone\x20(0) .< +b0 /< +sHdlNone\x20(0) 0< +b0 1< +sCompleted\x20(0) 2< +b0 3< +04< 05< -16< -b0 7< +06< +07< 08< -19< +09< 0:< 0;< -1<< -0=< -0>< -1?< +sHdlNone\x20(0) << +sAddSub\x20(0) =< +s0 >< +b0 ?< b0 @< -0A< -1B< -0C< +b0 A< +b0 B< +b0 C< 0D< -1E< +sFull64\x20(0) E< 0F< 0G< -1H< -b0 I< -0J< -1K< +0H< +0I< +s0 J< +b0 K< b0 L< -0M< -1N< +b0 M< +b0 N< b0 O< -sHdlSome\x20(1) P< -b0 Q< +0P< +sFull64\x20(0) Q< 0R< -1S< -sHdlNone\x20(0) T< -b0 U< -1V< -sHdlSome\x20(1) W< +0S< +0T< +0U< +s0 V< +b0 W< b0 X< -1Y< -sHdlSome\x20(1) Z< -sAddSub\x20(0) [< -s0 \< -b0 ]< +b0 Y< +b0 Z< +b0 [< +0\< +sFull64\x20(0) ]< b0 ^< b0 _< b0 `< -b1001000110100 a< +0a< 0b< -sFull64\x20(0) c< -1d< -1e< -1f< -1g< -s0 h< +0c< +0d< +0e< +0f< +0g< +0h< b0 i< -b0 j< -b0 k< -b0 l< -b1001000110100 m< +0j< +0k< +0l< +0m< 0n< -sFull64\x20(0) o< -1p< -1q< -1r< -1s< -s0 t< -b0 u< -b0 v< -b0 w< -b0 x< -b1001000110100 y< +0o< +0p< +0q< +b0 r< +0s< +0t< +0u< +0v< +0w< +0x< +0y< 0z< -sFull64\x20(0) {< -b1111 |< -sHdlSome\x20(1) }< -sAddSub\x20(0) ~< -s0 != -b0 "= -b0 #= -b0 $= -b0 %= -b1001000110100 &= +1{< +sHdlNone\x20(0) |< +b0 }< +sCompleted\x20(0) ~< +b0 != +0"= +0#= +0$= +0%= +0&= 0'= -sFull64\x20(0) (= -1)= -1*= -1+= -1,= -s0 -= +0(= +0)= +sHdlNone\x20(0) *= +sAddSub\x20(0) += +s0 ,= +b0 -= b0 .= b0 /= b0 0= b0 1= -b1001000110100 2= -03= -sFull64\x20(0) 4= -15= -16= -17= -18= -s0 9= +02= +sFull64\x20(0) 3= +04= +05= +06= +07= +s0 8= +b0 9= b0 := b0 ;= b0 <= b0 == -b1001000110100 >= -0?= -sFull64\x20(0) @= -b1111 A= -sHdlSome\x20(1) B= -sLogical\x20(2) C= +0>= +sFull64\x20(0) ?= +0@= +0A= +0B= +0C= s0 D= b0 E= b0 F= @@ -15901,770 +18790,770 @@ b0 H= b0 I= 0J= sFull64\x20(0) K= -0L= -1M= -1N= +b0 L= +b0 M= +b0 N= 0O= -s0 P= -b0 Q= -b0 R= -b0 S= -b0 T= -b0 U= +0P= +0Q= +0R= +0S= +0T= +0U= 0V= -sFull64\x20(0) W= +b0 W= 0X= -1Y= -1Z= +0Y= +0Z= 0[= -s0 \= -b0 ]= -b0 ^= -b0 _= +0\= +0]= +0^= +0_= b0 `= -b0 a= +0a= 0b= -sFull64\x20(0) c= -b110 d= -sHdlSome\x20(1) e= -sLogical\x20(2) f= -s0 g= -b0 h= -b0 i= +0c= +0d= +0e= +0f= +0g= +0h= +0i= b0 j= -b0 k= +0k= b0 l= -0m= -sFull64\x20(0) n= +b0 m= +b0 n= 0o= -1p= -1q= +0p= +0q= 0r= -s0 s= -b0 t= -b0 u= -b0 v= -b0 w= +0s= +0t= +0u= +0v= +0w= b0 x= 0y= -sFull64\x20(0) z= +0z= 0{= -1|= +0|= 1}= -0~= -s0 !> -b0 "> -b0 #> -b0 $> -b0 %> -b0 &> +1~= +0!> +0"> +0#> +0$> +0%> +1&> 0'> -sFull64\x20(0) (> -b110 )> +0(> +0)> 0*> -1+> -sHdlNone\x20(0) ,> -b0 -> -b0 .> -0/> +0+> +0,> +0-> +0.> +1/> 00> 01> -02> +b0 2> 03> -04> -05> -06> -sHdlNone\x20(0) 7> -b0 8> -b0 9> +b0 4> +b0 5> +b0 6> +07> +08> +09> 0:> 0;> 0<> 0=> 0>> 0?> -0@> +b0 @> 0A> -sHdlSome\x20(1) B> -sLogical\x20(2) C> -s0 D> -b0 E> -b0 F> -b0 G> -b0 H> -b0 I> +0B> +0C> +0D> +1E> +1F> +0G> +0H> +0I> 0J> -sFull64\x20(0) K> -0L> -1M> -1N> +0K> +1L> +0M> +0N> 0O> -s0 P> -b0 Q> -b0 R> -b0 S> -b0 T> -b0 U> +0P> +0Q> +0R> +0S> +0T> +1U> 0V> -sFull64\x20(0) W> -0X> -1Y> -1Z> -0[> -s0 \> -b0 ]> -b0 ^> -b0 _> -b0 `> -b0 a> +0W> +1X> +sHdlNone\x20(0) Y> +b0 Z> +b0 [> +0\> +0]> +0^> +0_> +0`> +0a> 0b> -sFull64\x20(0) c> -b110 d> -1e> -sHdlNone\x20(0) f> -b0 g> -sHdlNone\x20(0) h> -b0 i> -sCompleted\x20(0) j> -b0 k> +0c> +sHdlNone\x20(0) d> +b0 e> +b0 f> +0g> +0h> +0i> +0j> +0k> 0l> 0m> 0n> -0o> -0p> -0q> -0r> -0s> -0t> -1u> -sHdlNone\x20(0) v> -b0 w> -b0 x> -0y> -0z> -0{> -0|> -0}> -0~> -0!? -0"? -sHdlNone\x20(0) #? -b0 $? -b0 %? -0&? -0'? -0(? -0)? -0*? -0+? -0,? -0-? -sHdlSome\x20(1) .? -sLogical\x20(2) /? -s0 0? -b0 1? -b0 2? -b0 3? -b0 4? -b0 5? -06? -sFull64\x20(0) 7? -08? -19? -1:? -0;? -s0 ? -b0 ?? -b0 @? -b0 A? +sHdlSome\x20(1) o> +sAddSub\x20(0) p> +s0 q> +b0 r> +b0 s> +b0 t> +b0 u> +b1001000110100 v> +0w> +sFull64\x20(0) x> +1y> +1z> +1{> +1|> +s0 }> +b0 ~> +b0 !? +b0 "? +b0 #? +b1001000110100 $? +0%? +sFull64\x20(0) &? +1'? +1(? +1)? +1*? +s0 +? +b0 ,? +b0 -? +b0 .? +b0 /? +b1001000110100 0? +01? +sFull64\x20(0) 2? +b1111 3? +b1000000000000 4? +15? +sHdlNone\x20(0) 6? +b0 7? +sHdlNone\x20(0) 8? +b0 9? +sCompleted\x20(0) :? +b0 ;? +0? +0?? +0@? +0A? 0B? -sFull64\x20(0) C? -0D? -1E? +0C? +sPowerISA\x20(0) D? +0E? 1F? -0G? -s0 H? -b0 I? -b0 J? +sHdlNone\x20(0) G? +b0 H? +1I? +sHdlSome\x20(1) J? b0 K? -b0 L? -b0 M? +1L? +0M? 0N? -sFull64\x20(0) O? -b110 P? -1Q? -sHdlNone\x20(0) R? -b0 S? -sHdlNone\x20(0) T? -b0 U? -sCompleted\x20(0) V? -b0 W? +0O? +0P? +0Q? +0R? +0S? +0T? +0U? +0V? +0W? 0X? 0Y? 0Z? 0[? 0\? -0]? -0^? +sHdlNone\x20(0) ]? +b0 ^? 0_? -sHdlNone\x20(0) `? -sAddSub\x20(0) a? -s0 b? -b0 c? -b0 d? -b0 e? -b0 f? +1`? +0a? +0b? +1c? +0d? +0e? +1f? b0 g? 0h? -sFull64\x20(0) i? +1i? 0j? 0k? -0l? +1l? 0m? -s0 n? -b0 o? +0n? +1o? b0 p? -b0 q? -b0 r? +0q? +1r? b0 s? 0t? -sFull64\x20(0) u? +1u? 0v? 0w? -0x? +1x? 0y? -s0 z? -b0 {? +0z? +1{? b0 |? -b0 }? -b0 ~? -b0 !@ +0}? +1~? +0!@ 0"@ -sFull64\x20(0) #@ -b0 $@ -b0 %@ -0&@ -0'@ +1#@ +0$@ +0%@ +1&@ +b0 '@ 0(@ -0)@ -0*@ +1)@ +b0 *@ 0+@ -0,@ -0-@ -b0 .@ -0/@ +1,@ +b0 -@ +sHdlSome\x20(1) .@ +b0 /@ 00@ -01@ -02@ -03@ -04@ -05@ -06@ -b0 7@ -08@ -09@ -0:@ -0;@ -0<@ -0=@ -0>@ -0?@ -1@@ -sHdlNone\x20(0) A@ -b0 B@ -sCompleted\x20(0) C@ -b0 D@ -0E@ -0F@ -0G@ -0H@ -0I@ -0J@ -0K@ +11@ +sHdlNone\x20(0) 2@ +b0 3@ +14@ +sHdlSome\x20(1) 5@ +b0 6@ +17@ +sHdlSome\x20(1) 8@ +sAddSub\x20(0) 9@ +s0 :@ +b0 ;@ +b0 <@ +b0 =@ +b0 >@ +b1001000110100 ?@ +0@@ +sFull64\x20(0) A@ +1B@ +1C@ +1D@ +1E@ +s0 F@ +b0 G@ +b0 H@ +b0 I@ +b0 J@ +b1001000110100 K@ 0L@ -sHdlNone\x20(0) M@ -sReady\x20(0) N@ -sAddSub\x20(0) O@ -s0 P@ -b0 Q@ -b0 R@ +sFull64\x20(0) M@ +1N@ +1O@ +1P@ +1Q@ +s0 R@ b0 S@ b0 T@ b0 U@ -0V@ -sFull64\x20(0) W@ +b0 V@ +b1001000110100 W@ 0X@ -0Y@ -0Z@ -0[@ -s0 \@ -b0 ]@ -b0 ^@ +sFull64\x20(0) Y@ +b1111 Z@ +b1000000000000 [@ +sHdlSome\x20(1) \@ +sAddSub\x20(0) ]@ +s0 ^@ b0 _@ b0 `@ b0 a@ -0b@ -sFull64\x20(0) c@ +b0 b@ +b1001000110100 c@ 0d@ -0e@ -0f@ -0g@ -s0 h@ -b0 i@ -b0 j@ +sFull64\x20(0) e@ +1f@ +1g@ +1h@ +1i@ +s0 j@ b0 k@ b0 l@ b0 m@ -0n@ -sFull64\x20(0) o@ -b0 p@ -0q@ -0r@ -0s@ -sHdlNone\x20(0) t@ -sReady\x20(0) u@ -sAddSub\x20(0) v@ -s0 w@ +b0 n@ +b1001000110100 o@ +0p@ +sFull64\x20(0) q@ +1r@ +1s@ +1t@ +1u@ +s0 v@ +b0 w@ b0 x@ b0 y@ b0 z@ -b0 {@ -b0 |@ -0}@ -sFull64\x20(0) ~@ -0!A -0"A -0#A -0$A -s0 %A +b1001000110100 {@ +0|@ +sFull64\x20(0) }@ +b1111 ~@ +b1000000000000 !A +sHdlSome\x20(1) "A +sAddSub\x20(0) #A +s0 $A +b0 %A b0 &A b0 'A b0 (A -b0 )A -b0 *A -0+A -sFull64\x20(0) ,A -0-A -0.A -0/A -00A -s0 1A +b1001000110100 )A +0*A +sFull64\x20(0) +A +1,A +1-A +1.A +1/A +s0 0A +b0 1A b0 2A b0 3A b0 4A -b0 5A -b0 6A -07A -sFull64\x20(0) 8A -b0 9A -0:A -0;A -0A -sAddSub\x20(0) ?A -s0 @A -b0 AA -b0 BA -b0 CA -b0 DA -b0 EA -0FA -sFull64\x20(0) GA -0HA -0IA -0JA -0KA -s0 LA -b0 MA -b0 NA -b0 OA -b0 PA -b0 QA +b1001000110100 5A +06A +sFull64\x20(0) 7A +18A +19A +1:A +1;A +s0 A +b0 ?A +b0 @A +b1001000110100 AA +0BA +sFull64\x20(0) CA +b1111 DA +sHdlSome\x20(1) EA +sLogical\x20(2) FA +s0 GA +b0 HA +b0 IA +b0 JA +b0 KA +b0 LA +0MA +sFull64\x20(0) NA +0OA +1PA +1QA 0RA -sFull64\x20(0) SA -0TA -0UA -0VA -0WA -s0 XA -b0 YA -b0 ZA -b0 [A -b0 \A -b0 ]A +s0 SA +b0 TA +b0 UA +b0 VA +b0 WA +b0 XA +0YA +sFull64\x20(0) ZA +0[A +1\A +1]A 0^A -sFull64\x20(0) _A +s0 _A b0 `A -0aA -0bA -0cA -sHdlNone\x20(0) dA -sReady\x20(0) eA -sAddSub\x20(0) fA -s0 gA -b0 hA -b0 iA -b0 jA -b0 kA +b0 aA +b0 bA +b0 cA +b0 dA +0eA +sFull64\x20(0) fA +b110 gA +b1000000000100 hA +sHdlSome\x20(1) iA +sLogical\x20(2) jA +s0 kA b0 lA -0mA -sFull64\x20(0) nA -0oA -0pA +b0 mA +b0 nA +b0 oA +b0 pA 0qA -0rA -s0 sA -b0 tA -b0 uA -b0 vA -b0 wA +sFull64\x20(0) rA +0sA +1tA +1uA +0vA +s0 wA b0 xA -0yA -sFull64\x20(0) zA -0{A -0|A +b0 yA +b0 zA +b0 {A +b0 |A 0}A -0~A -s0 !B -b0 "B -b0 #B -b0 $B -b0 %B +sFull64\x20(0) ~A +0!B +1"B +1#B +0$B +s0 %B b0 &B -0'B -sFull64\x20(0) (B +b0 'B +b0 (B b0 )B -0*B +b0 *B 0+B -0,B -sHdlNone\x20(0) -B -sReady\x20(0) .B -sAddSub\x20(0) /B -s0 0B -b0 1B +sFull64\x20(0) ,B +b110 -B +b1000000000100 .B +sHdlSome\x20(1) /B +sLogical\x20(2) 0B +s0 1B b0 2B b0 3B b0 4B b0 5B -06B -sFull64\x20(0) 7B -08B +b0 6B +07B +sFull64\x20(0) 8B 09B -0:B -0;B -s0 B b0 ?B b0 @B b0 AB -0BB -sFull64\x20(0) CB -0DB +b0 BB +0CB +sFull64\x20(0) DB 0EB -0FB -0GB -s0 HB -b0 IB +1FB +1GB +0HB +s0 IB b0 JB b0 KB b0 LB b0 MB -0NB -sFull64\x20(0) OB -b0 PB -0QB +b0 NB +0OB +sFull64\x20(0) PB +b110 QB 0RB -0SB +1SB sHdlNone\x20(0) TB -sReady\x20(0) UB -sAddSub\x20(0) VB -s0 WB -b0 XB -b0 YB -b0 ZB -b0 [B -b0 \B +b0 UB +b0 VB +0WB +0XB +0YB +0ZB +0[B +0\B 0]B -sFull64\x20(0) ^B -0_B -0`B -0aB +0^B +sHdlNone\x20(0) _B +b0 `B +b0 aB 0bB -s0 cB -b0 dB -b0 eB -b0 fB -b0 gB -b0 hB +0cB +0dB +0eB +0fB +0gB +0hB 0iB -sFull64\x20(0) jB -0kB -0lB -0mB -0nB -s0 oB +sHdlSome\x20(1) jB +sLogical\x20(2) kB +s0 lB +b0 mB +b0 nB +b0 oB b0 pB b0 qB -b0 rB -b0 sB -b0 tB -0uB -sFull64\x20(0) vB -b0 wB -0xB -0yB -0zB -sHdlNone\x20(0) {B -sReady\x20(0) |B -sAddSub\x20(0) }B -s0 ~B -b0 !C -b0 "C -b0 #C -b0 $C -b0 %C -0&C -sFull64\x20(0) 'C -0(C -0)C -0*C -0+C -s0 ,C -b0 -C -b0 .C -b0 /C -b0 0C -b0 1C -02C -sFull64\x20(0) 3C -04C -05C -06C +0rB +sFull64\x20(0) sB +0tB +1uB +1vB +0wB +s0 xB +b0 yB +b0 zB +b0 {B +b0 |B +b0 }B +0~B +sFull64\x20(0) !C +0"C +1#C +1$C +0%C +s0 &C +b0 'C +b0 (C +b0 )C +b0 *C +b0 +C +0,C +sFull64\x20(0) -C +b110 .C +b1000000000100 /C +10C +sHdlNone\x20(0) 1C +b0 2C +sHdlNone\x20(0) 3C +b0 4C +sCompleted\x20(0) 5C +b0 6C 07C -s0 8C -b0 9C -b0 :C -b0 ;C -b0 C -sFull64\x20(0) ?C -b0 @C -0AC -0BC -0CC -sHdlNone\x20(0) DC -sReady\x20(0) EC -sAddSub\x20(0) FC -s0 GC -b0 HC -b0 IC -b0 JC -b0 KC -b0 LC -0MC -sFull64\x20(0) NC -0OC +sPowerISA\x20(0) ?C +0@C +1AC +sHdlNone\x20(0) BC +b0 CC +b0 DC +0EC +0FC +0GC +0HC +0IC +0JC +0KC +0LC +sHdlNone\x20(0) MC +b0 NC +b0 OC 0PC 0QC 0RC -s0 SC -b0 TC -b0 UC -b0 VC -b0 WC -b0 XC -0YC -sFull64\x20(0) ZC -0[C -0\C -0]C -0^C -s0 _C -b0 `C -b0 aC -b0 bC -b0 cC -b0 dC +0SC +0TC +0UC +0VC +0WC +sHdlSome\x20(1) XC +sLogical\x20(2) YC +s0 ZC +b0 [C +b0 \C +b0 ]C +b0 ^C +b0 _C +0`C +sFull64\x20(0) aC +0bC +1cC +1dC 0eC -sFull64\x20(0) fC +s0 fC b0 gC -0hC -0iC -0jC -sHdlSome\x20(1) kC -b0 lC -sHdlNone\x20(0) mC -b0 nC -sHdlSome\x20(1) oC -b1 pC -sHdlNone\x20(0) qC -b0 rC -sHdlSome\x20(1) sC +b0 hC +b0 iC +b0 jC +b0 kC +0lC +sFull64\x20(0) mC +0nC +1oC +1pC +0qC +s0 rC +b0 sC b0 tC -sHdlNone\x20(0) uC +b0 uC b0 vC -sHdlSome\x20(1) wC -b10 xC -sHdlNone\x20(0) yC -b0 zC -sHdlSome\x20(1) {C -b11 |C +b0 wC +0xC +sFull64\x20(0) yC +b110 zC +b1000000000100 {C +1|C sHdlNone\x20(0) }C b0 ~C -sHdlSome\x20(1) !D -b10 "D -sHdlNone\x20(0) #D +sHdlNone\x20(0) !D +b0 "D +sCompleted\x20(0) #D b0 $D -sHdlSome\x20(1) %D -b0 &D -sHdlNone\x20(0) 'D -b0 (D -sHdlSome\x20(1) )D -b100 *D -sHdlNone\x20(0) +D -b0 ,D -sHdlSome\x20(1) -D -b101 .D -sHdlNone\x20(0) /D +0%D +0&D +0'D +0(D +0)D +0*D +0+D +0,D +sHdlNone\x20(0) -D +sAddSub\x20(0) .D +s0 /D b0 0D -sHdlSome\x20(1) 1D -b100 2D -sHdlNone\x20(0) 3D +b0 1D +b0 2D +b0 3D b0 4D -sHdlSome\x20(1) 5D -b110 6D -sHdlNone\x20(0) 7D -b0 8D -sHdlSome\x20(1) 9D -b111 :D -sHdlNone\x20(0) ;D +05D +sFull64\x20(0) 6D +07D +08D +09D +0:D +s0 ;D b0 D -sHdlNone\x20(0) ?D +b0 =D +b0 >D +b0 ?D b0 @D -sHdlSome\x20(1) AD -b100 BD -sHdlNone\x20(0) CD -b0 DD -sHdlSome\x20(1) ED -b0 FD -sHdlNone\x20(0) GD +0AD +sFull64\x20(0) BD +0CD +0DD +0ED +0FD +s0 GD b0 HD -sHdlSome\x20(1) ID +b0 ID b0 JD -sHdlNone\x20(0) KD +b0 KD b0 LD -1MD -sHdlSome\x20(1) ND -sReady\x20(0) OD -sLogical\x20(2) PD -s0 QD -b0 RD -b0 SD -b0 TD -b0 UD -b0 VD +0MD +sFull64\x20(0) ND +b0 OD +b0 PD +b0 QD +0RD +0SD +0TD +0UD +0VD 0WD -sFull64\x20(0) XD +0XD 0YD -1ZD -1[D +b0 ZD +0[D 0\D -s0 ]D -b0 ^D -b0 _D -b0 `D -b0 aD -b0 bD -0cD -sFull64\x20(0) dD +0]D +0^D +0_D +0`D +0aD +0bD +b0 cD +0dD 0eD -1fD -1gD +0fD +0gD 0hD -s0 iD -b0 jD -b0 kD -b0 lD -b0 mD +0iD +0jD +0kD +1lD +sHdlNone\x20(0) mD b0 nD -0oD -sFull64\x20(0) pD -b110 qD -1rD -1sD -1tD -sHdlSome\x20(1) uD -sLogical\x20(2) vD -s0 wD -b0 xD +sCompleted\x20(0) oD +b0 pD +0qD +0rD +0sD +0tD +0uD +0vD +0wD +0xD b0 yD -b0 zD -b0 {D +0zD +0{D b0 |D 0}D -sFull64\x20(0) ~D +0~D 0!E -1"E -1#E +0"E +0#E 0$E -s0 %E -b0 &E +0%E +0&E b0 'E -b0 (E -b0 )E +0(E +0)E b0 *E 0+E -sFull64\x20(0) ,E +0,E 0-E -1.E -1/E +0.E +0/E 00E -s0 1E -b0 2E +01E +02E b0 3E -b0 4E -b0 5E +04E +05E b0 6E 07E -sFull64\x20(0) 8E -b110 9E -b0 :E -b0 ;E -b0 E -1?E -b0 @E -1AE -sHdlNone\x20(0) BE -sReady\x20(0) CE -sHdlNone\x20(0) DE -sReady\x20(0) EE -sHdlNone\x20(0) FE -sReady\x20(0) GE -sHdlNone\x20(0) HE -sReady\x20(0) IE -sHdlNone\x20(0) JE -sReady\x20(0) KE -sHdlNone\x20(0) LE -sReady\x20(0) ME -sHdlNone\x20(0) NE -sReady\x20(0) OE -sHdlNone\x20(0) PE -sReady\x20(0) QE -0RE -0SE -0TE +08E +09E +0:E +0;E +0E +b0 ?E +0@E +0AE +b0 BE +0CE +0DE +0EE +0FE +0GE +0HE +0IE +0JE +1KE +1LE +1ME +1NE +1OE +1PE +1QE +1RE +1SE +b0 TE 0UE 0VE -0WE +b0 WE 0XE 0YE 0ZE @@ -16673,10 +19562,10 @@ sReady\x20(0) QE 0]E 0^E 0_E -0`E +b0 `E 0aE 0bE -0cE +b0 cE 0dE 0eE 0fE @@ -16685,10 +19574,10 @@ sReady\x20(0) QE 0iE 0jE 0kE -0lE +b0 lE 0mE 0nE -0oE +b0 oE 0pE 0qE 0rE @@ -16697,416 +19586,416 @@ sReady\x20(0) QE 0uE 0vE 0wE -0xE +b0 xE 0yE 0zE -0{E +b0 {E 0|E 0}E 0~E 0!F 0"F 0#F -b0 $F -b0 %F -b0 &F -b0 'F -0(F -sHdlNone\x20(0) )F -sAddSub\x20(0) *F -s0 +F -b0 ,F -b0 -F -b0 .F -b0 /F -b0 0F -01F -sFull64\x20(0) 2F -03F -04F -05F -06F -s0 7F -b0 8F -b0 9F -b0 :F -b0 ;F -b0 F -0?F -0@F -0AF -0BF -s0 CF -b0 DF -b0 EF -b0 FF -b0 GF -b0 HF +s0 >F +b0 ?F +b0 @F +b0 AF +b0 BF +b0 CF +0DF +sFull64\x20(0) EF +0FF +0GF +0HF 0IF -sFull64\x20(0) JF +s0 JF b0 KF b0 LF -0MF -0NF -0OF +b0 MF +b0 NF +b0 OF 0PF -0QF -0RF -0SF +sFull64\x20(0) QF +b0 RF +b0 SF 0TF -b0 UF +0UF 0VF -0WF -0XF -0YF -0ZF -0[F -0\F -0]F +sHdlNone\x20(0) WF +sReady\x20(0) XF +sAddSub\x20(0) YF +s0 ZF +b0 [F +b0 \F +b0 ]F b0 ^F -0_F +b0 _F 0`F -0aF +sFull64\x20(0) aF 0bF 0cF 0dF 0eF -0fF +s0 fF b0 gF b0 hF b0 iF b0 jF b0 kF 0lF -sHdlNone\x20(0) mF -sAddSub\x20(0) nF -s0 oF -b0 pF -b0 qF -b0 rF +sFull64\x20(0) mF +0nF +0oF +0pF +0qF +s0 rF b0 sF b0 tF -0uF -sFull64\x20(0) vF -0wF +b0 uF +b0 vF +b0 wF 0xF -0yF -0zF -s0 {F -b0 |F -b0 }F -b0 ~F -b0 !G -b0 "G -0#G -sFull64\x20(0) $G -0%G -0&G -0'G -0(G -s0 )G -b0 *G -b0 +G -b0 ,G -b0 -G -b0 .G +sFull64\x20(0) yF +b0 zF +b0 {F +0|F +0}F +0~F +sHdlNone\x20(0) !G +sReady\x20(0) "G +sAddSub\x20(0) #G +s0 $G +b0 %G +b0 &G +b0 'G +b0 (G +b0 )G +0*G +sFull64\x20(0) +G +0,G +0-G +0.G 0/G -sFull64\x20(0) 0G +s0 0G b0 1G b0 2G -03G -04G -05G +b0 3G +b0 4G +b0 5G 06G -07G +sFull64\x20(0) 7G 08G 09G 0:G -b0 ;G -0G -0?G -0@G -0AG +0;G +s0 G +b0 ?G +b0 @G +b0 AG 0BG -0CG +sFull64\x20(0) CG b0 DG -0EG +b0 EG 0FG 0GG 0HG -0IG -0JG -0KG -0LG +sHdlNone\x20(0) IG +sReady\x20(0) JG +sAddSub\x20(0) KG +s0 LG b0 MG b0 NG b0 OG b0 PG b0 QG 0RG -sHdlNone\x20(0) SG -sAddSub\x20(0) TG -s0 UG -b0 VG -b0 WG -b0 XG +sFull64\x20(0) SG +0TG +0UG +0VG +0WG +s0 XG b0 YG b0 ZG -0[G -sFull64\x20(0) \G -0]G +b0 [G +b0 \G +b0 ]G 0^G -0_G +sFull64\x20(0) _G 0`G -s0 aG -b0 bG -b0 cG -b0 dG +0aG +0bG +0cG +s0 dG b0 eG b0 fG -0gG -sFull64\x20(0) hG -0iG +b0 gG +b0 hG +b0 iG 0jG -0kG -0lG -s0 mG -b0 nG -b0 oG -b0 pG -b0 qG -b0 rG -0sG -sFull64\x20(0) tG +sFull64\x20(0) kG +b0 lG +b0 mG +0nG +0oG +0pG +sHdlNone\x20(0) qG +sReady\x20(0) rG +sAddSub\x20(0) sG +s0 tG b0 uG b0 vG -0wG -0xG -0yG +b0 wG +b0 xG +b0 yG 0zG -0{G +sFull64\x20(0) {G 0|G 0}G 0~G -b0 !H -0"H -0#H -0$H -0%H -0&H -0'H +0!H +s0 "H +b0 #H +b0 $H +b0 %H +b0 &H +b0 'H 0(H -0)H -b0 *H +sFull64\x20(0) )H +0*H 0+H 0,H 0-H -0.H -0/H -00H -01H -02H +s0 .H +b0 /H +b0 0H +b0 1H +b0 2H b0 3H -b0 4H -b0 5H +04H +sFull64\x20(0) 5H b0 6H b0 7H 08H -sHdlNone\x20(0) 9H -sAddSub\x20(0) :H -s0 ;H -b0 H +09H +0:H +sHdlNone\x20(0) ;H +sReady\x20(0) H b0 ?H b0 @H -0AH -sFull64\x20(0) BH -0CH +b0 AH +b0 BH +b0 CH 0DH -0EH +sFull64\x20(0) EH 0FH -s0 GH -b0 HH -b0 IH -b0 JH +0GH +0HH +0IH +s0 JH b0 KH b0 LH -0MH -sFull64\x20(0) NH -0OH +b0 MH +b0 NH +b0 OH 0PH -0QH +sFull64\x20(0) QH 0RH -s0 SH -b0 TH -b0 UH -b0 VH +0SH +0TH +0UH +s0 VH b0 WH b0 XH -0YH -sFull64\x20(0) ZH +b0 YH +b0 ZH b0 [H -b0 \H -0]H -0^H -0_H +0\H +sFull64\x20(0) ]H +b0 ^H +b0 _H 0`H 0aH 0bH -0cH -0dH -b0 eH -0fH -0gH -0hH -0iH -0jH -0kH +sHdlNone\x20(0) cH +sReady\x20(0) dH +sAddSub\x20(0) eH +s0 fH +b0 gH +b0 hH +b0 iH +b0 jH +b0 kH 0lH -0mH -b0 nH +sFull64\x20(0) mH +0nH 0oH 0pH 0qH -0rH -0sH -0tH -0uH -0vH +s0 rH +b0 sH +b0 tH +b0 uH +b0 vH b0 wH -b0 xH -b0 yH -b0 zH -b0 {H +0xH +sFull64\x20(0) yH +0zH +0{H 0|H -sHdlNone\x20(0) }H -sAddSub\x20(0) ~H -s0 !I +0}H +s0 ~H +b0 !I b0 "I b0 #I b0 $I b0 %I -b0 &I -0'I -sFull64\x20(0) (I -0)I +0&I +sFull64\x20(0) 'I +b0 (I +b0 )I 0*I 0+I 0,I -s0 -I -b0 .I -b0 /I -b0 0I +sHdlNone\x20(0) -I +sReady\x20(0) .I +sAddSub\x20(0) /I +s0 0I b0 1I b0 2I -03I -sFull64\x20(0) 4I -05I +b0 3I +b0 4I +b0 5I 06I -07I +sFull64\x20(0) 7I 08I -s0 9I -b0 :I -b0 ;I -b0 I -0?I -sFull64\x20(0) @I +b0 ?I +b0 @I b0 AI -b0 BI -0CI +0BI +sFull64\x20(0) CI 0DI 0EI 0FI 0GI -0HI -0II -0JI +s0 HI +b0 II +b0 JI b0 KI -0LI -0MI +b0 LI +b0 MI 0NI -0OI -0PI -0QI +sFull64\x20(0) OI +b0 PI +b0 QI 0RI 0SI -b0 TI -0UI -0VI -0WI -0XI -0YI -0ZI -0[I -0\I -b0 ]I +0TI +sHdlSome\x20(1) UI +b0 VI +sHdlNone\x20(0) WI +b0 XI +sHdlSome\x20(1) YI +b1 ZI +sHdlNone\x20(0) [I +b0 \I +sHdlSome\x20(1) ]I b0 ^I -b0 _I +sHdlNone\x20(0) _I b0 `I -b0 aI -0bI +sHdlSome\x20(1) aI +b10 bI sHdlNone\x20(0) cI -sAddSub\x20(0) dI -s0 eI -b0 fI -b0 gI +b0 dI +sHdlSome\x20(1) eI +b11 fI +sHdlNone\x20(0) gI b0 hI -b0 iI -b0 jI -0kI -sFull64\x20(0) lI -0mI -0nI -0oI -0pI -s0 qI -b0 rI -b0 sI +sHdlSome\x20(1) iI +b10 jI +sHdlNone\x20(0) kI +b0 lI +sHdlSome\x20(1) mI +b0 nI +sHdlNone\x20(0) oI +b0 pI +sHdlSome\x20(1) qI +b100 rI +sHdlNone\x20(0) sI b0 tI -b0 uI -b0 vI -0wI -sFull64\x20(0) xI -0yI -0zI -0{I -0|I -s0 }I -b0 ~I -b0 !J +sHdlSome\x20(1) uI +b101 vI +sHdlNone\x20(0) wI +b0 xI +sHdlSome\x20(1) yI +b100 zI +sHdlNone\x20(0) {I +b0 |I +sHdlSome\x20(1) }I +b110 ~I +sHdlNone\x20(0) !J b0 "J -b0 #J -b0 $J -0%J -sFull64\x20(0) &J -b0 'J -b0 (J -0)J -0*J -0+J -0,J -0-J -0.J -0/J -00J -b0 1J -02J -03J -04J -05J -06J -07J -08J -09J +sHdlSome\x20(1) #J +b111 $J +sHdlNone\x20(0) %J +b0 &J +sHdlSome\x20(1) 'J +b110 (J +sHdlNone\x20(0) )J +b0 *J +sHdlSome\x20(1) +J +b100 ,J +sHdlNone\x20(0) -J +b0 .J +sHdlSome\x20(1) /J +b0 0J +sHdlNone\x20(0) 1J +b0 2J +sHdlSome\x20(1) 3J +b0 4J +sHdlNone\x20(0) 5J +b0 6J +17J +b0 8J +b0 9J b0 :J -0;J +b0 ;J 0J @@ -17114,125 +20003,125 @@ b0 :J 0@J 0AJ 0BJ -b0 CJ +0CJ b0 DJ -b0 EJ -b0 FJ -b0 GJ +0EJ +0FJ +0GJ 0HJ -sHdlNone\x20(0) IJ -sAddSub\x20(0) JJ -s0 KJ -b0 LJ +0IJ +0JJ +0KJ +0LJ b0 MJ -b0 NJ -b0 OJ -b0 PJ +0NJ +0OJ +0PJ 0QJ -sFull64\x20(0) RJ +0RJ 0SJ 0TJ 0UJ -0VJ -s0 WJ -b0 XJ -b0 YJ +sHdlSome\x20(1) VJ +sReady\x20(0) WJ +sLogical\x20(2) XJ +s0 YJ b0 ZJ b0 [J b0 \J -0]J -sFull64\x20(0) ^J +b0 ]J +b0 ^J 0_J -0`J +sFull64\x20(0) `J 0aJ -0bJ -s0 cJ -b0 dJ -b0 eJ +1bJ +1cJ +0dJ +s0 eJ b0 fJ b0 gJ b0 hJ -0iJ -sFull64\x20(0) jJ -b0 kJ -b0 lJ +b0 iJ +b0 jJ +0kJ +sFull64\x20(0) lJ 0mJ -0nJ -0oJ +1nJ +1oJ 0pJ -0qJ -0rJ -0sJ -0tJ +s0 qJ +b0 rJ +b0 sJ +b0 tJ b0 uJ -0vJ +b0 vJ 0wJ -0xJ -0yJ -0zJ -0{J -0|J -0}J -b0 ~J -0!K -0"K -0#K -0$K -0%K -0&K -0'K +sFull64\x20(0) xJ +b110 yJ +b1000000000100 zJ +1{J +1|J +1}J +sHdlSome\x20(1) ~J +sLogical\x20(2) !K +s0 "K +b0 #K +b0 $K +b0 %K +b0 &K +b0 'K 0(K -b0 )K -b0 *K -b0 +K -b0 ,K -b0 -K -0.K -sHdlNone\x20(0) /K -sAddSub\x20(0) 0K -s0 1K +sFull64\x20(0) )K +0*K +1+K +1,K +0-K +s0 .K +b0 /K +b0 0K +b0 1K b0 2K b0 3K -b0 4K -b0 5K -b0 6K -07K -sFull64\x20(0) 8K +04K +sFull64\x20(0) 5K +06K +17K +18K 09K -0:K -0;K -0K b0 ?K -b0 @K -b0 AK -b0 BK -0CK -sFull64\x20(0) DK -0EK -0FK -0GK -0HK -s0 IK +0@K +sFull64\x20(0) AK +b110 BK +b1000000000100 CK +b0 DK +b0 EK +b0 FK +1GK +1HK +1IK b0 JK -b0 KK -b0 LK -b0 MK -b0 NK -0OK -sFull64\x20(0) PK -b0 QK -b0 RK -0SK -0TK -0UK -0VK -0WK -0XK -0YK -0ZK -b0 [K +1KK +sHdlNone\x20(0) LK +sReady\x20(0) MK +sHdlNone\x20(0) NK +sReady\x20(0) OK +sHdlNone\x20(0) PK +sReady\x20(0) QK +sHdlNone\x20(0) RK +sReady\x20(0) SK +sHdlNone\x20(0) TK +sReady\x20(0) UK +sHdlNone\x20(0) VK +sReady\x20(0) WK +sHdlNone\x20(0) XK +sReady\x20(0) YK +sHdlNone\x20(0) ZK +sReady\x20(0) [K 0\K 0]K 0^K @@ -17241,7 +20130,7 @@ b0 [K 0aK 0bK 0cK -b0 dK +0dK 0eK 0fK 0gK @@ -17250,12 +20139,12 @@ b0 dK 0jK 0kK 0lK -b0 mK +0mK 0nK -1oK -sHdlNone\x20(0) pK -b0 qK -b0 rK +0oK +0pK +0qK +0rK 0sK 0tK 0uK @@ -17264,9 +20153,9 @@ b0 rK 0xK 0yK 0zK -sHdlNone\x20(0) {K -b0 |K -b0 }K +0{K +0|K +0}K 0~K 0!L 0"L @@ -17275,20 +20164,20 @@ b0 }K 0%L 0&L 0'L -sHdlSome\x20(1) (L -sLogical\x20(2) )L -s0 *L -b0 +L -b0 ,L -b0 -L +0(L +0)L +0*L +0+L +0,L +0-L b0 .L b0 /L -00L -sFull64\x20(0) 1L +b0 0L +b0 1L 02L -13L -14L -05L +03L +sHdlNone\x20(0) 4L +sAddSub\x20(0) 5L s0 6L b0 7L b0 8L @@ -17298,8 +20187,8 @@ b0 ;L 0L -1?L -1@L +0?L +0@L 0AL s0 BL b0 CL @@ -17309,91 +20198,91 @@ b0 FL b0 GL 0HL sFull64\x20(0) IL -b110 JL -1KL -sHdlNone\x20(0) LL -b0 ML -sHdlNone\x20(0) NL +0JL +0KL +0LL +0ML +s0 NL b0 OL -sCompleted\x20(0) PL +b0 PL b0 QL -0RL -0SL +b0 RL +b0 SL 0TL -0UL -0VL -0WL -0XL +sFull64\x20(0) UL +b0 VL +b0 WL +b0 XL 0YL -sHdlNone\x20(0) ZL -sAddSub\x20(0) [L -s0 \L -b0 ]L -b0 ^L -b0 _L -b0 `L +0ZL +0[L +0\L +0]L +0^L +0_L +0`L b0 aL 0bL -sFull64\x20(0) cL +0cL 0dL 0eL 0fL 0gL -s0 hL -b0 iL +0hL +0iL b0 jL -b0 kL -b0 lL -b0 mL +0kL +0lL +0mL 0nL -sFull64\x20(0) oL +0oL 0pL 0qL 0rL -0sL -s0 tL +b0 sL +b0 tL b0 uL b0 vL b0 wL -b0 xL -b0 yL -0zL -sFull64\x20(0) {L -b0 |L +0xL +0yL +sHdlNone\x20(0) zL +sAddSub\x20(0) {L +s0 |L b0 }L -0~L -0!M -0"M -0#M +b0 ~L +b0 !M +b0 "M +b0 #M 0$M -0%M +sFull64\x20(0) %M 0&M 0'M -b0 (M +0(M 0)M -0*M -0+M -0,M -0-M -0.M -0/M +s0 *M +b0 +M +b0 ,M +b0 -M +b0 .M +b0 /M 00M -b0 1M +sFull64\x20(0) 1M 02M 03M 04M 05M -06M -07M -08M -09M -1:M -sHdlNone\x20(0) ;M -b0 M -0?M -0@M +b0 ?M +b0 @M 0AM 0BM 0CM @@ -17401,87 +20290,87 @@ b0 >M 0EM 0FM 0GM -1HM -sHdlNone\x20(0) IM -b0 JM -b0 KM +0HM +b0 IM +0JM +0KM 0LM 0MM 0NM 0OM 0PM 0QM -0RM +b0 RM 0SM -sHdlNone\x20(0) TM -b0 UM -b0 VM +0TM +0UM +0VM 0WM 0XM 0YM 0ZM -0[M -0\M -0]M -0^M -sHdlSome\x20(1) _M -sLogical\x20(2) `M -s0 aM -b0 bM -b0 cM -b0 dM +b0 [M +b0 \M +b0 ]M +b0 ^M +b0 _M +0`M +0aM +sHdlNone\x20(0) bM +sAddSub\x20(0) cM +s0 dM b0 eM b0 fM -0gM -sFull64\x20(0) hM -0iM -1jM -1kM +b0 gM +b0 hM +b0 iM +0jM +sFull64\x20(0) kM 0lM -s0 mM -b0 nM -b0 oM -b0 pM +0mM +0nM +0oM +s0 pM b0 qM b0 rM -0sM -sFull64\x20(0) tM -0uM -1vM -1wM +b0 sM +b0 tM +b0 uM +0vM +sFull64\x20(0) wM 0xM -s0 yM -b0 zM -b0 {M -b0 |M +0yM +0zM +0{M +s0 |M b0 }M b0 ~M -0!N -sFull64\x20(0) "N -b110 #N -1$N -sHdlNone\x20(0) %N +b0 !N +b0 "N +b0 #N +0$N +sFull64\x20(0) %N b0 &N -sHdlNone\x20(0) 'N +b0 'N b0 (N -sCompleted\x20(0) )N -b0 *N +0)N +0*N 0+N 0,N 0-N 0.N 0/N 00N -01N +b0 1N 02N 03N -14N -sHdlNone\x20(0) 5N -b0 6N -17N -sHdlSome\x20(1) 8N -b0 9N -1:N +04N +05N +06N +07N +08N +09N +b0 :N 0;N 0O -1?O +0O +0?O s0 @O b0 AO b0 BO b0 CO b0 DO -b1001000110100 EO +b0 EO 0FO sFull64\x20(0) GO -b1111 HO -sHdlSome\x20(1) IO -sAddSub\x20(0) JO -s0 KO -b0 LO +0HO +0IO +0JO +0KO +s0 LO b0 MO b0 NO b0 OO -b1001000110100 PO -0QO -sFull64\x20(0) RO -1SO -1TO -1UO -1VO -s0 WO -b0 XO -b0 YO -b0 ZO -b0 [O -b1001000110100 \O +b0 PO +b0 QO +0RO +sFull64\x20(0) SO +b0 TO +b0 UO +b0 VO +0WO +0XO +0YO +0ZO +0[O +0\O 0]O -sFull64\x20(0) ^O -1_O -1`O -1aO -1bO -s0 cO -b0 dO -b0 eO -b0 fO -b0 gO -b1001000110100 hO +0^O +b0 _O +0`O +0aO +0bO +0cO +0dO +0eO +0fO +0gO +b0 hO 0iO -sFull64\x20(0) jO -b1111 kO -sHdlSome\x20(1) lO -sLogical\x20(2) mO -s0 nO -b0 oO -b0 pO +0jO +0kO +0lO +0mO +0nO +0oO +0pO b0 qO b0 rO b0 sO -0tO -sFull64\x20(0) uO +b0 tO +b0 uO 0vO -1wO -1xO -0yO +0wO +sHdlNone\x20(0) xO +sAddSub\x20(0) yO s0 zO b0 {O b0 |O @@ -17648,8 +20537,8 @@ b0 !P 0"P sFull64\x20(0) #P 0$P -1%P -1&P +0%P +0&P 0'P s0 (P b0 )P @@ -17659,4364 +20548,7846 @@ b0 ,P b0 -P 0.P sFull64\x20(0) /P -b110 0P -sHdlSome\x20(1) 1P -sLogical\x20(2) 2P -s0 3P -b0 4P +00P +01P +02P +03P +s0 4P b0 5P b0 6P b0 7P b0 8P -09P -sFull64\x20(0) :P -0;P -1