diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index 90b88e4..28368e9 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -2,17 +2,36 @@ // See Notices.txt for copyright information use crate::{ instruction::{PRegNum, UnitNum, UnitOutRegNum, CONST_ZERO_UNIT_NUM}, - unit::{UnitKind, UnitMOp}, + unit::{unit_base::UnitForwardingInfo, UnitCancelInput, UnitKind, UnitMOp, UnitOutputWrite}, }; use fayalite::prelude::*; use std::num::NonZeroUsize; +#[derive(Clone, Eq, PartialEq, Hash, Debug)] +#[non_exhaustive] +pub struct UnitConfig { + pub kind: UnitKind, + /// max number of instructions that can be in-flight through this unit at any point in time. + pub max_in_flight: Option, +} + +impl UnitConfig { + pub fn new(kind: UnitKind) -> Self { + Self { + kind, + max_in_flight: None, + } + } +} + #[derive(Clone, Eq, PartialEq, Hash, Debug)] #[non_exhaustive] pub struct CpuConfig { - pub unit_kinds: Vec, + pub units: Vec, pub out_reg_num_width: usize, pub fetch_width: NonZeroUsize, + /// default value for [`UnitConfig::max_in_flight`] + pub default_unit_max_in_flight: NonZeroUsize, } impl CpuConfig { @@ -23,15 +42,22 @@ impl CpuConfig { }; v }; - pub fn new(unit_kinds: Vec) -> Self { + pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = { + let Some(v) = NonZeroUsize::new(8) else { + unreachable!(); + }; + v + }; + pub fn new(units: Vec) -> Self { Self { - unit_kinds, + units, out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH, fetch_width: Self::DEFAULT_FETCH_WIDTH, + default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT, } } pub fn non_const_unit_nums(&self) -> std::ops::Range { - (CONST_ZERO_UNIT_NUM + 1)..(self.unit_kinds.len() + 1) + (CONST_ZERO_UNIT_NUM + 1)..(self.units.len() + 1) } pub fn unit_num_width(&self) -> usize { UInt::range(CONST_ZERO_UNIT_NUM..self.non_const_unit_nums().end).width() @@ -51,4 +77,22 @@ impl CpuConfig { pub fn unit_mop_in_unit(&self) -> UnitMOp, DynSize> { UnitMOp[self.unit_out_reg_num()][self.p_reg_num_width()] } + pub fn unit_output_write(&self) -> UnitOutputWrite { + UnitOutputWrite[self.out_reg_num_width] + } + pub fn unit_output_writes(&self) -> Array>> { + Array[HdlOption[self.unit_output_write()]][self.non_const_unit_nums().len()] + } + pub fn unit_cancel_input(&self) -> UnitCancelInput { + UnitCancelInput[self.out_reg_num_width] + } + pub fn unit_forwarding_info(&self) -> UnitForwardingInfo { + UnitForwardingInfo[self.unit_num_width()][self.out_reg_num_width] + [self.non_const_unit_nums().len()] + } + pub fn unit_max_in_flight(&self, unit_index: usize) -> NonZeroUsize { + self.units[unit_index] + .max_in_flight + .unwrap_or(self.default_unit_max_in_flight) + } } diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index 46c778c..befab9a 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -12,6 +12,10 @@ pub trait MOpTrait: Type { type SrcRegWidth: Size; fn dest_reg_ty(self) -> Self::DestReg; fn dest_reg(input: impl ToExpr) -> Expr; + fn for_each_src_reg( + input: impl ToExpr, + f: &mut impl FnMut(Expr>, usize), + ); fn mapped_ty( self, new_dest_reg: NewDestReg, @@ -63,6 +67,16 @@ impl MOpTrait for T { fn dest_reg(input: impl ToExpr) -> Expr { T::common_mop(input).dest } + fn for_each_src_reg( + input: impl ToExpr, + f: &mut impl FnMut(Expr>, usize), + ) { + let input = input.to_expr(); + let common = T::common_mop(input); + for index in 0..T::SrcCount::VALUE { + f(common.src[index], index); + } + } fn mapped_ty( self, new_dest_reg: NewDestReg, @@ -396,6 +410,17 @@ macro_rules! mop_enum { } dest_reg } + #[hdl] + fn for_each_src_reg( + input: impl ToExpr, + f: &mut impl FnMut(Expr>, usize), + ) { + #[hdl] + match input { + $MOp::<_, _>::$FirstVariant(v) => MOpTrait::for_each_src_reg(v, f), + $($MOp::<_, _>::$Variant(v) => MOpTrait::for_each_src_reg(v, f),)* + } + } fn mapped_ty( self, new_dest_reg: NewDestReg, diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs index d064bab..529d9a5 100644 --- a/crates/cpu/src/reg_alloc.rs +++ b/crates/cpu/src/reg_alloc.rs @@ -6,7 +6,7 @@ use crate::{ MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, RenameTableName, UnitOutRegNum, COMMON_MOP_SRC_LEN, }, - unit::{TrapData, UnitTrait}, + unit::{unit_base::UnitForwardingInfo, TrapData, UnitTrait}, util::tree_reduce::tree_reduce_with_state, }; use fayalite::{ @@ -17,6 +17,7 @@ use fayalite::{ }; use std::{ collections::{BTreeMap, VecDeque}, + marker::PhantomData, num::NonZeroUsize, }; @@ -79,8 +80,7 @@ pub fn reg_alloc(config: &CpuConfig) { } #[hdl] - let available_units = - wire(Array[Array[Bool][config.unit_kinds.len()]][config.fetch_width.get()]); + let available_units = wire(Array[Array[Bool][config.units.len()]][config.fetch_width.get()]); #[hdl] let selected_unit_indexes = wire(Array[HdlOption[UInt[config.unit_num_width()]]][config.fetch_width.get()]); @@ -95,7 +95,7 @@ pub fn reg_alloc(config: &CpuConfig) { ); connect( available_units[fetch_index], - repeat(false, config.unit_kinds.len()), + repeat(false, config.units.len()), ); connect( renamed_mops[fetch_index], @@ -116,7 +116,6 @@ pub fn reg_alloc(config: &CpuConfig) { connect(wire.addr, MOpRegNum::const_zero()); connect(wire.data, config.p_reg_num().const_zero()); for (&rename_table_name, mem) in &mut rename_table_mems { - let table_name = rename_table_name.as_str(); let read_port = mem.new_read_port(); connect(read_port.clk, cd.clk); connect_any(read_port.addr, 0u8); @@ -242,7 +241,7 @@ pub fn reg_alloc(config: &CpuConfig) { connect( selected_unit_indexes[fetch_index], tree_reduce_with_state( - 0..config.unit_kinds.len(), + 0..config.units.len(), &mut 0usize, |_state, unit_index| { let selected_unit_index_leaf = wire_with_loc( @@ -304,15 +303,15 @@ pub fn reg_alloc(config: &CpuConfig) { config.fetch_width.get(), ), ); - for (unit_index, &unit_kind) in config.unit_kinds.iter().enumerate() { - let dyn_unit = unit_kind.unit(config); + for (unit_index, unit_config) in config.units.iter().enumerate() { + let dyn_unit = unit_config.kind.unit(config, unit_index); let unit = instance_with_loc( &format!("unit_{unit_index}"), - dyn_unit.make_module(), + dyn_unit.module(), SourceLocation::caller(), ); connect(dyn_unit.cd(unit), cd); - let unit_input = dyn_unit.input(unit); + let unit_input_insn = dyn_unit.input_insn(unit); // TODO: handle assigning multiple instructions to a unit at a time let assign_to_unit_at_once = NonZeroUsize::new(1).unwrap(); // TODO: handle retiring multiple instructions from a unit at a time @@ -333,7 +332,10 @@ pub fn reg_alloc(config: &CpuConfig) { HdlOption[UInt[config.out_reg_num_width]].uninit(), // FIXME: just for debugging ); connect(unit_free_regs_tracker.alloc_out[0].ready, false); - connect(unit_input.data, Expr::ty(unit_input).data.HdlNone()); + connect( + unit_input_insn.data, + Expr::ty(unit_input_insn).data.HdlNone(), + ); for fetch_index in 0..config.fetch_width.get() { #[hdl] if let HdlNone = unit_free_regs_tracker.alloc_out[0].data { @@ -341,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) { connect(available_units[fetch_index][unit_index], false); } #[hdl] - if !unit_input.ready { + if !unit_input_insn.ready { // must come after to override connects in loops above connect(available_units[fetch_index][unit_index], false); } @@ -354,11 +356,11 @@ pub fn reg_alloc(config: &CpuConfig) { if let HdlSome(renamed_mop) = HdlOption::and_then(renamed_mops[fetch_index], |v| dyn_unit.extract_mop(v)) { - connect(unit_input.data, HdlSome(renamed_mop)); + connect(unit_input_insn.data, HdlSome(renamed_mop)); } else { connect( - unit_input.data, - HdlSome(Expr::ty(unit_input).data.HdlSome.uninit()), + unit_input_insn.data, + HdlSome(Expr::ty(unit_input_insn).data.HdlSome.uninit()), ); // FIXME: add hdl_assert(cd.clk, false.to_expr(), ""); } @@ -383,5 +385,23 @@ pub fn reg_alloc(config: &CpuConfig) { } } } + // TODO: connect outputs to other units + connect( + dyn_unit.unit_forwarding_info(unit), + #[hdl] + UnitForwardingInfo::<_, _, _> { + unit_output_writes: repeat( + HdlOption[config.unit_output_write()].HdlNone(), + config.units.len(), + ), + _phantom: PhantomData, + }, + ); + connect(dyn_unit.output(unit).ready, false); + // TODO: handle cancellation + connect( + dyn_unit.cancel_input(unit).data, + HdlOption[config.unit_cancel_input()].HdlNone(), + ); } } diff --git a/crates/cpu/src/register.rs b/crates/cpu/src/register.rs index 1594d64..33b7e5c 100644 --- a/crates/cpu/src/register.rs +++ b/crates/cpu/src/register.rs @@ -148,3 +148,14 @@ pub struct PRegValue { pub int_fp: UInt<64>, pub flags: PRegFlags, } + +impl PRegValue { + #[hdl] + pub fn zeroed() -> Expr { + #[hdl] + PRegValue { + int_fp: 0u64, + flags: PRegFlags::zeroed(), + } + } +} diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index eeee98f..e76342b 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -4,9 +4,10 @@ use crate::{ config::CpuConfig, instruction::{ - mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, PRegNum, UnitOutRegNum, + mop_enum, AluBranchMOp, L2RegisterFileMOp, LoadStoreMOp, MOpTrait, UnitOutRegNum, }, register::PRegValue, + unit::unit_base::UnitForwardingInfo, }; use fayalite::{ bundle::{Bundle, BundleType}, @@ -16,6 +17,7 @@ use fayalite::{ }; pub mod alu_branch; +pub mod unit_base; macro_rules! all_units { ( @@ -42,9 +44,9 @@ macro_rules! all_units { } impl $UnitKind { - pub fn unit(self, config: &CpuConfig) -> DynUnit { + pub fn unit(self, config: &CpuConfig, unit_index: usize) -> DynUnit { match self { - $($UnitKind::$Unit => $create_dyn_unit_fn(config),)* + $($UnitKind::$Unit => $create_dyn_unit_fn(config, unit_index),)* } } } @@ -111,11 +113,11 @@ macro_rules! all_units { #[hdl] pub fn available_units_for_kind(&self, unit_kind: impl ToExpr) -> Expr> { #[hdl] - let available_units_for_kind = wire(Array[Bool][self.unit_kinds.len()]); + let available_units_for_kind = wire(Array[Bool][self.units.len()]); #[hdl] match unit_kind { - $($HdlUnitKind::$Unit => for (index, &unit_kind) in self.unit_kinds.iter().enumerate() { - connect(available_units_for_kind[index], unit_kind == $UnitKind::$Unit); + $($HdlUnitKind::$Unit => for (index, unit) in self.units.iter().enumerate() { + connect(available_units_for_kind[index], unit.kind == $UnitKind::$Unit); })* } available_units_for_kind @@ -129,13 +131,13 @@ all_units! { #[unit_kind = UnitKind] #[hdl] pub enum UnitMOp { - #[create_dyn_unit_fn = |config| alu_branch::AluBranch::new(config).to_dyn()] + #[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()] #[extract = alu_branch_mop] AluBranch(AluBranchMOp), - #[create_dyn_unit_fn = |config| todo!()] + #[create_dyn_unit_fn = |config, unit_index| todo!()] #[extract = l2_register_file_mop] L2RegisterFile(L2RegisterFileMOp), - #[create_dyn_unit_fn = |config| todo!()] + #[create_dyn_unit_fn = |config, unit_index| todo!()] #[extract = load_store_mop] LoadStore(LoadStoreMOp), } @@ -147,6 +149,12 @@ pub struct UnitResultCompleted { pub extra_out: ExtraOut, } +#[hdl] +pub struct UnitOutputWrite { + pub which: UnitOutRegNum, + pub value: PRegValue, +} + #[hdl] pub struct TrapData { // TODO @@ -159,14 +167,14 @@ pub enum UnitResult { } #[hdl] -pub struct UnitOutput { - pub which: PRegNum, +pub struct UnitOutput { + pub which: UnitOutRegNum, pub result: UnitResult, } #[hdl] -pub struct UnitCancelInput { - pub which: PRegNum, +pub struct UnitCancelInput { + pub which: UnitOutRegNum, } pub trait UnitTrait: @@ -187,18 +195,22 @@ pub trait UnitTrait: mop: Expr, DynSize>>, ) -> Expr>; - fn make_module(&self) -> Interned>; + fn module(&self) -> Interned>; - fn input(&self, this: Expr) -> Expr>; + fn input_insn(&self, this: Expr) -> Expr>; - fn cancel_input( + fn cancel_input(&self, this: Expr) -> Expr>>; + + fn unit_forwarding_info( &self, this: Expr, - ) -> Expr>>; + ) -> Expr>; + fn output( &self, this: Expr, - ) -> Expr>>; + ) -> Expr>>; + fn cd(&self, this: Expr) -> Expr; fn to_dyn(&self) -> DynUnit; @@ -250,25 +262,29 @@ impl UnitTrait for DynUnit { self.unit.extract_mop(mop) } - fn make_module(&self) -> Interned> { - self.unit.make_module() + fn module(&self) -> Interned> { + self.unit.module() } - fn input(&self, this: Expr) -> Expr> { - self.unit.input(this) + fn input_insn(&self, this: Expr) -> Expr> { + self.unit.input_insn(this) } - fn cancel_input( + fn cancel_input(&self, this: Expr) -> Expr>> { + self.unit.cancel_input(this) + } + + fn unit_forwarding_info( &self, this: Expr, - ) -> Expr>> { - self.unit.cancel_input(this) + ) -> Expr> { + self.unit.unit_forwarding_info(this) } fn output( &self, this: Expr, - ) -> Expr>> { + ) -> Expr>> { self.unit.output(this) } @@ -312,25 +328,29 @@ impl UnitTrait for DynUnitWrapper Interned> { - self.0.make_module().canonical().intern_sized() + fn module(&self) -> Interned> { + self.0.module().canonical().intern_sized() } - fn input(&self, this: Expr) -> Expr> { - Expr::from_bundle(Expr::as_bundle(self.0.input(Expr::from_bundle(this)))) + fn input_insn(&self, this: Expr) -> Expr> { + Expr::from_bundle(Expr::as_bundle(self.0.input_insn(Expr::from_bundle(this)))) } - fn cancel_input( + fn cancel_input(&self, this: Expr) -> Expr>> { + self.0.cancel_input(Expr::from_bundle(this)) + } + + fn unit_forwarding_info( &self, this: Expr, - ) -> Expr>> { - self.0.cancel_input(Expr::from_bundle(this)) + ) -> Expr> { + self.0.unit_forwarding_info(Expr::from_bundle(this)) } fn output( &self, this: Expr, - ) -> Expr>> { + ) -> Expr>> { Expr::from_bundle(Expr::as_bundle(self.0.output(Expr::from_bundle(this)))) } diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index 2a09588..1a553d4 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -4,7 +4,10 @@ use crate::{ config::CpuConfig, instruction::{AluBranchMOp, UnitOutRegNum}, - unit::{DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitMOp, UnitOutput, UnitTrait}, + unit::{ + unit_base::{unit_base, UnitForwardingInfo}, + DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitMOp, UnitOutput, UnitTrait, + }, }; use fayalite::{ intern::{Intern, Interned}, @@ -13,14 +16,34 @@ use fayalite::{ }; #[hdl_module] -pub fn alu_branch(config: &CpuConfig) { +pub fn alu_branch(config: &CpuConfig, unit_index: usize) { #[hdl] let cd: ClockDomain = m.input(); #[hdl] - let input: ReadyValid, DynSize>> = + let input_insn: ReadyValid, DynSize>> = m.input(ReadyValid[AluBranchMOp[config.unit_out_reg_num()][config.p_reg_num_width()]]); + #[hdl] + let unit_forwarding_info: UnitForwardingInfo = + m.input(config.unit_forwarding_info()); + #[hdl] + let cancel_input: ReadyValid> = + m.input(ReadyValid[config.unit_cancel_input()]); + #[hdl] + let output: ReadyValid> = + m.output(ReadyValid[UnitOutput[config.out_reg_num_width][()]]); + #[hdl] + let unit_base = instance(unit_base( + config, + unit_index, + Expr::ty(input_insn).data.HdlSome, + )); + connect(unit_base.input_insn, input_insn); + connect(unit_base.cd, cd); + connect(unit_base.unit_forwarding_info, unit_forwarding_info); + connect(unit_base.cancel_input, cancel_input); // TODO: finish - connect(input.ready, true); + connect(unit_base.ready_mop.ready, true); + connect(output.data, Expr::ty(output.data).HdlNone()); } #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] @@ -30,10 +53,10 @@ pub struct AluBranch { } impl AluBranch { - pub fn new(config: &CpuConfig) -> Self { + pub fn new(config: &CpuConfig, unit_index: usize) -> Self { Self { config: config.intern(), - module: alu_branch(config), + module: alu_branch(config, unit_index), } } } @@ -52,7 +75,7 @@ impl UnitTrait for AluBranch { } fn mop_ty(&self) -> Self::MOp { - self.module.io_ty().input.data.HdlSome + self.module.io_ty().input_insn.data.HdlSome } fn unit_kind(&self) -> UnitKind { @@ -66,26 +89,30 @@ impl UnitTrait for AluBranch { UnitMOp::alu_branch_mop(mop) } - fn make_module(&self) -> Interned> { + fn module(&self) -> Interned> { self.module } - fn input(&self, this: Expr) -> Expr> { - this.input + fn input_insn(&self, this: Expr) -> Expr> { + this.input_insn } - fn cancel_input( + fn cancel_input(&self, this: Expr) -> Expr>> { + this.cancel_input + } + + fn unit_forwarding_info( &self, this: Expr, - ) -> Expr>> { - todo!() + ) -> Expr> { + this.unit_forwarding_info } fn output( &self, this: Expr, - ) -> Expr>> { - todo!() + ) -> Expr>> { + this.output } fn cd(&self, this: Expr) -> Expr { diff --git a/crates/cpu/src/unit/unit_base.rs b/crates/cpu/src/unit/unit_base.rs new file mode 100644 index 0000000..f6a1627 --- /dev/null +++ b/crates/cpu/src/unit/unit_base.rs @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::CpuConfig, + instruction::{MOpTrait, UnitOutRegNum, COMMON_MOP_SRC_LEN}, + register::PRegValue, + unit::{UnitCancelInput, UnitOutputWrite}, + util::tree_reduce::tree_reduce, +}; +use fayalite::{module::wire_with_loc, prelude::*, ty::StaticType, util::ready_valid::ReadyValid}; +use std::marker::PhantomData; + +#[hdl] +pub struct UnitForwardingInfo { + pub unit_output_writes: ArrayType>, UnitCount>, + pub _phantom: PhantomData, +} + +#[hdl] +pub struct ReadyMOp>> { + pub mop: MOp, + pub src_values: Array, +} + +#[hdl] +struct InFlightOp>> { + pub mop: MOp, + pub src_values: Array, { COMMON_MOP_SRC_LEN }>, +} + +#[hdl_module] +pub fn unit_base>>( + config: &CpuConfig, + unit_index: usize, + mop_ty: MOp, +) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let unit_forwarding_info: UnitForwardingInfo = + m.input(config.unit_forwarding_info()); + #[hdl] + let input_insn: ReadyValid = m.input(ReadyValid[mop_ty]); + connect(input_insn.ready, false); + #[hdl] + let cancel_input: ReadyValid> = + m.input(ReadyValid[config.unit_cancel_input()]); + connect(cancel_input.ready, true); + #[hdl] + let ready_mop: ReadyValid> = m.output(ReadyValid[ReadyMOp[mop_ty]]); + connect(ready_mop.data, Expr::ty(ready_mop.data).HdlNone()); + let max_in_flight = config.unit_max_in_flight(unit_index).get(); + #[hdl] + let in_flight_ops = reg_builder().clock_domain(cd).reset(repeat( + HdlOption[InFlightOp[mop_ty]].HdlNone(), + max_in_flight, + )); + let in_flight_op_index_ty = UInt::range(0..max_in_flight); + #[hdl] + let input_index = wire(HdlOption[in_flight_op_index_ty]); + connect( + input_index, + tree_reduce( + (0..max_in_flight).map(|i| -> Expr> { + HdlOption::map(in_flight_ops[i], |_| i.cast_to(in_flight_op_index_ty)) + }), + HdlOption::or, + ) + .expect("max_in_flight is known to be non-zero"), + ); + #[hdl] + let input_in_flight_op = wire(HdlOption[InFlightOp[mop_ty]]); + connect(input_in_flight_op, Expr::ty(input_in_flight_op).HdlNone()); + #[hdl] + if let HdlSome(mop) = ReadyValid::firing_data(input_insn) { + let src_values = wire_with_loc( + "input_in_flight_op_src_values", + SourceLocation::caller(), + StaticType::TYPE, + ); + connect( + src_values, + [HdlSome(PRegValue::zeroed()); COMMON_MOP_SRC_LEN], + ); + MOp::for_each_src_reg(mop, &mut |src_reg, src_index| { + #[hdl] + if config + .p_reg_num() + .const_zero() + .cast_to_bits() + .cmp_ne(src_reg) + { + connect(src_values[src_index], HdlNone()); + } + }); + connect( + input_in_flight_op, + HdlSome( + #[hdl] + InFlightOp::<_> { mop, src_values }, + ), + ); + } + for in_flight_op_index in 0..max_in_flight { + #[hdl] + if let HdlSome(in_flight_op) = in_flight_ops[in_flight_op_index] { + #[hdl] + if let HdlSome(cancel_input) = ReadyValid::firing_data(cancel_input) { + #[hdl] + let UnitCancelInput::<_> { which } = cancel_input; + #[hdl] + if which.value.cmp_eq(MOp::dest_reg(in_flight_op.mop).value) { + // TODO: if it needs extra time to cancel (e.g. still in pipeline), handle that here + connect( + in_flight_ops[in_flight_op_index], + HdlOption[InFlightOp[mop_ty]].HdlNone(), + ); + } + } + // TODO: finish + } else if let HdlSome(input_index) = input_index { + connect(input_insn.ready, true); + #[hdl] + if input_index.cmp_eq(in_flight_op_index) { + connect(in_flight_ops[in_flight_op_index], input_in_flight_op); + } + } + } +} diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd index 54c1f5f..3f2407e 100644 --- a/crates/cpu/tests/expected/reg_alloc.vcd +++ b/crates/cpu/tests/expected/reg_alloc.vcd @@ -600,2530 +600,2530 @@ $scope struct contents $end $scope struct \[0] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |1 adj_value $end +$var reg 2 |G adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _4 value $end +$var reg 4 _J value $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }1 adj_value $end +$var reg 2 }G adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `4 value $end +$var reg 4 `J value $end $upscope $end $upscope $end $upscope $end $scope struct \[2] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~1 adj_value $end +$var reg 2 ~G adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 a4 value $end +$var reg 4 aJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[3] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !2 adj_value $end +$var reg 2 !H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 b4 value $end +$var reg 4 bJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[4] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "2 adj_value $end +$var reg 2 "H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 c4 value $end +$var reg 4 cJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[5] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #2 adj_value $end +$var reg 2 #H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 d4 value $end +$var reg 4 dJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[6] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $2 adj_value $end +$var reg 2 $H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 e4 value $end +$var reg 4 eJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[7] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %2 adj_value $end +$var reg 2 %H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 f4 value $end +$var reg 4 fJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[8] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &2 adj_value $end +$var reg 2 &H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 g4 value $end +$var reg 4 gJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[9] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 '2 adj_value $end +$var reg 2 'H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 h4 value $end +$var reg 4 hJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[10] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (2 adj_value $end +$var reg 2 (H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 i4 value $end +$var reg 4 iJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[11] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )2 adj_value $end +$var reg 2 )H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 j4 value $end +$var reg 4 jJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[12] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *2 adj_value $end +$var reg 2 *H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 k4 value $end +$var reg 4 kJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[13] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +2 adj_value $end +$var reg 2 +H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 l4 value $end +$var reg 4 lJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[14] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,2 adj_value $end +$var reg 2 ,H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 m4 value $end +$var reg 4 mJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[15] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -2 adj_value $end +$var reg 2 -H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 n4 value $end +$var reg 4 nJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[16] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .2 adj_value $end +$var reg 2 .H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 o4 value $end +$var reg 4 oJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[17] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /2 adj_value $end +$var reg 2 /H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 p4 value $end +$var reg 4 pJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[18] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 02 adj_value $end +$var reg 2 0H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 q4 value $end +$var reg 4 qJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[19] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 12 adj_value $end +$var reg 2 1H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 r4 value $end +$var reg 4 rJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[20] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 22 adj_value $end +$var reg 2 2H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 s4 value $end +$var reg 4 sJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[21] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 32 adj_value $end +$var reg 2 3H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 t4 value $end +$var reg 4 tJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[22] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 42 adj_value $end +$var reg 2 4H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 u4 value $end +$var reg 4 uJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[23] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 52 adj_value $end +$var reg 2 5H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 v4 value $end +$var reg 4 vJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[24] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 62 adj_value $end +$var reg 2 6H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 w4 value $end +$var reg 4 wJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[25] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 72 adj_value $end +$var reg 2 7H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 x4 value $end +$var reg 4 xJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[26] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 82 adj_value $end +$var reg 2 8H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 y4 value $end +$var reg 4 yJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[27] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 92 adj_value $end +$var reg 2 9H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 z4 value $end +$var reg 4 zJ value $end $upscope $end $upscope $end $upscope $end $scope struct \[28] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 :2 adj_value $end +$var reg 2 :H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {4 value $end +$var reg 4 {J value $end $upscope $end $upscope $end $upscope $end $scope struct \[29] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ;2 adj_value $end +$var reg 2 ;H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 |4 value $end +$var reg 4 |J value $end $upscope $end $upscope $end $upscope $end $scope struct \[30] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 <2 adj_value $end +$var reg 2 2 adj_value $end +$var reg 2 >H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 !5 value $end +$var reg 4 !K value $end $upscope $end $upscope $end $upscope $end $scope struct \[33] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ?2 adj_value $end +$var reg 2 ?H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 "5 value $end +$var reg 4 "K value $end $upscope $end $upscope $end $upscope $end $scope struct \[34] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 @2 adj_value $end +$var reg 2 @H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 #5 value $end +$var reg 4 #K value $end $upscope $end $upscope $end $upscope $end $scope struct \[35] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 A2 adj_value $end +$var reg 2 AH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 $5 value $end +$var reg 4 $K value $end $upscope $end $upscope $end $upscope $end $scope struct \[36] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 B2 adj_value $end +$var reg 2 BH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 %5 value $end +$var reg 4 %K value $end $upscope $end $upscope $end $upscope $end $scope struct \[37] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 C2 adj_value $end +$var reg 2 CH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 &5 value $end +$var reg 4 &K value $end $upscope $end $upscope $end $upscope $end $scope struct \[38] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 D2 adj_value $end +$var reg 2 DH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 '5 value $end +$var reg 4 'K value $end $upscope $end $upscope $end $upscope $end $scope struct \[39] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 E2 adj_value $end +$var reg 2 EH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 (5 value $end +$var reg 4 (K value $end $upscope $end $upscope $end $upscope $end $scope struct \[40] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 F2 adj_value $end +$var reg 2 FH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 )5 value $end +$var reg 4 )K value $end $upscope $end $upscope $end $upscope $end $scope struct \[41] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 G2 adj_value $end +$var reg 2 GH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 *5 value $end +$var reg 4 *K value $end $upscope $end $upscope $end $upscope $end $scope struct \[42] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 H2 adj_value $end +$var reg 2 HH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 +5 value $end +$var reg 4 +K value $end $upscope $end $upscope $end $upscope $end $scope struct \[43] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 I2 adj_value $end +$var reg 2 IH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ,5 value $end +$var reg 4 ,K value $end $upscope $end $upscope $end $upscope $end $scope struct \[44] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 J2 adj_value $end +$var reg 2 JH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 -5 value $end +$var reg 4 -K value $end $upscope $end $upscope $end $upscope $end $scope struct \[45] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 K2 adj_value $end +$var reg 2 KH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 .5 value $end +$var reg 4 .K value $end $upscope $end $upscope $end $upscope $end $scope struct \[46] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 L2 adj_value $end +$var reg 2 LH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 /5 value $end +$var reg 4 /K value $end $upscope $end $upscope $end $upscope $end $scope struct \[47] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 M2 adj_value $end +$var reg 2 MH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 05 value $end +$var reg 4 0K value $end $upscope $end $upscope $end $upscope $end $scope struct \[48] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 N2 adj_value $end +$var reg 2 NH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 15 value $end +$var reg 4 1K value $end $upscope $end $upscope $end $upscope $end $scope struct \[49] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 O2 adj_value $end +$var reg 2 OH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 25 value $end +$var reg 4 2K value $end $upscope $end $upscope $end $upscope $end $scope struct \[50] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 P2 adj_value $end +$var reg 2 PH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 35 value $end +$var reg 4 3K value $end $upscope $end $upscope $end $upscope $end $scope struct \[51] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Q2 adj_value $end +$var reg 2 QH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 45 value $end +$var reg 4 4K value $end $upscope $end $upscope $end $upscope $end $scope struct \[52] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 R2 adj_value $end +$var reg 2 RH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 55 value $end +$var reg 4 5K value $end $upscope $end $upscope $end $upscope $end $scope struct \[53] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 S2 adj_value $end +$var reg 2 SH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 65 value $end +$var reg 4 6K value $end $upscope $end $upscope $end $upscope $end $scope struct \[54] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 T2 adj_value $end +$var reg 2 TH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 75 value $end +$var reg 4 7K value $end $upscope $end $upscope $end $upscope $end $scope struct \[55] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 U2 adj_value $end +$var reg 2 UH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 85 value $end +$var reg 4 8K value $end $upscope $end $upscope $end $upscope $end $scope struct \[56] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 V2 adj_value $end +$var reg 2 VH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 95 value $end +$var reg 4 9K value $end $upscope $end $upscope $end $upscope $end $scope struct \[57] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 W2 adj_value $end +$var reg 2 WH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :5 value $end +$var reg 4 :K value $end $upscope $end $upscope $end $upscope $end $scope struct \[58] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 X2 adj_value $end +$var reg 2 XH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;5 value $end +$var reg 4 ;K value $end $upscope $end $upscope $end $upscope $end $scope struct \[59] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Y2 adj_value $end +$var reg 2 YH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 <5 value $end +$var reg 4 5 value $end +$var reg 4 >K value $end $upscope $end $upscope $end $upscope $end $scope struct \[62] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \2 adj_value $end +$var reg 2 \H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?5 value $end +$var reg 4 ?K value $end $upscope $end $upscope $end $upscope $end $scope struct \[63] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]2 adj_value $end +$var reg 2 ]H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @5 value $end +$var reg 4 @K value $end $upscope $end $upscope $end $upscope $end $scope struct \[64] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^2 adj_value $end +$var reg 2 ^H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 A5 value $end +$var reg 4 AK value $end $upscope $end $upscope $end $upscope $end $scope struct \[65] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 _2 adj_value $end +$var reg 2 _H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 B5 value $end +$var reg 4 BK value $end $upscope $end $upscope $end $upscope $end $scope struct \[66] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 `2 adj_value $end +$var reg 2 `H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 C5 value $end +$var reg 4 CK value $end $upscope $end $upscope $end $upscope $end $scope struct \[67] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 a2 adj_value $end +$var reg 2 aH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 D5 value $end +$var reg 4 DK value $end $upscope $end $upscope $end $upscope $end $scope struct \[68] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 b2 adj_value $end +$var reg 2 bH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 E5 value $end +$var reg 4 EK value $end $upscope $end $upscope $end $upscope $end $scope struct \[69] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 c2 adj_value $end +$var reg 2 cH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 F5 value $end +$var reg 4 FK value $end $upscope $end $upscope $end $upscope $end $scope struct \[70] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 d2 adj_value $end +$var reg 2 dH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 G5 value $end +$var reg 4 GK value $end $upscope $end $upscope $end $upscope $end $scope struct \[71] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 e2 adj_value $end +$var reg 2 eH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 H5 value $end +$var reg 4 HK value $end $upscope $end $upscope $end $upscope $end $scope struct \[72] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 f2 adj_value $end +$var reg 2 fH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 I5 value $end +$var reg 4 IK value $end $upscope $end $upscope $end $upscope $end $scope struct \[73] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 g2 adj_value $end +$var reg 2 gH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 J5 value $end +$var reg 4 JK value $end $upscope $end $upscope $end $upscope $end $scope struct \[74] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 h2 adj_value $end +$var reg 2 hH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 K5 value $end +$var reg 4 KK value $end $upscope $end $upscope $end $upscope $end $scope struct \[75] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 i2 adj_value $end +$var reg 2 iH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 L5 value $end +$var reg 4 LK value $end $upscope $end $upscope $end $upscope $end $scope struct \[76] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 j2 adj_value $end +$var reg 2 jH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 M5 value $end +$var reg 4 MK value $end $upscope $end $upscope $end $upscope $end $scope struct \[77] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 k2 adj_value $end +$var reg 2 kH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 N5 value $end +$var reg 4 NK value $end $upscope $end $upscope $end $upscope $end $scope struct \[78] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 l2 adj_value $end +$var reg 2 lH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 O5 value $end +$var reg 4 OK value $end $upscope $end $upscope $end $upscope $end $scope struct \[79] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 m2 adj_value $end +$var reg 2 mH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 P5 value $end +$var reg 4 PK value $end $upscope $end $upscope $end $upscope $end $scope struct \[80] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 n2 adj_value $end +$var reg 2 nH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Q5 value $end +$var reg 4 QK value $end $upscope $end $upscope $end $upscope $end $scope struct \[81] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 o2 adj_value $end +$var reg 2 oH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 R5 value $end +$var reg 4 RK value $end $upscope $end $upscope $end $upscope $end $scope struct \[82] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 p2 adj_value $end +$var reg 2 pH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 S5 value $end +$var reg 4 SK value $end $upscope $end $upscope $end $upscope $end $scope struct \[83] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 q2 adj_value $end +$var reg 2 qH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 T5 value $end +$var reg 4 TK value $end $upscope $end $upscope $end $upscope $end $scope struct \[84] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 r2 adj_value $end +$var reg 2 rH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 U5 value $end +$var reg 4 UK value $end $upscope $end $upscope $end $upscope $end $scope struct \[85] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 s2 adj_value $end +$var reg 2 sH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 V5 value $end +$var reg 4 VK value $end $upscope $end $upscope $end $upscope $end $scope struct \[86] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 t2 adj_value $end +$var reg 2 tH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 W5 value $end +$var reg 4 WK value $end $upscope $end $upscope $end $upscope $end $scope struct \[87] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 u2 adj_value $end +$var reg 2 uH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 X5 value $end +$var reg 4 XK value $end $upscope $end $upscope $end $upscope $end $scope struct \[88] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 v2 adj_value $end +$var reg 2 vH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Y5 value $end +$var reg 4 YK value $end $upscope $end $upscope $end $upscope $end $scope struct \[89] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 w2 adj_value $end +$var reg 2 wH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Z5 value $end +$var reg 4 ZK value $end $upscope $end $upscope $end $upscope $end $scope struct \[90] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 x2 adj_value $end +$var reg 2 xH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 [5 value $end +$var reg 4 [K value $end $upscope $end $upscope $end $upscope $end $scope struct \[91] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 y2 adj_value $end +$var reg 2 yH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 \5 value $end +$var reg 4 \K value $end $upscope $end $upscope $end $upscope $end $scope struct \[92] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 z2 adj_value $end +$var reg 2 zH adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ]5 value $end +$var reg 4 ]K value $end $upscope $end $upscope $end $upscope $end $scope struct \[93] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 {2 adj_value $end +$var reg 2 {H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ^5 value $end +$var reg 4 ^K value $end $upscope $end $upscope $end $upscope $end $scope struct \[94] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |2 adj_value $end +$var reg 2 |H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _5 value $end +$var reg 4 _K value $end $upscope $end $upscope $end $upscope $end $scope struct \[95] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }2 adj_value $end +$var reg 2 }H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `5 value $end +$var reg 4 `K value $end $upscope $end $upscope $end $upscope $end $scope struct \[96] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~2 adj_value $end +$var reg 2 ~H adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 a5 value $end +$var reg 4 aK value $end $upscope $end $upscope $end $upscope $end $scope struct \[97] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !3 adj_value $end +$var reg 2 !I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 b5 value $end +$var reg 4 bK value $end $upscope $end $upscope $end $upscope $end $scope struct \[98] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "3 adj_value $end +$var reg 2 "I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 c5 value $end +$var reg 4 cK value $end $upscope $end $upscope $end $upscope $end $scope struct \[99] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #3 adj_value $end +$var reg 2 #I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 d5 value $end +$var reg 4 dK value $end $upscope $end $upscope $end $upscope $end $scope struct \[100] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $3 adj_value $end +$var reg 2 $I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 e5 value $end +$var reg 4 eK value $end $upscope $end $upscope $end $upscope $end $scope struct \[101] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %3 adj_value $end +$var reg 2 %I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 f5 value $end +$var reg 4 fK value $end $upscope $end $upscope $end $upscope $end $scope struct \[102] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &3 adj_value $end +$var reg 2 &I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 g5 value $end +$var reg 4 gK value $end $upscope $end $upscope $end $upscope $end $scope struct \[103] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 '3 adj_value $end +$var reg 2 'I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 h5 value $end +$var reg 4 hK value $end $upscope $end $upscope $end $upscope $end $scope struct \[104] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (3 adj_value $end +$var reg 2 (I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 i5 value $end +$var reg 4 iK value $end $upscope $end $upscope $end $upscope $end $scope struct \[105] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )3 adj_value $end +$var reg 2 )I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 j5 value $end +$var reg 4 jK value $end $upscope $end $upscope $end $upscope $end $scope struct \[106] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *3 adj_value $end +$var reg 2 *I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 k5 value $end +$var reg 4 kK value $end $upscope $end $upscope $end $upscope $end $scope struct \[107] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +3 adj_value $end +$var reg 2 +I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 l5 value $end +$var reg 4 lK value $end $upscope $end $upscope $end $upscope $end $scope struct \[108] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,3 adj_value $end +$var reg 2 ,I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 m5 value $end +$var reg 4 mK value $end $upscope $end $upscope $end $upscope $end $scope struct \[109] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -3 adj_value $end +$var reg 2 -I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 n5 value $end +$var reg 4 nK value $end $upscope $end $upscope $end $upscope $end $scope struct \[110] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .3 adj_value $end +$var reg 2 .I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 o5 value $end +$var reg 4 oK value $end $upscope $end $upscope $end $upscope $end $scope struct \[111] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /3 adj_value $end +$var reg 2 /I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 p5 value $end +$var reg 4 pK value $end $upscope $end $upscope $end $upscope $end $scope struct \[112] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 03 adj_value $end +$var reg 2 0I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 q5 value $end +$var reg 4 qK value $end $upscope $end $upscope $end $upscope $end $scope struct \[113] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 13 adj_value $end +$var reg 2 1I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 r5 value $end +$var reg 4 rK value $end $upscope $end $upscope $end $upscope $end $scope struct \[114] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 23 adj_value $end +$var reg 2 2I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 s5 value $end +$var reg 4 sK value $end $upscope $end $upscope $end $upscope $end $scope struct \[115] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 33 adj_value $end +$var reg 2 3I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 t5 value $end +$var reg 4 tK value $end $upscope $end $upscope $end $upscope $end $scope struct \[116] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 43 adj_value $end +$var reg 2 4I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 u5 value $end +$var reg 4 uK value $end $upscope $end $upscope $end $upscope $end $scope struct \[117] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 53 adj_value $end +$var reg 2 5I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 v5 value $end +$var reg 4 vK value $end $upscope $end $upscope $end $upscope $end $scope struct \[118] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 63 adj_value $end +$var reg 2 6I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 w5 value $end +$var reg 4 wK value $end $upscope $end $upscope $end $upscope $end $scope struct \[119] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 73 adj_value $end +$var reg 2 7I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 x5 value $end +$var reg 4 xK value $end $upscope $end $upscope $end $upscope $end $scope struct \[120] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 83 adj_value $end +$var reg 2 8I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 y5 value $end +$var reg 4 yK value $end $upscope $end $upscope $end $upscope $end $scope struct \[121] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 93 adj_value $end +$var reg 2 9I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 z5 value $end +$var reg 4 zK value $end $upscope $end $upscope $end $upscope $end $scope struct \[122] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 :3 adj_value $end +$var reg 2 :I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {5 value $end +$var reg 4 {K value $end $upscope $end $upscope $end $upscope $end $scope struct \[123] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ;3 adj_value $end +$var reg 2 ;I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 |5 value $end +$var reg 4 |K value $end $upscope $end $upscope $end $upscope $end $scope struct \[124] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 <3 adj_value $end +$var reg 2 3 adj_value $end +$var reg 2 >I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 !6 value $end +$var reg 4 !L value $end $upscope $end $upscope $end $upscope $end $scope struct \[127] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ?3 adj_value $end +$var reg 2 ?I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 "6 value $end +$var reg 4 "L value $end $upscope $end $upscope $end $upscope $end $scope struct \[128] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 @3 adj_value $end +$var reg 2 @I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 #6 value $end +$var reg 4 #L value $end $upscope $end $upscope $end $upscope $end $scope struct \[129] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 A3 adj_value $end +$var reg 2 AI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 $6 value $end +$var reg 4 $L value $end $upscope $end $upscope $end $upscope $end $scope struct \[130] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 B3 adj_value $end +$var reg 2 BI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 %6 value $end +$var reg 4 %L value $end $upscope $end $upscope $end $upscope $end $scope struct \[131] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 C3 adj_value $end +$var reg 2 CI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 &6 value $end +$var reg 4 &L value $end $upscope $end $upscope $end $upscope $end $scope struct \[132] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 D3 adj_value $end +$var reg 2 DI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 '6 value $end +$var reg 4 'L value $end $upscope $end $upscope $end $upscope $end $scope struct \[133] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 E3 adj_value $end +$var reg 2 EI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 (6 value $end +$var reg 4 (L value $end $upscope $end $upscope $end $upscope $end $scope struct \[134] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 F3 adj_value $end +$var reg 2 FI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 )6 value $end +$var reg 4 )L value $end $upscope $end $upscope $end $upscope $end $scope struct \[135] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 G3 adj_value $end +$var reg 2 GI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 *6 value $end +$var reg 4 *L value $end $upscope $end $upscope $end $upscope $end $scope struct \[136] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 H3 adj_value $end +$var reg 2 HI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 +6 value $end +$var reg 4 +L value $end $upscope $end $upscope $end $upscope $end $scope struct \[137] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 I3 adj_value $end +$var reg 2 II adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ,6 value $end +$var reg 4 ,L value $end $upscope $end $upscope $end $upscope $end $scope struct \[138] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 J3 adj_value $end +$var reg 2 JI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 -6 value $end +$var reg 4 -L value $end $upscope $end $upscope $end $upscope $end $scope struct \[139] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 K3 adj_value $end +$var reg 2 KI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 .6 value $end +$var reg 4 .L value $end $upscope $end $upscope $end $upscope $end $scope struct \[140] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 L3 adj_value $end +$var reg 2 LI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 /6 value $end +$var reg 4 /L value $end $upscope $end $upscope $end $upscope $end $scope struct \[141] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 M3 adj_value $end +$var reg 2 MI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 06 value $end +$var reg 4 0L value $end $upscope $end $upscope $end $upscope $end $scope struct \[142] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 N3 adj_value $end +$var reg 2 NI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 16 value $end +$var reg 4 1L value $end $upscope $end $upscope $end $upscope $end $scope struct \[143] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 O3 adj_value $end +$var reg 2 OI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 26 value $end +$var reg 4 2L value $end $upscope $end $upscope $end $upscope $end $scope struct \[144] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 P3 adj_value $end +$var reg 2 PI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 36 value $end +$var reg 4 3L value $end $upscope $end $upscope $end $upscope $end $scope struct \[145] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Q3 adj_value $end +$var reg 2 QI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 46 value $end +$var reg 4 4L value $end $upscope $end $upscope $end $upscope $end $scope struct \[146] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 R3 adj_value $end +$var reg 2 RI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 56 value $end +$var reg 4 5L value $end $upscope $end $upscope $end $upscope $end $scope struct \[147] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 S3 adj_value $end +$var reg 2 SI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 66 value $end +$var reg 4 6L value $end $upscope $end $upscope $end $upscope $end $scope struct \[148] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 T3 adj_value $end +$var reg 2 TI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 76 value $end +$var reg 4 7L value $end $upscope $end $upscope $end $upscope $end $scope struct \[149] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 U3 adj_value $end +$var reg 2 UI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 86 value $end +$var reg 4 8L value $end $upscope $end $upscope $end $upscope $end $scope struct \[150] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 V3 adj_value $end +$var reg 2 VI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 96 value $end +$var reg 4 9L value $end $upscope $end $upscope $end $upscope $end $scope struct \[151] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 W3 adj_value $end +$var reg 2 WI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :6 value $end +$var reg 4 :L value $end $upscope $end $upscope $end $upscope $end $scope struct \[152] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 X3 adj_value $end +$var reg 2 XI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;6 value $end +$var reg 4 ;L value $end $upscope $end $upscope $end $upscope $end $scope struct \[153] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Y3 adj_value $end +$var reg 2 YI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 <6 value $end +$var reg 4 6 value $end +$var reg 4 >L value $end $upscope $end $upscope $end $upscope $end $scope struct \[156] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \3 adj_value $end +$var reg 2 \I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?6 value $end +$var reg 4 ?L value $end $upscope $end $upscope $end $upscope $end $scope struct \[157] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]3 adj_value $end +$var reg 2 ]I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @6 value $end +$var reg 4 @L value $end $upscope $end $upscope $end $upscope $end $scope struct \[158] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^3 adj_value $end +$var reg 2 ^I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 A6 value $end +$var reg 4 AL value $end $upscope $end $upscope $end $upscope $end $scope struct \[159] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 _3 adj_value $end +$var reg 2 _I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 B6 value $end +$var reg 4 BL value $end $upscope $end $upscope $end $upscope $end $scope struct \[160] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 `3 adj_value $end +$var reg 2 `I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 C6 value $end +$var reg 4 CL value $end $upscope $end $upscope $end $upscope $end $scope struct \[161] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 a3 adj_value $end +$var reg 2 aI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 D6 value $end +$var reg 4 DL value $end $upscope $end $upscope $end $upscope $end $scope struct \[162] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 b3 adj_value $end +$var reg 2 bI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 E6 value $end +$var reg 4 EL value $end $upscope $end $upscope $end $upscope $end $scope struct \[163] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 c3 adj_value $end +$var reg 2 cI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 F6 value $end +$var reg 4 FL value $end $upscope $end $upscope $end $upscope $end $scope struct \[164] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 d3 adj_value $end +$var reg 2 dI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 G6 value $end +$var reg 4 GL value $end $upscope $end $upscope $end $upscope $end $scope struct \[165] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 e3 adj_value $end +$var reg 2 eI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 H6 value $end +$var reg 4 HL value $end $upscope $end $upscope $end $upscope $end $scope struct \[166] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 f3 adj_value $end +$var reg 2 fI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 I6 value $end +$var reg 4 IL value $end $upscope $end $upscope $end $upscope $end $scope struct \[167] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 g3 adj_value $end +$var reg 2 gI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 J6 value $end +$var reg 4 JL value $end $upscope $end $upscope $end $upscope $end $scope struct \[168] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 h3 adj_value $end +$var reg 2 hI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 K6 value $end +$var reg 4 KL value $end $upscope $end $upscope $end $upscope $end $scope struct \[169] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 i3 adj_value $end +$var reg 2 iI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 L6 value $end +$var reg 4 LL value $end $upscope $end $upscope $end $upscope $end $scope struct \[170] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 j3 adj_value $end +$var reg 2 jI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 M6 value $end +$var reg 4 ML value $end $upscope $end $upscope $end $upscope $end $scope struct \[171] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 k3 adj_value $end +$var reg 2 kI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 N6 value $end +$var reg 4 NL value $end $upscope $end $upscope $end $upscope $end $scope struct \[172] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 l3 adj_value $end +$var reg 2 lI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 O6 value $end +$var reg 4 OL value $end $upscope $end $upscope $end $upscope $end $scope struct \[173] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 m3 adj_value $end +$var reg 2 mI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 P6 value $end +$var reg 4 PL value $end $upscope $end $upscope $end $upscope $end $scope struct \[174] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 n3 adj_value $end +$var reg 2 nI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Q6 value $end +$var reg 4 QL value $end $upscope $end $upscope $end $upscope $end $scope struct \[175] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 o3 adj_value $end +$var reg 2 oI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 R6 value $end +$var reg 4 RL value $end $upscope $end $upscope $end $upscope $end $scope struct \[176] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 p3 adj_value $end +$var reg 2 pI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 S6 value $end +$var reg 4 SL value $end $upscope $end $upscope $end $upscope $end $scope struct \[177] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 q3 adj_value $end +$var reg 2 qI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 T6 value $end +$var reg 4 TL value $end $upscope $end $upscope $end $upscope $end $scope struct \[178] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 r3 adj_value $end +$var reg 2 rI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 U6 value $end +$var reg 4 UL value $end $upscope $end $upscope $end $upscope $end $scope struct \[179] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 s3 adj_value $end +$var reg 2 sI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 V6 value $end +$var reg 4 VL value $end $upscope $end $upscope $end $upscope $end $scope struct \[180] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 t3 adj_value $end +$var reg 2 tI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 W6 value $end +$var reg 4 WL value $end $upscope $end $upscope $end $upscope $end $scope struct \[181] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 u3 adj_value $end +$var reg 2 uI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 X6 value $end +$var reg 4 XL value $end $upscope $end $upscope $end $upscope $end $scope struct \[182] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 v3 adj_value $end +$var reg 2 vI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Y6 value $end +$var reg 4 YL value $end $upscope $end $upscope $end $upscope $end $scope struct \[183] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 w3 adj_value $end +$var reg 2 wI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 Z6 value $end +$var reg 4 ZL value $end $upscope $end $upscope $end $upscope $end $scope struct \[184] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 x3 adj_value $end +$var reg 2 xI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 [6 value $end +$var reg 4 [L value $end $upscope $end $upscope $end $upscope $end $scope struct \[185] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 y3 adj_value $end +$var reg 2 yI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 \6 value $end +$var reg 4 \L value $end $upscope $end $upscope $end $upscope $end $scope struct \[186] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 z3 adj_value $end +$var reg 2 zI adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ]6 value $end +$var reg 4 ]L value $end $upscope $end $upscope $end $upscope $end $scope struct \[187] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 {3 adj_value $end +$var reg 2 {I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ^6 value $end +$var reg 4 ^L value $end $upscope $end $upscope $end $upscope $end $scope struct \[188] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 |3 adj_value $end +$var reg 2 |I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 _6 value $end +$var reg 4 _L value $end $upscope $end $upscope $end $upscope $end $scope struct \[189] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 }3 adj_value $end +$var reg 2 }I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 `6 value $end +$var reg 4 `L value $end $upscope $end $upscope $end $upscope $end $scope struct \[190] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ~3 adj_value $end +$var reg 2 ~I adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 a6 value $end +$var reg 4 aL value $end $upscope $end $upscope $end $upscope $end $scope struct \[191] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 !4 adj_value $end +$var reg 2 !J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 b6 value $end +$var reg 4 bL value $end $upscope $end $upscope $end $upscope $end $scope struct \[192] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 "4 adj_value $end +$var reg 2 "J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 c6 value $end +$var reg 4 cL value $end $upscope $end $upscope $end $upscope $end $scope struct \[193] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 #4 adj_value $end +$var reg 2 #J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 d6 value $end +$var reg 4 dL value $end $upscope $end $upscope $end $upscope $end $scope struct \[194] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 $4 adj_value $end +$var reg 2 $J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 e6 value $end +$var reg 4 eL value $end $upscope $end $upscope $end $upscope $end $scope struct \[195] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 %4 adj_value $end +$var reg 2 %J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 f6 value $end +$var reg 4 fL value $end $upscope $end $upscope $end $upscope $end $scope struct \[196] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 &4 adj_value $end +$var reg 2 &J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 g6 value $end +$var reg 4 gL value $end $upscope $end $upscope $end $upscope $end $scope struct \[197] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 '4 adj_value $end +$var reg 2 'J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 h6 value $end +$var reg 4 hL value $end $upscope $end $upscope $end $upscope $end $scope struct \[198] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 (4 adj_value $end +$var reg 2 (J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 i6 value $end +$var reg 4 iL value $end $upscope $end $upscope $end $upscope $end $scope struct \[199] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 )4 adj_value $end +$var reg 2 )J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 j6 value $end +$var reg 4 jL value $end $upscope $end $upscope $end $upscope $end $scope struct \[200] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 *4 adj_value $end +$var reg 2 *J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 k6 value $end +$var reg 4 kL value $end $upscope $end $upscope $end $upscope $end $scope struct \[201] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 +4 adj_value $end +$var reg 2 +J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 l6 value $end +$var reg 4 lL value $end $upscope $end $upscope $end $upscope $end $scope struct \[202] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ,4 adj_value $end +$var reg 2 ,J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 m6 value $end +$var reg 4 mL value $end $upscope $end $upscope $end $upscope $end $scope struct \[203] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 -4 adj_value $end +$var reg 2 -J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 n6 value $end +$var reg 4 nL value $end $upscope $end $upscope $end $upscope $end $scope struct \[204] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 .4 adj_value $end +$var reg 2 .J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 o6 value $end +$var reg 4 oL value $end $upscope $end $upscope $end $upscope $end $scope struct \[205] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 /4 adj_value $end +$var reg 2 /J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 p6 value $end +$var reg 4 pL value $end $upscope $end $upscope $end $upscope $end $scope struct \[206] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 04 adj_value $end +$var reg 2 0J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 q6 value $end +$var reg 4 qL value $end $upscope $end $upscope $end $upscope $end $scope struct \[207] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 14 adj_value $end +$var reg 2 1J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 r6 value $end +$var reg 4 rL value $end $upscope $end $upscope $end $upscope $end $scope struct \[208] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 24 adj_value $end +$var reg 2 2J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 s6 value $end +$var reg 4 sL value $end $upscope $end $upscope $end $upscope $end $scope struct \[209] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 34 adj_value $end +$var reg 2 3J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 t6 value $end +$var reg 4 tL value $end $upscope $end $upscope $end $upscope $end $scope struct \[210] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 44 adj_value $end +$var reg 2 4J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 u6 value $end +$var reg 4 uL value $end $upscope $end $upscope $end $upscope $end $scope struct \[211] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 54 adj_value $end +$var reg 2 5J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 v6 value $end +$var reg 4 vL value $end $upscope $end $upscope $end $upscope $end $scope struct \[212] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 64 adj_value $end +$var reg 2 6J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 w6 value $end +$var reg 4 wL value $end $upscope $end $upscope $end $upscope $end $scope struct \[213] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 74 adj_value $end +$var reg 2 7J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 x6 value $end +$var reg 4 xL value $end $upscope $end $upscope $end $upscope $end $scope struct \[214] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 84 adj_value $end +$var reg 2 8J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 y6 value $end +$var reg 4 yL value $end $upscope $end $upscope $end $upscope $end $scope struct \[215] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 94 adj_value $end +$var reg 2 9J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 z6 value $end +$var reg 4 zL value $end $upscope $end $upscope $end $upscope $end $scope struct \[216] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 :4 adj_value $end +$var reg 2 :J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 {6 value $end +$var reg 4 {L value $end $upscope $end $upscope $end $upscope $end $scope struct \[217] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ;4 adj_value $end +$var reg 2 ;J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 |6 value $end +$var reg 4 |L value $end $upscope $end $upscope $end $upscope $end $scope struct \[218] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 <4 adj_value $end +$var reg 2 4 adj_value $end +$var reg 2 >J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 !7 value $end +$var reg 4 !M value $end $upscope $end $upscope $end $upscope $end $scope struct \[221] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ?4 adj_value $end +$var reg 2 ?J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 "7 value $end +$var reg 4 "M value $end $upscope $end $upscope $end $upscope $end $scope struct \[222] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 @4 adj_value $end +$var reg 2 @J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 #7 value $end +$var reg 4 #M value $end $upscope $end $upscope $end $upscope $end $scope struct \[223] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 A4 adj_value $end +$var reg 2 AJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 $7 value $end +$var reg 4 $M value $end $upscope $end $upscope $end $upscope $end $scope struct \[224] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 B4 adj_value $end +$var reg 2 BJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 %7 value $end +$var reg 4 %M value $end $upscope $end $upscope $end $upscope $end $scope struct \[225] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 C4 adj_value $end +$var reg 2 CJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 &7 value $end +$var reg 4 &M value $end $upscope $end $upscope $end $upscope $end $scope struct \[226] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 D4 adj_value $end +$var reg 2 DJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 '7 value $end +$var reg 4 'M value $end $upscope $end $upscope $end $upscope $end $scope struct \[227] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 E4 adj_value $end +$var reg 2 EJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 (7 value $end +$var reg 4 (M value $end $upscope $end $upscope $end $upscope $end $scope struct \[228] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 F4 adj_value $end +$var reg 2 FJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 )7 value $end +$var reg 4 )M value $end $upscope $end $upscope $end $upscope $end $scope struct \[229] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 G4 adj_value $end +$var reg 2 GJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 *7 value $end +$var reg 4 *M value $end $upscope $end $upscope $end $upscope $end $scope struct \[230] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 H4 adj_value $end +$var reg 2 HJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 +7 value $end +$var reg 4 +M value $end $upscope $end $upscope $end $upscope $end $scope struct \[231] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 I4 adj_value $end +$var reg 2 IJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ,7 value $end +$var reg 4 ,M value $end $upscope $end $upscope $end $upscope $end $scope struct \[232] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 J4 adj_value $end +$var reg 2 JJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 -7 value $end +$var reg 4 -M value $end $upscope $end $upscope $end $upscope $end $scope struct \[233] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 K4 adj_value $end +$var reg 2 KJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 .7 value $end +$var reg 4 .M value $end $upscope $end $upscope $end $upscope $end $scope struct \[234] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 L4 adj_value $end +$var reg 2 LJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 /7 value $end +$var reg 4 /M value $end $upscope $end $upscope $end $upscope $end $scope struct \[235] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 M4 adj_value $end +$var reg 2 MJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 07 value $end +$var reg 4 0M value $end $upscope $end $upscope $end $upscope $end $scope struct \[236] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 N4 adj_value $end +$var reg 2 NJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 17 value $end +$var reg 4 1M value $end $upscope $end $upscope $end $upscope $end $scope struct \[237] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 O4 adj_value $end +$var reg 2 OJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 27 value $end +$var reg 4 2M value $end $upscope $end $upscope $end $upscope $end $scope struct \[238] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 P4 adj_value $end +$var reg 2 PJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 37 value $end +$var reg 4 3M value $end $upscope $end $upscope $end $upscope $end $scope struct \[239] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Q4 adj_value $end +$var reg 2 QJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 47 value $end +$var reg 4 4M value $end $upscope $end $upscope $end $upscope $end $scope struct \[240] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 R4 adj_value $end +$var reg 2 RJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 57 value $end +$var reg 4 5M value $end $upscope $end $upscope $end $upscope $end $scope struct \[241] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 S4 adj_value $end +$var reg 2 SJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 67 value $end +$var reg 4 6M value $end $upscope $end $upscope $end $upscope $end $scope struct \[242] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 T4 adj_value $end +$var reg 2 TJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 77 value $end +$var reg 4 7M value $end $upscope $end $upscope $end $upscope $end $scope struct \[243] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 U4 adj_value $end +$var reg 2 UJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 87 value $end +$var reg 4 8M value $end $upscope $end $upscope $end $upscope $end $scope struct \[244] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 V4 adj_value $end +$var reg 2 VJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 97 value $end +$var reg 4 9M value $end $upscope $end $upscope $end $upscope $end $scope struct \[245] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 W4 adj_value $end +$var reg 2 WJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 :7 value $end +$var reg 4 :M value $end $upscope $end $upscope $end $upscope $end $scope struct \[246] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 X4 adj_value $end +$var reg 2 XJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ;7 value $end +$var reg 4 ;M value $end $upscope $end $upscope $end $upscope $end $scope struct \[247] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 Y4 adj_value $end +$var reg 2 YJ adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 <7 value $end +$var reg 4 7 value $end +$var reg 4 >M value $end $upscope $end $upscope $end $upscope $end $scope struct \[250] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 \4 adj_value $end +$var reg 2 \J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 ?7 value $end +$var reg 4 ?M value $end $upscope $end $upscope $end $upscope $end $scope struct \[251] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ]4 adj_value $end +$var reg 2 ]J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 @7 value $end +$var reg 4 @M value $end $upscope $end $upscope $end $upscope $end $scope struct \[252] $end $scope struct rename_table_normal_mem $end $scope struct unit_num $end -$var reg 2 ^4 adj_value $end +$var reg 2 ^J adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 A7 value $end +$var reg 4 AM value $end $upscope $end $upscope $end $upscope $end @@ -3296,20 +3296,20 @@ $scope struct contents $end $scope struct \[0] $end $scope struct rename_table_special_mem $end $scope struct unit_num $end -$var reg 2 B7 adj_value $end +$var reg 2 BM adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 D7 value $end +$var reg 4 DM value $end $upscope $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct rename_table_special_mem $end $scope struct unit_num $end -$var reg 2 C7 adj_value $end +$var reg 2 CM adj_value $end $upscope $end $scope struct unit_out_reg $end -$var reg 4 E7 value $end +$var reg 4 EM value $end $upscope $end $upscope $end $upscope $end @@ -5599,86 +5599,178 @@ $var wire 2 ]+ HdlSome $end $upscope $end $scope struct unit_0 $end $scope struct cd $end -$var wire 1 &, clk $end -$var wire 1 ', rst $end +$var wire 1 ^6 clk $end +$var wire 1 _6 rst $end $upscope $end -$scope struct input $end +$scope struct input_insn $end $scope struct data $end -$var string 1 (, \$tag $end +$var string 1 `6 \$tag $end $scope struct HdlSome $end -$var string 1 ), \$tag $end +$var string 1 a6 \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 *, prefix_pad $end +$var string 0 b6 prefix_pad $end $scope struct dest $end -$var wire 4 +, value $end +$var wire 4 c6 value $end $upscope $end $scope struct src $end -$var wire 6 ,, \[0] $end -$var wire 6 -, \[1] $end -$var wire 6 ., \[2] $end +$var wire 6 d6 \[0] $end +$var wire 6 e6 \[1] $end +$var wire 6 f6 \[2] $end $upscope $end -$var wire 25 /, imm_low $end -$var wire 1 0, imm_sign $end +$var wire 25 g6 imm_low $end +$var wire 1 h6 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 1, output_integer_mode $end +$var string 1 i6 output_integer_mode $end $upscope $end -$var wire 1 2, invert_src0 $end -$var wire 1 3, invert_carry_in $end -$var wire 1 4, invert_carry_out $end -$var wire 1 5, add_pc $end +$var wire 1 j6 invert_src0 $end +$var wire 1 k6 invert_carry_in $end +$var wire 1 l6 invert_carry_out $end +$var wire 1 m6 add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 6, prefix_pad $end +$var string 0 n6 prefix_pad $end $scope struct dest $end -$var wire 4 7, value $end +$var wire 4 o6 value $end $upscope $end $scope struct src $end -$var wire 6 8, \[0] $end -$var wire 6 9, \[1] $end -$var wire 6 :, \[2] $end +$var wire 6 p6 \[0] $end +$var wire 6 q6 \[1] $end +$var wire 6 r6 \[2] $end $upscope $end -$var wire 25 ;, imm_low $end -$var wire 1 <, imm_sign $end +$var wire 25 s6 imm_low $end +$var wire 1 t6 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 =, output_integer_mode $end +$var string 1 u6 output_integer_mode $end $upscope $end -$var wire 1 >, invert_src0 $end -$var wire 1 ?, invert_carry_in $end -$var wire 1 @, invert_carry_out $end -$var wire 1 A, add_pc $end +$var wire 1 v6 invert_src0 $end +$var wire 1 w6 invert_carry_in $end +$var wire 1 x6 invert_carry_out $end +$var wire 1 y6 add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 B, prefix_pad $end +$var string 0 z6 prefix_pad $end $scope struct dest $end -$var wire 4 C, value $end +$var wire 4 {6 value $end $upscope $end $scope struct src $end -$var wire 6 D, \[0] $end -$var wire 6 E, \[1] $end -$var wire 6 F, \[2] $end +$var wire 6 |6 \[0] $end +$var wire 6 }6 \[1] $end +$var wire 6 ~6 \[2] $end $upscope $end -$var wire 25 G, imm_low $end -$var wire 1 H, imm_sign $end +$var wire 25 !7 imm_low $end +$var wire 1 "7 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 I, output_integer_mode $end +$var string 1 #7 output_integer_mode $end $upscope $end -$var wire 4 J, lut $end +$var wire 4 $7 lut $end $upscope $end $upscope $end $upscope $end -$var wire 1 K, ready $end +$var wire 1 %7 ready $end +$upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 &7 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 '7 value $end +$upscope $end +$scope struct value $end +$var wire 64 (7 int_fp $end +$scope struct flags $end +$var wire 1 )7 pwr_ca_x86_cf $end +$var wire 1 *7 pwr_ca32_x86_af $end +$var wire 1 +7 pwr_ov_x86_of $end +$var wire 1 ,7 pwr_ov32_x86_df $end +$var wire 1 -7 pwr_cr_lt_x86_sf $end +$var wire 1 .7 pwr_cr_gt_x86_pf $end +$var wire 1 /7 pwr_cr_eq_x86_zf $end +$var wire 1 07 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 17 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 27 value $end +$upscope $end +$scope struct value $end +$var wire 64 37 int_fp $end +$scope struct flags $end +$var wire 1 47 pwr_ca_x86_cf $end +$var wire 1 57 pwr_ca32_x86_af $end +$var wire 1 67 pwr_ov_x86_of $end +$var wire 1 77 pwr_ov32_x86_df $end +$var wire 1 87 pwr_cr_lt_x86_sf $end +$var wire 1 97 pwr_cr_gt_x86_pf $end +$var wire 1 :7 pwr_cr_eq_x86_zf $end +$var wire 1 ;7 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 <7 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 =7 value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 >7 ready $end +$upscope $end +$scope struct output $end +$scope struct data $end +$var string 1 ?7 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 @7 value $end +$upscope $end +$scope struct result $end +$var string 1 A7 \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 B7 int_fp $end +$scope struct flags $end +$var wire 1 C7 pwr_ca_x86_cf $end +$var wire 1 D7 pwr_ca32_x86_af $end +$var wire 1 E7 pwr_ov_x86_of $end +$var wire 1 F7 pwr_ov32_x86_df $end +$var wire 1 G7 pwr_cr_lt_x86_sf $end +$var wire 1 H7 pwr_cr_gt_x86_pf $end +$var wire 1 I7 pwr_cr_eq_x86_zf $end +$var wire 1 J7 pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 K7 ready $end $upscope $end $upscope $end $scope module alu_branch $end @@ -5686,7 +5778,7 @@ $scope struct cd $end $var wire 1 ^+ clk $end $var wire 1 _+ rst $end $upscope $end -$scope struct input $end +$scope struct input_insn $end $scope struct data $end $var string 1 `+ \$tag $end $scope struct HdlSome $end @@ -5764,1586 +5856,5762 @@ $upscope $end $upscope $end $var wire 1 %, ready $end $upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 &, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ', value $end $upscope $end -$scope struct unit_0_free_regs_tracker $end +$scope struct value $end +$var wire 64 (, int_fp $end +$scope struct flags $end +$var wire 1 ), pwr_ca_x86_cf $end +$var wire 1 *, pwr_ca32_x86_af $end +$var wire 1 +, pwr_ov_x86_of $end +$var wire 1 ,, pwr_ov32_x86_df $end +$var wire 1 -, pwr_cr_lt_x86_sf $end +$var wire 1 ., pwr_cr_gt_x86_pf $end +$var wire 1 /, pwr_cr_eq_x86_zf $end +$var wire 1 0, pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 1, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 2, value $end +$upscope $end +$scope struct value $end +$var wire 64 3, int_fp $end +$scope struct flags $end +$var wire 1 4, pwr_ca_x86_cf $end +$var wire 1 5, pwr_ca32_x86_af $end +$var wire 1 6, pwr_ov_x86_of $end +$var wire 1 7, pwr_ov32_x86_df $end +$var wire 1 8, pwr_cr_lt_x86_sf $end +$var wire 1 9, pwr_cr_gt_x86_pf $end +$var wire 1 :, pwr_cr_eq_x86_zf $end +$var wire 1 ;, pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 <, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 =, value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 >, ready $end +$upscope $end +$scope struct output $end +$scope struct data $end +$var string 1 ?, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 @, value $end +$upscope $end +$scope struct result $end +$var string 1 A, \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 B, int_fp $end +$scope struct flags $end +$var wire 1 C, pwr_ca_x86_cf $end +$var wire 1 D, pwr_ca32_x86_af $end +$var wire 1 E, pwr_ov_x86_of $end +$var wire 1 F, pwr_ov32_x86_df $end +$var wire 1 G, pwr_cr_lt_x86_sf $end +$var wire 1 H, pwr_cr_gt_x86_pf $end +$var wire 1 I, pwr_cr_eq_x86_zf $end +$var wire 1 J, pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 K, ready $end +$upscope $end +$scope struct unit_base $end $scope struct cd $end -$var wire 1 7- clk $end -$var wire 1 8- rst $end +$var wire 1 >5 clk $end +$var wire 1 ?5 rst $end $upscope $end -$scope struct free_in $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end $scope struct \[0] $end +$var string 1 @5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 A5 value $end +$upscope $end +$scope struct value $end +$var wire 64 B5 int_fp $end +$scope struct flags $end +$var wire 1 C5 pwr_ca_x86_cf $end +$var wire 1 D5 pwr_ca32_x86_af $end +$var wire 1 E5 pwr_ov_x86_of $end +$var wire 1 F5 pwr_ov32_x86_df $end +$var wire 1 G5 pwr_cr_lt_x86_sf $end +$var wire 1 H5 pwr_cr_gt_x86_pf $end +$var wire 1 I5 pwr_cr_eq_x86_zf $end +$var wire 1 J5 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 K5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 L5 value $end +$upscope $end +$scope struct value $end +$var wire 64 M5 int_fp $end +$scope struct flags $end +$var wire 1 N5 pwr_ca_x86_cf $end +$var wire 1 O5 pwr_ca32_x86_af $end +$var wire 1 P5 pwr_ov_x86_of $end +$var wire 1 Q5 pwr_ov32_x86_df $end +$var wire 1 R5 pwr_cr_lt_x86_sf $end +$var wire 1 S5 pwr_cr_gt_x86_pf $end +$var wire 1 T5 pwr_cr_eq_x86_zf $end +$var wire 1 U5 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input_insn $end $scope struct data $end -$var string 1 9- \$tag $end -$var wire 4 :- HdlSome $end +$var string 1 V5 \$tag $end +$scope struct HdlSome $end +$var string 1 W5 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 X5 prefix_pad $end +$scope struct dest $end +$var wire 4 Y5 value $end $upscope $end -$var wire 1 ;- ready $end +$scope struct src $end +$var wire 6 Z5 \[0] $end +$var wire 6 [5 \[1] $end +$var wire 6 \5 \[2] $end +$upscope $end +$var wire 25 ]5 imm_low $end +$var wire 1 ^5 imm_sign $end +$scope struct _phantom $end $upscope $end $upscope $end -$scope struct alloc_out $end +$var string 1 _5 output_integer_mode $end +$upscope $end +$var wire 1 `5 invert_src0 $end +$var wire 1 a5 invert_carry_in $end +$var wire 1 b5 invert_carry_out $end +$var wire 1 c5 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 d5 prefix_pad $end +$scope struct dest $end +$var wire 4 e5 value $end +$upscope $end +$scope struct src $end +$var wire 6 f5 \[0] $end +$var wire 6 g5 \[1] $end +$var wire 6 h5 \[2] $end +$upscope $end +$var wire 25 i5 imm_low $end +$var wire 1 j5 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 k5 output_integer_mode $end +$upscope $end +$var wire 1 l5 invert_src0 $end +$var wire 1 m5 invert_carry_in $end +$var wire 1 n5 invert_carry_out $end +$var wire 1 o5 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 p5 prefix_pad $end +$scope struct dest $end +$var wire 4 q5 value $end +$upscope $end +$scope struct src $end +$var wire 6 r5 \[0] $end +$var wire 6 s5 \[1] $end +$var wire 6 t5 \[2] $end +$upscope $end +$var wire 25 u5 imm_low $end +$var wire 1 v5 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 w5 output_integer_mode $end +$upscope $end +$var wire 4 x5 lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 y5 ready $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 z5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 {5 value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 |5 ready $end +$upscope $end +$scope struct ready_mop $end +$scope struct data $end +$var string 1 }5 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 ~5 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 !6 prefix_pad $end +$scope struct dest $end +$var wire 4 "6 value $end +$upscope $end +$scope struct src $end +$var wire 6 #6 \[0] $end +$var wire 6 $6 \[1] $end +$var wire 6 %6 \[2] $end +$upscope $end +$var wire 25 &6 imm_low $end +$var wire 1 '6 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 (6 output_integer_mode $end +$upscope $end +$var wire 1 )6 invert_src0 $end +$var wire 1 *6 invert_carry_in $end +$var wire 1 +6 invert_carry_out $end +$var wire 1 ,6 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 -6 prefix_pad $end +$scope struct dest $end +$var wire 4 .6 value $end +$upscope $end +$scope struct src $end +$var wire 6 /6 \[0] $end +$var wire 6 06 \[1] $end +$var wire 6 16 \[2] $end +$upscope $end +$var wire 25 26 imm_low $end +$var wire 1 36 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 46 output_integer_mode $end +$upscope $end +$var wire 1 56 invert_src0 $end +$var wire 1 66 invert_carry_in $end +$var wire 1 76 invert_carry_out $end +$var wire 1 86 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 96 prefix_pad $end +$scope struct dest $end +$var wire 4 :6 value $end +$upscope $end +$scope struct src $end +$var wire 6 ;6 \[0] $end +$var wire 6 <6 \[1] $end +$var wire 6 =6 \[2] $end +$upscope $end +$var wire 25 >6 imm_low $end +$var wire 1 ?6 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 @6 output_integer_mode $end +$upscope $end +$var wire 4 A6 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end $scope struct \[0] $end -$scope struct data $end -$var string 1 <- \$tag $end -$var wire 4 =- HdlSome $end +$var wire 64 B6 int_fp $end +$scope struct flags $end +$var wire 1 C6 pwr_ca_x86_cf $end +$var wire 1 D6 pwr_ca32_x86_af $end +$var wire 1 E6 pwr_ov_x86_of $end +$var wire 1 F6 pwr_ov32_x86_df $end +$var wire 1 G6 pwr_cr_lt_x86_sf $end +$var wire 1 H6 pwr_cr_gt_x86_pf $end +$var wire 1 I6 pwr_cr_eq_x86_zf $end +$var wire 1 J6 pwr_so $end $upscope $end -$var wire 1 >- ready $end +$upscope $end +$scope struct \[1] $end +$var wire 64 K6 int_fp $end +$scope struct flags $end +$var wire 1 L6 pwr_ca_x86_cf $end +$var wire 1 M6 pwr_ca32_x86_af $end +$var wire 1 N6 pwr_ov_x86_of $end +$var wire 1 O6 pwr_ov32_x86_df $end +$var wire 1 P6 pwr_cr_lt_x86_sf $end +$var wire 1 Q6 pwr_cr_gt_x86_pf $end +$var wire 1 R6 pwr_cr_eq_x86_zf $end +$var wire 1 S6 pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 T6 int_fp $end +$scope struct flags $end +$var wire 1 U6 pwr_ca_x86_cf $end +$var wire 1 V6 pwr_ca32_x86_af $end +$var wire 1 W6 pwr_ov_x86_of $end +$var wire 1 X6 pwr_ov32_x86_df $end +$var wire 1 Y6 pwr_cr_lt_x86_sf $end +$var wire 1 Z6 pwr_cr_gt_x86_pf $end +$var wire 1 [6 pwr_cr_eq_x86_zf $end +$var wire 1 \6 pwr_so $end $upscope $end $upscope $end $upscope $end -$scope module unit_free_regs_tracker $end +$upscope $end +$upscope $end +$var wire 1 ]6 ready $end +$upscope $end +$upscope $end +$scope module unit_base_2 $end $scope struct cd $end $var wire 1 L, clk $end $var wire 1 M, rst $end $upscope $end -$scope struct free_in $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end $scope struct \[0] $end -$scope struct data $end $var string 1 N, \$tag $end -$var wire 4 O, HdlSome $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 O, value $end $upscope $end -$var wire 1 P, ready $end +$scope struct value $end +$var wire 64 P, int_fp $end +$scope struct flags $end +$var wire 1 Q, pwr_ca_x86_cf $end +$var wire 1 R, pwr_ca32_x86_af $end +$var wire 1 S, pwr_ov_x86_of $end +$var wire 1 T, pwr_ov32_x86_df $end +$var wire 1 U, pwr_cr_lt_x86_sf $end +$var wire 1 V, pwr_cr_gt_x86_pf $end +$var wire 1 W, pwr_cr_eq_x86_zf $end +$var wire 1 X, pwr_so $end $upscope $end $upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Y, \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 Z, value $end +$upscope $end +$scope struct value $end +$var wire 64 [, int_fp $end +$scope struct flags $end +$var wire 1 \, pwr_ca_x86_cf $end +$var wire 1 ], pwr_ca32_x86_af $end +$var wire 1 ^, pwr_ov_x86_of $end +$var wire 1 _, pwr_ov32_x86_df $end +$var wire 1 `, pwr_cr_lt_x86_sf $end +$var wire 1 a, pwr_cr_gt_x86_pf $end +$var wire 1 b, pwr_cr_eq_x86_zf $end +$var wire 1 c, pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input_insn $end $scope struct data $end -$var string 1 Q, \$tag $end -$var wire 4 R, HdlSome $end -$upscope $end -$var wire 1 S, ready $end -$upscope $end -$upscope $end -$scope struct allocated_reg $end -$var reg 1 T, \[0] $end -$var reg 1 U, \[1] $end -$var reg 1 V, \[2] $end -$var reg 1 W, \[3] $end -$var reg 1 X, \[4] $end -$var reg 1 Y, \[5] $end -$var reg 1 Z, \[6] $end -$var reg 1 [, \[7] $end -$var reg 1 \, \[8] $end -$var reg 1 ], \[9] $end -$var reg 1 ^, \[10] $end -$var reg 1 _, \[11] $end -$var reg 1 `, \[12] $end -$var reg 1 a, \[13] $end -$var reg 1 b, \[14] $end -$var reg 1 c, \[15] $end -$upscope $end -$scope struct firing_data $end $var string 1 d, \$tag $end -$var wire 4 e, HdlSome $end +$scope struct HdlSome $end +$var string 1 e, \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 f, prefix_pad $end +$scope struct dest $end +$var wire 4 g, value $end $upscope $end -$var wire 1 f, reduced_count_0_2 $end -$var wire 1 g, reduced_count_overflowed_0_2 $end -$scope struct reduced_alloc_nums_0_2 $end -$var wire 1 h, \[0] $end +$scope struct src $end +$var wire 6 h, \[0] $end +$var wire 6 i, \[1] $end +$var wire 6 j, \[2] $end $upscope $end -$var wire 1 i, reduced_count_2_4 $end -$var wire 1 j, reduced_count_overflowed_2_4 $end -$scope struct reduced_alloc_nums_2_4 $end -$var wire 1 k, \[0] $end +$var wire 25 k, imm_low $end +$var wire 1 l, imm_sign $end +$scope struct _phantom $end $upscope $end -$var wire 1 l, reduced_count_0_4 $end -$var wire 1 m, reduced_count_overflowed_0_4 $end -$scope struct reduced_alloc_nums_0_4 $end -$var wire 2 n, \[0] $end $upscope $end -$var wire 1 o, reduced_count_4_6 $end -$var wire 1 p, reduced_count_overflowed_4_6 $end -$scope struct reduced_alloc_nums_4_6 $end -$var wire 1 q, \[0] $end +$var string 1 m, output_integer_mode $end $upscope $end -$var wire 1 r, reduced_count_6_8 $end -$var wire 1 s, reduced_count_overflowed_6_8 $end -$scope struct reduced_alloc_nums_6_8 $end -$var wire 1 t, \[0] $end +$var wire 1 n, invert_src0 $end +$var wire 1 o, invert_carry_in $end +$var wire 1 p, invert_carry_out $end +$var wire 1 q, add_pc $end $upscope $end -$var wire 1 u, reduced_count_4_8 $end -$var wire 1 v, reduced_count_overflowed_4_8 $end -$scope struct reduced_alloc_nums_4_8 $end -$var wire 2 w, \[0] $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 r, prefix_pad $end +$scope struct dest $end +$var wire 4 s, value $end $upscope $end -$var wire 1 x, reduced_count_0_8 $end -$var wire 1 y, reduced_count_overflowed_0_8 $end -$scope struct reduced_alloc_nums_0_8 $end -$var wire 3 z, \[0] $end +$scope struct src $end +$var wire 6 t, \[0] $end +$var wire 6 u, \[1] $end +$var wire 6 v, \[2] $end $upscope $end -$var wire 1 {, reduced_count_8_10 $end -$var wire 1 |, reduced_count_overflowed_8_10 $end -$scope struct reduced_alloc_nums_8_10 $end -$var wire 1 }, \[0] $end +$var wire 25 w, imm_low $end +$var wire 1 x, imm_sign $end +$scope struct _phantom $end $upscope $end -$var wire 1 ~, reduced_count_10_12 $end -$var wire 1 !- reduced_count_overflowed_10_12 $end -$scope struct reduced_alloc_nums_10_12 $end -$var wire 1 "- \[0] $end $upscope $end -$var wire 1 #- reduced_count_8_12 $end -$var wire 1 $- reduced_count_overflowed_8_12 $end -$scope struct reduced_alloc_nums_8_12 $end -$var wire 2 %- \[0] $end +$var string 1 y, output_integer_mode $end $upscope $end -$var wire 1 &- reduced_count_12_14 $end -$var wire 1 '- reduced_count_overflowed_12_14 $end -$scope struct reduced_alloc_nums_12_14 $end -$var wire 1 (- \[0] $end +$var wire 1 z, invert_src0 $end +$var wire 1 {, invert_carry_in $end +$var wire 1 |, invert_carry_out $end +$var wire 1 }, add_pc $end $upscope $end -$var wire 1 )- reduced_count_14_16 $end -$var wire 1 *- reduced_count_overflowed_14_16 $end -$scope struct reduced_alloc_nums_14_16 $end -$var wire 1 +- \[0] $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ~, prefix_pad $end +$scope struct dest $end +$var wire 4 !- value $end $upscope $end -$var wire 1 ,- reduced_count_12_16 $end -$var wire 1 -- reduced_count_overflowed_12_16 $end -$scope struct reduced_alloc_nums_12_16 $end -$var wire 2 .- \[0] $end +$scope struct src $end +$var wire 6 "- \[0] $end +$var wire 6 #- \[1] $end +$var wire 6 $- \[2] $end $upscope $end -$var wire 1 /- reduced_count_8_16 $end -$var wire 1 0- reduced_count_overflowed_8_16 $end -$scope struct reduced_alloc_nums_8_16 $end -$var wire 3 1- \[0] $end +$var wire 25 %- imm_low $end +$var wire 1 &- imm_sign $end +$scope struct _phantom $end $upscope $end -$var wire 1 2- reduced_count_0_16 $end -$var wire 1 3- reduced_count_overflowed_0_16 $end -$scope struct reduced_alloc_nums_0_16 $end -$var wire 4 4- \[0] $end $upscope $end -$scope struct firing_data_2 $end -$var string 1 5- \$tag $end -$var wire 4 6- HdlSome $end +$var string 1 '- output_integer_mode $end $upscope $end +$var wire 4 (- lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 )- ready $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 *- \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 +- value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 ,- ready $end +$upscope $end +$scope struct ready_mop $end +$scope struct data $end +$var string 1 -- \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 .- \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 /- prefix_pad $end +$scope struct dest $end +$var wire 4 0- value $end +$upscope $end +$scope struct src $end +$var wire 6 1- \[0] $end +$var wire 6 2- \[1] $end +$var wire 6 3- \[2] $end +$upscope $end +$var wire 25 4- imm_low $end +$var wire 1 5- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 6- output_integer_mode $end +$upscope $end +$var wire 1 7- invert_src0 $end +$var wire 1 8- invert_carry_in $end +$var wire 1 9- invert_carry_out $end +$var wire 1 :- add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ;- prefix_pad $end +$scope struct dest $end +$var wire 4 <- value $end +$upscope $end +$scope struct src $end +$var wire 6 =- \[0] $end +$var wire 6 >- \[1] $end +$var wire 6 ?- \[2] $end +$upscope $end +$var wire 25 @- imm_low $end +$var wire 1 A- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 B- output_integer_mode $end +$upscope $end +$var wire 1 C- invert_src0 $end +$var wire 1 D- invert_carry_in $end +$var wire 1 E- invert_carry_out $end +$var wire 1 F- add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 G- prefix_pad $end +$scope struct dest $end +$var wire 4 H- value $end +$upscope $end +$scope struct src $end +$var wire 6 I- \[0] $end +$var wire 6 J- \[1] $end +$var wire 6 K- \[2] $end +$upscope $end +$var wire 25 L- imm_low $end +$var wire 1 M- imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 N- output_integer_mode $end +$upscope $end +$var wire 4 O- lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 P- int_fp $end +$scope struct flags $end +$var wire 1 Q- pwr_ca_x86_cf $end +$var wire 1 R- pwr_ca32_x86_af $end +$var wire 1 S- pwr_ov_x86_of $end +$var wire 1 T- pwr_ov32_x86_df $end +$var wire 1 U- pwr_cr_lt_x86_sf $end +$var wire 1 V- pwr_cr_gt_x86_pf $end +$var wire 1 W- pwr_cr_eq_x86_zf $end +$var wire 1 X- pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 Y- int_fp $end +$scope struct flags $end +$var wire 1 Z- pwr_ca_x86_cf $end +$var wire 1 [- pwr_ca32_x86_af $end +$var wire 1 \- pwr_ov_x86_of $end +$var wire 1 ]- pwr_ov32_x86_df $end +$var wire 1 ^- pwr_cr_lt_x86_sf $end +$var wire 1 _- pwr_cr_gt_x86_pf $end +$var wire 1 `- pwr_cr_eq_x86_zf $end +$var wire 1 a- pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 b- int_fp $end +$scope struct flags $end +$var wire 1 c- pwr_ca_x86_cf $end +$var wire 1 d- pwr_ca32_x86_af $end +$var wire 1 e- pwr_ov_x86_of $end +$var wire 1 f- pwr_ov32_x86_df $end +$var wire 1 g- pwr_cr_lt_x86_sf $end +$var wire 1 h- pwr_cr_gt_x86_pf $end +$var wire 1 i- pwr_cr_eq_x86_zf $end +$var wire 1 j- pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 k- ready $end $upscope $end $scope struct and_then_out $end -$var string 1 ?- \$tag $end -$scope struct HdlSome $end -$var string 1 @- \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 A- prefix_pad $end -$scope struct dest $end -$var wire 4 B- value $end -$upscope $end -$scope struct src $end -$var wire 6 C- \[0] $end -$var wire 6 D- \[1] $end -$var wire 6 E- \[2] $end -$upscope $end -$var wire 25 F- imm_low $end -$var wire 1 G- imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 H- output_integer_mode $end -$upscope $end -$var wire 1 I- invert_src0 $end -$var wire 1 J- invert_carry_in $end -$var wire 1 K- invert_carry_out $end -$var wire 1 L- add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 M- prefix_pad $end -$scope struct dest $end -$var wire 4 N- value $end -$upscope $end -$scope struct src $end -$var wire 6 O- \[0] $end -$var wire 6 P- \[1] $end -$var wire 6 Q- \[2] $end -$upscope $end -$var wire 25 R- imm_low $end -$var wire 1 S- imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 T- output_integer_mode $end -$upscope $end -$var wire 1 U- invert_src0 $end -$var wire 1 V- invert_carry_in $end -$var wire 1 W- invert_carry_out $end -$var wire 1 X- add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 Y- prefix_pad $end -$scope struct dest $end -$var wire 4 Z- value $end -$upscope $end -$scope struct src $end -$var wire 6 [- \[0] $end -$var wire 6 \- \[1] $end -$var wire 6 ]- \[2] $end -$upscope $end -$var wire 25 ^- imm_low $end -$var wire 1 _- imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 `- output_integer_mode $end -$upscope $end -$var wire 4 a- lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct alu_branch_mop $end -$var string 1 b- \$tag $end -$scope struct HdlSome $end -$var string 1 c- \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 d- prefix_pad $end -$scope struct dest $end -$var wire 4 e- value $end -$upscope $end -$scope struct src $end -$var wire 6 f- \[0] $end -$var wire 6 g- \[1] $end -$var wire 6 h- \[2] $end -$upscope $end -$var wire 25 i- imm_low $end -$var wire 1 j- imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 k- output_integer_mode $end -$upscope $end -$var wire 1 l- invert_src0 $end -$var wire 1 m- invert_carry_in $end -$var wire 1 n- invert_carry_out $end -$var wire 1 o- add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 p- prefix_pad $end -$scope struct dest $end -$var wire 4 q- value $end -$upscope $end -$scope struct src $end -$var wire 6 r- \[0] $end -$var wire 6 s- \[1] $end -$var wire 6 t- \[2] $end -$upscope $end -$var wire 25 u- imm_low $end -$var wire 1 v- imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 w- output_integer_mode $end -$upscope $end -$var wire 1 x- invert_src0 $end -$var wire 1 y- invert_carry_in $end -$var wire 1 z- invert_carry_out $end -$var wire 1 {- add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 |- prefix_pad $end -$scope struct dest $end -$var wire 4 }- value $end -$upscope $end -$scope struct src $end -$var wire 6 ~- \[0] $end -$var wire 6 !. \[1] $end -$var wire 6 ". \[2] $end -$upscope $end -$var wire 25 #. imm_low $end -$var wire 1 $. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 %. output_integer_mode $end -$upscope $end -$var wire 4 &. lut $end -$upscope $end -$upscope $end +$var string 1 l- \$tag $end +$var wire 3 m- HdlSome $end $upscope $end $scope struct and_then_out_2 $end -$var string 1 '. \$tag $end -$scope struct HdlSome $end -$var string 1 (. \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 ). prefix_pad $end -$scope struct dest $end -$var wire 4 *. value $end -$upscope $end -$scope struct src $end -$var wire 6 +. \[0] $end -$var wire 6 ,. \[1] $end -$var wire 6 -. \[2] $end -$upscope $end -$var wire 25 .. imm_low $end -$var wire 1 /. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 0. output_integer_mode $end -$upscope $end -$var wire 1 1. invert_src0 $end -$var wire 1 2. invert_carry_in $end -$var wire 1 3. invert_carry_out $end -$var wire 1 4. add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 5. prefix_pad $end -$scope struct dest $end -$var wire 4 6. value $end -$upscope $end -$scope struct src $end -$var wire 6 7. \[0] $end -$var wire 6 8. \[1] $end -$var wire 6 9. \[2] $end -$upscope $end -$var wire 25 :. imm_low $end -$var wire 1 ;. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 <. output_integer_mode $end -$upscope $end -$var wire 1 =. invert_src0 $end -$var wire 1 >. invert_carry_in $end -$var wire 1 ?. invert_carry_out $end -$var wire 1 @. add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 A. prefix_pad $end -$scope struct dest $end -$var wire 4 B. value $end -$upscope $end -$scope struct src $end -$var wire 6 C. \[0] $end -$var wire 6 D. \[1] $end -$var wire 6 E. \[2] $end -$upscope $end -$var wire 25 F. imm_low $end -$var wire 1 G. imm_sign $end -$scope struct _phantom $end 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-$var string 0 X. prefix_pad $end -$scope struct dest $end -$var wire 4 Y. value $end -$upscope $end -$scope struct src $end -$var wire 6 Z. \[0] $end -$var wire 6 [. \[1] $end -$var wire 6 \. \[2] $end -$upscope $end -$var wire 25 ]. imm_low $end -$var wire 1 ^. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 _. output_integer_mode $end -$upscope $end -$var wire 1 `. invert_src0 $end -$var wire 1 a. invert_carry_in $end -$var wire 1 b. invert_carry_out $end -$var wire 1 c. add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 d. prefix_pad $end -$scope struct dest $end -$var wire 4 e. value $end -$upscope $end -$scope struct src $end -$var wire 6 f. \[0] $end -$var wire 6 g. \[1] $end -$var wire 6 h. \[2] $end -$upscope $end -$var wire 25 i. imm_low $end -$var wire 1 j. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 k. output_integer_mode $end -$upscope $end -$var wire 4 l. lut $end -$upscope $end -$upscope $end -$upscope $end -$scope struct unit_1 $end -$scope struct cd $end -$var wire 1 5/ clk $end -$var wire 1 6/ rst $end -$upscope $end -$scope struct input $end -$scope struct data $end -$var string 1 7/ \$tag $end -$scope struct HdlSome $end -$var string 1 8/ \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 9/ prefix_pad $end -$scope struct dest $end -$var wire 4 :/ value $end -$upscope $end -$scope struct src $end -$var wire 6 ;/ \[0] $end -$var wire 6 / imm_low $end -$var wire 1 ?/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 @/ output_integer_mode $end -$upscope $end -$var wire 1 A/ invert_src0 $end -$var wire 1 B/ invert_carry_in $end -$var wire 1 C/ invert_carry_out $end -$var wire 1 D/ add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 E/ prefix_pad $end -$scope struct dest $end -$var wire 4 F/ value $end -$upscope $end -$scope struct src $end -$var wire 6 G/ \[0] $end -$var wire 6 H/ \[1] $end -$var wire 6 I/ \[2] $end -$upscope $end -$var wire 25 J/ imm_low $end -$var wire 1 K/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 L/ output_integer_mode $end -$upscope $end -$var wire 1 M/ invert_src0 $end -$var wire 1 N/ invert_carry_in $end -$var wire 1 O/ invert_carry_out $end -$var wire 1 P/ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 Q/ prefix_pad $end -$scope struct dest $end -$var wire 4 R/ value $end -$upscope $end -$scope struct src $end -$var wire 6 S/ \[0] $end -$var wire 6 T/ \[1] $end -$var wire 6 U/ \[2] $end -$upscope $end -$var wire 25 V/ imm_low $end -$var wire 1 W/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 X/ output_integer_mode $end -$upscope $end -$var wire 4 Y/ lut $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 Z/ ready $end -$upscope $end -$upscope $end -$scope module alu_branch_2 $end -$scope struct cd $end -$var wire 1 m. clk $end -$var wire 1 n. rst $end -$upscope $end -$scope struct input $end -$scope struct data $end -$var string 1 o. \$tag $end -$scope struct HdlSome $end -$var string 1 p. \$tag $end -$scope struct AddSub $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 q. prefix_pad $end -$scope struct dest $end -$var wire 4 r. value $end -$upscope $end -$scope struct src $end -$var wire 6 s. \[0] $end -$var wire 6 t. \[1] $end -$var wire 6 u. \[2] $end -$upscope $end -$var wire 25 v. imm_low $end -$var wire 1 w. imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 x. output_integer_mode $end -$upscope $end -$var wire 1 y. invert_src0 $end -$var wire 1 z. invert_carry_in $end -$var wire 1 {. invert_carry_out $end -$var wire 1 |. add_pc $end -$upscope $end -$scope struct AddSubI $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 }. prefix_pad $end -$scope struct dest $end -$var wire 4 ~. value $end -$upscope $end -$scope struct src $end -$var wire 6 !/ \[0] $end -$var wire 6 "/ \[1] $end -$var wire 6 #/ \[2] $end -$upscope $end -$var wire 25 $/ imm_low $end -$var wire 1 %/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 &/ output_integer_mode $end -$upscope $end -$var wire 1 '/ invert_src0 $end -$var wire 1 (/ invert_carry_in $end -$var wire 1 )/ invert_carry_out $end -$var wire 1 */ add_pc $end -$upscope $end -$scope struct Logical $end -$scope struct alu_common $end -$scope struct common $end -$var string 0 +/ prefix_pad $end -$scope struct dest $end -$var wire 4 ,/ value $end -$upscope $end -$scope struct src $end -$var wire 6 -/ \[0] $end -$var wire 6 ./ \[1] $end -$var wire 6 // \[2] $end -$upscope $end -$var wire 25 0/ imm_low $end -$var wire 1 1/ imm_sign $end -$scope struct _phantom $end -$upscope $end -$upscope $end -$var string 1 2/ output_integer_mode $end -$upscope $end -$var wire 4 3/ lut $end -$upscope $end -$upscope $end -$upscope $end -$var wire 1 4/ ready $end -$upscope $end -$upscope $end -$scope struct unit_1_free_regs_tracker $end -$scope struct cd $end -$var wire 1 F0 clk $end -$var wire 1 G0 rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 H0 \$tag $end -$var wire 4 I0 HdlSome $end -$upscope $end -$var wire 1 J0 ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 K0 \$tag $end -$var wire 4 L0 HdlSome $end -$upscope $end -$var wire 1 M0 ready $end -$upscope $end -$upscope $end -$upscope $end -$scope module unit_free_regs_tracker_2 $end -$scope struct cd $end -$var wire 1 [/ clk $end -$var wire 1 \/ rst $end -$upscope $end -$scope struct free_in $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 ]/ \$tag $end -$var wire 4 ^/ HdlSome $end -$upscope $end -$var wire 1 _/ ready $end -$upscope $end -$upscope $end -$scope struct alloc_out $end -$scope struct \[0] $end -$scope struct data $end -$var string 1 `/ \$tag $end -$var wire 4 a/ HdlSome $end -$upscope $end -$var wire 1 b/ ready $end -$upscope $end -$upscope $end -$scope struct allocated_reg $end -$var reg 1 c/ \[0] $end -$var reg 1 d/ \[1] $end -$var reg 1 e/ \[2] $end -$var reg 1 f/ \[3] $end -$var reg 1 g/ \[4] $end -$var reg 1 h/ \[5] $end -$var reg 1 i/ \[6] $end -$var reg 1 j/ \[7] $end -$var reg 1 k/ \[8] $end -$var reg 1 l/ \[9] $end -$var reg 1 m/ \[10] $end -$var reg 1 n/ \[11] $end -$var reg 1 o/ \[12] $end -$var reg 1 p/ \[13] $end -$var reg 1 q/ \[14] $end -$var reg 1 r/ \[15] $end -$upscope $end -$scope struct firing_data $end -$var string 1 s/ \$tag $end -$var wire 4 t/ HdlSome $end -$upscope $end -$var wire 1 u/ reduced_count_0_2 $end -$var wire 1 v/ reduced_count_overflowed_0_2 $end -$scope struct reduced_alloc_nums_0_2 $end -$var wire 1 w/ \[0] $end -$upscope $end -$var wire 1 x/ reduced_count_2_4 $end -$var wire 1 y/ reduced_count_overflowed_2_4 $end -$scope struct reduced_alloc_nums_2_4 $end -$var wire 1 z/ \[0] $end -$upscope $end -$var wire 1 {/ reduced_count_0_4 $end -$var wire 1 |/ reduced_count_overflowed_0_4 $end -$scope struct reduced_alloc_nums_0_4 $end -$var wire 2 }/ \[0] $end -$upscope $end -$var wire 1 ~/ reduced_count_4_6 $end -$var wire 1 !0 reduced_count_overflowed_4_6 $end -$scope struct reduced_alloc_nums_4_6 $end -$var wire 1 "0 \[0] $end -$upscope $end -$var wire 1 #0 reduced_count_6_8 $end -$var wire 1 $0 reduced_count_overflowed_6_8 $end -$scope struct reduced_alloc_nums_6_8 $end -$var wire 1 %0 \[0] $end -$upscope $end -$var wire 1 &0 reduced_count_4_8 $end -$var wire 1 '0 reduced_count_overflowed_4_8 $end -$scope struct reduced_alloc_nums_4_8 $end -$var wire 2 (0 \[0] $end -$upscope $end -$var wire 1 )0 reduced_count_0_8 $end -$var wire 1 *0 reduced_count_overflowed_0_8 $end -$scope struct reduced_alloc_nums_0_8 $end -$var wire 3 +0 \[0] $end -$upscope $end -$var wire 1 ,0 reduced_count_8_10 $end -$var wire 1 -0 reduced_count_overflowed_8_10 $end -$scope struct reduced_alloc_nums_8_10 $end -$var wire 1 .0 \[0] $end -$upscope $end -$var wire 1 /0 reduced_count_10_12 $end -$var wire 1 00 reduced_count_overflowed_10_12 $end -$scope struct reduced_alloc_nums_10_12 $end -$var wire 1 10 \[0] $end -$upscope $end -$var wire 1 20 reduced_count_8_12 $end -$var wire 1 30 reduced_count_overflowed_8_12 $end -$scope struct reduced_alloc_nums_8_12 $end -$var wire 2 40 \[0] $end -$upscope $end -$var wire 1 50 reduced_count_12_14 $end -$var wire 1 60 reduced_count_overflowed_12_14 $end -$scope struct reduced_alloc_nums_12_14 $end -$var wire 1 70 \[0] $end -$upscope $end -$var wire 1 80 reduced_count_14_16 $end -$var wire 1 90 reduced_count_overflowed_14_16 $end -$scope struct reduced_alloc_nums_14_16 $end -$var wire 1 :0 \[0] $end -$upscope $end -$var wire 1 ;0 reduced_count_12_16 $end -$var wire 1 <0 reduced_count_overflowed_12_16 $end -$scope struct reduced_alloc_nums_12_16 $end -$var wire 2 =0 \[0] $end -$upscope $end -$var wire 1 >0 reduced_count_8_16 $end -$var wire 1 ?0 reduced_count_overflowed_8_16 $end -$scope struct reduced_alloc_nums_8_16 $end -$var wire 3 @0 \[0] $end -$upscope $end -$var wire 1 A0 reduced_count_0_16 $end -$var wire 1 B0 reduced_count_overflowed_0_16 $end -$scope struct reduced_alloc_nums_0_16 $end -$var wire 4 C0 \[0] $end -$upscope $end -$scope struct firing_data_2 $end -$var string 1 D0 \$tag $end -$var wire 4 E0 HdlSome $end -$upscope $end +$var string 1 n- \$tag $end +$var wire 3 o- HdlSome $end $upscope $end $scope struct and_then_out_3 $end -$var string 1 N0 \$tag $end +$var string 1 p- \$tag $end +$var wire 3 q- HdlSome $end +$upscope $end +$scope struct and_then_out_4 $end +$var string 1 r- \$tag $end +$var wire 3 s- HdlSome $end +$upscope $end +$scope struct and_then_out_5 $end +$var string 1 t- \$tag $end +$var wire 3 u- HdlSome $end +$upscope $end +$scope struct and_then_out_6 $end +$var string 1 v- \$tag $end +$var wire 3 w- HdlSome $end +$upscope $end +$scope struct and_then_out_7 $end +$var string 1 x- \$tag $end +$var wire 3 y- HdlSome $end +$upscope $end +$scope struct and_then_out_8 $end +$var string 1 z- \$tag $end +$var wire 3 {- HdlSome $end +$upscope $end +$scope struct in_flight_ops $end +$scope struct \[0] $end +$var string 1 |- \$tag $end $scope struct HdlSome $end -$var string 1 O0 \$tag $end +$scope struct mop $end +$var string 1 }- \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 P0 prefix_pad $end +$var string 0 ~- prefix_pad $end $scope struct dest $end -$var wire 4 Q0 value $end +$var reg 4 !. value $end $upscope $end $scope struct src $end -$var wire 6 R0 \[0] $end -$var wire 6 S0 \[1] $end -$var wire 6 T0 \[2] $end +$var reg 6 ". \[0] $end +$var reg 6 #. \[1] $end +$var reg 6 $. \[2] $end $upscope $end -$var wire 25 U0 imm_low $end -$var wire 1 V0 imm_sign $end +$var reg 25 %. imm_low $end +$var reg 1 &. imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 W0 output_integer_mode $end +$var string 1 '. output_integer_mode $end $upscope $end -$var wire 1 X0 invert_src0 $end -$var wire 1 Y0 invert_carry_in $end -$var wire 1 Z0 invert_carry_out $end -$var wire 1 [0 add_pc $end +$var reg 1 (. invert_src0 $end +$var reg 1 ). invert_carry_in $end +$var reg 1 *. invert_carry_out $end +$var reg 1 +. add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 \0 prefix_pad $end +$var string 0 ,. prefix_pad $end $scope struct dest $end -$var wire 4 ]0 value $end +$var reg 4 -. value $end $upscope $end $scope struct src $end -$var wire 6 ^0 \[0] $end -$var wire 6 _0 \[1] $end -$var wire 6 `0 \[2] $end +$var reg 6 .. \[0] $end +$var reg 6 /. \[1] $end +$var reg 6 0. \[2] $end $upscope $end -$var wire 25 a0 imm_low $end -$var wire 1 b0 imm_sign $end +$var reg 25 1. imm_low $end +$var reg 1 2. imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 c0 output_integer_mode $end +$var string 1 3. output_integer_mode $end $upscope $end -$var wire 1 d0 invert_src0 $end -$var wire 1 e0 invert_carry_in $end -$var wire 1 f0 invert_carry_out $end -$var wire 1 g0 add_pc $end +$var reg 1 4. invert_src0 $end +$var reg 1 5. invert_carry_in $end +$var reg 1 6. invert_carry_out $end +$var reg 1 7. add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end +$var string 0 8. prefix_pad $end +$scope struct dest $end +$var reg 4 9. value $end +$upscope $end +$scope struct src $end +$var reg 6 :. \[0] $end +$var reg 6 ;. \[1] $end +$var reg 6 <. \[2] $end +$upscope $end +$var reg 25 =. imm_low $end +$var reg 1 >. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ?. output_integer_mode $end +$upscope $end +$var reg 4 @. lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 A. \$tag $end +$scope struct HdlSome $end +$var reg 64 B. int_fp $end +$scope struct flags $end +$var reg 1 C. pwr_ca_x86_cf $end +$var reg 1 D. pwr_ca32_x86_af $end +$var reg 1 E. pwr_ov_x86_of $end +$var reg 1 F. pwr_ov32_x86_df $end +$var reg 1 G. pwr_cr_lt_x86_sf $end +$var reg 1 H. pwr_cr_gt_x86_pf $end +$var reg 1 I. pwr_cr_eq_x86_zf $end +$var reg 1 J. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 K. \$tag $end +$scope struct HdlSome $end +$var reg 64 L. int_fp $end +$scope struct flags $end +$var reg 1 M. pwr_ca_x86_cf $end +$var reg 1 N. pwr_ca32_x86_af $end +$var reg 1 O. pwr_ov_x86_of $end +$var reg 1 P. pwr_ov32_x86_df $end +$var reg 1 Q. pwr_cr_lt_x86_sf $end +$var reg 1 R. pwr_cr_gt_x86_pf $end +$var reg 1 S. pwr_cr_eq_x86_zf $end +$var reg 1 T. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 U. \$tag $end +$scope struct HdlSome $end +$var reg 64 V. int_fp $end +$scope struct flags $end +$var reg 1 W. pwr_ca_x86_cf $end +$var reg 1 X. pwr_ca32_x86_af $end +$var reg 1 Y. pwr_ov_x86_of $end +$var reg 1 Z. pwr_ov32_x86_df $end +$var reg 1 [. pwr_cr_lt_x86_sf $end +$var reg 1 \. pwr_cr_gt_x86_pf $end +$var reg 1 ]. pwr_cr_eq_x86_zf $end +$var reg 1 ^. pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 _. \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 `. \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 a. prefix_pad $end +$scope struct dest $end +$var reg 4 b. value $end +$upscope $end +$scope struct src $end +$var reg 6 c. \[0] $end +$var reg 6 d. \[1] $end +$var reg 6 e. \[2] $end +$upscope $end +$var reg 25 f. imm_low $end +$var reg 1 g. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 h. output_integer_mode $end +$upscope $end +$var reg 1 i. invert_src0 $end +$var reg 1 j. invert_carry_in $end +$var reg 1 k. invert_carry_out $end +$var reg 1 l. add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 m. prefix_pad $end +$scope struct dest $end +$var reg 4 n. value $end +$upscope $end +$scope struct src $end +$var reg 6 o. \[0] $end +$var reg 6 p. \[1] $end +$var reg 6 q. \[2] $end +$upscope $end +$var reg 25 r. imm_low $end +$var reg 1 s. imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 t. output_integer_mode $end +$upscope $end +$var reg 1 u. invert_src0 $end +$var reg 1 v. invert_carry_in $end +$var reg 1 w. invert_carry_out $end +$var reg 1 x. add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 y. prefix_pad $end +$scope struct dest $end +$var reg 4 z. value $end +$upscope $end +$scope struct src $end +$var reg 6 {. \[0] $end +$var reg 6 |. \[1] $end +$var reg 6 }. \[2] $end +$upscope $end +$var reg 25 ~. imm_low $end +$var reg 1 !/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 "/ output_integer_mode $end +$upscope $end +$var reg 4 #/ lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 $/ \$tag $end +$scope struct HdlSome $end +$var reg 64 %/ int_fp $end +$scope struct flags $end +$var reg 1 &/ pwr_ca_x86_cf $end +$var reg 1 '/ pwr_ca32_x86_af $end +$var reg 1 (/ pwr_ov_x86_of $end +$var reg 1 )/ pwr_ov32_x86_df $end +$var reg 1 */ pwr_cr_lt_x86_sf $end +$var reg 1 +/ pwr_cr_gt_x86_pf $end +$var reg 1 ,/ pwr_cr_eq_x86_zf $end +$var reg 1 -/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ./ \$tag $end +$scope struct HdlSome $end +$var reg 64 // int_fp $end +$scope struct flags $end +$var reg 1 0/ pwr_ca_x86_cf $end +$var reg 1 1/ pwr_ca32_x86_af $end +$var reg 1 2/ pwr_ov_x86_of $end +$var reg 1 3/ pwr_ov32_x86_df $end +$var reg 1 4/ pwr_cr_lt_x86_sf $end +$var reg 1 5/ pwr_cr_gt_x86_pf $end +$var reg 1 6/ pwr_cr_eq_x86_zf $end +$var reg 1 7/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 8/ \$tag $end +$scope struct HdlSome $end +$var reg 64 9/ int_fp $end +$scope struct flags $end +$var reg 1 :/ pwr_ca_x86_cf $end +$var reg 1 ;/ pwr_ca32_x86_af $end +$var reg 1 / pwr_cr_lt_x86_sf $end +$var reg 1 ?/ pwr_cr_gt_x86_pf $end +$var reg 1 @/ pwr_cr_eq_x86_zf $end +$var reg 1 A/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 B/ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 C/ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 D/ prefix_pad $end +$scope struct dest $end +$var reg 4 E/ value $end +$upscope $end +$scope struct src $end +$var reg 6 F/ \[0] $end +$var reg 6 G/ \[1] $end +$var reg 6 H/ \[2] $end +$upscope $end +$var reg 25 I/ imm_low $end +$var reg 1 J/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 K/ output_integer_mode $end +$upscope $end +$var reg 1 L/ invert_src0 $end +$var reg 1 M/ invert_carry_in $end +$var reg 1 N/ invert_carry_out $end +$var reg 1 O/ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 P/ prefix_pad $end +$scope struct dest $end +$var reg 4 Q/ value $end +$upscope $end +$scope struct src $end +$var reg 6 R/ \[0] $end +$var reg 6 S/ \[1] $end +$var reg 6 T/ \[2] $end +$upscope $end +$var reg 25 U/ imm_low $end +$var reg 1 V/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 W/ output_integer_mode $end +$upscope $end +$var reg 1 X/ invert_src0 $end +$var reg 1 Y/ invert_carry_in $end +$var reg 1 Z/ invert_carry_out $end +$var reg 1 [/ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 \/ prefix_pad $end +$scope struct dest $end +$var reg 4 ]/ value $end +$upscope $end +$scope struct src $end +$var reg 6 ^/ \[0] $end +$var reg 6 _/ \[1] $end +$var reg 6 `/ \[2] $end +$upscope $end +$var reg 25 a/ imm_low $end +$var reg 1 b/ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 c/ output_integer_mode $end +$upscope $end +$var reg 4 d/ lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 e/ \$tag $end +$scope struct HdlSome $end +$var reg 64 f/ int_fp $end +$scope struct flags $end +$var reg 1 g/ pwr_ca_x86_cf $end +$var reg 1 h/ pwr_ca32_x86_af $end +$var reg 1 i/ pwr_ov_x86_of $end +$var reg 1 j/ pwr_ov32_x86_df $end +$var reg 1 k/ pwr_cr_lt_x86_sf $end +$var reg 1 l/ pwr_cr_gt_x86_pf $end +$var reg 1 m/ pwr_cr_eq_x86_zf $end +$var reg 1 n/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 o/ \$tag $end +$scope struct HdlSome $end +$var reg 64 p/ int_fp $end +$scope struct flags $end +$var reg 1 q/ pwr_ca_x86_cf $end +$var reg 1 r/ pwr_ca32_x86_af $end +$var reg 1 s/ pwr_ov_x86_of $end +$var reg 1 t/ pwr_ov32_x86_df $end +$var reg 1 u/ pwr_cr_lt_x86_sf $end +$var reg 1 v/ pwr_cr_gt_x86_pf $end +$var reg 1 w/ pwr_cr_eq_x86_zf $end +$var reg 1 x/ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 y/ \$tag $end +$scope struct HdlSome $end +$var reg 64 z/ int_fp $end +$scope struct flags $end +$var reg 1 {/ pwr_ca_x86_cf $end +$var reg 1 |/ pwr_ca32_x86_af $end +$var reg 1 }/ pwr_ov_x86_of $end +$var reg 1 ~/ pwr_ov32_x86_df $end +$var reg 1 !0 pwr_cr_lt_x86_sf $end +$var reg 1 "0 pwr_cr_gt_x86_pf $end +$var reg 1 #0 pwr_cr_eq_x86_zf $end +$var reg 1 $0 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 %0 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 &0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 '0 prefix_pad $end +$scope struct dest $end +$var reg 4 (0 value $end +$upscope $end +$scope struct src $end +$var reg 6 )0 \[0] $end +$var reg 6 *0 \[1] $end +$var reg 6 +0 \[2] $end +$upscope $end +$var reg 25 ,0 imm_low $end +$var reg 1 -0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 .0 output_integer_mode $end +$upscope $end +$var reg 1 /0 invert_src0 $end +$var reg 1 00 invert_carry_in $end +$var reg 1 10 invert_carry_out $end +$var reg 1 20 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 30 prefix_pad $end +$scope struct dest $end +$var reg 4 40 value $end +$upscope $end +$scope struct src $end +$var reg 6 50 \[0] $end +$var reg 6 60 \[1] $end +$var reg 6 70 \[2] $end +$upscope $end +$var reg 25 80 imm_low $end +$var reg 1 90 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 :0 output_integer_mode $end +$upscope $end +$var reg 1 ;0 invert_src0 $end +$var reg 1 <0 invert_carry_in $end +$var reg 1 =0 invert_carry_out $end +$var reg 1 >0 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ?0 prefix_pad $end +$scope struct dest $end +$var reg 4 @0 value $end +$upscope $end +$scope struct src $end +$var reg 6 A0 \[0] $end +$var reg 6 B0 \[1] $end +$var reg 6 C0 \[2] $end +$upscope $end +$var reg 25 D0 imm_low $end +$var reg 1 E0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 F0 output_integer_mode $end +$upscope $end +$var reg 4 G0 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 H0 \$tag $end +$scope struct HdlSome $end +$var reg 64 I0 int_fp $end +$scope struct flags $end +$var reg 1 J0 pwr_ca_x86_cf $end +$var reg 1 K0 pwr_ca32_x86_af $end +$var reg 1 L0 pwr_ov_x86_of $end +$var reg 1 M0 pwr_ov32_x86_df $end +$var reg 1 N0 pwr_cr_lt_x86_sf $end +$var reg 1 O0 pwr_cr_gt_x86_pf $end +$var reg 1 P0 pwr_cr_eq_x86_zf $end +$var reg 1 Q0 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 R0 \$tag $end +$scope struct HdlSome $end +$var reg 64 S0 int_fp $end +$scope struct flags $end +$var reg 1 T0 pwr_ca_x86_cf $end +$var reg 1 U0 pwr_ca32_x86_af $end +$var reg 1 V0 pwr_ov_x86_of $end +$var reg 1 W0 pwr_ov32_x86_df $end +$var reg 1 X0 pwr_cr_lt_x86_sf $end +$var reg 1 Y0 pwr_cr_gt_x86_pf $end +$var reg 1 Z0 pwr_cr_eq_x86_zf $end +$var reg 1 [0 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 \0 \$tag $end +$scope struct HdlSome $end +$var reg 64 ]0 int_fp $end +$scope struct flags $end +$var reg 1 ^0 pwr_ca_x86_cf $end +$var reg 1 _0 pwr_ca32_x86_af $end +$var reg 1 `0 pwr_ov_x86_of $end +$var reg 1 a0 pwr_ov32_x86_df $end +$var reg 1 b0 pwr_cr_lt_x86_sf $end +$var reg 1 c0 pwr_cr_gt_x86_pf $end +$var reg 1 d0 pwr_cr_eq_x86_zf $end +$var reg 1 e0 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 f0 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 g0 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end $var string 0 h0 prefix_pad $end $scope struct dest $end -$var wire 4 i0 value $end +$var reg 4 i0 value $end $upscope $end $scope struct src $end -$var wire 6 j0 \[0] $end -$var wire 6 k0 \[1] $end -$var wire 6 l0 \[2] $end +$var reg 6 j0 \[0] $end +$var reg 6 k0 \[1] $end +$var reg 6 l0 \[2] $end $upscope $end -$var wire 25 m0 imm_low $end -$var wire 1 n0 imm_sign $end +$var reg 25 m0 imm_low $end +$var reg 1 n0 imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end $var string 1 o0 output_integer_mode $end $upscope $end -$var wire 4 p0 lut $end +$var reg 1 p0 invert_src0 $end +$var reg 1 q0 invert_carry_in $end +$var reg 1 r0 invert_carry_out $end +$var reg 1 s0 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 t0 prefix_pad $end +$scope struct dest $end +$var reg 4 u0 value $end +$upscope $end +$scope struct src $end +$var reg 6 v0 \[0] $end +$var reg 6 w0 \[1] $end +$var reg 6 x0 \[2] $end +$upscope $end +$var reg 25 y0 imm_low $end +$var reg 1 z0 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 {0 output_integer_mode $end +$upscope $end +$var reg 1 |0 invert_src0 $end +$var reg 1 }0 invert_carry_in $end +$var reg 1 ~0 invert_carry_out $end +$var reg 1 !1 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 "1 prefix_pad $end +$scope struct dest $end +$var reg 4 #1 value $end +$upscope $end +$scope struct src $end +$var reg 6 $1 \[0] $end +$var reg 6 %1 \[1] $end +$var reg 6 &1 \[2] $end +$upscope $end +$var reg 25 '1 imm_low $end +$var reg 1 (1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 )1 output_integer_mode $end +$upscope $end +$var reg 4 *1 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 +1 \$tag $end +$scope struct HdlSome $end +$var reg 64 ,1 int_fp $end +$scope struct flags $end +$var reg 1 -1 pwr_ca_x86_cf $end +$var reg 1 .1 pwr_ca32_x86_af $end +$var reg 1 /1 pwr_ov_x86_of $end +$var reg 1 01 pwr_ov32_x86_df $end +$var reg 1 11 pwr_cr_lt_x86_sf $end +$var reg 1 21 pwr_cr_gt_x86_pf $end +$var reg 1 31 pwr_cr_eq_x86_zf $end +$var reg 1 41 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 51 \$tag $end +$scope struct HdlSome $end +$var reg 64 61 int_fp $end +$scope struct flags $end +$var reg 1 71 pwr_ca_x86_cf $end +$var reg 1 81 pwr_ca32_x86_af $end +$var reg 1 91 pwr_ov_x86_of $end +$var reg 1 :1 pwr_ov32_x86_df $end +$var reg 1 ;1 pwr_cr_lt_x86_sf $end +$var reg 1 <1 pwr_cr_gt_x86_pf $end +$var reg 1 =1 pwr_cr_eq_x86_zf $end +$var reg 1 >1 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 ?1 \$tag $end +$scope struct HdlSome $end +$var reg 64 @1 int_fp $end +$scope struct flags $end +$var reg 1 A1 pwr_ca_x86_cf $end +$var reg 1 B1 pwr_ca32_x86_af $end +$var reg 1 C1 pwr_ov_x86_of $end +$var reg 1 D1 pwr_ov32_x86_df $end +$var reg 1 E1 pwr_cr_lt_x86_sf $end +$var reg 1 F1 pwr_cr_gt_x86_pf $end +$var reg 1 G1 pwr_cr_eq_x86_zf $end +$var reg 1 H1 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 I1 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 J1 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 K1 prefix_pad $end +$scope struct dest $end +$var reg 4 L1 value $end +$upscope $end +$scope struct src $end +$var reg 6 M1 \[0] $end +$var reg 6 N1 \[1] $end +$var reg 6 O1 \[2] $end +$upscope $end +$var reg 25 P1 imm_low $end +$var reg 1 Q1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 R1 output_integer_mode $end +$upscope $end +$var reg 1 S1 invert_src0 $end +$var reg 1 T1 invert_carry_in $end +$var reg 1 U1 invert_carry_out $end +$var reg 1 V1 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 W1 prefix_pad $end +$scope struct dest $end +$var reg 4 X1 value $end +$upscope $end +$scope struct src $end +$var reg 6 Y1 \[0] $end +$var reg 6 Z1 \[1] $end +$var reg 6 [1 \[2] $end +$upscope $end +$var reg 25 \1 imm_low $end +$var reg 1 ]1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ^1 output_integer_mode $end +$upscope $end +$var reg 1 _1 invert_src0 $end +$var reg 1 `1 invert_carry_in $end +$var reg 1 a1 invert_carry_out $end +$var reg 1 b1 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 c1 prefix_pad $end +$scope struct dest $end +$var reg 4 d1 value $end +$upscope $end +$scope struct src $end +$var reg 6 e1 \[0] $end +$var reg 6 f1 \[1] $end +$var reg 6 g1 \[2] $end +$upscope $end +$var reg 25 h1 imm_low $end +$var reg 1 i1 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 j1 output_integer_mode $end +$upscope $end +$var reg 4 k1 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 l1 \$tag $end +$scope struct HdlSome $end +$var reg 64 m1 int_fp $end +$scope struct flags $end +$var reg 1 n1 pwr_ca_x86_cf $end +$var reg 1 o1 pwr_ca32_x86_af $end +$var reg 1 p1 pwr_ov_x86_of $end +$var reg 1 q1 pwr_ov32_x86_df $end +$var reg 1 r1 pwr_cr_lt_x86_sf $end +$var reg 1 s1 pwr_cr_gt_x86_pf $end +$var reg 1 t1 pwr_cr_eq_x86_zf $end +$var reg 1 u1 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 v1 \$tag $end +$scope struct HdlSome $end +$var reg 64 w1 int_fp $end +$scope struct flags $end +$var reg 1 x1 pwr_ca_x86_cf $end +$var reg 1 y1 pwr_ca32_x86_af $end +$var reg 1 z1 pwr_ov_x86_of $end +$var reg 1 {1 pwr_ov32_x86_df $end +$var reg 1 |1 pwr_cr_lt_x86_sf $end +$var reg 1 }1 pwr_cr_gt_x86_pf $end +$var reg 1 ~1 pwr_cr_eq_x86_zf $end +$var reg 1 !2 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 "2 \$tag $end +$scope struct HdlSome $end +$var reg 64 #2 int_fp $end +$scope struct flags $end +$var reg 1 $2 pwr_ca_x86_cf $end +$var reg 1 %2 pwr_ca32_x86_af $end +$var reg 1 &2 pwr_ov_x86_of $end +$var reg 1 '2 pwr_ov32_x86_df $end +$var reg 1 (2 pwr_cr_lt_x86_sf $end +$var reg 1 )2 pwr_cr_gt_x86_pf $end +$var reg 1 *2 pwr_cr_eq_x86_zf $end +$var reg 1 +2 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 ,2 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 -2 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 .2 prefix_pad $end +$scope struct dest $end +$var reg 4 /2 value $end +$upscope $end +$scope struct src $end +$var reg 6 02 \[0] $end +$var reg 6 12 \[1] $end +$var reg 6 22 \[2] $end +$upscope $end +$var reg 25 32 imm_low $end +$var reg 1 42 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 52 output_integer_mode $end +$upscope $end +$var reg 1 62 invert_src0 $end +$var reg 1 72 invert_carry_in $end +$var reg 1 82 invert_carry_out $end +$var reg 1 92 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 :2 prefix_pad $end +$scope struct dest $end +$var reg 4 ;2 value $end +$upscope $end +$scope struct src $end +$var reg 6 <2 \[0] $end +$var reg 6 =2 \[1] $end +$var reg 6 >2 \[2] $end +$upscope $end +$var reg 25 ?2 imm_low $end +$var reg 1 @2 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 A2 output_integer_mode $end +$upscope $end +$var reg 1 B2 invert_src0 $end +$var reg 1 C2 invert_carry_in $end +$var reg 1 D2 invert_carry_out $end +$var reg 1 E2 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 F2 prefix_pad $end +$scope struct dest $end +$var reg 4 G2 value $end +$upscope $end +$scope struct src $end +$var reg 6 H2 \[0] $end +$var reg 6 I2 \[1] $end +$var reg 6 J2 \[2] $end +$upscope $end +$var reg 25 K2 imm_low $end +$var reg 1 L2 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 M2 output_integer_mode $end +$upscope $end +$var reg 4 N2 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 O2 \$tag $end +$scope struct HdlSome $end +$var reg 64 P2 int_fp $end +$scope struct flags $end +$var reg 1 Q2 pwr_ca_x86_cf $end +$var reg 1 R2 pwr_ca32_x86_af $end +$var reg 1 S2 pwr_ov_x86_of $end +$var reg 1 T2 pwr_ov32_x86_df $end +$var reg 1 U2 pwr_cr_lt_x86_sf $end +$var reg 1 V2 pwr_cr_gt_x86_pf $end +$var reg 1 W2 pwr_cr_eq_x86_zf $end +$var reg 1 X2 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Y2 \$tag $end +$scope struct HdlSome $end +$var reg 64 Z2 int_fp $end +$scope struct flags $end +$var reg 1 [2 pwr_ca_x86_cf $end +$var reg 1 \2 pwr_ca32_x86_af $end +$var reg 1 ]2 pwr_ov_x86_of $end +$var reg 1 ^2 pwr_ov32_x86_df $end +$var reg 1 _2 pwr_cr_lt_x86_sf $end +$var reg 1 `2 pwr_cr_gt_x86_pf $end +$var reg 1 a2 pwr_cr_eq_x86_zf $end +$var reg 1 b2 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 c2 \$tag $end +$scope struct HdlSome $end +$var reg 64 d2 int_fp $end +$scope struct flags $end +$var reg 1 e2 pwr_ca_x86_cf $end +$var reg 1 f2 pwr_ca32_x86_af $end +$var reg 1 g2 pwr_ov_x86_of $end +$var reg 1 h2 pwr_ov32_x86_df $end +$var reg 1 i2 pwr_cr_lt_x86_sf $end +$var reg 1 j2 pwr_cr_gt_x86_pf $end +$var reg 1 k2 pwr_cr_eq_x86_zf $end +$var reg 1 l2 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 m2 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 n2 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 o2 prefix_pad $end +$scope struct dest $end +$var reg 4 p2 value $end +$upscope $end +$scope struct src $end +$var reg 6 q2 \[0] $end +$var reg 6 r2 \[1] $end +$var reg 6 s2 \[2] $end +$upscope $end +$var reg 25 t2 imm_low $end +$var reg 1 u2 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 v2 output_integer_mode $end +$upscope $end +$var reg 1 w2 invert_src0 $end +$var reg 1 x2 invert_carry_in $end +$var reg 1 y2 invert_carry_out $end +$var reg 1 z2 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 {2 prefix_pad $end +$scope struct dest $end +$var reg 4 |2 value $end +$upscope $end +$scope struct src $end +$var reg 6 }2 \[0] $end +$var reg 6 ~2 \[1] $end +$var reg 6 !3 \[2] $end +$upscope $end +$var reg 25 "3 imm_low $end +$var reg 1 #3 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 $3 output_integer_mode $end +$upscope $end +$var reg 1 %3 invert_src0 $end +$var reg 1 &3 invert_carry_in $end +$var reg 1 '3 invert_carry_out $end +$var reg 1 (3 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 )3 prefix_pad $end +$scope struct dest $end +$var reg 4 *3 value $end +$upscope $end +$scope struct src $end +$var reg 6 +3 \[0] $end +$var reg 6 ,3 \[1] $end +$var reg 6 -3 \[2] $end +$upscope $end +$var reg 25 .3 imm_low $end +$var reg 1 /3 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 03 output_integer_mode $end +$upscope $end +$var reg 4 13 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 23 \$tag $end +$scope struct HdlSome $end +$var reg 64 33 int_fp $end +$scope struct flags $end +$var reg 1 43 pwr_ca_x86_cf $end +$var reg 1 53 pwr_ca32_x86_af $end +$var reg 1 63 pwr_ov_x86_of $end +$var reg 1 73 pwr_ov32_x86_df $end +$var reg 1 83 pwr_cr_lt_x86_sf $end +$var reg 1 93 pwr_cr_gt_x86_pf $end +$var reg 1 :3 pwr_cr_eq_x86_zf $end +$var reg 1 ;3 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 <3 \$tag $end +$scope struct HdlSome $end +$var reg 64 =3 int_fp $end +$scope struct flags $end +$var reg 1 >3 pwr_ca_x86_cf $end +$var reg 1 ?3 pwr_ca32_x86_af $end +$var reg 1 @3 pwr_ov_x86_of $end +$var reg 1 A3 pwr_ov32_x86_df $end +$var reg 1 B3 pwr_cr_lt_x86_sf $end +$var reg 1 C3 pwr_cr_gt_x86_pf $end +$var reg 1 D3 pwr_cr_eq_x86_zf $end +$var reg 1 E3 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 F3 \$tag $end +$scope struct HdlSome $end +$var reg 64 G3 int_fp $end +$scope struct flags $end +$var reg 1 H3 pwr_ca_x86_cf $end +$var reg 1 I3 pwr_ca32_x86_af $end +$var reg 1 J3 pwr_ov_x86_of $end +$var reg 1 K3 pwr_ov32_x86_df $end +$var reg 1 L3 pwr_cr_lt_x86_sf $end +$var reg 1 M3 pwr_cr_gt_x86_pf $end +$var reg 1 N3 pwr_cr_eq_x86_zf $end +$var reg 1 O3 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct input_index $end +$var string 1 P3 \$tag $end +$var wire 3 Q3 HdlSome $end +$upscope $end +$scope struct or_out $end +$var string 1 R3 \$tag $end +$var wire 3 S3 HdlSome $end +$upscope $end +$scope struct or_out_2 $end +$var string 1 T3 \$tag $end +$var wire 3 U3 HdlSome $end +$upscope $end +$scope struct or_out_3 $end +$var string 1 V3 \$tag $end +$var wire 3 W3 HdlSome $end +$upscope $end +$scope struct or_out_4 $end +$var string 1 X3 \$tag $end +$var wire 3 Y3 HdlSome $end +$upscope $end +$scope struct or_out_5 $end +$var string 1 Z3 \$tag $end +$var wire 3 [3 HdlSome $end +$upscope $end +$scope struct or_out_6 $end +$var string 1 \3 \$tag $end +$var wire 3 ]3 HdlSome $end +$upscope $end +$scope struct or_out_7 $end +$var string 1 ^3 \$tag $end +$var wire 3 _3 HdlSome $end +$upscope $end +$scope struct input_in_flight_op $end +$var string 1 `3 \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 a3 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 b3 prefix_pad $end +$scope struct dest $end +$var wire 4 c3 value $end +$upscope $end +$scope struct src $end +$var wire 6 d3 \[0] $end +$var wire 6 e3 \[1] $end +$var wire 6 f3 \[2] $end +$upscope $end +$var wire 25 g3 imm_low $end +$var wire 1 h3 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 i3 output_integer_mode $end +$upscope $end +$var wire 1 j3 invert_src0 $end +$var wire 1 k3 invert_carry_in $end +$var wire 1 l3 invert_carry_out $end +$var wire 1 m3 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 n3 prefix_pad $end +$scope struct dest $end +$var wire 4 o3 value $end +$upscope $end +$scope struct src $end +$var wire 6 p3 \[0] $end +$var wire 6 q3 \[1] $end +$var wire 6 r3 \[2] $end +$upscope $end +$var wire 25 s3 imm_low $end +$var wire 1 t3 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 u3 output_integer_mode $end +$upscope $end +$var wire 1 v3 invert_src0 $end +$var wire 1 w3 invert_carry_in $end +$var wire 1 x3 invert_carry_out $end +$var wire 1 y3 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 z3 prefix_pad $end +$scope struct dest $end +$var wire 4 {3 value $end +$upscope $end +$scope struct src $end +$var wire 6 |3 \[0] $end +$var wire 6 }3 \[1] $end +$var wire 6 ~3 \[2] $end +$upscope $end +$var wire 25 !4 imm_low $end +$var wire 1 "4 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 #4 output_integer_mode $end +$upscope $end +$var wire 4 $4 lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 %4 \$tag $end +$scope struct HdlSome $end +$var wire 64 &4 int_fp $end +$scope struct flags $end +$var wire 1 '4 pwr_ca_x86_cf $end +$var wire 1 (4 pwr_ca32_x86_af $end +$var wire 1 )4 pwr_ov_x86_of $end +$var wire 1 *4 pwr_ov32_x86_df $end +$var wire 1 +4 pwr_cr_lt_x86_sf $end +$var wire 1 ,4 pwr_cr_gt_x86_pf $end +$var wire 1 -4 pwr_cr_eq_x86_zf $end +$var wire 1 .4 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 /4 \$tag $end +$scope struct HdlSome $end +$var wire 64 04 int_fp $end +$scope struct flags $end +$var wire 1 14 pwr_ca_x86_cf $end +$var wire 1 24 pwr_ca32_x86_af $end +$var wire 1 34 pwr_ov_x86_of $end +$var wire 1 44 pwr_ov32_x86_df $end +$var wire 1 54 pwr_cr_lt_x86_sf $end +$var wire 1 64 pwr_cr_gt_x86_pf $end +$var wire 1 74 pwr_cr_eq_x86_zf $end +$var wire 1 84 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 94 \$tag $end +$scope struct HdlSome $end +$var wire 64 :4 int_fp $end +$scope struct flags $end +$var wire 1 ;4 pwr_ca_x86_cf $end +$var wire 1 <4 pwr_ca32_x86_af $end +$var wire 1 =4 pwr_ov_x86_of $end +$var wire 1 >4 pwr_ov32_x86_df $end +$var wire 1 ?4 pwr_cr_lt_x86_sf $end +$var wire 1 @4 pwr_cr_gt_x86_pf $end +$var wire 1 A4 pwr_cr_eq_x86_zf $end +$var wire 1 B4 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct firing_data $end +$var string 1 C4 \$tag $end +$scope struct HdlSome $end +$var string 1 D4 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 E4 prefix_pad $end +$scope struct dest $end +$var wire 4 F4 value $end +$upscope $end +$scope struct src $end +$var wire 6 G4 \[0] $end +$var wire 6 H4 \[1] $end +$var wire 6 I4 \[2] $end +$upscope $end +$var wire 25 J4 imm_low $end +$var wire 1 K4 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 L4 output_integer_mode $end +$upscope $end +$var wire 1 M4 invert_src0 $end +$var wire 1 N4 invert_carry_in $end +$var wire 1 O4 invert_carry_out $end +$var wire 1 P4 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 Q4 prefix_pad $end +$scope struct dest $end +$var wire 4 R4 value $end +$upscope $end +$scope struct src $end +$var wire 6 S4 \[0] $end +$var wire 6 T4 \[1] $end +$var wire 6 U4 \[2] $end +$upscope $end +$var wire 25 V4 imm_low $end +$var wire 1 W4 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 X4 output_integer_mode $end +$upscope $end +$var wire 1 Y4 invert_src0 $end +$var wire 1 Z4 invert_carry_in $end +$var wire 1 [4 invert_carry_out $end +$var wire 1 \4 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ]4 prefix_pad $end +$scope struct dest $end +$var wire 4 ^4 value $end +$upscope $end +$scope struct src $end +$var wire 6 _4 \[0] $end +$var wire 6 `4 \[1] $end +$var wire 6 a4 \[2] $end +$upscope $end +$var wire 25 b4 imm_low $end +$var wire 1 c4 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 d4 output_integer_mode $end +$upscope $end +$var wire 4 e4 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct input_in_flight_op_src_values $end +$scope struct \[0] $end +$var string 1 f4 \$tag $end +$scope struct HdlSome $end +$var wire 64 g4 int_fp $end +$scope struct flags $end +$var wire 1 h4 pwr_ca_x86_cf $end +$var wire 1 i4 pwr_ca32_x86_af $end +$var wire 1 j4 pwr_ov_x86_of $end +$var wire 1 k4 pwr_ov32_x86_df $end +$var wire 1 l4 pwr_cr_lt_x86_sf $end +$var wire 1 m4 pwr_cr_gt_x86_pf $end +$var wire 1 n4 pwr_cr_eq_x86_zf $end +$var wire 1 o4 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 p4 \$tag $end +$scope struct HdlSome $end +$var wire 64 q4 int_fp $end +$scope struct flags $end +$var wire 1 r4 pwr_ca_x86_cf $end +$var wire 1 s4 pwr_ca32_x86_af $end +$var wire 1 t4 pwr_ov_x86_of $end +$var wire 1 u4 pwr_ov32_x86_df $end +$var wire 1 v4 pwr_cr_lt_x86_sf $end +$var wire 1 w4 pwr_cr_gt_x86_pf $end +$var wire 1 x4 pwr_cr_eq_x86_zf $end +$var wire 1 y4 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 z4 \$tag $end +$scope struct HdlSome $end +$var wire 64 {4 int_fp $end +$scope struct flags $end +$var wire 1 |4 pwr_ca_x86_cf $end +$var wire 1 }4 pwr_ca32_x86_af $end +$var wire 1 ~4 pwr_ov_x86_of $end +$var wire 1 !5 pwr_ov32_x86_df $end +$var wire 1 "5 pwr_cr_lt_x86_sf $end +$var wire 1 #5 pwr_cr_gt_x86_pf $end +$var wire 1 $5 pwr_cr_eq_x86_zf $end +$var wire 1 %5 pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 &5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 '5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg $end +$var wire 4 (5 value $end +$upscope $end +$scope struct firing_data_3 $end +$var string 1 )5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 *5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_2 $end +$var wire 4 +5 value $end +$upscope $end +$scope struct firing_data_4 $end +$var string 1 ,5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 -5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_3 $end +$var wire 4 .5 value $end +$upscope $end +$scope struct firing_data_5 $end +$var string 1 /5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 05 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_4 $end +$var wire 4 15 value $end +$upscope $end +$scope struct firing_data_6 $end +$var string 1 25 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 35 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_5 $end +$var wire 4 45 value $end +$upscope $end +$scope struct firing_data_7 $end +$var string 1 55 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 65 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_6 $end +$var wire 4 75 value $end +$upscope $end +$scope struct firing_data_8 $end +$var string 1 85 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 95 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_7 $end +$var wire 4 :5 value $end +$upscope $end +$scope struct firing_data_9 $end +$var string 1 ;5 \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 <5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_8 $end +$var wire 4 =5 value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_0_free_regs_tracker $end +$scope struct cd $end +$var wire 1 78 clk $end +$var wire 1 88 rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 98 \$tag $end +$var wire 4 :8 HdlSome $end +$upscope $end +$var wire 1 ;8 ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 <8 \$tag $end +$var wire 4 =8 HdlSome $end +$upscope $end +$var wire 1 >8 ready $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_free_regs_tracker $end +$scope struct cd $end +$var wire 1 L7 clk $end +$var wire 1 M7 rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 N7 \$tag $end +$var wire 4 O7 HdlSome $end +$upscope $end +$var wire 1 P7 ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 Q7 \$tag $end +$var wire 4 R7 HdlSome $end +$upscope $end +$var wire 1 S7 ready $end +$upscope $end +$upscope $end +$scope struct allocated_reg $end +$var reg 1 T7 \[0] $end +$var reg 1 U7 \[1] $end +$var reg 1 V7 \[2] $end +$var reg 1 W7 \[3] $end +$var reg 1 X7 \[4] $end +$var reg 1 Y7 \[5] $end +$var reg 1 Z7 \[6] $end +$var reg 1 [7 \[7] $end +$var reg 1 \7 \[8] $end +$var reg 1 ]7 \[9] $end +$var reg 1 ^7 \[10] $end +$var reg 1 _7 \[11] $end +$var reg 1 `7 \[12] $end +$var reg 1 a7 \[13] $end +$var reg 1 b7 \[14] $end +$var reg 1 c7 \[15] $end +$upscope $end +$scope struct firing_data $end +$var string 1 d7 \$tag $end +$var wire 4 e7 HdlSome $end +$upscope $end +$var wire 1 f7 reduced_count_0_2 $end +$var wire 1 g7 reduced_count_overflowed_0_2 $end +$scope struct reduced_alloc_nums_0_2 $end +$var wire 1 h7 \[0] $end +$upscope $end +$var wire 1 i7 reduced_count_2_4 $end +$var wire 1 j7 reduced_count_overflowed_2_4 $end +$scope struct reduced_alloc_nums_2_4 $end +$var wire 1 k7 \[0] $end +$upscope $end +$var wire 1 l7 reduced_count_0_4 $end +$var wire 1 m7 reduced_count_overflowed_0_4 $end +$scope struct reduced_alloc_nums_0_4 $end +$var wire 2 n7 \[0] $end +$upscope $end +$var wire 1 o7 reduced_count_4_6 $end +$var wire 1 p7 reduced_count_overflowed_4_6 $end +$scope struct reduced_alloc_nums_4_6 $end +$var wire 1 q7 \[0] $end +$upscope $end +$var wire 1 r7 reduced_count_6_8 $end +$var wire 1 s7 reduced_count_overflowed_6_8 $end +$scope struct reduced_alloc_nums_6_8 $end +$var wire 1 t7 \[0] $end +$upscope $end +$var wire 1 u7 reduced_count_4_8 $end +$var wire 1 v7 reduced_count_overflowed_4_8 $end +$scope struct reduced_alloc_nums_4_8 $end +$var wire 2 w7 \[0] $end +$upscope $end +$var wire 1 x7 reduced_count_0_8 $end +$var wire 1 y7 reduced_count_overflowed_0_8 $end +$scope struct reduced_alloc_nums_0_8 $end +$var wire 3 z7 \[0] $end +$upscope $end +$var wire 1 {7 reduced_count_8_10 $end +$var wire 1 |7 reduced_count_overflowed_8_10 $end +$scope struct reduced_alloc_nums_8_10 $end +$var wire 1 }7 \[0] $end +$upscope $end +$var wire 1 ~7 reduced_count_10_12 $end +$var wire 1 !8 reduced_count_overflowed_10_12 $end +$scope struct reduced_alloc_nums_10_12 $end +$var wire 1 "8 \[0] $end +$upscope $end +$var wire 1 #8 reduced_count_8_12 $end +$var wire 1 $8 reduced_count_overflowed_8_12 $end +$scope struct reduced_alloc_nums_8_12 $end +$var wire 2 %8 \[0] $end +$upscope $end +$var wire 1 &8 reduced_count_12_14 $end +$var wire 1 '8 reduced_count_overflowed_12_14 $end +$scope struct reduced_alloc_nums_12_14 $end +$var wire 1 (8 \[0] $end +$upscope $end +$var wire 1 )8 reduced_count_14_16 $end +$var wire 1 *8 reduced_count_overflowed_14_16 $end +$scope struct reduced_alloc_nums_14_16 $end +$var wire 1 +8 \[0] $end +$upscope $end +$var wire 1 ,8 reduced_count_12_16 $end +$var wire 1 -8 reduced_count_overflowed_12_16 $end +$scope struct reduced_alloc_nums_12_16 $end +$var wire 2 .8 \[0] $end +$upscope $end +$var wire 1 /8 reduced_count_8_16 $end +$var wire 1 08 reduced_count_overflowed_8_16 $end +$scope struct reduced_alloc_nums_8_16 $end +$var wire 3 18 \[0] $end +$upscope $end +$var wire 1 28 reduced_count_0_16 $end +$var wire 1 38 reduced_count_overflowed_0_16 $end +$scope struct reduced_alloc_nums_0_16 $end +$var wire 4 48 \[0] $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 58 \$tag $end +$var wire 4 68 HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out $end +$var string 1 ?8 \$tag $end +$scope struct HdlSome $end +$var string 1 @8 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A8 prefix_pad $end +$scope struct dest $end +$var wire 4 B8 value $end +$upscope $end +$scope struct src $end +$var wire 6 C8 \[0] $end +$var wire 6 D8 \[1] $end +$var wire 6 E8 \[2] $end +$upscope $end +$var wire 25 F8 imm_low $end +$var wire 1 G8 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 H8 output_integer_mode $end +$upscope $end +$var wire 1 I8 invert_src0 $end +$var wire 1 J8 invert_carry_in $end +$var wire 1 K8 invert_carry_out $end +$var wire 1 L8 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 M8 prefix_pad $end +$scope struct dest $end +$var wire 4 N8 value $end +$upscope $end +$scope struct src $end +$var wire 6 O8 \[0] $end +$var wire 6 P8 \[1] $end +$var wire 6 Q8 \[2] $end +$upscope $end +$var wire 25 R8 imm_low $end +$var wire 1 S8 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 T8 output_integer_mode $end +$upscope $end +$var wire 1 U8 invert_src0 $end +$var wire 1 V8 invert_carry_in $end +$var wire 1 W8 invert_carry_out $end +$var wire 1 X8 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 Y8 prefix_pad $end +$scope struct dest $end +$var wire 4 Z8 value $end +$upscope $end +$scope struct src $end +$var wire 6 [8 \[0] $end +$var wire 6 \8 \[1] $end +$var wire 6 ]8 \[2] $end +$upscope $end +$var wire 25 ^8 imm_low $end +$var wire 1 _8 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 `8 output_integer_mode $end +$upscope $end +$var wire 4 a8 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop $end +$var string 1 b8 \$tag $end +$scope struct HdlSome $end +$var string 1 c8 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 d8 prefix_pad $end +$scope struct dest $end +$var wire 4 e8 value $end +$upscope $end +$scope struct src $end +$var wire 6 f8 \[0] $end +$var wire 6 g8 \[1] $end +$var wire 6 h8 \[2] $end +$upscope $end +$var wire 25 i8 imm_low $end +$var wire 1 j8 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 k8 output_integer_mode $end +$upscope $end +$var wire 1 l8 invert_src0 $end +$var wire 1 m8 invert_carry_in $end +$var wire 1 n8 invert_carry_out $end +$var wire 1 o8 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 p8 prefix_pad $end +$scope struct dest $end +$var wire 4 q8 value $end +$upscope $end +$scope struct src $end +$var wire 6 r8 \[0] $end +$var wire 6 s8 \[1] $end +$var wire 6 t8 \[2] $end +$upscope $end +$var wire 25 u8 imm_low $end +$var wire 1 v8 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 w8 output_integer_mode $end +$upscope $end +$var wire 1 x8 invert_src0 $end +$var wire 1 y8 invert_carry_in $end +$var wire 1 z8 invert_carry_out $end +$var wire 1 {8 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 |8 prefix_pad $end +$scope struct dest $end +$var wire 4 }8 value $end +$upscope $end +$scope struct src $end +$var wire 6 ~8 \[0] $end +$var wire 6 !9 \[1] $end +$var wire 6 "9 \[2] $end +$upscope $end +$var wire 25 #9 imm_low $end +$var wire 1 $9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 %9 output_integer_mode $end +$upscope $end +$var wire 4 &9 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct and_then_out_2 $end +$var string 1 '9 \$tag $end +$scope struct HdlSome $end +$var string 1 (9 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 )9 prefix_pad $end +$scope struct dest $end +$var wire 4 *9 value $end +$upscope $end +$scope struct src $end +$var wire 6 +9 \[0] $end +$var wire 6 ,9 \[1] $end +$var wire 6 -9 \[2] $end +$upscope $end +$var wire 25 .9 imm_low $end +$var wire 1 /9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 09 output_integer_mode $end +$upscope $end +$var wire 1 19 invert_src0 $end +$var wire 1 29 invert_carry_in $end +$var wire 1 39 invert_carry_out $end +$var wire 1 49 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 59 prefix_pad $end +$scope struct dest $end +$var wire 4 69 value $end +$upscope $end +$scope struct src $end +$var wire 6 79 \[0] $end +$var wire 6 89 \[1] $end +$var wire 6 99 \[2] $end +$upscope $end +$var wire 25 :9 imm_low $end +$var wire 1 ;9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 <9 output_integer_mode $end +$upscope $end +$var wire 1 =9 invert_src0 $end +$var wire 1 >9 invert_carry_in $end +$var wire 1 ?9 invert_carry_out $end +$var wire 1 @9 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 A9 prefix_pad $end +$scope struct dest $end +$var wire 4 B9 value $end +$upscope $end +$scope struct src $end +$var wire 6 C9 \[0] $end +$var wire 6 D9 \[1] $end +$var wire 6 E9 \[2] $end +$upscope $end +$var wire 25 F9 imm_low $end +$var wire 1 G9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 H9 output_integer_mode $end +$upscope $end +$var wire 4 I9 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct alu_branch_mop_2 $end +$var string 1 J9 \$tag $end +$scope struct HdlSome $end +$var string 1 K9 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 L9 prefix_pad $end +$scope struct dest $end +$var wire 4 M9 value $end +$upscope $end +$scope struct src $end +$var wire 6 N9 \[0] $end +$var wire 6 O9 \[1] $end +$var wire 6 P9 \[2] $end +$upscope $end +$var wire 25 Q9 imm_low $end +$var wire 1 R9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 S9 output_integer_mode $end +$upscope $end +$var wire 1 T9 invert_src0 $end +$var wire 1 U9 invert_carry_in $end +$var wire 1 V9 invert_carry_out $end +$var wire 1 W9 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 X9 prefix_pad $end +$scope struct dest $end +$var wire 4 Y9 value $end +$upscope $end +$scope struct src $end +$var wire 6 Z9 \[0] $end +$var wire 6 [9 \[1] $end +$var wire 6 \9 \[2] $end +$upscope $end +$var wire 25 ]9 imm_low $end +$var wire 1 ^9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 _9 output_integer_mode $end +$upscope $end +$var wire 1 `9 invert_src0 $end +$var wire 1 a9 invert_carry_in $end +$var wire 1 b9 invert_carry_out $end +$var wire 1 c9 add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 d9 prefix_pad $end +$scope struct dest $end +$var wire 4 e9 value $end +$upscope $end +$scope struct src $end +$var wire 6 f9 \[0] $end +$var wire 6 g9 \[1] $end +$var wire 6 h9 \[2] $end +$upscope $end +$var wire 25 i9 imm_low $end +$var wire 1 j9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 k9 output_integer_mode $end +$upscope $end +$var wire 4 l9 lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_1 $end +$scope struct cd $end +$var wire 1 mD clk $end +$var wire 1 nD rst $end +$upscope $end +$scope struct input_insn $end +$scope struct data $end +$var string 1 oD \$tag $end +$scope struct HdlSome $end +$var string 1 pD \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 qD prefix_pad $end +$scope struct dest $end +$var wire 4 rD value $end +$upscope $end +$scope struct src $end +$var wire 6 sD \[0] $end +$var wire 6 tD \[1] $end +$var wire 6 uD \[2] $end +$upscope $end +$var wire 25 vD imm_low $end +$var wire 1 wD imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 xD output_integer_mode $end +$upscope $end +$var wire 1 yD invert_src0 $end +$var wire 1 zD invert_carry_in $end +$var wire 1 {D invert_carry_out $end +$var wire 1 |D add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }D prefix_pad $end +$scope struct dest $end +$var wire 4 ~D value $end +$upscope $end +$scope struct src $end +$var wire 6 !E \[0] $end +$var wire 6 "E \[1] $end +$var wire 6 #E \[2] $end +$upscope $end +$var wire 25 $E imm_low $end +$var wire 1 %E imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &E output_integer_mode $end +$upscope $end +$var wire 1 'E invert_src0 $end +$var wire 1 (E invert_carry_in $end +$var wire 1 )E invert_carry_out $end +$var wire 1 *E add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 +E prefix_pad $end +$scope struct dest $end +$var wire 4 ,E value $end +$upscope $end +$scope struct src $end +$var wire 6 -E \[0] $end +$var wire 6 .E \[1] $end +$var wire 6 /E \[2] $end +$upscope $end +$var wire 25 0E imm_low $end +$var wire 1 1E imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 2E output_integer_mode $end +$upscope $end +$var wire 4 3E lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 4E ready $end +$upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 5E \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 6E value $end +$upscope $end +$scope struct value $end +$var wire 64 7E int_fp $end +$scope struct flags $end +$var wire 1 8E pwr_ca_x86_cf $end +$var wire 1 9E pwr_ca32_x86_af $end +$var wire 1 :E pwr_ov_x86_of $end +$var wire 1 ;E pwr_ov32_x86_df $end +$var wire 1 E pwr_cr_eq_x86_zf $end +$var wire 1 ?E pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 @E \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 AE value $end +$upscope $end +$scope struct value $end +$var wire 64 BE int_fp $end +$scope struct flags $end +$var wire 1 CE pwr_ca_x86_cf $end +$var wire 1 DE pwr_ca32_x86_af $end +$var wire 1 EE pwr_ov_x86_of $end +$var wire 1 FE pwr_ov32_x86_df $end +$var wire 1 GE pwr_cr_lt_x86_sf $end +$var wire 1 HE pwr_cr_gt_x86_pf $end +$var wire 1 IE pwr_cr_eq_x86_zf $end +$var wire 1 JE pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 KE \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 LE value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 ME ready $end +$upscope $end +$scope struct output $end +$scope struct data $end +$var string 1 NE \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 OE value $end +$upscope $end +$scope struct result $end +$var string 1 PE \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 QE int_fp $end +$scope struct flags $end +$var wire 1 RE pwr_ca_x86_cf $end +$var wire 1 SE pwr_ca32_x86_af $end +$var wire 1 TE pwr_ov_x86_of $end +$var wire 1 UE pwr_ov32_x86_df $end +$var wire 1 VE pwr_cr_lt_x86_sf $end +$var wire 1 WE pwr_cr_gt_x86_pf $end +$var wire 1 XE pwr_cr_eq_x86_zf $end +$var wire 1 YE pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 ZE ready $end +$upscope $end +$upscope $end +$scope module alu_branch_2 $end +$scope struct cd $end +$var wire 1 m9 clk $end +$var wire 1 n9 rst $end +$upscope $end +$scope struct input_insn $end +$scope struct data $end +$var string 1 o9 \$tag $end +$scope struct HdlSome $end +$var string 1 p9 \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 q9 prefix_pad $end +$scope struct dest $end +$var wire 4 r9 value $end +$upscope $end +$scope struct src $end +$var wire 6 s9 \[0] $end +$var wire 6 t9 \[1] $end +$var wire 6 u9 \[2] $end +$upscope $end +$var wire 25 v9 imm_low $end +$var wire 1 w9 imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 x9 output_integer_mode $end +$upscope $end +$var wire 1 y9 invert_src0 $end +$var wire 1 z9 invert_carry_in $end +$var wire 1 {9 invert_carry_out $end +$var wire 1 |9 add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }9 prefix_pad $end +$scope struct dest $end +$var wire 4 ~9 value $end +$upscope $end +$scope struct src $end +$var wire 6 !: \[0] $end +$var wire 6 ": \[1] $end +$var wire 6 #: \[2] $end +$upscope $end +$var wire 25 $: imm_low $end +$var wire 1 %: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &: output_integer_mode $end +$upscope $end +$var wire 1 ': invert_src0 $end +$var wire 1 (: invert_carry_in $end +$var wire 1 ): invert_carry_out $end +$var wire 1 *: add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 +: prefix_pad $end +$scope struct dest $end +$var wire 4 ,: value $end +$upscope $end +$scope struct src $end +$var wire 6 -: \[0] $end +$var wire 6 .: \[1] $end +$var wire 6 /: \[2] $end +$upscope $end +$var wire 25 0: imm_low $end +$var wire 1 1: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 2: output_integer_mode $end +$upscope $end +$var wire 4 3: lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 4: ready $end +$upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 5: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 6: value $end +$upscope $end +$scope struct value $end +$var wire 64 7: int_fp $end +$scope struct flags $end +$var wire 1 8: pwr_ca_x86_cf $end +$var wire 1 9: pwr_ca32_x86_af $end +$var wire 1 :: pwr_ov_x86_of $end +$var wire 1 ;: pwr_ov32_x86_df $end +$var wire 1 <: pwr_cr_lt_x86_sf $end +$var wire 1 =: pwr_cr_gt_x86_pf $end +$var wire 1 >: pwr_cr_eq_x86_zf $end +$var wire 1 ?: pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 @: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 A: value $end +$upscope $end +$scope struct value $end +$var wire 64 B: int_fp $end +$scope struct flags $end +$var wire 1 C: pwr_ca_x86_cf $end +$var wire 1 D: pwr_ca32_x86_af $end +$var wire 1 E: pwr_ov_x86_of $end +$var wire 1 F: pwr_ov32_x86_df $end +$var wire 1 G: pwr_cr_lt_x86_sf $end +$var wire 1 H: pwr_cr_gt_x86_pf $end +$var wire 1 I: pwr_cr_eq_x86_zf $end +$var wire 1 J: pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 K: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 L: value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 M: ready $end +$upscope $end +$scope struct output $end +$scope struct data $end +$var string 1 N: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 O: value $end +$upscope $end +$scope struct result $end +$var string 1 P: \$tag $end +$scope struct Completed $end +$scope struct value $end +$var wire 64 Q: int_fp $end +$scope struct flags $end +$var wire 1 R: pwr_ca_x86_cf $end +$var wire 1 S: pwr_ca32_x86_af $end +$var wire 1 T: pwr_ov_x86_of $end +$var wire 1 U: pwr_ov32_x86_df $end +$var wire 1 V: pwr_cr_lt_x86_sf $end +$var wire 1 W: pwr_cr_gt_x86_pf $end +$var wire 1 X: pwr_cr_eq_x86_zf $end +$var wire 1 Y: pwr_so $end +$upscope $end +$upscope $end +$scope struct extra_out $end +$upscope $end +$upscope $end +$scope struct Trap $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 Z: ready $end +$upscope $end +$scope struct unit_base $end +$scope struct cd $end +$var wire 1 MC clk $end +$var wire 1 NC rst $end +$upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 OC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 PC value $end +$upscope $end +$scope struct value $end +$var wire 64 QC int_fp $end +$scope struct flags $end +$var wire 1 RC pwr_ca_x86_cf $end +$var wire 1 SC pwr_ca32_x86_af $end +$var wire 1 TC pwr_ov_x86_of $end +$var wire 1 UC pwr_ov32_x86_df $end +$var wire 1 VC pwr_cr_lt_x86_sf $end +$var wire 1 WC pwr_cr_gt_x86_pf $end +$var wire 1 XC pwr_cr_eq_x86_zf $end +$var wire 1 YC pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ZC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 [C value $end +$upscope $end +$scope struct value $end +$var wire 64 \C int_fp $end +$scope struct flags $end +$var wire 1 ]C pwr_ca_x86_cf $end +$var wire 1 ^C pwr_ca32_x86_af $end +$var wire 1 _C pwr_ov_x86_of $end +$var wire 1 `C pwr_ov32_x86_df $end +$var wire 1 aC pwr_cr_lt_x86_sf $end +$var wire 1 bC pwr_cr_gt_x86_pf $end +$var wire 1 cC pwr_cr_eq_x86_zf $end +$var wire 1 dC pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input_insn $end +$scope struct data $end +$var string 1 eC \$tag $end +$scope struct HdlSome $end +$var string 1 fC \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 gC prefix_pad $end +$scope struct dest $end +$var wire 4 hC value $end +$upscope $end +$scope struct src $end +$var wire 6 iC \[0] $end +$var wire 6 jC \[1] $end +$var wire 6 kC \[2] $end +$upscope $end +$var wire 25 lC imm_low $end +$var wire 1 mC imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 nC output_integer_mode $end +$upscope $end +$var wire 1 oC invert_src0 $end +$var wire 1 pC invert_carry_in $end +$var wire 1 qC invert_carry_out $end +$var wire 1 rC add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 sC prefix_pad $end +$scope struct dest $end +$var wire 4 tC value $end +$upscope $end +$scope struct src $end +$var wire 6 uC \[0] $end +$var wire 6 vC \[1] $end +$var wire 6 wC \[2] $end +$upscope $end +$var wire 25 xC imm_low $end +$var wire 1 yC imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 zC output_integer_mode $end +$upscope $end +$var wire 1 {C invert_src0 $end +$var wire 1 |C invert_carry_in $end +$var wire 1 }C invert_carry_out $end +$var wire 1 ~C add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 !D prefix_pad $end +$scope struct dest $end +$var wire 4 "D value $end +$upscope $end +$scope struct src $end +$var wire 6 #D \[0] $end +$var wire 6 $D \[1] $end +$var wire 6 %D \[2] $end +$upscope $end +$var wire 25 &D imm_low $end +$var wire 1 'D imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 (D output_integer_mode $end +$upscope $end +$var wire 4 )D lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 *D ready $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 +D \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ,D value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 -D ready $end +$upscope $end +$scope struct ready_mop $end +$scope struct data $end +$var string 1 .D \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 /D \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 0D prefix_pad $end +$scope struct dest $end +$var wire 4 1D value $end +$upscope $end +$scope struct src $end +$var wire 6 2D \[0] $end +$var wire 6 3D \[1] $end +$var wire 6 4D \[2] $end +$upscope $end +$var wire 25 5D imm_low $end +$var wire 1 6D imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 7D output_integer_mode $end +$upscope $end +$var wire 1 8D invert_src0 $end +$var wire 1 9D invert_carry_in $end +$var wire 1 :D invert_carry_out $end +$var wire 1 ;D add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 D \[0] $end +$var wire 6 ?D \[1] $end +$var wire 6 @D \[2] $end +$upscope $end +$var wire 25 AD imm_low $end +$var wire 1 BD imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 CD output_integer_mode $end +$upscope $end +$var wire 1 DD invert_src0 $end +$var wire 1 ED invert_carry_in $end +$var wire 1 FD invert_carry_out $end +$var wire 1 GD add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 HD prefix_pad $end +$scope struct dest $end +$var wire 4 ID value $end +$upscope $end +$scope struct src $end +$var wire 6 JD \[0] $end +$var wire 6 KD \[1] $end +$var wire 6 LD \[2] $end +$upscope $end +$var wire 25 MD imm_low $end +$var wire 1 ND imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 OD output_integer_mode $end +$upscope $end +$var wire 4 PD lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 QD int_fp $end +$scope struct flags $end +$var wire 1 RD pwr_ca_x86_cf $end +$var wire 1 SD pwr_ca32_x86_af $end +$var wire 1 TD pwr_ov_x86_of $end +$var wire 1 UD pwr_ov32_x86_df $end +$var wire 1 VD pwr_cr_lt_x86_sf $end +$var wire 1 WD pwr_cr_gt_x86_pf $end +$var wire 1 XD pwr_cr_eq_x86_zf $end +$var wire 1 YD pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 ZD int_fp $end +$scope struct flags $end +$var wire 1 [D pwr_ca_x86_cf $end +$var wire 1 \D pwr_ca32_x86_af $end +$var wire 1 ]D pwr_ov_x86_of $end +$var wire 1 ^D pwr_ov32_x86_df $end +$var wire 1 _D pwr_cr_lt_x86_sf $end +$var wire 1 `D pwr_cr_gt_x86_pf $end +$var wire 1 aD pwr_cr_eq_x86_zf $end +$var wire 1 bD pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 cD int_fp $end +$scope struct flags $end +$var wire 1 dD pwr_ca_x86_cf $end +$var wire 1 eD pwr_ca32_x86_af $end +$var wire 1 fD pwr_ov_x86_of $end +$var wire 1 gD pwr_ov32_x86_df $end +$var wire 1 hD pwr_cr_lt_x86_sf $end +$var wire 1 iD pwr_cr_gt_x86_pf $end +$var wire 1 jD pwr_cr_eq_x86_zf $end +$var wire 1 kD pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 lD ready $end +$upscope $end +$upscope $end +$scope module unit_base_2 $end +$scope struct cd $end +$var wire 1 [: clk $end +$var wire 1 \: rst $end +$upscope $end +$scope struct unit_forwarding_info $end +$scope struct unit_output_writes $end +$scope struct \[0] $end +$var string 1 ]: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ^: value $end +$upscope $end +$scope struct value $end +$var wire 64 _: int_fp $end +$scope struct flags $end +$var wire 1 `: pwr_ca_x86_cf $end +$var wire 1 a: pwr_ca32_x86_af $end +$var wire 1 b: pwr_ov_x86_of $end +$var wire 1 c: pwr_ov32_x86_df $end +$var wire 1 d: pwr_cr_lt_x86_sf $end +$var wire 1 e: pwr_cr_gt_x86_pf $end +$var wire 1 f: pwr_cr_eq_x86_zf $end +$var wire 1 g: pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 h: \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 i: value $end +$upscope $end +$scope struct value $end +$var wire 64 j: int_fp $end +$scope struct flags $end +$var wire 1 k: pwr_ca_x86_cf $end +$var wire 1 l: pwr_ca32_x86_af $end +$var wire 1 m: pwr_ov_x86_of $end +$var wire 1 n: pwr_ov32_x86_df $end +$var wire 1 o: pwr_cr_lt_x86_sf $end +$var wire 1 p: pwr_cr_gt_x86_pf $end +$var wire 1 q: pwr_cr_eq_x86_zf $end +$var wire 1 r: pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$scope struct input_insn $end +$scope struct data $end +$var string 1 s: \$tag $end +$scope struct HdlSome $end +$var string 1 t: \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 u: prefix_pad $end +$scope struct dest $end +$var wire 4 v: value $end +$upscope $end +$scope struct src $end +$var wire 6 w: \[0] $end +$var wire 6 x: \[1] $end +$var wire 6 y: \[2] $end +$upscope $end +$var wire 25 z: imm_low $end +$var wire 1 {: imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 |: output_integer_mode $end +$upscope $end +$var wire 1 }: invert_src0 $end +$var wire 1 ~: invert_carry_in $end +$var wire 1 !; invert_carry_out $end +$var wire 1 "; add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 #; prefix_pad $end +$scope struct dest $end +$var wire 4 $; value $end +$upscope $end +$scope struct src $end +$var wire 6 %; \[0] $end +$var wire 6 &; \[1] $end +$var wire 6 '; \[2] $end +$upscope $end +$var wire 25 (; imm_low $end +$var wire 1 ); imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 *; output_integer_mode $end +$upscope $end +$var wire 1 +; invert_src0 $end +$var wire 1 ,; invert_carry_in $end +$var wire 1 -; invert_carry_out $end +$var wire 1 .; add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 /; prefix_pad $end +$scope struct dest $end +$var wire 4 0; value $end +$upscope $end +$scope struct src $end +$var wire 6 1; \[0] $end +$var wire 6 2; \[1] $end +$var wire 6 3; \[2] $end +$upscope $end +$var wire 25 4; imm_low $end +$var wire 1 5; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 6; output_integer_mode $end +$upscope $end +$var wire 4 7; lut $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 8; ready $end +$upscope $end +$scope struct cancel_input $end +$scope struct data $end +$var string 1 9; \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 :; value $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 ;; ready $end +$upscope $end +$scope struct ready_mop $end +$scope struct data $end +$var string 1 <; \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 =; \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 >; prefix_pad $end +$scope struct dest $end +$var wire 4 ?; value $end +$upscope $end +$scope struct src $end +$var wire 6 @; \[0] $end +$var wire 6 A; \[1] $end +$var wire 6 B; \[2] $end +$upscope $end +$var wire 25 C; imm_low $end +$var wire 1 D; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 E; output_integer_mode $end +$upscope $end +$var wire 1 F; invert_src0 $end +$var wire 1 G; invert_carry_in $end +$var wire 1 H; invert_carry_out $end +$var wire 1 I; add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 J; prefix_pad $end +$scope struct dest $end +$var wire 4 K; value $end +$upscope $end +$scope struct src $end +$var wire 6 L; \[0] $end +$var wire 6 M; \[1] $end +$var wire 6 N; \[2] $end +$upscope $end +$var wire 25 O; imm_low $end +$var wire 1 P; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 Q; output_integer_mode $end +$upscope $end +$var wire 1 R; invert_src0 $end +$var wire 1 S; invert_carry_in $end +$var wire 1 T; invert_carry_out $end +$var wire 1 U; add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 V; prefix_pad $end +$scope struct dest $end +$var wire 4 W; value $end +$upscope $end +$scope struct src $end +$var wire 6 X; \[0] $end +$var wire 6 Y; \[1] $end +$var wire 6 Z; \[2] $end +$upscope $end +$var wire 25 [; imm_low $end +$var wire 1 \; imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ]; output_integer_mode $end +$upscope $end +$var wire 4 ^; lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var wire 64 _; int_fp $end +$scope struct flags $end +$var wire 1 `; pwr_ca_x86_cf $end +$var wire 1 a; pwr_ca32_x86_af $end +$var wire 1 b; pwr_ov_x86_of $end +$var wire 1 c; pwr_ov32_x86_df $end +$var wire 1 d; pwr_cr_lt_x86_sf $end +$var wire 1 e; pwr_cr_gt_x86_pf $end +$var wire 1 f; pwr_cr_eq_x86_zf $end +$var wire 1 g; pwr_so $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 64 h; int_fp $end +$scope struct flags $end +$var wire 1 i; pwr_ca_x86_cf $end +$var wire 1 j; pwr_ca32_x86_af $end +$var wire 1 k; pwr_ov_x86_of $end +$var wire 1 l; pwr_ov32_x86_df $end +$var wire 1 m; pwr_cr_lt_x86_sf $end +$var wire 1 n; pwr_cr_gt_x86_pf $end +$var wire 1 o; pwr_cr_eq_x86_zf $end +$var wire 1 p; pwr_so $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var wire 64 q; int_fp $end +$scope struct flags $end +$var wire 1 r; pwr_ca_x86_cf $end +$var wire 1 s; pwr_ca32_x86_af $end +$var wire 1 t; pwr_ov_x86_of $end +$var wire 1 u; pwr_ov32_x86_df $end +$var wire 1 v; pwr_cr_lt_x86_sf $end +$var wire 1 w; pwr_cr_gt_x86_pf $end +$var wire 1 x; pwr_cr_eq_x86_zf $end +$var wire 1 y; pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$var wire 1 z; ready $end +$upscope $end +$scope struct and_then_out $end +$var string 1 {; \$tag $end +$var wire 3 |; HdlSome $end +$upscope $end +$scope struct and_then_out_2 $end +$var string 1 }; \$tag $end +$var wire 3 ~; HdlSome $end +$upscope $end +$scope struct and_then_out_3 $end +$var string 1 !< \$tag $end +$var wire 3 "< HdlSome $end +$upscope $end +$scope struct and_then_out_4 $end +$var string 1 #< \$tag $end +$var wire 3 $< HdlSome $end +$upscope $end +$scope struct and_then_out_5 $end +$var string 1 %< \$tag $end +$var wire 3 &< HdlSome $end +$upscope $end +$scope struct and_then_out_6 $end +$var string 1 '< \$tag $end +$var wire 3 (< HdlSome $end +$upscope $end +$scope struct and_then_out_7 $end +$var string 1 )< \$tag $end +$var wire 3 *< HdlSome $end +$upscope $end +$scope struct and_then_out_8 $end +$var string 1 +< \$tag $end +$var wire 3 ,< HdlSome $end +$upscope $end +$scope struct in_flight_ops $end +$scope struct \[0] $end +$var string 1 -< \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 .< \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 /< prefix_pad $end +$scope struct dest $end +$var reg 4 0< value $end +$upscope $end +$scope struct src $end +$var reg 6 1< \[0] $end +$var reg 6 2< \[1] $end +$var reg 6 3< \[2] $end +$upscope $end +$var reg 25 4< imm_low $end +$var reg 1 5< imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 6< output_integer_mode $end +$upscope $end +$var reg 1 7< invert_src0 $end +$var reg 1 8< invert_carry_in $end +$var reg 1 9< invert_carry_out $end +$var reg 1 :< add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ;< prefix_pad $end +$scope struct dest $end +$var reg 4 << value $end +$upscope $end +$scope struct src $end +$var reg 6 =< \[0] $end +$var reg 6 >< \[1] $end +$var reg 6 ?< \[2] $end +$upscope $end +$var reg 25 @< imm_low $end +$var reg 1 A< imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 B< output_integer_mode $end +$upscope $end +$var reg 1 C< invert_src0 $end +$var reg 1 D< invert_carry_in $end +$var reg 1 E< invert_carry_out $end +$var reg 1 F< add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 G< prefix_pad $end +$scope struct dest $end +$var reg 4 H< value $end +$upscope $end +$scope struct src $end +$var reg 6 I< \[0] $end +$var reg 6 J< \[1] $end +$var reg 6 K< \[2] $end +$upscope $end +$var reg 25 L< imm_low $end +$var reg 1 M< imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 N< output_integer_mode $end +$upscope $end +$var reg 4 O< lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 P< \$tag $end +$scope struct HdlSome $end +$var reg 64 Q< int_fp $end +$scope struct flags $end +$var reg 1 R< pwr_ca_x86_cf $end +$var reg 1 S< pwr_ca32_x86_af $end +$var reg 1 T< pwr_ov_x86_of $end +$var reg 1 U< pwr_ov32_x86_df $end +$var reg 1 V< pwr_cr_lt_x86_sf $end +$var reg 1 W< pwr_cr_gt_x86_pf $end +$var reg 1 X< pwr_cr_eq_x86_zf $end +$var reg 1 Y< pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 Z< \$tag $end +$scope struct HdlSome $end +$var reg 64 [< int_fp $end +$scope struct flags $end +$var reg 1 \< pwr_ca_x86_cf $end +$var reg 1 ]< pwr_ca32_x86_af $end +$var reg 1 ^< pwr_ov_x86_of $end +$var reg 1 _< pwr_ov32_x86_df $end +$var reg 1 `< pwr_cr_lt_x86_sf $end +$var reg 1 a< pwr_cr_gt_x86_pf $end +$var reg 1 b< pwr_cr_eq_x86_zf $end +$var reg 1 c< pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 d< \$tag $end +$scope struct HdlSome $end +$var reg 64 e< int_fp $end +$scope struct flags $end +$var reg 1 f< pwr_ca_x86_cf $end +$var reg 1 g< pwr_ca32_x86_af $end +$var reg 1 h< pwr_ov_x86_of $end +$var reg 1 i< pwr_ov32_x86_df $end +$var reg 1 j< pwr_cr_lt_x86_sf $end +$var reg 1 k< pwr_cr_gt_x86_pf $end +$var reg 1 l< pwr_cr_eq_x86_zf $end +$var reg 1 m< pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 n< \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 o< \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 p< prefix_pad $end +$scope struct dest $end +$var reg 4 q< value $end +$upscope $end +$scope struct src $end +$var reg 6 r< \[0] $end +$var reg 6 s< \[1] $end +$var reg 6 t< \[2] $end +$upscope $end +$var reg 25 u< imm_low $end +$var reg 1 v< imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 w< output_integer_mode $end +$upscope $end +$var reg 1 x< invert_src0 $end +$var reg 1 y< invert_carry_in $end +$var reg 1 z< invert_carry_out $end +$var reg 1 {< add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 |< prefix_pad $end +$scope struct dest $end +$var reg 4 }< value $end +$upscope $end +$scope struct src $end +$var reg 6 ~< \[0] $end +$var reg 6 != \[1] $end +$var reg 6 "= \[2] $end +$upscope $end +$var reg 25 #= imm_low $end +$var reg 1 $= imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 %= output_integer_mode $end +$upscope $end +$var reg 1 &= invert_src0 $end +$var reg 1 '= invert_carry_in $end +$var reg 1 (= invert_carry_out $end +$var reg 1 )= add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 *= prefix_pad $end +$scope struct dest $end +$var reg 4 += value $end +$upscope $end +$scope struct src $end +$var reg 6 ,= \[0] $end +$var reg 6 -= \[1] $end +$var reg 6 .= \[2] $end +$upscope $end +$var reg 25 /= imm_low $end +$var reg 1 0= imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 1= output_integer_mode $end +$upscope $end +$var reg 4 2= lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 3= \$tag $end +$scope struct HdlSome $end +$var reg 64 4= int_fp $end +$scope struct flags $end +$var reg 1 5= pwr_ca_x86_cf $end +$var reg 1 6= pwr_ca32_x86_af $end +$var reg 1 7= pwr_ov_x86_of $end +$var reg 1 8= pwr_ov32_x86_df $end +$var reg 1 9= pwr_cr_lt_x86_sf $end +$var reg 1 := pwr_cr_gt_x86_pf $end +$var reg 1 ;= pwr_cr_eq_x86_zf $end +$var reg 1 <= pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 == \$tag $end +$scope struct HdlSome $end +$var reg 64 >= int_fp $end +$scope struct flags $end +$var reg 1 ?= pwr_ca_x86_cf $end +$var reg 1 @= pwr_ca32_x86_af $end +$var reg 1 A= pwr_ov_x86_of $end +$var reg 1 B= pwr_ov32_x86_df $end +$var reg 1 C= pwr_cr_lt_x86_sf $end +$var reg 1 D= pwr_cr_gt_x86_pf $end +$var reg 1 E= pwr_cr_eq_x86_zf $end +$var reg 1 F= pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 G= \$tag $end +$scope struct HdlSome $end +$var reg 64 H= int_fp $end +$scope struct flags $end +$var reg 1 I= pwr_ca_x86_cf $end +$var reg 1 J= pwr_ca32_x86_af $end +$var reg 1 K= pwr_ov_x86_of $end +$var reg 1 L= pwr_ov32_x86_df $end +$var reg 1 M= pwr_cr_lt_x86_sf $end +$var reg 1 N= pwr_cr_gt_x86_pf $end +$var reg 1 O= pwr_cr_eq_x86_zf $end +$var reg 1 P= pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 Q= \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 R= \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 S= prefix_pad $end +$scope struct dest $end +$var reg 4 T= value $end +$upscope $end +$scope struct src $end +$var reg 6 U= \[0] $end +$var reg 6 V= \[1] $end +$var reg 6 W= \[2] $end +$upscope $end +$var reg 25 X= imm_low $end +$var reg 1 Y= imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 Z= output_integer_mode $end +$upscope $end +$var reg 1 [= invert_src0 $end +$var reg 1 \= invert_carry_in $end +$var reg 1 ]= invert_carry_out $end +$var reg 1 ^= add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 _= prefix_pad $end +$scope struct dest $end +$var reg 4 `= value $end +$upscope $end +$scope struct src $end +$var reg 6 a= \[0] $end +$var reg 6 b= \[1] $end +$var reg 6 c= \[2] $end +$upscope $end +$var reg 25 d= imm_low $end +$var reg 1 e= imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 f= output_integer_mode $end +$upscope $end +$var reg 1 g= invert_src0 $end +$var reg 1 h= invert_carry_in $end +$var reg 1 i= invert_carry_out $end +$var reg 1 j= add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 k= prefix_pad $end +$scope struct dest $end +$var reg 4 l= value $end +$upscope $end +$scope struct src $end +$var reg 6 m= \[0] $end +$var reg 6 n= \[1] $end +$var reg 6 o= \[2] $end +$upscope $end +$var reg 25 p= imm_low $end +$var reg 1 q= imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 r= output_integer_mode $end +$upscope $end +$var reg 4 s= lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 t= \$tag $end +$scope struct HdlSome $end +$var reg 64 u= int_fp $end +$scope struct flags $end +$var reg 1 v= pwr_ca_x86_cf $end +$var reg 1 w= pwr_ca32_x86_af $end +$var reg 1 x= pwr_ov_x86_of $end +$var reg 1 y= pwr_ov32_x86_df $end +$var reg 1 z= pwr_cr_lt_x86_sf $end +$var reg 1 {= pwr_cr_gt_x86_pf $end +$var reg 1 |= pwr_cr_eq_x86_zf $end +$var reg 1 }= pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 ~= \$tag $end +$scope struct HdlSome $end +$var reg 64 !> int_fp $end +$scope struct flags $end +$var reg 1 "> pwr_ca_x86_cf $end +$var reg 1 #> pwr_ca32_x86_af $end +$var reg 1 $> pwr_ov_x86_of $end +$var reg 1 %> pwr_ov32_x86_df $end +$var reg 1 &> pwr_cr_lt_x86_sf $end +$var reg 1 '> pwr_cr_gt_x86_pf $end +$var reg 1 (> pwr_cr_eq_x86_zf $end +$var reg 1 )> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 *> \$tag $end +$scope struct HdlSome $end +$var reg 64 +> int_fp $end +$scope struct flags $end +$var reg 1 ,> pwr_ca_x86_cf $end +$var reg 1 -> pwr_ca32_x86_af $end +$var reg 1 .> pwr_ov_x86_of $end +$var reg 1 /> pwr_ov32_x86_df $end +$var reg 1 0> pwr_cr_lt_x86_sf $end +$var reg 1 1> pwr_cr_gt_x86_pf $end +$var reg 1 2> pwr_cr_eq_x86_zf $end +$var reg 1 3> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 4> \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 5> \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 6> prefix_pad $end +$scope struct dest $end +$var reg 4 7> value $end +$upscope $end +$scope struct src $end +$var reg 6 8> \[0] $end +$var reg 6 9> \[1] $end +$var reg 6 :> \[2] $end +$upscope $end +$var reg 25 ;> imm_low $end +$var reg 1 <> imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 => output_integer_mode $end +$upscope $end +$var reg 1 >> invert_src0 $end +$var reg 1 ?> invert_carry_in $end +$var reg 1 @> invert_carry_out $end +$var reg 1 A> add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 B> prefix_pad $end +$scope struct dest $end +$var reg 4 C> value $end +$upscope $end +$scope struct src $end +$var reg 6 D> \[0] $end +$var reg 6 E> \[1] $end +$var reg 6 F> \[2] $end +$upscope $end +$var reg 25 G> imm_low $end +$var reg 1 H> imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 I> output_integer_mode $end +$upscope $end +$var reg 1 J> invert_src0 $end +$var reg 1 K> invert_carry_in $end +$var reg 1 L> invert_carry_out $end +$var reg 1 M> add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 N> prefix_pad $end +$scope struct dest $end +$var reg 4 O> value $end +$upscope $end +$scope struct src $end +$var reg 6 P> \[0] $end +$var reg 6 Q> \[1] $end +$var reg 6 R> \[2] $end +$upscope $end +$var reg 25 S> imm_low $end +$var reg 1 T> imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 U> output_integer_mode $end +$upscope $end +$var reg 4 V> lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 W> \$tag $end +$scope struct HdlSome $end +$var reg 64 X> int_fp $end +$scope struct flags $end +$var reg 1 Y> pwr_ca_x86_cf $end +$var reg 1 Z> pwr_ca32_x86_af $end +$var reg 1 [> pwr_ov_x86_of $end +$var reg 1 \> pwr_ov32_x86_df $end +$var reg 1 ]> pwr_cr_lt_x86_sf $end +$var reg 1 ^> pwr_cr_gt_x86_pf $end +$var reg 1 _> pwr_cr_eq_x86_zf $end +$var reg 1 `> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 a> \$tag $end +$scope struct HdlSome $end +$var reg 64 b> int_fp $end +$scope struct flags $end +$var reg 1 c> pwr_ca_x86_cf $end +$var reg 1 d> pwr_ca32_x86_af $end +$var reg 1 e> pwr_ov_x86_of $end +$var reg 1 f> pwr_ov32_x86_df $end +$var reg 1 g> pwr_cr_lt_x86_sf $end +$var reg 1 h> pwr_cr_gt_x86_pf $end +$var reg 1 i> pwr_cr_eq_x86_zf $end +$var reg 1 j> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 k> \$tag $end +$scope struct HdlSome $end +$var reg 64 l> int_fp $end +$scope struct flags $end +$var reg 1 m> pwr_ca_x86_cf $end +$var reg 1 n> pwr_ca32_x86_af $end +$var reg 1 o> pwr_ov_x86_of $end +$var reg 1 p> pwr_ov32_x86_df $end +$var reg 1 q> pwr_cr_lt_x86_sf $end +$var reg 1 r> pwr_cr_gt_x86_pf $end +$var reg 1 s> pwr_cr_eq_x86_zf $end +$var reg 1 t> pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 u> \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 v> \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 w> prefix_pad $end +$scope struct dest $end +$var reg 4 x> value $end +$upscope $end +$scope struct src $end +$var reg 6 y> \[0] $end +$var reg 6 z> \[1] $end +$var reg 6 {> \[2] $end +$upscope $end +$var reg 25 |> imm_low $end +$var reg 1 }> imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ~> output_integer_mode $end +$upscope $end +$var reg 1 !? invert_src0 $end +$var reg 1 "? invert_carry_in $end +$var reg 1 #? invert_carry_out $end +$var reg 1 $? add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 %? prefix_pad $end +$scope struct dest $end +$var reg 4 &? value $end +$upscope $end +$scope struct src $end +$var reg 6 '? \[0] $end +$var reg 6 (? \[1] $end +$var reg 6 )? \[2] $end +$upscope $end +$var reg 25 *? imm_low $end +$var reg 1 +? imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ,? output_integer_mode $end +$upscope $end +$var reg 1 -? invert_src0 $end +$var reg 1 .? invert_carry_in $end +$var reg 1 /? invert_carry_out $end +$var reg 1 0? add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 1? prefix_pad $end +$scope struct dest $end +$var reg 4 2? value $end +$upscope $end +$scope struct src $end +$var reg 6 3? \[0] $end +$var reg 6 4? \[1] $end +$var reg 6 5? \[2] $end +$upscope $end +$var reg 25 6? imm_low $end +$var reg 1 7? imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 8? output_integer_mode $end +$upscope $end +$var reg 4 9? lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 :? \$tag $end +$scope struct HdlSome $end +$var reg 64 ;? int_fp $end +$scope struct flags $end +$var reg 1 ? pwr_ov_x86_of $end +$var reg 1 ?? pwr_ov32_x86_df $end +$var reg 1 @? pwr_cr_lt_x86_sf $end +$var reg 1 A? pwr_cr_gt_x86_pf $end +$var reg 1 B? pwr_cr_eq_x86_zf $end +$var reg 1 C? pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 D? \$tag $end +$scope struct HdlSome $end +$var reg 64 E? int_fp $end +$scope struct flags $end +$var reg 1 F? pwr_ca_x86_cf $end +$var reg 1 G? pwr_ca32_x86_af $end +$var reg 1 H? pwr_ov_x86_of $end +$var reg 1 I? pwr_ov32_x86_df $end +$var reg 1 J? pwr_cr_lt_x86_sf $end +$var reg 1 K? pwr_cr_gt_x86_pf $end +$var reg 1 L? pwr_cr_eq_x86_zf $end +$var reg 1 M? pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 N? \$tag $end +$scope struct HdlSome $end +$var reg 64 O? int_fp $end +$scope struct flags $end +$var reg 1 P? pwr_ca_x86_cf $end +$var reg 1 Q? pwr_ca32_x86_af $end +$var reg 1 R? pwr_ov_x86_of $end +$var reg 1 S? pwr_ov32_x86_df $end +$var reg 1 T? pwr_cr_lt_x86_sf $end +$var reg 1 U? pwr_cr_gt_x86_pf $end +$var reg 1 V? pwr_cr_eq_x86_zf $end +$var reg 1 W? pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 X? \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 Y? \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 Z? prefix_pad $end +$scope struct dest $end +$var reg 4 [? value $end +$upscope $end +$scope struct src $end +$var reg 6 \? \[0] $end +$var reg 6 ]? \[1] $end +$var reg 6 ^? \[2] $end +$upscope $end +$var reg 25 _? imm_low $end +$var reg 1 `? imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 a? output_integer_mode $end +$upscope $end +$var reg 1 b? invert_src0 $end +$var reg 1 c? invert_carry_in $end +$var reg 1 d? invert_carry_out $end +$var reg 1 e? add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 f? prefix_pad $end +$scope struct dest $end +$var reg 4 g? value $end +$upscope $end +$scope struct src $end +$var reg 6 h? \[0] $end +$var reg 6 i? \[1] $end +$var reg 6 j? \[2] $end +$upscope $end +$var reg 25 k? imm_low $end +$var reg 1 l? imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 m? output_integer_mode $end +$upscope $end +$var reg 1 n? invert_src0 $end +$var reg 1 o? invert_carry_in $end +$var reg 1 p? invert_carry_out $end +$var reg 1 q? add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 r? prefix_pad $end +$scope struct dest $end +$var reg 4 s? value $end +$upscope $end +$scope struct src $end +$var reg 6 t? \[0] $end +$var reg 6 u? \[1] $end +$var reg 6 v? \[2] $end +$upscope $end +$var reg 25 w? imm_low $end +$var reg 1 x? imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 y? output_integer_mode $end +$upscope $end +$var reg 4 z? lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 {? \$tag $end +$scope struct HdlSome $end +$var reg 64 |? int_fp $end +$scope struct flags $end +$var reg 1 }? pwr_ca_x86_cf $end +$var reg 1 ~? pwr_ca32_x86_af $end +$var reg 1 !@ pwr_ov_x86_of $end +$var reg 1 "@ pwr_ov32_x86_df $end +$var reg 1 #@ pwr_cr_lt_x86_sf $end +$var reg 1 $@ pwr_cr_gt_x86_pf $end +$var reg 1 %@ pwr_cr_eq_x86_zf $end +$var reg 1 &@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 '@ \$tag $end +$scope struct HdlSome $end +$var reg 64 (@ int_fp $end +$scope struct flags $end +$var reg 1 )@ pwr_ca_x86_cf $end +$var reg 1 *@ pwr_ca32_x86_af $end +$var reg 1 +@ pwr_ov_x86_of $end +$var reg 1 ,@ pwr_ov32_x86_df $end +$var reg 1 -@ pwr_cr_lt_x86_sf $end +$var reg 1 .@ pwr_cr_gt_x86_pf $end +$var reg 1 /@ pwr_cr_eq_x86_zf $end +$var reg 1 0@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 1@ \$tag $end +$scope struct HdlSome $end +$var reg 64 2@ int_fp $end +$scope struct flags $end +$var reg 1 3@ pwr_ca_x86_cf $end +$var reg 1 4@ pwr_ca32_x86_af $end +$var reg 1 5@ pwr_ov_x86_of $end +$var reg 1 6@ pwr_ov32_x86_df $end +$var reg 1 7@ pwr_cr_lt_x86_sf $end +$var reg 1 8@ pwr_cr_gt_x86_pf $end +$var reg 1 9@ pwr_cr_eq_x86_zf $end +$var reg 1 :@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 ;@ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 <@ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 =@ prefix_pad $end +$scope struct dest $end +$var reg 4 >@ value $end +$upscope $end +$scope struct src $end +$var reg 6 ?@ \[0] $end +$var reg 6 @@ \[1] $end +$var reg 6 A@ \[2] $end +$upscope $end +$var reg 25 B@ imm_low $end +$var reg 1 C@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 D@ output_integer_mode $end +$upscope $end +$var reg 1 E@ invert_src0 $end +$var reg 1 F@ invert_carry_in $end +$var reg 1 G@ invert_carry_out $end +$var reg 1 H@ add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 I@ prefix_pad $end +$scope struct dest $end +$var reg 4 J@ value $end +$upscope $end +$scope struct src $end +$var reg 6 K@ \[0] $end +$var reg 6 L@ \[1] $end +$var reg 6 M@ \[2] $end +$upscope $end +$var reg 25 N@ imm_low $end +$var reg 1 O@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 P@ output_integer_mode $end +$upscope $end +$var reg 1 Q@ invert_src0 $end +$var reg 1 R@ invert_carry_in $end +$var reg 1 S@ invert_carry_out $end +$var reg 1 T@ add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 U@ prefix_pad $end +$scope struct dest $end +$var reg 4 V@ value $end +$upscope $end +$scope struct src $end +$var reg 6 W@ \[0] $end +$var reg 6 X@ \[1] $end +$var reg 6 Y@ \[2] $end +$upscope $end +$var reg 25 Z@ imm_low $end +$var reg 1 [@ imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 \@ output_integer_mode $end +$upscope $end +$var reg 4 ]@ lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 ^@ \$tag $end +$scope struct HdlSome $end +$var reg 64 _@ int_fp $end +$scope struct flags $end +$var reg 1 `@ pwr_ca_x86_cf $end +$var reg 1 a@ pwr_ca32_x86_af $end +$var reg 1 b@ pwr_ov_x86_of $end +$var reg 1 c@ pwr_ov32_x86_df $end +$var reg 1 d@ pwr_cr_lt_x86_sf $end +$var reg 1 e@ pwr_cr_gt_x86_pf $end +$var reg 1 f@ pwr_cr_eq_x86_zf $end +$var reg 1 g@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 h@ \$tag $end +$scope struct HdlSome $end +$var reg 64 i@ int_fp $end +$scope struct flags $end +$var reg 1 j@ pwr_ca_x86_cf $end +$var reg 1 k@ pwr_ca32_x86_af $end +$var reg 1 l@ pwr_ov_x86_of $end +$var reg 1 m@ pwr_ov32_x86_df $end +$var reg 1 n@ pwr_cr_lt_x86_sf $end +$var reg 1 o@ pwr_cr_gt_x86_pf $end +$var reg 1 p@ pwr_cr_eq_x86_zf $end +$var reg 1 q@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 r@ \$tag $end +$scope struct HdlSome $end +$var reg 64 s@ int_fp $end +$scope struct flags $end +$var reg 1 t@ pwr_ca_x86_cf $end +$var reg 1 u@ pwr_ca32_x86_af $end +$var reg 1 v@ pwr_ov_x86_of $end +$var reg 1 w@ pwr_ov32_x86_df $end +$var reg 1 x@ pwr_cr_lt_x86_sf $end +$var reg 1 y@ pwr_cr_gt_x86_pf $end +$var reg 1 z@ pwr_cr_eq_x86_zf $end +$var reg 1 {@ pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 |@ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 }@ \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 ~@ prefix_pad $end +$scope struct dest $end +$var reg 4 !A value $end +$upscope $end +$scope struct src $end +$var reg 6 "A \[0] $end +$var reg 6 #A \[1] $end +$var reg 6 $A \[2] $end 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struct alu_common $end +$scope struct common $end +$var string 0 8A prefix_pad $end +$scope struct dest $end +$var reg 4 9A value $end +$upscope $end +$scope struct src $end +$var reg 6 :A \[0] $end +$var reg 6 ;A \[1] $end +$var reg 6 A imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 ?A output_integer_mode $end +$upscope $end +$var reg 4 @A lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 AA \$tag $end +$scope struct HdlSome $end +$var reg 64 BA int_fp $end +$scope struct flags $end +$var reg 1 CA pwr_ca_x86_cf $end +$var reg 1 DA pwr_ca32_x86_af $end +$var reg 1 EA pwr_ov_x86_of $end +$var reg 1 FA pwr_ov32_x86_df $end +$var reg 1 GA pwr_cr_lt_x86_sf $end +$var reg 1 HA pwr_cr_gt_x86_pf $end +$var reg 1 IA pwr_cr_eq_x86_zf $end +$var reg 1 JA pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 KA \$tag $end +$scope struct HdlSome $end +$var reg 64 LA int_fp $end +$scope struct flags $end +$var reg 1 MA pwr_ca_x86_cf $end +$var reg 1 NA pwr_ca32_x86_af $end +$var reg 1 OA pwr_ov_x86_of $end +$var reg 1 PA pwr_ov32_x86_df $end +$var reg 1 QA pwr_cr_lt_x86_sf $end +$var reg 1 RA pwr_cr_gt_x86_pf $end +$var reg 1 SA pwr_cr_eq_x86_zf $end +$var reg 1 TA pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 UA \$tag $end +$scope struct HdlSome $end +$var reg 64 VA int_fp $end +$scope struct flags $end +$var reg 1 WA pwr_ca_x86_cf $end +$var reg 1 XA pwr_ca32_x86_af $end +$var reg 1 YA pwr_ov_x86_of $end +$var reg 1 ZA pwr_ov32_x86_df $end +$var reg 1 [A pwr_cr_lt_x86_sf $end +$var reg 1 \A pwr_cr_gt_x86_pf $end +$var reg 1 ]A pwr_cr_eq_x86_zf $end +$var reg 1 ^A pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct input_index $end +$var string 1 _A \$tag $end +$var wire 3 `A HdlSome $end +$upscope $end +$scope struct or_out $end +$var string 1 aA \$tag $end +$var wire 3 bA HdlSome $end +$upscope $end +$scope struct or_out_2 $end +$var string 1 cA \$tag $end +$var wire 3 dA HdlSome $end +$upscope $end +$scope struct or_out_3 $end +$var string 1 eA \$tag $end +$var wire 3 fA HdlSome $end +$upscope $end +$scope struct or_out_4 $end +$var string 1 gA \$tag $end +$var wire 3 hA HdlSome $end +$upscope $end +$scope struct or_out_5 $end +$var string 1 iA \$tag $end +$var wire 3 jA HdlSome $end +$upscope $end +$scope struct or_out_6 $end +$var string 1 kA \$tag $end +$var wire 3 lA HdlSome $end +$upscope $end +$scope struct or_out_7 $end +$var string 1 mA \$tag $end +$var wire 3 nA HdlSome $end +$upscope $end +$scope struct input_in_flight_op $end +$var string 1 oA \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var string 1 pA \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 qA prefix_pad $end +$scope struct dest $end +$var wire 4 rA value $end +$upscope $end +$scope struct src $end +$var wire 6 sA \[0] $end +$var wire 6 tA \[1] $end +$var wire 6 uA \[2] $end +$upscope $end +$var wire 25 vA imm_low $end +$var wire 1 wA imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 xA output_integer_mode $end +$upscope $end +$var wire 1 yA invert_src0 $end +$var wire 1 zA invert_carry_in $end +$var wire 1 {A invert_carry_out $end +$var wire 1 |A add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 }A prefix_pad $end +$scope struct dest $end +$var wire 4 ~A value $end +$upscope $end +$scope struct src $end +$var wire 6 !B \[0] $end +$var wire 6 "B \[1] $end +$var wire 6 #B \[2] $end +$upscope $end +$var wire 25 $B imm_low $end +$var wire 1 %B imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 &B output_integer_mode $end +$upscope $end +$var wire 1 'B invert_src0 $end +$var wire 1 (B invert_carry_in $end +$var wire 1 )B invert_carry_out $end +$var wire 1 *B add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 +B prefix_pad $end +$scope struct dest $end +$var wire 4 ,B value $end +$upscope $end +$scope struct src $end +$var wire 6 -B \[0] $end +$var wire 6 .B \[1] $end +$var wire 6 /B \[2] $end +$upscope $end +$var wire 25 0B imm_low $end +$var wire 1 1B imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 2B output_integer_mode $end +$upscope $end +$var wire 4 3B lut $end +$upscope $end +$upscope $end +$scope struct src_values $end +$scope struct \[0] $end +$var string 1 4B \$tag $end +$scope struct HdlSome $end +$var wire 64 5B int_fp $end +$scope struct flags $end +$var wire 1 6B pwr_ca_x86_cf $end +$var wire 1 7B pwr_ca32_x86_af $end +$var wire 1 8B pwr_ov_x86_of $end +$var wire 1 9B pwr_ov32_x86_df $end +$var wire 1 :B pwr_cr_lt_x86_sf $end +$var wire 1 ;B pwr_cr_gt_x86_pf $end +$var wire 1 B \$tag $end +$scope struct HdlSome $end +$var wire 64 ?B int_fp $end +$scope struct flags $end +$var wire 1 @B pwr_ca_x86_cf $end +$var wire 1 AB pwr_ca32_x86_af $end +$var wire 1 BB pwr_ov_x86_of $end +$var wire 1 CB pwr_ov32_x86_df $end +$var wire 1 DB pwr_cr_lt_x86_sf $end +$var wire 1 EB pwr_cr_gt_x86_pf $end +$var wire 1 FB pwr_cr_eq_x86_zf $end +$var wire 1 GB pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 HB \$tag $end +$scope struct HdlSome $end +$var wire 64 IB int_fp $end +$scope struct flags $end +$var wire 1 JB pwr_ca_x86_cf $end +$var wire 1 KB pwr_ca32_x86_af $end +$var wire 1 LB pwr_ov_x86_of $end +$var wire 1 MB pwr_ov32_x86_df $end +$var wire 1 NB pwr_cr_lt_x86_sf $end +$var wire 1 OB pwr_cr_gt_x86_pf $end +$var wire 1 PB pwr_cr_eq_x86_zf $end +$var wire 1 QB pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end 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+$var wire 6 cB \[1] $end +$var wire 6 dB \[2] $end +$upscope $end +$var wire 25 eB imm_low $end +$var wire 1 fB imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 gB output_integer_mode $end +$upscope $end +$var wire 1 hB invert_src0 $end +$var wire 1 iB invert_carry_in $end +$var wire 1 jB invert_carry_out $end +$var wire 1 kB add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 lB prefix_pad $end +$scope struct dest $end +$var wire 4 mB value $end +$upscope $end +$scope struct src $end +$var wire 6 nB \[0] $end +$var wire 6 oB \[1] $end +$var wire 6 pB \[2] $end +$upscope $end +$var wire 25 qB imm_low $end +$var wire 1 rB imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 sB output_integer_mode $end +$upscope $end +$var wire 4 tB lut $end +$upscope $end +$upscope $end +$upscope $end +$scope struct input_in_flight_op_src_values $end +$scope struct \[0] $end +$var string 1 uB \$tag $end +$scope struct HdlSome $end +$var wire 64 vB int_fp $end +$scope struct flags $end +$var wire 1 wB pwr_ca_x86_cf $end +$var wire 1 xB pwr_ca32_x86_af $end +$var wire 1 yB pwr_ov_x86_of $end +$var wire 1 zB pwr_ov32_x86_df $end +$var wire 1 {B pwr_cr_lt_x86_sf $end +$var wire 1 |B pwr_cr_gt_x86_pf $end +$var wire 1 }B pwr_cr_eq_x86_zf $end +$var wire 1 ~B pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 !C \$tag $end +$scope struct HdlSome $end +$var wire 64 "C int_fp $end +$scope struct flags $end +$var wire 1 #C pwr_ca_x86_cf $end +$var wire 1 $C pwr_ca32_x86_af $end +$var wire 1 %C pwr_ov_x86_of $end +$var wire 1 &C pwr_ov32_x86_df $end +$var wire 1 'C pwr_cr_lt_x86_sf $end +$var wire 1 (C pwr_cr_gt_x86_pf $end +$var wire 1 )C pwr_cr_eq_x86_zf $end +$var wire 1 *C pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 +C \$tag $end +$scope struct HdlSome $end +$var wire 64 ,C int_fp $end +$scope struct flags $end +$var wire 1 -C pwr_ca_x86_cf $end +$var wire 1 .C pwr_ca32_x86_af $end +$var wire 1 /C pwr_ov_x86_of $end +$var wire 1 0C pwr_ov32_x86_df $end +$var wire 1 1C pwr_cr_lt_x86_sf $end +$var wire 1 2C pwr_cr_gt_x86_pf $end +$var wire 1 3C pwr_cr_eq_x86_zf $end +$var wire 1 4C pwr_so $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 5C \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 6C value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg $end +$var wire 4 7C value $end +$upscope $end +$scope struct firing_data_3 $end +$var string 1 8C \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 9C value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_2 $end +$var wire 4 :C value $end +$upscope $end +$scope struct firing_data_4 $end +$var string 1 ;C \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 C \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 ?C value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_4 $end +$var wire 4 @C value $end +$upscope $end +$scope struct firing_data_6 $end +$var string 1 AC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 BC value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_5 $end +$var wire 4 CC value $end +$upscope $end +$scope struct firing_data_7 $end +$var string 1 DC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 EC value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_6 $end +$var wire 4 FC value $end +$upscope $end +$scope struct firing_data_8 $end +$var string 1 GC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 HC value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_7 $end +$var wire 4 IC value $end +$upscope $end +$scope struct firing_data_9 $end +$var string 1 JC \$tag $end +$scope struct HdlSome $end +$scope struct which $end +$var wire 4 KC value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct dest_reg_8 $end +$var wire 4 LC value $end +$upscope $end +$upscope $end +$upscope $end +$scope struct unit_1_free_regs_tracker $end +$scope struct cd $end +$var wire 1 FF clk $end +$var wire 1 GF rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 HF \$tag $end +$var wire 4 IF HdlSome $end +$upscope $end +$var wire 1 JF ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 KF \$tag $end +$var wire 4 LF HdlSome $end +$upscope $end +$var wire 1 MF ready $end +$upscope $end +$upscope $end +$upscope $end +$scope module unit_free_regs_tracker_2 $end +$scope struct cd $end +$var wire 1 [E clk $end +$var wire 1 \E rst $end +$upscope $end +$scope struct free_in $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 ]E \$tag $end +$var wire 4 ^E HdlSome $end +$upscope $end +$var wire 1 _E ready $end +$upscope $end +$upscope $end +$scope struct alloc_out $end +$scope struct \[0] $end +$scope struct data $end +$var string 1 `E \$tag $end +$var wire 4 aE HdlSome $end +$upscope $end +$var wire 1 bE ready $end +$upscope $end +$upscope $end +$scope struct allocated_reg $end +$var reg 1 cE \[0] $end +$var reg 1 dE \[1] $end +$var reg 1 eE \[2] $end +$var reg 1 fE \[3] $end +$var reg 1 gE \[4] $end +$var reg 1 hE \[5] $end +$var reg 1 iE \[6] $end +$var reg 1 jE \[7] $end +$var reg 1 kE \[8] $end +$var reg 1 lE \[9] $end +$var reg 1 mE \[10] $end +$var reg 1 nE \[11] $end +$var reg 1 oE \[12] $end +$var reg 1 pE \[13] $end +$var reg 1 qE \[14] $end +$var reg 1 rE \[15] $end +$upscope $end +$scope struct firing_data $end +$var string 1 sE \$tag $end +$var wire 4 tE HdlSome $end +$upscope $end +$var wire 1 uE reduced_count_0_2 $end +$var wire 1 vE reduced_count_overflowed_0_2 $end +$scope struct reduced_alloc_nums_0_2 $end +$var wire 1 wE \[0] $end +$upscope $end +$var wire 1 xE reduced_count_2_4 $end +$var wire 1 yE reduced_count_overflowed_2_4 $end +$scope struct reduced_alloc_nums_2_4 $end +$var wire 1 zE \[0] $end +$upscope $end +$var wire 1 {E reduced_count_0_4 $end +$var wire 1 |E reduced_count_overflowed_0_4 $end +$scope struct reduced_alloc_nums_0_4 $end +$var wire 2 }E \[0] $end +$upscope $end +$var wire 1 ~E reduced_count_4_6 $end +$var wire 1 !F reduced_count_overflowed_4_6 $end +$scope struct reduced_alloc_nums_4_6 $end +$var wire 1 "F \[0] $end +$upscope $end +$var wire 1 #F reduced_count_6_8 $end +$var wire 1 $F reduced_count_overflowed_6_8 $end +$scope struct reduced_alloc_nums_6_8 $end +$var wire 1 %F \[0] $end +$upscope $end +$var wire 1 &F reduced_count_4_8 $end +$var wire 1 'F reduced_count_overflowed_4_8 $end +$scope struct reduced_alloc_nums_4_8 $end +$var wire 2 (F \[0] $end +$upscope $end +$var wire 1 )F reduced_count_0_8 $end +$var wire 1 *F reduced_count_overflowed_0_8 $end +$scope struct reduced_alloc_nums_0_8 $end +$var wire 3 +F \[0] $end +$upscope $end +$var wire 1 ,F reduced_count_8_10 $end +$var wire 1 -F reduced_count_overflowed_8_10 $end +$scope struct reduced_alloc_nums_8_10 $end +$var wire 1 .F \[0] $end +$upscope $end +$var wire 1 /F reduced_count_10_12 $end +$var wire 1 0F reduced_count_overflowed_10_12 $end +$scope struct reduced_alloc_nums_10_12 $end +$var wire 1 1F \[0] $end +$upscope $end +$var wire 1 2F reduced_count_8_12 $end +$var wire 1 3F reduced_count_overflowed_8_12 $end +$scope struct reduced_alloc_nums_8_12 $end +$var wire 2 4F \[0] $end +$upscope $end +$var wire 1 5F reduced_count_12_14 $end +$var wire 1 6F reduced_count_overflowed_12_14 $end +$scope struct reduced_alloc_nums_12_14 $end +$var wire 1 7F \[0] $end +$upscope $end +$var wire 1 8F reduced_count_14_16 $end +$var wire 1 9F reduced_count_overflowed_14_16 $end +$scope struct reduced_alloc_nums_14_16 $end +$var wire 1 :F \[0] $end +$upscope $end +$var wire 1 ;F reduced_count_12_16 $end +$var wire 1 F reduced_count_8_16 $end +$var wire 1 ?F reduced_count_overflowed_8_16 $end +$scope struct reduced_alloc_nums_8_16 $end +$var wire 3 @F \[0] $end +$upscope $end +$var wire 1 AF reduced_count_0_16 $end +$var wire 1 BF reduced_count_overflowed_0_16 $end +$scope struct reduced_alloc_nums_0_16 $end +$var wire 4 CF \[0] $end +$upscope $end +$scope struct firing_data_2 $end +$var string 1 DF \$tag $end +$var wire 4 EF HdlSome $end +$upscope $end +$upscope $end +$scope struct and_then_out_3 $end +$var string 1 NF \$tag $end +$scope struct HdlSome $end +$var string 1 OF \$tag $end +$scope struct AddSub $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 PF prefix_pad $end +$scope struct dest $end +$var wire 4 QF value $end +$upscope $end +$scope struct src $end +$var wire 6 RF \[0] $end +$var wire 6 SF \[1] $end +$var wire 6 TF \[2] $end +$upscope $end +$var wire 25 UF imm_low $end +$var wire 1 VF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 WF output_integer_mode $end +$upscope $end +$var wire 1 XF invert_src0 $end +$var wire 1 YF invert_carry_in $end +$var wire 1 ZF invert_carry_out $end +$var wire 1 [F add_pc $end +$upscope $end +$scope struct AddSubI $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 \F prefix_pad $end +$scope struct dest $end +$var wire 4 ]F value $end +$upscope $end +$scope struct src $end +$var wire 6 ^F \[0] $end +$var wire 6 _F \[1] $end +$var wire 6 `F \[2] $end +$upscope $end +$var wire 25 aF imm_low $end +$var wire 1 bF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 cF output_integer_mode $end +$upscope $end +$var wire 1 dF invert_src0 $end +$var wire 1 eF invert_carry_in $end +$var wire 1 fF invert_carry_out $end +$var wire 1 gF add_pc $end +$upscope $end +$scope struct Logical $end +$scope struct alu_common $end +$scope struct common $end +$var string 0 hF prefix_pad $end +$scope struct dest $end +$var wire 4 iF value $end +$upscope $end +$scope struct src $end +$var wire 6 jF \[0] $end +$var wire 6 kF \[1] $end +$var wire 6 lF \[2] $end +$upscope $end +$var wire 25 mF imm_low $end +$var wire 1 nF imm_sign $end +$scope struct _phantom $end +$upscope $end +$upscope $end +$var string 1 oF output_integer_mode $end +$upscope $end +$var wire 4 pF lut $end $upscope $end $upscope $end $upscope $end $scope struct alu_branch_mop_3 $end -$var string 1 q0 \$tag $end +$var string 1 qF \$tag $end $scope struct HdlSome $end -$var string 1 r0 \$tag $end +$var string 1 rF \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 s0 prefix_pad $end +$var string 0 sF prefix_pad $end $scope struct dest $end -$var wire 4 t0 value $end +$var wire 4 tF value $end $upscope $end $scope struct src $end -$var wire 6 u0 \[0] $end -$var wire 6 v0 \[1] $end -$var wire 6 w0 \[2] $end +$var wire 6 uF \[0] $end +$var wire 6 vF \[1] $end +$var wire 6 wF \[2] $end $upscope $end -$var wire 25 x0 imm_low $end -$var wire 1 y0 imm_sign $end +$var wire 25 xF imm_low $end +$var wire 1 yF imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 z0 output_integer_mode $end +$var string 1 zF output_integer_mode $end $upscope $end -$var wire 1 {0 invert_src0 $end -$var wire 1 |0 invert_carry_in $end -$var wire 1 }0 invert_carry_out $end -$var wire 1 ~0 add_pc $end +$var wire 1 {F invert_src0 $end +$var wire 1 |F invert_carry_in $end +$var wire 1 }F invert_carry_out $end +$var wire 1 ~F add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 !1 prefix_pad $end +$var string 0 !G prefix_pad $end $scope struct dest $end -$var wire 4 "1 value $end +$var wire 4 "G value $end $upscope $end $scope struct src $end -$var wire 6 #1 \[0] $end -$var wire 6 $1 \[1] $end -$var wire 6 %1 \[2] $end +$var wire 6 #G \[0] $end +$var wire 6 $G \[1] $end +$var wire 6 %G \[2] $end $upscope $end -$var wire 25 &1 imm_low $end -$var wire 1 '1 imm_sign $end +$var wire 25 &G imm_low $end +$var wire 1 'G imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 (1 output_integer_mode $end +$var string 1 (G output_integer_mode $end $upscope $end -$var wire 1 )1 invert_src0 $end -$var wire 1 *1 invert_carry_in $end -$var wire 1 +1 invert_carry_out $end -$var wire 1 ,1 add_pc $end +$var wire 1 )G invert_src0 $end +$var wire 1 *G invert_carry_in $end +$var wire 1 +G invert_carry_out $end +$var wire 1 ,G add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 -1 prefix_pad $end +$var string 0 -G prefix_pad $end $scope struct dest $end -$var wire 4 .1 value $end +$var wire 4 .G value $end $upscope $end $scope struct src $end -$var wire 6 /1 \[0] $end -$var wire 6 01 \[1] $end -$var wire 6 11 \[2] $end +$var wire 6 /G \[0] $end +$var wire 6 0G \[1] $end +$var wire 6 1G \[2] $end $upscope $end -$var wire 25 21 imm_low $end -$var wire 1 31 imm_sign $end +$var wire 25 2G imm_low $end +$var wire 1 3G imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 41 output_integer_mode $end +$var string 1 4G output_integer_mode $end $upscope $end -$var wire 4 51 lut $end +$var wire 4 5G lut $end $upscope $end $upscope $end $upscope $end $scope struct and_then_out_4 $end -$var string 1 61 \$tag $end +$var string 1 6G \$tag $end $scope struct HdlSome $end -$var string 1 71 \$tag $end +$var string 1 7G \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 81 prefix_pad $end +$var string 0 8G prefix_pad $end $scope struct dest $end -$var wire 4 91 value $end +$var wire 4 9G value $end $upscope $end $scope struct src $end -$var wire 6 :1 \[0] $end -$var wire 6 ;1 \[1] $end -$var wire 6 <1 \[2] $end +$var wire 6 :G \[0] $end +$var wire 6 ;G \[1] $end +$var wire 6 1 imm_sign $end +$var wire 25 =G imm_low $end +$var wire 1 >G imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 ?1 output_integer_mode $end +$var string 1 ?G output_integer_mode $end $upscope $end -$var wire 1 @1 invert_src0 $end -$var wire 1 A1 invert_carry_in $end -$var wire 1 B1 invert_carry_out $end -$var wire 1 C1 add_pc $end +$var wire 1 @G invert_src0 $end +$var wire 1 AG invert_carry_in $end +$var wire 1 BG invert_carry_out $end +$var wire 1 CG add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 D1 prefix_pad $end +$var string 0 DG prefix_pad $end $scope struct dest $end -$var wire 4 E1 value $end +$var wire 4 EG value $end $upscope $end $scope struct src $end -$var wire 6 F1 \[0] $end -$var wire 6 G1 \[1] $end -$var wire 6 H1 \[2] $end +$var wire 6 FG \[0] $end +$var wire 6 GG \[1] $end +$var wire 6 HG \[2] $end $upscope $end -$var wire 25 I1 imm_low $end -$var wire 1 J1 imm_sign $end +$var wire 25 IG imm_low $end +$var wire 1 JG imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 K1 output_integer_mode $end +$var string 1 KG output_integer_mode $end $upscope $end -$var wire 1 L1 invert_src0 $end -$var wire 1 M1 invert_carry_in $end -$var wire 1 N1 invert_carry_out $end -$var wire 1 O1 add_pc $end +$var wire 1 LG invert_src0 $end +$var wire 1 MG invert_carry_in $end +$var wire 1 NG invert_carry_out $end +$var wire 1 OG add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 P1 prefix_pad $end +$var string 0 PG prefix_pad $end $scope struct dest $end -$var wire 4 Q1 value $end +$var wire 4 QG value $end $upscope $end $scope struct src $end -$var wire 6 R1 \[0] $end -$var wire 6 S1 \[1] $end -$var wire 6 T1 \[2] $end +$var wire 6 RG \[0] $end +$var wire 6 SG \[1] $end +$var wire 6 TG \[2] $end $upscope $end -$var wire 25 U1 imm_low $end -$var wire 1 V1 imm_sign $end +$var wire 25 UG imm_low $end +$var wire 1 VG imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 W1 output_integer_mode $end +$var string 1 WG output_integer_mode $end $upscope $end -$var wire 4 X1 lut $end +$var wire 4 XG lut $end $upscope $end $upscope $end $upscope $end $scope struct alu_branch_mop_4 $end -$var string 1 Y1 \$tag $end +$var string 1 YG \$tag $end $scope struct HdlSome $end -$var string 1 Z1 \$tag $end +$var string 1 ZG \$tag $end $scope struct AddSub $end $scope struct alu_common $end $scope struct common $end -$var string 0 [1 prefix_pad $end +$var string 0 [G prefix_pad $end $scope struct dest $end -$var wire 4 \1 value $end +$var wire 4 \G value $end $upscope $end $scope struct src $end -$var wire 6 ]1 \[0] $end -$var wire 6 ^1 \[1] $end -$var wire 6 _1 \[2] $end +$var wire 6 ]G \[0] $end +$var wire 6 ^G \[1] $end +$var wire 6 _G \[2] $end $upscope $end -$var wire 25 `1 imm_low $end -$var wire 1 a1 imm_sign $end +$var wire 25 `G imm_low $end +$var wire 1 aG imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 b1 output_integer_mode $end +$var string 1 bG output_integer_mode $end $upscope $end -$var wire 1 c1 invert_src0 $end -$var wire 1 d1 invert_carry_in $end -$var wire 1 e1 invert_carry_out $end -$var wire 1 f1 add_pc $end +$var wire 1 cG invert_src0 $end +$var wire 1 dG invert_carry_in $end +$var wire 1 eG invert_carry_out $end +$var wire 1 fG add_pc $end $upscope $end $scope struct AddSubI $end $scope struct alu_common $end $scope struct common $end -$var string 0 g1 prefix_pad $end +$var string 0 gG prefix_pad $end $scope struct dest $end -$var wire 4 h1 value $end +$var wire 4 hG value $end $upscope $end $scope struct src $end -$var wire 6 i1 \[0] $end -$var wire 6 j1 \[1] $end -$var wire 6 k1 \[2] $end +$var wire 6 iG \[0] $end +$var wire 6 jG \[1] $end +$var wire 6 kG \[2] $end $upscope $end -$var wire 25 l1 imm_low $end -$var wire 1 m1 imm_sign $end +$var wire 25 lG imm_low $end +$var wire 1 mG imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 n1 output_integer_mode $end +$var string 1 nG output_integer_mode $end $upscope $end -$var wire 1 o1 invert_src0 $end -$var wire 1 p1 invert_carry_in $end -$var wire 1 q1 invert_carry_out $end -$var wire 1 r1 add_pc $end +$var wire 1 oG invert_src0 $end +$var wire 1 pG invert_carry_in $end +$var wire 1 qG invert_carry_out $end +$var wire 1 rG add_pc $end $upscope $end $scope struct Logical $end $scope struct alu_common $end $scope struct common $end -$var string 0 s1 prefix_pad $end +$var string 0 sG prefix_pad $end $scope struct dest $end -$var wire 4 t1 value $end +$var wire 4 tG value $end $upscope $end $scope struct src $end -$var wire 6 u1 \[0] $end -$var wire 6 v1 \[1] $end -$var wire 6 w1 \[2] $end +$var wire 6 uG \[0] $end +$var wire 6 vG \[1] $end +$var wire 6 wG \[2] $end $upscope $end -$var wire 25 x1 imm_low $end -$var wire 1 y1 imm_sign $end +$var wire 25 xG imm_low $end +$var wire 1 yG imm_sign $end $scope struct _phantom $end $upscope $end $upscope $end -$var string 1 z1 output_integer_mode $end +$var string 1 zG output_integer_mode $end $upscope $end -$var wire 4 {1 lut $end +$var wire 4 {G lut $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b0 |1 -b0 _4 -b0 }1 -b0 `4 -b0 ~1 -b0 a4 -b0 !2 -b0 b4 -b0 "2 -b0 c4 -b0 #2 -b0 d4 -b0 $2 -b0 e4 -b0 %2 -b0 f4 -b0 &2 -b0 g4 -b0 '2 -b0 h4 -b0 (2 -b0 i4 -b0 )2 -b0 j4 -b0 *2 -b0 k4 -b0 +2 -b0 l4 -b0 ,2 -b0 m4 -b0 -2 -b0 n4 -b0 .2 -b0 o4 -b0 /2 -b0 p4 -b0 02 -b0 q4 -b0 12 -b0 r4 -b0 22 -b0 s4 -b0 32 -b0 t4 -b0 42 -b0 u4 -b0 52 -b0 v4 -b0 62 -b0 w4 -b0 72 -b0 x4 -b0 82 -b0 y4 -b0 92 -b0 z4 -b0 :2 -b0 {4 -b0 ;2 -b0 |4 -b0 <2 -b0 }4 -b0 =2 -b0 ~4 -b0 >2 -b0 !5 -b0 ?2 -b0 "5 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+b0 1L +b0 OI +b0 2L +b0 PI +b0 3L +b0 QI +b0 4L +b0 RI +b0 5L +b0 SI +b0 6L +b0 TI +b0 7L +b0 UI +b0 8L +b0 VI +b0 9L +b0 WI +b0 :L +b0 XI +b0 ;L +b0 YI +b0 L +b0 \I +b0 ?L +b0 ]I +b0 @L +b0 ^I +b0 AL +b0 _I +b0 BL +b0 `I +b0 CL +b0 aI +b0 DL +b0 bI +b0 EL +b0 cI +b0 FL +b0 dI +b0 GL +b0 eI +b0 HL +b0 fI +b0 IL +b0 gI +b0 JL +b0 hI +b0 KL +b0 iI +b0 LL +b0 jI +b0 ML +b0 kI +b0 NL +b0 lI +b0 OL +b0 mI +b0 PL +b0 nI +b0 QL +b0 oI +b0 RL +b0 pI +b0 SL +b0 qI +b0 TL +b0 rI +b0 UL +b0 sI +b0 VL +b0 tI +b0 WL +b0 uI +b0 XL +b0 vI +b0 YL +b0 wI +b0 ZL +b0 xI +b0 [L +b0 yI +b0 \L +b0 zI +b0 ]L +b0 {I +b0 ^L +b0 |I +b0 _L +b0 }I +b0 `L +b0 ~I +b0 aL +b0 !J +b0 bL +b0 "J +b0 cL +b0 #J +b0 dL +b0 $J +b0 eL +b0 %J +b0 fL +b0 &J +b0 gL +b0 'J +b0 hL +b0 (J +b0 iL +b0 )J +b0 jL +b0 *J +b0 kL +b0 +J +b0 lL +b0 ,J +b0 mL +b0 -J +b0 nL +b0 .J +b0 oL +b0 /J +b0 pL +b0 0J +b0 qL +b0 1J +b0 rL +b0 2J +b0 sL +b0 3J +b0 tL +b0 4J +b0 uL +b0 5J +b0 vL +b0 6J +b0 wL +b0 7J +b0 xL +b0 8J +b0 yL +b0 9J +b0 zL +b0 :J +b0 {L +b0 ;J +b0 |L +b0 J +b0 !M +b0 ?J +b0 "M +b0 @J +b0 #M +b0 AJ +b0 $M +b0 BJ +b0 %M +b0 CJ +b0 &M +b0 DJ +b0 'M +b0 EJ +b0 (M +b0 FJ +b0 )M +b0 GJ +b0 *M +b0 HJ +b0 +M +b0 IJ +b0 ,M +b0 JJ +b0 -M +b0 KJ +b0 .M +b0 LJ +b0 /M +b0 MJ +b0 0M +b0 NJ +b0 1M +b0 OJ +b0 2M +b0 PJ +b0 3M +b0 QJ +b0 4M +b0 RJ +b0 5M +b0 SJ +b0 6M +b0 TJ +b0 7M +b0 UJ +b0 8M +b0 VJ +b0 9M +b0 WJ +b0 :M +b0 XJ +b0 ;M +b0 YJ +b0 M +b0 \J +b0 ?M +b0 ]J +b0 @M +b0 ^J +b0 AM +b0 BM +b0 DM +b0 CM +b0 EM 0! 1" sHdlSome\x20(1) # @@ -7529,25 +11797,25 @@ b1000000000100 w" sHdlNone\x20(0) y" sTrap\x20(0) z" 1{" -b1 |" -1}" +b0 |" +0}" 0~" b0 !# b0 "# -b10 ## -1$# +b0 ## +0$# 0%# b0 &# b0 '# -b11 (# -1)# +b0 (# +0)# 0*# b0 +# b0 ,# b0 -# -1.# +0.# 0/# -b1 0# +b0 0# b0 1# 12# 13# @@ -7558,13 +11826,13 @@ b0 7# b0 8# 19# 1:# -b10 ;# -1<# +b0 ;# +0<# 0=# b0 ># b0 ?# -b11 @# -1A# +b0 @# +0A# 0B# b0 C# b0 D# @@ -7573,10 +11841,10 @@ b0 E# 0G# b0 H# b0 I# -b1 J# -1K# +b0 J# +0K# 0L# -b10 M# +b0 M# b0 N# 1O# 1P# @@ -7617,9 +11885,9 @@ b0 r# 1s# 1t# 0u# -1v# +0v# 0w# -b1 x# +b0 x# b0 y# 1z# 1{# @@ -7666,22 +11934,22 @@ b0 E$ b0 F$ 1G$ 1H$ -1I$ -1J$ +0I$ +0J$ 0K$ -b10 L$ +b0 L$ b0 M$ 1N$ 1O$ -1P$ -1Q$ +0P$ +0Q$ 0R$ -1S$ -sHdlSome\x20(1) T$ +0S$ +sHdlNone\x20(0) T$ b0 U$ -sHdlSome\x20(1) V$ -b1 W$ -sHdlSome\x20(1) X$ +sHdlNone\x20(0) V$ +b0 W$ +sHdlNone\x20(0) X$ sAluBranch\x20(0) Y$ sAddSub\x20(0) Z$ s0 [$ @@ -7689,48 +11957,48 @@ b0 \$ b0 ]$ b0 ^$ b0 _$ -b1001000110100 `$ +b0 `$ 0a$ sFull64\x20(0) b$ -1c$ -1d$ -1e$ -1f$ +0c$ +0d$ +0e$ +0f$ s0 g$ b0 h$ b0 i$ b0 j$ b0 k$ -b1001000110100 l$ +b0 l$ 0m$ sFull64\x20(0) n$ -1o$ -1p$ -1q$ -1r$ +0o$ +0p$ +0q$ +0r$ s0 s$ b0 t$ b0 u$ b0 v$ b0 w$ -b1001000110100 x$ +b0 x$ 0y$ sFull64\x20(0) z$ -b1111 {$ +b0 {$ sReadL2Reg\x20(0) |$ 0}$ b0 ~$ b0 !% b0 "% b0 #% -b1001000110100 $% +b0 $% 0%% 0&% b0 '% b0 (% b0 )% b0 *% -b1001000110100 +% +b0 +% 0,% sLoad\x20(0) -% 0.% @@ -7738,18 +12006,18 @@ b0 /% b0 0% b0 1% b0 2% -b1001000110100 3% +b0 3% 04% 05% b0 6% b0 7% b0 8% b0 9% -b1001000110100 :% +b0 :% 0;% -sHdlSome\x20(1) <% +sHdlNone\x20(0) <% sAluBranch\x20(0) =% -sLogical\x20(2) >% +sAddSub\x20(0) >% s0 ?% b0 @% b0 A% @@ -7759,8 +12027,8 @@ b0 D% 0E% sFull64\x20(0) F% 0G% -1H% -1I% +0H% +0I% 0J% s0 K% b0 L% @@ -7771,8 +12039,8 @@ b0 P% 0Q% sFull64\x20(0) R% 0S% -1T% -1U% +0T% +0U% 0V% s0 W% b0 X% @@ -7782,16 +12050,16 @@ b0 [% b0 \% 0]% sFull64\x20(0) ^% -b110 _% +b0 _% sReadL2Reg\x20(0) `% -1a% +0a% b0 b% b0 c% b0 d% b0 e% b0 f% 0g% -1h% +0h% b0 i% b0 j% b0 k% @@ -7799,39 +12067,39 @@ b0 l% b0 m% 0n% sLoad\x20(0) o% -1p% +0p% b0 q% b0 r% b0 s% b0 t% b0 u% 0v% -1w% +0w% b0 x% b0 y% b0 z% b0 {% b0 |% 0}% -sHdlSome\x20(1) ~% -b1 !& +sHdlNone\x20(0) ~% +b0 !& b0 "& -sHdlSome\x20(1) #& -b10 $& +sHdlNone\x20(0) #& +b0 $& b0 %& -b10 && +b0 && b0 '& b0 (& -b11 )& +b0 )& b0 *& b0 +& -b100 ,& +b0 ,& b0 -& b0 .& b0 /& -10& +00& 01& -b1 2& +b0 2& b0 3& 14& 15& @@ -7857,9 +12125,9 @@ b0 H& 1I& 1J& 0K& -1L& +0L& 0M& -b1 N& +b0 N& b0 O& 1P& 1Q& @@ -8020,15 +12288,15 @@ b1001000110100 /( 00( b11111110 1( b0 2( -sHdlSome\x20(1) 3( +sHdlNone\x20(0) 3( b0 4( b0 5( -sHdlSome\x20(1) 6( -b1 7( +sHdlNone\x20(0) 6( +b0 7( b1 8( -sHdlSome\x20(1) 9( +sHdlNone\x20(0) 9( b0 :( -b11 ;( +b0 ;( b0 <( b0 =( b1 >( @@ -8067,7 +12335,7 @@ sHdlSome\x20(1) ^( sHdlNone\x20(0) _( b11111110 `( b0 a( -b100 b( +b0 b( b0 c( b0 d( b1 e( @@ -8145,10 +12413,10 @@ sHdlSome\x20(1) N) sHdlNone\x20(0) O) b11111110 P) b0 Q) -b1 R) -1S) +b0 R) +0S) 0T) -b10 U) +b0 U) b0 V) 1W) 1X) @@ -8180,10 +12448,10 @@ b0 q) b0 r) 1s) 1t) -1u) -1v) +0u) +0v) 0w) -b10 x) +b0 x) b0 y) 1z) 1{) @@ -8340,103 +12608,103 @@ b11111111 U+ sHdlNone\x20(0) V+ b0 W+ b0 X+ -sHdlSome\x20(1) Y+ -b1 Z+ +sHdlNone\x20(0) Y+ +b0 Z+ b1 [+ -sHdlSome\x20(1) \+ -b1 ]+ +sHdlNone\x20(0) \+ +b0 ]+ 0^+ 1_+ -sHdlSome\x20(1) `+ +sHdlNone\x20(0) `+ sAddSub\x20(0) a+ s0 b+ b0 c+ b0 d+ b0 e+ b0 f+ -b1001000110100 g+ +b0 g+ 0h+ sFull64\x20(0) i+ -1j+ -1k+ -1l+ -1m+ +0j+ +0k+ +0l+ +0m+ s0 n+ b0 o+ b0 p+ b0 q+ b0 r+ -b1001000110100 s+ +b0 s+ 0t+ sFull64\x20(0) u+ -1v+ -1w+ -1x+ -1y+ +0v+ +0w+ +0x+ +0y+ s0 z+ b0 {+ b0 |+ b0 }+ b0 ~+ -b1001000110100 !, +b0 !, 0", sFull64\x20(0) #, -b1111 $, -1%, -0&, -1', -sHdlSome\x20(1) (, -sAddSub\x20(0) ), -s0 *, -b0 +, -b0 ,, -b0 -, -b0 ., -b1001000110100 /, +b0 $, +0%, +sHdlNone\x20(0) &, +b0 ', +b0 (, +0), +0*, +0+, +0,, +0-, +0., +0/, 00, -sFull64\x20(0) 1, -12, -13, -14, -15, -s0 6, -b0 7, -b0 8, -b0 9, -b0 :, -b1001000110100 ;, -0<, -sFull64\x20(0) =, +sHdlNone\x20(0) 1, +b0 2, +b0 3, +04, +05, +06, +07, +08, +09, +0:, +0;, +sHdlNone\x20(0) <, +b0 =, 1>, -1?, -1@, -1A, -s0 B, -b0 C, -b0 D, -b0 E, -b0 F, -b1001000110100 G, +sHdlNone\x20(0) ?, +b0 @, +sCompleted\x20(0) A, +b0 B, +0C, +0D, +0E, +0F, +0G, 0H, -sFull64\x20(0) I, -b1111 J, -1K, +0I, +0J, +0K, 0L, 1M, sHdlNone\x20(0) N, b0 O, -1P, -sHdlSome\x20(1) Q, -b0 R, -1S, +b0 P, +0Q, +0R, +0S, 0T, 0U, 0V, 0W, 0X, -0Y, -0Z, -0[, +sHdlNone\x20(0) Y, +b0 Z, +b0 [, 0\, 0], 0^, @@ -8446,290 +12714,290 @@ b0 R, 0b, 0c, sHdlNone\x20(0) d, -b0 e, -0f, -1g, -0h, -0i, -1j, -0k, +sAddSub\x20(0) e, +s0 f, +b0 g, +b0 h, +b0 i, +b0 j, +b0 k, 0l, -1m, -b0 n, +sFull64\x20(0) m, +0n, 0o, -1p, +0p, 0q, -0r, -1s, -0t, -0u, -1v, +s0 r, +b0 s, +b0 t, +b0 u, +b0 v, b0 w, 0x, -1y, -b0 z, +sFull64\x20(0) y, +0z, 0{, -1|, +0|, 0}, -0~, -1!- -0"- -0#- -1$- +s0 ~, +b0 !- +b0 "- +b0 #- +b0 $- b0 %- 0&- -1'- -0(- +sFull64\x20(0) '- +b0 (- 0)- -1*- -0+- -0,- -1-- -b0 .- -0/- -10- +sHdlNone\x20(0) *- +b0 +- +1,- +sHdlNone\x20(0) -- +sAddSub\x20(0) .- +s0 /- +b0 0- b0 1- -02- -13- +b0 2- +b0 3- b0 4- -sHdlSome\x20(1) 5- -b0 6- +05- +sFull64\x20(0) 6- 07- -18- -sHdlNone\x20(0) 9- -b0 :- -1;- -sHdlSome\x20(1) <- +08- +09- +0:- +s0 ;- +b0 <- b0 =- -1>- -sHdlSome\x20(1) ?- -sAddSub\x20(0) @- -s0 A- -b0 B- -b0 C- -b0 D- -b0 E- -b1001000110100 F- -0G- -sFull64\x20(0) H- -1I- -1J- -1K- -1L- -s0 M- -b0 N- +b0 >- +b0 ?- +b0 @- +0A- +sFull64\x20(0) B- +0C- +0D- +0E- +0F- +s0 G- +b0 H- +b0 I- +b0 J- +b0 K- +b0 L- +0M- +sFull64\x20(0) N- b0 O- b0 P- -b0 Q- -b1001000110100 R- +0Q- +0R- 0S- -sFull64\x20(0) T- -1U- -1V- -1W- -1X- -s0 Y- -b0 Z- -b0 [- -b0 \- -b0 ]- -b1001000110100 ^- +0T- +0U- +0V- +0W- +0X- +b0 Y- +0Z- +0[- +0\- +0]- +0^- 0_- -sFull64\x20(0) `- -b1111 a- -sHdlSome\x20(1) b- -sAddSub\x20(0) c- -s0 d- -b0 e- -b0 f- -b0 g- -b0 h- -b1001000110100 i- +0`- +0a- +b0 b- +0c- +0d- +0e- +0f- +0g- +0h- +0i- 0j- -sFull64\x20(0) k- -1l- -1m- -1n- -1o- -s0 p- +1k- +sHdlNone\x20(0) l- +b0 m- +sHdlNone\x20(0) n- +b0 o- +sHdlNone\x20(0) p- b0 q- -b0 r- +sHdlNone\x20(0) r- b0 s- -b0 t- -b1001000110100 u- -0v- -sFull64\x20(0) w- -1x- -1y- -1z- -1{- -s0 |- -b0 }- -b0 ~- +sHdlNone\x20(0) t- +b0 u- +sHdlNone\x20(0) v- +b0 w- +sHdlNone\x20(0) x- +b0 y- +sHdlNone\x20(0) z- +b0 {- +sHdlNone\x20(0) |- +sAddSub\x20(0) }- +s0 ~- b0 !. b0 ". -b1001000110100 #. -0$. -sFull64\x20(0) %. -b1111 &. -sHdlSome\x20(1) '. -sLogical\x20(2) (. -s0 ). -b0 *. -b0 +. -b0 ,. +b0 #. +b0 $. +b0 %. +0&. +sFull64\x20(0) '. +0(. +0). +0*. +0+. +s0 ,. b0 -. b0 .. -0/. -sFull64\x20(0) 0. -01. -12. -13. +b0 /. +b0 0. +b0 1. +02. +sFull64\x20(0) 3. 04. -s0 5. -b0 6. -b0 7. -b0 8. +05. +06. +07. +s0 8. b0 9. b0 :. -0;. -sFull64\x20(0) <. -0=. -1>. -1?. -0@. -s0 A. +b0 ;. +b0 <. +b0 =. +0>. +sFull64\x20(0) ?. +b0 @. +sHdlNone\x20(0) A. b0 B. -b0 C. -b0 D. -b0 E. -b0 F. +0C. +0D. +0E. +0F. 0G. -sFull64\x20(0) H. -b110 I. -sHdlSome\x20(1) J. -sLogical\x20(2) K. -s0 L. -b0 M. -b0 N. -b0 O. -b0 P. -b0 Q. +0H. +0I. +0J. +sHdlNone\x20(0) K. +b0 L. +0M. +0N. +0O. +0P. +0Q. 0R. -sFull64\x20(0) S. +0S. 0T. -1U. -1V. +sHdlNone\x20(0) U. +b0 V. 0W. -s0 X. -b0 Y. -b0 Z. -b0 [. -b0 \. -b0 ]. +0X. +0Y. +0Z. +0[. +0\. +0]. 0^. -sFull64\x20(0) _. -0`. -1a. -1b. -0c. -s0 d. +sHdlNone\x20(0) _. +sAddSub\x20(0) `. +s0 a. +b0 b. +b0 c. +b0 d. b0 e. b0 f. -b0 g. -b0 h. -b0 i. +0g. +sFull64\x20(0) h. +0i. 0j. -sFull64\x20(0) k. -b110 l. -0m. -1n. -sHdlSome\x20(1) o. -sLogical\x20(2) p. -s0 q. +0k. +0l. +s0 m. +b0 n. +b0 o. +b0 p. +b0 q. b0 r. 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-b10 D, -b10 C- -b10 O- -b10 [- -b10 f- -b10 r- -b10 ~- -b10 R0 -b10 ^0 -b10 j0 -b10 u0 -b10 #1 -b10 /1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #1000000 0! 0" @@ -9072,29 +15367,29 @@ b10 /1 0w) 0^+ 0_+ -0&, -0', 0L, 0M, -07- -08- -0m. -0n. -05/ -06/ -0[/ -0\/ -0F0 -0G0 +0>5 +0?5 +0^6 +0_6 +0L7 +0M7 +078 +088 +0m9 +0n9 +0[: +0\: +0MC +0NC +0mD +0nD +0[E +0\E +0FF +0GF #1500000 -b1 |1 -b0 _4 -b10 }1 -b0 `4 -b1 B7 -b0 D7 -b10 C7 -b0 E7 1! 1~" 1%# @@ -9133,127 +15428,17 @@ b0 E7 1p) 1w) 1^+ -1&, 1L, -1T, -17- -1m. -15/ -1[/ -1c/ -1F0 -b1 1# -b1 N# -b1 y# -b1 M$ -b1 \$ -b1 h$ -b1 t$ -b1 ~$ -b1 '% -b1 /% -b1 6% -b1 @% -b1 L% -b1 X% -b1 b% -b1 i% -b1 q% -b1 x% -b1 "& -b1 %& -b1 3& -b1 O& -b1 o& -b1 {& -b1 )' -b1 3' -b1 :' -b1 B' -b1 I' -b1 Q' -b1 ]' -b1 i' -b1 s' -b1 z' -b1 $( -b1 +( -b1 V) -b1 y) -b1 4* -b1 @* -b1 L* -b1 V* -b1 ]* -b1 e* -b1 l* -b1 t* -b1 "+ -b1 .+ -b1 8+ -b1 ?+ -b1 G+ -b1 N+ -b1 c+ -b1 o+ -b1 {+ -b1 +, -b1 7, -b1 C, -b1 R, -1f, -0g, -1h, -1l, -b1 n, -1x, -b1 z, -12- -b1 4- -b1 6- -b1 =- -b1 B- -b1 N- -b1 Z- -b1 e- -b1 q- -b1 }- -b1 *. -b1 6. -b1 B. -b1 M. -b1 Y. -b1 e. -b1 r. -b1 ~. -b1 ,/ -b1 :/ -b1 F/ -b1 R/ -b1 a/ -1u/ -0v/ -1w/ -1{/ -b1 }/ -1)0 -b1 +0 -1A0 -b1 C0 -b1 E0 -b1 L0 -b1 Q0 -b1 ]0 -b1 i0 -b1 t0 -b1 "1 -b1 .1 -b1 91 -b1 E1 -b1 Q1 -b1 \1 -b1 h1 -b1 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #2000000 0! 0~" @@ -9293,22 +15478,18 @@ b1 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #2500000 -b1 |1 -b1 _4 -b10 }1 -b1 `4 -b1 B7 -b1 D7 -b10 C7 -b1 E7 1! 1~" 1%# @@ -9347,160 +15528,17 @@ b1 E7 1p) 1w) 1^+ -1&, 1L, -1U, -17- -1m. -15/ -1[/ -1d/ -1F0 -b1 "# -b10 1# -b10 N# -b10 y# -b10 M$ -b10 \$ -b110 ]$ -b10 h$ -b110 i$ -b10 t$ -b110 u$ -b10 ~$ -b110 !% -b10 '% -b110 (% -b10 /% -b110 0% -b10 6% -b110 7% -b10 @% -b10 L% -b10 X% -b10 b% -b10 i% -b10 q% -b10 x% -b10 "& -b10 %& -b1 (& -b10 3& -b10 O& -b10 o& -b110 p& -b10 {& -b110 |& -b10 )' -b110 *' -b10 3' -b110 4' -b10 :' -b110 ;' -b10 B' -b110 C' -b10 I' -b110 J' -b10 Q' -b110 R' -b10 ]' -b110 ^' -b10 i' -b110 j' -b10 s' -b10 z' -b10 $( -b10 +( -b10 V) -b10 y) -b10 4* -b10 @* -b10 L* -b10 V* -b10 ]* -b10 e* -b10 l* -b10 t* -b10 "+ -b10 .+ -b10 8+ -b10 ?+ -b10 G+ -b10 N+ -b10 c+ -b110 d+ -b10 o+ -b110 p+ -b10 {+ -b110 |+ -b10 +, -b110 ,, -b10 7, -b110 8, -b10 C, -b110 D, -b10 R, -0f, -0l, -b10 n, -0x, -b10 z, -02- -b10 4- -b10 6- -b10 =- -b10 B- -b110 C- -b10 N- -b110 O- -b10 Z- -b110 [- -b10 e- -b110 f- -b10 q- -b110 r- -b10 }- -b110 ~- -b10 *. -b10 6. -b10 B. -b10 M. -b10 Y. -b10 e. -b10 r. -b10 ~. -b10 ,/ -b10 :/ -b10 F/ -b10 R/ -b10 a/ -0u/ -0{/ -b10 }/ -0)0 -b10 +0 -0A0 -b10 C0 -b10 E0 -b10 L0 -b10 Q0 -b110 R0 -b10 ]0 -b110 ^0 -b10 i0 -b110 j0 -b10 t0 -b110 u0 -b10 "1 -b110 #1 -b10 .1 -b110 /1 -b10 91 -b10 E1 -b10 Q1 -b10 \1 -b10 h1 -b10 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #3000000 0! 0~" @@ -9540,22 +15578,18 @@ b10 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #3500000 -b1 |1 -b10 _4 -b10 }1 -b10 `4 -b1 B7 -b10 D7 -b10 C7 -b10 E7 1! 1~" 1%# @@ -9594,166 +15628,17 @@ b10 E7 1p) 1w) 1^+ -1&, 1L, -1V, -17- -1m. -15/ -1[/ -1e/ -1F0 -b10 "# -b11 1# -b11 N# -b11 y# -b11 M$ -b11 \$ -b1010 ]$ -b11 h$ -b1010 i$ -b11 t$ -b1010 u$ -b11 ~$ -b1010 !% -b11 '% -b1010 (% -b11 /% -b1010 0% -b11 6% -b1010 7% -b11 @% -b11 L% -b11 X% -b11 b% -b11 i% -b11 q% -b11 x% -b11 "& -b11 %& -b10 (& -b11 3& -b11 O& -b11 o& -b1010 p& -b11 {& -b1010 |& -b11 )' -b1010 *' -b11 3' -b1010 4' -b11 :' -b1010 ;' -b11 B' -b1010 C' -b11 I' -b1010 J' -b11 Q' -b1010 R' -b11 ]' -b1010 ^' -b11 i' -b1010 j' -b11 s' -b11 z' -b11 $( -b11 +( -b11 V) -b11 y) -b11 4* -b11 @* -b11 L* -b11 V* -b11 ]* -b11 e* -b11 l* -b11 t* -b11 "+ -b11 .+ -b11 8+ -b11 ?+ -b11 G+ -b11 N+ -b11 c+ -b1010 d+ -b11 o+ -b1010 p+ -b11 {+ -b1010 |+ -b11 +, -b1010 ,, -b11 7, -b1010 8, -b11 C, -b1010 D, -b11 R, -1i, -0j, -1k, -1l, -0m, -b11 n, -1x, -b11 z, -12- -b11 4- -b11 6- -b11 =- -b11 B- -b1010 C- -b11 N- -b1010 O- -b11 Z- -b1010 [- -b11 e- -b1010 f- -b11 q- -b1010 r- -b11 }- -b1010 ~- -b11 *. -b11 6. -b11 B. -b11 M. -b11 Y. -b11 e. -b11 r. -b11 ~. -b11 ,/ -b11 :/ -b11 F/ -b11 R/ -b11 a/ -1x/ -0y/ -1z/ -1{/ -0|/ -b11 }/ -1)0 -b11 +0 -1A0 -b11 C0 -b11 E0 -b11 L0 -b11 Q0 -b1010 R0 -b11 ]0 -b1010 ^0 -b11 i0 -b1010 j0 -b11 t0 -b1010 u0 -b11 "1 -b1010 #1 -b11 .1 -b1010 /1 -b11 91 -b11 E1 -b11 Q1 -b11 \1 -b11 h1 -b11 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #4000000 0! 0~" @@ -9793,22 +15678,18 @@ b11 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #4500000 -b1 |1 -b11 _4 -b10 }1 -b11 `4 -b1 B7 -b11 D7 -b10 C7 -b11 E7 1! 1~" 1%# @@ -9847,158 +15728,17 @@ b11 E7 1p) 1w) 1^+ -1&, 1L, -1W, -17- -1m. -15/ -1[/ -1f/ -1F0 -b11 "# -b100 1# -b100 N# -b100 y# -b100 M$ -b100 \$ -b1110 ]$ -b100 h$ -b1110 i$ -b100 t$ -b1110 u$ -b100 ~$ -b1110 !% -b100 '% -b1110 (% -b100 /% -b1110 0% -b100 6% -b1110 7% -b100 @% -b100 L% -b100 X% -b100 b% -b100 i% -b100 q% -b100 x% -b100 "& -b100 %& -b11 (& -b100 3& -b100 O& -b100 o& -b1110 p& -b100 {& -b1110 |& -b100 )' -b1110 *' -b100 3' -b1110 4' -b100 :' -b1110 ;' -b100 B' -b1110 C' -b100 I' -b1110 J' -b100 Q' -b1110 R' -b100 ]' -b1110 ^' -b100 i' -b1110 j' -b100 s' -b100 z' -b100 $( -b100 +( -b100 V) -b100 y) -b100 4* -b100 @* -b100 L* -b100 V* -b100 ]* -b100 e* -b100 l* -b100 t* -b100 "+ -b100 .+ -b100 8+ -b100 ?+ -b100 G+ -b100 N+ -b100 c+ -b1110 d+ -b100 o+ -b1110 p+ -b100 {+ -b1110 |+ -b100 +, -b1110 ,, -b100 7, -b1110 8, -b100 C, -b1110 D, -b100 R, -0i, -0l, -0x, -b100 z, -02- -b100 4- -b100 6- -b100 =- -b100 B- -b1110 C- -b100 N- -b1110 O- -b100 Z- -b1110 [- -b100 e- -b1110 f- -b100 q- -b1110 r- -b100 }- -b1110 ~- -b100 *. -b100 6. -b100 B. -b100 M. -b100 Y. -b100 e. -b100 r. -b100 ~. -b100 ,/ -b100 :/ -b100 F/ -b100 R/ -b100 a/ -0x/ -0{/ -0)0 -b100 +0 -0A0 -b100 C0 -b100 E0 -b100 L0 -b100 Q0 -b1110 R0 -b100 ]0 -b1110 ^0 -b100 i0 -b1110 j0 -b100 t0 -b1110 u0 -b100 "1 -b1110 #1 -b100 .1 -b1110 /1 -b100 91 -b100 E1 -b100 Q1 -b100 \1 -b100 h1 -b100 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #5000000 0! 0~" @@ -10038,22 +15778,18 @@ b100 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #5500000 -b1 |1 -b100 _4 -b10 }1 -b100 `4 -b1 B7 -b100 D7 -b10 C7 -b100 E7 1! 1~" 1%# @@ -10092,164 +15828,17 @@ b100 E7 1p) 1w) 1^+ -1&, 1L, -1X, -17- -1m. -15/ -1[/ -1g/ -1F0 -b100 "# -b101 1# -b101 N# -b101 y# -b101 M$ -b101 \$ -b10010 ]$ -b101 h$ -b10010 i$ -b101 t$ -b10010 u$ -b101 ~$ -b10010 !% -b101 '% -b10010 (% -b101 /% -b10010 0% -b101 6% -b10010 7% -b101 @% -b101 L% -b101 X% -b101 b% -b101 i% -b101 q% -b101 x% -b101 "& -b101 %& -b100 (& -b101 3& -b101 O& -b101 o& -b10010 p& -b101 {& -b10010 |& -b101 )' -b10010 *' -b101 3' -b10010 4' -b101 :' -b10010 ;' -b101 B' -b10010 C' -b101 I' -b10010 J' -b101 Q' -b10010 R' -b101 ]' -b10010 ^' -b101 i' -b10010 j' -b101 s' -b101 z' -b101 $( -b101 +( -b101 V) -b101 y) -b101 4* -b101 @* -b101 L* -b101 V* -b101 ]* -b101 e* -b101 l* -b101 t* -b101 "+ -b101 .+ -b101 8+ -b101 ?+ -b101 G+ -b101 N+ -b101 c+ -b10010 d+ -b101 o+ -b10010 p+ -b101 {+ -b10010 |+ -b101 +, -b10010 ,, -b101 7, -b10010 8, -b101 C, -b10010 D, -b101 R, -1o, -0p, -1q, -1u, -b1 w, -1x, -b101 z, -12- -b101 4- -b101 6- -b101 =- -b101 B- -b10010 C- -b101 N- -b10010 O- -b101 Z- -b10010 [- -b101 e- -b10010 f- -b101 q- -b10010 r- -b101 }- -b10010 ~- -b101 *. -b101 6. -b101 B. -b101 M. -b101 Y. -b101 e. -b101 r. -b101 ~. -b101 ,/ -b101 :/ -b101 F/ -b101 R/ -b101 a/ -1~/ -0!0 -1"0 -1&0 -b1 (0 -1)0 -b101 +0 -1A0 -b101 C0 -b101 E0 -b101 L0 -b101 Q0 -b10010 R0 -b101 ]0 -b10010 ^0 -b101 i0 -b10010 j0 -b101 t0 -b10010 u0 -b101 "1 -b10010 #1 -b101 .1 -b10010 /1 -b101 91 -b101 E1 -b101 Q1 -b101 \1 -b101 h1 -b101 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #6000000 0! 0~" @@ -10289,22 +15878,18 @@ b101 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #6500000 -b1 |1 -b101 _4 -b10 }1 -b101 `4 -b1 B7 -b101 D7 -b10 C7 -b101 E7 1! 1~" 1%# @@ -10343,160 +15928,17 @@ b101 E7 1p) 1w) 1^+ -1&, 1L, -1Y, -17- -1m. -15/ -1[/ -1h/ -1F0 -b101 "# -b110 1# -b110 N# -b110 y# -b110 M$ -b110 \$ -b10110 ]$ -b110 h$ -b10110 i$ -b110 t$ -b10110 u$ -b110 ~$ -b10110 !% -b110 '% -b10110 (% -b110 /% -b10110 0% -b110 6% -b10110 7% -b110 @% -b110 L% -b110 X% -b110 b% -b110 i% -b110 q% -b110 x% -b110 "& -b110 %& -b101 (& -b110 3& -b110 O& -b110 o& -b10110 p& -b110 {& -b10110 |& -b110 )' -b10110 *' -b110 3' -b10110 4' -b110 :' -b10110 ;' -b110 B' -b10110 C' -b110 I' -b10110 J' -b110 Q' -b10110 R' -b110 ]' -b10110 ^' -b110 i' -b10110 j' -b110 s' -b110 z' -b110 $( -b110 +( -b110 V) -b110 y) -b110 4* -b110 @* -b110 L* -b110 V* -b110 ]* -b110 e* -b110 l* -b110 t* -b110 "+ -b110 .+ -b110 8+ -b110 ?+ -b110 G+ -b110 N+ -b110 c+ -b10110 d+ -b110 o+ -b10110 p+ -b110 {+ -b10110 |+ -b110 +, -b10110 ,, -b110 7, -b10110 8, -b110 C, -b10110 D, -b110 R, -0o, -0u, -b10 w, -0x, -b110 z, -02- -b110 4- -b110 6- -b110 =- -b110 B- -b10110 C- -b110 N- -b10110 O- -b110 Z- -b10110 [- -b110 e- -b10110 f- -b110 q- -b10110 r- -b110 }- -b10110 ~- -b110 *. -b110 6. -b110 B. -b110 M. -b110 Y. -b110 e. -b110 r. -b110 ~. -b110 ,/ -b110 :/ -b110 F/ -b110 R/ -b110 a/ -0~/ -0&0 -b10 (0 -0)0 -b110 +0 -0A0 -b110 C0 -b110 E0 -b110 L0 -b110 Q0 -b10110 R0 -b110 ]0 -b10110 ^0 -b110 i0 -b10110 j0 -b110 t0 -b10110 u0 -b110 "1 -b10110 #1 -b110 .1 -b10110 /1 -b110 91 -b110 E1 -b110 Q1 -b110 \1 -b110 h1 -b110 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #7000000 0! 0~" @@ -10536,22 +15978,18 @@ b110 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #7500000 -b1 |1 -b110 _4 -b10 }1 -b110 `4 -b1 B7 -b110 D7 -b10 C7 -b110 E7 1! 1~" 1%# @@ -10590,168 +16028,17 @@ b110 E7 1p) 1w) 1^+ -1&, 1L, -1Z, -17- -1m. -15/ -1[/ -1i/ -1F0 -b110 "# -b111 1# -b111 N# -b111 y# -b111 M$ -b111 \$ -b11010 ]$ -b111 h$ -b11010 i$ -b111 t$ -b11010 u$ -b111 ~$ -b11010 !% -b111 '% -b11010 (% -b111 /% -b11010 0% -b111 6% -b11010 7% -b111 @% -b111 L% -b111 X% -b111 b% -b111 i% -b111 q% -b111 x% -b111 "& -b111 %& -b110 (& -b111 3& -b111 O& -b111 o& -b11010 p& -b111 {& -b11010 |& -b111 )' -b11010 *' -b111 3' -b11010 4' -b111 :' -b11010 ;' -b111 B' -b11010 C' -b111 I' -b11010 J' -b111 Q' -b11010 R' -b111 ]' -b11010 ^' -b111 i' -b11010 j' -b111 s' -b111 z' -b111 $( -b111 +( -b111 V) -b111 y) -b111 4* -b111 @* -b111 L* -b111 V* -b111 ]* -b111 e* -b111 l* -b111 t* -b111 "+ -b111 .+ -b111 8+ -b111 ?+ -b111 G+ -b111 N+ -b111 c+ -b11010 d+ -b111 o+ -b11010 p+ -b111 {+ -b11010 |+ -b111 +, -b11010 ,, -b111 7, -b11010 8, -b111 C, -b11010 D, -b111 R, -1r, -0s, -1t, -1u, -0v, -b11 w, -1x, -0y, -b111 z, -12- -b111 4- -b111 6- -b111 =- -b111 B- -b11010 C- -b111 N- -b11010 O- -b111 Z- -b11010 [- -b111 e- -b11010 f- -b111 q- -b11010 r- -b111 }- -b11010 ~- -b111 *. -b111 6. -b111 B. -b111 M. -b111 Y. -b111 e. -b111 r. -b111 ~. -b111 ,/ -b111 :/ -b111 F/ -b111 R/ -b111 a/ -1#0 -0$0 -1%0 -1&0 -0'0 -b11 (0 -1)0 -0*0 -b111 +0 -1A0 -b111 C0 -b111 E0 -b111 L0 -b111 Q0 -b11010 R0 -b111 ]0 -b11010 ^0 -b111 i0 -b11010 j0 -b111 t0 -b11010 u0 -b111 "1 -b11010 #1 -b111 .1 -b11010 /1 -b111 91 -b111 E1 -b111 Q1 -b111 \1 -b111 h1 -b111 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #8000000 0! 0~" @@ -10791,22 +16078,18 @@ b111 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #8500000 -b1 |1 -b111 _4 -b10 }1 -b111 `4 -b1 B7 -b111 D7 -b10 C7 -b111 E7 1! 1~" 1%# @@ -10845,156 +16128,17 @@ b111 E7 1p) 1w) 1^+ -1&, 1L, -1[, -17- -1m. -15/ -1[/ -1j/ -1F0 -b111 "# -b1000 1# -b1000 N# -b1000 y# -b1000 M$ -b1000 \$ -b11110 ]$ -b1000 h$ -b11110 i$ -b1000 t$ -b11110 u$ -b1000 ~$ -b11110 !% -b1000 '% -b11110 (% -b1000 /% -b11110 0% -b1000 6% -b11110 7% -b1000 @% -b1000 L% -b1000 X% -b1000 b% -b1000 i% -b1000 q% -b1000 x% -b1000 "& -b1000 %& -b111 (& -b1000 3& -b1000 O& -b1000 o& -b11110 p& -b1000 {& -b11110 |& -b1000 )' -b11110 *' -b1000 3' -b11110 4' -b1000 :' -b11110 ;' -b1000 B' -b11110 C' -b1000 I' -b11110 J' -b1000 Q' -b11110 R' -b1000 ]' -b11110 ^' -b1000 i' -b11110 j' -b1000 s' -b1000 z' -b1000 $( -b1000 +( -b1000 V) -b1000 y) -b1000 4* -b1000 @* -b1000 L* -b1000 V* -b1000 ]* -b1000 e* -b1000 l* -b1000 t* -b1000 "+ -b1000 .+ -b1000 8+ -b1000 ?+ -b1000 G+ -b1000 N+ -b1000 c+ -b11110 d+ -b1000 o+ -b11110 p+ -b1000 {+ -b11110 |+ -b1000 +, -b11110 ,, -b1000 7, -b11110 8, -b1000 C, -b11110 D, -b1000 R, -0r, -0u, -0x, -02- -b1000 4- -b1000 6- -b1000 =- -b1000 B- -b11110 C- -b1000 N- -b11110 O- -b1000 Z- -b11110 [- -b1000 e- -b11110 f- -b1000 q- -b11110 r- -b1000 }- -b11110 ~- -b1000 *. -b1000 6. -b1000 B. -b1000 M. -b1000 Y. -b1000 e. -b1000 r. -b1000 ~. -b1000 ,/ -b1000 :/ -b1000 F/ -b1000 R/ -b1000 a/ -0#0 -0&0 -0)0 -0A0 -b1000 C0 -b1000 E0 -b1000 L0 -b1000 Q0 -b11110 R0 -b1000 ]0 -b11110 ^0 -b1000 i0 -b11110 j0 -b1000 t0 -b11110 u0 -b1000 "1 -b11110 #1 -b1000 .1 -b11110 /1 -b1000 91 -b1000 E1 -b1000 Q1 -b1000 \1 -b1000 h1 -b1000 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #9000000 0! 0~" @@ -11034,22 +16178,18 @@ b1000 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #9500000 -b1 |1 -b1000 _4 -b10 }1 -b1000 `4 -b1 B7 -b1000 D7 -b10 C7 -b1000 E7 1! 1~" 1%# @@ -11088,164 +16228,17 @@ b1000 E7 1p) 1w) 1^+ -1&, 1L, -1\, -17- -1m. -15/ -1[/ -1k/ -1F0 -b1000 "# -b1001 1# -b1001 N# -b1001 y# -b1001 M$ -b1001 \$ -b100010 ]$ -b1001 h$ -b100010 i$ -b1001 t$ -b100010 u$ -b1001 ~$ -b100010 !% -b1001 '% -b100010 (% -b1001 /% -b100010 0% -b1001 6% -b100010 7% -b1001 @% -b1001 L% -b1001 X% -b1001 b% -b1001 i% -b1001 q% -b1001 x% -b1001 "& -b1001 %& -b1000 (& -b1001 3& -b1001 O& -b1001 o& -b100010 p& -b1001 {& -b100010 |& -b1001 )' -b100010 *' -b1001 3' -b100010 4' -b1001 :' -b100010 ;' -b1001 B' -b100010 C' -b1001 I' -b100010 J' -b1001 Q' -b100010 R' -b1001 ]' -b100010 ^' -b1001 i' -b100010 j' -b1001 s' -b1001 z' -b1001 $( -b1001 +( -b1001 V) -b1001 y) -b1001 4* -b1001 @* -b1001 L* -b1001 V* -b1001 ]* -b1001 e* -b1001 l* -b1001 t* -b1001 "+ -b1001 .+ -b1001 8+ -b1001 ?+ -b1001 G+ -b1001 N+ -b1001 c+ -b100010 d+ -b1001 o+ -b100010 p+ -b1001 {+ -b100010 |+ -b1001 +, -b100010 ,, -b1001 7, -b100010 8, -b1001 C, -b100010 D, -b1001 R, -1{, -0|, -1}, -1#- -b1 %- -1/- -b1 1- -12- -b1001 4- -b1001 6- -b1001 =- -b1001 B- -b100010 C- -b1001 N- -b100010 O- -b1001 Z- -b100010 [- -b1001 e- -b100010 f- -b1001 q- -b100010 r- -b1001 }- -b100010 ~- -b1001 *. -b1001 6. -b1001 B. -b1001 M. -b1001 Y. -b1001 e. -b1001 r. -b1001 ~. -b1001 ,/ -b1001 :/ -b1001 F/ -b1001 R/ -b1001 a/ -1,0 -0-0 -1.0 -120 -b1 40 -1>0 -b1 @0 -1A0 -b1001 C0 -b1001 E0 -b1001 L0 -b1001 Q0 -b100010 R0 -b1001 ]0 -b100010 ^0 -b1001 i0 -b100010 j0 -b1001 t0 -b100010 u0 -b1001 "1 -b100010 #1 -b1001 .1 -b100010 /1 -b1001 91 -b1001 E1 -b1001 Q1 -b1001 \1 -b1001 h1 -b1001 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #10000000 0! 0~" @@ -11285,22 +16278,18 @@ b1001 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #10500000 -b1 |1 -b1001 _4 -b10 }1 -b1001 `4 -b1 B7 -b1001 D7 -b10 C7 -b1001 E7 1! 1~" 1%# @@ -11339,160 +16328,17 @@ b1001 E7 1p) 1w) 1^+ -1&, 1L, -1], -17- -1m. -15/ -1[/ -1l/ -1F0 -b1001 "# -b1010 1# -b1010 N# -b1010 y# -b1010 M$ -b1010 \$ -b100110 ]$ -b1010 h$ -b100110 i$ -b1010 t$ -b100110 u$ -b1010 ~$ -b100110 !% -b1010 '% -b100110 (% -b1010 /% -b100110 0% -b1010 6% -b100110 7% -b1010 @% -b1010 L% -b1010 X% -b1010 b% -b1010 i% -b1010 q% -b1010 x% -b1010 "& -b1010 %& -b1001 (& -b1010 3& -b1010 O& -b1010 o& -b100110 p& -b1010 {& -b100110 |& -b1010 )' -b100110 *' -b1010 3' -b100110 4' -b1010 :' -b100110 ;' -b1010 B' -b100110 C' -b1010 I' -b100110 J' -b1010 Q' -b100110 R' -b1010 ]' -b100110 ^' -b1010 i' -b100110 j' -b1010 s' -b1010 z' -b1010 $( -b1010 +( -b1010 V) -b1010 y) -b1010 4* -b1010 @* -b1010 L* -b1010 V* -b1010 ]* -b1010 e* -b1010 l* -b1010 t* -b1010 "+ -b1010 .+ -b1010 8+ -b1010 ?+ -b1010 G+ -b1010 N+ -b1010 c+ -b100110 d+ -b1010 o+ -b100110 p+ -b1010 {+ -b100110 |+ -b1010 +, -b100110 ,, -b1010 7, -b100110 8, -b1010 C, -b100110 D, -b1010 R, -0{, -0#- -b10 %- -0/- -b10 1- -02- -b1010 4- -b1010 6- -b1010 =- -b1010 B- -b100110 C- -b1010 N- -b100110 O- -b1010 Z- -b100110 [- -b1010 e- -b100110 f- -b1010 q- -b100110 r- -b1010 }- -b100110 ~- -b1010 *. -b1010 6. -b1010 B. -b1010 M. -b1010 Y. -b1010 e. -b1010 r. -b1010 ~. -b1010 ,/ -b1010 :/ -b1010 F/ -b1010 R/ -b1010 a/ -0,0 -020 -b10 40 -0>0 -b10 @0 -0A0 -b1010 C0 -b1010 E0 -b1010 L0 -b1010 Q0 -b100110 R0 -b1010 ]0 -b100110 ^0 -b1010 i0 -b100110 j0 -b1010 t0 -b100110 u0 -b1010 "1 -b100110 #1 -b1010 .1 -b100110 /1 -b1010 91 -b1010 E1 -b1010 Q1 -b1010 \1 -b1010 h1 -b1010 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #11000000 0! 0~" @@ -11532,22 +16378,18 @@ b1010 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #11500000 -b1 |1 -b1010 _4 -b10 }1 -b1010 `4 -b1 B7 -b1010 D7 -b10 C7 -b1010 E7 1! 1~" 1%# @@ -11586,166 +16428,17 @@ b1010 E7 1p) 1w) 1^+ -1&, 1L, -1^, -17- -1m. -15/ -1[/ -1m/ -1F0 -b1010 "# -b1011 1# -b1011 N# -b1011 y# -b1011 M$ -b1011 \$ -b101010 ]$ -b1011 h$ -b101010 i$ -b1011 t$ -b101010 u$ -b1011 ~$ -b101010 !% -b1011 '% -b101010 (% -b1011 /% -b101010 0% -b1011 6% -b101010 7% -b1011 @% -b1011 L% -b1011 X% -b1011 b% -b1011 i% -b1011 q% -b1011 x% -b1011 "& -b1011 %& -b1010 (& -b1011 3& -b1011 O& -b1011 o& -b101010 p& -b1011 {& -b101010 |& -b1011 )' -b101010 *' -b1011 3' -b101010 4' -b1011 :' -b101010 ;' -b1011 B' -b101010 C' -b1011 I' -b101010 J' -b1011 Q' -b101010 R' -b1011 ]' -b101010 ^' -b1011 i' -b101010 j' -b1011 s' -b1011 z' -b1011 $( -b1011 +( -b1011 V) -b1011 y) -b1011 4* -b1011 @* -b1011 L* -b1011 V* -b1011 ]* -b1011 e* -b1011 l* -b1011 t* -b1011 "+ -b1011 .+ -b1011 8+ -b1011 ?+ -b1011 G+ -b1011 N+ -b1011 c+ -b101010 d+ -b1011 o+ -b101010 p+ -b1011 {+ -b101010 |+ -b1011 +, -b101010 ,, -b1011 7, -b101010 8, -b1011 C, -b101010 D, -b1011 R, -1~, -0!- -1"- -1#- -0$- -b11 %- -1/- -b11 1- -12- -b1011 4- -b1011 6- -b1011 =- -b1011 B- -b101010 C- -b1011 N- -b101010 O- -b1011 Z- -b101010 [- -b1011 e- -b101010 f- -b1011 q- -b101010 r- -b1011 }- -b101010 ~- -b1011 *. -b1011 6. -b1011 B. -b1011 M. -b1011 Y. -b1011 e. -b1011 r. -b1011 ~. -b1011 ,/ -b1011 :/ -b1011 F/ -b1011 R/ -b1011 a/ -1/0 -000 -110 -120 -030 -b11 40 -1>0 -b11 @0 -1A0 -b1011 C0 -b1011 E0 -b1011 L0 -b1011 Q0 -b101010 R0 -b1011 ]0 -b101010 ^0 -b1011 i0 -b101010 j0 -b1011 t0 -b101010 u0 -b1011 "1 -b101010 #1 -b1011 .1 -b101010 /1 -b1011 91 -b1011 E1 -b1011 Q1 -b1011 \1 -b1011 h1 -b1011 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #12000000 0! 0~" @@ -11785,22 +16478,18 @@ b1011 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #12500000 -b1 |1 -b1011 _4 -b10 }1 -b1011 `4 -b1 B7 -b1011 D7 -b10 C7 -b1011 E7 1! 1~" 1%# @@ -11839,158 +16528,17 @@ b1011 E7 1p) 1w) 1^+ -1&, 1L, -1_, -17- -1m. -15/ -1[/ -1n/ -1F0 -b1011 "# -b1100 1# -b1100 N# -b1100 y# -b1100 M$ -b1100 \$ -b101110 ]$ -b1100 h$ -b101110 i$ -b1100 t$ -b101110 u$ -b1100 ~$ -b101110 !% -b1100 '% -b101110 (% -b1100 /% -b101110 0% -b1100 6% -b101110 7% -b1100 @% -b1100 L% -b1100 X% -b1100 b% -b1100 i% -b1100 q% -b1100 x% -b1100 "& -b1100 %& -b1011 (& -b1100 3& -b1100 O& -b1100 o& -b101110 p& -b1100 {& -b101110 |& -b1100 )' -b101110 *' -b1100 3' -b101110 4' -b1100 :' -b101110 ;' -b1100 B' -b101110 C' -b1100 I' -b101110 J' -b1100 Q' -b101110 R' -b1100 ]' -b101110 ^' -b1100 i' -b101110 j' -b1100 s' -b1100 z' -b1100 $( -b1100 +( -b1100 V) -b1100 y) -b1100 4* -b1100 @* -b1100 L* -b1100 V* -b1100 ]* -b1100 e* -b1100 l* -b1100 t* -b1100 "+ -b1100 .+ -b1100 8+ -b1100 ?+ -b1100 G+ -b1100 N+ -b1100 c+ -b101110 d+ -b1100 o+ -b101110 p+ -b1100 {+ -b101110 |+ -b1100 +, -b101110 ,, -b1100 7, -b101110 8, -b1100 C, -b101110 D, -b1100 R, -0~, -0#- -0/- -b100 1- -02- -b1100 4- -b1100 6- -b1100 =- -b1100 B- -b101110 C- -b1100 N- -b101110 O- -b1100 Z- -b101110 [- -b1100 e- -b101110 f- -b1100 q- -b101110 r- -b1100 }- -b101110 ~- -b1100 *. -b1100 6. -b1100 B. -b1100 M. -b1100 Y. -b1100 e. -b1100 r. -b1100 ~. -b1100 ,/ -b1100 :/ -b1100 F/ -b1100 R/ -b1100 a/ -0/0 -020 -0>0 -b100 @0 -0A0 -b1100 C0 -b1100 E0 -b1100 L0 -b1100 Q0 -b101110 R0 -b1100 ]0 -b101110 ^0 -b1100 i0 -b101110 j0 -b1100 t0 -b101110 u0 -b1100 "1 -b101110 #1 -b1100 .1 -b101110 /1 -b1100 91 -b1100 E1 -b1100 Q1 -b1100 \1 -b1100 h1 -b1100 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #13000000 0! 0~" @@ -12030,22 +16578,18 @@ b1100 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #13500000 -b1 |1 -b1100 _4 -b10 }1 -b1100 `4 -b1 B7 -b1100 D7 -b10 C7 -b1100 E7 1! 1~" 1%# @@ -12084,164 +16628,17 @@ b1100 E7 1p) 1w) 1^+ -1&, 1L, -1`, -17- -1m. -15/ -1[/ -1o/ -1F0 -b1100 "# -b1101 1# -b1101 N# -b1101 y# -b1101 M$ -b1101 \$ -b110010 ]$ -b1101 h$ -b110010 i$ -b1101 t$ -b110010 u$ -b1101 ~$ -b110010 !% -b1101 '% -b110010 (% -b1101 /% -b110010 0% -b1101 6% -b110010 7% -b1101 @% -b1101 L% -b1101 X% -b1101 b% -b1101 i% -b1101 q% -b1101 x% -b1101 "& -b1101 %& -b1100 (& -b1101 3& -b1101 O& -b1101 o& -b110010 p& -b1101 {& -b110010 |& -b1101 )' -b110010 *' -b1101 3' -b110010 4' -b1101 :' -b110010 ;' -b1101 B' -b110010 C' -b1101 I' -b110010 J' -b1101 Q' -b110010 R' -b1101 ]' -b110010 ^' -b1101 i' -b110010 j' -b1101 s' -b1101 z' -b1101 $( -b1101 +( -b1101 V) -b1101 y) -b1101 4* -b1101 @* -b1101 L* -b1101 V* -b1101 ]* -b1101 e* -b1101 l* -b1101 t* -b1101 "+ -b1101 .+ -b1101 8+ -b1101 ?+ -b1101 G+ -b1101 N+ -b1101 c+ -b110010 d+ -b1101 o+ -b110010 p+ -b1101 {+ -b110010 |+ -b1101 +, -b110010 ,, -b1101 7, -b110010 8, -b1101 C, -b110010 D, -b1101 R, -1&- -0'- -1(- -1,- -b1 .- -1/- -b101 1- -12- -b1101 4- -b1101 6- -b1101 =- -b1101 B- -b110010 C- -b1101 N- -b110010 O- -b1101 Z- -b110010 [- -b1101 e- -b110010 f- -b1101 q- -b110010 r- -b1101 }- -b110010 ~- -b1101 *. -b1101 6. -b1101 B. -b1101 M. -b1101 Y. -b1101 e. -b1101 r. -b1101 ~. -b1101 ,/ -b1101 :/ -b1101 F/ -b1101 R/ -b1101 a/ -150 -060 -170 -1;0 -b1 =0 -1>0 -b101 @0 -1A0 -b1101 C0 -b1101 E0 -b1101 L0 -b1101 Q0 -b110010 R0 -b1101 ]0 -b110010 ^0 -b1101 i0 -b110010 j0 -b1101 t0 -b110010 u0 -b1101 "1 -b110010 #1 -b1101 .1 -b110010 /1 -b1101 91 -b1101 E1 -b1101 Q1 -b1101 \1 -b1101 h1 -b1101 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #14000000 0! 0~" @@ -12281,22 +16678,18 @@ b1101 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #14500000 -b1 |1 -b1101 _4 -b10 }1 -b1101 `4 -b1 B7 -b1101 D7 -b10 C7 -b1101 E7 1! 1~" 1%# @@ -12335,160 +16728,17 @@ b1101 E7 1p) 1w) 1^+ -1&, 1L, -1a, -17- -1m. -15/ -1[/ -1p/ -1F0 -b1101 "# -b1110 1# -b1110 N# -b1110 y# -b1110 M$ -b1110 \$ -b110110 ]$ -b1110 h$ -b110110 i$ -b1110 t$ -b110110 u$ -b1110 ~$ -b110110 !% -b1110 '% -b110110 (% -b1110 /% -b110110 0% -b1110 6% -b110110 7% -b1110 @% -b1110 L% -b1110 X% -b1110 b% -b1110 i% -b1110 q% -b1110 x% -b1110 "& -b1110 %& -b1101 (& -b1110 3& -b1110 O& -b1110 o& -b110110 p& -b1110 {& -b110110 |& -b1110 )' -b110110 *' -b1110 3' -b110110 4' -b1110 :' -b110110 ;' -b1110 B' -b110110 C' -b1110 I' -b110110 J' -b1110 Q' -b110110 R' -b1110 ]' -b110110 ^' -b1110 i' -b110110 j' -b1110 s' -b1110 z' -b1110 $( -b1110 +( -b1110 V) -b1110 y) -b1110 4* -b1110 @* -b1110 L* -b1110 V* -b1110 ]* -b1110 e* -b1110 l* -b1110 t* -b1110 "+ -b1110 .+ -b1110 8+ -b1110 ?+ -b1110 G+ -b1110 N+ -b1110 c+ -b110110 d+ -b1110 o+ -b110110 p+ -b1110 {+ -b110110 |+ -b1110 +, -b110110 ,, -b1110 7, -b110110 8, -b1110 C, -b110110 D, -b1110 R, -0&- -0,- -b10 .- -0/- -b110 1- -02- -b1110 4- -b1110 6- -b1110 =- -b1110 B- -b110110 C- -b1110 N- -b110110 O- -b1110 Z- -b110110 [- -b1110 e- -b110110 f- -b1110 q- -b110110 r- -b1110 }- -b110110 ~- -b1110 *. -b1110 6. -b1110 B. -b1110 M. -b1110 Y. -b1110 e. -b1110 r. -b1110 ~. -b1110 ,/ -b1110 :/ -b1110 F/ -b1110 R/ -b1110 a/ -050 -0;0 -b10 =0 -0>0 -b110 @0 -0A0 -b1110 C0 -b1110 E0 -b1110 L0 -b1110 Q0 -b110110 R0 -b1110 ]0 -b110110 ^0 -b1110 i0 -b110110 j0 -b1110 t0 -b110110 u0 -b1110 "1 -b110110 #1 -b1110 .1 -b110110 /1 -b1110 91 -b1110 E1 -b1110 Q1 -b1110 \1 -b1110 h1 -b1110 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #15000000 0! 0~" @@ -12528,22 +16778,18 @@ b1110 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #15500000 -b1 |1 -b1110 _4 -b10 }1 -b1110 `4 -b1 B7 -b1110 D7 -b10 C7 -b1110 E7 1! 1~" 1%# @@ -12582,170 +16828,17 @@ b1110 E7 1p) 1w) 1^+ -1&, 1L, -1b, -17- -1m. -15/ -1[/ -1q/ -1F0 -b1110 "# -b1111 1# -b1111 N# -b1111 y# -b1111 M$ -b1111 \$ -b111010 ]$ -b1111 h$ -b111010 i$ -b1111 t$ -b111010 u$ -b1111 ~$ -b111010 !% -b1111 '% -b111010 (% -b1111 /% -b111010 0% -b1111 6% -b111010 7% -b1111 @% -b1111 L% -b1111 X% -b1111 b% -b1111 i% -b1111 q% -b1111 x% -b1111 "& -b1111 %& -b1110 (& -b1111 3& -b1111 O& -b1111 o& -b111010 p& -b1111 {& -b111010 |& -b1111 )' -b111010 *' -b1111 3' -b111010 4' -b1111 :' -b111010 ;' -b1111 B' -b111010 C' -b1111 I' -b111010 J' -b1111 Q' -b111010 R' -b1111 ]' -b111010 ^' -b1111 i' -b111010 j' -b1111 s' -b1111 z' -b1111 $( -b1111 +( -b1111 V) -b1111 y) -b1111 4* -b1111 @* -b1111 L* -b1111 V* -b1111 ]* -b1111 e* -b1111 l* -b1111 t* -b1111 "+ -b1111 .+ -b1111 8+ -b1111 ?+ -b1111 G+ -b1111 N+ -b1111 c+ -b111010 d+ -b1111 o+ -b111010 p+ -b1111 {+ -b111010 |+ -b1111 +, -b111010 ,, -b1111 7, -b111010 8, -b1111 C, -b111010 D, -b1111 R, -1)- -0*- -1+- -1,- -0-- -b11 .- -1/- -00- -b111 1- -12- -03- -b1111 4- -b1111 6- -b1111 =- -b1111 B- -b111010 C- -b1111 N- -b111010 O- -b1111 Z- -b111010 [- -b1111 e- -b111010 f- -b1111 q- -b111010 r- -b1111 }- -b111010 ~- -b1111 *. -b1111 6. -b1111 B. -b1111 M. -b1111 Y. -b1111 e. -b1111 r. -b1111 ~. -b1111 ,/ -b1111 :/ -b1111 F/ -b1111 R/ -b1111 a/ -180 -090 -1:0 -1;0 -0<0 -b11 =0 -1>0 -0?0 -b111 @0 -1A0 -0B0 -b1111 C0 -b1111 E0 -b1111 L0 -b1111 Q0 -b111010 R0 -b1111 ]0 -b111010 ^0 -b1111 i0 -b111010 j0 -b1111 t0 -b111010 u0 -b1111 "1 -b111010 #1 -b1111 .1 -b111010 /1 -b1111 91 -b1111 E1 -b1111 Q1 -b1111 \1 -b1111 h1 -b1111 t1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #16000000 0! 0~" @@ -12785,22 +16878,18 @@ b1111 t1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #16500000 -b1 |1 -b1111 _4 -b10 }1 -b1111 `4 -b1 B7 -b1111 D7 -b10 C7 -b1111 E7 1! 1~" 1%# @@ -12839,363 +16928,17 @@ b1111 E7 1p) 1w) 1^+ -1&, 1L, -1c, -17- -1m. -15/ -1[/ -1r/ -1F0 -b0 |" -0}" -b0 !# -b0 "# -b0 ## -0$# -b0 (# -0)# -0.# -b0 0# -b0 1# -b0 ;# -0<# -b0 @# -0A# -b0 J# -0K# -b0 M# -b0 N# -0v# -b0 x# -b0 y# -0I$ -0J$ -b0 L$ -b0 M$ -0P$ -0Q$ -0S$ -sHdlNone\x20(0) T$ -sHdlNone\x20(0) V$ -b0 W$ -sHdlNone\x20(0) X$ -b0 \$ -b0 ]$ -b0 `$ -0c$ -0d$ -0e$ -0f$ -b0 h$ -b0 i$ -b0 l$ -0o$ -0p$ -0q$ -0r$ -b0 t$ -b0 u$ -b0 x$ -b0 {$ -b0 ~$ -b0 !% -b0 $% -b0 '% -b0 (% -b0 +% -b0 /% -b0 0% -b0 3% -b0 6% -b0 7% -b0 :% -sHdlNone\x20(0) <% -sAddSub\x20(0) >% -b0 @% -0H% -0I% -b0 L% -0T% -0U% -b0 X% -b0 _% -0a% -b0 b% -0h% -b0 i% -0p% -b0 q% -0w% -b0 x% -sHdlNone\x20(0) ~% -b0 !& -b0 "& -sHdlNone\x20(0) #& -b0 $& -b0 %& -b0 && -b0 '& -b0 (& -b0 )& -b0 ,& -00& -b0 2& -b0 3& -0L& -b0 N& -b0 O& -b0 o& -b0 p& -b0 {& -b0 |& -b0 )' -b0 *' -b0 3' -b0 4' -b0 :' -b0 ;' -b0 B' -b0 C' -b0 I' -b0 J' -b0 Q' -b0 R' -b0 ]' -b0 ^' -b0 i' -b0 j' -b0 s' -b0 z' -b0 $( -b0 +( -sHdlNone\x20(0) 3( -sHdlNone\x20(0) 6( -b0 7( -sHdlNone\x20(0) 9( -b0 ;( -b0 b( -b0 R) -0S) -b0 U) -b0 V) -0u) -0v) -b0 x) -b0 y) -b0 4* -b0 @* -b0 L* -b0 V* -b0 ]* -b0 e* -b0 l* -b0 t* -b0 "+ -b0 .+ -b0 8+ -b0 ?+ -b0 G+ -b0 N+ -sHdlNone\x20(0) Y+ -b0 Z+ -sHdlNone\x20(0) \+ -b0 ]+ -sHdlNone\x20(0) `+ -b0 c+ -b0 d+ -b0 g+ -0j+ -0k+ -0l+ -0m+ -b0 o+ -b0 p+ -b0 s+ -0v+ -0w+ -0x+ -0y+ -b0 {+ -b0 |+ -b0 !, -b0 $, -sHdlNone\x20(0) (, -b0 +, -b0 ,, -b0 /, -02, -03, -04, -05, -b0 7, -b0 8, -b0 ;, -0>, -0?, -0@, -0A, -b0 C, -b0 D, -b0 G, -b0 J, -sHdlNone\x20(0) Q, -b0 R, -0S, -0)- -0,- -0/- -02- -sHdlNone\x20(0) 5- -b0 6- -sHdlNone\x20(0) <- -b0 =- -0>- -sHdlNone\x20(0) ?- -b0 B- -b0 C- -b0 F- -0I- -0J- -0K- -0L- -b0 N- -b0 O- -b0 R- -0U- -0V- -0W- -0X- -b0 Z- -b0 [- -b0 ^- -b0 a- -b0 e- -b0 f- -b0 i- -0l- -0m- -0n- -0o- -b0 q- -b0 r- -b0 u- -0x- -0y- -0z- -0{- -b0 }- -b0 ~- -b0 #. -b0 &. -sHdlNone\x20(0) '. -sAddSub\x20(0) (. -b0 *. -02. -03. -b0 6. -0>. -0?. -b0 B. -b0 I. -sAddSub\x20(0) K. -b0 M. -0U. -0V. -b0 Y. -0a. -0b. -b0 e. -b0 l. -sHdlNone\x20(0) o. -sAddSub\x20(0) p. -b0 r. -0z. -0{. -b0 ~. -0(/ -0)/ -b0 ,/ -b0 3/ -sHdlNone\x20(0) 7/ -sAddSub\x20(0) 8/ -b0 :/ -0B/ -0C/ -b0 F/ -0N/ -0O/ -b0 R/ -b0 Y/ -sHdlNone\x20(0) `/ -b0 a/ -0b/ -080 -0;0 -0>0 -0A0 -sHdlNone\x20(0) D0 -b0 E0 -sHdlNone\x20(0) K0 -b0 L0 -0M0 -sHdlNone\x20(0) N0 -b0 Q0 -b0 R0 -b0 U0 -0X0 -0Y0 -0Z0 -0[0 -b0 ]0 -b0 ^0 -b0 a0 -0d0 -0e0 -0f0 -0g0 -b0 i0 -b0 j0 -b0 m0 -b0 p0 -b0 t0 -b0 u0 -b0 x0 -0{0 -0|0 -0}0 -0~0 -b0 "1 -b0 #1 -b0 &1 -0)1 -0*1 -0+1 -0,1 -b0 .1 -b0 /1 -b0 21 -b0 51 -sHdlNone\x20(0) 61 -sAddSub\x20(0) 71 -b0 91 -0A1 -0B1 -b0 E1 -0M1 -0N1 -b0 Q1 -b0 X1 -sAddSub\x20(0) Z1 -b0 \1 -0d1 -0e1 -b0 h1 -0p1 -0q1 -b0 t1 -b0 {1 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #17000000 0! 0~" @@ -13235,13 +16978,17 @@ b0 {1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #17500000 1! 1~" @@ -13281,13 +17028,17 @@ b0 {1 1p) 1w) 1^+ -1&, 1L, -17- -1m. -15/ -1[/ -1F0 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #18000000 0! 0~" @@ -13327,13 +17078,17 @@ b0 {1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #18500000 1! 1~" @@ -13373,13 +17128,17 @@ b0 {1 1p) 1w) 1^+ -1&, 1L, -17- -1m. -15/ -1[/ -1F0 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #19000000 0! 0~" @@ -13419,13 +17178,17 @@ b0 {1 0p) 0w) 0^+ -0&, 0L, -07- -0m. -05/ -0[/ -0F0 +0>5 +0^6 +0L7 +078 +0m9 +0[: +0MC +0mD +0[E +0FF #19500000 1! 1~" @@ -13465,11 +17228,15 @@ b0 {1 1p) 1w) 1^+ -1&, 1L, -17- -1m. -15/ -1[/ -1F0 +1>5 +1^6 +1L7 +178 +1m9 +1[: +1MC +1mD +1[E +1FF #20000000 diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs index 2d6ae29..5c15d13 100644 --- a/crates/cpu/tests/reg_alloc.rs +++ b/crates/cpu/tests/reg_alloc.rs @@ -2,7 +2,7 @@ // See Notices.txt for copyright information use cpu::{ - config::CpuConfig, + config::{CpuConfig, UnitConfig}, instruction::{ AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode, COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH, @@ -23,7 +23,10 @@ use std::num::NonZeroUsize; #[test] fn test_reg_alloc() { let _n = SourceLocation::normalize_files_for_tests(); - let mut config = CpuConfig::new(vec![UnitKind::AluBranch, UnitKind::AluBranch]); + let mut config = CpuConfig::new(vec![ + UnitConfig::new(UnitKind::AluBranch), + UnitConfig::new(UnitKind::AluBranch), + ]); config.fetch_width = NonZeroUsize::new(2).unwrap(); let m = reg_alloc(&config); let mut sim = Simulation::new(m); @@ -192,14 +195,35 @@ circuit reg_alloc: type Ty61 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>} type Ty62 = {|HdlNone, HdlSome: Ty46|} type Ty63 = {data: Ty62, flip ready: UInt<1>} - type Ty64 = {flip cd: Ty0, flip `input`: Ty63} - type Ty65 = {|HdlNone, HdlSome: UInt<4>|} - type Ty66 = {data: Ty65, flip ready: UInt<1>} - type Ty67 = {flip cd: Ty0, flip free_in: Ty66[1], alloc_out: Ty66[1]} - module reg_alloc: @[reg_alloc.rs 48:1] - input cd: Ty0 @[reg_alloc.rs 52:29] - input fetch_decode_interface: Ty22 @[reg_alloc.rs 55:11] - mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 73:25] + type Ty64 = {pwr_ca_x86_cf: UInt<1>, pwr_ca32_x86_af: UInt<1>, pwr_ov_x86_of: UInt<1>, pwr_ov32_x86_df: UInt<1>, pwr_cr_lt_x86_sf: UInt<1>, pwr_cr_gt_x86_pf: UInt<1>, pwr_cr_eq_x86_zf: UInt<1>, pwr_so: UInt<1>} + type Ty65 = {int_fp: UInt<64>, flags: Ty64} + type Ty66 = {which: Ty24, value: Ty65} + type Ty67 = {|HdlNone, HdlSome: Ty66|} + type Ty68 = {unit_output_writes: Ty67[2], _phantom: Ty2} + type Ty69 = {which: Ty24} + type Ty70 = {|HdlNone, HdlSome: Ty69|} + type Ty71 = {data: Ty70, flip ready: UInt<1>} + type Ty72 = {value: Ty65, extra_out: Ty2} + type Ty73 = {|Completed: Ty72, Trap: Ty2|} + type Ty74 = {which: Ty24, result: Ty73} + type Ty75 = {|HdlNone, HdlSome: Ty74|} + type Ty76 = {data: Ty75, flip ready: UInt<1>} + type Ty77 = {flip cd: Ty0, flip input_insn: Ty63, flip unit_forwarding_info: Ty68, flip cancel_input: Ty71, `output`: Ty76} + type Ty78 = {|HdlNone, HdlSome: UInt<4>|} + type Ty79 = {data: Ty78, flip ready: UInt<1>} + type Ty80 = {flip cd: Ty0, flip free_in: Ty79[1], alloc_out: Ty79[1]} + type Ty81 = {mop: Ty46, src_values: Ty65[3]} + type Ty82 = {|HdlNone, HdlSome: Ty81|} + type Ty83 = {data: Ty82, flip ready: UInt<1>} + type Ty84 = {flip cd: Ty0, flip unit_forwarding_info: Ty68, flip input_insn: Ty63, flip cancel_input: Ty71, ready_mop: Ty83} + type Ty85 = {|HdlNone, HdlSome: UInt<3>|} + type Ty86 = {|HdlNone, HdlSome: Ty65|} + type Ty87 = {mop: Ty46, src_values: Ty86[3]} + type Ty88 = {|HdlNone, HdlSome: Ty87|} + module reg_alloc: @[reg_alloc.rs 49:1] + input cd: Ty0 @[reg_alloc.rs 53:29] + input fetch_decode_interface: Ty22 @[reg_alloc.rs 56:11] + mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 74:25] data-type => UInt<2> depth => 253 read-latency => 0 @@ -215,7 +239,7 @@ circuit reg_alloc: writer => w4 writer => w8 writer => w9 - mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 73:25] + mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 74:25] data-type => UInt<4> depth => 253 read-latency => 0 @@ -231,7 +255,7 @@ circuit reg_alloc: writer => w4 writer => w8 writer => w9 - mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 73:25] + mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 74:25] data-type => UInt<2> depth => 2 read-latency => 0 @@ -251,7 +275,7 @@ circuit reg_alloc: writer => w11 writer => w12 writer => w13 - mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 73:25] + mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 74:25] data-type => UInt<4> depth => 2 read-latency => 0 @@ -271,248 +295,248 @@ circuit reg_alloc: writer => w11 writer => w12 writer => w13 - wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_w3: Ty30 @[reg_alloc.rs 167:39] - wire rename_table_normal_mem_w4: Ty30 @[reg_alloc.rs 167:39] - wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_r6: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_r7: Ty26 @[reg_alloc.rs 120:37] - wire rename_table_normal_mem_w8: Ty30 @[reg_alloc.rs 167:39] - wire rename_table_normal_mem_w9: Ty30 @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.w3.data, rename_table_normal_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.mask, rename_table_normal_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.data, rename_table_normal_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.mask, rename_table_normal_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r6.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r6.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r7.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.w8.data, rename_table_normal_mem_w8.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.mask, rename_table_normal_mem_w8.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.data, rename_table_normal_mem_w9.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.mask, rename_table_normal_mem_w9.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_num_adj_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_num_adj_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.w3.data, rename_table_normal_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.mask, rename_table_normal_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.data, rename_table_normal_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.mask, rename_table_normal_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r6.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r6.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_r7.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.w8.data, rename_table_normal_mem_w8.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.mask, rename_table_normal_mem_w8.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.data, rename_table_normal_mem_w9.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.mask, rename_table_normal_mem_w9.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 120:37] - connect rename_table_normal_mem_unit_out_reg_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 167:39] - connect rename_table_normal_mem_unit_out_reg_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 167:39] - wire rename_table_special_mem_r0: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_r1: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_r2: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_w3: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w4: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w5: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w6: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_r7: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_r8: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_r9: Ty35 @[reg_alloc.rs 120:37] - wire rename_table_special_mem_w10: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w11: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w12: Ty36 @[reg_alloc.rs 167:39] - wire rename_table_special_mem_w13: Ty36 @[reg_alloc.rs 167:39] - connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.w3.data, rename_table_special_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w3.mask, rename_table_special_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w4.data, rename_table_special_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w4.mask, rename_table_special_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w5.data, rename_table_special_mem_w5.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w5.mask, rename_table_special_mem_w5.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w6.data, rename_table_special_mem_w6.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w6.mask, rename_table_special_mem_w6.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_r7.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r8.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r8.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r9.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r9.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.w10.data, rename_table_special_mem_w10.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w10.mask, rename_table_special_mem_w10.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w11.data, rename_table_special_mem_w11.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w11.mask, rename_table_special_mem_w11.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w12.data, rename_table_special_mem_w12.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w12.mask, rename_table_special_mem_w12.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w13.data, rename_table_special_mem_w13.data.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w13.mask, rename_table_special_mem_w13.mask.unit_num.adj_value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_num_adj_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_num_adj_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.w3.data, rename_table_special_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w3.mask, rename_table_special_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w4.data, rename_table_special_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w4.mask, rename_table_special_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w5.data, rename_table_special_mem_w5.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w5.mask, rename_table_special_mem_w5.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w6.data, rename_table_special_mem_w6.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w6.mask, rename_table_special_mem_w6.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_r7.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r8.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r8.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_r9.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r9.data @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.w10.data, rename_table_special_mem_w10.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w10.mask, rename_table_special_mem_w10.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w11.data, rename_table_special_mem_w11.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w11.mask, rename_table_special_mem_w11.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w12.data, rename_table_special_mem_w12.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w12.mask, rename_table_special_mem_w12.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w13.data, rename_table_special_mem_w13.data.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w13.mask, rename_table_special_mem_w13.mask.unit_out_reg.value @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 120:37] - connect rename_table_special_mem_unit_out_reg_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 167:39] - connect rename_table_special_mem_unit_out_reg_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 167:39] - connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 57:5] - wire available_units: UInt<1>[2][2] @[reg_alloc.rs 83:9] + wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_w3: Ty30 @[reg_alloc.rs 166:39] + wire rename_table_normal_mem_w4: Ty30 @[reg_alloc.rs 166:39] + wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_r6: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_r7: Ty26 @[reg_alloc.rs 119:37] + wire rename_table_normal_mem_w8: Ty30 @[reg_alloc.rs 166:39] + wire rename_table_normal_mem_w9: Ty30 @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.w3.data, rename_table_normal_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w3.mask, rename_table_normal_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w4.data, rename_table_normal_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w4.mask, rename_table_normal_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r6.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r6.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r7.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.w8.data, rename_table_normal_mem_w8.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w8.mask, rename_table_normal_mem_w8.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w9.data, rename_table_normal_mem_w9.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w9.mask, rename_table_normal_mem_w9.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_num_adj_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_num_adj_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.w3.data, rename_table_normal_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w3.mask, rename_table_normal_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w4.data, rename_table_normal_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w4.mask, rename_table_normal_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r6.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r6.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_r7.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.w8.data, rename_table_normal_mem_w8.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w8.mask, rename_table_normal_mem_w8.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w9.data, rename_table_normal_mem_w9.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w9.mask, rename_table_normal_mem_w9.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 119:37] + connect rename_table_normal_mem_unit_out_reg_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 166:39] + connect rename_table_normal_mem_unit_out_reg_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 166:39] + wire rename_table_special_mem_r0: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_r1: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_r2: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_w3: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w4: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w5: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w6: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_r7: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_r8: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_r9: Ty35 @[reg_alloc.rs 119:37] + wire rename_table_special_mem_w10: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w11: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w12: Ty36 @[reg_alloc.rs 166:39] + wire rename_table_special_mem_w13: Ty36 @[reg_alloc.rs 166:39] + connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.w3.data, rename_table_special_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w3.mask, rename_table_special_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w4.data, rename_table_special_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w4.mask, rename_table_special_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w5.data, rename_table_special_mem_w5.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w5.mask, rename_table_special_mem_w5.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w6.data, rename_table_special_mem_w6.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w6.mask, rename_table_special_mem_w6.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_r7.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r8.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r8.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r9.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r9.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.w10.data, rename_table_special_mem_w10.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w10.mask, rename_table_special_mem_w10.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w11.data, rename_table_special_mem_w11.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w11.mask, rename_table_special_mem_w11.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w12.data, rename_table_special_mem_w12.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w12.mask, rename_table_special_mem_w12.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w13.data, rename_table_special_mem_w13.data.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w13.mask, rename_table_special_mem_w13.mask.unit_num.adj_value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_num_adj_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_num_adj_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.w3.data, rename_table_special_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w3.mask, rename_table_special_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w4.data, rename_table_special_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w4.mask, rename_table_special_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w5.data, rename_table_special_mem_w5.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w5.mask, rename_table_special_mem_w5.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w6.data, rename_table_special_mem_w6.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w6.mask, rename_table_special_mem_w6.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_r7.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r8.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r8.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_r9.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r9.data @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.w10.data, rename_table_special_mem_w10.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w10.mask, rename_table_special_mem_w10.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w11.data, rename_table_special_mem_w11.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w11.mask, rename_table_special_mem_w11.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w12.data, rename_table_special_mem_w12.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w12.mask, rename_table_special_mem_w12.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w13.data, rename_table_special_mem_w13.data.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w13.mask, rename_table_special_mem_w13.mask.unit_out_reg.value @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 119:37] + connect rename_table_special_mem_unit_out_reg_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 166:39] + connect rename_table_special_mem_unit_out_reg_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 166:39] + connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 58:5] + wire available_units: UInt<1>[2][2] @[reg_alloc.rs 83:27] wire selected_unit_indexes: Ty41[2] @[reg_alloc.rs 86:9] wire renamed_mops: Ty52[2] @[reg_alloc.rs 88:24] wire renamed_mops_out_reg: Ty53[2] @[reg_alloc.rs 90:32] @@ -534,29 +558,29 @@ circuit reg_alloc: connect _bundle_literal_expr_3.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_1.unit_out_reg, _bundle_literal_expr_3 connect rename_0_src_0.data, _bundle_literal_expr_1 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_0.data, rename_table_normal_mem_r0.data @[reg_alloc.rs 129:21] - connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_0.data, rename_table_normal_mem_r0.data @[reg_alloc.rs 128:21] + connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_0.data, rename_table_special_mem_r0.data @[reg_alloc.rs 129:21] + connect rename_table_special_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_0.data, rename_table_special_mem_r0.data @[reg_alloc.rs 128:21] wire rename_0_src_1: Ty54 @[reg_alloc.rs 113:17] wire _bundle_literal_expr_4: Ty1 connect _bundle_literal_expr_4.value, tail(UInt<32>(0h0), 24) @@ -569,29 +593,29 @@ circuit reg_alloc: connect _bundle_literal_expr_7.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_5.unit_out_reg, _bundle_literal_expr_7 connect rename_0_src_1.data, _bundle_literal_expr_5 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_1.data, rename_table_normal_mem_r1.data @[reg_alloc.rs 129:21] - connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_1.data, rename_table_normal_mem_r1.data @[reg_alloc.rs 128:21] + connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_1.data, rename_table_special_mem_r1.data @[reg_alloc.rs 129:21] + connect rename_table_special_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_1.data, rename_table_special_mem_r1.data @[reg_alloc.rs 128:21] wire rename_0_src_2: Ty54 @[reg_alloc.rs 113:17] wire _bundle_literal_expr_8: Ty1 connect _bundle_literal_expr_8.value, tail(UInt<32>(0h0), 24) @@ -604,31 +628,31 @@ circuit reg_alloc: connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11 connect rename_0_src_2.data, _bundle_literal_expr_9 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_2.data, rename_table_normal_mem_r2.data @[reg_alloc.rs 129:21] - connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_2.data, rename_table_normal_mem_r2.data @[reg_alloc.rs 128:21] + connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_0_src_2.data, rename_table_special_mem_r2.data @[reg_alloc.rs 129:21] - wire rename_table_normal_0_dest0: Ty30 @[reg_alloc.rs 171:21] - connect rename_table_normal_mem_w3, rename_table_normal_0_dest0 @[reg_alloc.rs 174:17] + connect rename_table_special_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_0_src_2.data, rename_table_special_mem_r2.data @[reg_alloc.rs 128:21] + wire rename_table_normal_0_dest0: Ty30 @[reg_alloc.rs 170:21] + connect rename_table_normal_mem_w3, rename_table_normal_0_dest0 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_12: Ty55 connect _bundle_literal_expr_12.addr, UInt<0>(0h0) connect _bundle_literal_expr_12.en, UInt<1>(0h0) @@ -647,9 +671,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_0_dest0, _bundle_literal_expr_12 @[reg_alloc.rs 176:17] - wire rename_table_special_0_dest0: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w3, rename_table_special_0_dest0 @[reg_alloc.rs 174:17] + connect rename_table_normal_0_dest0, _bundle_literal_expr_12 @[reg_alloc.rs 175:17] + wire rename_table_special_0_dest0: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w3, rename_table_special_0_dest0 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_16: Ty55 connect _bundle_literal_expr_16.addr, UInt<0>(0h0) connect _bundle_literal_expr_16.en, UInt<1>(0h0) @@ -668,9 +692,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_dest0, _bundle_literal_expr_16 @[reg_alloc.rs 176:17] - wire rename_table_normal_0_dest1: Ty30 @[reg_alloc.rs 171:21] - connect rename_table_normal_mem_w4, rename_table_normal_0_dest1 @[reg_alloc.rs 174:17] + connect rename_table_special_0_dest0, _bundle_literal_expr_16 @[reg_alloc.rs 175:17] + wire rename_table_normal_0_dest1: Ty30 @[reg_alloc.rs 170:21] + connect rename_table_normal_mem_w4, rename_table_normal_0_dest1 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_20: Ty55 connect _bundle_literal_expr_20.addr, UInt<0>(0h0) connect _bundle_literal_expr_20.en, UInt<1>(0h0) @@ -689,9 +713,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_0_dest1, _bundle_literal_expr_20 @[reg_alloc.rs 176:17] - wire rename_table_special_0_dest1: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w4, rename_table_special_0_dest1 @[reg_alloc.rs 174:17] + connect rename_table_normal_0_dest1, _bundle_literal_expr_20 @[reg_alloc.rs 175:17] + wire rename_table_special_0_dest1: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w4, rename_table_special_0_dest1 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_24: Ty55 connect _bundle_literal_expr_24.addr, UInt<0>(0h0) connect _bundle_literal_expr_24.en, UInt<1>(0h0) @@ -710,9 +734,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_dest1, _bundle_literal_expr_24 @[reg_alloc.rs 176:17] - wire rename_table_special_0_flag0_rFE: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w5, rename_table_special_0_flag0_rFE @[reg_alloc.rs 174:17] + connect rename_table_special_0_dest1, _bundle_literal_expr_24 @[reg_alloc.rs 175:17] + wire rename_table_special_0_flag0_rFE: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w5, rename_table_special_0_flag0_rFE @[reg_alloc.rs 173:17] wire _bundle_literal_expr_28: Ty55 connect _bundle_literal_expr_28.addr, UInt<0>(0h0) connect _bundle_literal_expr_28.en, UInt<1>(0h0) @@ -731,9 +755,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_flag0_rFE, _bundle_literal_expr_28 @[reg_alloc.rs 176:17] - wire rename_table_special_0_flag1_rFF: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w6, rename_table_special_0_flag1_rFF @[reg_alloc.rs 174:17] + connect rename_table_special_0_flag0_rFE, _bundle_literal_expr_28 @[reg_alloc.rs 175:17] + wire rename_table_special_0_flag1_rFF: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w6, rename_table_special_0_flag1_rFF @[reg_alloc.rs 173:17] wire _bundle_literal_expr_32: Ty55 connect _bundle_literal_expr_32.addr, UInt<0>(0h0) connect _bundle_literal_expr_32.en, UInt<1>(0h0) @@ -752,78 +776,78 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_0_flag1_rFF, _bundle_literal_expr_32 @[reg_alloc.rs 176:17] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 190:9] + connect rename_table_special_0_flag1_rFF, _bundle_literal_expr_32 @[reg_alloc.rs 175:17] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 189:9] HdlNone: skip HdlSome(_match_arm_value): - wire unit_kind: Ty56 @[unit.rs 127:1] - match _match_arm_value.mop: @[unit.rs 127:1] + wire unit_kind: Ty56 @[unit.rs 129:1] + match _match_arm_value.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_1): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_2): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 127:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 129:1] LoadStore(_match_arm_value_3): - connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 127:1] - wire available_units_for_kind: UInt<1>[2] @[unit.rs 127:1] - match unit_kind: @[unit.rs 127:1] + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 129:1] + wire available_units_for_kind: UInt<1>[2] @[unit.rs 129:1] + match unit_kind: @[unit.rs 129:1] AluBranch: - connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 127:1] - connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 127:1] + connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 129:1] + connect available_units_for_kind[1], UInt<1>(0h1) @[unit.rs 129:1] L2RegisterFile: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 129:1] LoadStore: - connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units[0], available_units_for_kind @[reg_alloc.rs 191:13] - match renamed_mops_out_reg[0]: @[reg_alloc.rs 196:13] + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units[0], available_units_for_kind @[reg_alloc.rs 190:13] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 195:13] HdlNone: skip HdlSome(_match_arm_value_4): - wire dest_reg: Ty4 @[unit.rs 127:1] - match _match_arm_value.mop: @[unit.rs 127:1] + wire dest_reg: Ty4 @[unit.rs 129:1] + match _match_arm_value.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_5): - wire dest_reg_1: Ty4 @[instruction.rs 477:1] - match _match_arm_value_5: @[instruction.rs 477:1] + wire dest_reg_1: Ty4 @[instruction.rs 502:1] + match _match_arm_value_5: @[instruction.rs 502:1] AddSub(_match_arm_value_6): - connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_1, _match_arm_value_6.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_7): - connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_1, _match_arm_value_7.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_8): - connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg, dest_reg_1 @[unit.rs 127:1] + connect dest_reg_1, _match_arm_value_8.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg, dest_reg_1 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_9): - wire dest_reg_2: Ty4 @[instruction.rs 504:1] - match _match_arm_value_9: @[instruction.rs 504:1] + wire dest_reg_2: Ty4 @[instruction.rs 529:1] + match _match_arm_value_9: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_10): - connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 504:1] + connect dest_reg_2, _match_arm_value_10.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_11): - connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 504:1] - connect dest_reg, dest_reg_2 @[unit.rs 127:1] + connect dest_reg_2, _match_arm_value_11.common.dest @[instruction.rs 529:1] + connect dest_reg, dest_reg_2 @[unit.rs 129:1] LoadStore(_match_arm_value_12): - wire dest_reg_3: Ty4 @[instruction.rs 539:1] - match _match_arm_value_12: @[instruction.rs 539:1] + wire dest_reg_3: Ty4 @[instruction.rs 564:1] + match _match_arm_value_12: @[instruction.rs 564:1] Load(_match_arm_value_13): - connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 539:1] + connect dest_reg_3, _match_arm_value_13.dest @[instruction.rs 564:1] Store(_match_arm_value_14): - connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 539:1] - connect dest_reg, dest_reg_3 @[unit.rs 127:1] - wire mapped_regs: Ty51 @[unit.rs 127:1] - match _match_arm_value.mop: @[unit.rs 127:1] + connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 564:1] + connect dest_reg, dest_reg_3 @[unit.rs 129:1] + wire mapped_regs: Ty51 @[unit.rs 129:1] + match _match_arm_value.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_15): - wire mapped_regs_1: Ty46 @[instruction.rs 477:1] - match _match_arm_value_15: @[instruction.rs 477:1] + wire mapped_regs_1: Ty46 @[instruction.rs 502:1] + match _match_arm_value_15: @[instruction.rs 502:1] AddSub(_match_arm_value_16): wire _bundle_literal_expr_36: Ty1 connect _bundle_literal_expr_36.value, _match_arm_value_16.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_36 @[reg_alloc.rs 205:29] + connect rename_0_src_0.addr, _bundle_literal_expr_36 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_37: Ty1 connect _bundle_literal_expr_37.value, _match_arm_value_16.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_37 @[reg_alloc.rs 205:29] + connect rename_0_src_1.addr, _bundle_literal_expr_37 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_38: Ty1 connect _bundle_literal_expr_38.value, _match_arm_value_16.alu_common.common.src[2] - connect rename_0_src_2.addr, _bundle_literal_expr_38 @[reg_alloc.rs 205:29] + connect rename_0_src_2.addr, _bundle_literal_expr_38 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_39: Ty44 wire _bundle_literal_expr_40: Ty43 wire _bundle_literal_expr_41: Ty42 @@ -927,14 +951,14 @@ circuit reg_alloc: connect _bundle_literal_expr_39.invert_carry_in, _match_arm_value_16.invert_carry_in connect _bundle_literal_expr_39.invert_carry_out, _match_arm_value_16.invert_carry_out connect _bundle_literal_expr_39.add_pc, _match_arm_value_16.add_pc - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 477:1] + connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 502:1] AddSubI(_match_arm_value_17): wire _bundle_literal_expr_45: Ty1 connect _bundle_literal_expr_45.value, _match_arm_value_17.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 205:29] + connect rename_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_46: Ty1 connect _bundle_literal_expr_46.value, _match_arm_value_17.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_46 @[reg_alloc.rs 205:29] + connect rename_0_src_1.addr, _bundle_literal_expr_46 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_47: Ty44 wire _bundle_literal_expr_48: Ty43 wire _bundle_literal_expr_49: Ty42 @@ -1031,14 +1055,14 @@ circuit reg_alloc: connect _bundle_literal_expr_47.invert_carry_in, _match_arm_value_17.invert_carry_in connect _bundle_literal_expr_47.invert_carry_out, _match_arm_value_17.invert_carry_out connect _bundle_literal_expr_47.add_pc, _match_arm_value_17.add_pc - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 477:1] + connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 502:1] Logical(_match_arm_value_18): wire _bundle_literal_expr_54: Ty1 connect _bundle_literal_expr_54.value, _match_arm_value_18.alu_common.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_54 @[reg_alloc.rs 205:29] + connect rename_0_src_0.addr, _bundle_literal_expr_54 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_55: Ty1 connect _bundle_literal_expr_55.value, _match_arm_value_18.alu_common.common.src[1] - connect rename_0_src_1.addr, _bundle_literal_expr_55 @[reg_alloc.rs 205:29] + connect rename_0_src_1.addr, _bundle_literal_expr_55 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_56: Ty45 wire _bundle_literal_expr_57: Ty43 wire _bundle_literal_expr_58: Ty42 @@ -1132,11 +1156,11 @@ circuit reg_alloc: connect _bundle_literal_expr_57.output_integer_mode, _match_arm_value_18.alu_common.output_integer_mode connect _bundle_literal_expr_56.alu_common, _bundle_literal_expr_57 connect _bundle_literal_expr_56.lut, _match_arm_value_18.lut - connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 477:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 127:1] + connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 502:1] + connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_19): - wire mapped_regs_2: Ty49 @[instruction.rs 504:1] - match _match_arm_value_19: @[instruction.rs 504:1] + wire mapped_regs_2: Ty49 @[instruction.rs 529:1] + match _match_arm_value_19: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_20): wire _bundle_literal_expr_63: Ty48 wire _bundle_literal_expr_64: Ty47 @@ -1201,11 +1225,11 @@ circuit reg_alloc: invalidate _bundle_literal_expr_68 connect _bundle_literal_expr_64._phantom, _bundle_literal_expr_68 connect _bundle_literal_expr_63.common, _bundle_literal_expr_64 - connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 504:1] + connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_21): wire _bundle_literal_expr_69: Ty1 connect _bundle_literal_expr_69.value, _match_arm_value_21.common.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_69 @[reg_alloc.rs 205:29] + connect rename_0_src_0.addr, _bundle_literal_expr_69 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_70: Ty48 wire _bundle_literal_expr_71: Ty47 connect _bundle_literal_expr_71.prefix_pad, _match_arm_value_21.common.prefix_pad @@ -1276,11 +1300,11 @@ circuit reg_alloc: invalidate _bundle_literal_expr_75 connect _bundle_literal_expr_71._phantom, _bundle_literal_expr_75 connect _bundle_literal_expr_70.common, _bundle_literal_expr_71 - connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 504:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 127:1] + connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 529:1] + connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 129:1] LoadStore(_match_arm_value_22): - wire mapped_regs_3: Ty50 @[instruction.rs 539:1] - match _match_arm_value_22: @[instruction.rs 539:1] + wire mapped_regs_3: Ty50 @[instruction.rs 564:1] + match _match_arm_value_22: @[instruction.rs 564:1] Load(_match_arm_value_23): wire _bundle_literal_expr_76: Ty47 connect _bundle_literal_expr_76.prefix_pad, _match_arm_value_23.prefix_pad @@ -1343,11 +1367,11 @@ circuit reg_alloc: wire _bundle_literal_expr_80: Ty2 invalidate _bundle_literal_expr_80 connect _bundle_literal_expr_76._phantom, _bundle_literal_expr_80 - connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 539:1] + connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 564:1] Store(_match_arm_value_24): wire _bundle_literal_expr_81: Ty1 connect _bundle_literal_expr_81.value, _match_arm_value_24.src[0] - connect rename_0_src_0.addr, _bundle_literal_expr_81 @[reg_alloc.rs 205:29] + connect rename_0_src_0.addr, _bundle_literal_expr_81 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_82: Ty47 connect _bundle_literal_expr_82.prefix_pad, _match_arm_value_24.prefix_pad connect _bundle_literal_expr_82.dest, _match_arm_value_4.unit_out_reg @@ -1416,99 +1440,99 @@ circuit reg_alloc: wire _bundle_literal_expr_86: Ty2 invalidate _bundle_literal_expr_86 connect _bundle_literal_expr_82._phantom, _bundle_literal_expr_86 - connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 539:1] - connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 127:1] - connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs) @[reg_alloc.rs 198:17] - wire flag_reg: Ty1 @[instruction.rs 806:32] + connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 564:1] + connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 129:1] + connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs) @[reg_alloc.rs 197:17] + wire flag_reg: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_87: Ty1 connect _bundle_literal_expr_87.value, tail(UInt<32>(0h0), 24) - connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 807:17] - match dest_reg.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 832:17] + match dest_reg.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_25): wire _bundle_literal_expr_88: Ty1 connect _bundle_literal_expr_88.value, tail(UInt<32>(0hFE), 24) - connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 811:21] - wire flag_reg_1: Ty1 @[instruction.rs 806:32] + connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 836:21] + wire flag_reg_1: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_89: Ty1 connect _bundle_literal_expr_89.value, tail(UInt<32>(0h0), 24) - connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 807:17] - match dest_reg.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 832:17] + match dest_reg.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_26): wire _bundle_literal_expr_90: Ty1 connect _bundle_literal_expr_90.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 811:21] - when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25] - connect rename_table_normal_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 836:21] + when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] + connect rename_table_normal_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33] - connect rename_table_normal_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect rename_table_normal_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] + connect rename_table_normal_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33] - connect rename_table_special_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25] - connect rename_table_normal_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect rename_table_special_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] + connect rename_table_special_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] + connect rename_table_normal_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33] - connect rename_table_normal_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect rename_table_normal_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] + connect rename_table_normal_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33] - connect rename_table_special_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(flag_reg.value, UInt<32>(0hFE)), lt(flag_reg.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_0_flag0_rFE.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect rename_table_special_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] + connect rename_table_special_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(flag_reg.value, UInt<32>(0hFE)), lt(flag_reg.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_0_flag0_rFE.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<32> - connect rename_table_special_0_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 232:33] - connect rename_table_special_0_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(flag_reg_1.value, UInt<32>(0hFE)), lt(flag_reg_1.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_0_flag1_rFF.data, _match_arm_value_4 @[reg_alloc.rs 230:29] + connect rename_table_special_0_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 231:33] + connect rename_table_special_0_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(flag_reg_1.value, UInt<32>(0hFE)), lt(flag_reg_1.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_0_flag1_rFF.data, _match_arm_value_4 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<32> - connect rename_table_special_0_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 232:33] - connect rename_table_special_0_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - wire selected_unit_index_leaf_0_0: Ty41 @[reg_alloc.rs 250:25] - connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21] - wire unit_index_0_0: UInt<2> @[reg_alloc.rs 259:25] + connect rename_table_special_0_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 231:33] + connect rename_table_special_0_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + wire selected_unit_index_leaf_0_0: Ty41 @[reg_alloc.rs 249:25] + connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] + wire unit_index_0_0: UInt<2> @[reg_alloc.rs 258:25] ; connect different types: ; lhs: UInt<2> ; rhs: UInt<64> - connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 262:21] - when available_units[0][0]: @[reg_alloc.rs 264:21] - connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 265:25] - wire selected_unit_index_leaf_0_1: Ty41 @[reg_alloc.rs 250:25] - connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21] - wire unit_index_0_1: UInt<2> @[reg_alloc.rs 259:25] + connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 261:21] + when available_units[0][0]: @[reg_alloc.rs 263:21] + connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 264:25] + wire selected_unit_index_leaf_0_1: Ty41 @[reg_alloc.rs 249:25] + connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] + wire unit_index_0_1: UInt<2> @[reg_alloc.rs 258:25] ; connect different types: ; lhs: UInt<2> ; rhs: UInt<64> - connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 262:21] - when available_units[0][1]: @[reg_alloc.rs 264:21] - connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 265:25] - wire selected_unit_index_node_0_0: Ty41 @[reg_alloc.rs 272:25] - connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 276:21] - match selected_unit_index_leaf_0_0: @[reg_alloc.rs 278:21] + connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 261:21] + when available_units[0][1]: @[reg_alloc.rs 263:21] + connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 264:25] + wire selected_unit_index_node_0_0: Ty41 @[reg_alloc.rs 271:25] + connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 275:21] + match selected_unit_index_leaf_0_0: @[reg_alloc.rs 277:21] HdlNone: - connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 279:25] + connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 278:25] HdlSome(_match_arm_value_27): skip - connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 242:9] + connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 241:9] connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 92:9] wire _array_literal_expr_37: UInt<1>[2] connect _array_literal_expr_37[0], UInt<1>(0h0) @@ -1527,157 +1551,157 @@ circuit reg_alloc: connect _bundle_literal_expr_94.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_92.unit_out_reg, _bundle_literal_expr_94 connect rename_1_src_0.data, _bundle_literal_expr_92 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r5.addr, sub(rename_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_0.data, rename_table_normal_mem_r5.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_normal_mem_r5.addr, sub(rename_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_0.data, rename_table_normal_mem_r5.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_28): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_29): - wire dest_reg_4: Ty4 @[unit.rs 127:1] - match _match_arm_value_28.mop: @[unit.rs 127:1] + wire dest_reg_4: Ty4 @[unit.rs 129:1] + match _match_arm_value_28.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_30): - wire dest_reg_5: Ty4 @[instruction.rs 477:1] - match _match_arm_value_30: @[instruction.rs 477:1] + wire dest_reg_5: Ty4 @[instruction.rs 502:1] + match _match_arm_value_30: @[instruction.rs 502:1] AddSub(_match_arm_value_31): - connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_32): - connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_33): - connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_4, dest_reg_5 @[unit.rs 127:1] + connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_4, dest_reg_5 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_34): - wire dest_reg_6: Ty4 @[instruction.rs 504:1] - match _match_arm_value_34: @[instruction.rs 504:1] + wire dest_reg_6: Ty4 @[instruction.rs 529:1] + match _match_arm_value_34: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_35): - connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 504:1] + connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_36): - connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 504:1] - connect dest_reg_4, dest_reg_6 @[unit.rs 127:1] + connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 529:1] + connect dest_reg_4, dest_reg_6 @[unit.rs 129:1] LoadStore(_match_arm_value_37): - wire dest_reg_7: Ty4 @[instruction.rs 539:1] - match _match_arm_value_37: @[instruction.rs 539:1] + wire dest_reg_7: Ty4 @[instruction.rs 564:1] + match _match_arm_value_37: @[instruction.rs 564:1] Load(_match_arm_value_38): - connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 539:1] + connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 564:1] Store(_match_arm_value_39): - connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 539:1] - connect dest_reg_4, dest_reg_7 @[unit.rs 127:1] - wire flag_reg_2: Ty1 @[instruction.rs 806:32] + connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 564:1] + connect dest_reg_4, dest_reg_7 @[unit.rs 129:1] + wire flag_reg_2: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_95: Ty1 connect _bundle_literal_expr_95.value, tail(UInt<32>(0h0), 24) - connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 807:17] - match dest_reg_4.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 832:17] + match dest_reg_4.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_40): wire _bundle_literal_expr_96: Ty1 connect _bundle_literal_expr_96.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 811:21] - wire flag_reg_3: Ty1 @[instruction.rs 806:32] + connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 836:21] + wire flag_reg_3: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_97: Ty1 connect _bundle_literal_expr_97.value, tail(UInt<32>(0h0), 24) - connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 807:17] - match dest_reg_4.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 832:17] + match dest_reg_4.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_41): wire _bundle_literal_expr_98: Ty1 connect _bundle_literal_expr_98.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 811:21] - when eq(dest_reg_4.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 147:45] - when eq(dest_reg_4.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 147:45] - connect rename_table_special_mem_r7.clk, cd.clk @[reg_alloc.rs 121:17] + connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 836:21] + when eq(dest_reg_4.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 146:45] + when eq(dest_reg_4.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 146:45] + connect rename_table_special_mem_r7.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r7.addr, sub(rename_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_0.data, rename_table_special_mem_r7.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_special_mem_r7.addr, sub(rename_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_0.data, rename_table_special_mem_r7.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_42): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_43): - wire dest_reg_8: Ty4 @[unit.rs 127:1] - match _match_arm_value_42.mop: @[unit.rs 127:1] + wire dest_reg_8: Ty4 @[unit.rs 129:1] + match _match_arm_value_42.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_44): - wire dest_reg_9: Ty4 @[instruction.rs 477:1] - match _match_arm_value_44: @[instruction.rs 477:1] + wire dest_reg_9: Ty4 @[instruction.rs 502:1] + match _match_arm_value_44: @[instruction.rs 502:1] AddSub(_match_arm_value_45): - connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_46): - connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_47): - connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_8, dest_reg_9 @[unit.rs 127:1] + connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_8, dest_reg_9 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_48): - wire dest_reg_10: Ty4 @[instruction.rs 504:1] - match _match_arm_value_48: @[instruction.rs 504:1] + wire dest_reg_10: Ty4 @[instruction.rs 529:1] + match _match_arm_value_48: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_49): - connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 504:1] + connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_50): - connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 504:1] - connect dest_reg_8, dest_reg_10 @[unit.rs 127:1] + connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 529:1] + connect dest_reg_8, dest_reg_10 @[unit.rs 129:1] LoadStore(_match_arm_value_51): - wire dest_reg_11: Ty4 @[instruction.rs 539:1] - match _match_arm_value_51: @[instruction.rs 539:1] + wire dest_reg_11: Ty4 @[instruction.rs 564:1] + match _match_arm_value_51: @[instruction.rs 564:1] Load(_match_arm_value_52): - connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 539:1] + connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 564:1] Store(_match_arm_value_53): - connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 539:1] - connect dest_reg_8, dest_reg_11 @[unit.rs 127:1] - wire flag_reg_4: Ty1 @[instruction.rs 806:32] + connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 564:1] + connect dest_reg_8, dest_reg_11 @[unit.rs 129:1] + wire flag_reg_4: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_99: Ty1 connect _bundle_literal_expr_99.value, tail(UInt<32>(0h0), 24) - connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 807:17] - match dest_reg_8.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 832:17] + match dest_reg_8.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_54): wire _bundle_literal_expr_100: Ty1 connect _bundle_literal_expr_100.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 811:21] - wire flag_reg_5: Ty1 @[instruction.rs 806:32] + connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 836:21] + wire flag_reg_5: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_101: Ty1 connect _bundle_literal_expr_101.value, tail(UInt<32>(0h0), 24) - connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 807:17] - match dest_reg_8.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 832:17] + match dest_reg_8.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_55): wire _bundle_literal_expr_102: Ty1 connect _bundle_literal_expr_102.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 811:21] - when eq(dest_reg_8.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45] - when eq(dest_reg_8.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45] - when eq(flag_reg_4.value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45] - when eq(flag_reg_5.value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45] + connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 836:21] + when eq(dest_reg_8.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] + when eq(dest_reg_8.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] + when eq(flag_reg_4.value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] + when eq(flag_reg_5.value, rename_1_src_0.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 146:45] wire rename_1_src_1: Ty54 @[reg_alloc.rs 113:17] wire _bundle_literal_expr_103: Ty1 connect _bundle_literal_expr_103.value, tail(UInt<32>(0h0), 24) @@ -1690,157 +1714,157 @@ circuit reg_alloc: connect _bundle_literal_expr_106.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_104.unit_out_reg, _bundle_literal_expr_106 connect rename_1_src_1.data, _bundle_literal_expr_104 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r6.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r6.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r6.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r6.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r6.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r6.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r6.addr, sub(rename_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r6.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_1.data, rename_table_normal_mem_r6.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_normal_mem_r6.addr, sub(rename_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r6.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_1.data, rename_table_normal_mem_r6.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_56): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_57): - wire dest_reg_12: Ty4 @[unit.rs 127:1] - match _match_arm_value_56.mop: @[unit.rs 127:1] + wire dest_reg_12: Ty4 @[unit.rs 129:1] + match _match_arm_value_56.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_58): - wire dest_reg_13: Ty4 @[instruction.rs 477:1] - match _match_arm_value_58: @[instruction.rs 477:1] + wire dest_reg_13: Ty4 @[instruction.rs 502:1] + match _match_arm_value_58: @[instruction.rs 502:1] AddSub(_match_arm_value_59): - connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_60): - connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_61): - connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_12, dest_reg_13 @[unit.rs 127:1] + connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_12, dest_reg_13 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_62): - wire dest_reg_14: Ty4 @[instruction.rs 504:1] - match _match_arm_value_62: @[instruction.rs 504:1] + wire dest_reg_14: Ty4 @[instruction.rs 529:1] + match _match_arm_value_62: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_63): - connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 504:1] + connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_64): - connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 504:1] - connect dest_reg_12, dest_reg_14 @[unit.rs 127:1] + connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 529:1] + connect dest_reg_12, dest_reg_14 @[unit.rs 129:1] LoadStore(_match_arm_value_65): - wire dest_reg_15: Ty4 @[instruction.rs 539:1] - match _match_arm_value_65: @[instruction.rs 539:1] + wire dest_reg_15: Ty4 @[instruction.rs 564:1] + match _match_arm_value_65: @[instruction.rs 564:1] Load(_match_arm_value_66): - connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 539:1] + connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 564:1] Store(_match_arm_value_67): - connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 539:1] - connect dest_reg_12, dest_reg_15 @[unit.rs 127:1] - wire flag_reg_6: Ty1 @[instruction.rs 806:32] + connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 564:1] + connect dest_reg_12, dest_reg_15 @[unit.rs 129:1] + wire flag_reg_6: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_107: Ty1 connect _bundle_literal_expr_107.value, tail(UInt<32>(0h0), 24) - connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 807:17] - match dest_reg_12.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 832:17] + match dest_reg_12.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_68): wire _bundle_literal_expr_108: Ty1 connect _bundle_literal_expr_108.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 811:21] - wire flag_reg_7: Ty1 @[instruction.rs 806:32] + connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 836:21] + wire flag_reg_7: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_109: Ty1 connect _bundle_literal_expr_109.value, tail(UInt<32>(0h0), 24) - connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 807:17] - match dest_reg_12.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 832:17] + match dest_reg_12.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_69): wire _bundle_literal_expr_110: Ty1 connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 811:21] - when eq(dest_reg_12.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 147:45] - when eq(dest_reg_12.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 147:45] - connect rename_table_special_mem_r8.clk, cd.clk @[reg_alloc.rs 121:17] + connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 836:21] + when eq(dest_reg_12.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 146:45] + when eq(dest_reg_12.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 146:45] + connect rename_table_special_mem_r8.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r8.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r8.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r8.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r8.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r8.addr, sub(rename_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r8.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_1.data, rename_table_special_mem_r8.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_special_mem_r8.addr, sub(rename_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r8.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_1.data, rename_table_special_mem_r8.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_70): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_71): - wire dest_reg_16: Ty4 @[unit.rs 127:1] - match _match_arm_value_70.mop: @[unit.rs 127:1] + wire dest_reg_16: Ty4 @[unit.rs 129:1] + match _match_arm_value_70.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_72): - wire dest_reg_17: Ty4 @[instruction.rs 477:1] - match _match_arm_value_72: @[instruction.rs 477:1] + wire dest_reg_17: Ty4 @[instruction.rs 502:1] + match _match_arm_value_72: @[instruction.rs 502:1] AddSub(_match_arm_value_73): - connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_74): - connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_75): - connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_16, dest_reg_17 @[unit.rs 127:1] + connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_16, dest_reg_17 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_76): - wire dest_reg_18: Ty4 @[instruction.rs 504:1] - match _match_arm_value_76: @[instruction.rs 504:1] + wire dest_reg_18: Ty4 @[instruction.rs 529:1] + match _match_arm_value_76: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_77): - connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 504:1] + connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_78): - connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 504:1] - connect dest_reg_16, dest_reg_18 @[unit.rs 127:1] + connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 529:1] + connect dest_reg_16, dest_reg_18 @[unit.rs 129:1] LoadStore(_match_arm_value_79): - wire dest_reg_19: Ty4 @[instruction.rs 539:1] - match _match_arm_value_79: @[instruction.rs 539:1] + wire dest_reg_19: Ty4 @[instruction.rs 564:1] + match _match_arm_value_79: @[instruction.rs 564:1] Load(_match_arm_value_80): - connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 539:1] + connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 564:1] Store(_match_arm_value_81): - connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 539:1] - connect dest_reg_16, dest_reg_19 @[unit.rs 127:1] - wire flag_reg_8: Ty1 @[instruction.rs 806:32] + connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 564:1] + connect dest_reg_16, dest_reg_19 @[unit.rs 129:1] + wire flag_reg_8: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_111: Ty1 connect _bundle_literal_expr_111.value, tail(UInt<32>(0h0), 24) - connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 807:17] - match dest_reg_16.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 832:17] + match dest_reg_16.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_82): wire _bundle_literal_expr_112: Ty1 connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 811:21] - wire flag_reg_9: Ty1 @[instruction.rs 806:32] + connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 836:21] + wire flag_reg_9: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_113: Ty1 connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24) - connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 807:17] - match dest_reg_16.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 832:17] + match dest_reg_16.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_83): wire _bundle_literal_expr_114: Ty1 connect _bundle_literal_expr_114.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 811:21] - when eq(dest_reg_16.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45] - when eq(dest_reg_16.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45] - when eq(flag_reg_8.value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45] - when eq(flag_reg_9.value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45] + connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 836:21] + when eq(dest_reg_16.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] + when eq(dest_reg_16.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] + when eq(flag_reg_8.value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] + when eq(flag_reg_9.value, rename_1_src_1.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 146:45] wire rename_1_src_2: Ty54 @[reg_alloc.rs 113:17] wire _bundle_literal_expr_115: Ty1 connect _bundle_literal_expr_115.value, tail(UInt<32>(0h0), 24) @@ -1853,159 +1877,159 @@ circuit reg_alloc: connect _bundle_literal_expr_118.value, tail(UInt<8>(0h0), 4) connect _bundle_literal_expr_116.unit_out_reg, _bundle_literal_expr_118 connect rename_1_src_2.data, _bundle_literal_expr_116 @[reg_alloc.rs 117:13] - connect rename_table_normal_mem_r7.clk, cd.clk @[reg_alloc.rs 121:17] - connect rename_table_normal_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_normal_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17] + connect rename_table_normal_mem_r7.clk, cd.clk @[reg_alloc.rs 120:17] + connect rename_table_normal_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_normal_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_mem_r7.addr, sub(rename_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21] - connect rename_table_normal_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_2.data, rename_table_normal_mem_r7.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_normal_mem_r7.addr, sub(rename_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 126:21] + connect rename_table_normal_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_2.data, rename_table_normal_mem_r7.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_84): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_85): - wire dest_reg_20: Ty4 @[unit.rs 127:1] - match _match_arm_value_84.mop: @[unit.rs 127:1] + wire dest_reg_20: Ty4 @[unit.rs 129:1] + match _match_arm_value_84.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_86): - wire dest_reg_21: Ty4 @[instruction.rs 477:1] - match _match_arm_value_86: @[instruction.rs 477:1] + wire dest_reg_21: Ty4 @[instruction.rs 502:1] + match _match_arm_value_86: @[instruction.rs 502:1] AddSub(_match_arm_value_87): - connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_88): - connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_89): - connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_20, dest_reg_21 @[unit.rs 127:1] + connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_20, dest_reg_21 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_90): - wire dest_reg_22: Ty4 @[instruction.rs 504:1] - match _match_arm_value_90: @[instruction.rs 504:1] + wire dest_reg_22: Ty4 @[instruction.rs 529:1] + match _match_arm_value_90: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_91): - connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 504:1] + connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_92): - connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 504:1] - connect dest_reg_20, dest_reg_22 @[unit.rs 127:1] + connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 529:1] + connect dest_reg_20, dest_reg_22 @[unit.rs 129:1] LoadStore(_match_arm_value_93): - wire dest_reg_23: Ty4 @[instruction.rs 539:1] - match _match_arm_value_93: @[instruction.rs 539:1] + wire dest_reg_23: Ty4 @[instruction.rs 564:1] + match _match_arm_value_93: @[instruction.rs 564:1] Load(_match_arm_value_94): - connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 539:1] + connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 564:1] Store(_match_arm_value_95): - connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 539:1] - connect dest_reg_20, dest_reg_23 @[unit.rs 127:1] - wire flag_reg_10: Ty1 @[instruction.rs 806:32] + connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 564:1] + connect dest_reg_20, dest_reg_23 @[unit.rs 129:1] + wire flag_reg_10: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_119: Ty1 connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24) - connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 807:17] - match dest_reg_20.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 832:17] + match dest_reg_20.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_96): wire _bundle_literal_expr_120: Ty1 connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 811:21] - wire flag_reg_11: Ty1 @[instruction.rs 806:32] + connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 836:21] + wire flag_reg_11: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_121: Ty1 connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24) - connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 807:17] - match dest_reg_20.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 832:17] + match dest_reg_20.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_97): wire _bundle_literal_expr_122: Ty1 connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 811:21] - when eq(dest_reg_20.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 147:45] - when eq(dest_reg_20.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 147:45] - connect rename_table_special_mem_r9.clk, cd.clk @[reg_alloc.rs 121:17] + connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 836:21] + when eq(dest_reg_20.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 146:45] + when eq(dest_reg_20.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 146:45] + connect rename_table_special_mem_r9.clk, cd.clk @[reg_alloc.rs 120:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<8> - connect rename_table_special_mem_r9.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17] - connect rename_table_special_mem_r9.en, UInt<1>(0h0) @[reg_alloc.rs 123:17] - when and(geq(rename_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17] + connect rename_table_special_mem_r9.addr, UInt<8>(0h0) @[reg_alloc.rs 121:17] + connect rename_table_special_mem_r9.en, UInt<1>(0h0) @[reg_alloc.rs 122:17] + when and(geq(rename_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 125:17] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_mem_r9.addr, sub(rename_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21] - connect rename_table_special_mem_r9.en, UInt<1>(0h1) @[reg_alloc.rs 128:21] - connect rename_1_src_2.data, rename_table_special_mem_r9.data @[reg_alloc.rs 129:21] - match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25] + connect rename_table_special_mem_r9.addr, sub(rename_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 126:21] + connect rename_table_special_mem_r9.en, UInt<1>(0h1) @[reg_alloc.rs 127:21] + connect rename_1_src_2.data, rename_table_special_mem_r9.data @[reg_alloc.rs 128:21] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 131:25] HdlNone: skip HdlSome(_match_arm_value_98): - match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29] + match renamed_mops_out_reg[0]: @[reg_alloc.rs 135:29] HdlNone: skip HdlSome(_match_arm_value_99): - wire dest_reg_24: Ty4 @[unit.rs 127:1] - match _match_arm_value_98.mop: @[unit.rs 127:1] + wire dest_reg_24: Ty4 @[unit.rs 129:1] + match _match_arm_value_98.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_100): - wire dest_reg_25: Ty4 @[instruction.rs 477:1] - match _match_arm_value_100: @[instruction.rs 477:1] + wire dest_reg_25: Ty4 @[instruction.rs 502:1] + match _match_arm_value_100: @[instruction.rs 502:1] AddSub(_match_arm_value_101): - connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_102): - connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_103): - connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_24, dest_reg_25 @[unit.rs 127:1] + connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_24, dest_reg_25 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_104): - wire dest_reg_26: Ty4 @[instruction.rs 504:1] - match _match_arm_value_104: @[instruction.rs 504:1] + wire dest_reg_26: Ty4 @[instruction.rs 529:1] + match _match_arm_value_104: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_105): - connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 504:1] + connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_106): - connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 504:1] - connect dest_reg_24, dest_reg_26 @[unit.rs 127:1] + connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 529:1] + connect dest_reg_24, dest_reg_26 @[unit.rs 129:1] LoadStore(_match_arm_value_107): - wire dest_reg_27: Ty4 @[instruction.rs 539:1] - match _match_arm_value_107: @[instruction.rs 539:1] + wire dest_reg_27: Ty4 @[instruction.rs 564:1] + match _match_arm_value_107: @[instruction.rs 564:1] Load(_match_arm_value_108): - connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 539:1] + connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 564:1] Store(_match_arm_value_109): - connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 539:1] - connect dest_reg_24, dest_reg_27 @[unit.rs 127:1] - wire flag_reg_12: Ty1 @[instruction.rs 806:32] + connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 564:1] + connect dest_reg_24, dest_reg_27 @[unit.rs 129:1] + wire flag_reg_12: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_123: Ty1 connect _bundle_literal_expr_123.value, tail(UInt<32>(0h0), 24) - connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 807:17] - match dest_reg_24.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 832:17] + match dest_reg_24.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_110): wire _bundle_literal_expr_124: Ty1 connect _bundle_literal_expr_124.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 811:21] - wire flag_reg_13: Ty1 @[instruction.rs 806:32] + connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 836:21] + wire flag_reg_13: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_125: Ty1 connect _bundle_literal_expr_125.value, tail(UInt<32>(0h0), 24) - connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 807:17] - match dest_reg_24.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 832:17] + match dest_reg_24.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_111): wire _bundle_literal_expr_126: Ty1 connect _bundle_literal_expr_126.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 811:21] - when eq(dest_reg_24.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45] - when eq(dest_reg_24.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45] - when eq(flag_reg_12.value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45] - when eq(flag_reg_13.value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41] - connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45] - wire rename_table_normal_1_dest0: Ty30 @[reg_alloc.rs 171:21] - connect rename_table_normal_mem_w8, rename_table_normal_1_dest0 @[reg_alloc.rs 174:17] + connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 836:21] + when eq(dest_reg_24.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] + when eq(dest_reg_24.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] + when eq(flag_reg_12.value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] + when eq(flag_reg_13.value, rename_1_src_2.addr.value): @[reg_alloc.rs 145:41] + connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 146:45] + wire rename_table_normal_1_dest0: Ty30 @[reg_alloc.rs 170:21] + connect rename_table_normal_mem_w8, rename_table_normal_1_dest0 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_127: Ty55 connect _bundle_literal_expr_127.addr, UInt<0>(0h0) connect _bundle_literal_expr_127.en, UInt<1>(0h0) @@ -2024,9 +2048,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_1_dest0, _bundle_literal_expr_127 @[reg_alloc.rs 176:17] - wire rename_table_special_1_dest0: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w10, rename_table_special_1_dest0 @[reg_alloc.rs 174:17] + connect rename_table_normal_1_dest0, _bundle_literal_expr_127 @[reg_alloc.rs 175:17] + wire rename_table_special_1_dest0: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w10, rename_table_special_1_dest0 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_131: Ty55 connect _bundle_literal_expr_131.addr, UInt<0>(0h0) connect _bundle_literal_expr_131.en, UInt<1>(0h0) @@ -2045,9 +2069,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_dest0, _bundle_literal_expr_131 @[reg_alloc.rs 176:17] - wire rename_table_normal_1_dest1: Ty30 @[reg_alloc.rs 171:21] - connect rename_table_normal_mem_w9, rename_table_normal_1_dest1 @[reg_alloc.rs 174:17] + connect rename_table_special_1_dest0, _bundle_literal_expr_131 @[reg_alloc.rs 175:17] + wire rename_table_normal_1_dest1: Ty30 @[reg_alloc.rs 170:21] + connect rename_table_normal_mem_w9, rename_table_normal_1_dest1 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_135: Ty55 connect _bundle_literal_expr_135.addr, UInt<0>(0h0) connect _bundle_literal_expr_135.en, UInt<1>(0h0) @@ -2066,9 +2090,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_normal_1_dest1, _bundle_literal_expr_135 @[reg_alloc.rs 176:17] - wire rename_table_special_1_dest1: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w11, rename_table_special_1_dest1 @[reg_alloc.rs 174:17] + connect rename_table_normal_1_dest1, _bundle_literal_expr_135 @[reg_alloc.rs 175:17] + wire rename_table_special_1_dest1: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w11, rename_table_special_1_dest1 @[reg_alloc.rs 173:17] wire _bundle_literal_expr_139: Ty55 connect _bundle_literal_expr_139.addr, UInt<0>(0h0) connect _bundle_literal_expr_139.en, UInt<1>(0h0) @@ -2087,9 +2111,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_dest1, _bundle_literal_expr_139 @[reg_alloc.rs 176:17] - wire rename_table_special_1_flag0_rFE: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w12, rename_table_special_1_flag0_rFE @[reg_alloc.rs 174:17] + connect rename_table_special_1_dest1, _bundle_literal_expr_139 @[reg_alloc.rs 175:17] + wire rename_table_special_1_flag0_rFE: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w12, rename_table_special_1_flag0_rFE @[reg_alloc.rs 173:17] wire _bundle_literal_expr_143: Ty55 connect _bundle_literal_expr_143.addr, UInt<0>(0h0) connect _bundle_literal_expr_143.en, UInt<1>(0h0) @@ -2108,9 +2132,9 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_flag0_rFE, _bundle_literal_expr_143 @[reg_alloc.rs 176:17] - wire rename_table_special_1_flag1_rFF: Ty36 @[reg_alloc.rs 171:21] - connect rename_table_special_mem_w13, rename_table_special_1_flag1_rFF @[reg_alloc.rs 174:17] + connect rename_table_special_1_flag0_rFE, _bundle_literal_expr_143 @[reg_alloc.rs 175:17] + wire rename_table_special_1_flag1_rFF: Ty36 @[reg_alloc.rs 170:21] + connect rename_table_special_mem_w13, rename_table_special_1_flag1_rFF @[reg_alloc.rs 173:17] wire _bundle_literal_expr_147: Ty55 connect _bundle_literal_expr_147.addr, UInt<0>(0h0) connect _bundle_literal_expr_147.en, UInt<1>(0h0) @@ -2129,78 +2153,78 @@ circuit reg_alloc: ; connect different types: ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}} - connect rename_table_special_1_flag1_rFF, _bundle_literal_expr_147 @[reg_alloc.rs 176:17] - match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 190:9] + connect rename_table_special_1_flag1_rFF, _bundle_literal_expr_147 @[reg_alloc.rs 175:17] + match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 189:9] HdlNone: skip HdlSome(_match_arm_value_112): - wire unit_kind_1: Ty56 @[unit.rs 127:1] - match _match_arm_value_112.mop: @[unit.rs 127:1] + wire unit_kind_1: Ty56 @[unit.rs 129:1] + match _match_arm_value_112.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_113): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1] + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_114): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 127:1] + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 129:1] LoadStore(_match_arm_value_115): - connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 127:1] - wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 127:1] - match unit_kind_1: @[unit.rs 127:1] + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 129:1] + wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 129:1] + match unit_kind_1: @[unit.rs 129:1] AluBranch: - connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 127:1] - connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 127:1] + connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 129:1] + connect available_units_for_kind_1[1], UInt<1>(0h1) @[unit.rs 129:1] L2RegisterFile: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 127:1] + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 129:1] LoadStore: - connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 127:1] - connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 191:13] - match renamed_mops_out_reg[1]: @[reg_alloc.rs 196:13] + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 129:1] + connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 190:13] + match renamed_mops_out_reg[1]: @[reg_alloc.rs 195:13] HdlNone: skip HdlSome(_match_arm_value_116): - wire dest_reg_28: Ty4 @[unit.rs 127:1] - match _match_arm_value_112.mop: @[unit.rs 127:1] + wire dest_reg_28: Ty4 @[unit.rs 129:1] + match _match_arm_value_112.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_117): - wire dest_reg_29: Ty4 @[instruction.rs 477:1] - match _match_arm_value_117: @[instruction.rs 477:1] + wire dest_reg_29: Ty4 @[instruction.rs 502:1] + match _match_arm_value_117: @[instruction.rs 502:1] AddSub(_match_arm_value_118): - connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 502:1] AddSubI(_match_arm_value_119): - connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 477:1] + connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 502:1] Logical(_match_arm_value_120): - connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 477:1] - connect dest_reg_28, dest_reg_29 @[unit.rs 127:1] + connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 502:1] + connect dest_reg_28, dest_reg_29 @[unit.rs 129:1] L2RegisterFile(_match_arm_value_121): - wire dest_reg_30: Ty4 @[instruction.rs 504:1] - match _match_arm_value_121: @[instruction.rs 504:1] + wire dest_reg_30: Ty4 @[instruction.rs 529:1] + match _match_arm_value_121: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_122): - connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 504:1] + connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_123): - connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 504:1] - connect dest_reg_28, dest_reg_30 @[unit.rs 127:1] + connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 529:1] + connect dest_reg_28, dest_reg_30 @[unit.rs 129:1] LoadStore(_match_arm_value_124): - wire dest_reg_31: Ty4 @[instruction.rs 539:1] - match _match_arm_value_124: @[instruction.rs 539:1] + wire dest_reg_31: Ty4 @[instruction.rs 564:1] + match _match_arm_value_124: @[instruction.rs 564:1] Load(_match_arm_value_125): - connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 539:1] + connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 564:1] Store(_match_arm_value_126): - connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 539:1] - connect dest_reg_28, dest_reg_31 @[unit.rs 127:1] - wire mapped_regs_4: Ty51 @[unit.rs 127:1] - match _match_arm_value_112.mop: @[unit.rs 127:1] + connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 564:1] + connect dest_reg_28, dest_reg_31 @[unit.rs 129:1] + wire mapped_regs_4: Ty51 @[unit.rs 129:1] + match _match_arm_value_112.mop: @[unit.rs 129:1] AluBranch(_match_arm_value_127): - wire mapped_regs_5: Ty46 @[instruction.rs 477:1] - match _match_arm_value_127: @[instruction.rs 477:1] + wire mapped_regs_5: Ty46 @[instruction.rs 502:1] + match _match_arm_value_127: @[instruction.rs 502:1] AddSub(_match_arm_value_128): wire _bundle_literal_expr_151: Ty1 connect _bundle_literal_expr_151.value, _match_arm_value_128.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_151 @[reg_alloc.rs 205:29] + connect rename_1_src_0.addr, _bundle_literal_expr_151 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_152: Ty1 connect _bundle_literal_expr_152.value, _match_arm_value_128.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_152 @[reg_alloc.rs 205:29] + connect rename_1_src_1.addr, _bundle_literal_expr_152 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_153: Ty1 connect _bundle_literal_expr_153.value, _match_arm_value_128.alu_common.common.src[2] - connect rename_1_src_2.addr, _bundle_literal_expr_153 @[reg_alloc.rs 205:29] + connect rename_1_src_2.addr, _bundle_literal_expr_153 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_154: Ty44 wire _bundle_literal_expr_155: Ty43 wire _bundle_literal_expr_156: Ty42 @@ -2304,14 +2328,14 @@ circuit reg_alloc: connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_128.invert_carry_in connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_128.invert_carry_out connect _bundle_literal_expr_154.add_pc, _match_arm_value_128.add_pc - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 477:1] + connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 502:1] AddSubI(_match_arm_value_129): wire _bundle_literal_expr_160: Ty1 connect _bundle_literal_expr_160.value, _match_arm_value_129.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_160 @[reg_alloc.rs 205:29] + connect rename_1_src_0.addr, _bundle_literal_expr_160 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_161: Ty1 connect _bundle_literal_expr_161.value, _match_arm_value_129.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_161 @[reg_alloc.rs 205:29] + connect rename_1_src_1.addr, _bundle_literal_expr_161 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_162: Ty44 wire _bundle_literal_expr_163: Ty43 wire _bundle_literal_expr_164: Ty42 @@ -2408,14 +2432,14 @@ circuit reg_alloc: connect _bundle_literal_expr_162.invert_carry_in, _match_arm_value_129.invert_carry_in connect _bundle_literal_expr_162.invert_carry_out, _match_arm_value_129.invert_carry_out connect _bundle_literal_expr_162.add_pc, _match_arm_value_129.add_pc - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 477:1] + connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 502:1] Logical(_match_arm_value_130): wire _bundle_literal_expr_169: Ty1 connect _bundle_literal_expr_169.value, _match_arm_value_130.alu_common.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_169 @[reg_alloc.rs 205:29] + connect rename_1_src_0.addr, _bundle_literal_expr_169 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_170: Ty1 connect _bundle_literal_expr_170.value, _match_arm_value_130.alu_common.common.src[1] - connect rename_1_src_1.addr, _bundle_literal_expr_170 @[reg_alloc.rs 205:29] + connect rename_1_src_1.addr, _bundle_literal_expr_170 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_171: Ty45 wire _bundle_literal_expr_172: Ty43 wire _bundle_literal_expr_173: Ty42 @@ -2509,11 +2533,11 @@ circuit reg_alloc: connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_130.alu_common.output_integer_mode connect _bundle_literal_expr_171.alu_common, _bundle_literal_expr_172 connect _bundle_literal_expr_171.lut, _match_arm_value_130.lut - connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 477:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 127:1] + connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 502:1] + connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_131): - wire mapped_regs_6: Ty49 @[instruction.rs 504:1] - match _match_arm_value_131: @[instruction.rs 504:1] + wire mapped_regs_6: Ty49 @[instruction.rs 529:1] + match _match_arm_value_131: @[instruction.rs 529:1] ReadL2Reg(_match_arm_value_132): wire _bundle_literal_expr_178: Ty48 wire _bundle_literal_expr_179: Ty47 @@ -2578,11 +2602,11 @@ circuit reg_alloc: invalidate _bundle_literal_expr_183 connect _bundle_literal_expr_179._phantom, _bundle_literal_expr_183 connect _bundle_literal_expr_178.common, _bundle_literal_expr_179 - connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 504:1] + connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 529:1] WriteL2Reg(_match_arm_value_133): wire _bundle_literal_expr_184: Ty1 connect _bundle_literal_expr_184.value, _match_arm_value_133.common.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 205:29] + connect rename_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_185: Ty48 wire _bundle_literal_expr_186: Ty47 connect _bundle_literal_expr_186.prefix_pad, _match_arm_value_133.common.prefix_pad @@ -2653,11 +2677,11 @@ circuit reg_alloc: invalidate _bundle_literal_expr_190 connect _bundle_literal_expr_186._phantom, _bundle_literal_expr_190 connect _bundle_literal_expr_185.common, _bundle_literal_expr_186 - connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 504:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 127:1] + connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 529:1] + connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 129:1] LoadStore(_match_arm_value_134): - wire mapped_regs_7: Ty50 @[instruction.rs 539:1] - match _match_arm_value_134: @[instruction.rs 539:1] + wire mapped_regs_7: Ty50 @[instruction.rs 564:1] + match _match_arm_value_134: @[instruction.rs 564:1] Load(_match_arm_value_135): wire _bundle_literal_expr_191: Ty47 connect _bundle_literal_expr_191.prefix_pad, _match_arm_value_135.prefix_pad @@ -2720,11 +2744,11 @@ circuit reg_alloc: wire _bundle_literal_expr_195: Ty2 invalidate _bundle_literal_expr_195 connect _bundle_literal_expr_191._phantom, _bundle_literal_expr_195 - connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 539:1] + connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 564:1] Store(_match_arm_value_136): wire _bundle_literal_expr_196: Ty1 connect _bundle_literal_expr_196.value, _match_arm_value_136.src[0] - connect rename_1_src_0.addr, _bundle_literal_expr_196 @[reg_alloc.rs 205:29] + connect rename_1_src_0.addr, _bundle_literal_expr_196 @[reg_alloc.rs 204:29] wire _bundle_literal_expr_197: Ty47 connect _bundle_literal_expr_197.prefix_pad, _match_arm_value_136.prefix_pad connect _bundle_literal_expr_197.dest, _match_arm_value_116.unit_out_reg @@ -2793,153 +2817,153 @@ circuit reg_alloc: wire _bundle_literal_expr_201: Ty2 invalidate _bundle_literal_expr_201 connect _bundle_literal_expr_197._phantom, _bundle_literal_expr_201 - connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 539:1] - connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 127:1] - connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 198:17] - wire flag_reg_14: Ty1 @[instruction.rs 806:32] + connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 564:1] + connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 129:1] + connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 197:17] + wire flag_reg_14: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_202: Ty1 connect _bundle_literal_expr_202.value, tail(UInt<32>(0h0), 24) - connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 807:17] - match dest_reg_28.flag_regs[0]: @[instruction.rs 809:17] + connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 832:17] + match dest_reg_28.flag_regs[0]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_137): wire _bundle_literal_expr_203: Ty1 connect _bundle_literal_expr_203.value, tail(UInt<32>(0hFE), 24) - connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 811:21] - wire flag_reg_15: Ty1 @[instruction.rs 806:32] + connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 836:21] + wire flag_reg_15: Ty1 @[instruction.rs 831:32] wire _bundle_literal_expr_204: Ty1 connect _bundle_literal_expr_204.value, tail(UInt<32>(0h0), 24) - connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 807:17] - match dest_reg_28.flag_regs[1]: @[instruction.rs 809:17] + connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 832:17] + match dest_reg_28.flag_regs[1]: @[instruction.rs 834:17] HdlNone: skip HdlSome(_match_arm_value_138): wire _bundle_literal_expr_205: Ty1 connect _bundle_literal_expr_205.value, tail(UInt<32>(0hFF), 24) - connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 811:21] - when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25] - connect rename_table_normal_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 836:21] + when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] + connect rename_table_normal_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33] - connect rename_table_normal_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect rename_table_normal_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] + connect rename_table_normal_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33] - connect rename_table_special_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25] - connect rename_table_normal_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect rename_table_special_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] + connect rename_table_special_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 228:25] + connect rename_table_normal_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<8> ; rhs: UInt<33> - connect rename_table_normal_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33] - connect rename_table_normal_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect rename_table_normal_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 233:33] + connect rename_table_normal_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<33> - connect rename_table_special_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33] - connect rename_table_special_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(flag_reg_14.value, UInt<32>(0hFE)), lt(flag_reg_14.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_1_flag0_rFE.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect rename_table_special_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 233:33] + connect rename_table_special_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(flag_reg_14.value, UInt<32>(0hFE)), lt(flag_reg_14.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_1_flag0_rFE.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<32> - connect rename_table_special_1_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 232:33] - connect rename_table_special_1_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - when and(geq(flag_reg_15.value, UInt<32>(0hFE)), lt(flag_reg_15.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25] - connect rename_table_special_1_flag1_rFF.data, _match_arm_value_116 @[reg_alloc.rs 230:29] + connect rename_table_special_1_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 231:33] + connect rename_table_special_1_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + when and(geq(flag_reg_15.value, UInt<32>(0hFE)), lt(flag_reg_15.value, UInt<32>(0h100))): @[reg_alloc.rs 228:25] + connect rename_table_special_1_flag1_rFF.data, _match_arm_value_116 @[reg_alloc.rs 229:29] ; connect different types: ; lhs: UInt<1> ; rhs: UInt<32> - connect rename_table_special_1_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 232:33] - connect rename_table_special_1_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 236:29] - wire selected_unit_index_leaf_1_0: Ty41 @[reg_alloc.rs 250:25] - connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21] - wire unit_index_1_0: UInt<2> @[reg_alloc.rs 259:25] + connect rename_table_special_1_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 231:33] + connect rename_table_special_1_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 235:29] + wire selected_unit_index_leaf_1_0: Ty41 @[reg_alloc.rs 249:25] + connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] + wire unit_index_1_0: UInt<2> @[reg_alloc.rs 258:25] ; connect different types: ; lhs: UInt<2> ; rhs: UInt<64> - connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 262:21] - when available_units[1][0]: @[reg_alloc.rs 264:21] - connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 265:25] - wire selected_unit_index_leaf_1_1: Ty41 @[reg_alloc.rs 250:25] - connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21] - wire unit_index_1_1: UInt<2> @[reg_alloc.rs 259:25] + connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 261:21] + when available_units[1][0]: @[reg_alloc.rs 263:21] + connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 264:25] + wire selected_unit_index_leaf_1_1: Ty41 @[reg_alloc.rs 249:25] + connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 252:21] + wire unit_index_1_1: UInt<2> @[reg_alloc.rs 258:25] ; connect different types: ; lhs: UInt<2> ; rhs: UInt<64> - connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 262:21] - when available_units[1][1]: @[reg_alloc.rs 264:21] - connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 265:25] - wire selected_unit_index_node_1_0: Ty41 @[reg_alloc.rs 272:25] - connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 276:21] - match selected_unit_index_leaf_1_0: @[reg_alloc.rs 278:21] + connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 261:21] + when available_units[1][1]: @[reg_alloc.rs 263:21] + connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 264:25] + wire selected_unit_index_node_1_0: Ty41 @[reg_alloc.rs 271:25] + connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 275:21] + match selected_unit_index_leaf_1_0: @[reg_alloc.rs 277:21] HdlNone: - connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 279:25] + connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 278:25] HdlSome(_match_arm_value_139): skip - connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 242:9] - match selected_unit_indexes[0]: @[reg_alloc.rs 292:13] + connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 241:9] + match selected_unit_indexes[0]: @[reg_alloc.rs 291:13] HdlNone: skip HdlSome(_match_arm_value_140): - connect available_units[1][_match_arm_value_140], UInt<1>(0h0) @[reg_alloc.rs 293:17] + connect available_units[1][_match_arm_value_140], UInt<1>(0h0) @[reg_alloc.rs 292:17] wire _array_literal_expr_74: Ty53[2] connect _array_literal_expr_74[0], {|HdlNone, HdlSome: Ty25|}(HdlNone) connect _array_literal_expr_74[1], {|HdlNone, HdlSome: Ty25|}(HdlNone) - connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 300:5] - inst unit_0 of alu_branch @[reg_alloc.rs 312:13] - connect unit_0.cd, cd @[reg_alloc.rs 314:9] - inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 327:13] - connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 329:9] - wire _uninit_expr_12: Ty65 + connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 299:5] + inst unit_0 of alu_branch @[reg_alloc.rs 311:13] + connect unit_0.cd, cd @[reg_alloc.rs 313:9] + inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 326:13] + connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9] + wire _uninit_expr_12: Ty78 invalidate _uninit_expr_12 - connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr_12 @[reg_alloc.rs 331:9] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 335:9] - connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 336:9] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13] + connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr_12 @[reg_alloc.rs 330:9] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9] + connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] HdlNone: - connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 341:17] + connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 343:17] HdlSome(_match_arm_value_141): skip - when not(unit_0.`input`.ready): @[reg_alloc.rs 344:13] - connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 346:17] - match selected_unit_indexes[0]: @[reg_alloc.rs 349:13] + when not(unit_0.input_insn.ready): @[reg_alloc.rs 346:13] + connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 348:17] + match selected_unit_indexes[0]: @[reg_alloc.rs 351:13] HdlNone: skip HdlSome(_match_arm_value_142): - when eq(_match_arm_value_142, UInt<64>(0h0)): @[reg_alloc.rs 351:17] - wire and_then_out: Ty62 @[reg_alloc.rs 355:25] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21] - match renamed_mops[0]: @[reg_alloc.rs 355:25] + when eq(_match_arm_value_142, UInt<64>(0h0)): @[reg_alloc.rs 353:17] + wire and_then_out: Ty62 @[reg_alloc.rs 357:25] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] + match renamed_mops[0]: @[reg_alloc.rs 357:25] HdlNone: - connect and_then_out, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25] + connect and_then_out, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] HdlSome(_match_arm_value_143): - wire alu_branch_mop: Ty62 @[unit.rs 127:1] - connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1] - match _match_arm_value_143: @[unit.rs 127:1] + wire alu_branch_mop: Ty62 @[unit.rs 129:1] + connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1] + match _match_arm_value_143: @[unit.rs 129:1] AluBranch(_match_arm_value_144): - connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 127:1] + connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_145): skip LoadStore(_match_arm_value_146): skip - connect and_then_out, alu_branch_mop @[reg_alloc.rs 355:25] - match and_then_out: @[reg_alloc.rs 354:21] + connect and_then_out, alu_branch_mop @[reg_alloc.rs 357:25] + match and_then_out: @[reg_alloc.rs 356:21] HdlNone: wire _uninit_expr_13: Ty46 invalidate _uninit_expr_13 - connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 359:25] + connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 361:25] HdlSome(_match_arm_value_147): - connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 357:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21] + connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 359:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] HdlNone: skip HdlSome(_match_arm_value_148): @@ -2950,43 +2974,43 @@ circuit reg_alloc: wire _bundle_literal_expr_208: Ty24 connect _bundle_literal_expr_208.value, _match_arm_value_148 connect _bundle_literal_expr_206.unit_out_reg, _bundle_literal_expr_208 - connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_206) @[reg_alloc.rs 372:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13] + connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_206) @[reg_alloc.rs 374:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] HdlNone: - connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 341:17] + connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 343:17] HdlSome(_match_arm_value_149): skip - when not(unit_0.`input`.ready): @[reg_alloc.rs 344:13] - connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 346:17] - match selected_unit_indexes[1]: @[reg_alloc.rs 349:13] + when not(unit_0.input_insn.ready): @[reg_alloc.rs 346:13] + connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 348:17] + match selected_unit_indexes[1]: @[reg_alloc.rs 351:13] HdlNone: skip HdlSome(_match_arm_value_150): - when eq(_match_arm_value_150, UInt<64>(0h0)): @[reg_alloc.rs 351:17] - wire and_then_out_1: Ty62 @[reg_alloc.rs 355:25] - connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21] - match renamed_mops[1]: @[reg_alloc.rs 355:25] + when eq(_match_arm_value_150, UInt<64>(0h0)): @[reg_alloc.rs 353:17] + wire and_then_out_1: Ty62 @[reg_alloc.rs 357:25] + connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] + match renamed_mops[1]: @[reg_alloc.rs 357:25] HdlNone: - connect and_then_out_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25] + connect and_then_out_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] HdlSome(_match_arm_value_151): - wire alu_branch_mop_1: Ty62 @[unit.rs 127:1] - connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1] - match _match_arm_value_151: @[unit.rs 127:1] + wire alu_branch_mop_1: Ty62 @[unit.rs 129:1] + connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1] + match _match_arm_value_151: @[unit.rs 129:1] AluBranch(_match_arm_value_152): - connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 127:1] + connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_153): skip LoadStore(_match_arm_value_154): skip - connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 355:25] - match and_then_out_1: @[reg_alloc.rs 354:21] + connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 357:25] + match and_then_out_1: @[reg_alloc.rs 356:21] HdlNone: wire _uninit_expr_14: Ty46 invalidate _uninit_expr_14 - connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 359:25] + connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 361:25] HdlSome(_match_arm_value_155): - connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 357:25] - match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21] + connect unit_0.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 359:25] + match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] HdlNone: skip HdlSome(_match_arm_value_156): @@ -2997,118 +3021,149 @@ circuit reg_alloc: wire _bundle_literal_expr_211: Ty24 connect _bundle_literal_expr_211.value, _match_arm_value_156 connect _bundle_literal_expr_209.unit_out_reg, _bundle_literal_expr_211 - connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_209) @[reg_alloc.rs 372:25] - inst unit_1 of alu_branch_1 @[reg_alloc.rs 312:13] - connect unit_1.cd, cd @[reg_alloc.rs 314:9] - inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 327:13] - connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 329:9] - wire _uninit_expr_15: Ty65 + connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_209) @[reg_alloc.rs 374:25] + wire _bundle_literal_expr_212: Ty68 + wire _array_literal_expr_75: Ty67[2] + connect _array_literal_expr_75[0], {|HdlNone, HdlSome: Ty66|}(HdlNone) + connect _array_literal_expr_75[1], {|HdlNone, HdlSome: Ty66|}(HdlNone) + connect _bundle_literal_expr_212.unit_output_writes, _array_literal_expr_75 + wire _bundle_literal_expr_213: Ty2 + invalidate _bundle_literal_expr_213 + connect _bundle_literal_expr_212._phantom, _bundle_literal_expr_213 + connect unit_0.unit_forwarding_info, _bundle_literal_expr_212 @[reg_alloc.rs 389:9] + connect unit_0.`output`.ready, UInt<1>(0h0) @[reg_alloc.rs 400:9] + connect unit_0.cancel_input.data, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 402:9] + inst unit_1 of alu_branch_1 @[reg_alloc.rs 311:13] + connect unit_1.cd, cd @[reg_alloc.rs 313:9] + inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 326:13] + connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 328:9] + wire _uninit_expr_15: Ty78 invalidate _uninit_expr_15 - connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_15 @[reg_alloc.rs 331:9] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 335:9] - connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 336:9] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13] + connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_15 @[reg_alloc.rs 330:9] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 334:9] + connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 335:9] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] HdlNone: - connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 341:17] + connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 343:17] HdlSome(_match_arm_value_157): skip - when not(unit_1.`input`.ready): @[reg_alloc.rs 344:13] - connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 346:17] - match selected_unit_indexes[0]: @[reg_alloc.rs 349:13] + when not(unit_1.input_insn.ready): @[reg_alloc.rs 346:13] + connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 348:17] + match selected_unit_indexes[0]: @[reg_alloc.rs 351:13] HdlNone: skip HdlSome(_match_arm_value_158): - when eq(_match_arm_value_158, UInt<64>(0h1)): @[reg_alloc.rs 351:17] - wire and_then_out_2: Ty62 @[reg_alloc.rs 355:25] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21] - match renamed_mops[0]: @[reg_alloc.rs 355:25] + when eq(_match_arm_value_158, UInt<64>(0h1)): @[reg_alloc.rs 353:17] + wire and_then_out_2: Ty62 @[reg_alloc.rs 357:25] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] + match renamed_mops[0]: @[reg_alloc.rs 357:25] HdlNone: - connect and_then_out_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25] + connect and_then_out_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] HdlSome(_match_arm_value_159): - wire alu_branch_mop_2: Ty62 @[unit.rs 127:1] - connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1] - match _match_arm_value_159: @[unit.rs 127:1] + wire alu_branch_mop_2: Ty62 @[unit.rs 129:1] + connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1] + match _match_arm_value_159: @[unit.rs 129:1] AluBranch(_match_arm_value_160): - connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 127:1] + connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_161): skip LoadStore(_match_arm_value_162): skip - connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 355:25] - match and_then_out_2: @[reg_alloc.rs 354:21] + connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 357:25] + match and_then_out_2: @[reg_alloc.rs 356:21] HdlNone: wire _uninit_expr_16: Ty46 invalidate _uninit_expr_16 - connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 359:25] + connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 361:25] HdlSome(_match_arm_value_163): - connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 357:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21] + connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 359:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] HdlNone: skip HdlSome(_match_arm_value_164): - wire _bundle_literal_expr_212: Ty25 - wire _bundle_literal_expr_213: Ty23 - connect _bundle_literal_expr_213.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_212.unit_num, _bundle_literal_expr_213 - wire _bundle_literal_expr_214: Ty24 - connect _bundle_literal_expr_214.value, _match_arm_value_164 - connect _bundle_literal_expr_212.unit_out_reg, _bundle_literal_expr_214 - connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_212) @[reg_alloc.rs 372:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13] + wire _bundle_literal_expr_214: Ty25 + wire _bundle_literal_expr_215: Ty23 + connect _bundle_literal_expr_215.adj_value, tail(UInt<64>(0h2), 62) + connect _bundle_literal_expr_214.unit_num, _bundle_literal_expr_215 + wire _bundle_literal_expr_216: Ty24 + connect _bundle_literal_expr_216.value, _match_arm_value_164 + connect _bundle_literal_expr_214.unit_out_reg, _bundle_literal_expr_216 + connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_214) @[reg_alloc.rs 374:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 341:13] HdlNone: - connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 341:17] + connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 343:17] HdlSome(_match_arm_value_165): skip - when not(unit_1.`input`.ready): @[reg_alloc.rs 344:13] - connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 346:17] - match selected_unit_indexes[1]: @[reg_alloc.rs 349:13] + when not(unit_1.input_insn.ready): @[reg_alloc.rs 346:13] + connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 348:17] + match selected_unit_indexes[1]: @[reg_alloc.rs 351:13] HdlNone: skip HdlSome(_match_arm_value_166): - when eq(_match_arm_value_166, UInt<64>(0h1)): @[reg_alloc.rs 351:17] - wire and_then_out_3: Ty62 @[reg_alloc.rs 355:25] - connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21] - match renamed_mops[1]: @[reg_alloc.rs 355:25] + when eq(_match_arm_value_166, UInt<64>(0h1)): @[reg_alloc.rs 353:17] + wire and_then_out_3: Ty62 @[reg_alloc.rs 357:25] + connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 354:21] + match renamed_mops[1]: @[reg_alloc.rs 357:25] HdlNone: - connect and_then_out_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25] + connect and_then_out_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 357:25] HdlSome(_match_arm_value_167): - wire alu_branch_mop_3: Ty62 @[unit.rs 127:1] - connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1] - match _match_arm_value_167: @[unit.rs 127:1] + wire alu_branch_mop_3: Ty62 @[unit.rs 129:1] + connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 129:1] + match _match_arm_value_167: @[unit.rs 129:1] AluBranch(_match_arm_value_168): - connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 127:1] + connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 129:1] L2RegisterFile(_match_arm_value_169): skip LoadStore(_match_arm_value_170): skip - connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 355:25] - match and_then_out_3: @[reg_alloc.rs 354:21] + connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 357:25] + match and_then_out_3: @[reg_alloc.rs 356:21] HdlNone: wire _uninit_expr_17: Ty46 invalidate _uninit_expr_17 - connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 359:25] + connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 361:25] HdlSome(_match_arm_value_171): - connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 357:25] - match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21] + connect unit_1.input_insn.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 359:25] + match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 368:21] HdlNone: skip HdlSome(_match_arm_value_172): - wire _bundle_literal_expr_215: Ty25 - wire _bundle_literal_expr_216: Ty23 - connect _bundle_literal_expr_216.adj_value, tail(UInt<64>(0h2), 62) - connect _bundle_literal_expr_215.unit_num, _bundle_literal_expr_216 - wire _bundle_literal_expr_217: Ty24 - connect _bundle_literal_expr_217.value, _match_arm_value_172 - connect _bundle_literal_expr_215.unit_out_reg, _bundle_literal_expr_217 - connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_215) @[reg_alloc.rs 372:25] - module alu_branch: @[alu_branch.rs 15:1] - input cd: Ty0 @[alu_branch.rs 18:29] - input `input`: Ty63 @[alu_branch.rs 21:11] - connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5] + wire _bundle_literal_expr_217: Ty25 + wire _bundle_literal_expr_218: Ty23 + connect _bundle_literal_expr_218.adj_value, tail(UInt<64>(0h2), 62) + connect _bundle_literal_expr_217.unit_num, _bundle_literal_expr_218 + wire _bundle_literal_expr_219: Ty24 + connect _bundle_literal_expr_219.value, _match_arm_value_172 + connect _bundle_literal_expr_217.unit_out_reg, _bundle_literal_expr_219 + connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_217) @[reg_alloc.rs 374:25] + wire _bundle_literal_expr_220: Ty68 + wire _array_literal_expr_76: Ty67[2] + connect _array_literal_expr_76[0], {|HdlNone, HdlSome: Ty66|}(HdlNone) + connect _array_literal_expr_76[1], {|HdlNone, HdlSome: Ty66|}(HdlNone) + connect _bundle_literal_expr_220.unit_output_writes, _array_literal_expr_76 + wire _bundle_literal_expr_221: Ty2 + invalidate _bundle_literal_expr_221 + connect _bundle_literal_expr_220._phantom, _bundle_literal_expr_221 + connect unit_1.unit_forwarding_info, _bundle_literal_expr_220 @[reg_alloc.rs 389:9] + connect unit_1.`output`.ready, UInt<1>(0h0) @[reg_alloc.rs 400:9] + connect unit_1.cancel_input.data, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[reg_alloc.rs 402:9] + module alu_branch: @[alu_branch.rs 18:1] + input cd: Ty0 @[alu_branch.rs 21:29] + input input_insn: Ty63 @[alu_branch.rs 24:11] + input unit_forwarding_info: Ty68 @[alu_branch.rs 27:11] + input cancel_input: Ty71 @[alu_branch.rs 30:11] + output `output`: Ty76 @[alu_branch.rs 33:11] + inst unit_base of unit_base @[alu_branch.rs 35:21] + connect unit_base.input_insn, input_insn @[alu_branch.rs 40:5] + connect unit_base.cd, cd @[alu_branch.rs 41:5] + connect unit_base.unit_forwarding_info, unit_forwarding_info @[alu_branch.rs 42:5] + connect unit_base.cancel_input, cancel_input @[alu_branch.rs 43:5] + connect unit_base.ready_mop.ready, UInt<1>(0h1) @[alu_branch.rs 45:5] + connect `output`.data, {|HdlNone, HdlSome: Ty74|}(HdlNone) @[alu_branch.rs 46:5] module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1] input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] - input free_in: Ty66[1] @[unit_free_regs_tracker.rs 17:11] - output alloc_out: Ty66[1] @[unit_free_regs_tracker.rs 20:11] + input free_in: Ty79[1] @[unit_free_regs_tracker.rs 17:11] + output alloc_out: Ty79[1] @[unit_free_regs_tracker.rs 20:11] wire _array_literal_expr: UInt<1>[16] connect _array_literal_expr[0], UInt<1>(0h0) connect _array_literal_expr[1], UInt<1>(0h0) @@ -3128,7 +3183,7 @@ circuit reg_alloc: connect _array_literal_expr[15], UInt<1>(0h0) regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] - wire firing_data: Ty65 @[ready_valid.rs 30:27] + wire firing_data: Ty78 @[ready_valid.rs 30:27] connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when free_in[0].ready: @[ready_valid.rs 33:9] connect firing_data, free_in[0].data @[ready_valid.rs 34:13] @@ -3439,7 +3494,7 @@ circuit reg_alloc: ; lhs: UInt<4> ; rhs: UInt<65> connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] - wire firing_data_1: Ty65 @[ready_valid.rs 30:27] + wire firing_data_1: Ty78 @[ready_valid.rs 30:27] connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when alloc_out[0].ready: @[ready_valid.rs 33:9] connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] @@ -3452,14 +3507,23 @@ circuit reg_alloc: connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] else: connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] - module alu_branch_1: @[alu_branch.rs 15:1] - input cd: Ty0 @[alu_branch.rs 18:29] - input `input`: Ty63 @[alu_branch.rs 21:11] - connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5] + module alu_branch_1: @[alu_branch.rs 18:1] + input cd: Ty0 @[alu_branch.rs 21:29] + input input_insn: Ty63 @[alu_branch.rs 24:11] + input unit_forwarding_info: Ty68 @[alu_branch.rs 27:11] + input cancel_input: Ty71 @[alu_branch.rs 30:11] + output `output`: Ty76 @[alu_branch.rs 33:11] + inst unit_base of unit_base_1 @[alu_branch.rs 35:21] + connect unit_base.input_insn, input_insn @[alu_branch.rs 40:5] + connect unit_base.cd, cd @[alu_branch.rs 41:5] + connect unit_base.unit_forwarding_info, unit_forwarding_info @[alu_branch.rs 42:5] + connect unit_base.cancel_input, cancel_input @[alu_branch.rs 43:5] + connect unit_base.ready_mop.ready, UInt<1>(0h1) @[alu_branch.rs 45:5] + connect `output`.data, {|HdlNone, HdlSome: Ty74|}(HdlNone) @[alu_branch.rs 46:5] module unit_free_regs_tracker_1: @[unit_free_regs_tracker.rs 7:1] input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] - input free_in: Ty66[1] @[unit_free_regs_tracker.rs 17:11] - output alloc_out: Ty66[1] @[unit_free_regs_tracker.rs 20:11] + input free_in: Ty79[1] @[unit_free_regs_tracker.rs 17:11] + output alloc_out: Ty79[1] @[unit_free_regs_tracker.rs 20:11] wire _array_literal_expr: UInt<1>[16] connect _array_literal_expr[0], UInt<1>(0h0) connect _array_literal_expr[1], UInt<1>(0h0) @@ -3479,7 +3543,7 @@ circuit reg_alloc: connect _array_literal_expr[15], UInt<1>(0h0) regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] - wire firing_data: Ty65 @[ready_valid.rs 30:27] + wire firing_data: Ty78 @[ready_valid.rs 30:27] connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when free_in[0].ready: @[ready_valid.rs 33:9] connect firing_data, free_in[0].data @[ready_valid.rs 34:13] @@ -3790,7 +3854,7 @@ circuit reg_alloc: ; lhs: UInt<4> ; rhs: UInt<65> connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] - wire firing_data_1: Ty65 @[ready_valid.rs 30:27] + wire firing_data_1: Ty78 @[ready_valid.rs 30:27] connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] when alloc_out[0].ready: @[ready_valid.rs 33:9] connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] @@ -3803,6 +3867,1006 @@ circuit reg_alloc: connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] else: connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] + module unit_base: @[unit_base.rs 32:1] + input cd: Ty0 @[unit_base.rs 39:29] + input unit_forwarding_info: Ty68 @[unit_base.rs 42:11] + input input_insn: Ty63 @[unit_base.rs 44:41] + input cancel_input: Ty71 @[unit_base.rs 48:11] + output ready_mop: Ty83 @[unit_base.rs 51:50] + wire and_then_out: Ty85 @[unit_base.rs 66:17] + wire and_then_out_1: Ty85 @[unit_base.rs 66:17] + wire and_then_out_2: Ty85 @[unit_base.rs 66:17] + wire and_then_out_3: Ty85 @[unit_base.rs 66:17] + wire and_then_out_4: Ty85 @[unit_base.rs 66:17] + wire and_then_out_5: Ty85 @[unit_base.rs 66:17] + wire and_then_out_6: Ty85 @[unit_base.rs 66:17] + wire and_then_out_7: Ty85 @[unit_base.rs 66:17] + connect input_insn.ready, UInt<1>(0h0) @[unit_base.rs 45:5] + connect cancel_input.ready, UInt<1>(0h1) @[unit_base.rs 49:5] + connect ready_mop.data, {|HdlNone, HdlSome: Ty81|}(HdlNone) @[unit_base.rs 52:5] + wire _array_literal_expr: Ty88[8] + connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) + regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 55:25] + wire input_index: Ty85 @[unit_base.rs 61:23] + match in_flight_ops[0]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value): + connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 66:17] + match in_flight_ops[1]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_1): + connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 66:17] + wire or_out: Ty85 @[function.rs 166:5] + connect or_out, and_then_out_1 @[function.rs 166:5] + match and_then_out: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_2): + connect or_out, and_then_out @[function.rs 166:5] + match in_flight_ops[2]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_3): + connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 66:17] + match in_flight_ops[3]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_4): + connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 66:17] + wire or_out_1: Ty85 @[function.rs 166:5] + connect or_out_1, and_then_out_3 @[function.rs 166:5] + match and_then_out_2: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_5): + connect or_out_1, and_then_out_2 @[function.rs 166:5] + wire or_out_2: Ty85 @[function.rs 166:5] + connect or_out_2, or_out_1 @[function.rs 166:5] + match or_out: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_6): + connect or_out_2, or_out @[function.rs 166:5] + match in_flight_ops[4]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_7): + connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 66:17] + match in_flight_ops[5]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_8): + connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 66:17] + wire or_out_3: Ty85 @[function.rs 166:5] + connect or_out_3, and_then_out_5 @[function.rs 166:5] + match and_then_out_4: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_9): + connect or_out_3, and_then_out_4 @[function.rs 166:5] + match in_flight_ops[6]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_10): + connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 66:17] + match in_flight_ops[7]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_11): + connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 66:17] + wire or_out_4: Ty85 @[function.rs 166:5] + connect or_out_4, and_then_out_7 @[function.rs 166:5] + match and_then_out_6: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_12): + connect or_out_4, and_then_out_6 @[function.rs 166:5] + wire or_out_5: Ty85 @[function.rs 166:5] + connect or_out_5, or_out_4 @[function.rs 166:5] + match or_out_3: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_13): + connect or_out_5, or_out_3 @[function.rs 166:5] + wire or_out_6: Ty85 @[function.rs 166:5] + connect or_out_6, or_out_5 @[function.rs 166:5] + match or_out_2: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_14): + connect or_out_6, or_out_2 @[function.rs 166:5] + connect input_index, or_out_6 @[unit_base.rs 62:5] + wire input_in_flight_op: Ty88 @[unit_base.rs 73:30] + connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 74:5] + wire firing_data: Ty62 @[ready_valid.rs 30:27] + connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9] + when input_insn.ready: @[ready_valid.rs 33:9] + connect firing_data, input_insn.data @[ready_valid.rs 34:13] + match firing_data: @[unit_base.rs 76:5] + HdlNone: + skip + HdlSome(_match_arm_value_15): + wire input_in_flight_op_src_values: Ty86[3] @[unit_base.rs 79:13] + wire _array_literal_expr_1: Ty86[3] + wire _bundle_literal_expr: Ty65 + connect _bundle_literal_expr.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_1: Ty64 + connect _bundle_literal_expr_1.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr.flags, _bundle_literal_expr_1 + connect _array_literal_expr_1[0], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr) + wire _bundle_literal_expr_2: Ty65 + connect _bundle_literal_expr_2.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_3: Ty64 + connect _bundle_literal_expr_3.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr_2.flags, _bundle_literal_expr_3 + connect _array_literal_expr_1[1], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_2) + wire _bundle_literal_expr_4: Ty65 + connect _bundle_literal_expr_4.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_5: Ty64 + connect _bundle_literal_expr_5.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr_4.flags, _bundle_literal_expr_5 + connect _array_literal_expr_1[2], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_4) + connect input_in_flight_op_src_values, _array_literal_expr_1 @[unit_base.rs 82:9] + match _match_arm_value_15: @[instruction.rs 502:1] + AddSub(_match_arm_value_16): + wire _bundle_literal_expr_6: Ty25 + wire _bundle_literal_expr_7: Ty23 + connect _bundle_literal_expr_7.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_6.unit_num, _bundle_literal_expr_7 + wire _bundle_literal_expr_8: Ty24 + connect _bundle_literal_expr_8.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_6.unit_out_reg, _bundle_literal_expr_8 + wire _cast_bundle_to_bits_expr: Ty57 + connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_6.unit_num.adj_value + connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_6.unit_out_reg.value + wire _cast_to_bits_expr: UInt<6> + connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) + when neq(_cast_to_bits_expr, _match_arm_value_16.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_9: Ty25 + wire _bundle_literal_expr_10: Ty23 + connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10 + wire _bundle_literal_expr_11: Ty24 + connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11 + wire _cast_bundle_to_bits_expr_1: Ty57 + connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_9.unit_num.adj_value + connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_9.unit_out_reg.value + wire _cast_to_bits_expr_1: UInt<6> + connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) + when neq(_cast_to_bits_expr_1, _match_arm_value_16.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_12: Ty25 + wire _bundle_literal_expr_13: Ty23 + connect _bundle_literal_expr_13.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_12.unit_num, _bundle_literal_expr_13 + wire _bundle_literal_expr_14: Ty24 + connect _bundle_literal_expr_14.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_12.unit_out_reg, _bundle_literal_expr_14 + wire _cast_bundle_to_bits_expr_2: Ty57 + connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_12.unit_num.adj_value + connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_12.unit_out_reg.value + wire _cast_to_bits_expr_2: UInt<6> + connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) + when neq(_cast_to_bits_expr_2, _match_arm_value_16.alu_common.common.src[2]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[2], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + AddSubI(_match_arm_value_17): + wire _bundle_literal_expr_15: Ty25 + wire _bundle_literal_expr_16: Ty23 + connect _bundle_literal_expr_16.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_15.unit_num, _bundle_literal_expr_16 + wire _bundle_literal_expr_17: Ty24 + connect _bundle_literal_expr_17.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_15.unit_out_reg, _bundle_literal_expr_17 + wire _cast_bundle_to_bits_expr_3: Ty57 + connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_15.unit_num.adj_value + connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_15.unit_out_reg.value + wire _cast_to_bits_expr_3: UInt<6> + connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) + when neq(_cast_to_bits_expr_3, _match_arm_value_17.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_18: Ty25 + wire _bundle_literal_expr_19: Ty23 + connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19 + wire _bundle_literal_expr_20: Ty24 + connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20 + wire _cast_bundle_to_bits_expr_4: Ty57 + connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_18.unit_num.adj_value + connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_18.unit_out_reg.value + wire _cast_to_bits_expr_4: UInt<6> + connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) + when neq(_cast_to_bits_expr_4, _match_arm_value_17.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + Logical(_match_arm_value_18): + wire _bundle_literal_expr_21: Ty25 + wire _bundle_literal_expr_22: Ty23 + connect _bundle_literal_expr_22.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22 + wire _bundle_literal_expr_23: Ty24 + connect _bundle_literal_expr_23.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23 + wire _cast_bundle_to_bits_expr_5: Ty57 + connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_21.unit_num.adj_value + connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_21.unit_out_reg.value + wire _cast_to_bits_expr_5: UInt<6> + connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) + when neq(_cast_to_bits_expr_5, _match_arm_value_18.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_24: Ty25 + wire _bundle_literal_expr_25: Ty23 + connect _bundle_literal_expr_25.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_24.unit_num, _bundle_literal_expr_25 + wire _bundle_literal_expr_26: Ty24 + connect _bundle_literal_expr_26.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_24.unit_out_reg, _bundle_literal_expr_26 + wire _cast_bundle_to_bits_expr_6: Ty57 + connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_24.unit_num.adj_value + connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_24.unit_out_reg.value + wire _cast_to_bits_expr_6: UInt<6> + connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) + when neq(_cast_to_bits_expr_6, _match_arm_value_18.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_27: Ty87 + connect _bundle_literal_expr_27.mop, _match_arm_value_15 + connect _bundle_literal_expr_27.src_values, input_in_flight_op_src_values + connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_27) @[unit_base.rs 97:9] + match in_flight_ops[0]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_19): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_19, UInt<64>(0h0)): @[unit_base.rs 125:13] + connect in_flight_ops[0], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_20): + wire firing_data_1: Ty70 @[ready_valid.rs 30:27] + connect firing_data_1, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_1, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_1: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_21): + wire dest_reg: Ty24 @[instruction.rs 502:1] + match _match_arm_value_20.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_22): + connect dest_reg, _match_arm_value_22.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_23): + connect dest_reg, _match_arm_value_23.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_24): + connect dest_reg, _match_arm_value_24.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_21.which.value, dest_reg.value): @[unit_base.rs 113:17] + connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[1]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_25): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_25, UInt<64>(0h1)): @[unit_base.rs 125:13] + connect in_flight_ops[1], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_26): + wire firing_data_2: Ty70 @[ready_valid.rs 30:27] + connect firing_data_2, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_2, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_2: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_27): + wire dest_reg_1: Ty24 @[instruction.rs 502:1] + match _match_arm_value_26.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_28): + connect dest_reg_1, _match_arm_value_28.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_29): + connect dest_reg_1, _match_arm_value_29.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_30): + connect dest_reg_1, _match_arm_value_30.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_27.which.value, dest_reg_1.value): @[unit_base.rs 113:17] + connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[2]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_31): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_31, UInt<64>(0h2)): @[unit_base.rs 125:13] + connect in_flight_ops[2], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_32): + wire firing_data_3: Ty70 @[ready_valid.rs 30:27] + connect firing_data_3, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_3, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_3: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_33): + wire dest_reg_2: Ty24 @[instruction.rs 502:1] + match _match_arm_value_32.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_34): + connect dest_reg_2, _match_arm_value_34.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_35): + connect dest_reg_2, _match_arm_value_35.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_36): + connect dest_reg_2, _match_arm_value_36.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_33.which.value, dest_reg_2.value): @[unit_base.rs 113:17] + connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[3]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_37): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_37, UInt<64>(0h3)): @[unit_base.rs 125:13] + connect in_flight_ops[3], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_38): + wire firing_data_4: Ty70 @[ready_valid.rs 30:27] + connect firing_data_4, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_4, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_4: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_39): + wire dest_reg_3: Ty24 @[instruction.rs 502:1] + match _match_arm_value_38.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_40): + connect dest_reg_3, _match_arm_value_40.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_41): + connect dest_reg_3, _match_arm_value_41.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_42): + connect dest_reg_3, _match_arm_value_42.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_39.which.value, dest_reg_3.value): @[unit_base.rs 113:17] + connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[4]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_43): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_43, UInt<64>(0h4)): @[unit_base.rs 125:13] + connect in_flight_ops[4], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_44): + wire firing_data_5: Ty70 @[ready_valid.rs 30:27] + connect firing_data_5, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_5, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_5: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_45): + wire dest_reg_4: Ty24 @[instruction.rs 502:1] + match _match_arm_value_44.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_46): + connect dest_reg_4, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_47): + connect dest_reg_4, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_48): + connect dest_reg_4, _match_arm_value_48.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_45.which.value, dest_reg_4.value): @[unit_base.rs 113:17] + connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[5]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_49): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_49, UInt<64>(0h5)): @[unit_base.rs 125:13] + connect in_flight_ops[5], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_50): + wire firing_data_6: Ty70 @[ready_valid.rs 30:27] + connect firing_data_6, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_6, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_6: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_51): + wire dest_reg_5: Ty24 @[instruction.rs 502:1] + match _match_arm_value_50.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_52): + connect dest_reg_5, _match_arm_value_52.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_53): + connect dest_reg_5, _match_arm_value_53.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_54): + connect dest_reg_5, _match_arm_value_54.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_51.which.value, dest_reg_5.value): @[unit_base.rs 113:17] + connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[6]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_55): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_55, UInt<64>(0h6)): @[unit_base.rs 125:13] + connect in_flight_ops[6], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_56): + wire firing_data_7: Ty70 @[ready_valid.rs 30:27] + connect firing_data_7, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_7, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_7: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_57): + wire dest_reg_6: Ty24 @[instruction.rs 502:1] + match _match_arm_value_56.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_58): + connect dest_reg_6, _match_arm_value_58.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_59): + connect dest_reg_6, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_60): + connect dest_reg_6, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_57.which.value, dest_reg_6.value): @[unit_base.rs 113:17] + connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[7]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_61): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_61, UInt<64>(0h7)): @[unit_base.rs 125:13] + connect in_flight_ops[7], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_62): + wire firing_data_8: Ty70 @[ready_valid.rs 30:27] + connect firing_data_8, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_8, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_8: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_63): + wire dest_reg_7: Ty24 @[instruction.rs 502:1] + match _match_arm_value_62.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_64): + connect dest_reg_7, _match_arm_value_64.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_65): + connect dest_reg_7, _match_arm_value_65.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_66): + connect dest_reg_7, _match_arm_value_66.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_63.which.value, dest_reg_7.value): @[unit_base.rs 113:17] + connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + module unit_base_1: @[unit_base.rs 32:1] + input cd: Ty0 @[unit_base.rs 39:29] + input unit_forwarding_info: Ty68 @[unit_base.rs 42:11] + input input_insn: Ty63 @[unit_base.rs 44:41] + input cancel_input: Ty71 @[unit_base.rs 48:11] + output ready_mop: Ty83 @[unit_base.rs 51:50] + wire and_then_out: Ty85 @[unit_base.rs 66:17] + wire and_then_out_1: Ty85 @[unit_base.rs 66:17] + wire and_then_out_2: Ty85 @[unit_base.rs 66:17] + wire and_then_out_3: Ty85 @[unit_base.rs 66:17] + wire and_then_out_4: Ty85 @[unit_base.rs 66:17] + wire and_then_out_5: Ty85 @[unit_base.rs 66:17] + wire and_then_out_6: Ty85 @[unit_base.rs 66:17] + wire and_then_out_7: Ty85 @[unit_base.rs 66:17] + connect input_insn.ready, UInt<1>(0h0) @[unit_base.rs 45:5] + connect cancel_input.ready, UInt<1>(0h1) @[unit_base.rs 49:5] + connect ready_mop.data, {|HdlNone, HdlSome: Ty81|}(HdlNone) @[unit_base.rs 52:5] + wire _array_literal_expr: Ty88[8] + connect _array_literal_expr[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) + connect _array_literal_expr[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) + regreset in_flight_ops: Ty88[8], cd.clk, cd.rst, _array_literal_expr @[unit_base.rs 55:25] + wire input_index: Ty85 @[unit_base.rs 61:23] + match in_flight_ops[0]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value): + connect and_then_out, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h0), 61)) @[unit_base.rs 66:17] + match in_flight_ops[1]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_1): + connect and_then_out_1, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h1), 61)) @[unit_base.rs 66:17] + wire or_out: Ty85 @[function.rs 166:5] + connect or_out, and_then_out_1 @[function.rs 166:5] + match and_then_out: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_2): + connect or_out, and_then_out @[function.rs 166:5] + match in_flight_ops[2]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_3): + connect and_then_out_2, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h2), 61)) @[unit_base.rs 66:17] + match in_flight_ops[3]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_4): + connect and_then_out_3, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h3), 61)) @[unit_base.rs 66:17] + wire or_out_1: Ty85 @[function.rs 166:5] + connect or_out_1, and_then_out_3 @[function.rs 166:5] + match and_then_out_2: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_5): + connect or_out_1, and_then_out_2 @[function.rs 166:5] + wire or_out_2: Ty85 @[function.rs 166:5] + connect or_out_2, or_out_1 @[function.rs 166:5] + match or_out: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_6): + connect or_out_2, or_out @[function.rs 166:5] + match in_flight_ops[4]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_7): + connect and_then_out_4, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h4), 61)) @[unit_base.rs 66:17] + match in_flight_ops[5]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_8): + connect and_then_out_5, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h5), 61)) @[unit_base.rs 66:17] + wire or_out_3: Ty85 @[function.rs 166:5] + connect or_out_3, and_then_out_5 @[function.rs 166:5] + match and_then_out_4: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_9): + connect or_out_3, and_then_out_4 @[function.rs 166:5] + match in_flight_ops[6]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_10): + connect and_then_out_6, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h6), 61)) @[unit_base.rs 66:17] + match in_flight_ops[7]: @[unit_base.rs 66:17] + HdlNone: + connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlNone) @[unit_base.rs 66:17] + HdlSome(_match_arm_value_11): + connect and_then_out_7, {|HdlNone, HdlSome: UInt<3>|}(HdlSome, tail(UInt<64>(0h7), 61)) @[unit_base.rs 66:17] + wire or_out_4: Ty85 @[function.rs 166:5] + connect or_out_4, and_then_out_7 @[function.rs 166:5] + match and_then_out_6: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_12): + connect or_out_4, and_then_out_6 @[function.rs 166:5] + wire or_out_5: Ty85 @[function.rs 166:5] + connect or_out_5, or_out_4 @[function.rs 166:5] + match or_out_3: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_13): + connect or_out_5, or_out_3 @[function.rs 166:5] + wire or_out_6: Ty85 @[function.rs 166:5] + connect or_out_6, or_out_5 @[function.rs 166:5] + match or_out_2: @[function.rs 166:5] + HdlNone: + skip + HdlSome(_match_arm_value_14): + connect or_out_6, or_out_2 @[function.rs 166:5] + connect input_index, or_out_6 @[unit_base.rs 62:5] + wire input_in_flight_op: Ty88 @[unit_base.rs 73:30] + connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 74:5] + wire firing_data: Ty62 @[ready_valid.rs 30:27] + connect firing_data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[ready_valid.rs 31:9] + when input_insn.ready: @[ready_valid.rs 33:9] + connect firing_data, input_insn.data @[ready_valid.rs 34:13] + match firing_data: @[unit_base.rs 76:5] + HdlNone: + skip + HdlSome(_match_arm_value_15): + wire input_in_flight_op_src_values: Ty86[3] @[unit_base.rs 79:13] + wire _array_literal_expr_1: Ty86[3] + wire _bundle_literal_expr: Ty65 + connect _bundle_literal_expr.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_1: Ty64 + connect _bundle_literal_expr_1.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_1.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr.flags, _bundle_literal_expr_1 + connect _array_literal_expr_1[0], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr) + wire _bundle_literal_expr_2: Ty65 + connect _bundle_literal_expr_2.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_3: Ty64 + connect _bundle_literal_expr_3.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_3.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr_2.flags, _bundle_literal_expr_3 + connect _array_literal_expr_1[1], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_2) + wire _bundle_literal_expr_4: Ty65 + connect _bundle_literal_expr_4.int_fp, UInt<64>(0h0) + wire _bundle_literal_expr_5: Ty64 + connect _bundle_literal_expr_5.pwr_ca_x86_cf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ca32_x86_af, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ov_x86_of, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_ov32_x86_df, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_lt_x86_sf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_gt_x86_pf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_cr_eq_x86_zf, UInt<1>(0h0) + connect _bundle_literal_expr_5.pwr_so, UInt<1>(0h0) + connect _bundle_literal_expr_4.flags, _bundle_literal_expr_5 + connect _array_literal_expr_1[2], {|HdlNone, HdlSome: Ty65|}(HdlSome, _bundle_literal_expr_4) + connect input_in_flight_op_src_values, _array_literal_expr_1 @[unit_base.rs 82:9] + match _match_arm_value_15: @[instruction.rs 502:1] + AddSub(_match_arm_value_16): + wire _bundle_literal_expr_6: Ty25 + wire _bundle_literal_expr_7: Ty23 + connect _bundle_literal_expr_7.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_6.unit_num, _bundle_literal_expr_7 + wire _bundle_literal_expr_8: Ty24 + connect _bundle_literal_expr_8.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_6.unit_out_reg, _bundle_literal_expr_8 + wire _cast_bundle_to_bits_expr: Ty57 + connect _cast_bundle_to_bits_expr.unit_num, _bundle_literal_expr_6.unit_num.adj_value + connect _cast_bundle_to_bits_expr.unit_out_reg, _bundle_literal_expr_6.unit_out_reg.value + wire _cast_to_bits_expr: UInt<6> + connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num) + when neq(_cast_to_bits_expr, _match_arm_value_16.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_9: Ty25 + wire _bundle_literal_expr_10: Ty23 + connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10 + wire _bundle_literal_expr_11: Ty24 + connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11 + wire _cast_bundle_to_bits_expr_1: Ty57 + connect _cast_bundle_to_bits_expr_1.unit_num, _bundle_literal_expr_9.unit_num.adj_value + connect _cast_bundle_to_bits_expr_1.unit_out_reg, _bundle_literal_expr_9.unit_out_reg.value + wire _cast_to_bits_expr_1: UInt<6> + connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num) + when neq(_cast_to_bits_expr_1, _match_arm_value_16.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_12: Ty25 + wire _bundle_literal_expr_13: Ty23 + connect _bundle_literal_expr_13.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_12.unit_num, _bundle_literal_expr_13 + wire _bundle_literal_expr_14: Ty24 + connect _bundle_literal_expr_14.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_12.unit_out_reg, _bundle_literal_expr_14 + wire _cast_bundle_to_bits_expr_2: Ty57 + connect _cast_bundle_to_bits_expr_2.unit_num, _bundle_literal_expr_12.unit_num.adj_value + connect _cast_bundle_to_bits_expr_2.unit_out_reg, _bundle_literal_expr_12.unit_out_reg.value + wire _cast_to_bits_expr_2: UInt<6> + connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num) + when neq(_cast_to_bits_expr_2, _match_arm_value_16.alu_common.common.src[2]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[2], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + AddSubI(_match_arm_value_17): + wire _bundle_literal_expr_15: Ty25 + wire _bundle_literal_expr_16: Ty23 + connect _bundle_literal_expr_16.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_15.unit_num, _bundle_literal_expr_16 + wire _bundle_literal_expr_17: Ty24 + connect _bundle_literal_expr_17.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_15.unit_out_reg, _bundle_literal_expr_17 + wire _cast_bundle_to_bits_expr_3: Ty57 + connect _cast_bundle_to_bits_expr_3.unit_num, _bundle_literal_expr_15.unit_num.adj_value + connect _cast_bundle_to_bits_expr_3.unit_out_reg, _bundle_literal_expr_15.unit_out_reg.value + wire _cast_to_bits_expr_3: UInt<6> + connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num) + when neq(_cast_to_bits_expr_3, _match_arm_value_17.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_18: Ty25 + wire _bundle_literal_expr_19: Ty23 + connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19 + wire _bundle_literal_expr_20: Ty24 + connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20 + wire _cast_bundle_to_bits_expr_4: Ty57 + connect _cast_bundle_to_bits_expr_4.unit_num, _bundle_literal_expr_18.unit_num.adj_value + connect _cast_bundle_to_bits_expr_4.unit_out_reg, _bundle_literal_expr_18.unit_out_reg.value + wire _cast_to_bits_expr_4: UInt<6> + connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num) + when neq(_cast_to_bits_expr_4, _match_arm_value_17.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + Logical(_match_arm_value_18): + wire _bundle_literal_expr_21: Ty25 + wire _bundle_literal_expr_22: Ty23 + connect _bundle_literal_expr_22.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22 + wire _bundle_literal_expr_23: Ty24 + connect _bundle_literal_expr_23.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23 + wire _cast_bundle_to_bits_expr_5: Ty57 + connect _cast_bundle_to_bits_expr_5.unit_num, _bundle_literal_expr_21.unit_num.adj_value + connect _cast_bundle_to_bits_expr_5.unit_out_reg, _bundle_literal_expr_21.unit_out_reg.value + wire _cast_to_bits_expr_5: UInt<6> + connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num) + when neq(_cast_to_bits_expr_5, _match_arm_value_18.alu_common.common.src[0]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[0], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_24: Ty25 + wire _bundle_literal_expr_25: Ty23 + connect _bundle_literal_expr_25.adj_value, tail(UInt<64>(0h0), 62) + connect _bundle_literal_expr_24.unit_num, _bundle_literal_expr_25 + wire _bundle_literal_expr_26: Ty24 + connect _bundle_literal_expr_26.value, tail(UInt<8>(0h0), 4) + connect _bundle_literal_expr_24.unit_out_reg, _bundle_literal_expr_26 + wire _cast_bundle_to_bits_expr_6: Ty57 + connect _cast_bundle_to_bits_expr_6.unit_num, _bundle_literal_expr_24.unit_num.adj_value + connect _cast_bundle_to_bits_expr_6.unit_out_reg, _bundle_literal_expr_24.unit_out_reg.value + wire _cast_to_bits_expr_6: UInt<6> + connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num) + when neq(_cast_to_bits_expr_6, _match_arm_value_18.alu_common.common.src[1]): @[unit_base.rs 88:13] + connect input_in_flight_op_src_values[1], {|HdlNone, HdlSome: Ty65|}(HdlNone) @[unit_base.rs 94:17] + wire _bundle_literal_expr_27: Ty87 + connect _bundle_literal_expr_27.mop, _match_arm_value_15 + connect _bundle_literal_expr_27.src_values, input_in_flight_op_src_values + connect input_in_flight_op, {|HdlNone, HdlSome: Ty87|}(HdlSome, _bundle_literal_expr_27) @[unit_base.rs 97:9] + match in_flight_ops[0]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_19): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_19, UInt<64>(0h0)): @[unit_base.rs 125:13] + connect in_flight_ops[0], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_20): + wire firing_data_1: Ty70 @[ready_valid.rs 30:27] + connect firing_data_1, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_1, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_1: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_21): + wire dest_reg: Ty24 @[instruction.rs 502:1] + match _match_arm_value_20.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_22): + connect dest_reg, _match_arm_value_22.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_23): + connect dest_reg, _match_arm_value_23.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_24): + connect dest_reg, _match_arm_value_24.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_21.which.value, dest_reg.value): @[unit_base.rs 113:17] + connect in_flight_ops[0], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[1]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_25): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_25, UInt<64>(0h1)): @[unit_base.rs 125:13] + connect in_flight_ops[1], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_26): + wire firing_data_2: Ty70 @[ready_valid.rs 30:27] + connect firing_data_2, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_2, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_2: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_27): + wire dest_reg_1: Ty24 @[instruction.rs 502:1] + match _match_arm_value_26.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_28): + connect dest_reg_1, _match_arm_value_28.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_29): + connect dest_reg_1, _match_arm_value_29.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_30): + connect dest_reg_1, _match_arm_value_30.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_27.which.value, dest_reg_1.value): @[unit_base.rs 113:17] + connect in_flight_ops[1], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[2]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_31): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_31, UInt<64>(0h2)): @[unit_base.rs 125:13] + connect in_flight_ops[2], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_32): + wire firing_data_3: Ty70 @[ready_valid.rs 30:27] + connect firing_data_3, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_3, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_3: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_33): + wire dest_reg_2: Ty24 @[instruction.rs 502:1] + match _match_arm_value_32.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_34): + connect dest_reg_2, _match_arm_value_34.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_35): + connect dest_reg_2, _match_arm_value_35.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_36): + connect dest_reg_2, _match_arm_value_36.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_33.which.value, dest_reg_2.value): @[unit_base.rs 113:17] + connect in_flight_ops[2], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[3]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_37): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_37, UInt<64>(0h3)): @[unit_base.rs 125:13] + connect in_flight_ops[3], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_38): + wire firing_data_4: Ty70 @[ready_valid.rs 30:27] + connect firing_data_4, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_4, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_4: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_39): + wire dest_reg_3: Ty24 @[instruction.rs 502:1] + match _match_arm_value_38.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_40): + connect dest_reg_3, _match_arm_value_40.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_41): + connect dest_reg_3, _match_arm_value_41.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_42): + connect dest_reg_3, _match_arm_value_42.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_39.which.value, dest_reg_3.value): @[unit_base.rs 113:17] + connect in_flight_ops[3], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[4]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_43): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_43, UInt<64>(0h4)): @[unit_base.rs 125:13] + connect in_flight_ops[4], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_44): + wire firing_data_5: Ty70 @[ready_valid.rs 30:27] + connect firing_data_5, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_5, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_5: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_45): + wire dest_reg_4: Ty24 @[instruction.rs 502:1] + match _match_arm_value_44.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_46): + connect dest_reg_4, _match_arm_value_46.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_47): + connect dest_reg_4, _match_arm_value_47.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_48): + connect dest_reg_4, _match_arm_value_48.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_45.which.value, dest_reg_4.value): @[unit_base.rs 113:17] + connect in_flight_ops[4], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[5]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_49): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_49, UInt<64>(0h5)): @[unit_base.rs 125:13] + connect in_flight_ops[5], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_50): + wire firing_data_6: Ty70 @[ready_valid.rs 30:27] + connect firing_data_6, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_6, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_6: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_51): + wire dest_reg_5: Ty24 @[instruction.rs 502:1] + match _match_arm_value_50.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_52): + connect dest_reg_5, _match_arm_value_52.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_53): + connect dest_reg_5, _match_arm_value_53.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_54): + connect dest_reg_5, _match_arm_value_54.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_51.which.value, dest_reg_5.value): @[unit_base.rs 113:17] + connect in_flight_ops[5], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[6]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_55): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_55, UInt<64>(0h6)): @[unit_base.rs 125:13] + connect in_flight_ops[6], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_56): + wire firing_data_7: Ty70 @[ready_valid.rs 30:27] + connect firing_data_7, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_7, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_7: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_57): + wire dest_reg_6: Ty24 @[instruction.rs 502:1] + match _match_arm_value_56.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_58): + connect dest_reg_6, _match_arm_value_58.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_59): + connect dest_reg_6, _match_arm_value_59.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_60): + connect dest_reg_6, _match_arm_value_60.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_57.which.value, dest_reg_6.value): @[unit_base.rs 113:17] + connect in_flight_ops[6], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] + match in_flight_ops[7]: @[unit_base.rs 107:9] + HdlNone: + match input_index: @[unit_base.rs 122:16] + HdlNone: + skip + HdlSome(_match_arm_value_61): + connect input_insn.ready, UInt<1>(0h1) @[unit_base.rs 123:13] + when eq(_match_arm_value_61, UInt<64>(0h7)): @[unit_base.rs 125:13] + connect in_flight_ops[7], input_in_flight_op @[unit_base.rs 126:17] + HdlSome(_match_arm_value_62): + wire firing_data_8: Ty70 @[ready_valid.rs 30:27] + connect firing_data_8, {|HdlNone, HdlSome: Ty69|}(HdlNone) @[ready_valid.rs 31:9] + when cancel_input.ready: @[ready_valid.rs 33:9] + connect firing_data_8, cancel_input.data @[ready_valid.rs 34:13] + match firing_data_8: @[unit_base.rs 109:13] + HdlNone: + skip + HdlSome(_match_arm_value_63): + wire dest_reg_7: Ty24 @[instruction.rs 502:1] + match _match_arm_value_62.mop: @[instruction.rs 502:1] + AddSub(_match_arm_value_64): + connect dest_reg_7, _match_arm_value_64.alu_common.common.dest @[instruction.rs 502:1] + AddSubI(_match_arm_value_65): + connect dest_reg_7, _match_arm_value_65.alu_common.common.dest @[instruction.rs 502:1] + Logical(_match_arm_value_66): + connect dest_reg_7, _match_arm_value_66.alu_common.common.dest @[instruction.rs 502:1] + when eq(_match_arm_value_63.which.value, dest_reg_7.value): @[unit_base.rs 113:17] + connect in_flight_ops[7], {|HdlNone, HdlSome: Ty87|}(HdlNone) @[unit_base.rs 115:21] ", }; // let sim_debug = format!("{sim:#?}");