speed up load/store and get it to work correctly
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
30 changed files with 105164 additions and 108712 deletions
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@ -5,10 +5,10 @@ use crate::{
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config::CpuConfig,
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instruction::{
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AddSubMOp, BranchMOp, CompareMOp, CompareMode, ConditionMode, LoadMOp, LoadStoreConversion,
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LoadStoreWidth, LogicalFlagsMOp, LogicalFlagsMOpImm, LogicalMOp, Lut4, MOp, MOpDestReg,
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MOpRegNum, MoveRegMOp, OutputIntegerMode, ReadSpecialMOp, ReadSpecialMOpImm,
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ShiftAmountOverflowBehavior, ShiftRotateDestLogicOp, ShiftRotateMOp, ShiftRotateMOpImm,
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ShiftRotateMode, StoreMOp, power_isa::PowerIsaSprEnum,
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LoadStoreOptions, LoadStoreWidth, LogicalFlagsMOp, LogicalFlagsMOpImm, LogicalMOp, Lut4,
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MOp, MOpDestReg, MOpRegNum, MoveRegMOp, OutputIntegerMode, ReadSpecialMOp,
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ReadSpecialMOpImm, ShiftAmountOverflowBehavior, ShiftRotateDestLogicOp, ShiftRotateMOp,
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ShiftRotateMOpImm, ShiftRotateMode, StoreMOp, power_isa::PowerIsaSprEnum,
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},
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powerisa_instructions_xml::{
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InstructionBitFieldName, InstructionBitFieldsInner, Instructions, TextLineItem,
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@ -916,7 +916,14 @@ impl DecodeState<'_> {
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}
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connect(
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*this.output[1],
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg],
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width,
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conversion,
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#[hdl]
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LoadStoreOptions { is_cacheable: true },
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),
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);
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},
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);
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@ -943,7 +950,14 @@ impl DecodeState<'_> {
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);
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connect(
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*this.output[1],
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg],
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width,
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conversion,
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#[hdl]
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LoadStoreOptions { is_cacheable: true },
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),
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);
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});
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} else if self.arguments == Some("RT,disp(RA)") {
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@ -968,7 +982,14 @@ impl DecodeState<'_> {
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);
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connect(
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*this.output[1],
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg],
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width,
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conversion,
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#[hdl]
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LoadStoreOptions { is_cacheable: true },
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),
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);
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});
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} else {
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@ -999,7 +1020,14 @@ impl DecodeState<'_> {
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);
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connect(
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*this.output[1],
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg],
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width,
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conversion,
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#[hdl]
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LoadStoreOptions { is_cacheable: true },
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),
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);
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});
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}
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@ -1073,6 +1101,8 @@ impl DecodeState<'_> {
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[ea_reg, gpr(rs)],
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width,
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LoadStoreConversion.ZeroExt(),
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#[hdl]
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LoadStoreOptions { is_cacheable: true },
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),
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);
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#[hdl]
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@ -3004,13 +3004,36 @@ pub enum LoadStoreConversion {
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// TODO(FP): add Power ISA's f32 in f64 format and RISC-V's ones-extension of floating-point
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}
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#[hdl(cmp_eq, custom_debug(sim))]
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pub struct LoadStoreOptions {
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/// if this is `false`, then if the address refers to a valid cache line, that cache line must have any dirty data
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/// written back to memory and then be set to invalid before performing the load/store.
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pub is_cacheable: Bool,
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}
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impl SimValueDebug for LoadStoreOptions {
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#[hdl]
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fn sim_value_debug(
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value: &<Self as Type>::SimValue,
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f: &mut fmt::Formatter<'_>,
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) -> fmt::Result {
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#[hdl(sim)]
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let Self { is_cacheable } = value;
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if **is_cacheable {
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f.write_str("cacheable")
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} else {
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f.write_str("uncacheable")
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}
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}
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}
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common_mop_struct! {
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#[mapped(<NewDestReg, NewSrcReg> LoadStoreCommonMOp<NewDestReg, NewSrcReg, SrcCount>)]
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#[hdl(cmp_eq)]
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/// `src0` is always the address to load from or store to.
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pub struct LoadStoreCommonMOp<DestReg: Type, SrcReg: Type, SrcCount: KnownSize> {
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#[common]
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pub common: CommonMOp<ConstUsize<3>, DestReg, SrcReg, SrcCount, CommonMOpDefaultImm<SrcCount>>,
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pub common: CommonMOp<ConstUsize<3>, DestReg, SrcReg, SrcCount, LoadStoreOptions>,
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pub width: LoadStoreWidth,
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pub conversion: LoadStoreConversion,
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}
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@ -3094,6 +3117,7 @@ impl<DestReg: Type, SrcReg: Type> LoadMOp<DestReg, SrcReg> {
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src: impl ToExpr<Type = Array<SrcReg, 1>>,
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width: impl ToExpr<Type = LoadStoreWidth>,
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conversion: impl ToExpr<Type = LoadStoreConversion>,
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options: impl ToExpr<Type = LoadStoreOptions>,
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) -> Expr<Target>
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where
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Self: MOpInto<Target>,
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@ -3108,7 +3132,7 @@ impl<DestReg: Type, SrcReg: Type> LoadMOp<DestReg, SrcReg> {
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prefix_pad: UInt::TYPE.zero(),
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dest,
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src,
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imm: CommonMOpDefaultImm::TYPE.zero(),
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imm: options,
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},
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width,
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conversion,
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@ -3144,6 +3168,7 @@ impl<DestReg: Type, SrcReg: Type> StoreMOp<DestReg, SrcReg> {
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src: impl ToExpr<Type = Array<SrcReg, 2>>,
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width: impl ToExpr<Type = LoadStoreWidth>,
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conversion: impl ToExpr<Type = LoadStoreConversion>,
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options: impl ToExpr<Type = LoadStoreOptions>,
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) -> Expr<Target>
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where
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Self: MOpInto<Target>,
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@ -3158,7 +3183,7 @@ impl<DestReg: Type, SrcReg: Type> StoreMOp<DestReg, SrcReg> {
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prefix_pad: UInt::TYPE.zero(),
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dest,
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src,
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imm: CommonMOpDefaultImm::TYPE.zero(),
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imm: options,
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},
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width,
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conversion,
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@ -203,6 +203,18 @@ pub struct UnitMOpCantCauseCancel<C: PhantomConstGet<CpuConfig>> {
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pub config: C,
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}
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/// This tells the Unit that:
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/// * Other Units can't cause any cancels for any µOps before [`Self::id`] (so all µOps before then are either assigned to this Unit or have reported that they can't cause a cancel or have finished without causing a cancel).
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///
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/// The rename/execute/retire logic guarantees:
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/// * [`Self::id`] refers to a µOp that is/was enqueued in this Unit.
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/// * This was not previously told to the unit.
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#[hdl(no_static)]
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pub struct UnitMOpOtherUnitsCantCauseCancelsBefore<C: PhantomConstGet<CpuConfig>> {
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pub id: MOpId,
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pub config: C,
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}
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/// Interface from the Rename/Execute/Retire control logic to a single Unit.
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///
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/// ## State diagram for a single µOp in a Unit
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@ -223,6 +235,9 @@ pub struct ExecuteToUnitInterface<C: PhantomConstGet<CpuConfig>> {
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pub inputs_ready: HdlOption<UnitInputsReady<C>>,
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/// if [`Self::unit_outputs_ready`] is `false`, then this is always [`HdlNone`]
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pub is_no_longer_speculative: HdlOption<UnitMOpIsNoLongerSpeculative<C>>,
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/// if [`Self::unit_outputs_ready`] is `false`, then this is always [`HdlNone`]
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pub other_units_cant_cause_cancels_before:
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HdlOption<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
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/// this uses [`Self::unit_outputs_ready`] as a shared ready flag
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#[hdl(flip)]
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pub cant_cause_cancel: HdlOption<UnitMOpCantCauseCancel<C>>,
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@ -466,6 +481,16 @@ impl MOpInUnitState {
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Self::FinishedAndOrCausedCancel => true,
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}
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}
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/// return `true` if this µOp has been enqueued and has neither finished nor caused a cancel.
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fn is_active(self) -> bool {
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match self {
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Self::NotYetEnqueued => false,
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Self::InputsNotReadySpeculative { .. }
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| Self::InputsReady { .. }
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| Self::OutputReady { .. } => true,
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Self::FinishedAndOrCausedCancel => false,
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}
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}
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}
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impl fmt::Debug for MOpInUnitState {
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@ -614,6 +639,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel,
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output,
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caused_cancel,
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other_units_cant_cause_cancels_before,
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sent_other_units_cant_cause_cancels_before,
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} in self.rob.renamed()
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{
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let masked_id = mop.id.as_int() as usize & mask;
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@ -631,6 +658,11 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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if *all_prior_mops_finished_and_or_caused_cancel {
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f.write_str("(apfc)")?;
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}
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if *sent_other_units_cant_cause_cancels_before {
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f.write_str("(socccb)")?;
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} else if *other_units_cant_cause_cancels_before {
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f.write_str("(occcb)")?;
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}
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if output.is_some() {
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f.write_str("(output)")?;
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}
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@ -647,7 +679,6 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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)
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})
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.to_string();
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// TODO
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}
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retval
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}
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@ -1219,6 +1250,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output: _,
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caused_cancel: _,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} in self.rob.renamed()
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{
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if *done_waiting_for_register_fences
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@ -1263,31 +1296,50 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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fn get_unit_mop_is_no_longer_speculative(
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&self,
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unit_index: usize,
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) -> SimValue<HdlOption<UnitMOpIsNoLongerSpeculative<C>>> {
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let ret_ty = HdlOption[UnitMOpIsNoLongerSpeculative[self.config]];
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) -> Option<SimValue<UnitMOpIsNoLongerSpeculative<C>>> {
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if self.is_canceling() {
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let retval = #[hdl(sim)]
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ret_ty.HdlNone();
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return retval; // separate variable to work around rust-analyzer parse error
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return None;
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}
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for rob in self.rob.renamed() {
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if rob.unit_index == unit_index
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&& !rob.is_speculative
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&& let Some(_) = rob.mop_in_unit_state.without_speculative()
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{
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let retval = #[hdl(sim)]
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ret_ty.HdlSome(
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return Some(
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#[hdl(sim)]
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UnitMOpIsNoLongerSpeculative::<_> {
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id: &rob.mop.id,
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config: self.config,
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},
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);
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return retval; // separate variable to work around rust-analyzer parse error
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}
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}
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#[hdl(sim)]
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ret_ty.HdlNone()
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None
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}
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#[hdl]
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fn get_unit_mop_other_units_cant_cause_cancels_before(
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&self,
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unit_index: usize,
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) -> Option<SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>> {
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if self.is_canceling() {
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return None;
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}
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for rob in self.rob.renamed() {
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if rob.unit_index == unit_index
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&& rob.other_units_cant_cause_cancels_before
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&& rob.is_speculative
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&& !rob.sent_other_units_cant_cause_cancels_before
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{
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return Some(
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#[hdl(sim)]
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UnitMOpOtherUnitsCantCauseCancelsBefore::<_> {
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id: &rob.mop.id,
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config: self.config,
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},
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);
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}
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}
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None
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}
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#[hdl]
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fn unit_output_ready(&mut self, output_ready: SimValue<UnitOutputReady<C>>) {
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@ -1310,6 +1362,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output,
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caused_cancel,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} = rob;
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assert!(output.is_none());
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assert!(caused_cancel.is_none());
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@ -1345,6 +1399,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output,
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caused_cancel,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} = self.rob.renamed_by_id_mut(&id);
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assert!(caused_cancel.is_none());
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let cancel_after_retire;
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@ -1459,6 +1515,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output,
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caused_cancel,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} = renamed_entry
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{
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if caused_cancel.is_some() {
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|
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@ -1584,6 +1642,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output: _,
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caused_cancel,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} in renamed_entries
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{
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assert_eq!(mop_in_unit_state, MOpInUnitState::FinishedAndOrCausedCancel);
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|
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@ -1618,24 +1678,24 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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};
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}
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for renamed in self.rob.renamed_mut() {
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let can_cause_cancel = match renamed.mop_in_unit_state {
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MOpInUnitState::NotYetEnqueued => true,
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MOpInUnitState::InputsNotReadySpeculative { can_cause_cancel } => can_cause_cancel,
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MOpInUnitState::InputsReady {
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speculative: _,
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can_cause_cancel,
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} => can_cause_cancel,
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MOpInUnitState::OutputReady {
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speculative: _,
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can_cause_cancel,
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} => can_cause_cancel,
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MOpInUnitState::FinishedAndOrCausedCancel => renamed.caused_cancel.is_some(),
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};
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renamed.is_speculative = false;
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if can_cause_cancel {
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if renamed.can_cause_cancel() {
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break;
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}
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}
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let mut unit_that_can_cause_cancel = None;
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for renamed in self.rob.renamed_mut() {
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if unit_that_can_cause_cancel.is_none_or(|v| v == renamed.unit_index) {
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renamed.other_units_cant_cause_cancels_before = true;
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}
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if renamed.can_cause_cancel() {
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let unit_that_can_cause_cancel =
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*unit_that_can_cause_cancel.get_or_insert(renamed.unit_index);
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if unit_that_can_cause_cancel != renamed.unit_index {
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break;
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}
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}
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}
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for renamed in self.rob.renamed_mut() {
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let RobEntry {
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is_register_fence,
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|
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@ -1647,6 +1707,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel,
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output: _,
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caused_cancel: _,
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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} = &renamed;
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if *is_register_fence {
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if !*all_prior_mops_finished_and_or_caused_cancel || *is_speculative {
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|
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@ -1671,6 +1733,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
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all_prior_mops_finished_and_or_caused_cancel: _,
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output: _,
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caused_cancel: Some(caused_cancel),
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other_units_cant_cause_cancels_before: _,
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sent_other_units_cant_cause_cancels_before: _,
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}) = first_renamed
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&& !*caused_cancel.cancel_after_retire
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{
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|
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@ -1719,6 +1783,7 @@ async fn rename_execute_retire_run(
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enqueue,
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inputs_ready,
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is_no_longer_speculative,
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||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _,
|
||||
output_ready: _,
|
||||
finish_cause_cancel: _,
|
||||
|
|
@ -1747,6 +1812,11 @@ async fn rename_execute_retire_run(
|
|||
state.get_unit_mop_is_no_longer_speculative(unit_index),
|
||||
)
|
||||
.await;
|
||||
sim.write(
|
||||
other_units_cant_cause_cancels_before,
|
||||
state.get_unit_mop_other_units_cant_cause_cancels_before(unit_index),
|
||||
)
|
||||
.await;
|
||||
sim.write(unit_outputs_ready, !is_canceling).await;
|
||||
}
|
||||
sim.wait_for_clock_edge(cd.clk).await;
|
||||
|
|
@ -1767,6 +1837,7 @@ async fn rename_execute_retire_run(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -1788,6 +1859,8 @@ async fn rename_execute_retire_run(
|
|||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output,
|
||||
caused_cancel,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
} = state.rob.renamed_by_id_mut(&enqueue.mop.id);
|
||||
assert!(output.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
|
|
@ -1809,6 +1882,8 @@ async fn rename_execute_retire_run(
|
|||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output,
|
||||
caused_cancel,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
} = state.rob.renamed_by_id_mut(&inputs_ready.mop.id);
|
||||
assert!(*done_waiting_for_register_fences);
|
||||
assert!(output.is_none());
|
||||
|
|
@ -1832,11 +1907,37 @@ async fn rename_execute_retire_run(
|
|||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output: _,
|
||||
caused_cancel: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
} = state.rob.renamed_by_id_mut(&is_no_longer_speculative.id);
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.without_speculative()
|
||||
.expect("UnitMOpIsNoLongerSpeculative is known to be valid");
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
assert!(!state.is_canceling());
|
||||
let RobEntry {
|
||||
is_register_fence: _,
|
||||
done_waiting_for_register_fences: _,
|
||||
mop: _,
|
||||
unit_index: _,
|
||||
mop_in_unit_state: _,
|
||||
is_speculative: _,
|
||||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output: _,
|
||||
caused_cancel: _,
|
||||
other_units_cant_cause_cancels_before,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
} = state
|
||||
.rob
|
||||
.renamed_by_id_mut(&other_units_cant_cause_cancels_before.id);
|
||||
assert!(*other_units_cant_cause_cancels_before);
|
||||
*sent_other_units_cant_cause_cancels_before = true;
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
|
||||
|
|
@ -1853,6 +1954,8 @@ async fn rename_execute_retire_run(
|
|||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output: _,
|
||||
caused_cancel,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
} = state.rob.renamed_by_id_mut(&id);
|
||||
assert!(caused_cancel.is_none());
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
|
|
@ -1959,6 +2062,7 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _,
|
||||
output_ready: _,
|
||||
finish_cause_cancel: _,
|
||||
|
|
@ -1992,6 +2096,12 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
|
|||
(is_no_longer_speculative.ty()).HdlNone(),
|
||||
)
|
||||
.await;
|
||||
sim.write(
|
||||
other_units_cant_cause_cancels_before,
|
||||
#[hdl(sim)]
|
||||
(other_units_cant_cause_cancels_before.ty()).HdlNone(),
|
||||
)
|
||||
.await;
|
||||
sim.write(unit_outputs_ready, false).await;
|
||||
}
|
||||
},
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ struct RobEntryDebugState<C: PhantomConstGet<CpuConfig>> {
|
|||
all_prior_mops_finished_and_or_caused_cancel: Bool,
|
||||
output: HdlOption<NextPcPredictorOp<C>>,
|
||||
caused_cancel: HdlOption<UnitCausedCancel<C>>,
|
||||
other_units_cant_cause_cancels_before: Bool,
|
||||
sent_other_units_cant_cause_cancels_before: Bool,
|
||||
}
|
||||
|
||||
impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
|
||||
|
|
@ -55,6 +57,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
|
|||
all_prior_mops_finished_and_or_caused_cancel: _,
|
||||
output,
|
||||
caused_cancel,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
} = self;
|
||||
#[hdl(sim)]
|
||||
Self {
|
||||
|
|
@ -69,6 +73,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
|
|||
output.HdlNone(),
|
||||
caused_cancel: #[hdl(sim)]
|
||||
caused_cancel.HdlNone(),
|
||||
other_units_cant_cause_cancels_before: false,
|
||||
sent_other_units_cant_cause_cancels_before: false,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -87,6 +93,8 @@ pub(crate) struct RobEntry<C: PhantomConstCpuConfig> {
|
|||
pub(crate) all_prior_mops_finished_and_or_caused_cancel: bool,
|
||||
pub(crate) output: Option<SimValue<NextPcPredictorOp<C>>>,
|
||||
pub(crate) caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
|
||||
pub(crate) other_units_cant_cause_cancels_before: bool,
|
||||
pub(crate) sent_other_units_cant_cause_cancels_before: bool,
|
||||
}
|
||||
|
||||
impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
||||
|
|
@ -105,6 +113,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
all_prior_mops_finished_and_or_caused_cancel: false,
|
||||
output: None,
|
||||
caused_cancel: None,
|
||||
other_units_cant_cause_cancels_before: false,
|
||||
sent_other_units_cant_cause_cancels_before: false,
|
||||
}
|
||||
}
|
||||
fn dest_reg(&self) -> Option<&SimValue<PRegNum<C>>> {
|
||||
|
|
@ -131,6 +141,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
all_prior_mops_finished_and_or_caused_cancel,
|
||||
output,
|
||||
caused_cancel,
|
||||
other_units_cant_cause_cancels_before,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
} = self;
|
||||
let ret_ty = RobEntryDebugState[config];
|
||||
#[hdl(sim)]
|
||||
|
|
@ -144,6 +156,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
all_prior_mops_finished_and_or_caused_cancel,
|
||||
output: output.into_sim_value_with_type(ret_ty.output),
|
||||
caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel),
|
||||
other_units_cant_cause_cancels_before,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
|
|
@ -173,6 +187,21 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
}
|
||||
}
|
||||
}
|
||||
pub(crate) fn can_cause_cancel(&self) -> bool {
|
||||
match self.mop_in_unit_state {
|
||||
MOpInUnitState::NotYetEnqueued => true,
|
||||
MOpInUnitState::InputsNotReadySpeculative { can_cause_cancel } => can_cause_cancel,
|
||||
MOpInUnitState::InputsReady {
|
||||
speculative: _,
|
||||
can_cause_cancel,
|
||||
} => can_cause_cancel,
|
||||
MOpInUnitState::OutputReady {
|
||||
speculative: _,
|
||||
can_cause_cancel,
|
||||
} => can_cause_cancel,
|
||||
MOpInUnitState::FinishedAndOrCausedCancel => self.caused_cancel.is_some(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
|
|
|
|||
|
|
@ -204,6 +204,7 @@ fn connect_to_unit_nop<C: Type + PhantomConstGet<CpuConfig>>(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _,
|
||||
output_ready: _,
|
||||
finish_cause_cancel: _,
|
||||
|
|
@ -218,6 +219,10 @@ fn connect_to_unit_nop<C: Type + PhantomConstGet<CpuConfig>>(
|
|||
is_no_longer_speculative,
|
||||
is_no_longer_speculative.ty().HdlNone(),
|
||||
);
|
||||
connect(
|
||||
other_units_cant_cause_cancels_before,
|
||||
other_units_cant_cause_cancels_before.ty().HdlNone(),
|
||||
);
|
||||
connect(unit_outputs_ready, false);
|
||||
connect(cancel_all.data, HdlNone());
|
||||
}
|
||||
|
|
@ -506,6 +511,7 @@ impl<C: PhantomConstCpuConfig, MaxMOpCount: Size> DecodeAndRunSingleInsnState<C,
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _, // we don't track if it can cause a cancel
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -513,6 +519,10 @@ impl<C: PhantomConstCpuConfig, MaxMOpCount: Size> DecodeAndRunSingleInsnState<C,
|
|||
cancel_all,
|
||||
config: _,
|
||||
} = to_unit;
|
||||
connect(
|
||||
other_units_cant_cause_cancels_before,
|
||||
other_units_cant_cause_cancels_before.ty().HdlNone(),
|
||||
);
|
||||
connect(unit_outputs_ready, true);
|
||||
connect(cancel_all.data, HdlNone());
|
||||
#[hdl]
|
||||
|
|
|
|||
|
|
@ -1260,6 +1260,7 @@ pub fn alu_branch(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative: _, // we don't care about being speculative for these instructions
|
||||
other_units_cant_cause_cancels_before: _, // we don't care about other instructions being able to cause cancels
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
|
|||
|
|
@ -11,9 +11,10 @@ use crate::{
|
|||
next_pc::{CallStackOp, SimValueDefault},
|
||||
register::{PRegFlags, PRegValue},
|
||||
rename_execute_retire::{
|
||||
ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp, UnitEnqueue,
|
||||
UnitFinishCauseCancel, UnitInputsReady, UnitMOpCantCauseCancel,
|
||||
UnitMOpIsNoLongerSpeculative, UnitOutputReady,
|
||||
ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
|
||||
UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel, UnitInputsReady,
|
||||
UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
|
||||
UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady,
|
||||
},
|
||||
unit::{DynUnit, DynUnitWrapper, RenamedMOpFilter, UnitIO, UnitKind, UnitMOp, UnitTrait},
|
||||
};
|
||||
|
|
@ -53,6 +54,8 @@ pub struct DCacheStart<C: PhantomConstGet<CpuConfig>> {
|
|||
}
|
||||
|
||||
#[hdl]
|
||||
/// All errors here cause asynchronous error interrupts, so anything requiring precise exceptions (e.g. page
|
||||
/// faults) must happen before the D-cache.
|
||||
pub enum DCacheFinishStatus {
|
||||
/// The operation finished successfully
|
||||
Success,
|
||||
|
|
@ -116,7 +119,7 @@ pub struct LoadStoreToDCacheInterface<C: PhantomConstGet<CpuConfig>> {
|
|||
/// Operations started through `start` must maintain sequential consistency -- so earlier operations
|
||||
/// can't appear to have happened after later operations.
|
||||
pub start: ReadyValid<DCacheStart<C>>,
|
||||
/// operations must finish in the same order they started.
|
||||
/// Operations must finish in the same order they started.
|
||||
#[hdl(flip)]
|
||||
pub finish: ReadyValid<DCacheFinish<C>>,
|
||||
/// It's valid for `start_speculative_load.ready` to be `false` at any time (or even always)
|
||||
|
|
@ -200,11 +203,10 @@ struct Op<C: PhantomConstCpuConfig> {
|
|||
pc: SimValue<UInt<64>>,
|
||||
size_in_bytes: u8,
|
||||
mop: SimValue<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
|
||||
/// earlier instructions can cause a cancel, so this instruction is still speculative.
|
||||
/// not to be confused with this instruction being able to cause a cancel.
|
||||
is_speculative: bool,
|
||||
other_units_cant_cause_cancels_before: bool,
|
||||
src_values: Option<[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN]>,
|
||||
dest_value: Option<SimValue<TraceAsString<PRegValue>>>,
|
||||
caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
|
||||
sent_cant_cause_cancel: bool,
|
||||
sent_output_ready: bool,
|
||||
state: OpState,
|
||||
|
|
@ -218,15 +220,16 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Op<C> {
|
|||
pc,
|
||||
size_in_bytes,
|
||||
mop,
|
||||
is_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
src_values,
|
||||
dest_value,
|
||||
caused_cancel,
|
||||
sent_cant_cause_cancel,
|
||||
sent_output_ready,
|
||||
state,
|
||||
} = self;
|
||||
if *is_speculative {
|
||||
f.write_str("(s)")?;
|
||||
if *other_units_cant_cause_cancels_before {
|
||||
f.write_str("(occcb)")?;
|
||||
}
|
||||
if *sent_cant_cause_cancel {
|
||||
f.write_str("(sccc)")?;
|
||||
|
|
@ -234,6 +237,18 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Op<C> {
|
|||
if *sent_output_ready {
|
||||
f.write_str("(sor)")?;
|
||||
}
|
||||
if let Some(caused_cancel) = caused_cancel {
|
||||
#[hdl(sim)]
|
||||
let UnitCausedCancel::<_> {
|
||||
start_at_pc,
|
||||
cancel_after_retire,
|
||||
config: _,
|
||||
} = caused_cancel;
|
||||
write!(
|
||||
f,
|
||||
"(caused_cancel start_at_pc={start_at_pc},cancel_after_retire={cancel_after_retire})"
|
||||
)?;
|
||||
}
|
||||
write!(
|
||||
f,
|
||||
"({state}) id={id:?} pc={pc:?} sz={size_in_bytes}: {mop:?}"
|
||||
|
|
@ -262,9 +277,10 @@ impl<C: PhantomConstCpuConfig> Op<C> {
|
|||
pc,
|
||||
size_in_bytes,
|
||||
mop,
|
||||
is_speculative: true,
|
||||
other_units_cant_cause_cancels_before: false,
|
||||
src_values: None,
|
||||
dest_value: None,
|
||||
caused_cancel: None,
|
||||
sent_cant_cause_cancel: false,
|
||||
sent_output_ready: false,
|
||||
state: OpState::InputNotReady,
|
||||
|
|
@ -299,10 +315,7 @@ impl<C: PhantomConstCpuConfig> Op<C> {
|
|||
LoadStoreMOp::<_, _>::Store(mop) => self.access_range_helper(&mop.load_store_common),
|
||||
}
|
||||
}
|
||||
fn can_cause_cancel(&self) -> bool {
|
||||
if self.is_speculative {
|
||||
return true;
|
||||
}
|
||||
fn can_cause_async_error(&self) -> bool {
|
||||
match self.state {
|
||||
OpState::InputNotReady
|
||||
| OpState::StartedSpeculativeLoad
|
||||
|
|
@ -312,6 +325,24 @@ impl<C: PhantomConstCpuConfig> Op<C> {
|
|||
}
|
||||
}
|
||||
}
|
||||
fn can_cause_cancel(&self) -> bool {
|
||||
match self.state {
|
||||
OpState::InputNotReady
|
||||
| OpState::StartedSpeculativeLoad
|
||||
| OpState::FinishedSpeculativeLoad
|
||||
| OpState::StartedLoadStore => true,
|
||||
OpState::FinishedLoadStore => self.dest_value.is_none(),
|
||||
}
|
||||
}
|
||||
fn blocks_d_cache_start_for_later_ops(&self) -> bool {
|
||||
match self.state {
|
||||
OpState::InputNotReady => true,
|
||||
OpState::StartedSpeculativeLoad => true,
|
||||
OpState::FinishedSpeculativeLoad => self.dest_value.is_none(),
|
||||
OpState::StartedLoadStore => false,
|
||||
OpState::FinishedLoadStore => false,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl(get(|c| c.rob_size.get().next_power_of_two()))]
|
||||
|
|
@ -324,18 +355,27 @@ type PhantomConstUnitIndex = PhantomConst<usize>;
|
|||
pub struct LoadStoreDebugState<C: PhantomConstGet<CpuConfig>> {
|
||||
global_state: GlobalState,
|
||||
ops: ArrayType<TraceAsString<OpDebugState>, OpsDebugLen<C>>,
|
||||
async_error: Bool,
|
||||
canceling: Bool,
|
||||
config: C,
|
||||
unit_index: PhantomConstUnitIndex,
|
||||
filter: LoadStoreFilter,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
struct AsyncErrorData<C: PhantomConstCpuConfig> {
|
||||
caused_cancel: SimValue<UnitCausedCancel<C>>,
|
||||
caused_async_error_id: SimValue<MOpId>,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
struct LoadStoreState<C: PhantomConstCpuConfig> {
|
||||
global_state: SimValue<GlobalState>,
|
||||
ops: VecDeque<Op<C>>,
|
||||
d_cache_start: Option<SimValue<DCacheStart<C>>>,
|
||||
d_cache_start_speculative_load: Option<SimValue<DCacheStartSpeculativeLoad<C>>>,
|
||||
async_error: bool,
|
||||
async_error_data: Option<AsyncErrorData<C>>,
|
||||
canceling: bool,
|
||||
config: C,
|
||||
unit_index: usize,
|
||||
|
|
@ -349,6 +389,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
ops: VecDeque::new(),
|
||||
d_cache_start: None,
|
||||
d_cache_start_speculative_load: None,
|
||||
async_error: false,
|
||||
async_error_data: None,
|
||||
canceling: false,
|
||||
config,
|
||||
unit_index,
|
||||
|
|
@ -364,6 +406,9 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
d_cache_start: _,
|
||||
// not included in debug state since it's identical to `to_d_cache.start_speculative_load.data`
|
||||
d_cache_start_speculative_load: _,
|
||||
async_error,
|
||||
// always None by this point
|
||||
async_error_data: _,
|
||||
canceling,
|
||||
config,
|
||||
unit_index,
|
||||
|
|
@ -378,21 +423,26 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
LoadStoreDebugState::<_> {
|
||||
global_state,
|
||||
ops,
|
||||
async_error,
|
||||
canceling,
|
||||
config,
|
||||
unit_index: PhantomConst::new_sized(unit_index),
|
||||
filter,
|
||||
}
|
||||
}
|
||||
fn try_op_by_id(&mut self, id: &<MOpId as Type>::SimValue) -> Option<&mut Op<C>> {
|
||||
self.ops.iter_mut().find(|op| *op.id == *id)
|
||||
}
|
||||
#[track_caller]
|
||||
fn op_by_id(&mut self, id: &<MOpId as Type>::SimValue) -> &mut Op<C> {
|
||||
match self.ops.iter_mut().find(|op| *op.id == *id) {
|
||||
match self.try_op_by_id(id) {
|
||||
Some(op) => op,
|
||||
None => panic!("can't find load_store Op with id {id:?}"),
|
||||
}
|
||||
}
|
||||
fn from_execute_enqueue_ready(&self) -> bool {
|
||||
!self.canceling
|
||||
&& !self.async_error
|
||||
&& self.ops.len() < self.config.get().unit_max_in_flight(self.unit_index).get()
|
||||
}
|
||||
#[hdl]
|
||||
|
|
@ -439,14 +489,28 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
) {
|
||||
#[hdl(sim)]
|
||||
let UnitMOpIsNoLongerSpeculative::<_> { id, config: _ } = is_no_longer_speculative;
|
||||
self.op_by_id(&id).is_speculative = false;
|
||||
self.op_by_id(&id).other_units_cant_cause_cancels_before = true;
|
||||
}
|
||||
#[hdl]
|
||||
fn from_execute_other_units_cant_cause_cancels_before(
|
||||
&mut self,
|
||||
other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
|
||||
) {
|
||||
#[hdl(sim)]
|
||||
let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
|
||||
other_units_cant_cause_cancels_before;
|
||||
self.op_by_id(&id).other_units_cant_cause_cancels_before = true;
|
||||
}
|
||||
#[hdl]
|
||||
fn from_execute_cant_cause_cancel(&self) -> Option<SimValue<UnitMOpCantCauseCancel<C>>> {
|
||||
if self.canceling {
|
||||
if self.canceling || self.async_error {
|
||||
return None;
|
||||
}
|
||||
for op in &self.ops {
|
||||
let can_cause_async_error = self.ops.iter().any(|op| op.can_cause_async_error());
|
||||
for (index, op) in self.ops.iter().enumerate() {
|
||||
if can_cause_async_error && index + 1 == self.ops.len() {
|
||||
return None;
|
||||
}
|
||||
if op.sent_cant_cause_cancel || op.can_cause_cancel() {
|
||||
continue;
|
||||
}
|
||||
|
|
@ -518,14 +582,15 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
pc: _,
|
||||
size_in_bytes: _,
|
||||
mop: _,
|
||||
is_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
src_values: _,
|
||||
dest_value,
|
||||
dest_value: _,
|
||||
caused_cancel,
|
||||
sent_cant_cause_cancel: _,
|
||||
sent_output_ready,
|
||||
state,
|
||||
} = self.ops.front()?;
|
||||
if *is_speculative {
|
||||
if !*other_units_cant_cause_cancels_before {
|
||||
return None;
|
||||
}
|
||||
let retval_ty = UnitFinishCauseCancel[self.config];
|
||||
|
|
@ -533,7 +598,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
OpState::InputNotReady => None,
|
||||
OpState::StartedSpeculativeLoad => None,
|
||||
OpState::FinishedSpeculativeLoad => {
|
||||
if *sent_output_ready {
|
||||
if *sent_output_ready || caused_cancel.is_some() {
|
||||
// TODO: handle when some other CPU stores to the same cache line before the speculative
|
||||
// load sends UnitFinishCauseCancel -- that needs to make the load cause a cancel so it
|
||||
// can be redone with the correct data. That enforces sequential consistency.
|
||||
|
|
@ -541,8 +606,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
#[hdl(sim)]
|
||||
UnitFinishCauseCancel::<_> {
|
||||
id,
|
||||
caused_cancel: #[hdl(sim)]
|
||||
(retval_ty.caused_cancel).HdlNone(),
|
||||
caused_cancel: caused_cancel
|
||||
.into_sim_value_with_type(retval_ty.caused_cancel),
|
||||
config: self.config,
|
||||
},
|
||||
)
|
||||
|
|
@ -552,16 +617,13 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
}
|
||||
OpState::StartedLoadStore => None,
|
||||
OpState::FinishedLoadStore => {
|
||||
if dest_value.is_none() {
|
||||
todo!("load/store caused error -- need to translate to a cancel");
|
||||
}
|
||||
if *sent_output_ready {
|
||||
if *sent_output_ready || caused_cancel.is_some() {
|
||||
Some(
|
||||
#[hdl(sim)]
|
||||
UnitFinishCauseCancel::<_> {
|
||||
id,
|
||||
caused_cancel: #[hdl(sim)]
|
||||
(retval_ty.caused_cancel).HdlNone(),
|
||||
caused_cancel: caused_cancel
|
||||
.into_sim_value_with_type(retval_ty.caused_cancel),
|
||||
config: self.config,
|
||||
},
|
||||
)
|
||||
|
|
@ -630,7 +692,12 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
};
|
||||
}
|
||||
DCacheFinishStatus::MemoryError(error) => {
|
||||
todo!("{error:?}")
|
||||
// cause an async error:
|
||||
// mark this instruction as completed so the rename/execute/retire logic will progress to
|
||||
// the instruction we mark as canceled.
|
||||
op.dest_value = Some(PRegValue::zeroed_sim().into_trace_as_string());
|
||||
let id = op.id.clone();
|
||||
self.cause_async_error(error, id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -694,8 +761,22 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
}
|
||||
#[hdl]
|
||||
fn canceling_step(&mut self) {
|
||||
self.d_cache_start = None;
|
||||
self.d_cache_start_speculative_load = None;
|
||||
let LoadStoreState {
|
||||
global_state: _,
|
||||
ops,
|
||||
d_cache_start,
|
||||
d_cache_start_speculative_load,
|
||||
async_error,
|
||||
async_error_data,
|
||||
canceling,
|
||||
config: _,
|
||||
unit_index: _,
|
||||
filter: _,
|
||||
} = self;
|
||||
*async_error = false;
|
||||
*async_error_data = None;
|
||||
*d_cache_start = None;
|
||||
*d_cache_start_speculative_load = None;
|
||||
let finished_canceling = |op: &mut Op<_>| match op.state {
|
||||
OpState::InputNotReady => true,
|
||||
OpState::StartedSpeculativeLoad => false,
|
||||
|
|
@ -703,18 +784,16 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
OpState::StartedLoadStore => false,
|
||||
OpState::FinishedLoadStore => true,
|
||||
};
|
||||
while let Some(_) = self.ops.pop_front_if(finished_canceling) {}
|
||||
if self.ops.is_empty() {
|
||||
self.canceling = false;
|
||||
while let Some(_) = ops.pop_front_if(finished_canceling) {}
|
||||
if ops.is_empty() {
|
||||
*canceling = false;
|
||||
}
|
||||
}
|
||||
fn is_cacheable_load(mop: &SimValue<LoadMOp<PRegNum<C>, PRegNum<C>>>) -> bool {
|
||||
// TODO: implement un-cacheable loads
|
||||
true
|
||||
*mop.load_store_common.common.imm.is_cacheable
|
||||
}
|
||||
fn is_cacheable_store(mop: &SimValue<StoreMOp<PRegNum<C>, PRegNum<C>>>) -> bool {
|
||||
// TODO: implement un-cacheable stores
|
||||
true
|
||||
*mop.load_store_common.common.imm.is_cacheable
|
||||
}
|
||||
#[hdl]
|
||||
fn process_load_data(
|
||||
|
|
@ -809,27 +888,85 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
}
|
||||
#[hdl]
|
||||
fn step(&mut self) {
|
||||
if self.canceling {
|
||||
let Self {
|
||||
global_state: _,
|
||||
ops,
|
||||
d_cache_start,
|
||||
d_cache_start_speculative_load,
|
||||
async_error,
|
||||
async_error_data,
|
||||
canceling,
|
||||
config,
|
||||
unit_index: _,
|
||||
filter: _,
|
||||
} = self;
|
||||
if *canceling {
|
||||
return self.canceling_step();
|
||||
}
|
||||
self.d_cache_start = None;
|
||||
self.d_cache_start_speculative_load = None;
|
||||
*d_cache_start = None;
|
||||
*d_cache_start_speculative_load = None;
|
||||
if *async_error {
|
||||
if let Some(AsyncErrorData {
|
||||
caused_cancel,
|
||||
caused_async_error_id,
|
||||
}) = async_error_data.take()
|
||||
{
|
||||
let mut earliest_op_that_can_be_canceled = None;
|
||||
for op in self.ops.iter_mut().rev() {
|
||||
if op.id == caused_async_error_id {
|
||||
// must not have instructions enqueued earlier than this one cause a cancel
|
||||
earliest_op_that_can_be_canceled = Some(op);
|
||||
break;
|
||||
}
|
||||
if op.sent_cant_cause_cancel {
|
||||
continue;
|
||||
}
|
||||
let state = op.state;
|
||||
if op.can_cause_cancel() {
|
||||
earliest_op_that_can_be_canceled = Some(op);
|
||||
}
|
||||
match state {
|
||||
OpState::InputNotReady
|
||||
| OpState::StartedSpeculativeLoad
|
||||
| OpState::FinishedSpeculativeLoad => {
|
||||
// no globally visible changes, so we can have earlier instructions cause a cancel
|
||||
}
|
||||
OpState::StartedLoadStore | OpState::FinishedLoadStore => {
|
||||
// changes are already or will be globally visible, so this instruction
|
||||
// must retire, so we can't cancel earlier instructions.
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
let Some(op) = earliest_op_that_can_be_canceled else {
|
||||
unreachable!();
|
||||
};
|
||||
op.caused_cancel = Some(caused_cancel);
|
||||
}
|
||||
return;
|
||||
}
|
||||
let store_queue_capacity = 4; // TODO: make configurable
|
||||
struct StoreQueueEntry {
|
||||
access_range: AddressRange,
|
||||
data: [u8; MAX_LOAD_STORE_SIZE],
|
||||
}
|
||||
let mut store_queue = Vec::<StoreQueueEntry>::with_capacity(store_queue_capacity);
|
||||
for op in &mut self.ops {
|
||||
let mut d_cache_start_blocked = false;
|
||||
for op in ops {
|
||||
let access_range = op.access_range();
|
||||
let d_cache_start_blocked = std::mem::replace(
|
||||
&mut d_cache_start_blocked,
|
||||
op.blocks_d_cache_start_for_later_ops(),
|
||||
);
|
||||
let Op {
|
||||
ref id,
|
||||
pc: _,
|
||||
size_in_bytes: _,
|
||||
ref mop,
|
||||
is_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
ref src_values,
|
||||
ref mut dest_value,
|
||||
caused_cancel: _,
|
||||
sent_cant_cause_cancel: _,
|
||||
sent_output_ready: _,
|
||||
ref mut state,
|
||||
|
|
@ -871,21 +1008,26 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
let mask = std::array::from_fn(|i| i < size.get() as usize);
|
||||
match state {
|
||||
OpState::InputNotReady
|
||||
if is_speculative && !blocking_store && is_cacheable =>
|
||||
if !other_units_cant_cause_cancels_before
|
||||
&& !blocking_store
|
||||
&& is_cacheable =>
|
||||
{
|
||||
self.d_cache_start_speculative_load.get_or_insert_with(|| {
|
||||
d_cache_start_speculative_load.get_or_insert_with(|| {
|
||||
#[hdl(sim)]
|
||||
DCacheStartSpeculativeLoad::<_> {
|
||||
id,
|
||||
address,
|
||||
mask,
|
||||
config: self.config,
|
||||
config,
|
||||
}
|
||||
});
|
||||
}
|
||||
OpState::InputNotReady | OpState::FinishedSpeculativeLoad => {
|
||||
if !is_speculative && dest_value.is_none() {
|
||||
self.d_cache_start.get_or_insert_with(|| {
|
||||
if other_units_cant_cause_cancels_before
|
||||
&& dest_value.is_none()
|
||||
&& !d_cache_start_blocked
|
||||
{
|
||||
d_cache_start.get_or_insert_with(|| {
|
||||
#[hdl(sim)]
|
||||
DCacheStart::<_> {
|
||||
id,
|
||||
|
|
@ -896,7 +1038,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
),
|
||||
address,
|
||||
data_and_mask: mask.map(|v| v.then_some(0)),
|
||||
config: self.config,
|
||||
config,
|
||||
}
|
||||
});
|
||||
}
|
||||
|
|
@ -912,9 +1054,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
pc: _,
|
||||
size_in_bytes: _,
|
||||
mop: _,
|
||||
is_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
ref src_values,
|
||||
ref dest_value,
|
||||
caused_cancel: _,
|
||||
sent_cant_cause_cancel: _,
|
||||
sent_output_ready: _,
|
||||
state,
|
||||
|
|
@ -939,8 +1082,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
}
|
||||
match state {
|
||||
OpState::InputNotReady => {
|
||||
if !is_speculative {
|
||||
self.d_cache_start.get_or_insert_with(|| {
|
||||
if other_units_cant_cause_cancels_before && !d_cache_start_blocked {
|
||||
d_cache_start.get_or_insert_with(|| {
|
||||
#[hdl(sim)]
|
||||
DCacheStart::<_> {
|
||||
id,
|
||||
|
|
@ -951,7 +1094,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
),
|
||||
address,
|
||||
data_and_mask,
|
||||
config: self.config,
|
||||
config,
|
||||
}
|
||||
});
|
||||
}
|
||||
|
|
@ -966,8 +1109,36 @@ impl<C: PhantomConstCpuConfig> LoadStoreState<C> {
|
|||
}
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
fn cause_async_error(
|
||||
&mut self,
|
||||
error: SimValue<MemoryOperationErrorKind>,
|
||||
caused_async_error_id: SimValue<MOpId>,
|
||||
) {
|
||||
if self.async_error {
|
||||
return; // we're already handling an error, ignore the new error
|
||||
}
|
||||
self.async_error = true;
|
||||
// TODO: set other registers properly for an interrupt
|
||||
let start_at_pc = #[hdl(sim)]
|
||||
match error {
|
||||
MemoryOperationErrorKind::Generic => MACHINE_CHECK_INTERRUPT_PC,
|
||||
};
|
||||
let caused_cancel = #[hdl(sim)]
|
||||
UnitCausedCancel::<_> {
|
||||
start_at_pc,
|
||||
cancel_after_retire: true,
|
||||
config: self.config,
|
||||
};
|
||||
self.async_error_data = Some(AsyncErrorData {
|
||||
caused_cancel,
|
||||
caused_async_error_id,
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
pub const MACHINE_CHECK_INTERRUPT_PC: u64 = 0x0000_0000_0000_0200;
|
||||
|
||||
#[hdl]
|
||||
async fn load_store_impl(
|
||||
config: PhantomConst<CpuConfig>,
|
||||
|
|
@ -988,6 +1159,7 @@ async fn load_store_impl(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -1042,6 +1214,7 @@ async fn load_store_impl(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -1066,6 +1239,15 @@ async fn load_store_impl(
|
|||
{
|
||||
state.from_execute_is_no_longer_speculative(is_no_longer_speculative);
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
state.from_execute_other_units_cant_cause_cancels_before(
|
||||
other_units_cant_cause_cancels_before,
|
||||
);
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
|
||||
|
|
@ -1221,6 +1403,7 @@ pub fn load_store(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
|
|||
96669
crates/cpu/tests/expected/load_store_unit_random.vcd
generated
96669
crates/cpu/tests/expected/load_store_unit_random.vcd
generated
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
7915
crates/cpu/tests/expected/rename_execute_retire_head_n1.vcd
generated
7915
crates/cpu/tests/expected/rename_execute_retire_head_n1.vcd
generated
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
11250
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd
generated
11250
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd
generated
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
|
|||
$var string 1 l(Ah_ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 ;aq90 \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 l{J$] id $end
|
||||
$var string 1 Nix(+ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 zJgj& \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -3327,7 +3334,9 @@ $var string 1 jQG"X config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P width $end
|
||||
$var string 1 jj\+I conversion $end
|
||||
|
|
@ -3369,7 +3378,9 @@ $var string 1 "^.&M config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9 is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@ width $end
|
||||
$var string 1 "-Sp[ conversion $end
|
||||
|
|
@ -4154,7 +4165,9 @@ $var string 1 :G)2\ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ width $end
|
||||
$var string 1 ?`G6o conversion $end
|
||||
|
|
@ -4196,7 +4209,9 @@ $var string 1 agwXx config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg width $end
|
||||
$var string 1 }v,d conversion $end
|
||||
|
|
@ -4818,7 +4833,9 @@ $var string 1 jQG"X" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P" width $end
|
||||
$var string 1 jj\+I" conversion $end
|
||||
|
|
@ -4860,7 +4877,9 @@ $var string 1 "^.&M" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@" width $end
|
||||
$var string 1 "-Sp[" conversion $end
|
||||
|
|
@ -5645,7 +5664,9 @@ $var string 1 :G)2\" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ" width $end
|
||||
$var string 1 ?`G6o" conversion $end
|
||||
|
|
@ -5687,7 +5708,9 @@ $var string 1 agwXx" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg" width $end
|
||||
$var string 1 }v,d!" conversion $end
|
||||
|
|
@ -6328,7 +6351,9 @@ $var string 1 )?xf* config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ(' width $end
|
||||
$var string 1 ;FwPz conversion $end
|
||||
|
|
@ -6370,7 +6395,9 @@ $var string 1 :W!m> config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l= imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa width $end
|
||||
$var string 1 9hG?R conversion $end
|
||||
|
|
@ -7025,7 +7052,9 @@ $var string 1 jQG"X# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P# width $end
|
||||
$var string 1 jj\+I# conversion $end
|
||||
|
|
@ -7067,7 +7096,9 @@ $var string 1 "^.&M# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@# width $end
|
||||
$var string 1 "-Sp[# conversion $end
|
||||
|
|
@ -7852,7 +7883,9 @@ $var string 1 :G)2\# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ# width $end
|
||||
$var string 1 ?`G6o# conversion $end
|
||||
|
|
@ -7894,7 +7927,9 @@ $var string 1 agwXx# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg# width $end
|
||||
$var string 1 }v,d!# conversion $end
|
||||
|
|
@ -8516,7 +8551,9 @@ $var string 1 jQG"X$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P$ width $end
|
||||
$var string 1 jj\+I$ conversion $end
|
||||
|
|
@ -8558,7 +8595,9 @@ $var string 1 "^.&M$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@$ width $end
|
||||
$var string 1 "-Sp[$ conversion $end
|
||||
|
|
@ -9343,7 +9382,9 @@ $var string 1 :G)2\$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ$ width $end
|
||||
$var string 1 ?`G6o$ conversion $end
|
||||
|
|
@ -9385,7 +9426,9 @@ $var string 1 agwXx$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg$ width $end
|
||||
$var string 1 }v,d!$ conversion $end
|
||||
|
|
@ -10026,7 +10069,9 @@ $var string 1 )?xf*" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ('" width $end
|
||||
$var string 1 ;FwPz" conversion $end
|
||||
|
|
@ -10068,7 +10113,9 @@ $var string 1 :W!m>" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l=" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa" width $end
|
||||
$var string 1 9hG?R" conversion $end
|
||||
|
|
@ -10723,7 +10770,9 @@ $var string 1 jQG"X% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P% width $end
|
||||
$var string 1 jj\+I% conversion $end
|
||||
|
|
@ -10765,7 +10814,9 @@ $var string 1 "^.&M% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@% width $end
|
||||
$var string 1 "-Sp[% conversion $end
|
||||
|
|
@ -11550,7 +11601,9 @@ $var string 1 :G)2\% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ% width $end
|
||||
$var string 1 ?`G6o% conversion $end
|
||||
|
|
@ -11592,7 +11645,9 @@ $var string 1 agwXx% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg% width $end
|
||||
$var string 1 }v,d!% conversion $end
|
||||
|
|
@ -12214,7 +12269,9 @@ $var string 1 jQG"X& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P& width $end
|
||||
$var string 1 jj\+I& conversion $end
|
||||
|
|
@ -12256,7 +12313,9 @@ $var string 1 "^.&M& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@& width $end
|
||||
$var string 1 "-Sp[& conversion $end
|
||||
|
|
@ -13041,7 +13100,9 @@ $var string 1 :G)2\& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ& width $end
|
||||
$var string 1 ?`G6o& conversion $end
|
||||
|
|
@ -13083,7 +13144,9 @@ $var string 1 agwXx& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg& width $end
|
||||
$var string 1 }v,d!& conversion $end
|
||||
|
|
@ -13724,7 +13787,9 @@ $var string 1 )?xf*# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ('# width $end
|
||||
$var string 1 ;FwPz# conversion $end
|
||||
|
|
@ -13766,7 +13831,9 @@ $var string 1 :W!m># config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l=# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa# width $end
|
||||
$var string 1 9hG?R# conversion $end
|
||||
|
|
@ -14589,6 +14656,13 @@ $var wire 16 ~w1^> id $end
|
|||
$var string 1 %RV:C config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 #<FC> \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 z[},} id $end
|
||||
$var string 1 UnOX` config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 &KsMs \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -15210,6 +15284,13 @@ $var wire 16 [hMz. id $end
|
|||
$var string 1 }!B*c config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 #5`o3 \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 gqr/^ id $end
|
||||
$var string 1 `haz~ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 0X}tP \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -15421,6 +15502,13 @@ $var wire 16 ']_J^ id $end
|
|||
$var string 1 lUFJg config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 \1bYR \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 }r^J= id $end
|
||||
$var string 1 ,1@Ze config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 `A[2< \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -17229,6 +17317,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) qtNE\
|
||||
b0 gDmEE
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
|
||||
sHdlNone\x20(0) ;aq90
|
||||
b0 l{J$]
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
|
||||
sHdlNone\x20(0) zJgj&
|
||||
b0 <~R^D
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
|
||||
|
|
@ -18324,7 +18415,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz
|
||||
b0 :sH])
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X
|
||||
b0 4-Xz
|
||||
0)?>/S
|
||||
sWidth8Bit\x20(0) <XF-P
|
||||
sZeroExt\x20(0) jj\+I
|
||||
b0 *Rb!a
|
||||
|
|
@ -18340,7 +18431,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi
|
||||
b0 cLfy`
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M
|
||||
b0 :srK^
|
||||
0tz*x9
|
||||
sWidth8Bit\x20(0) ?qa*@
|
||||
sZeroExt\x20(0) "-Sp[
|
||||
sAddSub\x20(0) UTvN`"
|
||||
|
|
@ -18656,7 +18747,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d
|
||||
b0 NaEMn
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\
|
||||
b0 PEMZT
|
||||
03Jcxw
|
||||
sWidth8Bit\x20(0) sr@tQ
|
||||
sZeroExt\x20(0) ?`G6o
|
||||
b0 =8aoP
|
||||
|
|
@ -18672,7 +18763,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#
|
||||
b0 Ty9rT
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx
|
||||
b0 h^#4^
|
||||
0/W5`l
|
||||
sWidth8Bit\x20(0) MXMmg
|
||||
sZeroExt\x20(0) }v,d
|
||||
0?t-Y"8
|
||||
|
|
@ -18923,7 +19014,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz"
|
||||
b0 :sH])"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X"
|
||||
b0 4-Xz!"
|
||||
0)?>/S"
|
||||
sWidth8Bit\x20(0) <XF-P"
|
||||
sZeroExt\x20(0) jj\+I"
|
||||
b0 *Rb!a"
|
||||
|
|
@ -18939,7 +19030,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi"
|
||||
b0 cLfy`"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M"
|
||||
b0 :srK^"
|
||||
0tz*x9"
|
||||
sWidth8Bit\x20(0) ?qa*@"
|
||||
sZeroExt\x20(0) "-Sp["
|
||||
sAddSub\x20(0) UTvN`%
|
||||
|
|
@ -19255,7 +19346,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d"
|
||||
b0 NaEMn"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\"
|
||||
b0 PEMZT"
|
||||
03Jcxw"
|
||||
sWidth8Bit\x20(0) sr@tQ"
|
||||
sZeroExt\x20(0) ?`G6o"
|
||||
b0 =8aoP"
|
||||
|
|
@ -19271,7 +19362,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#"
|
||||
b0 Ty9rT"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx"
|
||||
b0 h^#4^"
|
||||
0/W5`l"
|
||||
sWidth8Bit\x20(0) MXMmg"
|
||||
sZeroExt\x20(0) }v,d!"
|
||||
0?t-Y"R
|
||||
|
|
@ -19526,7 +19617,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk
|
||||
b0 qw;X3
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*
|
||||
b0 i\?$V
|
||||
0}=M'$
|
||||
sWidth8Bit\x20(0) YKZ('
|
||||
sZeroExt\x20(0) ;FwPz
|
||||
b0 ?M8WI
|
||||
|
|
@ -19542,7 +19633,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d
|
||||
b0 (mYPk
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>
|
||||
b0 Q)/l=
|
||||
0E~a,A
|
||||
sWidth8Bit\x20(0) MFboa
|
||||
sZeroExt\x20(0) 9hG?R
|
||||
1WES6M
|
||||
|
|
@ -19810,7 +19901,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz#
|
||||
b0 :sH])#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X#
|
||||
b0 4-Xz!#
|
||||
0)?>/S#
|
||||
sWidth8Bit\x20(0) <XF-P#
|
||||
sZeroExt\x20(0) jj\+I#
|
||||
b0 *Rb!a#
|
||||
|
|
@ -19826,7 +19917,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi#
|
||||
b0 cLfy`#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M#
|
||||
b0 :srK^#
|
||||
0tz*x9#
|
||||
sWidth8Bit\x20(0) ?qa*@#
|
||||
sZeroExt\x20(0) "-Sp[#
|
||||
sAddSub\x20(0) UTvN`(
|
||||
|
|
@ -20142,7 +20233,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d#
|
||||
b0 NaEMn#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\#
|
||||
b0 PEMZT#
|
||||
03Jcxw#
|
||||
sWidth8Bit\x20(0) sr@tQ#
|
||||
sZeroExt\x20(0) ?`G6o#
|
||||
b0 =8aoP#
|
||||
|
|
@ -20158,7 +20249,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU##
|
||||
b0 Ty9rT#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx#
|
||||
b0 h^#4^#
|
||||
0/W5`l#
|
||||
sWidth8Bit\x20(0) MXMmg#
|
||||
sZeroExt\x20(0) }v,d!#
|
||||
0?t-Y"l
|
||||
|
|
@ -20409,7 +20500,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz$
|
||||
b0 :sH])$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X$
|
||||
b0 4-Xz!$
|
||||
0)?>/S$
|
||||
sWidth8Bit\x20(0) <XF-P$
|
||||
sZeroExt\x20(0) jj\+I$
|
||||
b0 *Rb!a$
|
||||
|
|
@ -20425,7 +20516,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi$
|
||||
b0 cLfy`$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M$
|
||||
b0 :srK^$
|
||||
0tz*x9$
|
||||
sWidth8Bit\x20(0) ?qa*@$
|
||||
sZeroExt\x20(0) "-Sp[$
|
||||
sAddSub\x20(0) UTvN`+
|
||||
|
|
@ -20741,7 +20832,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d$
|
||||
b0 NaEMn$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\$
|
||||
b0 PEMZT$
|
||||
03Jcxw$
|
||||
sWidth8Bit\x20(0) sr@tQ$
|
||||
sZeroExt\x20(0) ?`G6o$
|
||||
b0 =8aoP$
|
||||
|
|
@ -20757,7 +20848,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#$
|
||||
b0 Ty9rT$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx$
|
||||
b0 h^#4^$
|
||||
0/W5`l$
|
||||
sWidth8Bit\x20(0) MXMmg$
|
||||
sZeroExt\x20(0) }v,d!$
|
||||
0?t-Y"("
|
||||
|
|
@ -21012,7 +21103,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk"
|
||||
b0 qw;X3"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*"
|
||||
b0 i\?$V"
|
||||
0}=M'$"
|
||||
sWidth8Bit\x20(0) YKZ('"
|
||||
sZeroExt\x20(0) ;FwPz"
|
||||
b0 ?M8WI"
|
||||
|
|
@ -21028,7 +21119,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d"
|
||||
b0 (mYPk"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>"
|
||||
b0 Q)/l="
|
||||
0E~a,A"
|
||||
sWidth8Bit\x20(0) MFboa"
|
||||
sZeroExt\x20(0) 9hG?R"
|
||||
1WES6M%
|
||||
|
|
@ -21296,7 +21387,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz%
|
||||
b0 :sH])%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X%
|
||||
b0 4-Xz!%
|
||||
0)?>/S%
|
||||
sWidth8Bit\x20(0) <XF-P%
|
||||
sZeroExt\x20(0) jj\+I%
|
||||
b0 *Rb!a%
|
||||
|
|
@ -21312,7 +21403,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi%
|
||||
b0 cLfy`%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M%
|
||||
b0 :srK^%
|
||||
0tz*x9%
|
||||
sWidth8Bit\x20(0) ?qa*@%
|
||||
sZeroExt\x20(0) "-Sp[%
|
||||
sAddSub\x20(0) UTvN`.
|
||||
|
|
@ -21628,7 +21719,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d%
|
||||
b0 NaEMn%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\%
|
||||
b0 PEMZT%
|
||||
03Jcxw%
|
||||
sWidth8Bit\x20(0) sr@tQ%
|
||||
sZeroExt\x20(0) ?`G6o%
|
||||
b0 =8aoP%
|
||||
|
|
@ -21644,7 +21735,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#%
|
||||
b0 Ty9rT%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx%
|
||||
b0 h^#4^%
|
||||
0/W5`l%
|
||||
sWidth8Bit\x20(0) MXMmg%
|
||||
sZeroExt\x20(0) }v,d!%
|
||||
0?t-Y"B"
|
||||
|
|
@ -21895,7 +21986,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz&
|
||||
b0 :sH])&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X&
|
||||
b0 4-Xz!&
|
||||
0)?>/S&
|
||||
sWidth8Bit\x20(0) <XF-P&
|
||||
sZeroExt\x20(0) jj\+I&
|
||||
b0 *Rb!a&
|
||||
|
|
@ -21911,7 +22002,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi&
|
||||
b0 cLfy`&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M&
|
||||
b0 :srK^&
|
||||
0tz*x9&
|
||||
sWidth8Bit\x20(0) ?qa*@&
|
||||
sZeroExt\x20(0) "-Sp[&
|
||||
sAddSub\x20(0) UTvN`1
|
||||
|
|
@ -22227,7 +22318,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d&
|
||||
b0 NaEMn&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\&
|
||||
b0 PEMZT&
|
||||
03Jcxw&
|
||||
sWidth8Bit\x20(0) sr@tQ&
|
||||
sZeroExt\x20(0) ?`G6o&
|
||||
b0 =8aoP&
|
||||
|
|
@ -22243,7 +22334,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#&
|
||||
b0 Ty9rT&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx&
|
||||
b0 h^#4^&
|
||||
0/W5`l&
|
||||
sWidth8Bit\x20(0) MXMmg&
|
||||
sZeroExt\x20(0) }v,d!&
|
||||
0?t-Y"\"
|
||||
|
|
@ -22498,7 +22589,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk#
|
||||
b0 qw;X3#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*#
|
||||
b0 i\?$V#
|
||||
0}=M'$#
|
||||
sWidth8Bit\x20(0) YKZ('#
|
||||
sZeroExt\x20(0) ;FwPz#
|
||||
b0 ?M8WI#
|
||||
|
|
@ -22514,7 +22605,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d#
|
||||
b0 (mYPk#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>#
|
||||
b0 Q)/l=#
|
||||
0E~a,A#
|
||||
sWidth8Bit\x20(0) MFboa#
|
||||
sZeroExt\x20(0) 9hG?R#
|
||||
1WES6M)
|
||||
|
|
@ -23167,6 +23258,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) Vy"k\
|
||||
b0 ~w1^>
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
|
||||
sHdlNone\x20(0) #<FC>
|
||||
b0 z[},}
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
|
||||
sHdlNone\x20(0) &KsMs
|
||||
b0 |]Zt8
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
|
||||
|
|
@ -23577,6 +23671,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) 05GRu
|
||||
b0 [hMz.
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
|
||||
sHdlNone\x20(0) #5`o3
|
||||
b0 gqr/^
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
|
||||
sHdlNone\x20(0) 0X}tP
|
||||
b0 vxQK:
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
|
||||
|
|
@ -23656,6 +23753,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) C2t\%
|
||||
b0 ']_J^
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
|
||||
sHdlNone\x20(0) \1bYR
|
||||
b0 }r^J=
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
|
||||
sHdlNone\x20(0) `A[2<
|
||||
b0 19hEe
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC
|
||||
|
|
@ -24338,7 +24438,8 @@ sPowerIsaTimeBaseU\x20(1) |_w|c
|
|||
1j=};d
|
||||
b11 ^AbsB
|
||||
1#\/Sm
|
||||
b11 4-Xz
|
||||
1)?>/S
|
||||
sWidth16Bit\x20(1) <XF-P
|
||||
173MPw
|
||||
17VGNK
|
||||
b1 cLfy`
|
||||
|
|
@ -24399,10 +24500,9 @@ b1 2<>>Z3
|
|||
b1 2<>>Z6
|
||||
1?t-Y"7
|
||||
14:6&j
|
||||
b100100 PEMZT
|
||||
sWidth32Bit\x20(2) sr@tQ
|
||||
1H\c_"
|
||||
b10 Ty9rT
|
||||
b1 h^#4^
|
||||
1?t-Y"8
|
||||
1?t-Y"9
|
||||
1?t-Y":
|
||||
|
|
@ -24439,7 +24539,8 @@ sPowerIsaTimeBaseU\x20(1) |_w|c"
|
|||
1j=};d"
|
||||
b11 ^AbsB"
|
||||
1#\/Sm"
|
||||
b11 4-Xz!"
|
||||
1)?>/S"
|
||||
sWidth16Bit\x20(1) <XF-P"
|
||||
173MPw"
|
||||
17VGNK"
|
||||
b1 cLfy`"
|
||||
|
|
@ -24500,10 +24601,9 @@ b1 2<>>ZM
|
|||
b1 2<>>ZP
|
||||
1?t-Y"Q
|
||||
14:6&j"
|
||||
b100100 PEMZT"
|
||||
sWidth32Bit\x20(2) sr@tQ"
|
||||
1H\c_""
|
||||
b10 Ty9rT"
|
||||
b1 h^#4^"
|
||||
1?t-Y"R
|
||||
1?t-Y"S
|
||||
1?t-Y"T
|
||||
|
|
@ -24541,7 +24641,8 @@ b1100001 S5C>D
|
|||
1oeF>d
|
||||
b11 H3yhv
|
||||
1'aVr>
|
||||
b11 i\?$V
|
||||
1}=M'$
|
||||
sWidth16Bit\x20(1) YKZ('
|
||||
15#YZ>
|
||||
1^boq>
|
||||
b1 (mYPk
|
||||
|
|
@ -24686,7 +24787,8 @@ sPowerIsaTimeBase\x20(0) |_w|c
|
|||
0j=};d
|
||||
b0 ^AbsB
|
||||
0#\/Sm
|
||||
b0 4-Xz
|
||||
0)?>/S
|
||||
sWidth8Bit\x20(0) <XF-P
|
||||
073MPw
|
||||
07VGNK
|
||||
b0 cLfy`
|
||||
|
|
@ -24747,10 +24849,9 @@ b0 2<>>Z3
|
|||
b0 2<>>Z6
|
||||
0?t-Y"7
|
||||
04:6&j
|
||||
b0 PEMZT
|
||||
sWidth8Bit\x20(0) sr@tQ
|
||||
0H\c_"
|
||||
b0 Ty9rT
|
||||
b0 h^#4^
|
||||
0?t-Y"8
|
||||
0?t-Y"9
|
||||
0?t-Y":
|
||||
|
|
@ -24787,7 +24888,8 @@ sPowerIsaTimeBase\x20(0) |_w|c"
|
|||
0j=};d"
|
||||
b0 ^AbsB"
|
||||
0#\/Sm"
|
||||
b0 4-Xz!"
|
||||
0)?>/S"
|
||||
sWidth8Bit\x20(0) <XF-P"
|
||||
073MPw"
|
||||
07VGNK"
|
||||
b0 cLfy`"
|
||||
|
|
@ -24848,10 +24950,9 @@ b0 2<>>ZM
|
|||
b0 2<>>ZP
|
||||
0?t-Y"Q
|
||||
04:6&j"
|
||||
b0 PEMZT"
|
||||
sWidth8Bit\x20(0) sr@tQ"
|
||||
0H\c_""
|
||||
b0 Ty9rT"
|
||||
b0 h^#4^"
|
||||
0?t-Y"R
|
||||
0?t-Y"S
|
||||
0?t-Y"T
|
||||
|
|
@ -24889,7 +24990,8 @@ b0 S5C>D
|
|||
0oeF>d
|
||||
b0 H3yhv
|
||||
0'aVr>
|
||||
b0 i\?$V
|
||||
0}=M'$
|
||||
sWidth8Bit\x20(0) YKZ('
|
||||
05#YZ>
|
||||
0^boq>
|
||||
b0 (mYPk
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1275,6 +1275,13 @@ $var wire 16 gDmEE id $end
|
|||
$var string 1 l(Ah_ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 ;aq90 \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 l{J$] id $end
|
||||
$var string 1 Nix(+ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 zJgj& \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -3327,7 +3334,9 @@ $var string 1 jQG"X config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P width $end
|
||||
$var string 1 jj\+I conversion $end
|
||||
|
|
@ -3369,7 +3378,9 @@ $var string 1 "^.&M config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9 is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@ width $end
|
||||
$var string 1 "-Sp[ conversion $end
|
||||
|
|
@ -4154,7 +4165,9 @@ $var string 1 :G)2\ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ width $end
|
||||
$var string 1 ?`G6o conversion $end
|
||||
|
|
@ -4196,7 +4209,9 @@ $var string 1 agwXx config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg width $end
|
||||
$var string 1 }v,d conversion $end
|
||||
|
|
@ -4818,7 +4833,9 @@ $var string 1 jQG"X" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P" width $end
|
||||
$var string 1 jj\+I" conversion $end
|
||||
|
|
@ -4860,7 +4877,9 @@ $var string 1 "^.&M" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@" width $end
|
||||
$var string 1 "-Sp[" conversion $end
|
||||
|
|
@ -5645,7 +5664,9 @@ $var string 1 :G)2\" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ" width $end
|
||||
$var string 1 ?`G6o" conversion $end
|
||||
|
|
@ -5687,7 +5708,9 @@ $var string 1 agwXx" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg" width $end
|
||||
$var string 1 }v,d!" conversion $end
|
||||
|
|
@ -6328,7 +6351,9 @@ $var string 1 )?xf* config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ(' width $end
|
||||
$var string 1 ;FwPz conversion $end
|
||||
|
|
@ -6370,7 +6395,9 @@ $var string 1 :W!m> config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l= imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa width $end
|
||||
$var string 1 9hG?R conversion $end
|
||||
|
|
@ -7025,7 +7052,9 @@ $var string 1 jQG"X# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P# width $end
|
||||
$var string 1 jj\+I# conversion $end
|
||||
|
|
@ -7067,7 +7096,9 @@ $var string 1 "^.&M# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@# width $end
|
||||
$var string 1 "-Sp[# conversion $end
|
||||
|
|
@ -7852,7 +7883,9 @@ $var string 1 :G)2\# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ# width $end
|
||||
$var string 1 ?`G6o# conversion $end
|
||||
|
|
@ -7894,7 +7927,9 @@ $var string 1 agwXx# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg# width $end
|
||||
$var string 1 }v,d!# conversion $end
|
||||
|
|
@ -8516,7 +8551,9 @@ $var string 1 jQG"X$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P$ width $end
|
||||
$var string 1 jj\+I$ conversion $end
|
||||
|
|
@ -8558,7 +8595,9 @@ $var string 1 "^.&M$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@$ width $end
|
||||
$var string 1 "-Sp[$ conversion $end
|
||||
|
|
@ -9343,7 +9382,9 @@ $var string 1 :G)2\$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ$ width $end
|
||||
$var string 1 ?`G6o$ conversion $end
|
||||
|
|
@ -9385,7 +9426,9 @@ $var string 1 agwXx$ config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^$ imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l$ is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg$ width $end
|
||||
$var string 1 }v,d!$ conversion $end
|
||||
|
|
@ -10026,7 +10069,9 @@ $var string 1 )?xf*" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ('" width $end
|
||||
$var string 1 ;FwPz" conversion $end
|
||||
|
|
@ -10068,7 +10113,9 @@ $var string 1 :W!m>" config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l=" imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A" is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa" width $end
|
||||
$var string 1 9hG?R" conversion $end
|
||||
|
|
@ -10723,7 +10770,9 @@ $var string 1 jQG"X% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P% width $end
|
||||
$var string 1 jj\+I% conversion $end
|
||||
|
|
@ -10765,7 +10814,9 @@ $var string 1 "^.&M% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@% width $end
|
||||
$var string 1 "-Sp[% conversion $end
|
||||
|
|
@ -11550,7 +11601,9 @@ $var string 1 :G)2\% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ% width $end
|
||||
$var string 1 ?`G6o% conversion $end
|
||||
|
|
@ -11592,7 +11645,9 @@ $var string 1 agwXx% config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^% imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l% is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg% width $end
|
||||
$var string 1 }v,d!% conversion $end
|
||||
|
|
@ -12214,7 +12269,9 @@ $var string 1 jQG"X& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 4-Xz!& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 )?>/S& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 <XF-P& width $end
|
||||
$var string 1 jj\+I& conversion $end
|
||||
|
|
@ -12256,7 +12313,9 @@ $var string 1 "^.&M& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 :srK^& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 tz*x9& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ?qa*@& width $end
|
||||
$var string 1 "-Sp[& conversion $end
|
||||
|
|
@ -13041,7 +13100,9 @@ $var string 1 :G)2\& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 PEMZT& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 3Jcxw& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 sr@tQ& width $end
|
||||
$var string 1 ?`G6o& conversion $end
|
||||
|
|
@ -13083,7 +13144,9 @@ $var string 1 agwXx& config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 h^#4^& imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 /W5`l& is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MXMmg& width $end
|
||||
$var string 1 }v,d!& conversion $end
|
||||
|
|
@ -13724,7 +13787,9 @@ $var string 1 )?xf*# config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 i\?$V# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 }=M'$# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 YKZ('# width $end
|
||||
$var string 1 ;FwPz# conversion $end
|
||||
|
|
@ -13766,7 +13831,9 @@ $var string 1 :W!m># config $end
|
|||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 34 Q)/l=# imm $end
|
||||
$scope struct imm $end
|
||||
$var wire 1 E~a,A# is_cacheable $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 MFboa# width $end
|
||||
$var string 1 9hG?R# conversion $end
|
||||
|
|
@ -14589,6 +14656,13 @@ $var wire 16 ~w1^> id $end
|
|||
$var string 1 %RV:C config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 #<FC> \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 z[},} id $end
|
||||
$var string 1 UnOX` config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 &KsMs \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -15210,6 +15284,13 @@ $var wire 16 [hMz. id $end
|
|||
$var string 1 }!B*c config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 #5`o3 \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 gqr/^ id $end
|
||||
$var string 1 `haz~ config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 0X}tP \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -15421,6 +15502,13 @@ $var wire 16 ']_J^ id $end
|
|||
$var string 1 lUFJg config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct other_units_cant_cause_cancels_before $end
|
||||
$var string 1 \1bYR \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 16 }r^J= id $end
|
||||
$var string 1 ,1@Ze config $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct cant_cause_cancel $end
|
||||
$var string 1 `A[2< \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
|
|
@ -17229,6 +17317,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) qtNE\
|
||||
b0 gDmEE
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l(Ah_
|
||||
sHdlNone\x20(0) ;aq90
|
||||
b0 l{J$]
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Nix(+
|
||||
sHdlNone\x20(0) zJgj&
|
||||
b0 <~R^D
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '}m>.
|
||||
|
|
@ -18324,7 +18415,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz
|
||||
b0 :sH])
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X
|
||||
b0 4-Xz
|
||||
0)?>/S
|
||||
sWidth8Bit\x20(0) <XF-P
|
||||
sZeroExt\x20(0) jj\+I
|
||||
b0 *Rb!a
|
||||
|
|
@ -18340,7 +18431,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi
|
||||
b0 cLfy`
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M
|
||||
b0 :srK^
|
||||
0tz*x9
|
||||
sWidth8Bit\x20(0) ?qa*@
|
||||
sZeroExt\x20(0) "-Sp[
|
||||
sAddSub\x20(0) UTvN`"
|
||||
|
|
@ -18656,7 +18747,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d
|
||||
b0 NaEMn
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\
|
||||
b0 PEMZT
|
||||
03Jcxw
|
||||
sWidth8Bit\x20(0) sr@tQ
|
||||
sZeroExt\x20(0) ?`G6o
|
||||
b0 =8aoP
|
||||
|
|
@ -18672,7 +18763,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#
|
||||
b0 Ty9rT
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx
|
||||
b0 h^#4^
|
||||
0/W5`l
|
||||
sWidth8Bit\x20(0) MXMmg
|
||||
sZeroExt\x20(0) }v,d
|
||||
0?t-Y"8
|
||||
|
|
@ -18923,7 +19014,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz"
|
||||
b0 :sH])"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X"
|
||||
b0 4-Xz!"
|
||||
0)?>/S"
|
||||
sWidth8Bit\x20(0) <XF-P"
|
||||
sZeroExt\x20(0) jj\+I"
|
||||
b0 *Rb!a"
|
||||
|
|
@ -18939,7 +19030,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi"
|
||||
b0 cLfy`"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M"
|
||||
b0 :srK^"
|
||||
0tz*x9"
|
||||
sWidth8Bit\x20(0) ?qa*@"
|
||||
sZeroExt\x20(0) "-Sp["
|
||||
sAddSub\x20(0) UTvN`%
|
||||
|
|
@ -19255,7 +19346,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d"
|
||||
b0 NaEMn"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\"
|
||||
b0 PEMZT"
|
||||
03Jcxw"
|
||||
sWidth8Bit\x20(0) sr@tQ"
|
||||
sZeroExt\x20(0) ?`G6o"
|
||||
b0 =8aoP"
|
||||
|
|
@ -19271,7 +19362,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#"
|
||||
b0 Ty9rT"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx"
|
||||
b0 h^#4^"
|
||||
0/W5`l"
|
||||
sWidth8Bit\x20(0) MXMmg"
|
||||
sZeroExt\x20(0) }v,d!"
|
||||
0?t-Y"R
|
||||
|
|
@ -19526,7 +19617,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk
|
||||
b0 qw;X3
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*
|
||||
b0 i\?$V
|
||||
0}=M'$
|
||||
sWidth8Bit\x20(0) YKZ('
|
||||
sZeroExt\x20(0) ;FwPz
|
||||
b0 ?M8WI
|
||||
|
|
@ -19542,7 +19633,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d
|
||||
b0 (mYPk
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>
|
||||
b0 Q)/l=
|
||||
0E~a,A
|
||||
sWidth8Bit\x20(0) MFboa
|
||||
sZeroExt\x20(0) 9hG?R
|
||||
1WES6M
|
||||
|
|
@ -19810,7 +19901,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz#
|
||||
b0 :sH])#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X#
|
||||
b0 4-Xz!#
|
||||
0)?>/S#
|
||||
sWidth8Bit\x20(0) <XF-P#
|
||||
sZeroExt\x20(0) jj\+I#
|
||||
b0 *Rb!a#
|
||||
|
|
@ -19826,7 +19917,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi#
|
||||
b0 cLfy`#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M#
|
||||
b0 :srK^#
|
||||
0tz*x9#
|
||||
sWidth8Bit\x20(0) ?qa*@#
|
||||
sZeroExt\x20(0) "-Sp[#
|
||||
sAddSub\x20(0) UTvN`(
|
||||
|
|
@ -20142,7 +20233,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d#
|
||||
b0 NaEMn#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\#
|
||||
b0 PEMZT#
|
||||
03Jcxw#
|
||||
sWidth8Bit\x20(0) sr@tQ#
|
||||
sZeroExt\x20(0) ?`G6o#
|
||||
b0 =8aoP#
|
||||
|
|
@ -20158,7 +20249,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU##
|
||||
b0 Ty9rT#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx#
|
||||
b0 h^#4^#
|
||||
0/W5`l#
|
||||
sWidth8Bit\x20(0) MXMmg#
|
||||
sZeroExt\x20(0) }v,d!#
|
||||
0?t-Y"l
|
||||
|
|
@ -20409,7 +20500,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz$
|
||||
b0 :sH])$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X$
|
||||
b0 4-Xz!$
|
||||
0)?>/S$
|
||||
sWidth8Bit\x20(0) <XF-P$
|
||||
sZeroExt\x20(0) jj\+I$
|
||||
b0 *Rb!a$
|
||||
|
|
@ -20425,7 +20516,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi$
|
||||
b0 cLfy`$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M$
|
||||
b0 :srK^$
|
||||
0tz*x9$
|
||||
sWidth8Bit\x20(0) ?qa*@$
|
||||
sZeroExt\x20(0) "-Sp[$
|
||||
sAddSub\x20(0) UTvN`+
|
||||
|
|
@ -20741,7 +20832,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d$
|
||||
b0 NaEMn$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\$
|
||||
b0 PEMZT$
|
||||
03Jcxw$
|
||||
sWidth8Bit\x20(0) sr@tQ$
|
||||
sZeroExt\x20(0) ?`G6o$
|
||||
b0 =8aoP$
|
||||
|
|
@ -20757,7 +20848,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#$
|
||||
b0 Ty9rT$
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx$
|
||||
b0 h^#4^$
|
||||
0/W5`l$
|
||||
sWidth8Bit\x20(0) MXMmg$
|
||||
sZeroExt\x20(0) }v,d!$
|
||||
0?t-Y"("
|
||||
|
|
@ -21012,7 +21103,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk"
|
||||
b0 qw;X3"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*"
|
||||
b0 i\?$V"
|
||||
0}=M'$"
|
||||
sWidth8Bit\x20(0) YKZ('"
|
||||
sZeroExt\x20(0) ;FwPz"
|
||||
b0 ?M8WI"
|
||||
|
|
@ -21028,7 +21119,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d"
|
||||
b0 (mYPk"
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>"
|
||||
b0 Q)/l="
|
||||
0E~a,A"
|
||||
sWidth8Bit\x20(0) MFboa"
|
||||
sZeroExt\x20(0) 9hG?R"
|
||||
1WES6M%
|
||||
|
|
@ -21296,7 +21387,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz%
|
||||
b0 :sH])%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X%
|
||||
b0 4-Xz!%
|
||||
0)?>/S%
|
||||
sWidth8Bit\x20(0) <XF-P%
|
||||
sZeroExt\x20(0) jj\+I%
|
||||
b0 *Rb!a%
|
||||
|
|
@ -21312,7 +21403,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi%
|
||||
b0 cLfy`%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M%
|
||||
b0 :srK^%
|
||||
0tz*x9%
|
||||
sWidth8Bit\x20(0) ?qa*@%
|
||||
sZeroExt\x20(0) "-Sp[%
|
||||
sAddSub\x20(0) UTvN`.
|
||||
|
|
@ -21628,7 +21719,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d%
|
||||
b0 NaEMn%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\%
|
||||
b0 PEMZT%
|
||||
03Jcxw%
|
||||
sWidth8Bit\x20(0) sr@tQ%
|
||||
sZeroExt\x20(0) ?`G6o%
|
||||
b0 =8aoP%
|
||||
|
|
@ -21644,7 +21735,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#%
|
||||
b0 Ty9rT%
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx%
|
||||
b0 h^#4^%
|
||||
0/W5`l%
|
||||
sWidth8Bit\x20(0) MXMmg%
|
||||
sZeroExt\x20(0) }v,d!%
|
||||
0?t-Y"B"
|
||||
|
|
@ -21895,7 +21986,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }*fWz&
|
||||
b0 :sH])&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jQG"X&
|
||||
b0 4-Xz!&
|
||||
0)?>/S&
|
||||
sWidth8Bit\x20(0) <XF-P&
|
||||
sZeroExt\x20(0) jj\+I&
|
||||
b0 *Rb!a&
|
||||
|
|
@ -21911,7 +22002,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \^EZi&
|
||||
b0 cLfy`&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "^.&M&
|
||||
b0 :srK^&
|
||||
0tz*x9&
|
||||
sWidth8Bit\x20(0) ?qa*@&
|
||||
sZeroExt\x20(0) "-Sp[&
|
||||
sAddSub\x20(0) UTvN`1
|
||||
|
|
@ -22227,7 +22318,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m"s>d&
|
||||
b0 NaEMn&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :G)2\&
|
||||
b0 PEMZT&
|
||||
03Jcxw&
|
||||
sWidth8Bit\x20(0) sr@tQ&
|
||||
sZeroExt\x20(0) ?`G6o&
|
||||
b0 =8aoP&
|
||||
|
|
@ -22243,7 +22334,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?%FU#&
|
||||
b0 Ty9rT&
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) agwXx&
|
||||
b0 h^#4^&
|
||||
0/W5`l&
|
||||
sWidth8Bit\x20(0) MXMmg&
|
||||
sZeroExt\x20(0) }v,d!&
|
||||
0?t-Y"\"
|
||||
|
|
@ -22498,7 +22589,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a[;Tk#
|
||||
b0 qw;X3#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )?xf*#
|
||||
b0 i\?$V#
|
||||
0}=M'$#
|
||||
sWidth8Bit\x20(0) YKZ('#
|
||||
sZeroExt\x20(0) ;FwPz#
|
||||
b0 ?M8WI#
|
||||
|
|
@ -22514,7 +22605,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p=h4d#
|
||||
b0 (mYPk#
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :W!m>#
|
||||
b0 Q)/l=#
|
||||
0E~a,A#
|
||||
sWidth8Bit\x20(0) MFboa#
|
||||
sZeroExt\x20(0) 9hG?R#
|
||||
1WES6M)
|
||||
|
|
@ -23167,6 +23258,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) Vy"k\
|
||||
b0 ~w1^>
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) %RV:C
|
||||
sHdlNone\x20(0) #<FC>
|
||||
b0 z[},}
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) UnOX`
|
||||
sHdlNone\x20(0) &KsMs
|
||||
b0 |]Zt8
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6!=|
|
||||
|
|
@ -23577,6 +23671,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) 05GRu
|
||||
b0 [hMz.
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }!B*c
|
||||
sHdlNone\x20(0) #5`o3
|
||||
b0 gqr/^
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `haz~
|
||||
sHdlNone\x20(0) 0X}tP
|
||||
b0 vxQK:
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +4v<h
|
||||
|
|
@ -23656,6 +23753,9 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out
|
|||
sHdlNone\x20(0) C2t\%
|
||||
b0 ']_J^
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) lUFJg
|
||||
sHdlNone\x20(0) \1bYR
|
||||
b0 }r^J=
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,1@Ze
|
||||
sHdlNone\x20(0) `A[2<
|
||||
b0 19hEe
|
||||
sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":1,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |6GEC
|
||||
|
|
@ -24340,9 +24440,7 @@ b1 @5YF|
|
|||
b100000000000000000 ^AbsB
|
||||
sStore\x20(1) ^*?.1
|
||||
1#\/Sm
|
||||
b100000000000000000 4-Xz
|
||||
173MPw
|
||||
b1000000000000 :srK^
|
||||
sAddSubI\x20(1) UTvN`"
|
||||
1f'24R
|
||||
b10000000 *>S(>
|
||||
|
|
@ -24378,9 +24476,7 @@ sPowerIsaTimeBaseU\x20(1) x)cf*
|
|||
1?t-Y"7
|
||||
sStore\x20(1) UTvN`#
|
||||
14:6&j
|
||||
b100000000000000000 PEMZT
|
||||
1H\c_"
|
||||
b1000000000000 h^#4^
|
||||
1?t-Y"8
|
||||
1?t-Y"9
|
||||
sAddSubI\x20(1) c_e1S"
|
||||
|
|
@ -24410,9 +24506,7 @@ b1 @5YF|"
|
|||
b100000000000000000 ^AbsB"
|
||||
sStore\x20(1) ^*?.1"
|
||||
1#\/Sm"
|
||||
b100000000000000000 4-Xz!"
|
||||
173MPw"
|
||||
b1000000000000 :srK^"
|
||||
sAddSubI\x20(1) UTvN`%
|
||||
1f'24R"
|
||||
b10000000 *>S(>"
|
||||
|
|
@ -24448,9 +24542,7 @@ sPowerIsaTimeBaseU\x20(1) x)cf*"
|
|||
1?t-Y"Q
|
||||
sStore\x20(1) UTvN`&
|
||||
14:6&j"
|
||||
b100000000000000000 PEMZT"
|
||||
1H\c_""
|
||||
b1000000000000 h^#4^"
|
||||
1?t-Y"R
|
||||
1?t-Y"S
|
||||
sAddSubI\x20(1) I#;m2
|
||||
|
|
@ -24480,9 +24572,7 @@ b1 S5C>D
|
|||
1oeF>d
|
||||
sStore\x20(1) {F4Z%
|
||||
1'aVr>
|
||||
b100000000000000000 i\?$V
|
||||
15#YZ>
|
||||
b1000000000000 Q)/l=
|
||||
b1000000000000 ~]ped
|
||||
b1000000001000 T)Z*)
|
||||
b1000 DZ.w"
|
||||
|
|
@ -24627,9 +24717,7 @@ b0 @5YF|
|
|||
b0 ^AbsB
|
||||
sLoad\x20(0) ^*?.1
|
||||
0#\/Sm
|
||||
b0 4-Xz
|
||||
073MPw
|
||||
b0 :srK^
|
||||
sAddSub\x20(0) UTvN`"
|
||||
0f'24R
|
||||
b0 *>S(>
|
||||
|
|
@ -24665,9 +24753,7 @@ sPowerIsaTimeBase\x20(0) x)cf*
|
|||
0?t-Y"7
|
||||
sLoad\x20(0) UTvN`#
|
||||
04:6&j
|
||||
b0 PEMZT
|
||||
0H\c_"
|
||||
b0 h^#4^
|
||||
0?t-Y"8
|
||||
0?t-Y"9
|
||||
sAddSub\x20(0) c_e1S"
|
||||
|
|
@ -24697,9 +24783,7 @@ b0 @5YF|"
|
|||
b0 ^AbsB"
|
||||
sLoad\x20(0) ^*?.1"
|
||||
0#\/Sm"
|
||||
b0 4-Xz!"
|
||||
073MPw"
|
||||
b0 :srK^"
|
||||
sAddSub\x20(0) UTvN`%
|
||||
0f'24R"
|
||||
b0 *>S(>"
|
||||
|
|
@ -24735,9 +24819,7 @@ sPowerIsaTimeBase\x20(0) x)cf*"
|
|||
0?t-Y"Q
|
||||
sLoad\x20(0) UTvN`&
|
||||
04:6&j"
|
||||
b0 PEMZT"
|
||||
0H\c_""
|
||||
b0 h^#4^"
|
||||
0?t-Y"R
|
||||
0?t-Y"S
|
||||
sAddSub\x20(0) I#;m2
|
||||
|
|
@ -24767,9 +24849,7 @@ b0 S5C>D
|
|||
0oeF>d
|
||||
sLoad\x20(0) {F4Z%
|
||||
0'aVr>
|
||||
b0 i\?$V
|
||||
05#YZ>
|
||||
b0 Q)/l=
|
||||
b0 ~]ped
|
||||
b0 T)Z*)
|
||||
b100 DZ.w"
|
||||
|
|
|
|||
|
|
@ -5,14 +5,17 @@ use cpu::{
|
|||
config::{CpuConfig, CpuConfig2PowOutRegNumWidth, PhantomConstCpuConfig, UnitConfig},
|
||||
instruction::{
|
||||
COMMON_MOP_SRC_LEN, CommonMOp, LoadMOp, LoadStoreCommonMOp, LoadStoreConversion,
|
||||
LoadStoreMOp, LoadStoreWidth, MOpTrait, PRegNum, StoreMOp, UnitNum, UnitOutRegNum,
|
||||
LoadStoreMOp, LoadStoreOptions, LoadStoreWidth, MOpTrait, PRegNum, StoreMOp, UnitNum,
|
||||
UnitOutRegNum,
|
||||
},
|
||||
main_memory_and_io::MemoryOperationErrorKind,
|
||||
next_pc::CallStackOp,
|
||||
register::{FlagsMode, PRegFlags, PRegFlagsPowerISA, PRegValue},
|
||||
rename_execute_retire::{
|
||||
ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
|
||||
UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel, UnitInputsReady,
|
||||
UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady,
|
||||
UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
|
||||
UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady,
|
||||
},
|
||||
unit::{
|
||||
UnitKind,
|
||||
|
|
@ -20,7 +23,7 @@ use cpu::{
|
|||
DCacheFinish, DCacheFinishSpeculativeLoad, DCacheFinishStatus,
|
||||
DCacheForeignWriteToCacheLine, DCacheOpKind, DCacheOpKindLoad, DCacheOpKindStore,
|
||||
DCacheStart, DCacheStartSpeculativeLoad, LoadStoreToDCacheInterface,
|
||||
MAX_LOAD_STORE_SIZE, load_store,
|
||||
MACHINE_CHECK_INTERRUPT_PC, MAX_LOAD_STORE_SIZE, load_store,
|
||||
},
|
||||
},
|
||||
util::array_vec::ArrayVec,
|
||||
|
|
@ -267,10 +270,6 @@ impl fmt::Debug for MemoryState {
|
|||
}
|
||||
|
||||
impl MemoryState {
|
||||
const IO_START: u64 = 0x1_0000_0000;
|
||||
fn is_cacheable(address: u64) -> bool {
|
||||
address < Self::IO_START
|
||||
}
|
||||
fn split_op(
|
||||
address: u64,
|
||||
mut data: [Option<u8>; MAX_LOAD_STORE_SIZE],
|
||||
|
|
@ -303,26 +302,21 @@ impl MemoryState {
|
|||
&self,
|
||||
address: u64,
|
||||
mask: [bool; MAX_LOAD_STORE_SIZE],
|
||||
) -> Option<[u8; MAX_LOAD_STORE_SIZE]> {
|
||||
) -> [u8; MAX_LOAD_STORE_SIZE] {
|
||||
const { assert!(Self::BLOCK_SIZE.is_power_of_two()) }
|
||||
assert_ne!(mask, [false; _]);
|
||||
if Self::is_cacheable(address) {
|
||||
let mut retval = [0; MAX_LOAD_STORE_SIZE];
|
||||
for (load_offset, mask) in mask.into_iter().enumerate() {
|
||||
if mask {
|
||||
let address = address.wrapping_add(load_offset as u64);
|
||||
assert!(Self::is_cacheable(address), "{address:#X}");
|
||||
let block_offset = address % Self::BLOCK_SIZE as u64;
|
||||
retval[load_offset] = self
|
||||
.cacheable
|
||||
.get(&(address - block_offset))
|
||||
.map_or(0, |block| block.data.as_flattened()[block_offset as usize]);
|
||||
}
|
||||
let mut retval = [0; MAX_LOAD_STORE_SIZE];
|
||||
for (load_offset, mask) in mask.into_iter().enumerate() {
|
||||
if mask {
|
||||
let address = address.wrapping_add(load_offset as u64);
|
||||
let block_offset = address % Self::BLOCK_SIZE as u64;
|
||||
retval[load_offset] = self
|
||||
.cacheable
|
||||
.get(&(address - block_offset))
|
||||
.map_or(0, |block| block.data.as_flattened()[block_offset as usize]);
|
||||
}
|
||||
Some(retval)
|
||||
} else {
|
||||
None
|
||||
}
|
||||
retval
|
||||
}
|
||||
fn next_io_bytes(&self) -> [u8; MAX_LOAD_STORE_SIZE] {
|
||||
RandomState {
|
||||
|
|
@ -335,23 +329,12 @@ impl MemoryState {
|
|||
&mut self,
|
||||
address: u64,
|
||||
mask: [bool; MAX_LOAD_STORE_SIZE],
|
||||
is_cacheable: bool,
|
||||
) -> [u8; MAX_LOAD_STORE_SIZE] {
|
||||
const { assert!(Self::BLOCK_SIZE.is_power_of_two()) }
|
||||
assert_ne!(mask, [false; _]);
|
||||
if Self::is_cacheable(address) {
|
||||
let mut retval = [0; MAX_LOAD_STORE_SIZE];
|
||||
for (load_offset, mask) in mask.into_iter().enumerate() {
|
||||
if mask {
|
||||
let address = address.wrapping_add(load_offset as u64);
|
||||
assert!(Self::is_cacheable(address), "{address:#X}");
|
||||
let block_offset = address % Self::BLOCK_SIZE as u64;
|
||||
retval[load_offset] = self
|
||||
.cacheable
|
||||
.get(&(address - block_offset))
|
||||
.map_or(0, |block| block.data.as_flattened()[block_offset as usize]);
|
||||
}
|
||||
}
|
||||
retval
|
||||
if is_cacheable {
|
||||
self.cached_load(address, mask)
|
||||
} else {
|
||||
let mut retval = [0; MAX_LOAD_STORE_SIZE];
|
||||
let mut data = [None; MAX_LOAD_STORE_SIZE];
|
||||
|
|
@ -371,14 +354,13 @@ impl MemoryState {
|
|||
retval
|
||||
}
|
||||
}
|
||||
fn store(&mut self, address: u64, data: [Option<u8>; MAX_LOAD_STORE_SIZE]) {
|
||||
fn store(&mut self, address: u64, data: [Option<u8>; MAX_LOAD_STORE_SIZE], is_cacheable: bool) {
|
||||
const { assert!(Self::BLOCK_SIZE.is_power_of_two()) }
|
||||
assert_ne!(data, [None; _]);
|
||||
if Self::is_cacheable(address) {
|
||||
if is_cacheable {
|
||||
for (store_offset, data) in data.into_iter().enumerate() {
|
||||
if let Some(data) = data {
|
||||
let address = address.wrapping_add(store_offset as u64);
|
||||
assert!(Self::is_cacheable(address), "{address:#X}");
|
||||
let block_offset = address % Self::BLOCK_SIZE as u64;
|
||||
self.cacheable
|
||||
.entry(address - block_offset)
|
||||
|
|
@ -604,7 +586,10 @@ impl MemoryState {
|
|||
#[test]
|
||||
fn test_memory_state() {
|
||||
let mut state = MemoryState::default();
|
||||
assert_eq!(state.load(0x1000, [true; MAX_LOAD_STORE_SIZE]), [0; _]);
|
||||
assert_eq!(
|
||||
state.load(0x1000, [true; MAX_LOAD_STORE_SIZE], true),
|
||||
[0; _]
|
||||
);
|
||||
state.assert_is_string(
|
||||
r"MemoryState {
|
||||
io_random_seed: 0x0,
|
||||
|
|
@ -613,6 +598,7 @@ fn test_memory_state() {
|
|||
state.store(
|
||||
0x1000,
|
||||
[0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87].map(Some),
|
||||
true,
|
||||
);
|
||||
state.assert_is_string(
|
||||
r"MemoryState {
|
||||
|
|
@ -622,7 +608,7 @@ fn test_memory_state() {
|
|||
}",
|
||||
);
|
||||
assert_eq!(
|
||||
state.load(0x1000, [true; MAX_LOAD_STORE_SIZE]),
|
||||
state.load(0x1000, [true; MAX_LOAD_STORE_SIZE], true),
|
||||
[0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87],
|
||||
);
|
||||
state.assert_is_string(
|
||||
|
|
@ -638,7 +624,7 @@ fn test_memory_state() {
|
|||
let io_bytes = state.next_io_bytes();
|
||||
let expected_data = std::array::from_fn(|i| if i < $size { io_bytes[i] } else { 0 });
|
||||
assert_eq!(
|
||||
state.load($address, std::array::from_fn(|i| i < $size)),
|
||||
state.load($address, std::array::from_fn(|i| i < $size), false),
|
||||
expected_data,
|
||||
);
|
||||
state.assert_is_string($expected);
|
||||
|
|
@ -821,6 +807,7 @@ struct MockDCacheToLoadStoreTester {
|
|||
#[hdl(flip)]
|
||||
memory_state_seed: UInt<64>,
|
||||
memory_state: MemorySimState,
|
||||
memory_error: Bool,
|
||||
}
|
||||
|
||||
const LOAD_STORE_QUEUE_SIZE: usize = 16;
|
||||
|
|
@ -843,6 +830,7 @@ struct MockDCacheDebugState<C: PhantomConstGet<CpuConfig>> {
|
|||
cache_line_addresses: Array<TraceAsString<HdlOption<UInt<64>>>, 16>,
|
||||
load_store_queue: Array<HdlOption<MockDCacheLoadStoreDebugState<C>>, { LOAD_STORE_QUEUE_SIZE }>,
|
||||
speculative_load_queue: Array<HdlOption<DCacheStartSpeculativeLoad<C>>, 3>,
|
||||
memory_error: Bool,
|
||||
config: C,
|
||||
}
|
||||
|
||||
|
|
@ -851,6 +839,7 @@ struct MockDCacheState<'a, C: PhantomConstCpuConfig> {
|
|||
cache_line_addresses: [Option<u64>; 16],
|
||||
load_store_queue: VecDeque<MockDCacheLoadStore<C>>,
|
||||
speculative_load_queue: [Option<SimValue<DCacheStartSpeculativeLoad<C>>>; 3],
|
||||
memory_error: bool,
|
||||
config: C,
|
||||
random_state: &'a RandomState,
|
||||
}
|
||||
|
|
@ -862,6 +851,7 @@ impl<C: PhantomConstCpuConfig> fmt::Debug for MockDCacheState<'_, C> {
|
|||
cache_line_addresses,
|
||||
load_store_queue,
|
||||
speculative_load_queue,
|
||||
memory_error,
|
||||
config,
|
||||
random_state: _,
|
||||
} = self;
|
||||
|
|
@ -870,6 +860,7 @@ impl<C: PhantomConstCpuConfig> fmt::Debug for MockDCacheState<'_, C> {
|
|||
.field("cache_line_addresses", cache_line_addresses)
|
||||
.field("load_store_queue", load_store_queue)
|
||||
.field("speculative_load_queue", speculative_load_queue)
|
||||
.field("memory_error", memory_error)
|
||||
.field("config", config)
|
||||
.finish_non_exhaustive()
|
||||
}
|
||||
|
|
@ -883,6 +874,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
cache_line_addresses: [None; _],
|
||||
load_store_queue: VecDeque::with_capacity(LOAD_STORE_QUEUE_SIZE),
|
||||
speculative_load_queue: [const { None }; _],
|
||||
memory_error: false,
|
||||
config,
|
||||
random_state,
|
||||
}
|
||||
|
|
@ -894,6 +886,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
ref cache_line_addresses,
|
||||
ref load_store_queue,
|
||||
ref speculative_load_queue,
|
||||
memory_error,
|
||||
config,
|
||||
random_state: _,
|
||||
} = *self;
|
||||
|
|
@ -915,6 +908,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
load_store_queue: load_store_queue.into_sim_value_with_type(ret_ty.load_store_queue),
|
||||
speculative_load_queue: speculative_load_queue
|
||||
.into_sim_value_with_type(ret_ty.speculative_load_queue),
|
||||
memory_error,
|
||||
config,
|
||||
}
|
||||
}
|
||||
|
|
@ -992,18 +986,15 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
let address = address.wrapping_add(i as u64);
|
||||
let offset = address % cache_line_size as u64;
|
||||
let cache_line_address = address.wrapping_sub(offset);
|
||||
if self
|
||||
if !self
|
||||
.cache_line_addresses
|
||||
.contains(&Some(cache_line_address))
|
||||
{
|
||||
assert!(
|
||||
MemoryState::is_cacheable(address),
|
||||
"{address:#X} is not cacheable but is in cached line at {cache_line_address:#X}\n{self:#?}"
|
||||
);
|
||||
return None;
|
||||
}
|
||||
}
|
||||
}
|
||||
self.memory_state.cached_load(address, mask)
|
||||
Some(self.memory_state.cached_load(address, mask))
|
||||
}
|
||||
#[hdl]
|
||||
fn from_load_store_finish_speculative_load_data(
|
||||
|
|
@ -1053,7 +1044,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
let mut update_cache_for_access =
|
||||
|address: u64,
|
||||
data_and_mask: &[SimValue<HdlOption<UInt<8>>>; _],
|
||||
mut is_cacheable: bool| {
|
||||
is_cacheable: bool| {
|
||||
let mut cache_line_addresses = [0; 2];
|
||||
let mut cache_line_addresses_len = 0;
|
||||
for (i, data_and_mask) in data_and_mask.iter().enumerate() {
|
||||
|
|
@ -1062,7 +1053,6 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
continue;
|
||||
}
|
||||
let address = address.wrapping_add(i as u64);
|
||||
is_cacheable &= MemoryState::is_cacheable(address);
|
||||
let offset = address % MemoryState::BLOCK_SIZE as u64;
|
||||
let cache_line_address = address - offset;
|
||||
if cache_line_addresses_len == 0
|
||||
|
|
@ -1141,17 +1131,25 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
config: _,
|
||||
} = op;
|
||||
let address = address.as_int();
|
||||
*finish_status = Some(
|
||||
if self.random_state.random_u64(Self::RANDOM_KEY) % (1 << 6) == 0 {
|
||||
self.memory_error = true;
|
||||
#[hdl(sim)]
|
||||
DCacheFinishStatus.MemoryError(
|
||||
#[hdl(sim)]
|
||||
MemoryOperationErrorKind.Generic(),
|
||||
)
|
||||
} else {
|
||||
#[hdl(sim)]
|
||||
DCacheFinishStatus.Success()
|
||||
},
|
||||
);
|
||||
#[hdl(sim)]
|
||||
match &kind {
|
||||
DCacheOpKind::Load(kind) => {
|
||||
#[hdl(sim)]
|
||||
let DCacheOpKindLoad { is_cacheable } = kind;
|
||||
update_cache_for_access(address, data_and_mask, **is_cacheable);
|
||||
// TODO: simulate random memory errors
|
||||
*finish_status = Some(
|
||||
#[hdl(sim)]
|
||||
DCacheFinishStatus.Success(),
|
||||
);
|
||||
let data = self.memory_state.load(
|
||||
address,
|
||||
std::array::from_fn(|i| {
|
||||
|
|
@ -1162,6 +1160,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
false
|
||||
}
|
||||
}),
|
||||
**is_cacheable,
|
||||
);
|
||||
for (&data, data_and_mask) in data.iter().zip(data_and_mask) {
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1174,11 +1173,6 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
#[hdl(sim)]
|
||||
let DCacheOpKindStore { is_cacheable } = kind;
|
||||
update_cache_for_access(address, data_and_mask, **is_cacheable);
|
||||
// TODO: simulate random memory errors
|
||||
*finish_status = Some(
|
||||
#[hdl(sim)]
|
||||
DCacheFinishStatus.Success(),
|
||||
);
|
||||
self.memory_state.store(
|
||||
address,
|
||||
std::array::from_fn(|i| {
|
||||
|
|
@ -1189,6 +1183,7 @@ impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> {
|
|||
None
|
||||
}
|
||||
}),
|
||||
**is_cacheable,
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -1242,9 +1237,11 @@ async fn mock_d_cache_impl<C: PhantomConstCpuConfig>(
|
|||
let MockDCacheToLoadStoreTester {
|
||||
memory_state_seed: _,
|
||||
memory_state,
|
||||
memory_error,
|
||||
} = to_load_store_tester;
|
||||
sim.write(memory_state, state.memory_state.to_sim_value())
|
||||
.await;
|
||||
sim.write(memory_error, state.memory_error).await;
|
||||
}
|
||||
sim.write(debug_state, state.debug_state()).await;
|
||||
sim.wait_for_clock_edge(cd.clk).await;
|
||||
|
|
@ -1253,6 +1250,7 @@ async fn mock_d_cache_impl<C: PhantomConstCpuConfig>(
|
|||
let MockDCacheToLoadStoreTester {
|
||||
memory_state_seed,
|
||||
memory_state: _,
|
||||
memory_error: _,
|
||||
} = to_load_store_tester;
|
||||
let memory_state_seed = sim.read_past(memory_state_seed, cd.clk).await.as_int();
|
||||
if state.memory_state.io_random_seed != memory_state_seed {
|
||||
|
|
@ -1372,9 +1370,11 @@ fn mock_d_cache(config: PhantomConst<CpuConfig>) {
|
|||
let MockDCacheToLoadStoreTester {
|
||||
memory_state_seed: _,
|
||||
memory_state,
|
||||
memory_error,
|
||||
} = to_load_store_tester;
|
||||
sim.write(memory_state, MemoryState::default().to_sim_value())
|
||||
.await;
|
||||
sim.write(memory_error, false).await;
|
||||
sim.write(debug_state, state.debug_state()).await;
|
||||
state
|
||||
},
|
||||
|
|
@ -1395,15 +1395,32 @@ fn mock_d_cache(config: PhantomConst<CpuConfig>) {
|
|||
);
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
enum InsnCausedCancel {
|
||||
Retry,
|
||||
AsyncError,
|
||||
}
|
||||
|
||||
impl InsnCausedCancel {
|
||||
fn cancel_after_retire(self) -> bool {
|
||||
match self {
|
||||
Self::Retry => false,
|
||||
Self::AsyncError => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug)]
|
||||
struct Insn<C: PhantomConstCpuConfig> {
|
||||
cycles_after_start_to_cancel: Option<usize>,
|
||||
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
|
||||
sent_inputs_ready: bool,
|
||||
sent_is_no_longer_speculative: bool,
|
||||
caused_cancel_before_retire: bool,
|
||||
sent_other_units_cant_cause_cancels_before: bool,
|
||||
caused_cancel: Option<InsnCausedCancel>,
|
||||
cant_cause_cancel: bool,
|
||||
output: Option<SimValue<TraceAsString<PRegValue>>>,
|
||||
expected_output: SimValue<TraceAsString<PRegValue>>,
|
||||
finished: bool,
|
||||
}
|
||||
|
||||
|
|
@ -1415,9 +1432,11 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Insn<C> {
|
|||
mop,
|
||||
sent_inputs_ready,
|
||||
sent_is_no_longer_speculative,
|
||||
caused_cancel_before_retire,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
caused_cancel,
|
||||
cant_cause_cancel,
|
||||
output,
|
||||
expected_output,
|
||||
finished,
|
||||
} = self;
|
||||
write!(f, "cy_a_s_c=")?;
|
||||
|
|
@ -1432,8 +1451,14 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Insn<C> {
|
|||
if *sent_is_no_longer_speculative {
|
||||
write!(f, " (sinls)")?;
|
||||
}
|
||||
if *caused_cancel_before_retire {
|
||||
write!(f, " (ccbr)")?;
|
||||
if *sent_other_units_cant_cause_cancels_before {
|
||||
write!(f, " (socccb)")?;
|
||||
}
|
||||
if let Some(caused_cancel) = caused_cancel {
|
||||
match caused_cancel {
|
||||
InsnCausedCancel::Retry => write!(f, " (caused_cancel=retry)")?,
|
||||
InsnCausedCancel::AsyncError => write!(f, " (caused_cancel=async_error)")?,
|
||||
}
|
||||
}
|
||||
if *cant_cause_cancel {
|
||||
write!(f, " (ccc)")?;
|
||||
|
|
@ -1444,6 +1469,13 @@ impl<C: PhantomConstCpuConfig> fmt::Display for Insn<C> {
|
|||
write!(f, " {:?}", mop.mop)?;
|
||||
if let Some(output) = output {
|
||||
write!(f, " -> {output:?}")?;
|
||||
if output == expected_output {
|
||||
write!(f, ": matches expected")?;
|
||||
} else {
|
||||
write!(f, ": doesn't match expected: {expected_output:?}")?;
|
||||
}
|
||||
} else {
|
||||
write!(f, ": expected: {expected_output:?}")?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
|
@ -1482,6 +1514,8 @@ struct LoadStoreTesterDebugState<C: PhantomConstGet<CpuConfig>> {
|
|||
canceling: Bool,
|
||||
expected_memory_state: MemorySimState,
|
||||
matches_expected_memory_state: Bool,
|
||||
d_cache_caused_memory_error: Bool,
|
||||
retired_async_error: Bool,
|
||||
config: C,
|
||||
}
|
||||
|
||||
|
|
@ -1493,6 +1527,8 @@ struct LoadStoreTesterState<C: PhantomConstCpuConfig> {
|
|||
canceling: bool,
|
||||
expected_memory_state: MemoryState,
|
||||
matches_expected_memory_state: bool,
|
||||
d_cache_caused_memory_error: bool,
|
||||
retired_async_error: bool,
|
||||
config: C,
|
||||
load_store_unit_index: usize,
|
||||
input_unit_index: usize,
|
||||
|
|
@ -1540,13 +1576,11 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
src_index == 0 || random_state.random_u64(Self::RANDOM_KEY) % 2 == 0;
|
||||
let mask = if is_address {
|
||||
// an address:
|
||||
// pick between cacheable and I/O
|
||||
let io_mask = MemoryState::IO_START;
|
||||
// pick one of 4 cache lines
|
||||
let cache_line_mask = 3 * MemoryState::BLOCK_SIZE as u64;
|
||||
// pick a byte in a cache line
|
||||
let byte_in_cache_line_mask = MemoryState::BLOCK_SIZE as u64 - 1;
|
||||
io_mask | cache_line_mask | byte_in_cache_line_mask
|
||||
cache_line_mask | byte_in_cache_line_mask
|
||||
} else {
|
||||
// any value
|
||||
!0
|
||||
|
|
@ -1575,6 +1609,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
});
|
||||
let width = random_state.random_enum(LoadStoreWidth, Self::RANDOM_KEY);
|
||||
let conversion = random_state.random_enum(LoadStoreConversion, Self::RANDOM_KEY);
|
||||
let options = #[hdl(sim)]
|
||||
LoadStoreOptions {
|
||||
is_cacheable: random_state.random_u64(Self::RANDOM_KEY) % 2 != 0,
|
||||
};
|
||||
let mop: Expr<LoadStoreMOp<_, _>> =
|
||||
if random_state.random_u64(Self::RANDOM_KEY) % 2 != 0 {
|
||||
load_outputs.push(dest.clone());
|
||||
|
|
@ -1583,6 +1621,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
[&src0].into_sim_value_with_type(Array[src0.ty()][ConstUsize]),
|
||||
width,
|
||||
conversion,
|
||||
options,
|
||||
)
|
||||
} else {
|
||||
StoreMOp::store(
|
||||
|
|
@ -1590,6 +1629,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
[&src0, &src1].into_sim_value_with_type(Array[src0.ty()][ConstUsize]),
|
||||
width,
|
||||
conversion,
|
||||
options,
|
||||
)
|
||||
};
|
||||
let pc = 0x1000 + insn_index as u64 * 4;
|
||||
|
|
@ -1612,9 +1652,11 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
},
|
||||
sent_inputs_ready: false,
|
||||
sent_is_no_longer_speculative: false,
|
||||
caused_cancel_before_retire: false,
|
||||
sent_other_units_cant_cause_cancels_before: false,
|
||||
caused_cancel: None,
|
||||
cant_cause_cancel: false,
|
||||
output: None,
|
||||
expected_output: PRegValue::zeroed_sim().into_trace_as_string(),
|
||||
finished: false,
|
||||
});
|
||||
}
|
||||
|
|
@ -1626,15 +1668,17 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
canceling: false,
|
||||
expected_memory_state: MemoryState::empty(random_state.random_u64(Self::RANDOM_KEY)),
|
||||
matches_expected_memory_state: false,
|
||||
d_cache_caused_memory_error: false,
|
||||
retired_async_error: false,
|
||||
config,
|
||||
load_store_unit_index,
|
||||
input_unit_index,
|
||||
};
|
||||
retval.fill_in_expected_memory_state();
|
||||
retval.fill_in_expected();
|
||||
retval
|
||||
}
|
||||
#[hdl]
|
||||
fn fill_in_expected_memory_state(&mut self) {
|
||||
fn fill_in_expected(&mut self) {
|
||||
let const_zero = PRegValue::zeroed_sim().into_trace_as_string();
|
||||
for insn_index in 0..self.insns.len() {
|
||||
let Insn { mop, .. } = &self.insns[insn_index];
|
||||
|
|
@ -1654,8 +1698,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
prefix_pad: _,
|
||||
dest: _,
|
||||
src,
|
||||
imm: _,
|
||||
imm: options,
|
||||
} = common;
|
||||
#[hdl(sim)]
|
||||
let LoadStoreOptions { is_cacheable } = options;
|
||||
let [src0] = SimValue::value(src);
|
||||
let Some(src0_value) = self.read_reg(src0, &const_zero) else {
|
||||
unreachable!();
|
||||
|
|
@ -1664,6 +1710,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
let mut loaded = self.expected_memory_state.load(
|
||||
src0_value.inner().int_fp.as_int(),
|
||||
std::array::from_fn(|i| i < byte_size.get() as usize),
|
||||
**is_cacheable,
|
||||
);
|
||||
#[hdl(sim)]
|
||||
match conversion {
|
||||
|
|
@ -1697,8 +1744,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
prefix_pad: _,
|
||||
dest: _,
|
||||
src,
|
||||
imm: _,
|
||||
imm: options,
|
||||
} = common;
|
||||
#[hdl(sim)]
|
||||
let LoadStoreOptions { is_cacheable } = options;
|
||||
let [src0, src1] = SimValue::value(src);
|
||||
let Some(src0_value) = self.read_reg(src0, &const_zero) else {
|
||||
unreachable!();
|
||||
|
|
@ -1717,6 +1766,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
std::array::from_fn(|i| {
|
||||
(i < byte_size.get() as usize).then_some(data[i])
|
||||
}),
|
||||
**is_cacheable,
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -1726,7 +1776,10 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
self.insns[insn_index].output = Some(output.into_trace_as_string());
|
||||
}
|
||||
for insn in &mut self.insns {
|
||||
insn.output = None;
|
||||
let Some(expected_output) = insn.output.take() else {
|
||||
unreachable!()
|
||||
};
|
||||
insn.expected_output = expected_output;
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
|
|
@ -1739,6 +1792,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
canceling,
|
||||
ref expected_memory_state,
|
||||
matches_expected_memory_state,
|
||||
d_cache_caused_memory_error,
|
||||
retired_async_error,
|
||||
config,
|
||||
load_store_unit_index: _,
|
||||
input_unit_index: _,
|
||||
|
|
@ -1759,6 +1814,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
canceling,
|
||||
expected_memory_state: expected_memory_state.to_sim_value(),
|
||||
matches_expected_memory_state,
|
||||
d_cache_caused_memory_error,
|
||||
retired_async_error,
|
||||
config,
|
||||
}
|
||||
}
|
||||
|
|
@ -1782,7 +1839,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
}
|
||||
#[hdl]
|
||||
fn to_load_store_enqueue(&self) -> Option<SimValue<UnitEnqueue<C>>> {
|
||||
if self.canceling {
|
||||
if self.canceling || self.retired_async_error {
|
||||
return None;
|
||||
}
|
||||
if self.enqueued.end < self.insns.len() {
|
||||
|
|
@ -1859,9 +1916,11 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
mop,
|
||||
sent_inputs_ready,
|
||||
sent_is_no_longer_speculative: _,
|
||||
caused_cancel_before_retire: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
caused_cancel: _,
|
||||
cant_cause_cancel: _,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
finished: _,
|
||||
} = insn;
|
||||
if *sent_inputs_ready {
|
||||
|
|
@ -1929,9 +1988,11 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
mop,
|
||||
sent_inputs_ready: _,
|
||||
sent_is_no_longer_speculative,
|
||||
caused_cancel_before_retire,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
caused_cancel,
|
||||
cant_cause_cancel,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
finished,
|
||||
} = insn;
|
||||
if cycles_after_start_to_cancel.is_some() {
|
||||
|
|
@ -1949,7 +2010,7 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
if *cant_cause_cancel {
|
||||
continue;
|
||||
}
|
||||
if *finished && !*caused_cancel_before_retire {
|
||||
if *finished && caused_cancel.is_none() {
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
|
@ -1964,8 +2025,61 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
if self.canceling {
|
||||
return;
|
||||
}
|
||||
Self::insn_by_id(&mut self.insns, &is_no_longer_speculative.id)
|
||||
.sent_is_no_longer_speculative = true;
|
||||
let insn = Self::insn_by_id(&mut self.insns, &is_no_longer_speculative.id);
|
||||
insn.sent_is_no_longer_speculative = true;
|
||||
}
|
||||
#[hdl]
|
||||
fn to_load_store_other_units_cant_cause_cancels_before(
|
||||
&self,
|
||||
) -> Option<SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>> {
|
||||
if self.canceling {
|
||||
return None;
|
||||
}
|
||||
let mut is_speculative = false;
|
||||
for insn in &self.insns[self.enqueued.clone()] {
|
||||
let Insn {
|
||||
cycles_after_start_to_cancel,
|
||||
mop,
|
||||
sent_inputs_ready: _,
|
||||
sent_is_no_longer_speculative: _,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
caused_cancel,
|
||||
cant_cause_cancel,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
finished,
|
||||
} = insn;
|
||||
if cycles_after_start_to_cancel.is_some() {
|
||||
return None;
|
||||
}
|
||||
if !*sent_other_units_cant_cause_cancels_before && is_speculative {
|
||||
return Some(
|
||||
#[hdl(sim)]
|
||||
UnitMOpOtherUnitsCantCauseCancelsBefore::<_> {
|
||||
id: &mop.id,
|
||||
config: self.config,
|
||||
},
|
||||
);
|
||||
}
|
||||
if *finished && caused_cancel.is_none() {
|
||||
continue;
|
||||
}
|
||||
if !*cant_cause_cancel {
|
||||
is_speculative = true;
|
||||
}
|
||||
}
|
||||
None
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_to_load_store_other_units_cant_cause_cancels_before(
|
||||
&mut self,
|
||||
other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
|
||||
) {
|
||||
if self.canceling {
|
||||
return;
|
||||
}
|
||||
Self::insn_by_id(&mut self.insns, &other_units_cant_cause_cancels_before.id)
|
||||
.sent_other_units_cant_cause_cancels_before = true;
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_to_load_store_cant_cause_cancel(
|
||||
|
|
@ -2026,9 +2140,14 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
cancel_after_retire,
|
||||
config: _,
|
||||
} = caused_cancel;
|
||||
assert_eq!(start_at_pc, insn.mop.pc);
|
||||
assert_eq!(*cancel_after_retire, false);
|
||||
insn.caused_cancel_before_retire = true;
|
||||
let caused_cancel = if start_at_pc.as_int() == MACHINE_CHECK_INTERRUPT_PC {
|
||||
InsnCausedCancel::AsyncError
|
||||
} else {
|
||||
assert_eq!(start_at_pc, insn.mop.pc);
|
||||
InsnCausedCancel::Retry
|
||||
};
|
||||
assert_eq!(*cancel_after_retire, caused_cancel.cancel_after_retire());
|
||||
insn.caused_cancel = Some(caused_cancel);
|
||||
}
|
||||
insn.finished = true;
|
||||
}
|
||||
|
|
@ -2041,13 +2160,30 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
self.canceling = false;
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_from_mock_d_cache_memory_state(&mut self, memory_state: SimValue<MemorySimState>) {
|
||||
fn handle_from_mock_d_cache_memory_state(
|
||||
&mut self,
|
||||
memory_state: SimValue<MemorySimState>,
|
||||
memory_error: bool,
|
||||
) {
|
||||
self.d_cache_caused_memory_error = memory_error;
|
||||
self.matches_expected_memory_state =
|
||||
self.expected_memory_state == MemoryState::from_sim_value(&memory_state);
|
||||
}
|
||||
#[hdl]
|
||||
fn test_passed(&self) -> bool {
|
||||
self.retired.end >= self.insns.len()
|
||||
if self.retired_async_error {
|
||||
self.d_cache_caused_memory_error
|
||||
} else if self.retired.end >= self.insns.len() {
|
||||
!self.d_cache_caused_memory_error
|
||||
&& self.matches_expected_memory_state
|
||||
&& self.insns.iter().all(|insn| {
|
||||
insn.output
|
||||
.as_ref()
|
||||
.is_some_and(|output| *output == insn.expected_output)
|
||||
})
|
||||
} else {
|
||||
false
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
fn cancel_all_unretired(&mut self) {
|
||||
|
|
@ -2059,6 +2195,8 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
canceling,
|
||||
expected_memory_state: _,
|
||||
matches_expected_memory_state: _,
|
||||
d_cache_caused_memory_error: _,
|
||||
retired_async_error: _,
|
||||
config: _,
|
||||
load_store_unit_index: _,
|
||||
input_unit_index: _,
|
||||
|
|
@ -2071,14 +2209,17 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
mop: _,
|
||||
sent_inputs_ready,
|
||||
sent_is_no_longer_speculative,
|
||||
caused_cancel_before_retire,
|
||||
sent_other_units_cant_cause_cancels_before,
|
||||
caused_cancel,
|
||||
cant_cause_cancel,
|
||||
output,
|
||||
expected_output: _,
|
||||
finished,
|
||||
} = insn;
|
||||
*sent_inputs_ready = false;
|
||||
*sent_is_no_longer_speculative = false;
|
||||
*caused_cancel_before_retire = false;
|
||||
*sent_other_units_cant_cause_cancels_before = false;
|
||||
*caused_cancel = None;
|
||||
*cant_cause_cancel = false;
|
||||
*output = None;
|
||||
*finished = false;
|
||||
|
|
@ -2095,9 +2236,11 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
mop: _,
|
||||
sent_inputs_ready: _,
|
||||
sent_is_no_longer_speculative: _,
|
||||
caused_cancel_before_retire: _,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
caused_cancel: _,
|
||||
cant_cause_cancel: _,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
finished: _,
|
||||
} = insn;
|
||||
if let Some(cycles_after_start_to_cancel) = cycles_after_start_to_cancel {
|
||||
|
|
@ -2110,16 +2253,25 @@ impl<C: PhantomConstCpuConfig> LoadStoreTesterState<C> {
|
|||
mop: _,
|
||||
sent_inputs_ready: _,
|
||||
sent_is_no_longer_speculative: _,
|
||||
caused_cancel_before_retire,
|
||||
sent_other_units_cant_cause_cancels_before: _,
|
||||
caused_cancel,
|
||||
cant_cause_cancel: _,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
finished,
|
||||
} = insn;
|
||||
if *cycles_after_start_to_cancel == Some(0) {
|
||||
*cycles_after_start_to_cancel = None;
|
||||
return self.cancel_all_unretired();
|
||||
}
|
||||
if *caused_cancel_before_retire {
|
||||
if let Some(caused_cancel) = caused_cancel {
|
||||
if caused_cancel.cancel_after_retire() {
|
||||
self.retired.end += 1;
|
||||
}
|
||||
match caused_cancel {
|
||||
InsnCausedCancel::Retry => {}
|
||||
InsnCausedCancel::AsyncError => self.retired_async_error = true,
|
||||
}
|
||||
return self.cancel_all_unretired();
|
||||
}
|
||||
if *finished {
|
||||
|
|
@ -2149,6 +2301,7 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _,
|
||||
output_ready: _,
|
||||
finish_cause_cancel: _,
|
||||
|
|
@ -2168,6 +2321,11 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
state.to_load_store_is_no_longer_speculative(),
|
||||
)
|
||||
.await;
|
||||
sim.write(
|
||||
other_units_cant_cause_cancels_before,
|
||||
state.to_load_store_other_units_cant_cause_cancels_before(),
|
||||
)
|
||||
.await;
|
||||
} else {
|
||||
sim.write(enqueue.data, enqueue.ty().data.HdlNone()).await;
|
||||
sim.write(inputs_ready, inputs_ready.ty().HdlNone()).await;
|
||||
|
|
@ -2176,6 +2334,11 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
is_no_longer_speculative.ty().HdlNone(),
|
||||
)
|
||||
.await;
|
||||
sim.write(
|
||||
other_units_cant_cause_cancels_before,
|
||||
other_units_cant_cause_cancels_before.ty().HdlNone(),
|
||||
)
|
||||
.await;
|
||||
}
|
||||
sim.write(cancel_all.data, state.to_load_store_cancel_all())
|
||||
.await;
|
||||
|
|
@ -2190,6 +2353,7 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2213,6 +2377,15 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
{
|
||||
state.handle_to_load_store_is_no_longer_speculative(is_no_longer_speculative);
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
state.handle_to_load_store_other_units_cant_cause_cancels_before(
|
||||
other_units_cant_cause_cancels_before,
|
||||
);
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await {
|
||||
|
|
@ -2243,8 +2416,12 @@ async fn load_store_tester_impl<C: PhantomConstCpuConfig>(
|
|||
let MockDCacheToLoadStoreTester {
|
||||
memory_state_seed: _,
|
||||
memory_state,
|
||||
memory_error,
|
||||
} = from_mock_d_cache;
|
||||
state.handle_from_mock_d_cache_memory_state(sim.read_past(memory_state, cd.clk).await);
|
||||
state.handle_from_mock_d_cache_memory_state(
|
||||
sim.read_past(memory_state, cd.clk).await,
|
||||
sim.read_past_bool(memory_error, cd.clk).await,
|
||||
);
|
||||
}
|
||||
state.step();
|
||||
}
|
||||
|
|
@ -2293,6 +2470,7 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel: _,
|
||||
output_ready: _,
|
||||
finish_cause_cancel: _,
|
||||
|
|
@ -2318,6 +2496,11 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
|
|||
is_no_longer_speculative.ty().HdlNone(),
|
||||
)
|
||||
.await;
|
||||
sim.write(
|
||||
other_units_cant_cause_cancels_before,
|
||||
other_units_cant_cause_cancels_before.ty().HdlNone(),
|
||||
)
|
||||
.await;
|
||||
sim.write(unit_outputs_ready, false).await;
|
||||
sim.write(cancel_all.data, HdlNone()).await;
|
||||
sim.write(test_passed, false).await;
|
||||
|
|
@ -2326,6 +2509,7 @@ fn load_store_tester(config: PhantomConst<CpuConfig>) {
|
|||
let MockDCacheToLoadStoreTester {
|
||||
memory_state_seed,
|
||||
memory_state: _,
|
||||
memory_error: _,
|
||||
} = from_mock_d_cache;
|
||||
sim.write(
|
||||
memory_state_seed,
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ use cpu::{
|
|||
instruction::{
|
||||
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
|
||||
CompareMOp, CompareMode, ConditionMode, L2RegNum, L2RegisterFileMOp, LoadMOp,
|
||||
LoadStoreCommonMOp, LoadStoreConversion, LoadStoreMOp, LoadStoreWidth, MOp, MOpDestReg,
|
||||
MOpRegNum, MOpTrait, MoveRegMOp, OutputIntegerMode, PRegNum, ReadL2RegMOp,
|
||||
LoadStoreCommonMOp, LoadStoreConversion, LoadStoreMOp, LoadStoreOptions, LoadStoreWidth,
|
||||
MOp, MOpDestReg, MOpRegNum, MOpTrait, MoveRegMOp, OutputIntegerMode, PRegNum, ReadL2RegMOp,
|
||||
ShiftAmountOverflowBehavior, ShiftRotateDestLogicOp, ShiftRotateMOp, ShiftRotateMOpImm,
|
||||
ShiftRotateMode, StoreMOp, UnitNum, WriteL2RegMOp,
|
||||
},
|
||||
|
|
@ -20,8 +20,9 @@ use cpu::{
|
|||
ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
|
||||
PostDecodeOutputInterface, RenamedMOp, RetireToNextPcInterface,
|
||||
RetireToNextPcInterfaceInner, UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel,
|
||||
UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady,
|
||||
rename_execute_retire, to_unit_interfaces::ExecuteToUnitInterfaces,
|
||||
UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative,
|
||||
UnitMOpOtherUnitsCantCauseCancelsBefore, UnitOutputReady, rename_execute_retire,
|
||||
to_unit_interfaces::ExecuteToUnitInterfaces,
|
||||
},
|
||||
unit::{UnitKind, UnitMOp},
|
||||
util::array_vec::ArrayVec,
|
||||
|
|
@ -451,6 +452,7 @@ impl InsnsBuilder {
|
|||
)],
|
||||
));
|
||||
}
|
||||
#[hdl]
|
||||
fn power_isa_lbzu(&mut self, dest: usize, src: usize, disp: i16) {
|
||||
self.add_insn(Insn::new(
|
||||
4,
|
||||
|
|
@ -474,10 +476,13 @@ impl InsnsBuilder {
|
|||
[MOpRegNum::power_isa_gpr_reg_imm(src)],
|
||||
LoadStoreWidth.Width8Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
],
|
||||
));
|
||||
}
|
||||
#[hdl]
|
||||
fn power_isa_ld(&mut self, dest: usize, src: usize, disp: i16) {
|
||||
self.add_insn(Insn::new(
|
||||
4,
|
||||
|
|
@ -501,10 +506,13 @@ impl InsnsBuilder {
|
|||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
],
|
||||
));
|
||||
}
|
||||
#[hdl]
|
||||
fn power_isa_stb(&mut self, value_src: usize, addr_src: usize, disp: i16) {
|
||||
self.add_insn(Insn::new(
|
||||
4,
|
||||
|
|
@ -531,10 +539,13 @@ impl InsnsBuilder {
|
|||
],
|
||||
LoadStoreWidth.Width8Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
],
|
||||
));
|
||||
}
|
||||
#[hdl]
|
||||
fn power_isa_std(&mut self, value_src: usize, addr_src: usize, disp: i16) {
|
||||
self.add_insn(Insn::new(
|
||||
4,
|
||||
|
|
@ -561,10 +572,13 @@ impl InsnsBuilder {
|
|||
],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
],
|
||||
));
|
||||
}
|
||||
#[hdl]
|
||||
fn power_isa_stdu(&mut self, value_src: usize, addr_src: usize, disp: i16) {
|
||||
if value_src == addr_src {
|
||||
self.add_insn(Insn::new(
|
||||
|
|
@ -592,6 +606,8 @@ impl InsnsBuilder {
|
|||
],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(addr_src)], &[]),
|
||||
|
|
@ -626,6 +642,8 @@ impl InsnsBuilder {
|
|||
],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
#[hdl]
|
||||
LoadStoreOptions { is_cacheable: true },
|
||||
),
|
||||
],
|
||||
));
|
||||
|
|
@ -2468,6 +2486,14 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
|
|||
_is_no_longer_speculative: SimValue<UnitMOpIsNoLongerSpeculative<C>>,
|
||||
) {
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_mop_other_units_cant_cause_cancels_before(
|
||||
&mut self,
|
||||
_other_units_cant_cause_cancels_before: SimValue<
|
||||
UnitMOpOtherUnitsCantCauseCancelsBefore<C>,
|
||||
>,
|
||||
) {
|
||||
}
|
||||
fn cancel_all(&mut self) {
|
||||
let Self {
|
||||
global_state: _,
|
||||
|
|
@ -2508,6 +2534,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2586,6 +2613,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2612,6 +2640,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
enqueue: _, // we ignore enqueues since we don't need to track order for these instructions
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2630,6 +2659,15 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
{
|
||||
state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
state.handle_mop_other_units_cant_cause_cancels_before(
|
||||
other_units_cant_cause_cancels_before,
|
||||
);
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) =
|
||||
|
|
@ -2680,6 +2718,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2724,6 +2763,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative: _, // we don't care about being speculative for these instructions
|
||||
other_units_cant_cause_cancels_before: _, // we don't care about being speculative for these instructions
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -2984,6 +3024,23 @@ impl<C: PhantomConstCpuConfig> MockL2RegFileUnitState<C> {
|
|||
} = self.op_by_id_mut(&id);
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_mop_other_units_cant_cause_cancels_before(
|
||||
&mut self,
|
||||
other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
|
||||
) {
|
||||
#[hdl(sim)]
|
||||
let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
|
||||
other_units_cant_cause_cancels_before;
|
||||
let MockL2RegFileOp {
|
||||
mop: _,
|
||||
src_values: _,
|
||||
dest_value: _,
|
||||
sent_cant_cause_cancel: _,
|
||||
sent_output_ready: _,
|
||||
config: _,
|
||||
} = self.op_by_id_mut(&id);
|
||||
}
|
||||
#[hdl]
|
||||
fn peek_mop_cant_cause_cancel(&self) -> SimValue<HdlOption<UnitMOpCantCauseCancel<C>>> {
|
||||
let ret_ty = HdlOption[UnitMOpCantCauseCancel[self.config]];
|
||||
for MockL2RegFileOp {
|
||||
|
|
@ -3160,6 +3217,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3222,6 +3280,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3246,6 +3305,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3270,6 +3330,15 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
|
|||
{
|
||||
state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
state.handle_mop_other_units_cant_cause_cancels_before(
|
||||
other_units_cant_cause_cancels_before,
|
||||
);
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) =
|
||||
|
|
@ -3631,6 +3700,27 @@ impl<'a, C: PhantomConstCpuConfig> MockLoadStoreUnitState<'a, C> {
|
|||
*is_speculative = false;
|
||||
}
|
||||
#[hdl]
|
||||
fn handle_mop_other_units_cant_cause_cancels_before(
|
||||
&mut self,
|
||||
other_units_cant_cause_cancels_before: SimValue<UnitMOpOtherUnitsCantCauseCancelsBefore<C>>,
|
||||
) {
|
||||
#[hdl(sim)]
|
||||
let UnitMOpOtherUnitsCantCauseCancelsBefore::<_> { id, config: _ } =
|
||||
other_units_cant_cause_cancels_before;
|
||||
let MockLoadStoreOp {
|
||||
mop: _,
|
||||
is_speculative: _,
|
||||
src_values: _,
|
||||
dest_value: _,
|
||||
cycles_left: _,
|
||||
ran_nonspeculatively: _,
|
||||
sent_cant_cause_cancel: _,
|
||||
sent_output_ready: _,
|
||||
config: _,
|
||||
} = self.op_by_id_mut(&id);
|
||||
// TODO
|
||||
}
|
||||
#[hdl]
|
||||
fn peek_mop_cant_cause_cancel(&self) -> SimValue<HdlOption<UnitMOpCantCauseCancel<C>>> {
|
||||
let ret_ty = HdlOption[UnitMOpCantCauseCancel[self.config]];
|
||||
for MockLoadStoreOp {
|
||||
|
|
@ -3843,6 +3933,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3923,6 +4014,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
|
|||
enqueue,
|
||||
inputs_ready: _,
|
||||
is_no_longer_speculative: _,
|
||||
other_units_cant_cause_cancels_before: _,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3949,6 +4041,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
|
|||
enqueue,
|
||||
inputs_ready,
|
||||
is_no_longer_speculative,
|
||||
other_units_cant_cause_cancels_before,
|
||||
cant_cause_cancel,
|
||||
output_ready,
|
||||
finish_cause_cancel,
|
||||
|
|
@ -3972,6 +4065,15 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
|
|||
{
|
||||
state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
|
||||
}
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(other_units_cant_cause_cancels_before) = sim
|
||||
.read_past(other_units_cant_cause_cancels_before, cd.clk)
|
||||
.await
|
||||
{
|
||||
state.handle_mop_other_units_cant_cause_cancels_before(
|
||||
other_units_cant_cause_cancels_before,
|
||||
);
|
||||
}
|
||||
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(cant_cause_cancel) =
|
||||
|
|
|
|||
|
|
@ -13355,7 +13355,7 @@ b0 4rj;&$
|
|||
b0 4rj;&%
|
||||
#116000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20u8 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20u8 dcA>9
|
||||
b10 "53=.
|
||||
b10001000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
|
|
@ -14531,7 +14531,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#123000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20u8 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20u8 dcA>9
|
||||
b10001100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -14903,7 +14903,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#125000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20u16 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20u16 dcA>9
|
||||
b10100000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -15932,7 +15932,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#132000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20u16 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20u16 dcA>9
|
||||
b10100100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -16257,7 +16257,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#134000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20s16 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20s16 dcA>9
|
||||
b10101000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -17286,7 +17286,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#141000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20s16 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20s16 dcA>9
|
||||
b10101100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -17658,7 +17658,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#143000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20u32 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20u32 dcA>9
|
||||
b10000000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -18687,7 +18687,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#150000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20u32 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20u32 dcA>9
|
||||
b10000100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -19059,7 +19059,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#152000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20s32 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20s32 dcA>9
|
||||
b11101000011001000001001000110110 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -20060,7 +20060,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#159000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20s32 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20s32 dcA>9
|
||||
b1111100011001000010101011101010 8O._Q
|
||||
b110010000101010111010 <EJ`t
|
||||
b101010111010 US1xY
|
||||
|
|
@ -20243,7 +20243,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#160000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x200x0_i34,\x20u64 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp),\x20cacheable,\x20u64 dcA>9
|
||||
b11101000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -21244,7 +21244,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#167000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x200x0_i34,\x20u64 dcA>9
|
||||
sLoad\x20{r0x23(pwr:r3)},\x20r0x24(pwr:r4),\x20cacheable,\x20u64 dcA>9
|
||||
b11101000011001000001001000110101 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -21618,7 +21618,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#169000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u8 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u8 dcA>9
|
||||
b10011000011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -22647,7 +22647,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#176000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u8 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u8 dcA>9
|
||||
b10011100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -22879,7 +22879,7 @@ b1000100 4rj;&$
|
|||
b1000100 4rj;&%
|
||||
#177000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u8 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u8 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b10011100011000110001001000110100 8O._Q
|
||||
|
|
@ -22991,7 +22991,7 @@ b1000011 4rj;&$
|
|||
b1000011 4rj;&%
|
||||
#178000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u8 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u8 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b1111100011001000010100111101110 8O._Q
|
||||
|
|
@ -23225,7 +23225,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#179000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u8 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u8 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b1111100011000110010100111101110 8O._Q
|
||||
|
|
@ -23337,7 +23337,7 @@ b10100011 4rj;&$
|
|||
b10100011 4rj;&%
|
||||
#180000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u16 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u16 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b10110000011001000001001000110100 8O._Q
|
||||
|
|
@ -24451,7 +24451,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#187000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u16 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u16 dcA>9
|
||||
b10110100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -24683,7 +24683,7 @@ b1000100 4rj;&$
|
|||
b1000100 4rj;&%
|
||||
#188000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u16 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u16 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b10110100011000110001001000110100 8O._Q
|
||||
|
|
@ -24795,7 +24795,7 @@ b1000011 4rj;&$
|
|||
b1000011 4rj;&%
|
||||
#189000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u16 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u16 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b1111100011001000010101101101110 8O._Q
|
||||
|
|
@ -25029,7 +25029,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#190000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u16 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u16 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b1111100011000110010101101101110 8O._Q
|
||||
|
|
@ -25141,7 +25141,7 @@ b10100011 4rj;&$
|
|||
b10100011 4rj;&%
|
||||
#191000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u32 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u32 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b10010000011001000001001000110100 8O._Q
|
||||
|
|
@ -26263,7 +26263,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#198000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u32 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u32 dcA>9
|
||||
b10010100011001000001001000110100 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -26495,7 +26495,7 @@ b1000100 4rj;&$
|
|||
b1000100 4rj;&%
|
||||
#199000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u32 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u32 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b10010100011000110001001000110100 8O._Q
|
||||
|
|
@ -26607,7 +26607,7 @@ b1000011 4rj;&$
|
|||
b1000011 4rj;&%
|
||||
#200000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u32 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u32 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b1111100011001000010100101101110 8O._Q
|
||||
|
|
@ -26829,7 +26829,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#201000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u32 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u32 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b1111100011000110010100101101110 8O._Q
|
||||
|
|
@ -26941,7 +26941,7 @@ b10100011 4rj;&$
|
|||
b10100011 4rj;&%
|
||||
#202000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u64 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u64 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b11111000011001000001001000110100 8O._Q
|
||||
|
|
@ -28023,7 +28023,7 @@ b10100000 4rj;&$
|
|||
b10100000 4rj;&%
|
||||
#209000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u64 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u64 dcA>9
|
||||
b11111000011001000001001000110101 8O._Q
|
||||
b110010000010010001101 <EJ`t
|
||||
b10010001101 US1xY
|
||||
|
|
@ -28256,7 +28256,7 @@ b1000100 4rj;&$
|
|||
b1000100 4rj;&%
|
||||
#210000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20rzero,\x200x1234_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u64 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u64 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b11111000011000110001001000110101 8O._Q
|
||||
|
|
@ -28368,7 +28368,7 @@ b1000011 4rj;&$
|
|||
b1000011 4rj;&%
|
||||
#211000000
|
||||
sAddSub\x20{r0x24(pwr:r4)},\x20r0x24(pwr:r4),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x200x0_i34,\x20u64 dcA>9
|
||||
sStore\x20{},\x20r0x24(pwr:r4),\x20r0x23(pwr:r3),\x20cacheable,\x20u64 dcA>9
|
||||
sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 |N3g]
|
||||
b10 "53=.
|
||||
b1111100011001000010100101101010 8O._Q
|
||||
|
|
@ -28603,7 +28603,7 @@ b10100100 4rj;&$
|
|||
b10100100 4rj;&%
|
||||
#212000000
|
||||
sAddSub\x20{r0x8(pwr:temp)},\x20r0x23(pwr:r3),\x20r0x25(pwr:r5),\x200x0_i34 Ue5%A
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x200x0_i34,\x20u64 dcA>9
|
||||
sStore\x20{},\x20r0x8(pwr:temp),\x20r0x23(pwr:r3),\x20cacheable,\x20u64 dcA>9
|
||||
sMoveReg\x20{r0x23(pwr:r3)},\x20r0x8(pwr:temp) |N3g]
|
||||
b11 "53=.
|
||||
b1111100011000110010100101101010 8O._Q
|
||||
|
|
|
|||
|
|
@ -3,11 +3,17 @@
|
|||
|
||||
use crate::test_cases::{TestCase, insn_double};
|
||||
use cpu::instruction::{
|
||||
AddSubMOp, LoadMOp, LoadStoreConversion, LoadStoreWidth, MOpDestReg, MOpRegNum,
|
||||
OutputIntegerMode,
|
||||
AddSubMOp, LoadMOp, LoadStoreConversion, LoadStoreOptions, LoadStoreWidth, MOpDestReg,
|
||||
MOpRegNum, OutputIntegerMode,
|
||||
};
|
||||
use fayalite::prelude::*;
|
||||
|
||||
#[hdl]
|
||||
fn load_store_options(is_cacheable: bool) -> SimValue<LoadStoreOptions> {
|
||||
#[hdl(sim)]
|
||||
LoadStoreOptions { is_cacheable }
|
||||
}
|
||||
|
||||
/// covers instructions in PowerISA v3.1C Book I 3.3.2 Fixed-Point Load Instructions
|
||||
pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
||||
macro_rules! load_prefixed {
|
||||
|
|
@ -45,6 +51,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -86,6 +93,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -123,6 +131,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
[MOpRegNum::power_isa_gpr_reg_imm($ra)],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -164,6 +173,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -201,6 +211,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
[MOpRegNum::power_isa_gpr_reg_imm($ra)],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
|
|||
|
|
@ -3,11 +3,17 @@
|
|||
|
||||
use crate::test_cases::{TestCase, insn_double, insn_triple};
|
||||
use cpu::instruction::{
|
||||
AddSubMOp, LoadStoreConversion, LoadStoreWidth, MOpDestReg, MOpRegNum, MoveRegMOp,
|
||||
OutputIntegerMode, StoreMOp,
|
||||
AddSubMOp, LoadStoreConversion, LoadStoreOptions, LoadStoreWidth, MOpDestReg, MOpRegNum,
|
||||
MoveRegMOp, OutputIntegerMode, StoreMOp,
|
||||
};
|
||||
use fayalite::prelude::*;
|
||||
|
||||
#[hdl]
|
||||
fn load_store_options(is_cacheable: bool) -> SimValue<LoadStoreOptions> {
|
||||
#[hdl(sim)]
|
||||
LoadStoreOptions { is_cacheable }
|
||||
}
|
||||
|
||||
/// covers instructions in PowerISA v3.1C Book I 3.3.3 Fixed-Point Store Instructions
|
||||
pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
||||
macro_rules! store_prefixed {
|
||||
|
|
@ -47,6 +53,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -90,6 +97,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -130,6 +138,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
|
|
@ -167,6 +176,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -211,6 +221,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
@ -251,6 +262,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
|
|
@ -292,6 +304,7 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
load_store_options(true),
|
||||
),
|
||||
]
|
||||
},
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue