forked from libre-chip/fayalite
1603 lines
No EOL
68 KiB
Text
1603 lines
No EOL
68 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 9,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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|
ty: Bool,
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},
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|
SlotDebugData {
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name: "",
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|
ty: Bool,
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|
},
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|
SlotDebugData {
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|
name: "",
|
|
ty: Bool,
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|
},
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|
SlotDebugData {
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|
name: "",
|
|
ty: Bool,
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|
},
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|
SlotDebugData {
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|
name: "",
|
|
ty: Bool,
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|
},
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|
SlotDebugData {
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name: "",
|
|
ty: Bool,
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|
},
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|
SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 58,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o",
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ty: UInt<6>,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<3>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<3>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<5>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<5>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<6>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<6>,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next",
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ty: Bool,
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},
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SlotDebugData {
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name: ".clk",
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ty: Clock,
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},
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SlotDebugData {
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name: ".rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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|
SlotDebugData {
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name: "",
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ty: SyncReset,
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},
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|
SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
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ty: Clock,
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|
},
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|
SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next",
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ty: Bool,
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},
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SlotDebugData {
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name: ".clk",
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ty: Clock,
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},
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SlotDebugData {
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name: ".rst",
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ty: SyncReset,
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|
},
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|
SlotDebugData {
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name: "",
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ty: Clock,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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|
SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next",
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ty: Bool,
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},
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SlotDebugData {
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name: ".clk",
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ty: Clock,
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},
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|
SlotDebugData {
|
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name: ".rst",
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ty: SyncReset,
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},
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|
SlotDebugData {
|
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name: "",
|
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ty: Clock,
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},
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|
SlotDebugData {
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name: "",
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ty: Bool,
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},
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|
SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:9:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
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src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:11:1
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1: Copy {
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dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
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src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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2: NotU {
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dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
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width: 1,
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},
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// at: module-XXXXXXXXXX.rs:8:1
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3: Copy {
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dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
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src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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4: Copy {
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dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
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src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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5: Copy {
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dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
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src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:10:1
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6: Copy {
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dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:9:1
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7: Copy {
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dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
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src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
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},
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8: Copy {
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dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
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src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:11:1
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9: Copy {
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dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
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src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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10: Copy {
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dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
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src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
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},
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11: NotU {
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dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
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width: 1,
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},
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// at: module-XXXXXXXXXX.rs:8:1
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12: Copy {
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dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
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src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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13: Copy {
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dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
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src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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14: Copy {
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dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
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src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:10:1
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15: Copy {
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dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
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|
src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
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|
},
|
|
// at: module-XXXXXXXXXX.rs:9:1
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16: Copy {
|
|
dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
|
|
},
|
|
17: Copy {
|
|
dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
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|
src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
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|
},
|
|
// at: module-XXXXXXXXXX.rs:11:1
|
|
18: Copy {
|
|
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
19: Copy {
|
|
dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
|
|
},
|
|
20: NotU {
|
|
dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
|
|
width: 1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:8:1
|
|
21: Copy {
|
|
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:7:1
|
|
22: Copy {
|
|
dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
23: Copy {
|
|
dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:10:1
|
|
24: Copy {
|
|
dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:9:1
|
|
25: Copy {
|
|
dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
26: Const {
|
|
dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
value: 0x0,
|
|
},
|
|
27: Copy {
|
|
dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
|
|
src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
28: Copy {
|
|
dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
|
|
},
|
|
29: Copy {
|
|
dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
|
|
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:6:1
|
|
30: IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
|
|
},
|
|
31: AndSmall {
|
|
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
32: Copy {
|
|
dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
|
|
},
|
|
33: Copy {
|
|
dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
|
|
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:6:1
|
|
34: IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
|
|
},
|
|
35: AndSmall {
|
|
dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
36: Copy {
|
|
dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
|
|
},
|
|
37: Copy {
|
|
dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
|
|
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:6:1
|
|
38: IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
|
|
},
|
|
39: AndSmall {
|
|
dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
40: Copy {
|
|
dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
|
|
},
|
|
41: Shl {
|
|
dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
|
lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: 5,
|
|
},
|
|
42: Copy {
|
|
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
|
|
},
|
|
43: Shl {
|
|
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
|
|
lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: 4,
|
|
},
|
|
44: Copy {
|
|
dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
|
|
},
|
|
45: Shl {
|
|
dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
|
lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: 3,
|
|
},
|
|
46: Copy {
|
|
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
|
|
},
|
|
47: Shl {
|
|
dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
|
|
lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: 2,
|
|
},
|
|
48: Copy {
|
|
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
|
|
},
|
|
49: Shl {
|
|
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: 1,
|
|
},
|
|
50: Copy {
|
|
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
|
|
},
|
|
51: Or {
|
|
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
},
|
|
52: Or {
|
|
dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
|
|
lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
|
|
},
|
|
53: Or {
|
|
dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
|
lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
|
|
rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
|
},
|
|
54: Or {
|
|
dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
|
|
lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
|
rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
|
|
},
|
|
55: Or {
|
|
dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
|
lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
|
|
rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
56: Copy {
|
|
dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
|
|
src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:6:1
|
|
57: BranchIfSmallZero {
|
|
target: 59,
|
|
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
58: Copy {
|
|
dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
|
|
},
|
|
59: BranchIfSmallZero {
|
|
target: 61,
|
|
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
60: Copy {
|
|
dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
|
|
},
|
|
61: BranchIfSmallZero {
|
|
target: 63,
|
|
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
62: Copy {
|
|
dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
|
|
},
|
|
63: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
64: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
65: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
66: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 66,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
0,
|
|
0,
|
|
1,
|
|
1,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
],
|
|
},
|
|
sim_only_slots: StatePart {
|
|
value: [],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::ripple_counter,
|
|
instantiated: Module {
|
|
name: ripple_counter,
|
|
..
|
|
},
|
|
},
|
|
main_module: SimulationModuleState {
|
|
base_targets: [
|
|
Instance {
|
|
name: <simulator>::ripple_counter,
|
|
instantiated: Module {
|
|
name: ripple_counter,
|
|
..
|
|
},
|
|
}.clk,
|
|
Instance {
|
|
name: <simulator>::ripple_counter,
|
|
instantiated: Module {
|
|
name: ripple_counter,
|
|
..
|
|
},
|
|
}.o,
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::ripple_counter,
|
|
instantiated: Module {
|
|
name: ripple_counter,
|
|
..
|
|
},
|
|
}.clk,
|
|
Instance {
|
|
name: <simulator>::ripple_counter,
|
|
instantiated: Module {
|
|
name: ripple_counter,
|
|
..
|
|
},
|
|
}.o,
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
extern_modules: [
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX-2.rs:4:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
wait_targets: {
|
|
Change {
|
|
key: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
},
|
|
value: SimValue {
|
|
ty: Clock,
|
|
value: OpaqueSimValue {
|
|
bits: 0x0_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX-2.rs:4:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
wait_targets: {
|
|
Change {
|
|
key: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
},
|
|
value: SimValue {
|
|
ty: Clock,
|
|
value: OpaqueSimValue {
|
|
bits: 0x0_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::clk,
|
|
is_input: true,
|
|
ty: Clock,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
}: ModuleIO {
|
|
name: sw_reg::o,
|
|
is_input: false,
|
|
ty: Bool,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX-2.rs:4:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
wait_targets: {
|
|
Change {
|
|
key: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
},
|
|
value: SimValue {
|
|
ty: Clock,
|
|
value: OpaqueSimValue {
|
|
bits: 0x0_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
],
|
|
state_ready_to_run: false,
|
|
trace_decls: TraceModule {
|
|
name: "ripple_counter",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clk",
|
|
child: TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
ty: Clock,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceUInt {
|
|
location: TraceScalarId(1),
|
|
name: "o",
|
|
ty: UInt<6>,
|
|
flow: Sink,
|
|
},
|
|
ty: UInt<6>,
|
|
flow: Sink,
|
|
},
|
|
TraceWire {
|
|
name: "bits",
|
|
child: TraceArray {
|
|
name: "bits",
|
|
elements: [
|
|
TraceBool {
|
|
location: TraceScalarId(2),
|
|
name: "[0]",
|
|
flow: Duplex,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(3),
|
|
name: "[1]",
|
|
flow: Duplex,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(4),
|
|
name: "[2]",
|
|
flow: Duplex,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(5),
|
|
name: "[3]",
|
|
flow: Duplex,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "[4]",
|
|
flow: Duplex,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(7),
|
|
name: "[5]",
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Array<Bool, 6>,
|
|
flow: Duplex,
|
|
},
|
|
ty: Array<Bool, 6>,
|
|
},
|
|
TraceReg {
|
|
name: "bit_reg_0",
|
|
child: TraceBool {
|
|
location: TraceScalarId(8),
|
|
name: "bit_reg_0",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceInstance {
|
|
name: "bit_reg_1",
|
|
instance_io: TraceBundle {
|
|
name: "bit_reg_1",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(11),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(12),
|
|
name: "o",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "sw_reg",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clk",
|
|
child: TraceClock {
|
|
location: TraceScalarId(9),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
ty: Clock,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceBool {
|
|
location: TraceScalarId(10),
|
|
name: "o",
|
|
flow: Sink,
|
|
},
|
|
ty: Bool,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
},
|
|
TraceReg {
|
|
name: "bit_reg_2",
|
|
child: TraceBool {
|
|
location: TraceScalarId(13),
|
|
name: "bit_reg_2",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceInstance {
|
|
name: "bit_reg_3",
|
|
instance_io: TraceBundle {
|
|
name: "bit_reg_3",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(16),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(17),
|
|
name: "o",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "sw_reg",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clk",
|
|
child: TraceClock {
|
|
location: TraceScalarId(14),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
ty: Clock,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceBool {
|
|
location: TraceScalarId(15),
|
|
name: "o",
|
|
flow: Sink,
|
|
},
|
|
ty: Bool,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
},
|
|
TraceReg {
|
|
name: "bit_reg_4",
|
|
child: TraceBool {
|
|
location: TraceScalarId(18),
|
|
name: "bit_reg_4",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceInstance {
|
|
name: "bit_reg_5",
|
|
instance_io: TraceBundle {
|
|
name: "bit_reg_5",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(21),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(22),
|
|
name: "o",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "sw_reg",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clk",
|
|
child: TraceClock {
|
|
location: TraceScalarId(19),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
ty: Clock,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceBool {
|
|
location: TraceScalarId(20),
|
|
name: "o",
|
|
flow: Sink,
|
|
},
|
|
ty: Bool,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
o: Bool,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
ty: UInt<6>,
|
|
},
|
|
state: 0x00,
|
|
last_state: 0x00,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(24),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(33),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(34),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(31),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(12),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(32),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(13),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(36),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(14),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(44),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(15),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(45),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(16),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(42),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(17),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(43),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(18),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(47),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(19),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(55),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(20),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(56),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(21),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(53),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(22),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(54),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 256 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
StatePartIndex<SmallSlots>(4),
|
|
StatePartIndex<SmallSlots>(7),
|
|
],
|
|
..
|
|
} |