forked from libre-chip/fayalite
2254 lines
No EOL
107 KiB
Text
2254 lines
No EOL
107 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 12,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 31,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]",
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ty: Bool,
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},
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SlotDebugData {
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name: "[0]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "[1]",
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ty: Enum {
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Text(UInt<512>),
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FmtError,
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},
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},
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SlotDebugData {
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name: "[0]",
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ty: Bool,
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},
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SlotDebugData {
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name: "[1]",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 1,
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debug_data: [
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(),
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],
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layout_data: [
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MemoryData {
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array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
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data: [
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// len = 0x4
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[0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
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[0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
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[0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
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[0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
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],
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},
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],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:16:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool },
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src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]", ty: Bool },
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool },
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src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:15:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool },
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src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:14:1
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3: Copy {
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dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
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src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
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},
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4: Copy {
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dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
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src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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5: CastToUInt {
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dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr", ty: UInt<8> },
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dest_width: 2,
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},
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// at: module-XXXXXXXXXX.rs:13:1
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6: Copy {
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dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:12:1
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7: Copy {
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dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:9:1
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8: Copy {
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dest: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool },
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src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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9: CastToUInt {
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dest: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr", ty: UInt<8> },
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dest_width: 2,
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},
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// at: module-XXXXXXXXXX.rs:8:1
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10: Copy {
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dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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11: Copy {
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dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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12: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> },
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},
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13: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(8), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool },
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},
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14: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(7), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock },
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},
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15: AndSmall {
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dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(7), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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16: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> },
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},
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17: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool },
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},
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18: BranchIfSmallZero {
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target: 22,
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value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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19: MemoryReadUInt {
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dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
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memory: StatePartIndex<Memories>(0), // (MemoryData {
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// array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
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// data: [
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// // len = 0x4
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// [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada,
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// [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
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// [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada,
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|
// [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada,
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// ],
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// }) (),
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addr: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
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stride: 1026,
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start: 0,
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width: 513,
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},
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20: MemoryReadUInt {
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dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
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|
memory: StatePartIndex<Memories>(0), // (MemoryData {
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|
// array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
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// data: [
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|
// // len = 0x4
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|
// [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada,
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|
// [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
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|
// [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada,
|
|
// [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada,
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// ],
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|
// }) (),
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|
addr: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
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stride: 1026,
|
|
start: 513,
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width: 513,
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},
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21: Branch {
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target: 24,
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},
|
|
22: Const {
|
|
dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
value: 0x0,
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|
},
|
|
23: Const {
|
|
dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
value: 0x0,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:10:1
|
|
24: Copy {
|
|
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
src: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
},
|
|
25: Copy {
|
|
dest: StatePartIndex<BigSlots>(5), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
src: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
26: IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock },
|
|
},
|
|
27: AndSmall {
|
|
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
28: BranchIfSmallZero {
|
|
target: 29,
|
|
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
29: BranchIfSmallZero {
|
|
target: 41,
|
|
value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
30: CopySmall {
|
|
dest: StatePartIndex<SmallSlots>(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
|
|
src: StatePartIndex<SmallSlots>(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
|
|
},
|
|
31: CopySmall {
|
|
dest: StatePartIndex<SmallSlots>(11), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<SmallSlots>(8), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
32: Copy {
|
|
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
},
|
|
33: Copy {
|
|
dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
},
|
|
34: Copy {
|
|
dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool },
|
|
},
|
|
35: Copy {
|
|
dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool },
|
|
},
|
|
36: BranchIfSmallZero {
|
|
target: 41,
|
|
value: StatePartIndex<SmallSlots>(11), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
37: BranchIfZero {
|
|
target: 39,
|
|
value: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
|
|
},
|
|
38: MemoryWriteUInt {
|
|
value: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
memory: StatePartIndex<Memories>(0), // (MemoryData {
|
|
// array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
|
|
// data: [
|
|
// // len = 0x4
|
|
// [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada,
|
|
// [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
|
|
// [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada,
|
|
// [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada,
|
|
// ],
|
|
// }) (),
|
|
addr: StatePartIndex<SmallSlots>(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
|
|
stride: 1026,
|
|
start: 0,
|
|
width: 513,
|
|
},
|
|
39: BranchIfZero {
|
|
target: 41,
|
|
value: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
|
|
},
|
|
40: MemoryWriteUInt {
|
|
value: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} },
|
|
memory: StatePartIndex<Memories>(0), // (MemoryData {
|
|
// array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
|
|
// data: [
|
|
// // len = 0x4
|
|
// [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada,
|
|
// [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
|
|
// [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada,
|
|
// [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada,
|
|
// ],
|
|
// }) (),
|
|
addr: StatePartIndex<SmallSlots>(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> },
|
|
stride: 1026,
|
|
start: 513,
|
|
width: 513,
|
|
},
|
|
41: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
42: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(7), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
43: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 43,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [
|
|
MemoryData {
|
|
array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
|
|
data: [
|
|
// len = 0x4
|
|
[0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada,
|
|
[0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
|
|
[0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada,
|
|
[0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada,
|
|
],
|
|
},
|
|
],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
0,
|
|
0,
|
|
1,
|
|
1,
|
|
1,
|
|
0,
|
|
0,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
1,
|
|
1,
|
|
1,
|
|
0,
|
|
1 (modified),
|
|
1 (modified),
|
|
1,
|
|
1,
|
|
0,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
1,
|
|
],
|
|
},
|
|
sim_only_slots: StatePart {
|
|
value: [],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
},
|
|
main_module: SimulationModuleState {
|
|
base_targets: [
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.clk,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write,
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.clk,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.addr,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.clk,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.data,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.data.<inner>,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.data.<inner>[0],
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.data.<inner>[1],
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.read.en,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.addr,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.clk,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.data,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.data[0],
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.data[0].<inner>,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.data[1],
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.data[1].<inner>,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.en,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.mask,
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.mask[0],
|
|
Instance {
|
|
name: <simulator>::sim_trace_as_string,
|
|
instantiated: Module {
|
|
name: sim_trace_as_string,
|
|
..
|
|
},
|
|
}.write.mask[1],
|
|
},
|
|
did_initial_settle: true,
|
|
clocks_for_past: {},
|
|
},
|
|
extern_modules: [],
|
|
trace_decls: TraceModule {
|
|
name: "sim_trace_as_string",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clk",
|
|
child: TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
ty: Clock,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "read",
|
|
child: TraceBundle {
|
|
name: "read",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(1),
|
|
name: "addr",
|
|
ty: UInt<8>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(2),
|
|
name: "en",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(3),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(4),
|
|
name: "data",
|
|
ty: TraceAsString {
|
|
inner_ty: Array<Enum {Text(UInt<512>), FmtError}, 2>,
|
|
..
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<8>,
|
|
/* offset = 8 */
|
|
en: Bool,
|
|
/* offset = 9 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 10 */
|
|
data: TraceAsString {
|
|
inner_ty: Array<Enum {Text(UInt<512>), FmtError}, 2>,
|
|
..
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<8>,
|
|
/* offset = 8 */
|
|
en: Bool,
|
|
/* offset = 9 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 10 */
|
|
data: TraceAsString {
|
|
inner_ty: Array<Enum {Text(UInt<512>), FmtError}, 2>,
|
|
..
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "write",
|
|
child: TraceBundle {
|
|
name: "write",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(5),
|
|
name: "addr",
|
|
ty: UInt<8>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "en",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(7),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceArray {
|
|
name: "data",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(8),
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(9),
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Source,
|
|
},
|
|
TraceArray {
|
|
name: "mask",
|
|
elements: [
|
|
TraceBool {
|
|
location: TraceScalarId(10),
|
|
name: "[0]",
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(11),
|
|
name: "[1]",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Array<Bool, 2>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<8>,
|
|
/* offset = 8 */
|
|
en: Bool,
|
|
/* offset = 9 */
|
|
clk: Clock,
|
|
/* offset = 10 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1036 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<8>,
|
|
/* offset = 8 */
|
|
en: Bool,
|
|
/* offset = 9 */
|
|
clk: Clock,
|
|
/* offset = 10 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1036 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 1026,
|
|
element_type: TraceArray {
|
|
name: "mem",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 4,
|
|
stride: 1026,
|
|
start: 0,
|
|
len: 513,
|
|
},
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 4,
|
|
stride: 1026,
|
|
start: 513,
|
|
len: 513,
|
|
},
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "r0",
|
|
bundle: TraceBundle {
|
|
name: "r0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(12),
|
|
name: "addr",
|
|
ty: UInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(13),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(14),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "data",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(15),
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(16),
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
},
|
|
},
|
|
TraceMemPort {
|
|
name: "w1",
|
|
bundle: TraceBundle {
|
|
name: "w1",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(17),
|
|
name: "addr",
|
|
ty: UInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(18),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(19),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "data",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(20),
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(21),
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "mask",
|
|
elements: [
|
|
TraceBool {
|
|
location: TraceScalarId(22),
|
|
name: "[0]",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(23),
|
|
name: "[1]",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<Bool, 2>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
/* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1030 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
/* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1030 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x01,
|
|
last_state: 0x01,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Array<Enum {Text(UInt<512>), FmtError}, 2>,
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 2,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Array<Enum {Text(UInt<512>), FmtError}, 2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 2,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Array {
|
|
elements_non_empty: [
|
|
CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 2 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001_u1026,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0x174C56D74C56DB595B400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000BA60B6BA62B6DACADA_u1026,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x01,
|
|
last_state: 0x01,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(12),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(12),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(13),
|
|
ty: UInt<2>,
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(13),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(14),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(14),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(15),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(15),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0xBA60B6BA62B6DACADA_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(16),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 17, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0xBA62B6BA62B6DACADA_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(17),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(18),
|
|
ty: UInt<2>,
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(18),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(19),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(19),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(20),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(20),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 5, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 21, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(21),
|
|
kind: TraceAsString {
|
|
layout: CompiledTypeLayout {
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Transparent {
|
|
inner: CompiledTypeLayout {
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]",
|
|
ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 5, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
},
|
|
maybe_changed: true,
|
|
state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
last_state: OpaqueSimValue {
|
|
bits: 0x1_u513,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(22),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(23),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(23),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(24),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
],
|
|
trace_memories: {
|
|
StatePartIndex<Memories>(0): TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 1026,
|
|
element_type: TraceArray {
|
|
name: "mem",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 4,
|
|
stride: 1026,
|
|
start: 0,
|
|
len: 513,
|
|
},
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 4,
|
|
stride: 1026,
|
|
start: 513,
|
|
len: 513,
|
|
},
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "r0",
|
|
bundle: TraceBundle {
|
|
name: "r0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(12),
|
|
name: "addr",
|
|
ty: UInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(13),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(14),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "data",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(15),
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(16),
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
},
|
|
},
|
|
TraceMemPort {
|
|
name: "w1",
|
|
bundle: TraceBundle {
|
|
name: "w1",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(17),
|
|
name: "addr",
|
|
ty: UInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(18),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(19),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "data",
|
|
elements: [
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(20),
|
|
name: "[0]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceTraceAsString {
|
|
location: TraceScalarId(21),
|
|
name: "[1]",
|
|
ty: TraceAsString {
|
|
inner_ty: Enum {
|
|
Text(UInt<512>),
|
|
FmtError,
|
|
},
|
|
..
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
flow: Sink,
|
|
},
|
|
TraceArray {
|
|
name: "mask",
|
|
elements: [
|
|
TraceBool {
|
|
location: TraceScalarId(22),
|
|
name: "[0]",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(23),
|
|
name: "[1]",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<Bool, 2>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
/* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1030 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<2>,
|
|
/* offset = 2 */
|
|
en: Bool,
|
|
/* offset = 3 */
|
|
clk: Clock,
|
|
/* offset = 4 */
|
|
data: Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>,
|
|
/* offset = 1030 */
|
|
mask: Array<Bool, 2>,
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Array<TraceAsString { inner_ty: Enum {Text(UInt<512>), FmtError}, .. }, 2>, 4>,
|
|
},
|
|
},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
StatePartIndex<SmallSlots>(6),
|
|
],
|
|
event_queue: EventQueue(EventQueueData {
|
|
instant: 7 μs,
|
|
events: {},
|
|
}),
|
|
waiting_sensitivity_sets_by_address: {},
|
|
waiting_sensitivity_sets_by_compiled_value: {},
|
|
..
|
|
} |