forked from libre-chip/fayalite
141 lines
4.4 KiB
Plaintext
141 lines
4.4 KiB
Plaintext
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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memories: StatePartAllocationLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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value: 5,
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},
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// at: module-XXXXXXXXXX.rs:3:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 2,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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5,
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5,
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],
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},
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},
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io: Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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}.o: CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<8>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "connect_const",
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children: [
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TraceModuleIO {
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name: "o",
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child: TraceUInt {
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location: TraceScalarId(0),
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name: "o",
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ty: UInt<8>,
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flow: Sink,
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},
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ty: UInt<8>,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(0),
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ty: UInt<8>,
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},
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state: 0x05,
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last_state: 0x05,
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},
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],
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trace_memories: {},
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trace_writers: [],
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instant: 0 s,
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clocks_triggered: [],
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} |