forked from libre-chip/fayalite
14 lines
214 B
Text
14 lines
214 B
Text
$timescale 1 ps $end
|
|
$scope module conditional_assignment_last $end
|
|
$var wire 1 xt~(W i $end
|
|
$var wire 1 6:7im w $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$dumpvars
|
|
0xt~(W
|
|
16:7im
|
|
$end
|
|
#1000000
|
|
1xt~(W
|
|
06:7im
|
|
#2000000
|