diff --git a/.forgejo/workflows/deps.yml b/.forgejo/workflows/deps.yml
index ffaca53..b29723c 100644
--- a/.forgejo/workflows/deps.yml
+++ b/.forgejo/workflows/deps.yml
@@ -12,10 +12,10 @@ jobs:
     outputs:
       cache-primary-key: ${{ steps.restore-deps.outputs.cache-primary-key }}
     steps:
-      - uses: https://code.forgejo.org/actions/checkout@v3
+      - uses: https://git.libre-chip.org/mirrors/checkout@v3
         with:
           fetch-depth: 0
-      - uses: https://code.forgejo.org/actions/cache/restore@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
         id: restore-deps
         with:
           path: deps
@@ -58,19 +58,19 @@ jobs:
       - name: Get SymbiYosys
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git deps/sby
+          git clone --depth=1 --branch=yosys-0.45 https://git.libre-chip.org/mirrors/sby deps/sby
       - name: Build Z3
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --recursive --branch=z3-4.13.3 https://github.com/Z3Prover/z3.git deps/z3
+          git clone --depth=1 --recursive --branch=z3-4.13.3 https://git.libre-chip.org/mirrors/z3 deps/z3
           (cd deps/z3; PYTHON=python3 ./configure --prefix=/usr/local)
           make -C deps/z3/build -j"$(nproc)"
       - name: Build Yosys
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git deps/yosys
+          git clone --depth=1 --recursive --branch=0.45 https://git.libre-chip.org/mirrors/yosys deps/yosys
           make -C deps/yosys -j"$(nproc)"
-      - uses: https://code.forgejo.org/actions/cache/save@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/save@v3
         if: steps.restore-deps.outputs.cache-hit != 'true'
         with:
           path: deps
diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 969d691..b2d03ba 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -9,7 +9,7 @@ jobs:
     runs-on: debian-12
     needs: deps
     steps:
-      - uses: https://code.forgejo.org/actions/checkout@v3
+      - uses: https://git.libre-chip.org/mirrors/checkout@v3
         with:
           fetch-depth: 0
       - run: |
@@ -38,10 +38,10 @@ jobs:
             z3 \
             zlib1g-dev
       - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
+          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.82.0
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://code.forgejo.org/actions/cache/restore@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
         with:
           path: deps
           key: ${{ needs.deps.outputs.cache-primary-key }}
@@ -52,9 +52,11 @@ jobs:
           make -C deps/yosys install
           export PATH="$(realpath deps/firtool/bin):$PATH"
           echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://github.com/Swatinem/rust-cache@v2
+      - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}
       - run: cargo test
       - run: cargo build --tests --features=unstable-doc
+      - run: cargo test --doc --features=unstable-doc
       - run: cargo doc --features=unstable-doc
+      - run: FAYALITE_TEST_HASHER=always_zero cargo test --test=module --features=unstable-doc,unstable-test-hasher
diff --git a/Cargo.lock b/Cargo.lock
index 500bd34..e0c32e9 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2,18 +2,6 @@
 # It is not intended for manual editing.
 version = 3
 
-[[package]]
-name = "ahash"
-version = "0.8.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77c3a9648d43b9cd48db467b3f87fdd6e146bcc88ab0180006cef2179fe11d01"
-dependencies = [
- "cfg-if",
- "once_cell",
- "version_check",
- "zerocopy",
-]
-
 [[package]]
 name = "allocator-api2"
 version = "0.2.16"
@@ -301,7 +289,7 @@ checksum = "25cbce373ec4653f1a01a31e8a5e5ec0c622dc27ff9c4e6606eefef5cbbed4a5"
 
 [[package]]
 name = "fayalite"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "bitvec",
  "blake3",
@@ -315,23 +303,25 @@ dependencies = [
  "num-bigint",
  "num-traits",
  "os_pipe",
+ "petgraph",
  "serde",
  "serde_json",
  "tempfile",
  "trybuild",
+ "vec_map",
  "which",
 ]
 
 [[package]]
 name = "fayalite-proc-macros"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
 
 [[package]]
 name = "fayalite-proc-macros-impl"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -345,7 +335,7 @@ dependencies = [
 
 [[package]]
 name = "fayalite-visit-gen"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "indexmap",
  "prettyplease",
@@ -357,6 +347,18 @@ dependencies = [
  "thiserror",
 ]
 
+[[package]]
+name = "fixedbitset"
+version = "0.5.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"
+
+[[package]]
+name = "foldhash"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
+
 [[package]]
 name = "funty"
 version = "2.0.0"
@@ -392,12 +394,13 @@ checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b"
 
 [[package]]
 name = "hashbrown"
-version = "0.14.3"
+version = "0.15.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "290f1a1d9242c78d09ce40a5e87e7554ee637af1351968159f4952f028f75604"
+checksum = "bf151400ff0baff5465007dd2f3e717f3fe502074ca563069ce3a6629d07b289"
 dependencies = [
- "ahash",
  "allocator-api2",
+ "equivalent",
+ "foldhash",
 ]
 
 [[package]]
@@ -423,9 +426,9 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"
 
 [[package]]
 name = "indexmap"
-version = "2.2.6"
+version = "2.9.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "168fb715dda47215e360912c096649d23d58bf392ac62f73919e831745e40f26"
+checksum = "cea70ddb795996207ad57735b50c5982d8844f38ba9ee5f1aedcfb708a2aa11e"
 dependencies = [
  "equivalent",
  "hashbrown",
@@ -472,11 +475,10 @@ checksum = "01cda141df6706de531b6c46c3a33ecca755538219bd484262fa09410c13539c"
 
 [[package]]
 name = "num-bigint"
-version = "0.4.4"
+version = "0.4.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "608e7659b5c3d7cba262d894801b9ec9d00de989e8a82bd4bef91d08da45cdc0"
+checksum = "a5e44f723f1133c9deac646763579fdb3ac745e418f2a7af9cd0c431da1f20b9"
 dependencies = [
- "autocfg",
  "num-integer",
  "num-traits",
 ]
@@ -515,6 +517,18 @@ dependencies = [
  "windows-sys 0.59.0",
 ]
 
+[[package]]
+name = "petgraph"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a98c6720655620a521dcc722d0ad66cd8afd5d86e34a89ef691c50b7b24de06"
+dependencies = [
+ "fixedbitset",
+ "hashbrown",
+ "indexmap",
+ "serde",
+]
+
 [[package]]
 name = "prettyplease"
 version = "0.2.20"
@@ -527,9 +541,9 @@ dependencies = [
 
 [[package]]
 name = "proc-macro2"
-version = "1.0.83"
+version = "1.0.92"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0b33eb56c327dec362a9e55b3ad14f9d2f0904fb5a5b03b513ab5465399e9f43"
+checksum = "37d3544b3f2748c54e147655edb5025752e2303145b5aefb3c3ea2c78b973bb0"
 dependencies = [
  "unicode-ident",
 ]
@@ -631,9 +645,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.66"
+version = "2.0.93"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
+checksum = "9c786062daee0d6db1132800e623df74274a0a87322d8e183338e01b3d98d058"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -720,6 +734,12 @@ version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821"
 
+[[package]]
+name = "vec_map"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1bddf1187be692e79c5ffeab891132dfb0f236ed36a43c7ed39f1165ee20191"
+
 [[package]]
 name = "version_check"
 version = "0.9.4"
@@ -871,23 +891,3 @@ checksum = "05f360fc0b24296329c78fda852a1e9ae82de9cf7b27dae4b7f62f118f77b9ed"
 dependencies = [
  "tap",
 ]
-
-[[package]]
-name = "zerocopy"
-version = "0.7.32"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "74d4d3961e53fa4c9a25a8637fc2bfaf2595b3d3ae34875568a5cf64787716be"
-dependencies = [
- "zerocopy-derive",
-]
-
-[[package]]
-name = "zerocopy-derive"
-version = "0.7.32"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ce1b18ccd8e73a9321186f97e46f9f04b778851177567b1975109d26a08d2a6"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
diff --git a/Cargo.toml b/Cargo.toml
index b6b8616..d681425 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -5,38 +5,40 @@ resolver = "2"
 members = ["crates/*"]
 
 [workspace.package]
-version = "0.2.1"
+version = "0.3.0"
 license = "LGPL-3.0-or-later"
 edition = "2021"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
 keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"]
 categories = ["simulation", "development-tools", "compilers"]
-rust-version = "1.80.1"
+rust-version = "1.82.0"
 
 [workspace.dependencies]
-fayalite-proc-macros = { version = "=0.2.1", path = "crates/fayalite-proc-macros" }
-fayalite-proc-macros-impl = { version = "=0.2.1", path = "crates/fayalite-proc-macros-impl" }
-fayalite-visit-gen = { version = "=0.2.1", path = "crates/fayalite-visit-gen" }
+fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" }
+fayalite-proc-macros-impl = { version = "=0.3.0", path = "crates/fayalite-proc-macros-impl" }
+fayalite-visit-gen = { version = "=0.3.0", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
 blake3 = { version = "1.5.4", features = ["serde"] }
 clap = { version = "4.5.9", features = ["derive", "env", "string"] }
 ctor = "0.2.8"
 eyre = "0.6.12"
-hashbrown = "0.14.3"
-indexmap = { version = "2.2.6", features = ["serde"] }
+hashbrown = "0.15.2"
+indexmap = { version = "2.5.0", features = ["serde"] }
 jobslot = "0.2.19"
-num-bigint = "0.4.4"
+num-bigint = "0.4.6"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
+petgraph = "0.8.1"
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"
 serde = { version = "1.0.202", features = ["derive"] }
 serde_json = { version = "1.0.117", features = ["preserve_order"] }
 sha2 = "0.10.8"
-syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"] }
+syn = { version = "2.0.93", features = ["full", "fold", "visit", "extra-traits"] }
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"
+vec_map = "0.8.2"
 which = "6.0.1"
diff --git a/crates/fayalite-proc-macros-impl/src/fold.rs b/crates/fayalite-proc-macros-impl/src/fold.rs
index 49cc8c1..22e7b82 100644
--- a/crates/fayalite-proc-macros-impl/src/fold.rs
+++ b/crates/fayalite-proc-macros-impl/src/fold.rs
@@ -220,6 +220,7 @@ forward_fold!(syn::ExprArray => fold_expr_array);
 forward_fold!(syn::ExprCall => fold_expr_call);
 forward_fold!(syn::ExprIf => fold_expr_if);
 forward_fold!(syn::ExprMatch => fold_expr_match);
+forward_fold!(syn::ExprMethodCall => fold_expr_method_call);
 forward_fold!(syn::ExprPath => fold_expr_path);
 forward_fold!(syn::ExprRepeat => fold_expr_repeat);
 forward_fold!(syn::ExprStruct => fold_expr_struct);
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 79326e2..7441cb3 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -30,7 +30,9 @@ pub(crate) struct ParsedBundle {
     pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip, kw::hdl>>>,
     pub(crate) mask_type_ident: Ident,
     pub(crate) mask_type_match_variant_ident: Ident,
+    pub(crate) mask_type_sim_value_ident: Ident,
     pub(crate) match_variant_ident: Ident,
+    pub(crate) sim_value_ident: Ident,
     pub(crate) builder_ident: Ident,
     pub(crate) mask_type_builder_ident: Ident,
 }
@@ -83,6 +85,7 @@ impl ParsedBundle {
             custom_bounds,
             no_static: _,
             no_runtime_generics: _,
+            cmp_eq: _,
         } = options.body;
         let mut fields = match fields {
             syn::Fields::Named(fields) => fields,
@@ -124,7 +127,9 @@ impl ParsedBundle {
             field_flips,
             mask_type_ident: format_ident!("__{}__MaskType", ident),
             mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident),
+            mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident),
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
+            sim_value_ident: format_ident!("__{}__SimValue", ident),
             mask_type_builder_ident: format_ident!("__{}__MaskType__Builder", ident),
             builder_ident: format_ident!("__{}__Builder", ident),
             ident,
@@ -426,7 +431,9 @@ impl ToTokens for ParsedBundle {
             field_flips,
             mask_type_ident,
             mask_type_match_variant_ident,
+            mask_type_sim_value_ident,
             match_variant_ident,
+            sim_value_ident,
             builder_ident,
             mask_type_builder_ident,
         } = self;
@@ -437,6 +444,7 @@ impl ToTokens for ParsedBundle {
             custom_bounds: _,
             no_static,
             no_runtime_generics,
+            cmp_eq,
         } = &options.body;
         let target = get_target(target, ident);
         let mut item_attrs = attrs.clone();
@@ -521,7 +529,7 @@ impl ToTokens for ParsedBundle {
             semi_token: None,
         }
         .to_tokens(tokens);
-        let mut mask_type_match_variant_fields = mask_type_fields;
+        let mut mask_type_match_variant_fields = mask_type_fields.clone();
         for Field { ty, .. } in &mut mask_type_match_variant_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
@@ -563,6 +571,58 @@ impl ToTokens for ParsedBundle {
             semi_token: None,
         }
         .to_tokens(tokens);
+        let mut mask_type_sim_value_fields = mask_type_fields;
+        for Field { ty, .. } in &mut mask_type_sim_value_fields.named {
+            *ty = parse_quote_spanned! {span=>
+                ::fayalite::sim::value::SimValue<#ty>
+            };
+        }
+        ItemStruct {
+            attrs: vec![
+                parse_quote_spanned! {span=>
+                    #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
+                        ::fayalite::__std::clone::Clone,
+                    )]
+                },
+                parse_quote_spanned! {span=>
+                    #[allow(non_camel_case_types, dead_code)]
+                },
+            ],
+            vis: vis.clone(),
+            struct_token: *struct_token,
+            ident: mask_type_sim_value_ident.clone(),
+            generics: generics.into(),
+            fields: Fields::Named(mask_type_sim_value_fields),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
+        let mut sim_value_fields = FieldsNamed::from(fields.clone());
+        for Field { ty, .. } in &mut sim_value_fields.named {
+            *ty = parse_quote_spanned! {span=>
+                ::fayalite::sim::value::SimValue<#ty>
+            };
+        }
+        ItemStruct {
+            attrs: vec![
+                parse_quote_spanned! {span=>
+                    #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
+                        ::fayalite::__std::clone::Clone,
+                    )]
+                },
+                parse_quote_spanned! {span=>
+                    #[allow(non_camel_case_types, dead_code)]
+                },
+            ],
+            vis: vis.clone(),
+            struct_token: *struct_token,
+            ident: sim_value_ident.clone(),
+            generics: generics.into(),
+            fields: Fields::Named(sim_value_fields),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
         let this_token = Ident::new("__this", span);
         let fields_token = Ident::new("__fields", span);
         let self_token = Token![self](span);
@@ -613,6 +673,31 @@ impl ToTokens for ParsedBundle {
                 }
             },
         ));
+        let sim_value_from_bits_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                #ident: v.field_from_bits(),
+            }
+        }));
+        let sim_value_clone_from_bits_fields =
+            Vec::from_iter(fields.named().into_iter().map(|field| {
+                let ident: &Ident = field.ident().as_ref().unwrap();
+                quote_spanned! {span=>
+                    v.field_clone_from_bits(&mut value.#ident);
+                }
+            }));
+        let sim_value_to_bits_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                v.field_to_bits(&value.#ident);
+            }
+        }));
+        let to_sim_value_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                #ident: ::fayalite::sim::value::SimValue::ty(&self.#ident),
+            }
+        }));
         let fields_len = fields.named().into_iter().len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -621,6 +706,7 @@ impl ToTokens for ParsedBundle {
             {
                 type BaseType = ::fayalite::bundle::Bundle;
                 type MaskType = #mask_type_ident #type_generics;
+                type SimValue = #mask_type_sim_value_ident #type_generics;
                 type MatchVariant = #mask_type_match_variant_ident #type_generics;
                 type MatchActiveScope = ();
                 type MatchVariantAndInactiveScope = ::fayalite::ty::MatchVariantWithoutScope<
@@ -658,6 +744,34 @@ impl ToTokens for ParsedBundle {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #mask_type_sim_value_ident {
+                        #(#sim_value_from_bits_fields)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #(#sim_value_clone_from_bits_fields)*
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
+                    #(#sim_value_to_bits_fields)*
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::bundle::BundleType for #mask_type_ident #type_generics
@@ -689,11 +803,57 @@ impl ToTokens for ParsedBundle {
                 }
             }
             #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValue for #mask_type_sim_value_ident #type_generics
+            #where_clause
+            {
+                type Type = #mask_type_ident #type_generics;
+
+                fn to_sim_value(
+                    &self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #mask_type_ident {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value(
+                    self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #mask_type_ident {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#mask_type_ident #type_generics>
+            for #mask_type_sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #mask_type_ident #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#mask_type_ident #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #mask_type_ident #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#mask_type_ident #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
             impl #impl_generics ::fayalite::ty::Type for #target #type_generics
             #where_clause
             {
                 type BaseType = ::fayalite::bundle::Bundle;
                 type MaskType = #mask_type_ident #type_generics;
+                type SimValue = #sim_value_ident #type_generics;
                 type MatchVariant = #match_variant_ident #type_generics;
                 type MatchActiveScope = ();
                 type MatchVariantAndInactiveScope = ::fayalite::ty::MatchVariantWithoutScope<
@@ -733,6 +893,34 @@ impl ToTokens for ParsedBundle {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #sim_value_ident {
+                        #(#sim_value_from_bits_fields)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #(#sim_value_clone_from_bits_fields)*
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
+                    #(#sim_value_to_bits_fields)*
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::bundle::BundleType for #target #type_generics
@@ -763,8 +951,144 @@ impl ToTokens for ParsedBundle {
                     ::fayalite::intern::Interned::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
                 }
             }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValue for #sim_value_ident #type_generics
+            #where_clause
+            {
+                type Type = #target #type_generics;
+
+                fn to_sim_value(
+                    &self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #target {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value(
+                    self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #target {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
+            for #sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
         }
         .to_tokens(tokens);
+        if let Some((cmp_eq,)) = cmp_eq {
+            let mut expr_where_clause =
+                Generics::from(generics)
+                    .where_clause
+                    .unwrap_or_else(|| syn::WhereClause {
+                        where_token: Token![where](span),
+                        predicates: Punctuated::new(),
+                    });
+            let mut sim_value_where_clause = expr_where_clause.clone();
+            let mut fields_sim_value_eq = vec![];
+            let mut fields_cmp_eq = vec![];
+            let mut fields_cmp_ne = vec![];
+            for field in fields.named() {
+                let field_ident = field.ident();
+                let field_ty = field.ty();
+                expr_where_clause
+                    .predicates
+                    .push(parse_quote_spanned! {cmp_eq.span=>
+                        #field_ty: ::fayalite::expr::ops::ExprPartialEq<#field_ty>
+                    });
+                sim_value_where_clause
+                    .predicates
+                    .push(parse_quote_spanned! {cmp_eq.span=>
+                        #field_ty: ::fayalite::sim::value::SimValuePartialEq<#field_ty>
+                    });
+                fields_sim_value_eq.push(quote_spanned! {span=>
+                    ::fayalite::sim::value::SimValuePartialEq::sim_value_eq(&__lhs.#field_ident, &__rhs.#field_ident)
+                });
+                fields_cmp_eq.push(quote_spanned! {span=>
+                    ::fayalite::expr::ops::ExprPartialEq::cmp_eq(__lhs.#field_ident, __rhs.#field_ident)
+                });
+                fields_cmp_ne.push(quote_spanned! {span=>
+                    ::fayalite::expr::ops::ExprPartialEq::cmp_ne(__lhs.#field_ident, __rhs.#field_ident)
+                });
+            }
+            let sim_value_eq_body;
+            let cmp_eq_body;
+            let cmp_ne_body;
+            if fields_len == 0 {
+                sim_value_eq_body = quote_spanned! {span=>
+                    true
+                };
+                cmp_eq_body = quote_spanned! {span=>
+                    ::fayalite::expr::ToExpr::to_expr(&true)
+                };
+                cmp_ne_body = quote_spanned! {span=>
+                    ::fayalite::expr::ToExpr::to_expr(&false)
+                };
+            } else {
+                sim_value_eq_body = quote_spanned! {span=>
+                    #(#fields_sim_value_eq)&&*
+                };
+                cmp_eq_body = quote_spanned! {span=>
+                    #(#fields_cmp_eq)&*
+                };
+                cmp_ne_body = quote_spanned! {span=>
+                    #(#fields_cmp_ne)|*
+                };
+            };
+            quote_spanned! {span=>
+                #[automatically_derived]
+                impl #impl_generics ::fayalite::expr::ops::ExprPartialEq<Self> for #target #type_generics
+                #expr_where_clause
+                {
+                    fn cmp_eq(
+                        __lhs: ::fayalite::expr::Expr<Self>,
+                        __rhs: ::fayalite::expr::Expr<Self>,
+                    ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
+                        #cmp_eq_body
+                    }
+                    fn cmp_ne(
+                        __lhs: ::fayalite::expr::Expr<Self>,
+                        __rhs: ::fayalite::expr::Expr<Self>,
+                    ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
+                        #cmp_ne_body
+                    }
+                }
+                #[automatically_derived]
+                impl #impl_generics ::fayalite::sim::value::SimValuePartialEq<Self> for #target #type_generics
+                #sim_value_where_clause
+                {
+                    fn sim_value_eq(
+                        __lhs: &::fayalite::sim::value::SimValue<Self>,
+                        __rhs: &::fayalite::sim::value::SimValue<Self>,
+                    ) -> bool {
+                        #sim_value_eq_body
+                    }
+                }
+            }
+            .to_tokens(tokens);
+        }
         if let (None, MaybeParsed::Parsed(generics)) = (no_static, &self.generics) {
             let static_generics = generics.clone().for_static_type();
             let (static_impl_generics, static_type_generics, static_where_clause) =
@@ -800,6 +1124,14 @@ impl ToTokens for ParsedBundle {
                 }
             }));
             quote_spanned! {span=>
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default for #mask_type_ident #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType for #mask_type_ident #static_type_generics
                 #static_where_clause
@@ -822,6 +1154,15 @@ impl ToTokens for ParsedBundle {
                     };
                 }
                 #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default
+                for #target #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
+                #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType for #target #static_type_generics
                 #static_where_clause
                 {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 1d16177..e072135 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -129,6 +129,9 @@ pub(crate) struct ParsedEnum {
     pub(crate) brace_token: Brace,
     pub(crate) variants: Punctuated<ParsedVariant, Token![,]>,
     pub(crate) match_variant_ident: Ident,
+    pub(crate) sim_value_ident: Ident,
+    pub(crate) sim_builder_ident: Ident,
+    pub(crate) sim_builder_ty_field_ident: Ident,
 }
 
 impl ParsedEnum {
@@ -155,7 +158,11 @@ impl ParsedEnum {
             custom_bounds,
             no_static: _,
             no_runtime_generics: _,
+            cmp_eq,
         } = options.body;
+        if let Some((cmp_eq,)) = cmp_eq {
+            errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums");
+        }
         attrs.retain(|attr| {
             if attr.path().is_ident("repr") {
                 errors.error(attr, "#[repr] is not supported on #[hdl] enums");
@@ -186,6 +193,9 @@ impl ParsedEnum {
             brace_token,
             variants,
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
+            sim_value_ident: format_ident!("__{}__SimValue", ident),
+            sim_builder_ident: format_ident!("__{}__SimBuilder", ident),
+            sim_builder_ty_field_ident: format_ident!("__ty", span = ident.span()),
             ident,
         })
     }
@@ -203,6 +213,9 @@ impl ToTokens for ParsedEnum {
             brace_token,
             variants,
             match_variant_ident,
+            sim_value_ident,
+            sim_builder_ident,
+            sim_builder_ty_field_ident,
         } = self;
         let span = ident.span();
         let ItemOptions {
@@ -211,6 +224,7 @@ impl ToTokens for ParsedEnum {
             custom_bounds: _,
             no_static,
             no_runtime_generics,
+            cmp_eq: _, // TODO: implement cmp_eq for enums
         } = &options.body;
         let target = get_target(target, ident);
         let mut struct_attrs = attrs.clone();
@@ -404,6 +418,133 @@ impl ToTokens for ParsedEnum {
             )),
         }
         .to_tokens(tokens);
+        let mut struct_attrs = attrs.clone();
+        struct_attrs.push(parse_quote_spanned! {span=>
+            #[allow(dead_code, non_camel_case_types)]
+        });
+        ItemStruct {
+            attrs: struct_attrs,
+            vis: vis.clone(),
+            struct_token: Token![struct](enum_token.span),
+            ident: sim_builder_ident.clone(),
+            generics: generics.into(),
+            fields: FieldsNamed {
+                brace_token: *brace_token,
+                named: Punctuated::from_iter([Field {
+                    attrs: vec![],
+                    vis: Visibility::Inherited,
+                    mutability: FieldMutability::None,
+                    ident: Some(sim_builder_ty_field_ident.clone()),
+                    colon_token: Some(Token![:](span)),
+                    ty: parse_quote_spanned! {span=>
+                        #target #type_generics
+                    },
+                }]),
+            }
+            .into(),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
+        let mut enum_attrs = attrs.clone();
+        enum_attrs.push(parse_quote_spanned! {span=>
+            #[::fayalite::__std::prelude::v1::derive(
+                ::fayalite::__std::fmt::Debug,
+                ::fayalite::__std::clone::Clone,
+            )]
+        });
+        enum_attrs.push(parse_quote_spanned! {span=>
+            #[allow(dead_code, non_camel_case_types)]
+        });
+        let sim_value_has_unknown_variant = !variants.len().is_power_of_two();
+        let sim_value_unknown_variant_name = sim_value_has_unknown_variant.then(|| {
+            let mut name = String::new();
+            let unknown = "Unknown";
+            loop {
+                let orig_len = name.len();
+                name.push_str(unknown);
+                if variants.iter().all(|v| v.ident != name) {
+                    break Ident::new(&name, span);
+                }
+                name.truncate(orig_len);
+                name.push('_');
+            }
+        });
+        let sim_value_unknown_variant =
+            sim_value_unknown_variant_name
+                .as_ref()
+                .map(|unknown_variant_name| {
+                    Pair::End(parse_quote_spanned! {span=>
+                        #unknown_variant_name(::fayalite::enum_::UnknownVariantSimValue)
+                    })
+                });
+        ItemEnum {
+            attrs: enum_attrs,
+            vis: vis.clone(),
+            enum_token: *enum_token,
+            ident: sim_value_ident.clone(),
+            generics: generics.into(),
+            brace_token: *brace_token,
+            variants: Punctuated::from_iter(
+                variants
+                    .pairs()
+                    .map_pair_value_ref(
+                        |ParsedVariant {
+                             attrs,
+                             options: _,
+                             ident,
+                             field,
+                         }| Variant {
+                            attrs: attrs.clone(),
+                            ident: ident.clone(),
+                            fields: match field {
+                                Some(ParsedVariantField {
+                                    paren_token,
+                                    attrs,
+                                    options: _,
+                                    ty,
+                                    comma_token,
+                                }) => Fields::Unnamed(FieldsUnnamed {
+                                    paren_token: *paren_token,
+                                    unnamed: Punctuated::from_iter([
+                                        Pair::new(
+                                            Field {
+                                                attrs: attrs.clone(),
+                                                vis: Visibility::Inherited,
+                                                mutability: FieldMutability::None,
+                                                ident: None,
+                                                colon_token: None,
+                                                ty: parse_quote_spanned! {span=>
+                                                    ::fayalite::sim::value::SimValue<#ty>
+                                                },
+                                            },
+                                            Some(comma_token.unwrap_or(Token![,](ident.span()))),
+                                        ),
+                                        Pair::new(
+                                            Field {
+                                                attrs: vec![],
+                                                vis: Visibility::Inherited,
+                                                mutability: FieldMutability::None,
+                                                ident: None,
+                                                colon_token: None,
+                                                ty: parse_quote_spanned! {span=>
+                                                    ::fayalite::enum_::EnumPaddingSimValue
+                                                },
+                                            },
+                                            None,
+                                        ),
+                                    ]),
+                                }),
+                                None => Fields::Unnamed(parse_quote_spanned! {span=>
+                                    (::fayalite::enum_::EnumPaddingSimValue)
+                                }),
+                            },
+                            discriminant: None,
+                        },
+                    )
+                    .chain(sim_value_unknown_variant),
+            ),
+        }
+        .to_tokens(tokens);
         let self_token = Token![self](span);
         for (index, ParsedVariant { ident, field, .. }) in variants.iter().enumerate() {
             if let Some(ParsedVariantField { ty, .. }) = field {
@@ -430,6 +571,25 @@ impl ToTokens for ParsedEnum {
                             )
                         }
                     }
+                    #[automatically_derived]
+                    impl #impl_generics #sim_builder_ident #type_generics
+                    #where_clause
+                    {
+                        #[allow(non_snake_case, dead_code)]
+                        #vis fn #ident<__V: ::fayalite::sim::value::ToSimValueWithType<#ty>>(
+                            #self_token,
+                            v: __V,
+                        ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                            let v = ::fayalite::sim::value::ToSimValueWithType::into_sim_value_with_type(
+                                v,
+                                #self_token.#sim_builder_ty_field_ident.#ident,
+                            );
+                            ::fayalite::sim::value::SimValue::from_value(
+                                #self_token.#sim_builder_ty_field_ident,
+                                #sim_value_ident::#ident(v, ::fayalite::enum_::EnumPaddingSimValue::new()),
+                            )
+                        }
+                    }
                 }
             } else {
                 quote_spanned! {span=>
@@ -448,6 +608,18 @@ impl ToTokens for ParsedEnum {
                             )
                         }
                     }
+                    #[automatically_derived]
+                    impl #impl_generics #sim_builder_ident #type_generics
+                    #where_clause
+                    {
+                        #[allow(non_snake_case, dead_code)]
+                        #vis fn #ident(#self_token) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                            ::fayalite::sim::value::SimValue::from_value(
+                                #self_token.#sim_builder_ty_field_ident,
+                                #sim_value_ident::#ident(::fayalite::enum_::EnumPaddingSimValue::new()),
+                            )
+                        }
+                    }
                 }
             }
             .to_tokens(tokens);
@@ -529,6 +701,142 @@ impl ToTokens for ParsedEnum {
                 }
             },
         ));
+        let sim_value_from_bits_unknown_match_arm = if let Some(sim_value_unknown_variant_name) =
+            &sim_value_unknown_variant_name
+        {
+            quote_spanned! {span=>
+                _ => #sim_value_ident::#sim_value_unknown_variant_name(v.unknown_variant_from_bits()),
+            }
+        } else {
+            quote_spanned! {span=>
+                _ => ::fayalite::__std::unreachable!(),
+            }
+        };
+        let sim_value_from_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #index => {
+                                    let (field, padding) = v.variant_with_field_from_bits();
+                                    #sim_value_ident::#ident(field, padding)
+                                }
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #index => #sim_value_ident::#ident(
+                                    v.variant_no_field_from_bits(),
+                                ),
+                            }
+                        }
+                    },
+                )
+                .chain([sim_value_from_bits_unknown_match_arm]),
+        );
+        let sim_value_clone_from_bits_unknown_match_arm =
+            if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name {
+                quote_spanned! {span=>
+                    _ => if let #sim_value_ident::#sim_value_unknown_variant_name(value) = value {
+                        v.unknown_variant_clone_from_bits(value);
+                    } else {
+                        *value = #sim_value_ident::#sim_value_unknown_variant_name(
+                            v.unknown_variant_from_bits(),
+                        );
+                    },
+                }
+            } else {
+                quote_spanned! {span=>
+                    _ => ::fayalite::__std::unreachable!(),
+                }
+            };
+        let sim_value_clone_from_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #index => if let #sim_value_ident::#ident(field, padding) = value {
+                                    v.variant_with_field_clone_from_bits(field, padding);
+                                } else {
+                                    let (field, padding) = v.variant_with_field_from_bits();
+                                    *value = #sim_value_ident::#ident(field, padding);
+                                },
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #index => if let #sim_value_ident::#ident(padding) = value {
+                                    v.variant_no_field_clone_from_bits(padding);
+                                } else {
+                                    *value = #sim_value_ident::#ident(
+                                        v.variant_no_field_from_bits(),
+                                    );
+                                },
+                            }
+                        }
+                    },
+                )
+                .chain([sim_value_clone_from_bits_unknown_match_arm]),
+        );
+        let sim_value_to_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #sim_value_ident::#ident(field, padding) => {
+                                    v.variant_with_field_to_bits(#index, field, padding);
+                                }
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #sim_value_ident::#ident(padding) => {
+                                    v.variant_no_field_to_bits(#index, padding);
+                                }
+                            }
+                        }
+                    },
+                )
+                .chain(sim_value_unknown_variant_name.as_ref().map(
+                    |sim_value_unknown_variant_name| {
+                        quote_spanned! {span=>
+                            #sim_value_ident::#sim_value_unknown_variant_name(value) => {
+                                v.unknown_variant_to_bits(value);
+                            }
+                        }
+                    },
+                )),
+        );
         let variants_len = variants.len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -537,6 +845,7 @@ impl ToTokens for ParsedEnum {
             {
                 type BaseType = ::fayalite::enum_::Enum;
                 type MaskType = ::fayalite::int::Bool;
+                type SimValue = #sim_value_ident #type_generics;
                 type MatchVariant = #match_variant_ident #type_generics;
                 type MatchActiveScope = ::fayalite::module::Scope;
                 type MatchVariantAndInactiveScope = ::fayalite::enum_::EnumMatchVariantAndInactiveScope<Self>;
@@ -569,11 +878,41 @@ impl ToTokens for ParsedEnum {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
+                    match v.discriminant() {
+                        #(#sim_value_from_bits_match_arms)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
+                    match v.discriminant() {
+                        #(#sim_value_clone_from_bits_match_arms)*
+                    }
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
+                ) {
+                    let v = ::fayalite::enum_::EnumSimValueToBits::new(*self, bits);
+                    match value {
+                        #(#sim_value_to_bits_match_arms)*
+                    }
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::enum_::EnumType for #target #type_generics
             #where_clause
             {
+                type SimBuilder = #sim_builder_ident #type_generics;
                 fn match_activate_scope(
                     v: <Self as ::fayalite::ty::Type>::MatchVariantAndInactiveScope,
                 ) -> (<Self as ::fayalite::ty::Type>::MatchVariant, <Self as ::fayalite::ty::Type>::MatchActiveScope) {
@@ -592,6 +931,33 @@ impl ToTokens for ParsedEnum {
                     ][..])
                 }
             }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
+            for #sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::__std::convert::From<#target #type_generics>
+            for #sim_builder_ident #type_generics
+            #where_clause
+            {
+                fn from(#sim_builder_ty_field_ident: #target #type_generics) -> Self {
+                    Self { #sim_builder_ty_field_ident }
+                }
+            }
         }
         .to_tokens(tokens);
         if let (None, MaybeParsed::Parsed(generics)) = (no_static, &self.generics) {
@@ -629,6 +995,15 @@ impl ToTokens for ParsedEnum {
                     }
                 }));
             quote_spanned! {span=>
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default
+                for #target #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType
                 for #target #static_type_generics
@@ -647,6 +1022,34 @@ impl ToTokens for ParsedEnum {
                     const MASK_TYPE_PROPERTIES: ::fayalite::ty::TypeProperties =
                         <::fayalite::int::Bool as ::fayalite::ty::StaticType>::TYPE_PROPERTIES;
                 }
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::sim::value::ToSimValue
+                for #sim_value_ident #static_type_generics
+                #static_where_clause
+                {
+                    type Type = #target #static_type_generics;
+
+                    fn to_sim_value(
+                        &self,
+                    ) -> ::fayalite::sim::value::SimValue<
+                        <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                    > {
+                        ::fayalite::sim::value::SimValue::from_value(
+                            ::fayalite::ty::StaticType::TYPE,
+                            ::fayalite::__std::clone::Clone::clone(self),
+                        )
+                    }
+                    fn into_sim_value(
+                        self,
+                    ) -> ::fayalite::sim::value::SimValue<
+                        <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                    > {
+                        ::fayalite::sim::value::SimValue::from_value(
+                            ::fayalite::ty::StaticType::TYPE,
+                            self,
+                        )
+                    }
+                }
             }
             .to_tokens(tokens);
         }
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
index e5d5f7b..97501e7 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
@@ -49,10 +49,14 @@ impl ParsedTypeAlias {
             custom_bounds,
             no_static,
             no_runtime_generics: _,
+            cmp_eq,
         } = options.body;
         if let Some((no_static,)) = no_static {
             errors.error(no_static, "no_static is not valid on type aliases");
         }
+        if let Some((cmp_eq,)) = cmp_eq {
+            errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
+        }
         let generics = if custom_bounds.is_some() {
             MaybeParsed::Unrecognized(generics)
         } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
@@ -95,6 +99,7 @@ impl ToTokens for ParsedTypeAlias {
             custom_bounds: _,
             no_static: _,
             no_runtime_generics,
+            cmp_eq: _,
         } = &options.body;
         let target = get_target(target, ident);
         let mut type_attrs = attrs.clone();
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 3f3f817..2da0915 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -26,6 +26,7 @@ crate::options! {
         CustomBounds(custom_bounds),
         NoStatic(no_static),
         NoRuntimeGenerics(no_runtime_generics),
+        CmpEq(cmp_eq),
     }
 }
 
@@ -2044,6 +2045,7 @@ pub(crate) mod known_items {
     impl_known_item!(::fayalite::int::Size);
     impl_known_item!(::fayalite::int::UInt);
     impl_known_item!(::fayalite::int::UIntType);
+    impl_known_item!(::fayalite::reset::ResetType);
     impl_known_item!(::fayalite::ty::CanonicalType);
     impl_known_item!(::fayalite::ty::StaticType);
     impl_known_item!(::fayalite::ty::Type);
@@ -2068,11 +2070,16 @@ macro_rules! impl_bounds {
             $(
                 $Variant:ident,
             )*
+            $(
+                #[unknown]
+                $Unknown:ident,
+            )?
         }
     ) => {
         #[derive(Clone, Debug)]
         $vis enum $enum_type {
             $($Variant(known_items::$Variant),)*
+            $($Unknown(syn::TypeParamBound),)?
         }
 
         $(impl From<known_items::$Variant> for $enum_type {
@@ -2085,28 +2092,54 @@ macro_rules! impl_bounds {
             fn to_tokens(&self, tokens: &mut TokenStream) {
                 match self {
                     $(Self::$Variant(v) => v.to_tokens(tokens),)*
+                    $(Self::$Unknown(v) => v.to_tokens(tokens),)?
                 }
             }
         }
 
         impl $enum_type {
             $vis fn parse_path(path: Path) -> Result<Self, Path> {
+                #![allow(unreachable_code)]
                 $(let path = match known_items::$Variant::parse_path(path) {
                     Ok(v) => return Ok(Self::$Variant(v)),
                     Err(path) => path,
                 };)*
+                $(return Ok(Self::$Unknown(syn::TraitBound {
+                    paren_token: None,
+                    modifier: syn::TraitBoundModifier::None,
+                    lifetimes: None,
+                    path,
+                }.into()));)?
                 Err(path)
             }
+            $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> Result<Self, syn::TypeParamBound> {
+                #![allow(unreachable_code)]
+                if let syn::TypeParamBound::Trait(mut trait_bound) = type_param_bound {
+                    if let syn::TraitBound {
+                        paren_token: _,
+                        modifier: syn::TraitBoundModifier::None,
+                        lifetimes: None,
+                        path: _,
+                    } = trait_bound {
+                        match Self::parse_path(trait_bound.path) {
+                            Ok(retval) => return Ok(retval),
+                            Err(path) => trait_bound.path = path,
+                        }
+                    }
+                    type_param_bound = trait_bound.into();
+                }
+                $(return Ok(Self::$Unknown(type_param_bound));)?
+                Err(type_param_bound)
+            }
         }
 
         impl Parse for $enum_type {
             fn parse(input: ParseStream) -> syn::Result<Self> {
-                Self::parse_path(Path::parse_mod_style(input)?).map_err(|path| {
-                    syn::Error::new_spanned(
-                        path,
+                Self::parse_type_param_bound(input.parse()?)
+                    .map_err(|type_param_bound| syn::Error::new_spanned(
+                        type_param_bound,
                         format_args!("expected one of: {}", [$(stringify!($Variant)),*].join(", ")),
-                    )
-                })
+                    ))
             }
         }
 
@@ -2114,6 +2147,7 @@ macro_rules! impl_bounds {
         #[allow(non_snake_case)]
         $vis struct $struct_type {
             $($vis $Variant: Option<known_items::$Variant>,)*
+            $($vis $Unknown: Vec<syn::TypeParamBound>,)?
         }
 
         impl ToTokens for $struct_type {
@@ -2125,42 +2159,63 @@ macro_rules! impl_bounds {
                     separator = Some(<Token![+]>::default());
                     v.to_tokens(tokens);
                 })*
+                $(for v in &self.$Unknown {
+                    separator.to_tokens(tokens);
+                    separator = Some(<Token![+]>::default());
+                    v.to_tokens(tokens);
+                })*
             }
         }
 
         const _: () = {
             #[derive(Clone, Debug)]
-            $vis struct Iter($vis $struct_type);
+            #[allow(non_snake_case)]
+            $vis struct Iter {
+                $($Variant: Option<known_items::$Variant>,)*
+                $($Unknown: std::vec::IntoIter<syn::TypeParamBound>,)?
+            }
 
             impl IntoIterator for $struct_type {
                 type Item = $enum_type;
                 type IntoIter = Iter;
 
                 fn into_iter(self) -> Self::IntoIter {
-                    Iter(self)
+                    Iter {
+                        $($Variant: self.$Variant,)*
+                        $($Unknown: self.$Unknown.into_iter(),)?
+                    }
                 }
             }
 
             impl Iterator for Iter {
                 type Item = $enum_type;
 
-
                 fn next(&mut self) -> Option<Self::Item> {
                     $(
-                        if let Some(value) = self.0.$Variant.take() {
+                        if let Some(value) = self.$Variant.take() {
                             return Some($enum_type::$Variant(value));
                         }
                     )*
+                    $(
+                        if let Some(value) = self.$Unknown.next() {
+                            return Some($enum_type::$Unknown(value));
+                        }
+                    )?
                     None
                 }
 
                 #[allow(unused_mut, unused_variables)]
                 fn fold<B, F: FnMut(B, Self::Item) -> B>(mut self, mut init: B, mut f: F) -> B {
                     $(
-                        if let Some(value) = self.0.$Variant.take() {
+                        if let Some(value) = self.$Variant.take() {
                             init = f(init, $enum_type::$Variant(value));
                         }
                     )*
+                    $(
+                        if let Some(value) = self.$Unknown.next() {
+                            init = f(init, $enum_type::$Unknown(value));
+                        }
+                    )?
                     init
                 }
             }
@@ -2172,6 +2227,9 @@ macro_rules! impl_bounds {
                     $($enum_type::$Variant(v) => {
                         self.$Variant = Some(v);
                     })*
+                    $($enum_type::$Unknown(v) => {
+                        self.$Unknown.push(v);
+                    })?
                 });
             }
         }
@@ -2190,6 +2248,7 @@ macro_rules! impl_bounds {
                     $(if let Some(v) = v.$Variant {
                         self.$Variant = Some(v);
                     })*
+                    $(self.$Unknown.extend(v.$Unknown);)*
                 });
             }
         }
@@ -2239,9 +2298,12 @@ impl_bounds! {
         EnumType,
         IntType,
         KnownSize,
+        ResetType,
         Size,
         StaticType,
         Type,
+        #[unknown]
+        Unknown,
     }
 }
 
@@ -2252,8 +2314,11 @@ impl_bounds! {
         BundleType,
         EnumType,
         IntType,
+        ResetType,
         StaticType,
         Type,
+        #[unknown]
+        Unknown,
     }
 }
 
@@ -2264,8 +2329,10 @@ impl From<ParsedTypeBound> for ParsedBound {
             ParsedTypeBound::BundleType(v) => ParsedBound::BundleType(v),
             ParsedTypeBound::EnumType(v) => ParsedBound::EnumType(v),
             ParsedTypeBound::IntType(v) => ParsedBound::IntType(v),
+            ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v),
             ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v),
             ParsedTypeBound::Type(v) => ParsedBound::Type(v),
+            ParsedTypeBound::Unknown(v) => ParsedBound::Unknown(v),
         }
     }
 }
@@ -2277,8 +2344,10 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             BundleType,
             EnumType,
             IntType,
+            ResetType,
             StaticType,
             Type,
+            Unknown,
         } = value;
         Self {
             BoolOrIntType,
@@ -2286,9 +2355,11 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             EnumType,
             IntType,
             KnownSize: None,
+            ResetType,
             Size: None,
             StaticType,
             Type,
+            Unknown,
         }
     }
 }
@@ -2314,11 +2385,17 @@ impl ParsedTypeBound {
                 ParsedTypeBound::BoolOrIntType(known_items::BoolOrIntType(span)),
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
+            Self::ResetType(v) => ParsedTypeBounds::from_iter([
+                ParsedTypeBound::from(v),
+                ParsedTypeBound::StaticType(known_items::StaticType(span)),
+                ParsedTypeBound::Type(known_items::Type(span)),
+            ]),
             Self::StaticType(v) => ParsedTypeBounds::from_iter([
                 ParsedTypeBound::from(v),
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
             Self::Type(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::from(v)]),
+            Self::Unknown(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::Unknown(v)]),
         }
     }
 }
@@ -2349,9 +2426,11 @@ impl From<ParsedSizeTypeBounds> for ParsedBounds {
             EnumType: None,
             IntType: None,
             KnownSize,
+            ResetType: None,
             Size,
             StaticType: None,
             Type: None,
+            Unknown: vec![],
         }
     }
 }
@@ -2379,6 +2458,7 @@ impl ParsedBounds {
     fn categorize(self, errors: &mut Errors, span: Span) -> ParsedBoundsCategory {
         let mut type_bounds = None;
         let mut size_type_bounds = None;
+        let mut unknown_bounds = vec![];
         self.into_iter().for_each(|bound| match bound.categorize() {
             ParsedBoundCategory::Type(bound) => {
                 type_bounds
@@ -2390,15 +2470,37 @@ impl ParsedBounds {
                     .get_or_insert_with(ParsedSizeTypeBounds::default)
                     .extend([bound]);
             }
+            ParsedBoundCategory::Unknown(bound) => unknown_bounds.push(bound),
         });
-        match (type_bounds, size_type_bounds) {
-            (None, None) => ParsedBoundsCategory::Type(ParsedTypeBounds {
+        match (type_bounds, size_type_bounds, unknown_bounds.is_empty()) {
+            (None, None, true) => ParsedBoundsCategory::Type(ParsedTypeBounds {
                 Type: Some(known_items::Type(span)),
                 ..Default::default()
             }),
-            (None, Some(bounds)) => ParsedBoundsCategory::SizeType(bounds),
-            (Some(bounds), None) => ParsedBoundsCategory::Type(bounds),
-            (Some(type_bounds), Some(size_type_bounds)) => {
+            (None, None, false) => {
+                errors.error(
+                    unknown_bounds.remove(0),
+                    "unknown bounds: must use at least one known bound (such as `Type`) with any unknown bounds",
+                );
+                ParsedBoundsCategory::Type(ParsedTypeBounds {
+                    Unknown: unknown_bounds,
+                    ..Default::default()
+                })
+            }
+            (None, Some(bounds), true) => ParsedBoundsCategory::SizeType(bounds),
+            (None, Some(bounds), false) => {
+                // TODO: implement
+                errors.error(
+                    unknown_bounds.remove(0),
+                    "unknown bounds with `Size` bounds are not implemented",
+                );
+                ParsedBoundsCategory::SizeType(bounds)
+            }
+            (Some(bounds), None, _) => ParsedBoundsCategory::Type(ParsedTypeBounds {
+                Unknown: unknown_bounds,
+                ..bounds
+            }),
+            (Some(type_bounds), Some(size_type_bounds), _) => {
                 errors.error(
                     size_type_bounds
                         .Size
@@ -2415,6 +2517,7 @@ impl ParsedBounds {
 pub(crate) enum ParsedBoundCategory {
     Type(ParsedTypeBound),
     SizeType(ParsedSizeTypeBound),
+    Unknown(syn::TypeParamBound),
 }
 
 impl ParsedBound {
@@ -2425,15 +2528,18 @@ impl ParsedBound {
             Self::EnumType(v) => ParsedBoundCategory::Type(ParsedTypeBound::EnumType(v)),
             Self::IntType(v) => ParsedBoundCategory::Type(ParsedTypeBound::IntType(v)),
             Self::KnownSize(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::KnownSize(v)),
+            Self::ResetType(v) => ParsedBoundCategory::Type(ParsedTypeBound::ResetType(v)),
             Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)),
             Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)),
             Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)),
+            Self::Unknown(v) => ParsedBoundCategory::Unknown(v),
         }
     }
     fn implied_bounds(self) -> ParsedBounds {
         match self.categorize() {
             ParsedBoundCategory::Type(v) => v.implied_bounds().into(),
             ParsedBoundCategory::SizeType(v) => v.implied_bounds().into(),
+            ParsedBoundCategory::Unknown(v) => ParsedBounds::from_iter([ParsedBound::Unknown(v)]),
         }
     }
 }
@@ -3310,8 +3416,9 @@ impl ParsedGenerics {
                                 ParsedTypeBound::BoolOrIntType(_)
                                 | ParsedTypeBound::BundleType(_)
                                 | ParsedTypeBound::EnumType(_)
-                                | ParsedTypeBound::IntType(_) => {
-                                    errors.error(bound, "bound on mask type not implemented");
+                                | ParsedTypeBound::IntType(_)
+                                | ParsedTypeBound::ResetType(_) => {
+                                    errors.error(bound, "bounds on mask types are not implemented");
                                 }
                                 ParsedTypeBound::StaticType(bound) => {
                                     if bounds.StaticType.is_none() {
@@ -3323,6 +3430,12 @@ impl ParsedGenerics {
                                     }
                                 }
                                 ParsedTypeBound::Type(_) => {}
+                                ParsedTypeBound::Unknown(_) => {
+                                    errors.error(
+                                        bound,
+                                        "unknown bounds on mask types are not implemented",
+                                    );
+                                }
                             }
                         }
                         bounds.add_implied_bounds();
diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 0ffd4d4..4f7c4f0 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -3,14 +3,20 @@
 #![cfg_attr(test, recursion_limit = "512")]
 use proc_macro2::{Span, TokenStream};
 use quote::{quote, ToTokens};
-use std::io::{ErrorKind, Write};
+use std::{
+    collections::{hash_map::Entry, HashMap},
+    io::{ErrorKind, Write},
+};
 use syn::{
-    bracketed, parenthesized,
+    bracketed,
+    ext::IdentExt,
+    parenthesized,
     parse::{Parse, ParseStream, Parser},
     parse_quote,
-    punctuated::Pair,
+    punctuated::{Pair, Punctuated},
     spanned::Spanned,
-    AttrStyle, Attribute, Error, Item, ItemFn, Token,
+    token::{Bracket, Paren},
+    AttrStyle, Attribute, Error, Ident, Item, ItemFn, LitBool, LitStr, Meta, Token,
 };
 
 mod fold;
@@ -19,6 +25,7 @@ mod hdl_enum;
 mod hdl_type_alias;
 mod hdl_type_common;
 mod module;
+mod process_cfg;
 
 pub(crate) trait CustomToken:
     Copy
@@ -59,14 +66,20 @@ mod kw {
         };
     }
 
+    custom_keyword!(__evaluated_cfgs);
+    custom_keyword!(all);
+    custom_keyword!(any);
+    custom_keyword!(cfg);
+    custom_keyword!(cfg_attr);
     custom_keyword!(clock_domain);
+    custom_keyword!(cmp_eq);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
     custom_keyword!(flip);
     custom_keyword!(hdl);
     custom_keyword!(hdl_module);
-    custom_keyword!(input);
     custom_keyword!(incomplete_wire);
+    custom_keyword!(input);
     custom_keyword!(instance);
     custom_keyword!(m);
     custom_keyword!(memory);
@@ -75,10 +88,12 @@ mod kw {
     custom_keyword!(no_reset);
     custom_keyword!(no_runtime_generics);
     custom_keyword!(no_static);
+    custom_keyword!(not);
     custom_keyword!(outline_generated);
     custom_keyword!(output);
     custom_keyword!(reg_builder);
     custom_keyword!(reset);
+    custom_keyword!(sim);
     custom_keyword!(skip);
     custom_keyword!(target);
     custom_keyword!(wire);
@@ -901,15 +916,346 @@ fn hdl_module_impl(item: ItemFn) -> syn::Result<TokenStream> {
     Ok(contents)
 }
 
-pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl_module::default();
-    hdl_module_impl(syn::parse2(quote! { #[#kw(#attr)] #item })?)
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) enum CfgExpr {
+    Option {
+        ident: Ident,
+        value: Option<(Token![=], LitStr)>,
+    },
+    All {
+        all: kw::all,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Any {
+        any: kw::any,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Not {
+        not: kw::not,
+        paren: Paren,
+        expr: Box<CfgExpr>,
+        trailing_comma: Option<Token![,]>,
+    },
 }
 
-pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl::default();
-    let item = quote! { #[#kw(#attr)] #item };
-    let item = syn::parse2::<Item>(item)?;
+impl Parse for CfgExpr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        match input.cursor().ident() {
+            Some((_, cursor)) if cursor.eof() => {
+                return Ok(CfgExpr::Option {
+                    ident: input.call(Ident::parse_any)?,
+                    value: None,
+                });
+            }
+            _ => {}
+        }
+        if input.peek(Ident::peek_any) && input.peek2(Token![=]) {
+            return Ok(CfgExpr::Option {
+                ident: input.call(Ident::parse_any)?,
+                value: Some((input.parse()?, input.parse()?)),
+            });
+        }
+        let contents;
+        if input.peek(kw::all) {
+            Ok(CfgExpr::All {
+                all: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::any) {
+            Ok(CfgExpr::Any {
+                any: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::not) {
+            Ok(CfgExpr::Not {
+                not: input.parse()?,
+                paren: parenthesized!(contents in input),
+                expr: contents.parse()?,
+                trailing_comma: contents.parse()?,
+            })
+        } else {
+            Err(input.error("expected cfg-pattern"))
+        }
+    }
+}
+
+impl ToTokens for CfgExpr {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        match self {
+            CfgExpr::Option { ident, value } => {
+                ident.to_tokens(tokens);
+                if let Some((eq, value)) = value {
+                    eq.to_tokens(tokens);
+                    value.to_tokens(tokens);
+                }
+            }
+            CfgExpr::All { all, paren, exprs } => {
+                all.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Any { any, paren, exprs } => {
+                any.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Not {
+                not,
+                paren,
+                expr,
+                trailing_comma,
+            } => {
+                not.to_tokens(tokens);
+                paren.surround(tokens, |tokens| {
+                    expr.to_tokens(tokens);
+                    trailing_comma.to_tokens(tokens);
+                });
+            }
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct Cfg {
+    cfg: kw::cfg,
+    paren: Paren,
+    expr: CfgExpr,
+    trailing_comma: Option<Token![,]>,
+}
+
+impl Cfg {
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl ToTokens for Cfg {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            cfg,
+            paren,
+            expr,
+            trailing_comma,
+        } = self;
+        cfg.to_tokens(tokens);
+        paren.surround(tokens, |tokens| {
+            expr.to_tokens(tokens);
+            trailing_comma.to_tokens(tokens);
+        });
+    }
+}
+
+impl Parse for Cfg {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            trailing_comma: contents.parse()?,
+        })
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct CfgAttr {
+    cfg_attr: kw::cfg_attr,
+    paren: Paren,
+    expr: CfgExpr,
+    comma: Token![,],
+    attrs: Punctuated<Meta, Token![,]>,
+}
+
+impl CfgAttr {
+    pub(crate) fn to_cfg(&self) -> Cfg {
+        Cfg {
+            cfg: kw::cfg(self.cfg_attr.span),
+            paren: self.paren,
+            expr: self.expr.clone(),
+            trailing_comma: None,
+        }
+    }
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl Parse for CfgAttr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg_attr: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            comma: contents.parse()?,
+            attrs: contents.call(Punctuated::parse_terminated)?,
+        })
+    }
+}
+
+pub(crate) struct CfgAndValue {
+    cfg: Cfg,
+    eq_token: Token![=],
+    value: LitBool,
+}
+
+impl Parse for CfgAndValue {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        Ok(Self {
+            cfg: input.parse()?,
+            eq_token: input.parse()?,
+            value: input.parse()?,
+        })
+    }
+}
+
+pub(crate) struct Cfgs<T> {
+    pub(crate) bracket: Bracket,
+    pub(crate) cfgs_map: HashMap<Cfg, T>,
+    pub(crate) cfgs_list: Vec<Cfg>,
+}
+
+impl<T> Default for Cfgs<T> {
+    fn default() -> Self {
+        Self {
+            bracket: Default::default(),
+            cfgs_map: Default::default(),
+            cfgs_list: Default::default(),
+        }
+    }
+}
+
+impl<T> Cfgs<T> {
+    fn insert_cfg(&mut self, cfg: Cfg, value: T) {
+        match self.cfgs_map.entry(cfg) {
+            Entry::Occupied(_) => {}
+            Entry::Vacant(entry) => {
+                self.cfgs_list.push(entry.key().clone());
+                entry.insert(value);
+            }
+        }
+    }
+}
+
+impl Parse for Cfgs<bool> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for CfgAndValue {
+            cfg,
+            eq_token,
+            value,
+        } in contents.call(Punctuated::<CfgAndValue, Token![,]>::parse_terminated)?
+        {
+            let _ = eq_token;
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(value.value);
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl Parse for Cfgs<()> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for cfg in contents.call(Punctuated::<Cfg, Token![,]>::parse_terminated)? {
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(());
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl ToTokens for Cfgs<()> {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            bracket,
+            cfgs_map: _,
+            cfgs_list,
+        } = self;
+        bracket.surround(tokens, |tokens| {
+            for cfg in cfgs_list {
+                cfg.to_tokens(tokens);
+                <Token![,]>::default().to_tokens(tokens);
+            }
+        });
+    }
+}
+
+fn hdl_main(
+    kw: impl CustomToken,
+    attr: TokenStream,
+    item: TokenStream,
+) -> syn::Result<TokenStream> {
+    fn parse_evaluated_cfgs_attr<R>(
+        input: ParseStream,
+        parse_inner: impl FnOnce(ParseStream) -> syn::Result<R>,
+    ) -> syn::Result<R> {
+        let _: Token![#] = input.parse()?;
+        let bracket_content;
+        bracketed!(bracket_content in input);
+        let _: kw::__evaluated_cfgs = bracket_content.parse()?;
+        let paren_content;
+        parenthesized!(paren_content in bracket_content);
+        parse_inner(&paren_content)
+    }
+    let (evaluated_cfgs, item): (_, TokenStream) = Parser::parse2(
+        |input: ParseStream| {
+            let peek = input.fork();
+            if parse_evaluated_cfgs_attr(&peek, |_| Ok(())).is_ok() {
+                let evaluated_cfgs = parse_evaluated_cfgs_attr(input, Cfgs::<bool>::parse)?;
+                Ok((Some(evaluated_cfgs), input.parse()?))
+            } else {
+                Ok((None, input.parse()?))
+            }
+        },
+        item,
+    )?;
+    let cfgs = if let Some(cfgs) = evaluated_cfgs {
+        cfgs
+    } else {
+        let cfgs = process_cfg::collect_cfgs(syn::parse2(item.clone())?)?;
+        if cfgs.cfgs_list.is_empty() {
+            Cfgs::default()
+        } else {
+            return Ok(quote! {
+                ::fayalite::__cfg_expansion_helper! {
+                    []
+                    #cfgs
+                    {#[::fayalite::#kw(#attr)]} { #item }
+                }
+            });
+        }
+    };
+    let item = syn::parse2(quote! { #[#kw(#attr)] #item })?;
+    let Some(item) = process_cfg::process_cfgs(item, cfgs)? else {
+        return Ok(TokenStream::new());
+    };
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
@@ -921,3 +1267,11 @@ pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream
         )),
     }
 }
+
+pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl_module::default(), attr, item)
+}
+
+pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl::default(), attr, item)
+}
diff --git a/crates/fayalite-proc-macros-impl/src/module.rs b/crates/fayalite-proc-macros-impl/src/module.rs
index 0852f58..62b7837 100644
--- a/crates/fayalite-proc-macros-impl/src/module.rs
+++ b/crates/fayalite-proc-macros-impl/src/module.rs
@@ -377,7 +377,7 @@ impl ModuleFn {
             module_kind,
             vis,
             sig,
-            block,
+            mut block,
             struct_generics,
             the_struct,
         } = match self.0 {
@@ -439,6 +439,12 @@ impl ModuleFn {
         body_sig
             .inputs
             .insert(0, parse_quote! { m: &::fayalite::module::ModuleBuilder });
+        block.stmts.insert(
+            0,
+            parse_quote! {
+                let _ = m;
+            },
+        );
         let body_fn = ItemFn {
             attrs: vec![],
             vis: Visibility::Inherited,
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index 6e99e87..a0f8eb0 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -16,7 +16,7 @@ use std::{borrow::Borrow, convert::Infallible};
 use syn::{
     fold::{fold_expr, fold_expr_lit, fold_expr_unary, fold_local, fold_stmt, Fold},
     parenthesized,
-    parse::{Nothing, Parse, ParseStream},
+    parse::{Parse, ParseStream},
     parse_quote, parse_quote_spanned,
     spanned::Spanned,
     token::Paren,
@@ -27,6 +27,13 @@ use syn::{
 mod expand_aggregate_literals;
 mod expand_match;
 
+options! {
+    #[options = ExprOptions]
+    pub(crate) enum ExprOption {
+        Sim(sim),
+    }
+}
+
 options! {
     pub(crate) enum LetFnKind {
         Input(input),
@@ -952,7 +959,7 @@ with_debug_clone_and_fold! {
     #[allow(dead_code)]
     pub(crate) struct HdlLet<Kind = HdlLetKind> {
         pub(crate) attrs: Vec<Attribute>,
-        pub(crate) hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        pub(crate) hdl_attr: HdlAttr<syn::parse::Nothing, kw::hdl>,
         pub(crate) let_token: Token![let],
         pub(crate) mut_token: Option<Token![mut]>,
         pub(crate) name: Ident,
@@ -1109,7 +1116,7 @@ fn parse_quote_let_pat<T, R: ToTokens, C: Borrow<Token![:]>>(
     }
 }
 
-fn wrap_ty_with_expr(ty: impl ToTokens) -> Type {
+pub(crate) fn wrap_ty_with_expr(ty: impl ToTokens) -> Type {
     parse_quote_spanned! {ty.span()=>
         ::fayalite::expr::Expr<#ty>
     }
@@ -1173,7 +1180,7 @@ impl Visitor<'_> {
             Some(_) => {}
         }
     }
-    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<Nothing, kw::hdl>, expr_if: ExprIf) -> Expr {
+    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<ExprOptions, kw::hdl>, expr_if: ExprIf) -> Expr {
         let ExprIf {
             attrs,
             if_token,
@@ -1181,10 +1188,10 @@ impl Visitor<'_> {
             then_branch,
             else_branch,
         } = expr_if;
-        self.require_normal_module_or_fn(if_token);
-        let else_expr = else_branch.unzip().1.map(|else_expr| match *else_expr {
-            Expr::If(expr_if) => self.process_hdl_if(hdl_attr.clone(), expr_if),
-            expr => expr,
+        let (else_token, else_expr) = else_branch.unzip();
+        let else_expr = else_expr.map(|else_expr| match *else_expr {
+            Expr::If(expr_if) => Box::new(self.process_hdl_if(hdl_attr.clone(), expr_if)),
+            _ => else_expr,
         });
         if let Expr::Let(ExprLet {
             attrs: let_attrs,
@@ -1206,7 +1213,19 @@ impl Visitor<'_> {
                 },
             );
         }
-        if let Some(else_expr) = else_expr {
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            ExprIf {
+                attrs,
+                if_token,
+                cond: parse_quote_spanned! {if_token.span=>
+                    *::fayalite::sim::value::SimValue::<::fayalite::int::Bool>::value(&::fayalite::sim::value::ToSimValue::into_sim_value(#cond))
+                },
+                then_branch,
+                else_branch: else_token.zip(else_expr),
+            }
+            .into()
+        } else if let Some(else_expr) = else_expr {
             parse_quote_spanned! {if_token.span=>
                 #(#attrs)*
                 {
@@ -1586,7 +1605,7 @@ impl Visitor<'_> {
     }
 }
 
-fn empty_let() -> Local {
+pub(crate) fn empty_let() -> Local {
     Local {
         attrs: vec![],
         let_token: Default::default(),
@@ -1668,20 +1687,42 @@ impl Fold for Visitor<'_> {
                 Repeat => process_hdl_repeat,
                 Struct => process_hdl_struct,
                 Tuple => process_hdl_tuple,
+                MethodCall => process_hdl_method_call,
+                Call => process_hdl_call,
             }
         }
     }
 
-    fn fold_local(&mut self, let_stmt: Local) -> Local {
+    fn fold_local(&mut self, mut let_stmt: Local) -> Local {
         match self
             .errors
-            .ok(HdlAttr::<Nothing, kw::hdl>::parse_and_leave_attr(
+            .ok(HdlAttr::<ExprOptions, kw::hdl>::parse_and_leave_attr(
                 &let_stmt.attrs,
             )) {
             None => return empty_let(),
             Some(None) => return fold_local(self, let_stmt),
             Some(Some(HdlAttr { .. })) => {}
         };
+        let mut pat = &let_stmt.pat;
+        if let Pat::Type(pat_type) = pat {
+            pat = &pat_type.pat;
+        }
+        let Pat::Ident(syn::PatIdent {
+            attrs: _,
+            by_ref: None,
+            mutability: _,
+            ident: _,
+            subpat: None,
+        }) = pat
+        else {
+            let hdl_attr =
+                HdlAttr::<ExprOptions, kw::hdl>::parse_and_take_attr(&mut let_stmt.attrs)
+                    .ok()
+                    .flatten()
+                    .expect("already checked above");
+            let let_stmt = fold_local(self, let_stmt);
+            return self.process_hdl_let_pat(hdl_attr, let_stmt);
+        };
         let hdl_let = syn::parse2::<HdlLet<HdlLetKind<Type>>>(let_stmt.into_token_stream());
         let Some(hdl_let) = self.errors.ok(hdl_let) else {
             return empty_let();
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
index b5a0ad3..61f6c75 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
@@ -1,45 +1,103 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use crate::{kw, module::transform_body::Visitor, HdlAttr};
+
+use crate::{
+    kw,
+    module::transform_body::{
+        expand_match::{parse_enum_path, EnumPath},
+        ExprOptions, Visitor,
+    },
+    HdlAttr,
+};
 use quote::{format_ident, quote_spanned};
+use std::mem;
 use syn::{
-    parse::Nothing, parse_quote, parse_quote_spanned, spanned::Spanned, Expr, ExprArray, ExprPath,
-    ExprRepeat, ExprStruct, ExprTuple, FieldValue, TypePath,
+    parse_quote_spanned, punctuated::Punctuated, spanned::Spanned, token::Paren, Expr, ExprArray,
+    ExprCall, ExprGroup, ExprMethodCall, ExprParen, ExprPath, ExprRepeat, ExprStruct, ExprTuple,
+    FieldValue, Token, TypePath,
 };
 
 impl Visitor<'_> {
     pub(crate) fn process_hdl_array(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         mut expr_array: ExprArray,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
-        for elem in &mut expr_array.elems {
-            *elem = parse_quote_spanned! {elem.span()=>
-                ::fayalite::expr::ToExpr::to_expr(&(#elem))
-            };
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        if sim.is_some() {
+            for elem in &mut expr_array.elems {
+                *elem = parse_quote_spanned! {elem.span()=>
+                    ::fayalite::sim::value::ToSimValue::to_sim_value(&(#elem))
+                };
+            }
+            parse_quote_spanned! {span=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_array)
+            }
+        } else {
+            for elem in &mut expr_array.elems {
+                *elem = parse_quote_spanned! {elem.span()=>
+                    ::fayalite::expr::ToExpr::to_expr(&(#elem))
+                };
+            }
+            parse_quote_spanned! {span=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_array)
+            }
         }
-        parse_quote! {::fayalite::expr::ToExpr::to_expr(&#expr_array)}
     }
     pub(crate) fn process_hdl_repeat(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         mut expr_repeat: ExprRepeat,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
         let repeated_value = &expr_repeat.expr;
-        *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
-            ::fayalite::expr::ToExpr::to_expr(&(#repeated_value))
-        };
-        parse_quote! {::fayalite::expr::ToExpr::to_expr(&#expr_repeat)}
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        if sim.is_some() {
+            *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
+                ::fayalite::sim::value::ToSimValue::to_sim_value(&(#repeated_value))
+            };
+            parse_quote_spanned! {span=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_repeat)
+            }
+        } else {
+            *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
+                ::fayalite::expr::ToExpr::to_expr(&(#repeated_value))
+            };
+            parse_quote_spanned! {span=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_repeat)
+            }
+        }
     }
     pub(crate) fn process_hdl_struct(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
-        expr_struct: ExprStruct,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_struct: ExprStruct,
     ) -> Expr {
-        self.require_normal_module_or_fn(&hdl_attr);
         let name_span = expr_struct.path.segments.last().unwrap().ident.span();
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            let ty_path = TypePath {
+                qself: expr_struct.qself.take(),
+                path: expr_struct.path,
+            };
+            expr_struct.path = parse_quote_spanned! {name_span=>
+                __SimValue::<#ty_path>
+            };
+            for field in &mut expr_struct.fields {
+                let expr = &field.expr;
+                field.expr = parse_quote_spanned! {field.member.span()=>
+                    ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr))
+                };
+            }
+            return parse_quote_spanned! {name_span=>
+                {
+                    type __SimValue<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let value: ::fayalite::sim::value::SimValue<#ty_path> = ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_struct);
+                    value
+                }
+            };
+        }
         let builder_ident = format_ident!("__builder", span = name_span);
         let empty_builder = if expr_struct.qself.is_some()
             || expr_struct
@@ -91,12 +149,126 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_tuple(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
-        expr_tuple: ExprTuple,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_tuple: ExprTuple,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
-        parse_quote_spanned! {expr_tuple.span()=>
-            ::fayalite::expr::ToExpr::to_expr(&#expr_tuple)
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            for element in &mut expr_tuple.elems {
+                *element = parse_quote_spanned! {element.span()=>
+                    &(#element)
+                };
+            }
+            parse_quote_spanned! {expr_tuple.span()=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_tuple)
+            }
+        } else {
+            parse_quote_spanned! {expr_tuple.span()=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_tuple)
+            }
         }
     }
+    pub(crate) fn process_hdl_call(
+        &mut self,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_call: ExprCall,
+    ) -> Expr {
+        let span = hdl_attr.kw.span;
+        let mut func = &mut *expr_call.func;
+        let EnumPath {
+            variant_path: _,
+            enum_path,
+            variant_name,
+        } = loop {
+            match func {
+                Expr::Group(ExprGroup { expr, .. }) | Expr::Paren(ExprParen { expr, .. }) => {
+                    func = &mut **expr;
+                }
+                Expr::Path(_) => {
+                    let Expr::Path(ExprPath { attrs, qself, path }) =
+                        mem::replace(func, Expr::PLACEHOLDER)
+                    else {
+                        unreachable!();
+                    };
+                    match parse_enum_path(TypePath { qself, path }) {
+                        Ok(path) => break path,
+                        Err(path) => {
+                            self.errors.error(&path, "unsupported enum variant path");
+                            let TypePath { qself, path } = path;
+                            *func = ExprPath { attrs, qself, path }.into();
+                            return expr_call.into();
+                        }
+                    }
+                }
+                _ => {
+                    self.errors.error(
+                        &expr_call.func,
+                        "#[hdl] function call -- function must be a possibly-parenthesized path",
+                    );
+                    return expr_call.into();
+                }
+            }
+        };
+        self.process_hdl_method_call(
+            hdl_attr,
+            ExprMethodCall {
+                attrs: expr_call.attrs,
+                receiver: parse_quote_spanned! {span=>
+                    <#enum_path as ::fayalite::ty::StaticType>::TYPE
+                },
+                dot_token: Token![.](span),
+                method: variant_name,
+                turbofish: None,
+                paren_token: expr_call.paren_token,
+                args: expr_call.args,
+            },
+        )
+    }
+    pub(crate) fn process_hdl_method_call(
+        &mut self,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_method_call: ExprMethodCall,
+    ) -> Expr {
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        // remove any number of groups and up to one paren
+        let mut receiver = &mut *expr_method_call.receiver;
+        let mut has_group = false;
+        let receiver = loop {
+            match receiver {
+                Expr::Group(ExprGroup { expr, .. }) => {
+                    has_group = true;
+                    receiver = expr;
+                }
+                Expr::Paren(ExprParen { expr, .. }) => break &mut **expr,
+                receiver @ Expr::Path(_) => break receiver,
+                _ => {
+                    if !has_group {
+                        self.errors.error(
+                            &expr_method_call.receiver,
+                            "#[hdl] on a method call needs parenthesized receiver",
+                        );
+                    }
+                    break &mut *expr_method_call.receiver;
+                }
+            }
+        };
+        let func = if sim.is_some() {
+            parse_quote_spanned! {span=>
+                ::fayalite::enum_::enum_type_to_sim_builder
+            }
+        } else {
+            parse_quote_spanned! {span=>
+                ::fayalite::enum_::assert_is_enum_type
+            }
+        };
+        *expr_method_call.receiver = ExprCall {
+            attrs: vec![],
+            func,
+            paren_token: Paren(span),
+            args: Punctuated::from_iter([mem::replace(receiver, Expr::PLACEHOLDER)]),
+        }
+        .into();
+        expr_method_call.into()
+    }
 }
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index 1d53104..68218c1 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -3,22 +3,119 @@
 use crate::{
     fold::{impl_fold, DoFold},
     kw,
-    module::transform_body::{with_debug_clone_and_fold, Visitor},
+    module::transform_body::{
+        empty_let, with_debug_clone_and_fold, wrap_ty_with_expr, ExprOptions, Visitor,
+    },
     Errors, HdlAttr, PairsIterExt,
 };
 use proc_macro2::{Span, TokenStream};
 use quote::{format_ident, quote_spanned, ToTokens, TokenStreamExt};
+use std::collections::BTreeSet;
 use syn::{
-    fold::{fold_arm, fold_expr_match, fold_pat, Fold},
-    parse::Nothing,
+    fold::{fold_arm, fold_expr_match, fold_local, fold_pat, Fold},
     parse_quote_spanned,
     punctuated::Punctuated,
     spanned::Spanned,
     token::{Brace, Paren},
-    Arm, Attribute, Expr, ExprMatch, FieldPat, Ident, Member, Pat, PatIdent, PatOr, PatParen,
-    PatPath, PatRest, PatStruct, PatTupleStruct, PatWild, Path, PathSegment, Token, TypePath,
+    Arm, Attribute, Expr, ExprMatch, FieldPat, Ident, Local, Member, Pat, PatIdent, PatOr,
+    PatParen, PatPath, PatRest, PatStruct, PatTuple, PatTupleStruct, PatWild, Path, PathSegment,
+    Token, TypePath,
 };
 
+macro_rules! visit_trait {
+    (
+        $($vis:vis fn $fn:ident($state:ident: _, $value:ident: &$Value:ty) $block:block)*
+    ) => {
+        trait VisitMatchPat<'a> {
+            $(fn $fn(&mut self, $value: &'a $Value) {
+                $fn(self, $value);
+            })*
+        }
+
+        $($vis fn $fn<'a>($state: &mut (impl ?Sized + VisitMatchPat<'a>), $value: &'a $Value) $block)*
+    };
+}
+
+visit_trait! {
+    fn visit_match_pat_binding(_state: _, v: &MatchPatBinding) {
+        let MatchPatBinding { ident: _ } = v;
+    }
+    fn visit_match_pat_wild(_state: _, v: &MatchPatWild) {
+        let MatchPatWild { underscore_token: _ } = v;
+    }
+    fn visit_match_pat_rest(_state: _, v: &MatchPatRest) {
+        let MatchPatRest { dot2_token: _ } = v;
+    }
+    fn visit_match_pat_paren(state: _, v: &MatchPatParen<MatchPat>) {
+        let MatchPatParen { paren_token: _, pat } = v;
+        state.visit_match_pat(pat);
+    }
+    fn visit_match_pat_paren_simple(state: _, v: &MatchPatParen<MatchPatSimple>) {
+        let MatchPatParen { paren_token: _, pat } = v;
+        state.visit_match_pat_simple(pat);
+    }
+    fn visit_match_pat_or(state: _, v: &MatchPatOr<MatchPat>) {
+        let MatchPatOr { leading_vert: _, cases } = v;
+        for v in cases {
+            state.visit_match_pat(v);
+        }
+    }
+    fn visit_match_pat_or_simple(state: _, v: &MatchPatOr<MatchPatSimple>) {
+        let MatchPatOr { leading_vert: _, cases } = v;
+        for v in cases {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_struct_field(state: _, v: &MatchPatStructField) {
+        let MatchPatStructField { field_name: _, colon_token: _, pat } = v;
+        state.visit_match_pat_simple(pat);
+    }
+    fn visit_match_pat_struct(state: _, v: &MatchPatStruct) {
+        let MatchPatStruct { match_span: _, path: _, brace_token: _, fields, rest: _ } = v;
+        for v in fields {
+            state.visit_match_pat_struct_field(v);
+        }
+    }
+    fn visit_match_pat_tuple(state: _, v: &MatchPatTuple) {
+        let MatchPatTuple { paren_token: _, fields } = v;
+        for v in fields {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_enum_variant(state: _, v: &MatchPatEnumVariant) {
+        let MatchPatEnumVariant {
+            match_span:_,
+            sim:_,
+            variant_path: _,
+            enum_path: _,
+            variant_name: _,
+            field,
+        } = v;
+        if let Some((_, v)) = field {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_simple(state: _, v: &MatchPatSimple) {
+        match v {
+            MatchPatSimple::Paren(v) => state.visit_match_pat_paren_simple(v),
+            MatchPatSimple::Or(v) => state.visit_match_pat_or_simple(v),
+            MatchPatSimple::Binding(v) => state.visit_match_pat_binding(v),
+            MatchPatSimple::Wild(v) => state.visit_match_pat_wild(v),
+            MatchPatSimple::Rest(v) => state.visit_match_pat_rest(v),
+        }
+    }
+    fn visit_match_pat(state: _, v: &MatchPat) {
+        match v {
+            MatchPat::Simple(v) => state.visit_match_pat_simple(v),
+            MatchPat::Or(v) => state.visit_match_pat_or(v),
+            MatchPat::Paren(v) => state.visit_match_pat_paren(v),
+            MatchPat::Struct(v) => state.visit_match_pat_struct(v),
+            MatchPat::Tuple(v) => state.visit_match_pat_tuple(v),
+            MatchPat::EnumVariant(v) => state.visit_match_pat_enum_variant(v),
+        }
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatBinding<> {
         ident: Ident,
@@ -53,6 +150,15 @@ with_debug_clone_and_fold! {
     }
 }
 
+impl<P> MatchPatOr<P> {
+    /// returns the first `|` between two patterns
+    fn first_inner_vert(&self) -> Option<Token![|]> {
+        let mut pairs = self.cases.pairs();
+        pairs.next_back();
+        pairs.next().and_then(|v| v.into_tuple().1.copied())
+    }
+}
+
 impl<P: ToTokens> ToTokens for MatchPatOr<P> {
     fn to_tokens(&self, tokens: &mut TokenStream) {
         let Self {
@@ -77,6 +183,19 @@ impl ToTokens for MatchPatWild {
     }
 }
 
+with_debug_clone_and_fold! {
+    struct MatchPatRest<> {
+        dot2_token: Token![..],
+    }
+}
+
+impl ToTokens for MatchPatRest {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self { dot2_token } = self;
+        dot2_token.to_tokens(tokens);
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatStructField<> {
         field_name: Ident,
@@ -159,9 +278,29 @@ impl ToTokens for MatchPatStruct {
     }
 }
 
+with_debug_clone_and_fold! {
+    struct MatchPatTuple<> {
+        paren_token: Paren,
+        fields: Punctuated<MatchPatSimple, Token![,]>,
+    }
+}
+
+impl ToTokens for MatchPatTuple {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            paren_token,
+            fields,
+        } = self;
+        paren_token.surround(tokens, |tokens| {
+            fields.to_tokens(tokens);
+        })
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatEnumVariant<> {
         match_span: Span,
+        sim: Option<(kw::sim,)>,
         variant_path: Path,
         enum_path: Path,
         variant_name: Ident,
@@ -173,6 +312,7 @@ impl ToTokens for MatchPatEnumVariant {
     fn to_tokens(&self, tokens: &mut TokenStream) {
         let Self {
             match_span,
+            sim,
             variant_path: _,
             enum_path,
             variant_name,
@@ -182,7 +322,28 @@ impl ToTokens for MatchPatEnumVariant {
             __MatchTy::<#enum_path>::#variant_name
         }
         .to_tokens(tokens);
-        if let Some((paren_token, field)) = field {
+        if sim.is_some() {
+            if let Some((paren_token, field)) = field {
+                paren_token.surround(tokens, |tokens| {
+                    field.to_tokens(tokens);
+                    match field {
+                        MatchPatSimple::Paren(_)
+                        | MatchPatSimple::Or(_)
+                        | MatchPatSimple::Binding(_)
+                        | MatchPatSimple::Wild(_) => quote_spanned! {*match_span=>
+                            , _
+                        }
+                        .to_tokens(tokens),
+                        MatchPatSimple::Rest(_) => {}
+                    }
+                });
+            } else {
+                quote_spanned! {*match_span=>
+                    (_)
+                }
+                .to_tokens(tokens);
+            }
+        } else if let Some((paren_token, field)) = field {
             paren_token.surround(tokens, |tokens| field.to_tokens(tokens));
         }
     }
@@ -194,6 +355,7 @@ enum MatchPatSimple {
     Or(MatchPatOr<MatchPatSimple>),
     Binding(MatchPatBinding),
     Wild(MatchPatWild),
+    Rest(MatchPatRest),
 }
 
 impl_fold! {
@@ -202,6 +364,7 @@ impl_fold! {
         Or(MatchPatOr<MatchPatSimple>),
         Binding(MatchPatBinding),
         Wild(MatchPatWild),
+        Rest(MatchPatRest),
     }
 }
 
@@ -212,17 +375,18 @@ impl ToTokens for MatchPatSimple {
             Self::Paren(v) => v.to_tokens(tokens),
             Self::Binding(v) => v.to_tokens(tokens),
             Self::Wild(v) => v.to_tokens(tokens),
+            Self::Rest(v) => v.to_tokens(tokens),
         }
     }
 }
 
-struct EnumPath {
-    variant_path: Path,
-    enum_path: Path,
-    variant_name: Ident,
+pub(crate) struct EnumPath {
+    pub(crate) variant_path: Path,
+    pub(crate) enum_path: Path,
+    pub(crate) variant_name: Ident,
 }
 
-fn parse_enum_path(variant_path: TypePath) -> Result<EnumPath, TypePath> {
+pub(crate) fn parse_enum_path(variant_path: TypePath) -> Result<EnumPath, TypePath> {
     let TypePath {
         qself: None,
         path: variant_path,
@@ -278,6 +442,7 @@ trait ParseMatchPat: Sized {
     fn or(v: MatchPatOr<Self>) -> Self;
     fn paren(v: MatchPatParen<Self>) -> Self;
     fn struct_(state: &mut HdlMatchParseState<'_>, v: MatchPatStruct) -> Result<Self, ()>;
+    fn tuple(state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()>;
     fn enum_variant(state: &mut HdlMatchParseState<'_>, v: MatchPatEnumVariant)
         -> Result<Self, ()>;
     fn parse(state: &mut HdlMatchParseState<'_>, pat: Pat) -> Result<Self, ()> {
@@ -313,6 +478,7 @@ trait ParseMatchPat: Sized {
                         state,
                         MatchPatEnumVariant {
                             match_span: state.match_span,
+                            sim: state.sim,
                             variant_path,
                             enum_path,
                             variant_name,
@@ -359,6 +525,7 @@ trait ParseMatchPat: Sized {
                     state,
                     MatchPatEnumVariant {
                         match_span: state.match_span,
+                        sim: state.sim,
                         variant_path,
                         enum_path,
                         variant_name,
@@ -443,6 +610,7 @@ trait ParseMatchPat: Sized {
                     state,
                     MatchPatEnumVariant {
                         match_span: state.match_span,
+                        sim: state.sim,
                         variant_path,
                         enum_path,
                         variant_name,
@@ -462,7 +630,34 @@ trait ParseMatchPat: Sized {
             }) => Ok(Self::simple(MatchPatSimple::Wild(MatchPatWild {
                 underscore_token,
             }))),
-            Pat::Tuple(_) | Pat::Slice(_) | Pat::Const(_) | Pat::Lit(_) | Pat::Range(_) => {
+            Pat::Tuple(PatTuple {
+                attrs: _,
+                paren_token,
+                elems,
+            }) => {
+                let fields = elems
+                    .into_pairs()
+                    .filter_map_pair_value(|field_pat| {
+                        if let Pat::Rest(PatRest {
+                            attrs: _,
+                            dot2_token,
+                        }) = field_pat
+                        {
+                            Some(MatchPatSimple::Rest(MatchPatRest { dot2_token }))
+                        } else {
+                            MatchPatSimple::parse(state, field_pat).ok()
+                        }
+                    })
+                    .collect();
+                Self::tuple(
+                    state,
+                    MatchPatTuple {
+                        paren_token,
+                        fields,
+                    },
+                )
+            }
+            Pat::Slice(_) | Pat::Const(_) | Pat::Lit(_) | Pat::Range(_) => {
                 state
                     .errors
                     .error(pat, "not yet implemented in #[hdl] patterns");
@@ -497,6 +692,14 @@ impl ParseMatchPat for MatchPatSimple {
         Err(())
     }
 
+    fn tuple(state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()> {
+        state.errors.push(syn::Error::new(
+            v.paren_token.span.open(),
+            "matching tuples is not yet implemented inside structs/enums in #[hdl] patterns",
+        ));
+        Err(())
+    }
+
     fn enum_variant(
         state: &mut HdlMatchParseState<'_>,
         v: MatchPatEnumVariant,
@@ -515,6 +718,7 @@ enum MatchPat {
     Or(MatchPatOr<MatchPat>),
     Paren(MatchPatParen<MatchPat>),
     Struct(MatchPatStruct),
+    Tuple(MatchPatTuple),
     EnumVariant(MatchPatEnumVariant),
 }
 
@@ -524,6 +728,7 @@ impl_fold! {
         Or(MatchPatOr<MatchPat>),
         Paren(MatchPatParen<MatchPat>),
         Struct(MatchPatStruct),
+        Tuple(MatchPatTuple),
         EnumVariant(MatchPatEnumVariant),
     }
 }
@@ -545,6 +750,10 @@ impl ParseMatchPat for MatchPat {
         Ok(Self::Struct(v))
     }
 
+    fn tuple(_state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()> {
+        Ok(Self::Tuple(v))
+    }
+
     fn enum_variant(
         _state: &mut HdlMatchParseState<'_>,
         v: MatchPatEnumVariant,
@@ -560,6 +769,7 @@ impl ToTokens for MatchPat {
             Self::Or(v) => v.to_tokens(tokens),
             Self::Paren(v) => v.to_tokens(tokens),
             Self::Struct(v) => v.to_tokens(tokens),
+            Self::Tuple(v) => v.to_tokens(tokens),
             Self::EnumVariant(v) => v.to_tokens(tokens),
         }
     }
@@ -622,10 +832,6 @@ struct RewriteAsCheckMatch {
 }
 
 impl Fold for RewriteAsCheckMatch {
-    fn fold_field_pat(&mut self, mut i: FieldPat) -> FieldPat {
-        i.colon_token = Some(Token![:](i.member.span()));
-        i
-    }
     fn fold_pat(&mut self, pat: Pat) -> Pat {
         match pat {
             Pat::Ident(mut pat_ident) => match parse_enum_ident(pat_ident.ident) {
@@ -740,17 +946,177 @@ impl Fold for RewriteAsCheckMatch {
         // don't recurse into expressions
         i
     }
+    fn fold_local(&mut self, mut let_stmt: Local) -> Local {
+        if let Some(syn::LocalInit {
+            eq_token,
+            expr: _,
+            diverge,
+        }) = let_stmt.init.take()
+        {
+            let_stmt.init = Some(syn::LocalInit {
+                eq_token,
+                expr: parse_quote_spanned! {self.span=>
+                    __match_value
+                },
+                diverge: diverge.map(|(else_, _expr)| {
+                    (
+                        else_,
+                        parse_quote_spanned! {self.span=>
+                            match __infallible {}
+                        },
+                    )
+                }),
+            });
+        }
+        fold_local(self, let_stmt)
+    }
 }
 
 struct HdlMatchParseState<'a> {
+    sim: Option<(kw::sim,)>,
     match_span: Span,
     errors: &'a mut Errors,
 }
 
+struct HdlLetPatVisitState<'a> {
+    errors: &'a mut Errors,
+    bindings: BTreeSet<&'a Ident>,
+}
+
+impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> {
+    fn visit_match_pat_binding(&mut self, v: &'a MatchPatBinding) {
+        self.bindings.insert(&v.ident);
+    }
+
+    fn visit_match_pat_or(&mut self, v: &'a MatchPatOr<MatchPat>) {
+        if let Some(first_inner_vert) = v.first_inner_vert() {
+            self.errors.error(
+                first_inner_vert,
+                "or-patterns are not supported in let statements",
+            );
+        }
+        visit_match_pat_or(self, v);
+    }
+
+    fn visit_match_pat_or_simple(&mut self, v: &'a MatchPatOr<MatchPatSimple>) {
+        if let Some(first_inner_vert) = v.first_inner_vert() {
+            self.errors.error(
+                first_inner_vert,
+                "or-patterns are not supported in let statements",
+            );
+        }
+        visit_match_pat_or_simple(self, v);
+    }
+
+    fn visit_match_pat_enum_variant(&mut self, v: &'a MatchPatEnumVariant) {
+        self.errors.error(v, "refutable pattern in let statement");
+    }
+}
+
 impl Visitor<'_> {
+    pub(crate) fn process_hdl_let_pat(
+        &mut self,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut let_stmt: Local,
+    ) -> Local {
+        let span = let_stmt.let_token.span();
+        let ExprOptions { sim } = hdl_attr.body;
+        if let Pat::Type(pat) = &mut let_stmt.pat {
+            *pat.ty = wrap_ty_with_expr((*pat.ty).clone());
+        }
+        let check_let_stmt = RewriteAsCheckMatch { span }.fold_local(let_stmt.clone());
+        let Local {
+            attrs: _,
+            let_token,
+            pat,
+            init,
+            semi_token,
+        } = let_stmt;
+        let Some(syn::LocalInit {
+            eq_token,
+            expr,
+            diverge,
+        }) = init
+        else {
+            self.errors
+                .error(let_token, "#[hdl] let must be assigned a value");
+            return empty_let();
+        };
+        if let Some((else_, _)) = diverge {
+            // TODO: implement let-else
+            self.errors
+                .error(else_, "#[hdl] let ... else { ... } is not implemented");
+            return empty_let();
+        }
+        let Ok(pat) = MatchPat::parse(
+            &mut HdlMatchParseState {
+                sim,
+                match_span: span,
+                errors: &mut self.errors,
+            },
+            pat,
+        ) else {
+            return empty_let();
+        };
+        let mut state = HdlLetPatVisitState {
+            errors: &mut self.errors,
+            bindings: BTreeSet::new(),
+        };
+        state.visit_match_pat(&pat);
+        let HdlLetPatVisitState {
+            errors: _,
+            bindings,
+        } = state;
+        let retval = if sim.is_some() {
+            parse_quote_spanned! {span=>
+                let (#(#bindings,)*) = {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let __match_value = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr));
+                    #let_token #pat #eq_token ::fayalite::sim::value::SimValue::into_value(__match_value) #semi_token
+                    (#(#bindings,)*)
+                };
+            }
+        } else {
+            parse_quote_spanned! {span=>
+                let (#(#bindings,)* __scope,) = {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
+                    let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
+                    ::fayalite::expr::check_match_expr(
+                        __match_expr,
+                        |__match_value, __infallible| {
+                            #[allow(unused_variables)]
+                            #check_let_stmt
+                            match __infallible {}
+                        },
+                    );
+                    let mut __match_iter = ::fayalite::module::match_(__match_expr);
+                    let ::fayalite::__std::option::Option::Some(__match_variant) =
+                        ::fayalite::__std::iter::Iterator::next(&mut __match_iter)
+                    else {
+                        ::fayalite::__std::unreachable!("#[hdl] let with uninhabited type");
+                    };
+                    let ::fayalite::__std::option::Option::None =
+                        ::fayalite::__std::iter::Iterator::next(&mut __match_iter)
+                    else {
+                        ::fayalite::__std::unreachable!("#[hdl] let with refutable pattern");
+                    };
+                    let (__match_variant, __scope) =
+                        ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
+                            __match_variant,
+                        );
+                    #let_token #pat #eq_token __match_variant #semi_token
+                    (#(#bindings,)* __scope,)
+                };
+            }
+        };
+        match retval {
+            syn::Stmt::Local(retval) => retval,
+            _ => unreachable!(),
+        }
+    }
     pub(crate) fn process_hdl_match(
         &mut self,
-        _hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         expr_match: ExprMatch,
     ) -> Expr {
         let span = expr_match.match_token.span();
@@ -762,8 +1128,9 @@ impl Visitor<'_> {
             brace_token: _,
             arms,
         } = expr_match;
-        self.require_normal_module_or_fn(match_token);
+        let ExprOptions { sim } = hdl_attr.body;
         let mut state = HdlMatchParseState {
+            sim,
             match_span: span,
             errors: &mut self.errors,
         };
@@ -771,24 +1138,36 @@ impl Visitor<'_> {
             arms.into_iter()
                 .filter_map(|arm| MatchArm::parse(&mut state, arm).ok()),
         );
-        let expr = quote_spanned! {span=>
-            {
-                type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
-                let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
-                ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
-                    #[allow(unused_variables)]
-                    #check_match
-                });
-                for __match_variant in ::fayalite::module::match_(__match_expr) {
-                    let (__match_variant, __scope) =
-                        ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                            __match_variant,
-                        );
-                    #match_token __match_variant {
+        let expr = if sim.is_some() {
+            quote_spanned! {span=>
+                {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let __match_expr = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr));
+                    #match_token ::fayalite::sim::value::SimValue::into_value(__match_expr) {
                         #(#arms)*
                     }
                 }
             }
+        } else {
+            quote_spanned! {span=>
+                {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
+                    let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
+                    ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
+                        #[allow(unused_variables)]
+                        #check_match
+                    });
+                    for __match_variant in ::fayalite::module::match_(__match_expr) {
+                        let (__match_variant, __scope) =
+                            ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
+                                __match_variant,
+                            );
+                        #match_token __match_variant {
+                            #(#arms)*
+                        }
+                    }
+                }
+            }
         };
         syn::parse2(expr).unwrap()
     }
diff --git a/crates/fayalite-proc-macros-impl/src/process_cfg.rs b/crates/fayalite-proc-macros-impl/src/process_cfg.rs
new file mode 100644
index 0000000..5cff08f
--- /dev/null
+++ b/crates/fayalite-proc-macros-impl/src/process_cfg.rs
@@ -0,0 +1,2527 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{Cfg, CfgAttr, Cfgs, Errors};
+use proc_macro2::Ident;
+use std::{collections::VecDeque, marker::PhantomData};
+use syn::{
+    punctuated::{Pair, Punctuated},
+    Token,
+};
+
+struct State<P: Phase> {
+    cfgs: Cfgs<P::CfgsValue>,
+    errors: Errors,
+    _phantom: PhantomData<P>,
+}
+
+impl<P: Phase> State<P> {
+    #[must_use]
+    fn eval_cfg(&mut self, cfg: Cfg) -> bool {
+        struct MyDispatch<'a> {
+            cfg: Cfg,
+            _phantom: PhantomData<&'a ()>,
+        }
+        impl<'a> PhaseDispatch for MyDispatch<'a> {
+            type Args<P: Phase> = &'a mut State<P>;
+            type Output<P: Phase> = bool;
+
+            fn dispatch_collect(
+                self,
+                args: Self::Args<CollectCfgsPhase>,
+            ) -> Self::Output<CollectCfgsPhase> {
+                args.cfgs.insert_cfg(self.cfg, ());
+                true
+            }
+
+            fn dispatch_process(
+                self,
+                args: Self::Args<ProcessCfgsPhase>,
+            ) -> Self::Output<ProcessCfgsPhase> {
+                if let Some(&retval) = args.cfgs.cfgs_map.get(&self.cfg) {
+                    retval
+                } else {
+                    args.errors.error(self.cfg, "unrecognized cfg -- cfg wasn't evaluated when running `__cfg_expansion_helper!`");
+                    true
+                }
+            }
+        }
+        P::dispatch(
+            MyDispatch {
+                cfg,
+                _phantom: PhantomData,
+            },
+            self,
+        )
+    }
+    #[must_use]
+    fn eval_cfgs(
+        &mut self,
+        mut attrs: Vec<syn::Attribute>,
+    ) -> Option<Output<Vec<syn::Attribute>, P>> {
+        let mut queue = VecDeque::from(attrs);
+        attrs = Vec::with_capacity(queue.len()); // cfg_attr is rare, and cfg can't increase length
+        while let Some(attr) = queue.pop_front() {
+            if attr.path().is_ident("cfg") {
+                if let Some(cfg) = self.errors.ok(Cfg::parse_meta(&attr.meta)) {
+                    if !self.eval_cfg(cfg) {
+                        return None;
+                    }
+                    continue;
+                }
+            } else if attr.path().is_ident("cfg_attr") {
+                if let Some(cfg_attr) = self.errors.ok(CfgAttr::parse_meta(&attr.meta)) {
+                    if self.eval_cfg(cfg_attr.to_cfg()) {
+                        // push onto queue since cfg_attr(<cond1>, cfg_attr(<cond2>, <attr>)) is valid
+                        for meta in cfg_attr.attrs {
+                            queue.push_front(syn::Attribute {
+                                pound_token: attr.pound_token,
+                                style: attr.style,
+                                bracket_token: attr.bracket_token,
+                                meta,
+                            });
+                        }
+                    }
+                    continue;
+                }
+            }
+            attrs.push(attr);
+        }
+        Some(Output::new(attrs))
+    }
+    fn process_qself_and_path(
+        &mut self,
+        qself: Option<syn::QSelf>,
+        path: syn::Path,
+    ) -> Option<(Output<Option<syn::QSelf>, P>, Output<syn::Path, P>)> {
+        let qself = if let Some(syn::QSelf {
+            lt_token,
+            ty,
+            position,
+            as_token,
+            gt_token,
+        }) = qself
+        {
+            ty.process(self)?.map(|ty| {
+                Some(syn::QSelf {
+                    lt_token,
+                    ty,
+                    position,
+                    as_token,
+                    gt_token,
+                })
+            })
+        } else {
+            Output::new(None)
+        };
+        let syn::Path {
+            leading_colon,
+            segments,
+        } = path;
+        // path segments don't get removed
+        let path = segments.process(self)?.map(|segments| syn::Path {
+            leading_colon,
+            segments,
+        });
+        Some((qself, path))
+    }
+}
+
+trait PhaseDispatch {
+    type Args<P: Phase>;
+    type Output<P: Phase>;
+    fn dispatch_collect(self, args: Self::Args<CollectCfgsPhase>)
+        -> Self::Output<CollectCfgsPhase>;
+    fn dispatch_process(self, args: Self::Args<ProcessCfgsPhase>)
+        -> Self::Output<ProcessCfgsPhase>;
+}
+
+trait Phase: Sized + 'static {
+    type Output<T>;
+    type CfgsValue;
+    fn output_new<T>(v: T) -> Output<T, Self>;
+    fn output_map<T, U, F: FnOnce(T) -> U>(v: Output<T, Self>, f: F) -> Output<U, Self>;
+    fn output_zip<T, U>(t: Output<T, Self>, u: Output<U, Self>) -> Output<(T, U), Self>;
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self>;
+}
+
+struct CollectCfgsPhase;
+
+impl Phase for CollectCfgsPhase {
+    type Output<T> = ();
+    type CfgsValue = ();
+
+    fn output_new<T>(_v: T) -> Output<T, Self> {
+        Output(())
+    }
+
+    fn output_map<T, U, F: FnOnce(T) -> U>(_v: Output<T, Self>, _f: F) -> Output<U, Self> {
+        Output(())
+    }
+
+    fn output_zip<T, U>(_t: Output<T, Self>, _u: Output<U, Self>) -> Output<(T, U), Self> {
+        Output(())
+    }
+
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self> {
+        d.dispatch_collect(args)
+    }
+}
+
+struct ProcessCfgsPhase;
+
+impl Phase for ProcessCfgsPhase {
+    type Output<T> = T;
+    type CfgsValue = bool;
+
+    fn output_new<T>(v: T) -> Output<T, Self> {
+        Output(v)
+    }
+
+    fn output_map<T, U, F: FnOnce(T) -> U>(v: Output<T, Self>, f: F) -> Output<U, Self> {
+        Output(f(v.0))
+    }
+
+    fn output_zip<T, U>(t: Output<T, Self>, u: Output<U, Self>) -> Output<(T, U), Self> {
+        Output((t.0, u.0))
+    }
+
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self> {
+        d.dispatch_process(args)
+    }
+}
+
+struct Output<T, P: Phase>(P::Output<T>);
+
+trait OutputZip<P: Phase>: Sized {
+    type Output;
+    fn zip(self) -> Output<Self::Output, P>;
+    fn call<R, F: FnOnce(Self::Output) -> R>(self, f: F) -> Output<R, P> {
+        self.zip().map(f)
+    }
+}
+
+impl<P: Phase> OutputZip<P> for () {
+    type Output = ();
+
+    fn zip(self) -> Output<Self::Output, P> {
+        Output::new(())
+    }
+}
+
+impl<P: Phase, T> OutputZip<P> for (Output<T, P>,) {
+    type Output = (T,);
+
+    fn zip(self) -> Output<Self::Output, P> {
+        self.0.map(|v| (v,))
+    }
+}
+
+macro_rules! impl_zip {
+    ($first_arg:ident: $first_T:ident, $($arg:ident: $T:ident),* $(,)?) => {
+        impl_zip!(@step [], [($first_arg: $first_T) $(($arg: $T))*], (),);
+    };
+    (
+        @impl($first_arg:tt,),
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @impl(($first_arg:ident: $first_T:ident),
+            $(($arg:ident: $T:ident),)*),
+        $tuple_pat:tt,
+    ) => {
+        impl<$first_T, $($T,)* P: Phase> OutputZip<P> for (Output<$first_T, P>, $(Output<$T, P>),*) {
+            type Output = ($first_T, $($T),*);
+            fn zip(self) -> Output<($first_T, $($T),*), P> {
+                let (tuples, $($arg),*) = self;
+                $(let tuples = P::output_zip(tuples, $arg);)*
+                tuples.map(|$tuple_pat| ($first_arg, $($arg),*))
+            }
+        }
+    };
+    (
+        @step [$($cur:tt)*],
+        [],
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        (),
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), $next_arg,);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], $next_arg,);
+    };
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        $tuple_pat:tt,
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), ($tuple_pat, $next_arg),);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], ($tuple_pat, $next_arg),);
+    };
+}
+
+impl_zip!(t0: T0, t1: T1, t2: T2, t3: T3, t4: T4, t5: T5, t6: T6, t7: T7, t8: T8, t9: T9, t10: T10, t11: T11);
+
+impl<T, P: Phase> Copy for Output<T, P> where P::Output<T>: Copy {}
+
+impl<T, P: Phase> Clone for Output<T, P>
+where
+    P::Output<T>: Clone,
+{
+    fn clone(&self) -> Self {
+        Self(self.0.clone())
+    }
+}
+
+impl<T, P: Phase> Output<T, P> {
+    fn new(v: T) -> Self {
+        P::output_new(v)
+    }
+    fn map<U, F: FnOnce(T) -> U>(self, f: F) -> Output<U, P> {
+        P::output_map(self, f)
+    }
+}
+
+trait Process<P: Phase>: Sized {
+    #[must_use]
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>>;
+}
+
+impl<P: Phase> Process<P> for syn::Item {
+    fn process(self, _state: &mut State<P>) -> Option<Output<Self, P>> {
+        // don't recurse into items
+        Some(Output::new(self))
+    }
+}
+
+impl<P: Phase> Process<P> for Vec<syn::Attribute> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        state.eval_cfgs(self)
+    }
+}
+
+impl<T: Process<P>, P: Phase> Process<P> for Box<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        Some(T::process(*self, state)?.map(Box::new))
+    }
+}
+
+trait ProcessVecElement {
+    const REMOVE_ELEMENTS: bool;
+}
+
+impl ProcessVecElement for syn::Arm {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::Stmt {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::ForeignItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::ImplItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::Item {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::TraitItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl<T: Process<P> + ProcessVecElement, P: Phase> Process<P> for Vec<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let mut output = Output::new(Vec::new());
+        for value in self {
+            if let Some(value) = value.process(state) {
+                output = (output, value).call(|(mut output, value)| {
+                    output.push(value);
+                    output
+                });
+            } else if !T::REMOVE_ELEMENTS {
+                return None;
+            }
+        }
+        Some(output)
+    }
+}
+
+trait ProcessOption {
+    /// if a configured-off value causes this value to be `None` instead of propagating the configuring-off
+    const REMOVE_VALUE: bool;
+}
+
+impl ProcessOption for syn::Abi {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Block {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::WhereClause {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Expr {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Type {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for Box<syn::Expr> {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::AngleBracketedGenericArguments {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::ImplRestriction {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::BoundLifetimes {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (Token![=], syn::Expr) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![=], syn::Type) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![if], Box<syn::Expr>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![else], Box<syn::Expr>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![&], Option<syn::Lifetime>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![as], Ident) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Ident, Token![:]) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Option<Token![!]>, syn::Path, Token![for]) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::BareVariadic {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Variadic {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::LocalInit {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::Label {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::PatRest {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Box<syn::Pat>, Token![:]) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (Token![@], Box<syn::Pat>) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (syn::token::Brace, Vec<syn::Item>) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl<T: Process<P> + ProcessOption, P: Phase> Process<P> for Option<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        if let Some(this) = self {
+            match this.process(state) {
+                Some(v) => Some(v.map(Some)),
+                None => {
+                    if T::REMOVE_VALUE {
+                        Some(Output::new(None))
+                    } else {
+                        None
+                    }
+                }
+            }
+        } else {
+            Some(Output::new(None))
+        }
+    }
+}
+
+trait ProcessPunctuatedElement {
+    const REMOVE_ELEMENTS: bool;
+}
+
+impl<T: Process<P> + ProcessPunctuatedElement, P: Phase, Punct: Default> Process<P>
+    for Punctuated<T, Punct>
+{
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let mut output = Output::new(Punctuated::<T, Punct>::new());
+        for pair in self.into_pairs() {
+            let (value, punct) = pair.into_tuple();
+            if let Some(value) = value.process(state) {
+                output = (output, value).call(|(mut output, value)| {
+                    output.extend([Pair::new(value, punct)]);
+                    output
+                });
+            } else if !T::REMOVE_ELEMENTS {
+                return None;
+            }
+        }
+        Some(output)
+    }
+}
+
+impl ProcessPunctuatedElement for syn::PathSegment {
+    const REMOVE_ELEMENTS: bool = false;
+}
+
+impl ProcessPunctuatedElement for syn::Type {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Expr {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Pat {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::CapturedParam {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::GenericArgument {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::GenericParam {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Lifetime {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::WherePredicate {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Variant {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FnArg {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::BareFnArg {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::TypeParamBound {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FieldValue {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Field {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FieldPat {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::UseTree {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl<T: Process<P>, U: Process<P>, P: Phase> Process<P> for (T, U) {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let (t, u) = self;
+        let t = t.process(state)?;
+        let u = u.process(state)?;
+        Some((t, u).zip())
+    }
+}
+
+impl<T: Process<P>, U: Process<P>, V: Process<P>, P: Phase> Process<P> for (T, U, V) {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let (t, u, v) = self;
+        let t = t.process(state)?;
+        let u = u.process(state)?;
+        let v = v.process(state)?;
+        Some((t, u, v).zip())
+    }
+}
+
+macro_rules! process_no_op {
+    ($ty:ty) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, _state: &mut State<P>) -> Option<Output<Self, P>> {
+                Some(Output::new(self))
+            }
+        }
+
+        impl ProcessOption for $ty {
+            const REMOVE_VALUE: bool = false;
+        }
+    };
+}
+
+process_no_op!(Token![Self]);
+process_no_op!(Token![abstract]);
+process_no_op!(Token![as]);
+process_no_op!(Token![async]);
+process_no_op!(Token![auto]);
+process_no_op!(Token![await]);
+process_no_op!(Token![become]);
+process_no_op!(Token![box]);
+process_no_op!(Token![break]);
+process_no_op!(Token![const]);
+process_no_op!(Token![continue]);
+process_no_op!(Token![crate]);
+process_no_op!(Token![default]);
+process_no_op!(Token![do]);
+process_no_op!(Token![dyn]);
+process_no_op!(Token![else]);
+process_no_op!(Token![enum]);
+process_no_op!(Token![extern]);
+process_no_op!(Token![final]);
+process_no_op!(Token![fn]);
+process_no_op!(Token![for]);
+process_no_op!(Token![if]);
+process_no_op!(Token![impl]);
+process_no_op!(Token![in]);
+process_no_op!(Token![let]);
+process_no_op!(Token![loop]);
+process_no_op!(Token![macro]);
+process_no_op!(Token![match]);
+process_no_op!(Token![mod]);
+process_no_op!(Token![move]);
+process_no_op!(Token![mut]);
+process_no_op!(Token![override]);
+process_no_op!(Token![priv]);
+process_no_op!(Token![pub]);
+process_no_op!(Token![raw]);
+process_no_op!(Token![ref]);
+process_no_op!(Token![return]);
+process_no_op!(Token![self]);
+process_no_op!(Token![static]);
+process_no_op!(Token![struct]);
+process_no_op!(Token![super]);
+process_no_op!(Token![trait]);
+process_no_op!(Token![try]);
+process_no_op!(Token![type]);
+process_no_op!(Token![typeof]);
+process_no_op!(Token![union]);
+process_no_op!(Token![unsafe]);
+process_no_op!(Token![unsized]);
+process_no_op!(Token![use]);
+process_no_op!(Token![virtual]);
+process_no_op!(Token![where]);
+process_no_op!(Token![while]);
+process_no_op!(Token![yield]);
+
+process_no_op!(Token![!]);
+process_no_op!(Token![!=]);
+process_no_op!(Token![#]);
+process_no_op!(Token![$]);
+process_no_op!(Token![%]);
+process_no_op!(Token![%=]);
+process_no_op!(Token![&]);
+process_no_op!(Token![&&]);
+process_no_op!(Token![&=]);
+process_no_op!(Token![*]);
+process_no_op!(Token![*=]);
+process_no_op!(Token![+]);
+process_no_op!(Token![+=]);
+process_no_op!(Token![,]);
+process_no_op!(Token![-]);
+process_no_op!(Token![-=]);
+process_no_op!(Token![->]);
+process_no_op!(Token![.]);
+process_no_op!(Token![..]);
+process_no_op!(Token![...]);
+process_no_op!(Token![..=]);
+process_no_op!(Token![/]);
+process_no_op!(Token![/=]);
+process_no_op!(Token![:]);
+process_no_op!(Token![::]);
+process_no_op!(Token![;]);
+process_no_op!(Token![<]);
+process_no_op!(Token![<-]);
+process_no_op!(Token![<<]);
+process_no_op!(Token![<<=]);
+process_no_op!(Token![<=]);
+process_no_op!(Token![=]);
+process_no_op!(Token![==]);
+process_no_op!(Token![=>]);
+process_no_op!(Token![>]);
+process_no_op!(Token![>=]);
+process_no_op!(Token![>>]);
+process_no_op!(Token![>>=]);
+process_no_op!(Token![?]);
+process_no_op!(Token![@]);
+process_no_op!(Token![^]);
+process_no_op!(Token![^=]);
+process_no_op!(Token![_]);
+process_no_op!(Token![|]);
+process_no_op!(Token![|=]);
+process_no_op!(Token![||]);
+process_no_op!(Token![~]);
+
+process_no_op!(syn::token::Brace);
+process_no_op!(syn::token::Bracket);
+process_no_op!(syn::token::Paren);
+process_no_op!(syn::token::Group);
+
+process_no_op!(Ident);
+process_no_op!(syn::Index);
+process_no_op!(syn::Lifetime);
+process_no_op!(syn::LitBool);
+process_no_op!(syn::LitByte);
+process_no_op!(syn::LitByteStr);
+process_no_op!(syn::LitChar);
+process_no_op!(syn::LitCStr);
+process_no_op!(syn::LitFloat);
+process_no_op!(syn::LitInt);
+process_no_op!(syn::LitStr);
+process_no_op!(proc_macro2::TokenStream);
+process_no_op!(proc_macro2::Literal);
+
+macro_rules! process_struct {
+    ($ty:path {
+        $($field:ident,)*
+    }) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                let Self {
+                    $($field,)*
+                } = self;
+                $(let $field = $field.process(state)?;)*
+                Some(($($field,)*).call(|($($field,)*)| Self {
+                    $($field,)*
+                }))
+            }
+        }
+    };
+    ($ty:path {
+        $($fields_before:ident,)*
+        #[qself]
+        $qself:ident,
+        $path:ident,
+        $($fields_after:ident,)*
+    }) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                let Self {
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                } = self;
+                $(let $fields_before = $fields_before.process(state)?;)*
+                let ($qself, $path) = state.process_qself_and_path($qself, $path)?;
+                $(let $fields_after = $fields_after.process(state)?;)*
+                Some((
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                ).call(|(
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                )| Self {
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                }))
+            }
+        }
+    };
+}
+
+process_struct! {
+    syn::Abi {
+        extern_token,
+        name,
+    }
+}
+
+process_struct! {
+    syn::AngleBracketedGenericArguments {
+        colon2_token,
+        lt_token,
+        args,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::Arm {
+        attrs,
+        pat,
+        guard,
+        fat_arrow_token,
+        body,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::AssocConst {
+        ident,
+        generics,
+        eq_token,
+        value,
+    }
+}
+
+process_struct! {
+    syn::AssocType {
+        ident,
+        generics,
+        eq_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::BareFnArg {
+        attrs,
+        name,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::BareVariadic {
+        attrs,
+        name,
+        dots,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::Block {
+        brace_token,
+        stmts,
+    }
+}
+
+process_struct! {
+    syn::BoundLifetimes {
+        for_token,
+        lt_token,
+        lifetimes,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::ConstParam {
+        attrs,
+        const_token,
+        ident,
+        colon_token,
+        ty,
+        eq_token,
+        default,
+    }
+}
+
+process_struct! {
+    syn::Constraint {
+        ident,
+        generics,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::DataEnum {
+        enum_token,
+        brace_token,
+        variants,
+    }
+}
+
+process_struct! {
+    syn::DataStruct {
+        struct_token,
+        fields,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::DataUnion {
+        union_token,
+        fields,
+    }
+}
+
+process_struct! {
+    syn::DeriveInput {
+        attrs,
+        vis,
+        ident,
+        generics,
+        data,
+    }
+}
+
+process_struct! {
+    syn::ExprArray {
+        attrs,
+        bracket_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::ExprAssign {
+        attrs,
+        left,
+        eq_token,
+        right,
+    }
+}
+
+process_struct! {
+    syn::ExprAsync {
+        attrs,
+        async_token,
+        capture,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprAwait {
+        attrs,
+        base,
+        dot_token,
+        await_token,
+    }
+}
+
+process_struct! {
+    syn::ExprBinary {
+        attrs,
+        left,
+        op,
+        right,
+    }
+}
+
+process_struct! {
+    syn::ExprBlock {
+        attrs,
+        label,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprBreak {
+        attrs,
+        break_token,
+        label,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprCall {
+        attrs,
+        func,
+        paren_token,
+        args,
+    }
+}
+
+process_struct! {
+    syn::ExprCast {
+        attrs,
+        expr,
+        as_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::ExprClosure {
+        attrs,
+        lifetimes,
+        constness,
+        movability,
+        asyncness,
+        capture,
+        or1_token,
+        inputs,
+        or2_token,
+        output,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprConst {
+        attrs,
+        const_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprContinue {
+        attrs,
+        continue_token,
+        label,
+    }
+}
+
+process_struct! {
+    syn::ExprField {
+        attrs,
+        base,
+        dot_token,
+        member,
+    }
+}
+
+process_struct! {
+    syn::ExprForLoop {
+        attrs,
+        label,
+        for_token,
+        pat,
+        in_token,
+        expr,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprGroup {
+        attrs,
+        group_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprIf {
+        attrs,
+        if_token,
+        cond,
+        then_branch,
+        else_branch,
+    }
+}
+
+process_struct! {
+    syn::ExprIndex {
+        attrs,
+        expr,
+        bracket_token,
+        index,
+    }
+}
+
+process_struct! {
+    syn::ExprInfer {
+        attrs,
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::ExprLet {
+        attrs,
+        let_token,
+        pat,
+        eq_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprLit {
+        attrs,
+        lit,
+    }
+}
+
+process_struct! {
+    syn::ExprLoop {
+        attrs,
+        label,
+        loop_token,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprMacro {
+        attrs,
+        mac,
+    }
+}
+
+process_struct! {
+    syn::ExprMatch {
+        attrs,
+        match_token,
+        expr,
+        brace_token,
+        arms,
+    }
+}
+
+process_struct! {
+    syn::ExprMethodCall {
+        attrs,
+        receiver,
+        dot_token,
+        method,
+        turbofish,
+        paren_token,
+        args,
+    }
+}
+
+process_struct! {
+    syn::ExprParen {
+        attrs,
+        paren_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprPath {
+        attrs,
+        #[qself]
+        qself,
+        path,
+    }
+}
+
+process_struct! {
+    syn::ExprRange {
+        attrs,
+        start,
+        limits,
+        end,
+    }
+}
+
+process_struct! {
+    syn::ExprRawAddr {
+        attrs,
+        and_token,
+        raw,
+        mutability,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprReference {
+        attrs,
+        and_token,
+        mutability,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprRepeat {
+        attrs,
+        bracket_token,
+        expr,
+        semi_token,
+        len,
+    }
+}
+
+process_struct! {
+    syn::ExprReturn {
+        attrs,
+        return_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        brace_token,
+        fields,
+        dot2_token,
+        rest,
+    }
+}
+
+process_struct! {
+    syn::ExprTry {
+        attrs,
+        expr,
+        question_token,
+    }
+}
+
+process_struct! {
+    syn::ExprTryBlock {
+        attrs,
+        try_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprTuple {
+        attrs,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::ExprUnary {
+        attrs,
+        op,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprUnsafe {
+        attrs,
+        unsafe_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprWhile {
+        attrs,
+        label,
+        while_token,
+        cond,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprYield {
+        attrs,
+        yield_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::Field {
+        attrs,
+        vis,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::FieldPat {
+        attrs,
+        member,
+        colon_token,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::FieldValue {
+        attrs,
+        member,
+        colon_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::FieldsNamed {
+        brace_token,
+        named,
+    }
+}
+
+process_struct! {
+    syn::FieldsUnnamed {
+        paren_token,
+        unnamed,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemFn {
+        attrs,
+        vis,
+        sig,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemStatic {
+        attrs,
+        vis,
+        static_token,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemType {
+        attrs,
+        vis,
+        type_token,
+        ident,
+        generics,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::Generics {
+        lt_token,
+        params,
+        gt_token,
+        where_clause,
+    }
+}
+
+process_struct! {
+    syn::ImplItemConst {
+        attrs,
+        vis,
+        defaultness,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ImplItemFn {
+        attrs,
+        vis,
+        defaultness,
+        sig,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ImplItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ImplItemType {
+        attrs,
+        vis,
+        defaultness,
+        type_token,
+        ident,
+        generics,
+        eq_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemConst {
+        attrs,
+        vis,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemEnum {
+        attrs,
+        vis,
+        enum_token,
+        ident,
+        generics,
+        brace_token,
+        variants,
+    }
+}
+
+process_struct! {
+    syn::ItemExternCrate {
+        attrs,
+        vis,
+        extern_token,
+        crate_token,
+        ident,
+        rename,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemFn {
+        attrs,
+        vis,
+        sig,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ItemForeignMod {
+        attrs,
+        unsafety,
+        abi,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemImpl {
+        attrs,
+        defaultness,
+        unsafety,
+        impl_token,
+        generics,
+        trait_,
+        self_ty,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemMacro {
+        attrs,
+        ident,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemMod {
+        attrs,
+        vis,
+        unsafety,
+        mod_token,
+        ident,
+        content,
+        semi,
+    }
+}
+
+process_struct! {
+    syn::ItemStatic {
+        attrs,
+        vis,
+        static_token,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemStruct {
+        attrs,
+        vis,
+        struct_token,
+        ident,
+        generics,
+        fields,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemTrait {
+        attrs,
+        vis,
+        unsafety,
+        auto_token,
+        restriction,
+        trait_token,
+        ident,
+        generics,
+        colon_token,
+        supertraits,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemTraitAlias {
+        attrs,
+        vis,
+        trait_token,
+        ident,
+        generics,
+        eq_token,
+        bounds,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemType {
+        attrs,
+        vis,
+        type_token,
+        ident,
+        generics,
+        eq_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemUnion {
+        attrs,
+        vis,
+        union_token,
+        ident,
+        generics,
+        fields,
+    }
+}
+
+process_struct! {
+    syn::ItemUse {
+        attrs,
+        vis,
+        use_token,
+        leading_colon,
+        tree,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::Label {
+        name,
+        colon_token,
+    }
+}
+
+process_struct! {
+    syn::LifetimeParam {
+        attrs,
+        lifetime,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::Local {
+        attrs,
+        let_token,
+        pat,
+        init,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::LocalInit {
+        eq_token,
+        expr,
+        diverge,
+    }
+}
+
+process_struct! {
+    syn::Macro {
+        path,
+        bang_token,
+        delimiter,
+        tokens,
+    }
+}
+
+process_struct! {
+    syn::MetaList {
+        path,
+        delimiter,
+        tokens,
+    }
+}
+
+process_struct! {
+    syn::MetaNameValue {
+        path,
+        eq_token,
+        value,
+    }
+}
+
+process_struct! {
+    syn::ParenthesizedGenericArguments {
+        paren_token,
+        inputs,
+        output,
+    }
+}
+
+process_struct! {
+    syn::PatIdent {
+        attrs,
+        by_ref,
+        mutability,
+        ident,
+        subpat,
+    }
+}
+
+process_struct! {
+    syn::PatOr {
+        attrs,
+        leading_vert,
+        cases,
+    }
+}
+
+process_struct! {
+    syn::PatParen {
+        attrs,
+        paren_token,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::PatReference {
+        attrs,
+        and_token,
+        mutability,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::PatRest {
+        attrs,
+        dot2_token,
+    }
+}
+
+process_struct! {
+    syn::PatSlice {
+        attrs,
+        bracket_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        brace_token,
+        fields,
+        rest,
+    }
+}
+
+process_struct! {
+    syn::PatTuple {
+        attrs,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatTupleStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatType {
+        attrs,
+        pat,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::PatWild {
+        attrs,
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::Path {
+        leading_colon,
+        segments,
+    }
+}
+
+process_struct! {
+    syn::PathSegment {
+        ident,
+        arguments,
+    }
+}
+
+process_struct! {
+    syn::PreciseCapture {
+        use_token,
+        lt_token,
+        params,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::PredicateLifetime {
+        lifetime,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::PredicateType {
+        lifetimes,
+        bounded_ty,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::Receiver {
+        attrs,
+        reference,
+        mutability,
+        self_token,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::Signature {
+        constness,
+        asyncness,
+        unsafety,
+        abi,
+        fn_token,
+        ident,
+        generics,
+        paren_token,
+        inputs,
+        variadic,
+        output,
+    }
+}
+
+process_struct! {
+    syn::StmtMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitBound {
+        paren_token,
+        modifier,
+        lifetimes,
+        path,
+    }
+}
+
+process_struct! {
+    syn::TraitItemConst {
+        attrs,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemFn {
+        attrs,
+        sig,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemType {
+        attrs,
+        type_token,
+        ident,
+        generics,
+        colon_token,
+        bounds,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TypeArray {
+        bracket_token,
+        elem,
+        semi_token,
+        len,
+    }
+}
+
+process_struct! {
+    syn::TypeBareFn {
+        lifetimes,
+        unsafety,
+        abi,
+        fn_token,
+        paren_token,
+        inputs,
+        variadic,
+        output,
+    }
+}
+
+process_struct! {
+    syn::TypeGroup {
+        group_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeImplTrait {
+        impl_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::TypeInfer {
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::TypeMacro {
+        mac,
+    }
+}
+
+process_struct! {
+    syn::TypeNever {
+        bang_token,
+    }
+}
+
+process_struct! {
+    syn::TypeParam {
+        attrs,
+        ident,
+        colon_token,
+        bounds,
+        eq_token,
+        default,
+    }
+}
+
+process_struct! {
+    syn::TypeParen {
+        paren_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypePath {
+        #[qself]
+        qself,
+        path,
+    }
+}
+
+process_struct! {
+    syn::TypePtr {
+        star_token,
+        const_token,
+        mutability,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeReference {
+        and_token,
+        lifetime,
+        mutability,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeSlice {
+        bracket_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeTraitObject {
+        dyn_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::TypeTuple {
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::UseGlob {
+        star_token,
+    }
+}
+
+process_struct! {
+    syn::UseGroup {
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::UseName {
+        ident,
+    }
+}
+
+process_struct! {
+    syn::UsePath {
+        ident,
+        colon2_token,
+        tree,
+    }
+}
+
+process_struct! {
+    syn::UseRename {
+        ident,
+        as_token,
+        rename,
+    }
+}
+
+process_struct! {
+    syn::Variadic {
+        attrs,
+        pat,
+        dots,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::Variant {
+        attrs,
+        ident,
+        fields,
+        discriminant,
+    }
+}
+
+process_struct! {
+    syn::VisRestricted {
+        pub_token,
+        paren_token,
+        in_token,
+        path,
+    }
+}
+
+process_struct! {
+    syn::WhereClause {
+        where_token,
+        predicates,
+    }
+}
+
+macro_rules! process_enum {
+    ($path:path {
+        $($variant:ident$(($($field:ident),* $(,)?))?,)*
+    }) => {
+        impl<P: Phase> Process<P> for $path {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                match self {
+                    $(Self::$variant$(($($field),*))? => Some(($($($field.process(state)?,)*)?).call(|($($($field,)*)?)| Self::$variant$(($($field),*))?)),)*
+                }
+            }
+        }
+    };
+    ($path:path {
+        $($variant:ident$(($($field:ident),* $(,)?))?,)*
+        #[no_op]
+        _,
+    }) => {
+        impl<P: Phase> Process<P> for $path {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                #![allow(unused_variables)]
+                match self {
+                    $(Self::$variant$(($($field),*))? => Some(($($($field.process(state)?,)*)?).call(|($($($field,)*)?)| Self::$variant$(($($field),*))?)),)*
+                    _ => Some(Output::new(self)),
+                }
+            }
+        }
+    };
+}
+
+process_enum! {
+    syn::AttrStyle {
+        Outer,
+        Inner(f0),
+    }
+}
+
+process_enum! {
+    syn::BinOp {
+        Add(f0),
+        Sub(f0),
+        Mul(f0),
+        Div(f0),
+        Rem(f0),
+        And(f0),
+        Or(f0),
+        BitXor(f0),
+        BitAnd(f0),
+        BitOr(f0),
+        Shl(f0),
+        Shr(f0),
+        Eq(f0),
+        Lt(f0),
+        Le(f0),
+        Ne(f0),
+        Ge(f0),
+        Gt(f0),
+        AddAssign(f0),
+        SubAssign(f0),
+        MulAssign(f0),
+        DivAssign(f0),
+        RemAssign(f0),
+        BitXorAssign(f0),
+        BitAndAssign(f0),
+        BitOrAssign(f0),
+        ShlAssign(f0),
+        ShrAssign(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::CapturedParam {
+        Lifetime(f0),
+        Ident(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Data {
+        Struct(f0),
+        Enum(f0),
+        Union(f0),
+    }
+}
+
+process_enum! {
+    syn::Expr {
+        Array(f0),
+        Assign(f0),
+        Async(f0),
+        Await(f0),
+        Binary(f0),
+        Block(f0),
+        Break(f0),
+        Call(f0),
+        Cast(f0),
+        Closure(f0),
+        Const(f0),
+        Continue(f0),
+        Field(f0),
+        ForLoop(f0),
+        Group(f0),
+        If(f0),
+        Index(f0),
+        Infer(f0),
+        Let(f0),
+        Lit(f0),
+        Loop(f0),
+        Macro(f0),
+        Match(f0),
+        MethodCall(f0),
+        Paren(f0),
+        Path(f0),
+        Range(f0),
+        RawAddr(f0),
+        Reference(f0),
+        Repeat(f0),
+        Return(f0),
+        Struct(f0),
+        Try(f0),
+        TryBlock(f0),
+        Tuple(f0),
+        Unary(f0),
+        Unsafe(f0),
+        Verbatim(f0),
+        While(f0),
+        Yield(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::FieldMutability {
+        None,
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Fields {
+        Named(f0),
+        Unnamed(f0),
+        Unit,
+    }
+}
+
+process_enum! {
+    syn::FnArg {
+        Receiver(f0),
+        Typed(f0),
+    }
+}
+
+process_enum! {
+    syn::ForeignItem {
+        Fn(f0),
+        Static(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::GenericArgument {
+        Lifetime(f0),
+        Type(f0),
+        Const(f0),
+        AssocType(f0),
+        AssocConst(f0),
+        Constraint(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::GenericParam {
+        Lifetime(f0),
+        Type(f0),
+        Const(f0),
+    }
+}
+
+process_enum! {
+    syn::ImplItem {
+        Const(f0),
+        Fn(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::ImplRestriction {
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Lit {
+        Str(f0),
+        ByteStr(f0),
+        CStr(f0),
+        Byte(f0),
+        Char(f0),
+        Int(f0),
+        Float(f0),
+        Bool(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::MacroDelimiter {
+        Paren(f0),
+        Brace(f0),
+        Bracket(f0),
+    }
+}
+
+process_enum! {
+    syn::Member {
+        Named(f0),
+        Unnamed(f0),
+    }
+}
+
+process_enum! {
+    syn::Meta {
+        Path(f0),
+        List(f0),
+        NameValue(f0),
+    }
+}
+
+process_enum! {
+    syn::Pat {
+        Const(f0),
+        Ident(f0),
+        Lit(f0),
+        Macro(f0),
+        Or(f0),
+        Paren(f0),
+        Path(f0),
+        Range(f0),
+        Reference(f0),
+        Rest(f0),
+        Slice(f0),
+        Struct(f0),
+        Tuple(f0),
+        TupleStruct(f0),
+        Type(f0),
+        Verbatim(f0),
+        Wild(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::PathArguments {
+        None,
+        AngleBracketed(f0),
+        Parenthesized(f0),
+    }
+}
+
+process_enum! {
+    syn::PointerMutability {
+        Const(f0),
+        Mut(f0),
+    }
+}
+
+process_enum! {
+    syn::RangeLimits {
+        HalfOpen(f0),
+        Closed(f0),
+    }
+}
+
+process_enum! {
+    syn::ReturnType {
+        Default,
+        Type(f0, f1),
+    }
+}
+
+process_enum! {
+    syn::StaticMutability {
+        Mut(f0),
+        None,
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Stmt {
+        Local(f0),
+        Item(f0),
+        Expr(f0, f1),
+        Macro(f0),
+    }
+}
+
+process_enum! {
+    syn::TraitBoundModifier {
+        None,
+        Maybe(f0),
+    }
+}
+
+process_enum! {
+    syn::TraitItem {
+        Const(f0),
+        Fn(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Type {
+        Array(f0),
+        BareFn(f0),
+        Group(f0),
+        ImplTrait(f0),
+        Infer(f0),
+        Macro(f0),
+        Never(f0),
+        Paren(f0),
+        Path(f0),
+        Ptr(f0),
+        Reference(f0),
+        Slice(f0),
+        TraitObject(f0),
+        Tuple(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::TypeParamBound {
+        Trait(f0),
+        Lifetime(f0),
+        PreciseCapture(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::UnOp {
+        Deref(f0),
+        Not(f0),
+        Neg(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::UseTree {
+        Path(f0),
+        Name(f0),
+        Rename(f0),
+        Glob(f0),
+        Group(f0),
+    }
+}
+
+process_enum! {
+    syn::Visibility {
+        Public(f0),
+        Restricted(f0),
+        Inherited,
+    }
+}
+
+process_enum! {
+    syn::WherePredicate {
+        Lifetime(f0),
+        Type(f0),
+        #[no_op]
+        _,
+    }
+}
+
+struct TopItem(syn::Item);
+
+impl<P: Phase> Process<P> for TopItem {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        match self.0 {
+            syn::Item::Const(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Enum(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::ExternCrate(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Fn(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::ForeignMod(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Impl(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Macro(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Mod(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Static(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Struct(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Trait(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::TraitAlias(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Type(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Union(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Use(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            _ => Some(Output::new(self)),
+        }
+    }
+}
+
+pub(crate) fn process_cfgs(item: syn::Item, cfgs: Cfgs<bool>) -> syn::Result<Option<syn::Item>> {
+    let mut state = State::<ProcessCfgsPhase> {
+        cfgs,
+        errors: Errors::new(),
+        _phantom: PhantomData,
+    };
+    let retval = TopItem(item).process(&mut state).map(|v| v.0 .0);
+    state.errors.finish()?;
+    Ok(retval)
+}
+
+pub(crate) fn collect_cfgs(item: syn::Item) -> syn::Result<Cfgs<()>> {
+    let mut state = State::<CollectCfgsPhase> {
+        cfgs: Cfgs::default(),
+        errors: Errors::new(),
+        _phantom: PhantomData,
+    };
+    let (None | Some(Output(()))) = TopItem(item).process(&mut state);
+    state.errors.finish()?;
+    Ok(state.cfgs)
+}
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 5724a80..f176698 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -25,9 +25,11 @@ jobslot.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
 os_pipe.workspace = true
+petgraph.workspace = true
 serde_json.workspace = true
 serde.workspace = true
 tempfile.workspace = true
+vec_map.workspace = true
 which.workspace = true
 
 [dev-dependencies]
@@ -38,6 +40,7 @@ fayalite-visit-gen.workspace = true
 
 [features]
 unstable-doc = []
+unstable-test-hasher = []
 
 [package.metadata.docs.rs]
 features = ["unstable-doc"]
diff --git a/crates/fayalite/build.rs b/crates/fayalite/build.rs
index 24d8f31..c6680d5 100644
--- a/crates/fayalite/build.rs
+++ b/crates/fayalite/build.rs
@@ -5,6 +5,9 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_true_for_tests)");
+    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
index 61d29b5..229871b 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 //! ## `#[hdl] let` statements
 
+pub mod destructuring;
 pub mod inputs_outputs;
 pub mod instances;
 pub mod memories;
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs
new file mode 100644
index 0000000..1fc4705
--- /dev/null
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+//! ### Destructuring Let
+//!
+//! You can use `#[hdl] let` to destructure types, similarly to Rust `let` statements with non-trivial patterns.
+//!
+//! `#[hdl] let` statements can only match one level of struct/tuple pattern for now,
+//! e.g. you can match with the pattern `MyStruct { a, b }`, but not `MyStruct { a, b: Struct2 { v } }`.
+//!
+//! ```
+//! # use fayalite::prelude::*;
+//! #[hdl]
+//! struct MyStruct {
+//!     a: UInt<8>,
+//!     b: Bool,
+//! }
+//!
+//! #[hdl_module]
+//! fn my_module() {
+//!     #[hdl]
+//!     let my_input: MyStruct = m.input();
+//!     #[hdl]
+//!     let my_output: UInt<8> = m.input();
+//!     #[hdl]
+//!     let MyStruct { a, b } = my_input;
+//!     #[hdl]
+//!     if b {
+//!         connect(my_output, a);
+//!     } else {
+//!         connect(my_output, 0_hdl_u8);
+//!     }
+//! }
+//! ```
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
index 9e6c511..6df70f1 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
@@ -7,5 +7,5 @@
 //!
 //! `#[hdl] match` statements' bodies must evaluate to type `()` for now.
 //!
-//! `#[hdl] match` statements can only match one level of struct/enum pattern for now,
+//! `#[hdl] match` statements can only match one level of struct/tuple/enum pattern for now,
 //! e.g. you can match with the pattern `HdlSome(v)`, but not `HdlSome(HdlSome(_))`.
diff --git a/crates/fayalite/src/annotations.rs b/crates/fayalite/src/annotations.rs
index 8eff4a0..1c517ae 100644
--- a/crates/fayalite/src/annotations.rs
+++ b/crates/fayalite/src/annotations.rs
@@ -12,7 +12,7 @@ use std::{
     ops::Deref,
 };
 
-#[derive(Clone)]
+#[derive(Clone, Debug)]
 struct CustomFirrtlAnnotationFieldsImpl {
     value: serde_json::Map<String, serde_json::Value>,
     serialized: Interned<str>,
diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index f617f91..6d9b043 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -2,17 +2,24 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::ArrayIndex, Expr, ToExpr},
-    int::{DynSize, KnownSize, Size, SizeType, DYN_SIZE},
+    expr::{
+        ops::{ArrayLiteral, ExprFromIterator, ExprIntoIterator, ExprPartialEq},
+        CastToBits, Expr, HdlPartialEq, ReduceBits, ToExpr,
+    },
+    int::{Bool, DynSize, KnownSize, Size, SizeType, DYN_SIZE},
     intern::{Intern, Interned, LazyInterned},
     module::transform::visit::{Fold, Folder, Visit, Visitor},
+    sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
     ty::{
-        CanonicalType, MatchVariantWithoutScope, StaticType, Type, TypeProperties, TypeWithDeref,
+        serde_impls::SerdeCanonicalType, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
+        TypeProperties, TypeWithDeref,
     },
     util::ConstUsize,
 };
-use std::ops::Index;
+use bitvec::slice::BitSlice;
+use serde::{de::Error, Deserialize, Deserializer, Serialize, Serializer};
+use std::{iter::FusedIterator, ops::Index};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
@@ -91,6 +98,12 @@ impl<T: Type, Len: KnownSize + Size<SizeType = Len>> ArrayType<T, Len> {
     }
 }
 
+impl<T: StaticType, Len: KnownSize> Default for ArrayType<T, Len> {
+    fn default() -> Self {
+        Self::TYPE
+    }
+}
+
 impl<T: StaticType, Len: KnownSize> StaticType for ArrayType<T, Len> {
     const TYPE: Self = Self {
         element: LazyInterned::new_lazy(&|| T::TYPE.intern_sized()),
@@ -139,6 +152,7 @@ impl<T: Type + Visit<State>, Len: Size, State: Visitor + ?Sized> Visit<State>
 impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
     type BaseType = Array;
     type MaskType = ArrayType<T::MaskType, Len>;
+    type SimValue = Len::ArraySimValue<T>;
     type MatchVariant = Len::ArrayMatch<T>;
     type MatchActiveScope = ();
     type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Len::ArrayMatch<T>>;
@@ -148,10 +162,8 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
         this: Expr<Self>,
         source_location: SourceLocation,
     ) -> Self::MatchVariantsIter {
-        let base = Expr::as_dyn_array(this);
-        let base_ty = Expr::ty(base);
         let _ = source_location;
-        let retval = Vec::from_iter((0..base_ty.len()).map(|i| ArrayIndex::new(base, i).to_expr()));
+        let retval = Vec::from_iter(this);
         std::iter::once(MatchVariantWithoutScope(
             Len::ArrayMatch::<T>::try_from(retval)
                 .ok()
@@ -177,16 +189,97 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
             Len::from_usize(array.len()),
         )
     }
+
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element = self.element();
+        let element_bit_width = element.canonical().bit_width();
+        TryFrom::try_from(Vec::from_iter((0..self.len()).map(|i| {
+            SimValue::from_bitslice(element, &bits[i * element_bit_width..][..element_bit_width])
+        })))
+        .ok()
+        .expect("used correct length")
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element_ty = self.element();
+        let element_bit_width = element_ty.canonical().bit_width();
+        let value: &mut [SimValue<T>] = value.as_mut();
+        assert_eq!(self.len(), value.len());
+        for (i, element_value) in value.iter_mut().enumerate() {
+            assert_eq!(SimValue::ty(element_value), element_ty);
+            SimValue::bits_mut(element_value)
+                .bits_mut()
+                .copy_from_bitslice(&bits[i * element_bit_width..][..element_bit_width]);
+        }
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element_ty = self.element();
+        let element_bit_width = element_ty.canonical().bit_width();
+        let value: &[SimValue<T>] = value.as_ref();
+        assert_eq!(self.len(), value.len());
+        for (i, element_value) in value.iter().enumerate() {
+            assert_eq!(SimValue::ty(element_value), element_ty);
+            bits[i * element_bit_width..][..element_bit_width]
+                .copy_from_bitslice(SimValue::bits(element_value).bits());
+        }
+    }
+}
+
+impl<T: Type + Serialize, Len: Size> Serialize for ArrayType<T, Len> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeCanonicalType::<T>::Array {
+            element: self.element(),
+            len: self.len(),
+        }
+        .serialize(serializer)
+    }
+}
+
+impl<'de, T: Type + Deserialize<'de>, Len: Size> Deserialize<'de> for ArrayType<T, Len> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let name = |len| -> String {
+            if let Some(len) = len {
+                format!("an Array<_, {len}>")
+            } else {
+                "an Array<_>".to_string()
+            }
+        };
+        match SerdeCanonicalType::<T>::deserialize(deserializer)? {
+            SerdeCanonicalType::Array { element, len } => {
+                if let Some(len) = Len::try_from_usize(len) {
+                    Ok(Self::new(element, len))
+                } else {
+                    Err(Error::invalid_value(
+                        serde::de::Unexpected::Other(&name(Some(len))),
+                        &&*name(Len::KNOWN_VALUE),
+                    ))
+                }
+            }
+            ty => Err(Error::invalid_value(
+                serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                &&*name(Len::KNOWN_VALUE),
+            )),
+        }
+    }
 }
 
 impl<T: Type, Len: Size> TypeWithDeref for ArrayType<T, Len> {
     fn expr_deref(this: &Expr<Self>) -> &Self::MatchVariant {
-        let base = Expr::as_dyn_array(*this);
-        let base_ty = Expr::ty(base);
-        let retval = Vec::from_iter((0..base_ty.len()).map(|i| ArrayIndex::new(base, i).to_expr()));
+        let retval = Vec::from_iter(*this);
         Interned::into_inner(Intern::intern_sized(
             Len::ArrayMatch::<T>::try_from(retval)
                 .ok()
@@ -218,3 +311,143 @@ impl<T: Type, L: SizeType> Index<L> for ArrayWithoutLen<T> {
         Interned::into_inner(Intern::intern_sized(ArrayType::new(self.element, len)))
     }
 }
+
+impl<Lhs: Type, Rhs: Type, Len: Size> ExprPartialEq<ArrayType<Rhs, Len>> for ArrayType<Lhs, Len>
+where
+    Lhs: ExprPartialEq<Rhs>,
+{
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<ArrayType<Rhs, Len>>) -> Expr<Bool> {
+        let lhs_ty = Expr::ty(lhs);
+        let rhs_ty = Expr::ty(rhs);
+        assert_eq!(lhs_ty.len(), rhs_ty.len());
+        lhs.into_iter()
+            .zip(rhs)
+            .map(|(l, r)| l.cmp_eq(r))
+            .collect::<Expr<Array<Bool>>>()
+            .cast_to_bits()
+            .all_one_bits()
+    }
+
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<ArrayType<Rhs, Len>>) -> Expr<Bool> {
+        let lhs_ty = Expr::ty(lhs);
+        let rhs_ty = Expr::ty(rhs);
+        assert_eq!(lhs_ty.len(), rhs_ty.len());
+        lhs.into_iter()
+            .zip(rhs)
+            .map(|(l, r)| l.cmp_ne(r))
+            .collect::<Expr<Array<Bool>>>()
+            .cast_to_bits()
+            .any_one_bits()
+    }
+}
+
+impl<Lhs: Type, Rhs: Type, Len: Size> SimValuePartialEq<ArrayType<Rhs, Len>> for ArrayType<Lhs, Len>
+where
+    Lhs: SimValuePartialEq<Rhs>,
+{
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<ArrayType<Rhs, Len>>) -> bool {
+        AsRef::<[_]>::as_ref(&**this)
+            .iter()
+            .zip(AsRef::<[_]>::as_ref(&**other))
+            .all(|(l, r)| SimValuePartialEq::sim_value_eq(l, r))
+    }
+}
+
+impl<T: Type, Len: Size> ExprIntoIterator for ArrayType<T, Len> {
+    type Item = T;
+    type ExprIntoIter = ExprArrayIter<T, Len>;
+
+    fn expr_into_iter(e: Expr<Self>) -> Self::ExprIntoIter {
+        ExprArrayIter {
+            base: e,
+            indexes: 0..Expr::ty(e).len(),
+        }
+    }
+}
+
+#[derive(Clone, Debug)]
+pub struct ExprArrayIter<T: Type, Len: Size> {
+    base: Expr<ArrayType<T, Len>>,
+    indexes: std::ops::Range<usize>,
+}
+
+impl<T: Type, Len: Size> ExprArrayIter<T, Len> {
+    pub fn base(&self) -> Expr<ArrayType<T, Len>> {
+        self.base
+    }
+    pub fn indexes(&self) -> std::ops::Range<usize> {
+        self.indexes.clone()
+    }
+}
+
+impl<T: Type, Len: Size> Iterator for ExprArrayIter<T, Len> {
+    type Item = Expr<T>;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.indexes.next().map(|i| self.base[i])
+    }
+
+    fn size_hint(&self) -> (usize, Option<usize>) {
+        self.indexes.size_hint()
+    }
+
+    fn count(self) -> usize {
+        self.indexes.count()
+    }
+
+    fn last(mut self) -> Option<Self::Item> {
+        self.next_back()
+    }
+
+    fn nth(&mut self, n: usize) -> Option<Self::Item> {
+        self.indexes.nth(n).map(|i| self.base[i])
+    }
+
+    fn fold<B, F>(self, init: B, mut f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.indexes.fold(init, |b, i| f(b, self.base[i]))
+    }
+}
+
+impl<T: Type, Len: Size> DoubleEndedIterator for ExprArrayIter<T, Len> {
+    fn next_back(&mut self) -> Option<Self::Item> {
+        self.indexes.next_back().map(|i| self.base[i])
+    }
+
+    fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+        self.indexes.nth_back(n).map(|i| self.base[i])
+    }
+
+    fn rfold<B, F>(self, init: B, mut f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.indexes.rfold(init, |b, i| f(b, self.base[i]))
+    }
+}
+
+impl<T: Type, Len: Size> ExactSizeIterator for ExprArrayIter<T, Len> {
+    fn len(&self) -> usize {
+        self.indexes.len()
+    }
+}
+
+impl<T: Type, Len: Size> FusedIterator for ExprArrayIter<T, Len> {}
+
+impl<A: StaticType> ExprFromIterator<Expr<A>> for Array<A> {
+    fn expr_from_iter<T: IntoIterator<Item = Expr<A>>>(iter: T) -> Expr<Self> {
+        ArrayLiteral::new(
+            A::TYPE,
+            iter.into_iter().map(|v| Expr::canonical(v)).collect(),
+        )
+        .to_expr()
+    }
+}
+
+impl<'a, A: StaticType> ExprFromIterator<&'a Expr<A>> for Array<A> {
+    fn expr_from_iter<T: IntoIterator<Item = &'a Expr<A>>>(iter: T) -> Expr<Self> {
+        iter.into_iter().copied().collect()
+    }
+}
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 843eb6c..240c0c6 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -2,18 +2,25 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::BundleLiteral, Expr, ToExpr},
+    expr::{
+        ops::{ArrayLiteral, BundleLiteral, ExprPartialEq},
+        CastToBits, Expr, ReduceBits, ToExpr,
+    },
+    int::{Bool, DynSize},
     intern::{Intern, Interned},
+    sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{
-        impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
-        TypeProperties, TypeWithDeref,
+        impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, OpaqueSimValue,
+        StaticType, Type, TypeProperties, TypeWithDeref,
     },
+    util::HashMap,
 };
-use hashbrown::HashMap;
+use bitvec::{slice::BitSlice, vec::BitVec};
+use serde::{Deserialize, Serialize};
 use std::{fmt, marker::PhantomData};
 
-#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
+#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq, Serialize, Deserialize)]
 pub struct BundleField {
     pub name: Interned<str>,
     pub flipped: bool,
@@ -153,7 +160,7 @@ impl Default for BundleTypePropertiesBuilder {
 impl Bundle {
     #[track_caller]
     pub fn new(fields: Interned<[BundleField]>) -> Self {
-        let mut name_indexes = HashMap::with_capacity(fields.len());
+        let mut name_indexes = HashMap::with_capacity_and_hasher(fields.len(), Default::default());
         let mut field_offsets = Vec::with_capacity(fields.len());
         let mut type_props_builder = BundleTypePropertiesBuilder::new();
         for (index, &BundleField { name, flipped, ty }) in fields.iter().enumerate() {
@@ -210,6 +217,7 @@ impl Bundle {
 impl Type for Bundle {
     type BaseType = Bundle;
     type MaskType = Bundle;
+    type SimValue = OpaqueSimValue;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         Self::new(Interned::from_iter(self.0.fields.into_iter().map(
@@ -233,6 +241,20 @@ impl Type for Bundle {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        bits.copy_from_bitslice(value.bits().bits());
+    }
 }
 
 pub trait BundleType: Type<BaseType = Bundle> {
@@ -241,6 +263,93 @@ pub trait BundleType: Type<BaseType = Bundle> {
     fn fields(&self) -> Interned<[BundleField]>;
 }
 
+pub struct BundleSimValueFromBits<'a> {
+    fields: std::slice::Iter<'static, BundleField>,
+    bits: &'a BitSlice,
+}
+
+impl<'a> BundleSimValueFromBits<'a> {
+    #[track_caller]
+    pub fn new<T: BundleType>(bundle_ty: T, bits: &'a BitSlice) -> Self {
+        let fields = bundle_ty.fields();
+        assert_eq!(
+            bits.len(),
+            fields
+                .iter()
+                .map(|BundleField { ty, .. }| ty.bit_width())
+                .sum::<usize>()
+        );
+        Self {
+            fields: Interned::into_inner(fields).iter(),
+            bits,
+        }
+    }
+    #[track_caller]
+    fn field_ty_and_bits<T: Type>(&mut self) -> (T, &'a BitSlice) {
+        let Some(&BundleField {
+            name: _,
+            flipped: _,
+            ty,
+        }) = self.fields.next()
+        else {
+            panic!("tried to read too many fields from BundleSimValueFromBits");
+        };
+        let (field_bits, rest) = self.bits.split_at(ty.bit_width());
+        self.bits = rest;
+        (T::from_canonical(ty), field_bits)
+    }
+    #[track_caller]
+    pub fn field_from_bits<T: Type>(&mut self) -> SimValue<T> {
+        let (field_ty, field_bits) = self.field_ty_and_bits::<T>();
+        SimValue::from_bitslice(field_ty, field_bits)
+    }
+    #[track_caller]
+    pub fn field_clone_from_bits<T: Type>(&mut self, field_value: &mut SimValue<T>) {
+        let (field_ty, field_bits) = self.field_ty_and_bits::<T>();
+        assert_eq!(field_ty, SimValue::ty(field_value));
+        SimValue::bits_mut(field_value)
+            .bits_mut()
+            .copy_from_bitslice(field_bits);
+    }
+}
+
+pub struct BundleSimValueToBits<'a> {
+    fields: std::slice::Iter<'static, BundleField>,
+    bits: &'a mut BitSlice,
+}
+
+impl<'a> BundleSimValueToBits<'a> {
+    #[track_caller]
+    pub fn new<T: BundleType>(bundle_ty: T, bits: &'a mut BitSlice) -> Self {
+        let fields = bundle_ty.fields();
+        assert_eq!(
+            bits.len(),
+            fields
+                .iter()
+                .map(|BundleField { ty, .. }| ty.bit_width())
+                .sum::<usize>()
+        );
+        Self {
+            fields: Interned::into_inner(fields).iter(),
+            bits,
+        }
+    }
+    #[track_caller]
+    pub fn field_to_bits<T: Type>(&mut self, field_value: &SimValue<T>) {
+        let Some(&BundleField {
+            name: _,
+            flipped: _,
+            ty,
+        }) = self.fields.next()
+        else {
+            panic!("tried to read too many fields from BundleSimValueFromBits");
+        };
+        assert_eq!(T::from_canonical(ty), SimValue::ty(field_value));
+        self.bits[..ty.bit_width()].copy_from_bitslice(SimValue::bits(field_value).bits());
+        self.bits = &mut std::mem::take(&mut self.bits)[ty.bit_width()..];
+    }
+}
+
 #[derive(Default)]
 pub struct NoBuilder;
 
@@ -323,7 +432,19 @@ macro_rules! impl_tuple_builder_fields {
 }
 
 macro_rules! impl_tuples {
-    ([$({#[num = $num:literal, field = $field:ident] $var:ident: $T:ident})*] []) => {
+    (
+        [$({
+            #[
+                num = $num:tt,
+                field = $field:ident,
+                ty = $ty_var:ident: $Ty:ident,
+                lhs = $lhs_var:ident: $Lhs:ident,
+                rhs = $rhs_var:ident: $Rhs:ident
+            ]
+            $var:ident: $T:ident
+        })*]
+        []
+    ) => {
         impl_tuple_builder_fields! {
             {}
             [$({
@@ -335,6 +456,7 @@ macro_rules! impl_tuples {
         impl<$($T: Type,)*> Type for ($($T,)*) {
             type BaseType = Bundle;
             type MaskType = ($($T::MaskType,)*);
+            type SimValue = ($(SimValue<$T>,)*);
             type MatchVariant = ($(Expr<$T>,)*);
             type MatchActiveScope = ();
             type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
@@ -373,6 +495,24 @@ macro_rules! impl_tuples {
             fn source_location() -> SourceLocation {
                 SourceLocation::builtin()
             }
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueFromBits::new(*self, bits);
+                $(let $var = v.field_from_bits();)*
+                ($($var,)*)
+            }
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueFromBits::new(*self, bits);
+                let ($($var,)*) = value;
+                $(v.field_clone_from_bits($var);)*
+            }
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueToBits::new(*self, bits);
+                let ($($var,)*) = value;
+                $(v.field_to_bits($var);)*
+            }
         }
         impl<$($T: Type,)*> BundleType for ($($T,)*) {
             type Builder = TupleBuilder<($(Unfilled<$T>,)*)>;
@@ -423,6 +563,106 @@ macro_rules! impl_tuples {
                 BundleLiteral::new(ty, field_values[..].intern()).to_expr()
             }
         }
+        impl<$($T: ToSimValueWithType<CanonicalType>,)*> ToSimValueWithType<CanonicalType> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(ToSimValueWithType::<Bundle>::to_sim_value_with_type(self, Bundle::from_canonical(ty)))
+            }
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType>
+            {
+                SimValue::into_canonical(ToSimValueWithType::<Bundle>::into_sim_value_with_type(self, Bundle::from_canonical(ty)))
+            }
+        }
+        impl<$($T: ToSimValueWithType<CanonicalType>,)*> ToSimValueWithType<Bundle> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value_with_type(&self, ty: Bundle) -> SimValue<Bundle> {
+                let ($($var,)*) = self;
+                let [$($ty_var,)*] = *ty.fields() else {
+                    panic!("bundle has wrong number of fields");
+                };
+                $(let $var = $var.to_sim_value_with_type($ty_var.ty);)*
+                ToSimValueWithType::into_sim_value_with_type(($($var,)*), ty)
+            }
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: Bundle) -> SimValue<Bundle> {
+                #![allow(unused_mut)]
+                #![allow(clippy::unused_unit)]
+                let ($($var,)*) = self;
+                let [$($ty_var,)*] = *ty.fields() else {
+                    panic!("bundle has wrong number of fields");
+                };
+                let mut bits = BitVec::new();
+                $(let $var = $var.into_sim_value_with_type($ty_var.ty);
+                assert_eq!(SimValue::ty(&$var), $ty_var.ty);
+                bits.extend_from_bitslice(SimValue::bits(&$var).bits());
+                )*
+                bits.into_sim_value_with_type(ty)
+            }
+        }
+        impl<$($T: ToSimValueWithType<$Ty>, $Ty: Type,)*> ToSimValueWithType<($($Ty,)*)> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value_with_type(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+                let ($($var,)*) = self;
+                let ($($ty_var,)*) = ty;
+                $(let $var = $var.to_sim_value_with_type($ty_var);)*
+                SimValue::from_value(ty, ($($var,)*))
+            }
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+                let ($($var,)*) = self;
+                let ($($ty_var,)*) = ty;
+                $(let $var = $var.into_sim_value_with_type($ty_var);)*
+                SimValue::from_value(ty, ($($var,)*))
+            }
+        }
+        impl<$($T: ToSimValue,)*> ToSimValue for ($($T,)*) {
+            type Type = ($($T::Type,)*);
+            #[track_caller]
+            fn to_sim_value(&self) -> SimValue<Self::Type> {
+                let ($($var,)*) = self;
+                $(let $var = $var.to_sim_value();)*
+                SimValue::from_value(($(SimValue::ty(&$var),)*), ($($var,)*))
+            }
+            #[track_caller]
+            fn into_sim_value(self) -> SimValue<Self::Type> {
+                let ($($var,)*) = self;
+                $(let $var = $var.to_sim_value();)*
+                SimValue::from_value(($(SimValue::ty(&$var),)*), ($($var,)*))
+            }
+        }
+        impl<$($Lhs: Type + ExprPartialEq<$Rhs>, $Rhs: Type,)*> ExprPartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<($($Rhs,)*)>) -> Expr<Bool> {
+                let ($($lhs_var,)*) = *lhs;
+                let ($($rhs_var,)*) = *rhs;
+                ArrayLiteral::<Bool, DynSize>::new(
+                    Bool,
+                    FromIterator::from_iter([$(Expr::canonical(ExprPartialEq::cmp_eq($lhs_var, $rhs_var)),)*]),
+                )
+                .cast_to_bits()
+                .all_one_bits()
+            }
+
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<($($Rhs,)*)>) -> Expr<Bool> {
+                let ($($lhs_var,)*) = *lhs;
+                let ($($rhs_var,)*) = *rhs;
+                ArrayLiteral::<Bool, DynSize>::new(
+                    Bool,
+                    FromIterator::from_iter([$(Expr::canonical(ExprPartialEq::cmp_ne($lhs_var, $rhs_var)),)*]),
+                )
+                .cast_to_bits()
+                .any_one_bits()
+            }
+        }
+        impl<$($Lhs: SimValuePartialEq<$Rhs>, $Rhs: Type,)*> SimValuePartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
+            fn sim_value_eq(lhs: &SimValue<Self>, rhs: &SimValue<($($Rhs,)*)>) -> bool {
+                let ($($lhs_var,)*) = &**lhs;
+                let ($($rhs_var,)*) = &**rhs;
+                let retval = true;
+                $(let retval = retval && $lhs_var == $rhs_var;)*
+                retval
+            }
+        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -432,24 +672,25 @@ macro_rules! impl_tuples {
 
 impl_tuples! {
     [] [
-        {#[num = 0, field = field_0] v0: T0}
-        {#[num = 1, field = field_1] v1: T1}
-        {#[num = 2, field = field_2] v2: T2}
-        {#[num = 3, field = field_3] v3: T3}
-        {#[num = 4, field = field_4] v4: T4}
-        {#[num = 5, field = field_5] v5: T5}
-        {#[num = 6, field = field_6] v6: T6}
-        {#[num = 7, field = field_7] v7: T7}
-        {#[num = 8, field = field_8] v8: T8}
-        {#[num = 9, field = field_9] v9: T9}
-        {#[num = 10, field = field_10] v10: T10}
-        {#[num = 11, field = field_11] v11: T11}
+        {#[num = 0, field = field_0, ty = ty0: Ty0, lhs = lhs0: Lhs0, rhs = rhs0: Rhs0] v0: T0}
+        {#[num = 1, field = field_1, ty = ty1: Ty1, lhs = lhs1: Lhs1, rhs = rhs1: Rhs1] v1: T1}
+        {#[num = 2, field = field_2, ty = ty2: Ty2, lhs = lhs2: Lhs2, rhs = rhs2: Rhs2] v2: T2}
+        {#[num = 3, field = field_3, ty = ty3: Ty3, lhs = lhs3: Lhs3, rhs = rhs3: Rhs3] v3: T3}
+        {#[num = 4, field = field_4, ty = ty4: Ty4, lhs = lhs4: Lhs4, rhs = rhs4: Rhs4] v4: T4}
+        {#[num = 5, field = field_5, ty = ty5: Ty5, lhs = lhs5: Lhs5, rhs = rhs5: Rhs5] v5: T5}
+        {#[num = 6, field = field_6, ty = ty6: Ty6, lhs = lhs6: Lhs6, rhs = rhs6: Rhs6] v6: T6}
+        {#[num = 7, field = field_7, ty = ty7: Ty7, lhs = lhs7: Lhs7, rhs = rhs7: Rhs7] v7: T7}
+        {#[num = 8, field = field_8, ty = ty8: Ty8, lhs = lhs8: Lhs8, rhs = rhs8: Rhs8] v8: T8}
+        {#[num = 9, field = field_9, ty = ty9: Ty9, lhs = lhs9: Lhs9, rhs = rhs9: Rhs9] v9: T9}
+        {#[num = 10, field = field_10, ty = ty10: Ty10, lhs = lhs10: Lhs10, rhs = rhs10: Rhs10] v10: T10}
+        {#[num = 11, field = field_11, ty = ty11: Ty11, lhs = lhs11: Lhs11, rhs = rhs11: Rhs11] v11: T11}
     ]
 }
 
 impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     type BaseType = Bundle;
     type MaskType = ();
+    type SimValue = PhantomData<T>;
     type MatchVariant = PhantomData<T>;
     type MatchActiveScope = ();
     type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
@@ -482,6 +723,16 @@ impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert!(bits.is_empty());
+        *self
+    }
+    fn sim_value_clone_from_bits(&self, _value: &mut Self::SimValue, bits: &BitSlice) {
+        assert!(bits.is_empty());
+    }
+    fn sim_value_to_bits(&self, _value: &Self::SimValue, bits: &mut BitSlice) {
+        assert!(bits.is_empty());
+    }
 }
 
 pub struct PhantomDataBuilder<T: ?Sized + Send + Sync + 'static>(PhantomData<T>);
@@ -528,3 +779,39 @@ impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
         BundleLiteral::new(PhantomData, Interned::default()).to_expr()
     }
 }
+
+impl<T: ?Sized + Send + Sync + 'static> ToSimValue for PhantomData<T> {
+    type Type = PhantomData<T>;
+
+    #[track_caller]
+    fn to_sim_value(&self) -> SimValue<Self> {
+        SimValue::from_value(*self, *self)
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> ToSimValueWithType<Self> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Self) -> SimValue<Self> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl<T: ?Sized> ToSimValueWithType<Bundle> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Bundle) -> SimValue<Bundle> {
+        assert!(ty.fields().is_empty());
+        ToSimValueWithType::into_sim_value_with_type(BitVec::new(), ty)
+    }
+}
+
+impl<T: ?Sized> ToSimValueWithType<CanonicalType> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        let ty = Bundle::from_canonical(ty);
+        assert!(ty.fields().is_empty());
+        SimValue::into_canonical(ToSimValueWithType::into_sim_value_with_type(
+            BitVec::new(),
+            ty,
+        ))
+    }
+}
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 1030474..1f208a8 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -258,7 +258,7 @@ pub struct VerilogArgs {
         default_value = "firtool",
         env = "FIRTOOL",
         value_hint = ValueHint::CommandName,
-        value_parser = OsStringValueParser::new().try_map(which::which)
+        value_parser = OsStringValueParser::new().try_map(which)
     )]
     pub firtool: PathBuf,
     #[arg(long)]
@@ -428,6 +428,13 @@ impl clap::Args for FormalAdjustArgs {
     }
 }
 
+fn which(v: std::ffi::OsString) -> which::Result<PathBuf> {
+    #[cfg(not(miri))]
+    return which::which(v);
+    #[cfg(miri)]
+    return Ok(Path::new("/").join(v));
+}
+
 #[derive(Parser, Clone)]
 #[non_exhaustive]
 pub struct FormalArgs {
@@ -438,7 +445,7 @@ pub struct FormalArgs {
         default_value = "sby",
         env = "SBY",
         value_hint = ValueHint::CommandName,
-        value_parser = OsStringValueParser::new().try_map(which::which)
+        value_parser = OsStringValueParser::new().try_map(which)
     )]
     pub sby: PathBuf,
     #[arg(long)]
@@ -653,21 +660,19 @@ impl FormalArgs {
                 self.sby.display()
             )))
         };
-        if do_cache {
-            fs::write(
-                cache_file,
-                serde_json::to_string_pretty(&FormalCache {
-                    version: FormalCacheVersion::CURRENT,
-                    contents_hash: contents_hash.unwrap(),
-                    stdout_stderr: captured_output,
-                    result: match &result {
-                        Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
-                        Err(error) => Err(error.to_string()),
-                    },
-                })
-                .expect("serialization shouldn't ever fail"),
-            )?;
-        }
+        fs::write(
+            cache_file,
+            serde_json::to_string_pretty(&FormalCache {
+                version: FormalCacheVersion::CURRENT,
+                contents_hash: contents_hash.unwrap(),
+                stdout_stderr: captured_output,
+                result: match &result {
+                    Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
+                    Err(error) => Err(error.to_string()),
+                },
+            })
+            .expect("serialization shouldn't ever fail"),
+        )?;
         result
     }
 }
diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs
index fe99653..f0623d4 100644
--- a/crates/fayalite/src/clock.rs
+++ b/crates/fayalite/src/clock.rs
@@ -4,10 +4,11 @@ use crate::{
     expr::{Expr, ToExpr},
     hdl,
     int::Bool,
-    reset::Reset,
+    reset::{Reset, ResetType},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
+use bitvec::slice::BitSlice;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
 pub struct Clock;
@@ -15,6 +16,7 @@ pub struct Clock;
 impl Type for Clock {
     type BaseType = Clock;
     type MaskType = Bool;
+    type SimValue = bool;
 
     impl_match_variant_as_self!();
 
@@ -36,6 +38,21 @@ impl Type for Clock {
         };
         retval
     }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), 1);
+        *value = bits[0];
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), 1);
+        bits.set(0, *value);
+    }
 }
 
 impl Clock {
@@ -88,9 +105,9 @@ impl ToClock for Expr<Clock> {
 }
 
 #[hdl]
-pub struct ClockDomain {
+pub struct ClockDomain<R: ResetType = Reset> {
     pub clk: Clock,
-    pub rst: Reset,
+    pub rst: R,
 }
 
 impl ToClock for bool {
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 2ed0b8e..36b5aa7 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -2,21 +2,30 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::VariantAccess, Expr, ToExpr},
+    expr::{
+        ops::{ExprPartialEq, VariantAccess},
+        Expr, ToExpr,
+    },
     hdl,
-    int::Bool,
+    int::{Bool, UIntValue},
     intern::{Intern, Interned},
     module::{
         connect, enum_match_variants_helper, incomplete_wire, wire,
         EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope,
     },
+    sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
-    ty::{CanonicalType, MatchVariantAndInactiveScope, StaticType, Type, TypeProperties},
+    ty::{
+        CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, StaticType, Type,
+        TypeProperties,
+    },
+    util::HashMap,
 };
-use hashbrown::HashMap;
-use std::{convert::Infallible, fmt, iter::FusedIterator};
+use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
+use serde::{Deserialize, Serialize};
+use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
 pub struct EnumVariant {
     pub name: Interned<str>,
     pub ty: Option<CanonicalType>,
@@ -149,6 +158,12 @@ impl EnumTypePropertiesBuilder {
             variant_count: variant_count + 1,
         }
     }
+    #[must_use]
+    pub fn variants(self, variants: impl IntoIterator<Item = EnumVariant>) -> Self {
+        variants.into_iter().fold(self, |this, variant| {
+            this.variant(variant.ty.map(CanonicalType::type_properties))
+        })
+    }
     pub const fn finish(self) -> TypeProperties {
         assert!(
             self.variant_count != 0,
@@ -178,7 +193,8 @@ impl Default for EnumTypePropertiesBuilder {
 impl Enum {
     #[track_caller]
     pub fn new(variants: Interned<[EnumVariant]>) -> Self {
-        let mut name_indexes = HashMap::with_capacity(variants.len());
+        let mut name_indexes =
+            HashMap::with_capacity_and_hasher(variants.len(), Default::default());
         let mut type_props_builder = EnumTypePropertiesBuilder::new();
         for (index, EnumVariant { name, ty }) in variants.iter().enumerate() {
             if let Some(old_index) = name_indexes.insert(*name, index) {
@@ -245,6 +261,7 @@ pub trait EnumType:
     MatchVariantsIter = EnumMatchVariantsIter<Self>,
 >
 {
+    type SimBuilder: From<Self>;
     fn variants(&self) -> Interned<[EnumVariant]>;
     fn match_activate_scope(
         v: Self::MatchVariantAndInactiveScope,
@@ -307,7 +324,18 @@ impl<T: EnumType> DoubleEndedIterator for EnumMatchVariantsIter<T> {
     }
 }
 
+pub struct NoBuilder {
+    _ty: Enum,
+}
+
+impl From<Enum> for NoBuilder {
+    fn from(_ty: Enum) -> Self {
+        Self { _ty }
+    }
+}
+
 impl EnumType for Enum {
+    type SimBuilder = NoBuilder;
     fn match_activate_scope(
         v: Self::MatchVariantAndInactiveScope,
     ) -> (Self::MatchVariant, Self::MatchActiveScope) {
@@ -322,6 +350,7 @@ impl EnumType for Enum {
 impl Type for Enum {
     type BaseType = Enum;
     type MaskType = Bool;
+    type SimValue = OpaqueSimValue;
     type MatchVariant = Option<Expr<CanonicalType>>;
     type MatchActiveScope = Scope;
     type MatchVariantAndInactiveScope = EnumMatchVariantAndInactiveScope<Self>;
@@ -352,6 +381,309 @@ impl Type for Enum {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        bits.copy_from_bitslice(value.bits().bits());
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct EnumPaddingSimValue {
+    bits: Option<UIntValue>,
+}
+
+impl EnumPaddingSimValue {
+    pub const fn new() -> Self {
+        Self { bits: None }
+    }
+    pub fn bit_width(&self) -> Option<usize> {
+        self.bits.as_ref().map(UIntValue::width)
+    }
+    pub fn bits(&self) -> &Option<UIntValue> {
+        &self.bits
+    }
+    pub fn bits_mut(&mut self) -> &mut Option<UIntValue> {
+        &mut self.bits
+    }
+    pub fn into_bits(self) -> Option<UIntValue> {
+        self.bits
+    }
+    pub fn from_bits(bits: Option<UIntValue>) -> Self {
+        Self { bits }
+    }
+    pub fn from_bitslice(v: &BitSlice) -> Self {
+        Self {
+            bits: Some(UIntValue::new(Arc::new(v.to_bitvec()))),
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub struct UnknownVariantSimValue {
+    discriminant: usize,
+    body_bits: UIntValue,
+}
+
+impl UnknownVariantSimValue {
+    pub fn discriminant(&self) -> usize {
+        self.discriminant
+    }
+    pub fn body_bits(&self) -> &UIntValue {
+        &self.body_bits
+    }
+    pub fn body_bits_mut(&mut self) -> &mut UIntValue {
+        &mut self.body_bits
+    }
+    pub fn into_body_bits(self) -> UIntValue {
+        self.body_bits
+    }
+    pub fn into_parts(self) -> (usize, UIntValue) {
+        (self.discriminant, self.body_bits)
+    }
+    pub fn new(discriminant: usize, body_bits: UIntValue) -> Self {
+        Self {
+            discriminant,
+            body_bits,
+        }
+    }
+}
+
+pub struct EnumSimValueFromBits<'a> {
+    variants: Interned<[EnumVariant]>,
+    discriminant: usize,
+    body_bits: &'a BitSlice,
+}
+
+impl<'a> EnumSimValueFromBits<'a> {
+    #[track_caller]
+    pub fn new<T: EnumType>(ty: T, bits: &'a BitSlice) -> Self {
+        let variants = ty.variants();
+        let bit_width = EnumTypePropertiesBuilder::new()
+            .variants(variants)
+            .finish()
+            .bit_width;
+        assert_eq!(bit_width, bits.len());
+        let (discriminant_bits, body_bits) =
+            bits.split_at(discriminant_bit_width_impl(variants.len()));
+        let mut discriminant = 0usize;
+        discriminant.view_bits_mut::<Lsb0>()[..discriminant_bits.len()]
+            .copy_from_bitslice(discriminant_bits);
+        Self {
+            variants,
+            discriminant,
+            body_bits,
+        }
+    }
+    pub fn discriminant(&self) -> usize {
+        self.discriminant
+    }
+    #[track_caller]
+    #[cold]
+    fn usage_error(&self, clone: bool) -> ! {
+        let clone = if clone { "clone_" } else { "" };
+        match self.variants.get(self.discriminant) {
+            None => {
+                panic!("should have called EnumSimValueFromBits::unknown_variant_{clone}from_bits");
+            }
+            Some(EnumVariant { ty: None, .. }) => {
+                panic!(
+                    "should have called EnumSimValueFromBits::variant_no_field_{clone}from_bits"
+                );
+            }
+            Some(EnumVariant { ty: Some(_), .. }) => {
+                panic!(
+                    "should have called EnumSimValueFromBits::variant_with_field_{clone}from_bits"
+                );
+            }
+        }
+    }
+    #[track_caller]
+    fn known_variant(&self, clone: bool) -> (Option<CanonicalType>, &'a BitSlice, &'a BitSlice) {
+        let Some(EnumVariant { ty, .. }) = self.variants.get(self.discriminant) else {
+            self.usage_error(clone);
+        };
+        let variant_bit_width = ty.map_or(0, CanonicalType::bit_width);
+        let (variant_bits, padding_bits) = self.body_bits.split_at(variant_bit_width);
+        (*ty, variant_bits, padding_bits)
+    }
+    #[track_caller]
+    pub fn unknown_variant_from_bits(self) -> UnknownVariantSimValue {
+        let None = self.variants.get(self.discriminant) else {
+            self.usage_error(false);
+        };
+        UnknownVariantSimValue::new(
+            self.discriminant,
+            UIntValue::new(Arc::new(self.body_bits.to_bitvec())),
+        )
+    }
+    #[track_caller]
+    pub fn unknown_variant_clone_from_bits(self, value: &mut UnknownVariantSimValue) {
+        let None = self.variants.get(self.discriminant) else {
+            self.usage_error(true);
+        };
+        value.discriminant = self.discriminant;
+        assert_eq!(value.body_bits.width(), self.body_bits.len());
+        value
+            .body_bits
+            .bits_mut()
+            .copy_from_bitslice(self.body_bits);
+    }
+    #[track_caller]
+    pub fn variant_no_field_from_bits(self) -> EnumPaddingSimValue {
+        let (None, _variant_bits, padding_bits) = self.known_variant(false) else {
+            self.usage_error(false);
+        };
+        EnumPaddingSimValue::from_bitslice(padding_bits)
+    }
+    #[track_caller]
+    pub fn variant_with_field_from_bits<T: Type>(self) -> (SimValue<T>, EnumPaddingSimValue) {
+        let (Some(variant_ty), variant_bits, padding_bits) = self.known_variant(false) else {
+            self.usage_error(false);
+        };
+        (
+            SimValue::from_bitslice(T::from_canonical(variant_ty), variant_bits),
+            EnumPaddingSimValue::from_bitslice(padding_bits),
+        )
+    }
+    #[track_caller]
+    fn clone_padding_from_bits(padding: &mut EnumPaddingSimValue, padding_bits: &BitSlice) {
+        match padding.bits_mut() {
+            None => *padding = EnumPaddingSimValue::from_bitslice(padding_bits),
+            Some(padding) => {
+                assert_eq!(padding.width(), padding_bits.len());
+                padding.bits_mut().copy_from_bitslice(padding_bits);
+            }
+        }
+    }
+    #[track_caller]
+    pub fn variant_no_field_clone_from_bits(self, padding: &mut EnumPaddingSimValue) {
+        let (None, _variant_bits, padding_bits) = self.known_variant(true) else {
+            self.usage_error(true);
+        };
+        Self::clone_padding_from_bits(padding, padding_bits);
+    }
+    #[track_caller]
+    pub fn variant_with_field_clone_from_bits<T: Type>(
+        self,
+        value: &mut SimValue<T>,
+        padding: &mut EnumPaddingSimValue,
+    ) {
+        let (Some(variant_ty), variant_bits, padding_bits) = self.known_variant(true) else {
+            self.usage_error(true);
+        };
+        assert_eq!(SimValue::ty(value), T::from_canonical(variant_ty));
+        SimValue::bits_mut(value)
+            .bits_mut()
+            .copy_from_bitslice(variant_bits);
+        Self::clone_padding_from_bits(padding, padding_bits);
+    }
+}
+
+pub struct EnumSimValueToBits<'a> {
+    variants: Interned<[EnumVariant]>,
+    bit_width: usize,
+    discriminant_bit_width: usize,
+    bits: &'a mut BitSlice,
+}
+
+impl<'a> EnumSimValueToBits<'a> {
+    #[track_caller]
+    pub fn new<T: EnumType>(ty: T, bits: &'a mut BitSlice) -> Self {
+        let variants = ty.variants();
+        let bit_width = EnumTypePropertiesBuilder::new()
+            .variants(variants)
+            .finish()
+            .bit_width;
+        assert_eq!(bit_width, bits.len());
+        Self {
+            variants,
+            bit_width,
+            discriminant_bit_width: discriminant_bit_width_impl(variants.len()),
+            bits,
+        }
+    }
+    #[track_caller]
+    fn discriminant_to_bits(&mut self, mut discriminant: usize) {
+        let orig_discriminant = discriminant;
+        let discriminant_bits =
+            &mut discriminant.view_bits_mut::<Lsb0>()[..self.discriminant_bit_width];
+        self.bits[..self.discriminant_bit_width].copy_from_bitslice(discriminant_bits);
+        discriminant_bits.fill(false);
+        assert!(
+            discriminant == 0,
+            "{orig_discriminant:#x} is too big to fit in enum discriminant bits",
+        );
+    }
+    #[track_caller]
+    pub fn unknown_variant_to_bits(mut self, value: &UnknownVariantSimValue) {
+        self.discriminant_to_bits(value.discriminant);
+        let None = self.variants.get(value.discriminant) else {
+            panic!("can't use UnknownVariantSimValue to set known discriminant");
+        };
+        assert_eq!(
+            self.bit_width - self.discriminant_bit_width,
+            value.body_bits.width()
+        );
+        self.bits[self.discriminant_bit_width..].copy_from_bitslice(value.body_bits.bits());
+    }
+    #[track_caller]
+    fn known_variant(
+        mut self,
+        discriminant: usize,
+        padding: &EnumPaddingSimValue,
+    ) -> (Option<CanonicalType>, &'a mut BitSlice) {
+        self.discriminant_to_bits(discriminant);
+        let variant_ty = self.variants[discriminant].ty;
+        let variant_bit_width = variant_ty.map_or(0, CanonicalType::bit_width);
+        let padding_bits = &mut self.bits[self.discriminant_bit_width..][variant_bit_width..];
+        if let Some(padding) = padding.bits() {
+            assert_eq!(padding.width(), padding_bits.len());
+            padding_bits.copy_from_bitslice(padding.bits());
+        } else {
+            padding_bits.fill(false);
+        }
+        let variant_bits = &mut self.bits[self.discriminant_bit_width..][..variant_bit_width];
+        (variant_ty, variant_bits)
+    }
+    #[track_caller]
+    pub fn variant_no_field_to_bits(self, discriminant: usize, padding: &EnumPaddingSimValue) {
+        let (None, _variant_bits) = self.known_variant(discriminant, padding) else {
+            panic!("expected variant to have no field");
+        };
+    }
+    #[track_caller]
+    pub fn variant_with_field_to_bits<T: Type>(
+        self,
+        discriminant: usize,
+        value: &SimValue<T>,
+        padding: &EnumPaddingSimValue,
+    ) {
+        let (Some(variant_ty), variant_bits) = self.known_variant(discriminant, padding) else {
+            panic!("expected variant to have a field");
+        };
+        assert_eq!(SimValue::ty(value), T::from_canonical(variant_ty));
+        variant_bits.copy_from_bitslice(SimValue::bits(value).bits());
+    }
+}
+
+#[doc(hidden)]
+pub fn assert_is_enum_type<T: EnumType>(v: T) -> T {
+    v
+}
+
+#[doc(hidden)]
+pub fn enum_type_to_sim_builder<T: EnumType>(v: T) -> T::SimBuilder {
+    v.into()
 }
 
 #[hdl]
@@ -360,6 +692,79 @@ pub enum HdlOption<T: Type> {
     HdlSome(T),
 }
 
+impl<Lhs: Type + ExprPartialEq<Rhs>, Rhs: Type> ExprPartialEq<HdlOption<Rhs>> for HdlOption<Lhs> {
+    #[hdl]
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_eq = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_eq, ExprPartialEq::cmp_eq(lhs, rhs)),
+                    HdlNone => connect(cmp_eq, false),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_eq, false),
+                    HdlNone => connect(cmp_eq, true),
+                }
+            }
+        }
+        cmp_eq
+    }
+
+    #[hdl]
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_ne = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_ne, ExprPartialEq::cmp_ne(lhs, rhs)),
+                    HdlNone => connect(cmp_ne, true),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_ne, true),
+                    HdlNone => connect(cmp_ne, false),
+                }
+            }
+        }
+        cmp_ne
+    }
+}
+
+impl<Lhs: SimValuePartialEq<Rhs>, Rhs: Type> SimValuePartialEq<HdlOption<Rhs>> for HdlOption<Lhs> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<HdlOption<Rhs>>) -> bool {
+        type SimValueMatch<T> = <T as Type>::SimValue;
+        match (&**this, &**other) {
+            (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_)) => {
+                true
+            }
+            (SimValueMatch::<Self>::HdlSome(..), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_))
+            | (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlSome(..)) => {
+                false
+            }
+            (
+                SimValueMatch::<Self>::HdlSome(l, _),
+                SimValueMatch::<HdlOption<Rhs>>::HdlSome(r, _),
+            ) => l == r,
+        }
+    }
+}
+
 #[allow(non_snake_case)]
 pub fn HdlNone<T: StaticType>() -> Expr<HdlOption<T>> {
     HdlOption[T::TYPE].HdlNone()
diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index fa50852..e070674 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -16,7 +16,9 @@ use crate::{
         transform::visit::{Fold, Folder, Visit, Visitor},
         Instance, ModuleIO,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     ty::{CanonicalType, StaticType, Type, TypeWithDeref},
     wire::Wire,
 };
@@ -108,6 +110,7 @@ expr_enum! {
         UIntLiteral(Interned<UIntValue>),
         SIntLiteral(Interned<SIntValue>),
         BoolLiteral(bool),
+        PhantomConst(PhantomConst),
         BundleLiteral(ops::BundleLiteral),
         ArrayLiteral(ops::ArrayLiteral<CanonicalType, DynSize>),
         EnumLiteral(ops::EnumLiteral),
@@ -209,7 +212,9 @@ expr_enum! {
         ModuleIO(ModuleIO<CanonicalType>),
         Instance(Instance<Bundle>),
         Wire(Wire<CanonicalType>),
-        Reg(Reg<CanonicalType>),
+        Reg(Reg<CanonicalType, Reset>),
+        RegSync(Reg<CanonicalType, SyncReset>),
+        RegAsync(Reg<CanonicalType, AsyncReset>),
         MemPort(MemPort<DynPortType>),
     }
 }
@@ -269,6 +274,17 @@ pub struct Expr<T: Type> {
 
 impl<T: Type + fmt::Debug> fmt::Debug for Expr<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        #[cfg(debug_assertions)]
+        {
+            let Self {
+                __enum,
+                __ty,
+                __flow,
+            } = self;
+            let expr_ty = __ty.canonical();
+            let enum_ty = __enum.to_expr().__ty;
+            assert_eq!(expr_ty, enum_ty, "expr ty mismatch:\nExpr {{\n__enum: {__enum:?},\n__ty: {__ty:?},\n__flow: {__flow:?}\n}}");
+        }
         self.__enum.fmt(f)
     }
 }
@@ -593,25 +609,42 @@ impl<T: Type> GetTarget for Wire<T> {
     }
 }
 
-impl<T: Type> ToExpr for Reg<T> {
+impl<T: Type, R: ResetType> ToExpr for Reg<T, R> {
     type Type = T;
 
     fn to_expr(&self) -> Expr<Self::Type> {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = ExprEnum;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                ExprEnum::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                ExprEnum::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                ExprEnum::RegAsync(input)
+            }
+        }
         Expr {
-            __enum: ExprEnum::Reg(self.canonical()).intern_sized(),
+            __enum: R::dispatch(self.canonical(), Dispatch).intern_sized(),
             __ty: self.ty(),
             __flow: self.flow(),
         }
     }
 }
 
-impl<T: Type> ToLiteralBits for Reg<T> {
+impl<T: Type, R: ResetType> ToLiteralBits for Reg<T, R> {
     fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
         Err(NotALiteralExpr)
     }
 }
 
-impl<T: Type> GetTarget for Reg<T> {
+impl<T: Type, R: ResetType> GetTarget for Reg<T, R> {
     fn target(&self) -> Option<Interned<Target>> {
         Some(Intern::intern_sized(self.canonical().into()))
     }
@@ -678,6 +711,7 @@ impl<T: ToExpr + ?Sized> CastToBits for T {
 }
 
 pub trait CastBitsTo {
+    #[track_caller]
     fn cast_bits_to<T: Type>(&self, ty: T) -> Expr<T>;
 }
 
@@ -735,3 +769,27 @@ pub fn repeat<T: Type, L: SizeType>(
     )
     .to_expr()
 }
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> ToExpr for PhantomConst<T> {
+    type Type = Self;
+
+    fn to_expr(&self) -> Expr<Self::Type> {
+        Expr {
+            __enum: ExprEnum::PhantomConst(self.canonical_phantom_const()).intern_sized(),
+            __ty: *self,
+            __flow: Flow::Source,
+        }
+    }
+}
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> GetTarget for PhantomConst<T> {
+    fn target(&self) -> Option<Interned<Target>> {
+        None
+    }
+}
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> ToLiteralBits for PhantomConst<T> {
+    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
+        Ok(Interned::default())
+    }
+}
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 3579641..e794a68 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -11,15 +11,19 @@ use crate::{
             GetTarget, Target, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
         },
-        CastTo, Expr, ExprEnum, Flow, HdlPartialEq, HdlPartialOrd, NotALiteralExpr, ReduceBits,
-        ToExpr, ToLiteralBits,
+        CastBitsTo as _, CastTo, CastToBits as _, Expr, ExprEnum, Flow, HdlPartialEq,
+        HdlPartialOrd, NotALiteralExpr, ReduceBits, ToExpr, ToLiteralBits,
     },
     int::{
         Bool, BoolOrIntType, DynSize, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt,
         UIntType, UIntValue,
     },
     intern::{Intern, Interned},
-    reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
+    phantom_const::{PhantomConst, PhantomConstValue},
+    reset::{
+        AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset, ToAsyncReset, ToReset,
+        ToSyncReset,
+    },
     ty::{CanonicalType, StaticType, Type},
     util::ConstUsize,
 };
@@ -262,7 +266,7 @@ impl Neg {
         };
         let result_ty = retval.ty();
         retval.literal_bits = arg.to_literal_bits().map(|bits| {
-            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(-SInt::bits_to_bigint(&bits)))
+            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(&-SInt::bits_to_bigint(&bits)))
         });
         retval
     }
@@ -369,7 +373,7 @@ fn binary_op_literal_bits<ResultTy: BoolOrIntType, Lhs: BoolOrIntType, Rhs: Bool
     let rhs = Rhs::bits_to_bigint(&rhs);
     let result = f(lhs, rhs)?;
     Ok(Intern::intern_owned(
-        result_ty.bits_from_bigint_wrapping(result),
+        result_ty.bits_from_bigint_wrapping(&result),
     ))
 }
 
@@ -1344,7 +1348,7 @@ macro_rules! binary_op_fixed_shift {
                     literal_bits: Err(NotALiteralExpr),
                 };
                 retval.literal_bits = lhs.to_literal_bits().map(|bits| {
-                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping($Trait::$method(
+                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping(&$Trait::$method(
                         $ty::bits_to_bigint(&bits),
                         rhs,
                     )))
@@ -1621,7 +1625,7 @@ macro_rules! impl_cast_int_op {
                     ty,
                     literal_bits: arg.to_literal_bits().map(|bits| {
                         Intern::intern_owned(
-                            ty.bits_from_bigint_wrapping($from::bits_to_bigint(&bits)),
+                            ty.bits_from_bigint_wrapping(&$from::bits_to_bigint(&bits)),
                         )
                     }),
                 }
@@ -1773,11 +1777,11 @@ impl_cast_bit_op!(CastSIntToAsyncReset, SInt<1>, #[dyn] SInt, AsyncReset, #[trai
 impl_cast_bit_op!(CastSyncResetToBool, SyncReset, Bool);
 impl_cast_bit_op!(CastSyncResetToUInt, SyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastSyncResetToSInt, SyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset, #[trait] ToReset::to_reset);
+impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset);
 impl_cast_bit_op!(CastAsyncResetToBool, AsyncReset, Bool);
 impl_cast_bit_op!(CastAsyncResetToUInt, AsyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastAsyncResetToSInt, AsyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset, #[trait] ToReset::to_reset);
+impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset);
 impl_cast_bit_op!(CastResetToBool, Reset, Bool);
 impl_cast_bit_op!(CastResetToUInt, Reset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastResetToSInt, Reset, SInt<1>, #[dyn] SInt);
@@ -1788,6 +1792,127 @@ impl_cast_bit_op!(CastClockToBool, Clock, Bool);
 impl_cast_bit_op!(CastClockToUInt, Clock, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastClockToSInt, Clock, SInt<1>, #[dyn] SInt);
 
+impl<T: ResetType> ToReset for Expr<T> {
+    fn to_reset(&self) -> Expr<Reset> {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Expr<T>;
+            type Output<T: ResetType> = Expr<Reset>;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                input
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                input.cast_to_static()
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                input.cast_to_static()
+            }
+        }
+        T::dispatch(*self, Dispatch)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for AsyncReset {
+    fn cast_to(src: Expr<Self>, _to_type: AsyncReset) -> Expr<AsyncReset> {
+        src
+    }
+}
+
+impl ExprCastTo<SyncReset> for AsyncReset {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Clock> for AsyncReset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for SyncReset {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for SyncReset {
+    fn cast_to(src: Expr<Self>, _to_type: SyncReset) -> Expr<SyncReset> {
+        src
+    }
+}
+
+impl ExprCastTo<Clock> for SyncReset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Reset> for Reset {
+    fn cast_to(src: Expr<Self>, _to_type: Reset) -> Expr<Reset> {
+        src
+    }
+}
+
+impl ExprCastTo<Clock> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for Clock {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for Clock {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Clock> for Clock {
+    fn cast_to(src: Expr<Self>, _to_type: Clock) -> Expr<Clock> {
+        src
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprCastTo<()> for PhantomConst<T> {
+    fn cast_to(src: Expr<Self>, to_type: ()) -> Expr<()> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprCastTo<PhantomConst<T>> for () {
+    fn cast_to(src: Expr<Self>, to_type: PhantomConst<T>) -> Expr<PhantomConst<T>> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue, U: ?Sized + PhantomConstValue> ExprCastTo<PhantomConst<T>>
+    for PhantomConst<U>
+{
+    fn cast_to(src: Expr<Self>, to_type: PhantomConst<T>) -> Expr<PhantomConst<T>> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct FieldAccess<FieldType: Type = CanonicalType> {
     base: Expr<Bundle>,
@@ -2604,3 +2729,47 @@ impl<T: Type> ToExpr for Uninit<T> {
         }
     }
 }
+
+pub trait ExprIntoIterator: Type {
+    type Item: Type;
+    type ExprIntoIter: Iterator<Item = Expr<Self::Item>>;
+
+    fn expr_into_iter(e: Expr<Self>) -> Self::ExprIntoIter;
+}
+
+impl<T: ExprIntoIterator> IntoIterator for Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(self)
+    }
+}
+
+impl<T: ExprIntoIterator> IntoIterator for &'_ Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(*self)
+    }
+}
+
+impl<T: ExprIntoIterator> IntoIterator for &'_ mut Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(*self)
+    }
+}
+
+pub trait ExprFromIterator<A>: Type {
+    fn expr_from_iter<T: IntoIterator<Item = A>>(iter: T) -> Expr<Self>;
+}
+
+impl<This: ExprFromIterator<A>, A> FromIterator<A> for Expr<This> {
+    fn from_iter<T: IntoIterator<Item = A>>(iter: T) -> Self {
+        This::expr_from_iter(iter)
+    }
+}
diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index 0f85f62..c8c55e9 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -3,18 +3,19 @@
 use crate::{
     array::Array,
     bundle::{Bundle, BundleField},
-    expr::Flow,
+    expr::{Expr, Flow, ToExpr},
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort},
     module::{Instance, ModuleIO, TargetName},
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
 };
 use std::fmt;
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathBundleField {
     pub name: Interned<str>,
 }
@@ -25,7 +26,7 @@ impl fmt::Display for TargetPathBundleField {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathArrayElement {
     pub index: usize,
 }
@@ -36,7 +37,7 @@ impl fmt::Display for TargetPathArrayElement {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathDynArrayElement {}
 
 impl fmt::Display for TargetPathDynArrayElement {
@@ -45,7 +46,7 @@ impl fmt::Display for TargetPathDynArrayElement {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub enum TargetPathElement {
     BundleField(TargetPathBundleField),
     ArrayElement(TargetPathArrayElement),
@@ -127,6 +128,7 @@ macro_rules! impl_target_base {
         $(#[$enum_meta:meta])*
         $enum_vis:vis enum $TargetBase:ident {
             $(
+                $(#[from = $from:ident])?
                 #[is = $is_fn:ident]
                 #[to = $to_fn:ident]
                 $(#[$variant_meta:meta])*
@@ -150,19 +152,19 @@ macro_rules! impl_target_base {
             }
         }
 
-        $(
+        $($(
         impl From<$VariantTy> for $TargetBase {
-            fn from(value: $VariantTy) -> Self {
+            fn $from(value: $VariantTy) -> Self {
                 Self::$Variant(value)
             }
         }
 
         impl From<$VariantTy> for Target {
-            fn from(value: $VariantTy) -> Self {
+            fn $from(value: $VariantTy) -> Self {
                 $TargetBase::$Variant(value).into()
             }
         }
-        )*
+        )*)?
 
         impl $TargetBase {
             $(
@@ -193,30 +195,79 @@ macro_rules! impl_target_base {
                 }
             }
         }
+
+        impl ToExpr for $TargetBase {
+            type Type = CanonicalType;
+
+            fn to_expr(&self) -> Expr<Self::Type> {
+                match self {
+                    $(Self::$Variant(v) => Expr::canonical(v.to_expr()),)*
+                }
+            }
+        }
     };
 }
 
 impl_target_base! {
-    #[derive(Clone, PartialEq, Eq, Hash)]
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
     pub enum TargetBase {
+        #[from = from]
         #[is = is_module_io]
         #[to = module_io]
         ModuleIO(ModuleIO<CanonicalType>),
+        #[from = from]
         #[is = is_mem_port]
         #[to = mem_port]
         MemPort(MemPort<DynPortType>),
         #[is = is_reg]
         #[to = reg]
-        Reg(Reg<CanonicalType>),
+        Reg(Reg<CanonicalType, Reset>),
+        #[is = is_reg_sync]
+        #[to = reg_sync]
+        RegSync(Reg<CanonicalType, SyncReset>),
+        #[is = is_reg_async]
+        #[to = reg_async]
+        RegAsync(Reg<CanonicalType, AsyncReset>),
+        #[from = from]
         #[is = is_wire]
         #[to = wire]
         Wire(Wire<CanonicalType>),
+        #[from = from]
         #[is = is_instance]
         #[to = instance]
         Instance(Instance<Bundle>),
     }
 }
 
+impl<R: ResetType> From<Reg<CanonicalType, R>> for TargetBase {
+    fn from(value: Reg<CanonicalType, R>) -> Self {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = TargetBase;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                TargetBase::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                TargetBase::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                TargetBase::RegAsync(input)
+            }
+        }
+        R::dispatch(value, Dispatch)
+    }
+}
+
+impl<R: ResetType> From<Reg<CanonicalType, R>> for Target {
+    fn from(value: Reg<CanonicalType, R>) -> Self {
+        TargetBase::from(value).into()
+    }
+}
+
 impl fmt::Display for TargetBase {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         write!(f, "{:?}", self.target_name())
@@ -229,6 +280,8 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => TargetName(v.scoped_name(), None),
             TargetBase::MemPort(v) => TargetName(v.mem_name(), Some(v.port_name())),
             TargetBase::Reg(v) => TargetName(v.scoped_name(), None),
+            TargetBase::RegSync(v) => TargetName(v.scoped_name(), None),
+            TargetBase::RegAsync(v) => TargetName(v.scoped_name(), None),
             TargetBase::Wire(v) => TargetName(v.scoped_name(), None),
             TargetBase::Instance(v) => TargetName(v.scoped_name(), None),
         }
@@ -238,6 +291,8 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => v.ty(),
             TargetBase::MemPort(v) => v.ty().canonical(),
             TargetBase::Reg(v) => v.ty(),
+            TargetBase::RegSync(v) => v.ty(),
+            TargetBase::RegAsync(v) => v.ty(),
             TargetBase::Wire(v) => v.ty(),
             TargetBase::Instance(v) => v.ty().canonical(),
         }
@@ -313,7 +368,7 @@ impl TargetChild {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub enum Target {
     Base(Interned<TargetBase>),
     Child(TargetChild),
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index bc75ccc..d33c7a9 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -15,7 +15,7 @@ use crate::{
         target::{
             Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement,
         },
-        Expr, ExprEnum,
+        CastBitsTo, Expr, ExprEnum,
     },
     formal::FormalKind,
     int::{Bool, DynSize, IntType, SIntValue, UInt, UIntValue},
@@ -31,17 +31,16 @@ use crate::{
         StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
         StmtWire,
     },
-    reset::{AsyncReset, Reset, SyncReset},
+    reset::{AsyncReset, Reset, ResetType, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::{
         const_str_array_is_strictly_ascending, BitSliceWriteWithBase, DebugAsRawString,
-        GenericConstBool,
+        GenericConstBool, HashMap, HashSet,
     },
 };
 use bitvec::slice::BitSlice;
 use clap::value_parser;
-use hashbrown::{HashMap, HashSet};
 use num_traits::Signed;
 use serde::Serialize;
 use std::{
@@ -447,6 +446,7 @@ impl TypeState {
             CanonicalType::AsyncReset(AsyncReset {}) => "AsyncReset".into(),
             CanonicalType::SyncReset(SyncReset {}) => "UInt<1>".into(),
             CanonicalType::Reset(Reset {}) => "Reset".into(),
+            CanonicalType::PhantomConst(_) => "{}".into(),
         }
     }
 }
@@ -1152,6 +1152,7 @@ impl<'a> Exporter<'a> {
             | CanonicalType::Clock(_)
             | CanonicalType::AsyncReset(_)
             | CanonicalType::Reset(_) => format!("asUInt({value_str})"),
+            CanonicalType::PhantomConst(_) => "UInt<0>(0)".into(),
         }
     }
     fn expr_cast_bits_to_bundle(
@@ -1357,6 +1358,12 @@ impl<'a> Exporter<'a> {
             CanonicalType::AsyncReset(_) => format!("asAsyncReset({value_str})"),
             CanonicalType::SyncReset(_) => value_str,
             CanonicalType::Reset(_) => unreachable!("Reset is not bit castable to"),
+            CanonicalType::PhantomConst(_) => {
+                let retval = self.module.ns.make_new("_cast_bits_to_phantom_const_expr");
+                definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {{}}"));
+                definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}"));
+                return retval.to_string();
+            }
         }
     }
     fn expr_unary<T: Type>(
@@ -1395,6 +1402,11 @@ impl<'a> Exporter<'a> {
             ExprEnum::UIntLiteral(literal) => self.uint_literal(&literal),
             ExprEnum::SIntLiteral(literal) => self.sint_literal(&literal),
             ExprEnum::BoolLiteral(literal) => self.bool_literal(literal),
+            ExprEnum::PhantomConst(ty) => self.expr(
+                UInt[0].zero().cast_bits_to(ty.canonical()),
+                definitions,
+                const_ty,
+            ),
             ExprEnum::ArrayLiteral(array_literal) => {
                 self.array_literal_expr(array_literal, definitions, const_ty)
             }
@@ -1739,6 +1751,14 @@ impl<'a> Exporter<'a> {
                 assert!(!const_ty, "not a constant");
                 self.module.ns.get(expr.scoped_name().1).to_string()
             }
+            ExprEnum::RegSync(expr) => {
+                assert!(!const_ty, "not a constant");
+                self.module.ns.get(expr.scoped_name().1).to_string()
+            }
+            ExprEnum::RegAsync(expr) => {
+                assert!(!const_ty, "not a constant");
+                self.module.ns.get(expr.scoped_name().1).to_string()
+            }
             ExprEnum::MemPort(expr) => {
                 assert!(!const_ty, "not a constant");
                 let mem_name = self.module.ns.get(expr.mem_name().1);
@@ -1848,6 +1868,8 @@ impl<'a> Exporter<'a> {
                         self.module.ns.get(v.mem_name().1)
                     }
                     TargetBase::Reg(v) => self.module.ns.get(v.name_id()),
+                    TargetBase::RegSync(v) => self.module.ns.get(v.name_id()),
+                    TargetBase::RegAsync(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Wire(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Instance(v) => self.module.ns.get(v.name_id()),
                 };
@@ -1956,6 +1978,37 @@ impl<'a> Exporter<'a> {
         drop(memory_indent);
         Ok(body)
     }
+    fn stmt_reg<R: ResetType>(
+        &mut self,
+        stmt_reg: StmtReg<R>,
+        module_name: Ident,
+        definitions: &RcDefinitions,
+        body: &mut String,
+    ) {
+        let StmtReg { annotations, reg } = stmt_reg;
+        let indent = self.indent;
+        self.targeted_annotations(module_name, vec![], &annotations);
+        let name = self.module.ns.get(reg.name_id());
+        let ty = self.type_state.ty(reg.ty());
+        let clk = self.expr(Expr::canonical(reg.clock_domain().clk), definitions, false);
+        if let Some(init) = reg.init() {
+            let rst = self.expr(Expr::canonical(reg.clock_domain().rst), definitions, false);
+            let init = self.expr(init, definitions, false);
+            writeln!(
+                body,
+                "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
+                FileInfo::new(reg.source_location()),
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                body,
+                "{indent}reg {name}: {ty}, {clk}{}",
+                FileInfo::new(reg.source_location()),
+            )
+            .unwrap();
+        }
+    }
     fn block(
         &mut self,
         module: Interned<Module<Bundle>>,
@@ -2126,30 +2179,14 @@ impl<'a> Exporter<'a> {
                     )
                     .unwrap();
                 }
-                Stmt::Declaration(StmtDeclaration::Reg(StmtReg { annotations, reg })) => {
-                    self.targeted_annotations(module_name, vec![], &annotations);
-                    let name = self.module.ns.get(reg.name_id());
-                    let ty = self.type_state.ty(reg.ty());
-                    let clk =
-                        self.expr(Expr::canonical(reg.clock_domain().clk), &definitions, false);
-                    if let Some(init) = reg.init() {
-                        let rst =
-                            self.expr(Expr::canonical(reg.clock_domain().rst), &definitions, false);
-                        let init = self.expr(init, &definitions, false);
-                        writeln!(
-                            body,
-                            "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
-                            FileInfo::new(reg.source_location()),
-                        )
-                        .unwrap();
-                    } else {
-                        writeln!(
-                            body,
-                            "{indent}reg {name}: {ty}, {clk}{}",
-                            FileInfo::new(reg.source_location()),
-                        )
-                        .unwrap();
-                    }
+                Stmt::Declaration(StmtDeclaration::Reg(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                }
+                Stmt::Declaration(StmtDeclaration::RegSync(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                }
+                Stmt::Declaration(StmtDeclaration::RegAsync(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
                 }
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations,
@@ -2220,6 +2257,7 @@ impl<'a> Exporter<'a> {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name,
                 parameters,
+                simulation: _,
             }) => {
                 let verilog_name = Ident(verilog_name);
                 writeln!(body, "{indent}defname = {verilog_name}").unwrap();
@@ -2583,7 +2621,7 @@ fn export_impl(
             indent_depth: &indent_depth,
             indent: "    ",
         },
-        seen_modules: HashSet::new(),
+        seen_modules: HashSet::default(),
         unwritten_modules: VecDeque::new(),
         global_ns,
         module: ModuleState::default(),
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 03b2c88..d8364b1 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -2,27 +2,52 @@
 // See Notices.txt for copyright information
 
 use crate::{
+    array::ArrayType,
     expr::{
         target::{GetTarget, Target},
         Expr, NotALiteralExpr, ToExpr, ToLiteralBits,
     },
+    hdl,
     intern::{Intern, Interned, Memoize},
+    sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
     util::{interned_bit, ConstBool, ConstUsize, GenericConstBool, GenericConstUsize},
 };
-use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec};
+use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use num_bigint::{BigInt, BigUint, Sign};
-use num_traits::{Signed, Zero};
+use num_traits::{One, Signed, Zero};
+use serde::{
+    de::{DeserializeOwned, Error, Visitor},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{
     borrow::{BorrowMut, Cow},
     fmt,
     marker::PhantomData,
     num::NonZero,
     ops::{Bound, Index, Not, Range, RangeBounds, RangeInclusive},
+    str::FromStr,
     sync::Arc,
 };
 
+mod uint_in_range;
+
+#[hdl]
+pub type UIntInRangeType<Start: Size, End: Size> = uint_in_range::UIntInRangeType<Start, End>;
+
+#[hdl]
+pub type UIntInRange<const START: usize, const END: usize> =
+    UIntInRangeType<ConstUsize<START>, ConstUsize<END>>;
+
+#[hdl]
+pub type UIntInRangeInclusiveType<Start: Size, End: Size> =
+    uint_in_range::UIntInRangeInclusiveType<Start, End>;
+
+#[hdl]
+pub type UIntInRangeInclusive<const START: usize, const END: usize> =
+    UIntInRangeInclusiveType<ConstUsize<START>, ConstUsize<END>>;
+
 mod sealed {
     pub trait BoolOrIntTypeSealed {}
     pub trait SizeSealed {}
@@ -49,6 +74,16 @@ pub trait KnownSize:
         + IntoIterator<Item = Expr<Element>>
         + TryFrom<Vec<Expr<Element>>>
         + Into<Vec<Expr<Element>>>;
+    type ArraySimValue<Element: Type>: AsRef<[SimValue<Element>]>
+        + AsMut<[SimValue<Element>]>
+        + BorrowMut<[SimValue<Element>]>
+        + 'static
+        + Clone
+        + std::fmt::Debug
+        + IntoIterator<Item = SimValue<Element>>
+        + TryFrom<Vec<SimValue<Element>>>
+        + Into<Vec<SimValue<Element>>>
+        + ToSimValueWithType<ArrayType<Element, Self>>;
 }
 
 macro_rules! known_widths {
@@ -60,6 +95,7 @@ macro_rules! known_widths {
         }> {
             const SIZE: Self = Self;
             type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
+            type ArraySimValue<Element: Type> = [SimValue<Element>; Self::VALUE];
         }
     };
     ([2 $($rest:tt)*] $($bits:literal)+) => {
@@ -72,6 +108,7 @@ macro_rules! known_widths {
         impl KnownSize for ConstUsize<{2 $(* $rest)*}> {
             const SIZE: Self = Self;
             type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
+            type ArraySimValue<Element: Type> = [SimValue<Element>; Self::VALUE];
         }
     };
 }
@@ -79,13 +116,31 @@ macro_rules! known_widths {
 known_widths!([2 2 2 2 2 2 2 2 2]);
 
 pub trait SizeType:
-    sealed::SizeTypeSealed + Copy + Ord + std::hash::Hash + std::fmt::Debug + Send + Sync + 'static
+    sealed::SizeTypeSealed
+    + Copy
+    + Ord
+    + std::hash::Hash
+    + std::fmt::Debug
+    + Send
+    + Sync
+    + 'static
+    + Serialize
+    + DeserializeOwned
 {
     type Size: Size<SizeType = Self>;
 }
 
 pub trait Size:
-    sealed::SizeSealed + Copy + Ord + std::hash::Hash + std::fmt::Debug + Send + Sync + 'static
+    sealed::SizeSealed
+    + Copy
+    + Ord
+    + std::hash::Hash
+    + std::fmt::Debug
+    + Send
+    + Sync
+    + 'static
+    + Serialize
+    + DeserializeOwned
 {
     type ArrayMatch<Element: Type>: AsRef<[Expr<Element>]>
         + AsMut<[Expr<Element>]>
@@ -100,6 +155,16 @@ pub trait Size:
         + IntoIterator<Item = Expr<Element>>
         + TryFrom<Vec<Expr<Element>>>
         + Into<Vec<Expr<Element>>>;
+    type ArraySimValue<Element: Type>: AsRef<[SimValue<Element>]>
+        + AsMut<[SimValue<Element>]>
+        + BorrowMut<[SimValue<Element>]>
+        + 'static
+        + Clone
+        + std::fmt::Debug
+        + IntoIterator<Item = SimValue<Element>>
+        + TryFrom<Vec<SimValue<Element>>>
+        + Into<Vec<SimValue<Element>>>
+        + ToSimValueWithType<ArrayType<Element, Self>>;
     const KNOWN_VALUE: Option<usize>;
     type SizeType: SizeType<Size = Self>
         + Copy
@@ -125,6 +190,7 @@ impl SizeType for usize {
 
 impl Size for DynSize {
     type ArrayMatch<Element: Type> = Box<[Expr<Element>]>;
+    type ArraySimValue<Element: Type> = Box<[SimValue<Element>]>;
     const KNOWN_VALUE: Option<usize> = None;
     type SizeType = usize;
 
@@ -147,6 +213,7 @@ impl<T: KnownSize> SizeType for T {
 
 impl<T: KnownSize> Size for T {
     type ArrayMatch<Element: Type> = <T as KnownSize>::ArrayMatch<Element>;
+    type ArraySimValue<Element: Type> = <T as KnownSize>::ArraySimValue<Element>;
 
     const KNOWN_VALUE: Option<usize> = Some(T::VALUE);
 
@@ -165,6 +232,305 @@ impl<T: KnownSize> Size for T {
     }
 }
 
+#[derive(Clone, PartialEq, Eq, Debug)]
+pub enum ParseIntValueError {
+    Empty,
+    InvalidDigit,
+    MissingDigits,
+    InvalidRadix,
+    MissingType,
+    InvalidType,
+    TypeMismatch {
+        parsed_signed: bool,
+        parsed_width: usize,
+        expected_signed: bool,
+        expected_width: usize,
+    },
+    PosOverflow,
+    NegOverflow,
+    WidthOverflow,
+    MissingWidth,
+}
+
+impl std::error::Error for ParseIntValueError {}
+
+impl fmt::Display for ParseIntValueError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(match self {
+            Self::Empty => "can't parse integer from empty string",
+            Self::InvalidDigit => "invalid digit",
+            Self::MissingDigits => "missing digits",
+            Self::InvalidRadix => "invalid radix",
+            Self::MissingType => "missing type",
+            Self::InvalidType => "invalid type",
+            Self::TypeMismatch {
+                parsed_signed,
+                parsed_width,
+                expected_signed,
+                expected_width,
+            } => {
+                return write!(
+                    f,
+                    "type mismatch: parsed type {parsed_signed_str}{parsed_width}, \
+                    expected type {expected_signed_str}{expected_width}",
+                    parsed_signed_str = if *parsed_signed { "i" } else { "u" },
+                    expected_signed_str = if *expected_signed { "i" } else { "u" },
+                );
+            }
+            Self::PosOverflow => "value too large to fit in type",
+            Self::NegOverflow => "value too small to fit in type",
+            Self::WidthOverflow => "width is too large",
+            Self::MissingWidth => "missing width",
+        })
+    }
+}
+
+fn parse_int_value(
+    s: &str,
+    type_is_signed: bool,
+    type_width: Option<usize>,
+    parse_type: bool,
+) -> Result<Arc<BitVec>, ParseIntValueError> {
+    if !parse_type && type_width.is_none() {
+        return Err(ParseIntValueError::MissingWidth);
+    }
+    let mut s = s.trim();
+    if s.is_empty() {
+        return Err(ParseIntValueError::Empty);
+    }
+    let negative = match s.bytes().next() {
+        Some(ch @ (b'+' | b'-')) => {
+            s = s[1..].trim_start();
+            ch == b'-'
+        }
+        _ => false,
+    };
+    let radix = match s.bytes().next() {
+        Some(b'0') => match s.bytes().nth(1) {
+            Some(b'x' | b'X') => {
+                s = &s[2..];
+                16
+            }
+            Some(b'b' | b'B') => {
+                s = &s[2..];
+                2
+            }
+            Some(b'o' | b'O') => {
+                s = &s[2..];
+                8
+            }
+            _ => 10,
+        },
+        Some(b'1'..=b'9') => 10,
+        _ => return Err(ParseIntValueError::InvalidDigit),
+    };
+    let mut any_digits = false;
+    let digits_end = s
+        .as_bytes()
+        .iter()
+        .position(|&ch| {
+            if ch == b'_' {
+                false
+            } else if (ch as char).to_digit(radix).is_some() {
+                any_digits = true;
+                false
+            } else {
+                true
+            }
+        })
+        .unwrap_or(s.len());
+    let digits = &s[..digits_end];
+    s = &s[digits_end..];
+    if !any_digits {
+        return Err(ParseIntValueError::MissingDigits);
+    }
+    let width = if parse_type {
+        const HDL_PREFIX: &[u8] = b"hdl_";
+        let mut missing_type = ParseIntValueError::MissingType;
+        if s.as_bytes()
+            .get(..HDL_PREFIX.len())
+            .is_some_and(|bytes| bytes.eq_ignore_ascii_case(HDL_PREFIX))
+        {
+            s = &s[HDL_PREFIX.len()..];
+            missing_type = ParseIntValueError::InvalidType;
+        }
+        let signed = match s.bytes().next() {
+            Some(b'u' | b'U') => false,
+            Some(b'i' | b'I') => true,
+            Some(_) => return Err(ParseIntValueError::InvalidType),
+            None => return Err(missing_type),
+        };
+        s = &s[1..];
+        let mut width = 0usize;
+        let mut any_digits = false;
+        for ch in s.bytes() {
+            let digit = (ch as char)
+                .to_digit(10)
+                .ok_or(ParseIntValueError::InvalidDigit)?;
+            any_digits = true;
+            width = width
+                .checked_mul(10)
+                .and_then(|v| v.checked_add(digit as usize))
+                .ok_or(ParseIntValueError::WidthOverflow)?;
+        }
+        if !any_digits {
+            return Err(ParseIntValueError::MissingDigits);
+        }
+        if width > <BitSlice>::MAX_BITS {
+            return Err(ParseIntValueError::WidthOverflow);
+        }
+        let expected_width = type_width.unwrap_or(width);
+        if type_is_signed != signed || expected_width != width {
+            let expected_width = type_width.unwrap_or(width);
+            return Err(ParseIntValueError::TypeMismatch {
+                parsed_signed: signed,
+                parsed_width: width,
+                expected_signed: type_is_signed,
+                expected_width,
+            });
+        }
+        width
+    } else {
+        if !s.is_empty() {
+            return Err(ParseIntValueError::InvalidDigit);
+        }
+        type_width.expect("checked earlier")
+    };
+    if !type_is_signed && negative {
+        return Err(ParseIntValueError::InvalidDigit);
+    }
+    if radix == 10 {
+        let mut value: BigInt = digits
+            .replace("_", "")
+            .parse()
+            .expect("checked that the digits are valid already");
+        if negative {
+            value = -value;
+        }
+        let uint_value: UIntValue = UInt::new(width).from_bigint_wrapping(&value);
+        if value.is_zero() {
+            Ok(uint_value.into_bits())
+        } else {
+            for i in 0..width {
+                value.set_bit(i as u64, type_is_signed && negative);
+            }
+            if value.is_zero() {
+                Ok(uint_value.into_bits())
+            } else if type_is_signed && negative {
+                if value.sign() == Sign::Minus && value.magnitude().is_one() {
+                    Ok(uint_value.into_bits())
+                } else {
+                    Err(ParseIntValueError::NegOverflow)
+                }
+            } else {
+                Err(ParseIntValueError::PosOverflow)
+            }
+        }
+    } else {
+        let mut value = BitVec::repeat(false, width);
+        let bits_per_digit = match radix {
+            2 => 1,
+            8 => 3,
+            16 => 4,
+            _ => unreachable!(),
+        };
+        let mut digits = digits
+            .bytes()
+            .rev()
+            .filter_map(|ch| (ch as char).to_digit(radix));
+        let overflow_error = if negative {
+            ParseIntValueError::NegOverflow
+        } else {
+            ParseIntValueError::PosOverflow
+        };
+        for chunk in value.chunks_mut(bits_per_digit) {
+            if let Some(mut digit) = digits.next() {
+                let digit_bits = &mut digit.view_bits_mut::<Lsb0>()[..chunk.len()];
+                chunk.clone_from_bitslice(digit_bits);
+                digit_bits.fill(false);
+                if digit != 0 {
+                    return Err(overflow_error);
+                }
+            } else {
+                break;
+            }
+        }
+        for digit in digits {
+            if digit != 0 {
+                return Err(overflow_error);
+            }
+        }
+        let negative_zero = if negative {
+            // negating a value happens in three regions:
+            // * the least-significant zeros, which are left as zeros
+            // * the least-significant one bit, which is left as a one bit
+            // * all the most-significant bits, which are inverted
+            // e.g.:
+            const {
+                let inp = 0b1010_1_000_u8;
+                let out = 0b0101_1_000_u8;
+                assert!(inp.wrapping_neg() == out);
+            };
+            if let Some(first_one) = value.first_one() {
+                let most_significant_bits = &mut value[first_one + 1..];
+                // modifies in-place despite using `Not::not`
+                let _ = Not::not(most_significant_bits);
+                false
+            } else {
+                true
+            }
+        } else {
+            false
+        };
+        if !negative_zero && type_is_signed && negative != value[value.len() - 1] {
+            Err(overflow_error)
+        } else {
+            Ok(Arc::new(value))
+        }
+    }
+}
+
+fn deserialize_int_value<'de, D: Deserializer<'de>>(
+    deserializer: D,
+    type_is_signed: bool,
+    type_width: Option<usize>,
+) -> Result<Arc<BitVec>, D::Error> {
+    struct IntValueVisitor {
+        type_is_signed: bool,
+        type_width: Option<usize>,
+    }
+    impl<'de> Visitor<'de> for IntValueVisitor {
+        type Value = Arc<BitVec>;
+
+        fn expecting(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+            f.write_str(if self.type_is_signed {
+                "SIntValue"
+            } else {
+                "UIntValue"
+            })?;
+            if let Some(type_width) = self.type_width {
+                write!(f, "<{type_width}>")?;
+            }
+            Ok(())
+        }
+
+        fn visit_str<E: Error>(self, v: &str) -> Result<Self::Value, E> {
+            parse_int_value(v, self.type_is_signed, self.type_width, true).map_err(E::custom)
+        }
+
+        fn visit_bytes<E: Error>(self, v: &[u8]) -> Result<Self::Value, E> {
+            match std::str::from_utf8(v) {
+                Ok(v) => self.visit_str(v),
+                Err(_) => Err(Error::invalid_value(serde::de::Unexpected::Bytes(v), &self)),
+            }
+        }
+    }
+    deserializer.deserialize_str(IntValueVisitor {
+        type_is_signed,
+        type_width,
+    })
+}
+
 macro_rules! impl_int {
     ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal) => {
         #[derive(Copy, Clone, PartialEq, Eq, Hash)]
@@ -188,31 +554,26 @@ macro_rules! impl_int {
         pub const $name: $generic_name = $generic_name;
 
         impl<Width: Size> $name<Width> {
-            pub fn new(width: Width::SizeType) -> Self {
+            pub const fn new(width: Width::SizeType) -> Self {
                 Self { width }
             }
             pub fn width(self) -> usize {
                 Width::as_usize(self.width)
             }
             pub fn type_properties(self) -> TypeProperties {
-                TypeProperties {
-                    is_passive: true,
-                    is_storable: true,
-                    is_castable_from_bits: true,
-                    bit_width: self.width(),
-                }
+                self.as_dyn_int().type_properties_dyn()
             }
-            pub fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
+            pub fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
                 BoolOrIntType::bits_from_bigint_wrapping(self, v)
             }
-            pub fn from_bigint_wrapping(self, v: BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(self, v: &BigInt) -> $value<Width> {
                 $value {
                     bits: Arc::new(self.bits_from_bigint_wrapping(v)),
                     _phantom: PhantomData,
                 }
             }
             pub fn from_int_wrapping(self, v: impl Into<BigInt>) -> $value<Width> {
-                self.from_bigint_wrapping(v.into())
+                self.from_bigint_wrapping(&v.into())
             }
             pub fn zero(self) -> $value<Width> {
                 self.from_int_wrapping(0u8)
@@ -227,12 +588,29 @@ macro_rules! impl_int {
         impl<Width: Size> BoolOrIntType for $name<Width> {
             type Width = Width;
             type Signed = ConstBool<$SIGNED>;
+            type Value = $value<Width>;
             fn width(self) -> usize {
                 $name::width(self)
             }
             fn new(width: Width::SizeType) -> Self {
                 $name { width }
             }
+            fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
+                $value::<Width>::from_bigint_wrapping(self, v)
+            }
+            fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
+                #[derive(Copy, Clone, Eq, PartialEq, Hash)]
+                struct MemoizeBitsToValue;
+                impl Memoize for MemoizeBitsToValue {
+                    type Input = BitSlice;
+                    type InputOwned = BitVec;
+                    type Output = Arc<BitVec>;
+                    fn inner(self, input: &Self::Input) -> Self::Output {
+                        Arc::new(input.to_bitvec())
+                    }
+                }
+                $value::new(MemoizeBitsToValue.get_cow(bits))
+            }
             fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
                 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
                 struct MemoizeBitsToExpr;
@@ -246,6 +624,12 @@ macro_rules! impl_int {
                 }
                 Expr::from_dyn_int(MemoizeBitsToExpr.get_cow(bits))
             }
+            fn from_str_without_ty(
+                self,
+                s: &str,
+            ) -> Result<Self::Value, <Self::Value as FromStr>::Err> {
+                parse_int_value(s, $SIGNED, Some(self.width()), false).map(Self::Value::new)
+            }
         }
 
         impl<Width: Size> IntType for $name<Width> {
@@ -253,12 +637,20 @@ macro_rules! impl_int {
         }
 
         impl $name {
-            pub fn new_dyn(width: usize) -> Self {
+            pub const fn new_dyn(width: usize) -> Self {
                 Self { width }
             }
             pub fn bits_to_bigint(bits: &BitSlice) -> BigInt {
                 <Self as BoolOrIntType>::bits_to_bigint(bits)
             }
+            pub const fn type_properties_dyn(self) -> TypeProperties {
+                TypeProperties {
+                    is_passive: true,
+                    is_storable: true,
+                    is_castable_from_bits: true,
+                    bit_width: self.width,
+                }
+            }
         }
 
         impl<Width: KnownSize> $name<Width> {
@@ -270,6 +662,7 @@ macro_rules! impl_int {
         impl<Width: Size> Type for $name<Width> {
             type BaseType = $pretty_name;
             type MaskType = Bool;
+            type SimValue = $value<Width>;
             impl_match_variant_as_self!();
             fn mask_type(&self) -> Self::MaskType {
                 Bool
@@ -280,7 +673,7 @@ macro_rules! impl_int {
             #[track_caller]
             fn from_canonical(canonical_type: CanonicalType) -> Self {
                 let CanonicalType::$pretty_name(retval) = canonical_type else {
-                    panic!("expected {}", stringify!($name));
+                    panic!("expected {}", stringify!($pretty_name));
                 };
                 $name {
                     width: Width::from_usize(retval.width),
@@ -289,20 +682,78 @@ macro_rules! impl_int {
             fn source_location() -> SourceLocation {
                 SourceLocation::builtin()
             }
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                assert_eq!(bits.len(), self.width());
+                $value::new(Arc::new(bits.to_bitvec()))
+            }
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                assert_eq!(bits.len(), self.width());
+                assert_eq!(value.width(), self.width());
+                value.bits_mut().copy_from_bitslice(bits);
+            }
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                assert_eq!(bits.len(), self.width());
+                assert_eq!(value.width(), self.width());
+                bits.copy_from_bitslice(value.bits());
+            }
+        }
+
+        impl<Width: KnownSize> Default for $name<Width> {
+            fn default() -> Self {
+                Self::TYPE
+            }
         }
 
         impl<Width: KnownSize> StaticType for $name<Width> {
             const TYPE: Self = Self { width: Width::SIZE };
             const MASK_TYPE: Self::MaskType = Bool;
-            const TYPE_PROPERTIES: TypeProperties = TypeProperties {
-                is_passive: true,
-                is_storable: true,
-                is_castable_from_bits: true,
-                bit_width: Width::VALUE,
-            };
+            const TYPE_PROPERTIES: TypeProperties = $name {
+                width: Width::VALUE,
+            }
+            .type_properties_dyn();
             const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
         }
 
+        impl<Width: Size> Serialize for $name<Width> {
+            fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+            where
+                S: Serializer,
+            {
+                self.canonical().serialize(serializer)
+            }
+        }
+
+        impl<'de, Width: Size> Deserialize<'de> for $name<Width> {
+            fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+            where
+                D: Deserializer<'de>,
+            {
+                let name = |width| -> String {
+                    if let Some(width) = width {
+                        format!("a {}<{width}>", stringify!($pretty_name))
+                    } else {
+                        format!("a {}", stringify!($pretty_name))
+                    }
+                };
+                match CanonicalType::deserialize(deserializer)? {
+                    CanonicalType::$pretty_name(retval) => {
+                        if let Some(width) = Width::try_from_usize(retval.width()) {
+                            Ok($name { width })
+                        } else {
+                            Err(Error::invalid_value(
+                                serde::de::Unexpected::Other(&name(Some(retval.width()))),
+                                &&*name(Width::KNOWN_VALUE),
+                            ))
+                        }
+                    }
+                    ty => Err(Error::invalid_value(
+                        serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                        &&*name(Width::KNOWN_VALUE),
+                    )),
+                }
+            }
+        }
+
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
         pub struct $generic_name;
 
@@ -320,7 +771,7 @@ macro_rules! impl_int {
             _phantom: PhantomData<Width>,
         }
 
-        impl<Width: Size> fmt::Debug for $value<Width> {
+        impl<Width: Size> fmt::Display for $value<Width> {
             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
                 let value = self.to_bigint();
                 let (sign, magnitude) = value.into_parts();
@@ -334,6 +785,47 @@ macro_rules! impl_int {
             }
         }
 
+        impl<Width: Size> fmt::Debug for $value<Width> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                fmt::Display::fmt(self, f)
+            }
+        }
+
+        impl<Width: Size> std::str::FromStr for $value<Width> {
+            type Err = ParseIntValueError;
+
+            fn from_str(s: &str) -> Result<Self, Self::Err> {
+                parse_int_value(s, $SIGNED, Width::KNOWN_VALUE, true).map(Self::new)
+            }
+        }
+
+        impl<Width: Size> Serialize for $value<Width> {
+            fn serialize<S: Serializer>(&self, serializer: S) -> Result<S::Ok, S::Error> {
+                self.to_string().serialize(serializer)
+            }
+        }
+
+        impl<'de, Width: Size> Deserialize<'de> for $value<Width> {
+            fn deserialize<D: Deserializer<'de>>(deserializer: D) -> Result<Self, D::Error> {
+                deserialize_int_value(deserializer, $SIGNED, Width::KNOWN_VALUE).map(Self::new)
+            }
+        }
+
+        impl<Width: Size> PartialOrd for $value<Width> {
+            fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
+                if self.width() != other.width() {
+                    return None;
+                }
+                Some(self.to_bigint().cmp(&other.to_bigint()))
+            }
+        }
+
+        impl<Width: Size> From<$value<Width>> for BigInt {
+            fn from(v: $value<Width>) -> BigInt {
+                v.to_bigint()
+            }
+        }
+
         impl<Width: Size> $value<Width> {
             pub fn width(&self) -> usize {
                 if let Some(retval) = Width::KNOWN_VALUE {
@@ -343,7 +835,7 @@ macro_rules! impl_int {
                     self.bits.len()
                 }
             }
-            pub fn from_bigint_wrapping(ty: $name<Width>, v: BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(ty: $name<Width>, v: &BigInt) -> $value<Width> {
                 ty.from_bigint_wrapping(v)
             }
             pub fn to_bigint(&self) -> BigInt {
@@ -366,6 +858,9 @@ macro_rules! impl_int {
             pub fn bits(&self) -> &Arc<BitVec> {
                 &self.bits
             }
+            pub fn bits_mut(&mut self) -> &mut BitSlice {
+                Arc::<BitVec>::make_mut(&mut self.bits)
+            }
         }
 
         impl<Width: Size> ToLiteralBits for $value<Width> {
@@ -420,6 +915,10 @@ impl UInt {
         let v: BigUint = v.into();
         Self::new(v.bits().try_into().expect("too big"))
     }
+    /// gets the smallest `UInt` that fits `v` losslessly
+    pub const fn for_value_usize(v: usize) -> Self {
+        Self::new((usize::BITS - v.leading_zeros()) as usize)
+    }
     /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
     #[track_caller]
     pub fn range(r: Range<impl Into<BigUint>>) -> Self {
@@ -430,6 +929,12 @@ impl UInt {
     }
     /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
     #[track_caller]
+    pub const fn range_usize(r: Range<usize>) -> Self {
+        assert!(r.end != 0, "empty range");
+        Self::range_inclusive_usize(r.start..=(r.end - 1))
+    }
+    /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
+    #[track_caller]
     pub fn range_inclusive(r: RangeInclusive<impl Into<BigUint>>) -> Self {
         let (start, end) = r.into_inner();
         let start: BigUint = start.into();
@@ -439,6 +944,16 @@ impl UInt {
         // so must not take more bits than `end`
         Self::for_value(end)
     }
+    /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
+    #[track_caller]
+    pub const fn range_inclusive_usize(r: RangeInclusive<usize>) -> Self {
+        let start = *r.start();
+        let end = *r.end();
+        assert!(start <= end, "empty range");
+        // no need to check `start`` since it's no larger than `end`
+        // so must not take more bits than `end`
+        Self::for_value_usize(end)
+    }
 }
 
 impl SInt {
@@ -453,7 +968,10 @@ impl SInt {
                     v.not().bits().checked_add(1).expect("too big")
                 }
                 Sign::NoSign => 0,
-                Sign::Plus => v.bits(),
+                Sign::Plus => {
+                    // account for sign bit
+                    v.bits().checked_add(1).expect("too big")
+                }
             }
             .try_into()
             .expect("too big"),
@@ -482,6 +1000,19 @@ macro_rules! impl_prim_int {
         $(#[$meta:meta])*
         $prim_int:ident, $ty:ty
     ) => {
+        impl From<$prim_int> for <$ty as BoolOrIntType>::Value {
+            fn from(v: $prim_int) -> Self {
+                <$ty>::le_bytes_to_value_wrapping(
+                    &v.to_le_bytes(),
+                    <$ty as BoolOrIntType>::Width::VALUE,
+                )
+            }
+        }
+        impl From<NonZero<$prim_int>> for <$ty as BoolOrIntType>::Value {
+            fn from(v: NonZero<$prim_int>) -> Self {
+                v.get().into()
+            }
+        }
         $(#[$meta])*
         impl ToExpr for $prim_int {
             type Type = $ty;
@@ -498,10 +1029,7 @@ macro_rules! impl_prim_int {
             type Type = $ty;
 
             fn to_expr(&self) -> Expr<Self::Type> {
-                <$ty>::le_bytes_to_expr_wrapping(
-                    &self.get().to_le_bytes(),
-                    <$ty as BoolOrIntType>::Width::VALUE,
-                )
+                self.get().to_expr()
             }
         }
     };
@@ -519,18 +1047,30 @@ impl_prim_int!(i64, SInt<64>);
 impl_prim_int!(i128, SInt<128>);
 
 impl_prim_int!(
-    /// for portability reasons, [`usize`] always translates to [`UInt<64>`]
+    /// for portability reasons, [`usize`] always translates to [`UInt<64>`][type@UInt]
     usize, UInt<64>
 );
 
 impl_prim_int!(
-    /// for portability reasons, [`isize`] always translates to [`SInt<64>`]
+    /// for portability reasons, [`isize`] always translates to [`SInt<64>`][type@SInt]
     isize, SInt<64>
 );
 
 pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     type Width: Size;
     type Signed: GenericConstBool;
+    type Value: Clone
+        + PartialOrd
+        + Eq
+        + std::hash::Hash
+        + fmt::Debug
+        + fmt::Display
+        + Send
+        + Sync
+        + 'static
+        + ToExpr<Type = Self>
+        + Into<BigInt>
+        + std::str::FromStr;
     fn width(self) -> usize;
     fn new(width: <Self::Width as Size>::SizeType) -> Self;
     fn new_static() -> Self
@@ -545,17 +1085,30 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     fn as_same_width_uint(self) -> UIntType<Self::Width> {
         UIntType::new(Self::Width::from_usize(self.width()))
     }
-    fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
-        let width = self.width();
+    fn value_from_int_wrapping(self, v: impl Into<BigInt>) -> Self::Value {
+        self.value_from_bigint_wrapping(&v.into())
+    }
+    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value;
+    fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
+        let mut bits = BitVec::repeat(false, self.width());
+        Self::copy_bits_from_bigint_wrapping(v, &mut bits);
+        bits
+    }
+    fn copy_bits_from_bigint_wrapping(v: &BigInt, bits: &mut BitSlice) {
+        let width = bits.len();
         let mut bytes = v.to_signed_bytes_le();
         bytes.resize(
             width.div_ceil(u8::BITS as usize),
             if v.is_negative() { 0xFF } else { 0 },
         );
         let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
-        let mut bits = BitVec::new();
-        bits.extend_from_bitslice(bitslice);
-        bits
+        bits.clone_from_bitslice(bitslice);
+    }
+    fn bits_equal_bigint_wrapping(v: &BigInt, bits: &BitSlice) -> bool {
+        bits.iter()
+            .by_vals()
+            .enumerate()
+            .all(|(bit_index, bit): (usize, bool)| v.bit(bit_index as u64) == bit)
     }
     fn bits_to_bigint(bits: &BitSlice) -> BigInt {
         let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
@@ -567,8 +1120,9 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         BitSlice::<u8, Lsb0>::from_slice_mut(&mut bytes)[..bits.len()].clone_from_bitslice(bits);
         BigInt::from_signed_bytes_le(&bytes)
     }
+    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value;
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self>;
-    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
+    fn le_bytes_to_bits_wrapping(bytes: &[u8], bit_width: usize) -> BitVec {
         let bitslice = BitSlice::<u8, Lsb0>::from_slice(bytes);
         let bitslice = &bitslice[..bit_width.min(bitslice.len())];
         let mut bits = BitVec::new();
@@ -577,11 +1131,24 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
             bit_width,
             Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false),
         );
-        Self::bits_to_expr(Cow::Owned(bits))
+        bits
     }
+    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
+        Self::bits_to_expr(Cow::Owned(Self::le_bytes_to_bits_wrapping(
+            bytes, bit_width,
+        )))
+    }
+    fn le_bytes_to_value_wrapping(bytes: &[u8], bit_width: usize) -> Self::Value {
+        Self::bits_to_value(Cow::Owned(Self::le_bytes_to_bits_wrapping(
+            bytes, bit_width,
+        )))
+    }
+    fn from_str_without_ty(self, s: &str) -> Result<Self::Value, <Self::Value as FromStr>::Err>;
 }
 
-pub trait IntType: BoolOrIntType<BaseType = <Self as IntType>::Dyn> {
+pub trait IntType:
+    BoolOrIntType<BaseType = <Self as IntType>::Dyn, Value: FromStr<Err = ParseIntValueError>>
+{
     type Dyn: IntType<Dyn = Self::Dyn, Signed = Self::Signed, Width = DynSize>;
     fn as_dyn_int(self) -> Self::Dyn {
         Self::new_dyn(self.width())
@@ -621,7 +1188,7 @@ pub trait IntType: BoolOrIntType<BaseType = <Self as IntType>::Dyn> {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
 pub struct Bool;
 
 impl sealed::BoolOrIntTypeSealed for Bool {}
@@ -629,6 +1196,7 @@ impl sealed::BoolOrIntTypeSealed for Bool {}
 impl BoolOrIntType for Bool {
     type Width = ConstUsize<1>;
     type Signed = ConstBool<false>;
+    type Value = bool;
 
     fn width(self) -> usize {
         1
@@ -639,10 +1207,23 @@ impl BoolOrIntType for Bool {
         Bool
     }
 
+    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
+        v.bit(0)
+    }
+
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
         assert_eq!(bits.len(), 1);
         bits[0].to_expr()
     }
+
+    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
+
+    fn from_str_without_ty(self, s: &str) -> Result<Self::Value, <Self::Value as FromStr>::Err> {
+        FromStr::from_str(s)
+    }
 }
 
 impl Bool {
@@ -657,6 +1238,7 @@ impl Bool {
 impl Type for Bool {
     type BaseType = Bool;
     type MaskType = Bool;
+    type SimValue = bool;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         Bool
@@ -674,6 +1256,18 @@ impl Type for Bool {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), 1);
+        *value = bits[0];
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), 1);
+        bits.set(0, *value);
+    }
 }
 
 impl StaticType for Bool {
@@ -693,3 +1287,138 @@ impl ToLiteralBits for bool {
         Ok(interned_bit(*self))
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_different_value_widths_compare_ne() {
+        // interning relies on [SU]IntValue with different `width` comparing not equal
+        assert_ne!(UInt[3].from_int_wrapping(0), UInt[4].from_int_wrapping(0));
+        assert_ne!(SInt[3].from_int_wrapping(0), SInt[4].from_int_wrapping(0));
+    }
+
+    #[test]
+    fn test_uint_for_value() {
+        assert_eq!(UInt::for_value(0u8).width, 0);
+        assert_eq!(UInt::for_value(1u8).width, 1);
+        assert_eq!(UInt::for_value(2u8).width, 2);
+        assert_eq!(UInt::for_value(3u8).width, 2);
+        assert_eq!(UInt::for_value(4u8).width, 3);
+    }
+
+    #[test]
+    fn test_sint_for_value() {
+        assert_eq!(SInt::for_value(-5).width, 4);
+        assert_eq!(SInt::for_value(-4).width, 3);
+        assert_eq!(SInt::for_value(-3).width, 3);
+        assert_eq!(SInt::for_value(-2).width, 2);
+        assert_eq!(SInt::for_value(-1).width, 1);
+        assert_eq!(SInt::for_value(0).width, 0);
+        assert_eq!(SInt::for_value(1).width, 2);
+        assert_eq!(SInt::for_value(2).width, 3);
+        assert_eq!(SInt::for_value(3).width, 3);
+        assert_eq!(SInt::for_value(4).width, 4);
+    }
+
+    #[test]
+    fn test_serde_round_trip() {
+        use serde_json::json;
+        #[track_caller]
+        fn check<T: Serialize + DeserializeOwned + PartialEq + fmt::Debug>(
+            value: T,
+            expected: serde_json::Value,
+        ) {
+            assert_eq!(serde_json::to_value(&value).unwrap(), expected);
+            assert_eq!(value, T::deserialize(expected).unwrap());
+        }
+        check(UInt[0], json! { { "UInt": { "width": 0 } } });
+        check(UInt::<0>::TYPE, json! { { "UInt": { "width": 0 } } });
+        check(UInt::<35>::TYPE, json! { { "UInt": { "width": 35 } } });
+        check(SInt[0], json! { { "SInt": { "width": 0 } } });
+        check(SInt::<0>::TYPE, json! { { "SInt": { "width": 0 } } });
+        check(SInt::<35>::TYPE, json! { { "SInt": { "width": 35 } } });
+        check(Bool, json! { "Bool" });
+        check(UIntValue::from(0u8), json! { "0x0_u8" });
+        check(SIntValue::from(-128i8), json! { "-0x80_i8" });
+        check(UInt[3].from_int_wrapping(5), json! { "0x5_u3" });
+        check(UInt[12].from_int_wrapping(0x1123), json! { "0x123_u12" });
+        check(SInt[12].from_int_wrapping(0xFEE), json! { "-0x12_i12" });
+        check(SInt[12].from_int_wrapping(0x7EE), json! { "0x7EE_i12" });
+    }
+
+    #[test]
+    fn test_deserialize() {
+        use serde_json::json;
+        #[track_caller]
+        fn check<T: DeserializeOwned + fmt::Debug + PartialEq>(
+            expected: Result<T, &str>,
+            input: serde_json::Value,
+        ) {
+            let mut error = String::new();
+            let value = T::deserialize(input).map_err(|e| -> &str {
+                error = e.to_string();
+                &error
+            });
+            assert_eq!(value, expected);
+        }
+        check::<UInt<0>>(
+            Err("invalid value: a UInt<2>, expected a UInt<0>"),
+            json! { { "UInt": { "width": 2 } } },
+        );
+        check::<UInt<0>>(
+            Err("invalid value: a Bool, expected a UInt<0>"),
+            json! { "Bool" },
+        );
+        check::<SInt<0>>(
+            Err("invalid value: a Bool, expected a SInt<0>"),
+            json! { "Bool" },
+        );
+        check::<UInt>(
+            Err("invalid value: a Bool, expected a UInt"),
+            json! { "Bool" },
+        );
+        check::<SInt>(
+            Err("invalid value: a Bool, expected a SInt"),
+            json! { "Bool" },
+        );
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "2_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "10_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0x2_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0b10_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0o2_u1" });
+        check::<SIntValue>(Err("value too large to fit in type"), json! { "0o377_i8" });
+        check::<SIntValue>(Err("value too large to fit in type"), json! { "0o200_i8" });
+        check(Ok(SInt[8].from_int_wrapping(i8::MAX)), json! { "0o177_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o201_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o377_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o400_i8" });
+        check::<SIntValue>(
+            Err("value too small to fit in type"),
+            json! { "-0o4000_i8" },
+        );
+        check(Ok(UIntValue::from(0u8)), json! { "0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0b0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "00_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0x0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0o0_u8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0x000_80_i8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0o002_00_hdl_i8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0b1__000_0000_i8" });
+        check(Ok(UInt[3].from_int_wrapping(5)), json! { " + 0x5_u3 " });
+        check(
+            Ok(UInt[12].from_int_wrapping(0x1123)),
+            json! { "0x1_2_3_hdl_u12" },
+        );
+        check(Ok(SInt[12].from_int_wrapping(0xFEE)), json! { "-0x12_i12" });
+        check(
+            Ok(SInt[12].from_int_wrapping(0x7EE)),
+            json! { " + \t0x7__E_e_i012\n" },
+        );
+        check(Ok(SInt[0].from_int_wrapping(0)), json! { "-0i0" });
+        check(Ok(SInt[1].from_int_wrapping(0)), json! { "-0i1" });
+        check(Ok(SInt[0].from_int_wrapping(0)), json! { "-0x0i0" });
+        check(Ok(SInt[1].from_int_wrapping(0)), json! { "-0x0i1" });
+    }
+}
diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs
new file mode 100644
index 0000000..0e2d07e
--- /dev/null
+++ b/crates/fayalite/src/int/uint_in_range.rs
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    bundle::{Bundle, BundleField, BundleType, BundleTypePropertiesBuilder, NoBuilder},
+    expr::{
+        ops::{ExprCastTo, ExprPartialEq, ExprPartialOrd},
+        CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd,
+    },
+    int::{Bool, DynSize, KnownSize, Size, SizeType, UInt, UIntType},
+    intern::{Intern, Interned},
+    phantom_const::PhantomConst,
+    sim::value::{SimValue, SimValuePartialEq, ToSimValueWithType},
+    source_location::SourceLocation,
+    ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
+};
+use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
+use serde::{
+    de::{value::UsizeDeserializer, Error, Visitor},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
+use std::{fmt, marker::PhantomData, ops::Index};
+
+const UINT_IN_RANGE_TYPE_FIELD_NAMES: [&'static str; 2] = ["value", "range"];
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct UIntInRangeMaskType {
+    value: Bool,
+    range: PhantomConstRangeMaskType,
+}
+
+impl Type for UIntInRangeMaskType {
+    type BaseType = Bundle;
+    type MaskType = Self;
+    type SimValue = bool;
+    impl_match_variant_as_self!();
+
+    fn mask_type(&self) -> Self::MaskType {
+        *self
+    }
+
+    fn canonical(&self) -> CanonicalType {
+        CanonicalType::Bundle(Bundle::new(self.fields()))
+    }
+
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let fields = Bundle::from_canonical(canonical_type).fields();
+        let [BundleField {
+            name: value_name,
+            flipped: false,
+            ty: value,
+        }, BundleField {
+            name: range_name,
+            flipped: false,
+            ty: range,
+        }] = *fields
+        else {
+            panic!("expected UIntInRangeMaskType");
+        };
+        assert_eq!([&*value_name, &*range_name], UINT_IN_RANGE_TYPE_FIELD_NAMES);
+        let value = Bool::from_canonical(value);
+        let range = PhantomConstRangeMaskType::from_canonical(range);
+        Self { value, range }
+    }
+
+    fn source_location() -> SourceLocation {
+        SourceLocation::builtin()
+    }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        Bool.sim_value_from_bits(bits)
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        Bool.sim_value_clone_from_bits(value, bits);
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        Bool.sim_value_to_bits(value, bits);
+    }
+}
+
+impl BundleType for UIntInRangeMaskType {
+    type Builder = NoBuilder;
+    type FilledBuilder = Expr<UIntInRangeMaskType>;
+
+    fn fields(&self) -> Interned<[BundleField]> {
+        let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES;
+        let Self { value, range } = self;
+        [
+            BundleField {
+                name: value_name.intern(),
+                flipped: false,
+                ty: value.canonical(),
+            },
+            BundleField {
+                name: range_name.intern(),
+                flipped: false,
+                ty: range.canonical(),
+            },
+        ][..]
+            .intern()
+    }
+}
+
+impl StaticType for UIntInRangeMaskType {
+    const TYPE: Self = Self {
+        value: Bool,
+        range: PhantomConstRangeMaskType::TYPE,
+    };
+    const MASK_TYPE: Self::MaskType = Self::TYPE;
+    const TYPE_PROPERTIES: TypeProperties = BundleTypePropertiesBuilder::new()
+        .field(false, Bool::TYPE_PROPERTIES)
+        .field(false, PhantomConstRangeMaskType::TYPE_PROPERTIES)
+        .finish();
+    const MASK_TYPE_PROPERTIES: TypeProperties = Self::TYPE_PROPERTIES;
+}
+
+impl ToSimValueWithType<UIntInRangeMaskType> for bool {
+    fn to_sim_value_with_type(&self, ty: UIntInRangeMaskType) -> SimValue<UIntInRangeMaskType> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl ExprCastTo<Bool> for UIntInRangeMaskType {
+    fn cast_to(src: Expr<Self>, to_type: Bool) -> Expr<Bool> {
+        src.cast_to_bits().cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<UIntInRangeMaskType> for Bool {
+    fn cast_to(src: Expr<Self>, to_type: UIntInRangeMaskType) -> Expr<UIntInRangeMaskType> {
+        src.cast_to_static::<UInt<1>>().cast_bits_to(to_type)
+    }
+}
+
+impl ExprPartialEq<Self> for UIntInRangeMaskType {
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+    }
+}
+
+impl SimValuePartialEq<Self> for UIntInRangeMaskType {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        **this == **other
+    }
+}
+
+type PhantomConstRangeMaskType = <PhantomConst<SerdeRange<DynSize, DynSize>> as Type>::MaskType;
+
+#[derive(Default, Copy, Clone, Debug)]
+struct RangeParseError;
+
+macro_rules! define_uint_in_range_type {
+    (
+        $UIntInRange:ident,
+        $UIntInRangeType:ident,
+        $UIntInRangeTypeWithoutGenerics:ident,
+        $UIntInRangeTypeWithStart:ident,
+        $SerdeRange:ident,
+        $range_operator_str:literal,
+        |$uint_range_usize_start:ident, $uint_range_usize_end:ident| $uint_range_usize:expr,
+    ) => {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct $SerdeRange<Start: Size, End: Size> {
+            start: Start::SizeType,
+            end: End::SizeType,
+        }
+
+        impl<Start: KnownSize, End: KnownSize> Default for $SerdeRange<Start, End> {
+            fn default() -> Self {
+                Self {
+                    start: Start::SIZE,
+                    end: End::SIZE,
+                }
+            }
+        }
+
+        impl std::str::FromStr for $SerdeRange<DynSize, DynSize> {
+            type Err = RangeParseError;
+
+            fn from_str(s: &str) -> Result<Self, Self::Err> {
+                let Some((start, end)) = s.split_once($range_operator_str) else {
+                    return Err(RangeParseError);
+                };
+                if start.is_empty()
+                    || start.bytes().any(|b| !b.is_ascii_digit())
+                    || end.is_empty()
+                    || end.bytes().any(|b| !b.is_ascii_digit())
+                {
+                    return Err(RangeParseError);
+                }
+                let start = start.parse().map_err(|_| RangeParseError)?;
+                let end = end.parse().map_err(|_| RangeParseError)?;
+                let retval = Self { start, end };
+                if retval.is_empty() {
+                    Err(RangeParseError)
+                } else {
+                    Ok(retval)
+                }
+            }
+        }
+
+        impl<Start: Size, End: Size> fmt::Display for $SerdeRange<Start, End> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self { start, end } = *self;
+                write!(
+                    f,
+                    "{}{}{}",
+                    Start::as_usize(start),
+                    $range_operator_str,
+                    End::as_usize(end),
+                )
+            }
+        }
+
+        impl<Start: Size, End: Size> Serialize for $SerdeRange<Start, End> {
+            fn serialize<S: Serializer>(&self, serializer: S) -> Result<S::Ok, S::Error> {
+                serializer.collect_str(self)
+            }
+        }
+
+        impl<'de, Start: Size, End: Size> Deserialize<'de> for $SerdeRange<Start, End> {
+            fn deserialize<D: Deserializer<'de>>(deserializer: D) -> Result<Self, D::Error> {
+                struct SerdeRangeVisitor<Start: Size, End: Size>(PhantomData<(Start, End)>);
+                impl<'de, Start: Size, End: Size> Visitor<'de> for SerdeRangeVisitor<Start, End> {
+                    type Value = $SerdeRange<Start, End>;
+
+                    fn expecting(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                        f.write_str("a string with format \"")?;
+                        if let Some(start) = Start::KNOWN_VALUE {
+                            write!(f, "{start}")?;
+                        } else {
+                            f.write_str("<int>")?;
+                        };
+                        f.write_str($range_operator_str)?;
+                        if let Some(end) = End::KNOWN_VALUE {
+                            write!(f, "{end}")?;
+                        } else {
+                            f.write_str("<int>")?;
+                        };
+                        f.write_str("\" that is a non-empty range")
+                    }
+
+                    fn visit_str<E: Error>(self, v: &str) -> Result<Self::Value, E> {
+                        let $SerdeRange::<DynSize, DynSize> { start, end } =
+                            v.parse().map_err(|_| {
+                                Error::invalid_value(serde::de::Unexpected::Str(v), &self)
+                            })?;
+                        let start =
+                            Start::SizeType::deserialize(UsizeDeserializer::<E>::new(start))?;
+                        let end = End::SizeType::deserialize(UsizeDeserializer::<E>::new(end))?;
+                        Ok($SerdeRange { start, end })
+                    }
+
+                    fn visit_bytes<E: Error>(self, v: &[u8]) -> Result<Self::Value, E> {
+                        match std::str::from_utf8(v) {
+                            Ok(v) => self.visit_str(v),
+                            Err(_) => {
+                                Err(Error::invalid_value(serde::de::Unexpected::Bytes(v), &self))
+                            }
+                        }
+                    }
+                }
+                deserializer.deserialize_str(SerdeRangeVisitor(PhantomData))
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+        pub struct $UIntInRangeType<Start: Size, End: Size> {
+            value: UInt,
+            range: PhantomConst<$SerdeRange<Start, End>>,
+        }
+
+        impl<Start: Size, End: Size> $UIntInRangeType<Start, End> {
+            fn from_phantom_const_range(range: PhantomConst<$SerdeRange<Start, End>>) -> Self {
+                let $SerdeRange { start, end } = *range.get();
+                let $uint_range_usize_start = Start::as_usize(start);
+                let $uint_range_usize_end = End::as_usize(end);
+                Self {
+                    value: $uint_range_usize,
+                    range,
+                }
+            }
+            pub fn new(start: Start::SizeType, end: End::SizeType) -> Self {
+                Self::from_phantom_const_range(PhantomConst::new(
+                    $SerdeRange { start, end }.intern_sized(),
+                ))
+            }
+        }
+
+        impl<Start: Size, End: Size> fmt::Debug for $UIntInRangeType<Start, End> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self { value, range } = self;
+                let $SerdeRange { start, end } = *range.get();
+                f.debug_struct(&format!(
+                    "{}<{}, {}>",
+                    stringify!($UIntInRange),
+                    Start::as_usize(start),
+                    End::as_usize(end),
+                ))
+                .field("value", value)
+                .finish_non_exhaustive()
+            }
+        }
+
+        impl<Start: Size, End: Size> Type for $UIntInRangeType<Start, End> {
+            type BaseType = Bundle;
+            type MaskType = UIntInRangeMaskType;
+            type SimValue = usize;
+            impl_match_variant_as_self!();
+
+            fn mask_type(&self) -> Self::MaskType {
+                UIntInRangeMaskType::TYPE
+            }
+
+            fn canonical(&self) -> CanonicalType {
+                CanonicalType::Bundle(Bundle::new(self.fields()))
+            }
+
+            fn from_canonical(canonical_type: CanonicalType) -> Self {
+                let fields = Bundle::from_canonical(canonical_type).fields();
+                let [BundleField {
+                    name: value_name,
+                    flipped: false,
+                    ty: value,
+                }, BundleField {
+                    name: range_name,
+                    flipped: false,
+                    ty: range,
+                }] = *fields
+                else {
+                    panic!("expected {}", stringify!($UIntInRange));
+                };
+                assert_eq!([&*value_name, &*range_name], UINT_IN_RANGE_TYPE_FIELD_NAMES);
+                let value = UInt::from_canonical(value);
+                let range = PhantomConst::<$SerdeRange<Start, End>>::from_canonical(range);
+                let retval = Self::from_phantom_const_range(range);
+                assert_eq!(retval, Self { value, range });
+                retval
+            }
+
+            fn source_location() -> SourceLocation {
+                SourceLocation::builtin()
+            }
+
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                let mut retval = 0usize;
+                retval.view_bits_mut::<Lsb0>()[..bits.len()].clone_from_bitslice(bits);
+                retval
+            }
+
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                *value = self.sim_value_from_bits(bits);
+            }
+
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                bits.clone_from_bitslice(&value.view_bits::<Lsb0>()[..bits.len()]);
+            }
+        }
+
+        impl<Start: Size, End: Size> BundleType for $UIntInRangeType<Start, End> {
+            type Builder = NoBuilder;
+            type FilledBuilder = Expr<Self>;
+
+            fn fields(&self) -> Interned<[BundleField]> {
+                let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES;
+                let Self { value, range } = self;
+                [
+                    BundleField {
+                        name: value_name.intern(),
+                        flipped: false,
+                        ty: value.canonical(),
+                    },
+                    BundleField {
+                        name: range_name.intern(),
+                        flipped: false,
+                        ty: range.canonical(),
+                    },
+                ][..]
+                    .intern()
+            }
+        }
+
+        impl<Start: KnownSize, End: KnownSize> Default for $UIntInRangeType<Start, End> {
+            fn default() -> Self {
+                Self::TYPE
+            }
+        }
+
+        impl<Start: KnownSize, End: KnownSize> StaticType for $UIntInRangeType<Start, End> {
+            const TYPE: Self = {
+                let $uint_range_usize_start = Start::VALUE;
+                let $uint_range_usize_end = End::VALUE;
+                Self {
+                    value: $uint_range_usize,
+                    range: PhantomConst::<$SerdeRange<Start, End>>::TYPE,
+                }
+            };
+            const MASK_TYPE: Self::MaskType = UIntInRangeMaskType::TYPE;
+            const TYPE_PROPERTIES: TypeProperties = BundleTypePropertiesBuilder::new()
+                .field(false, Self::TYPE.value.type_properties_dyn())
+                .field(
+                    false,
+                    PhantomConst::<$SerdeRange<Start, End>>::TYPE_PROPERTIES,
+                )
+                .finish();
+            const MASK_TYPE_PROPERTIES: TypeProperties = UIntInRangeMaskType::TYPE_PROPERTIES;
+        }
+
+        impl<Start: Size, End: Size> ToSimValueWithType<$UIntInRangeType<Start, End>> for usize {
+            fn to_sim_value_with_type(
+                &self,
+                ty: $UIntInRangeType<Start, End>,
+            ) -> SimValue<$UIntInRangeType<Start, End>> {
+                SimValue::from_value(ty, *self)
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub struct $UIntInRangeTypeWithoutGenerics;
+
+        #[allow(non_upper_case_globals)]
+        pub const $UIntInRangeType: $UIntInRangeTypeWithoutGenerics =
+            $UIntInRangeTypeWithoutGenerics;
+
+        impl<StartSize: SizeType> Index<StartSize> for $UIntInRangeTypeWithoutGenerics {
+            type Output = $UIntInRangeTypeWithStart<StartSize::Size>;
+
+            fn index(&self, start: StartSize) -> &Self::Output {
+                Interned::into_inner($UIntInRangeTypeWithStart(start).intern_sized())
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub struct $UIntInRangeTypeWithStart<Start: Size>(Start::SizeType);
+
+        impl<Start: Size, EndSize: SizeType<Size = End>, End: Size<SizeType = EndSize>>
+            Index<EndSize> for $UIntInRangeTypeWithStart<Start>
+        {
+            type Output = $UIntInRangeType<Start, End>;
+
+            fn index(&self, end: EndSize) -> &Self::Output {
+                Interned::into_inner($UIntInRangeType::new(self.0, end).intern_sized())
+            }
+        }
+
+        impl<Start: Size, End: Size> ExprCastTo<UInt> for $UIntInRangeType<Start, End> {
+            fn cast_to(src: Expr<Self>, to_type: UInt) -> Expr<UInt> {
+                src.cast_to_bits().cast_to(to_type)
+            }
+        }
+
+        impl<Start: Size, End: Size> ExprCastTo<$UIntInRangeType<Start, End>> for UInt {
+            fn cast_to(
+                src: Expr<Self>,
+                to_type: $UIntInRangeType<Start, End>,
+            ) -> Expr<$UIntInRangeType<Start, End>> {
+                src.cast_bits_to(to_type)
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            ExprPartialEq<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn cmp_eq(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+            }
+            fn cmp_ne(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            ExprPartialOrd<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn cmp_lt(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_lt(rhs.cast_to_bits())
+            }
+            fn cmp_le(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_le(rhs.cast_to_bits())
+            }
+            fn cmp_gt(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_gt(rhs.cast_to_bits())
+            }
+            fn cmp_ge(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ge(rhs.cast_to_bits())
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            SimValuePartialEq<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn sim_value_eq(
+                this: &SimValue<Self>,
+                other: &SimValue<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> bool {
+                **this == **other
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialEq<UIntType<Width>>
+            for $UIntInRangeType<Start, End>
+        {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_eq(rhs)
+            }
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ne(rhs)
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialEq<$UIntInRangeType<Start, End>>
+            for UIntType<Width>
+        {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_eq(rhs.cast_to_bits())
+            }
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_ne(rhs.cast_to_bits())
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialOrd<UIntType<Width>>
+            for $UIntInRangeType<Start, End>
+        {
+            fn cmp_lt(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_lt(rhs)
+            }
+            fn cmp_le(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_le(rhs)
+            }
+            fn cmp_gt(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_gt(rhs)
+            }
+            fn cmp_ge(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ge(rhs)
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialOrd<$UIntInRangeType<Start, End>>
+            for UIntType<Width>
+        {
+            fn cmp_lt(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_lt(rhs.cast_to_bits())
+            }
+            fn cmp_le(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_le(rhs.cast_to_bits())
+            }
+            fn cmp_gt(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_gt(rhs.cast_to_bits())
+            }
+            fn cmp_ge(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_ge(rhs.cast_to_bits())
+            }
+        }
+    };
+}
+
+define_uint_in_range_type! {
+    UIntInRange,
+    UIntInRangeType,
+    UIntInRangeTypeWithoutGenerics,
+    UIntInRangeTypeWithStart,
+    SerdeRange,
+    "..",
+    |start, end| UInt::range_usize(start..end),
+}
+
+define_uint_in_range_type! {
+    UIntInRangeInclusive,
+    UIntInRangeInclusiveType,
+    UIntInRangeInclusiveTypeWithoutGenerics,
+    UIntInRangeInclusiveTypeWithStart,
+    SerdeRangeInclusive,
+    "..=",
+    |start, end| UInt::range_inclusive_usize(start..=end),
+}
+
+impl SerdeRange<DynSize, DynSize> {
+    fn is_empty(self) -> bool {
+        self.start >= self.end
+    }
+}
+
+impl SerdeRangeInclusive<DynSize, DynSize> {
+    fn is_empty(self) -> bool {
+        self.start > self.end
+    }
+}
diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index 3780ad3..af91f0a 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 #![allow(clippy::type_complexity)]
-use crate::intern::type_map::TypeIdMap;
+use crate::{intern::type_map::TypeIdMap, util::DefaultBuildHasher};
 use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec};
-use hashbrown::{hash_map::RawEntryMut, HashMap, HashTable};
+use hashbrown::HashTable;
 use serde::{Deserialize, Serialize};
 use std::{
     any::{Any, TypeId},
@@ -17,7 +17,7 @@ use std::{
     sync::{Mutex, RwLock},
 };
 
-pub mod type_map;
+mod type_map;
 
 pub trait LazyInternedTrait<T: ?Sized + Send + Sync + 'static>: Send + Sync + Any {
     fn get(&self) -> Interned<T>;
@@ -316,8 +316,13 @@ pub trait Intern: Any + Send + Sync {
     }
 }
 
+struct InternerState<T: ?Sized + 'static + Send + Sync> {
+    table: HashTable<&'static T>,
+    hasher: DefaultBuildHasher,
+}
+
 pub struct Interner<T: ?Sized + 'static + Send + Sync> {
-    map: Mutex<HashMap<&'static T, ()>>,
+    state: Mutex<InternerState<T>>,
 }
 
 impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
@@ -330,7 +335,10 @@ impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
 impl<T: ?Sized + 'static + Send + Sync> Default for Interner<T> {
     fn default() -> Self {
         Self {
-            map: Default::default(),
+            state: Mutex::new(InternerState {
+                table: HashTable::new(),
+                hasher: Default::default(),
+            }),
         }
     }
 }
@@ -341,17 +349,16 @@ impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned> Interner<T> {
         alloc: F,
         value: Cow<'_, T>,
     ) -> Interned<T> {
-        let mut map = self.map.lock().unwrap();
-        let hasher = map.hasher().clone();
-        let hash = hasher.hash_one(&*value);
-        let inner = match map.raw_entry_mut().from_hash(hash, |k| **k == *value) {
-            RawEntryMut::Occupied(entry) => *entry.key(),
-            RawEntryMut::Vacant(entry) => {
-                *entry
-                    .insert_with_hasher(hash, alloc(value), (), |k| hasher.hash_one(&**k))
-                    .0
-            }
-        };
+        let mut state = self.state.lock().unwrap();
+        let InternerState { table, hasher } = &mut *state;
+        let inner = *table
+            .entry(
+                hasher.hash_one(&*value),
+                |k| **k == *value,
+                |k| hasher.hash_one(&**k),
+            )
+            .or_insert_with(|| alloc(value))
+            .get();
         Interned { inner }
     }
 }
@@ -742,7 +749,7 @@ pub trait MemoizeGeneric: 'static + Send + Sync + Hash + Eq + Copy {
     fn get_cow(self, input: Self::InputCow<'_>) -> Self::Output {
         static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
         let map: &RwLock<(
-            hashbrown::hash_map::DefaultHashBuilder,
+            DefaultBuildHasher,
             HashTable<(Self, Self::InputOwned, Self::Output)>,
         )> = TYPE_ID_MAP.get_or_insert_default();
         fn hash_eq_key<'a, 'b, T: MemoizeGeneric>(
diff --git a/crates/fayalite/src/intern/type_map.rs b/crates/fayalite/src/intern/type_map.rs
index 48433af..945116b 100644
--- a/crates/fayalite/src/intern/type_map.rs
+++ b/crates/fayalite/src/intern/type_map.rs
@@ -1,10 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use hashbrown::HashMap;
 use std::{
     any::{Any, TypeId},
     hash::{BuildHasher, Hasher},
-    ptr::NonNull,
     sync::RwLock,
 };
 
@@ -75,59 +73,36 @@ impl BuildHasher for TypeIdBuildHasher {
     }
 }
 
-struct Value(NonNull<dyn Any + Send + Sync>);
-
-impl Value {
-    unsafe fn get_transmute_lifetime<'b>(&self) -> &'b (dyn Any + Send + Sync) {
-        unsafe { &*self.0.as_ptr() }
-    }
-    fn new(v: Box<dyn Any + Send + Sync>) -> Self {
-        unsafe { Self(NonNull::new_unchecked(Box::into_raw(v))) }
-    }
-}
-
-unsafe impl Send for Value {}
-unsafe impl Sync for Value {}
-
-impl Drop for Value {
-    fn drop(&mut self) {
-        unsafe { std::ptr::drop_in_place(self.0.as_ptr()) }
-    }
-}
-
-pub struct TypeIdMap(RwLock<HashMap<TypeId, Value, TypeIdBuildHasher>>);
+pub(crate) struct TypeIdMap(
+    RwLock<hashbrown::HashMap<TypeId, &'static (dyn Any + Send + Sync), TypeIdBuildHasher>>,
+);
 
 impl TypeIdMap {
-    pub const fn new() -> Self {
-        Self(RwLock::new(HashMap::with_hasher(TypeIdBuildHasher)))
+    pub(crate) const fn new() -> Self {
+        Self(RwLock::new(hashbrown::HashMap::with_hasher(
+            TypeIdBuildHasher,
+        )))
     }
     #[cold]
-    unsafe fn insert_slow(
+    fn insert_slow(
         &self,
         type_id: TypeId,
         make: fn() -> Box<dyn Any + Sync + Send>,
-    ) -> &(dyn Any + Sync + Send) {
-        let value = Value::new(make());
+    ) -> &'static (dyn Any + Sync + Send) {
+        let value = Box::leak(make());
         let mut write_guard = self.0.write().unwrap();
-        unsafe {
-            write_guard
-                .entry(type_id)
-                .or_insert(value)
-                .get_transmute_lifetime()
-        }
+        *write_guard.entry(type_id).or_insert(value)
     }
-    pub fn get_or_insert_default<T: Sized + Any + Send + Sync + Default>(&self) -> &T {
+    pub(crate) fn get_or_insert_default<T: Sized + Any + Send + Sync + Default>(&self) -> &T {
         let type_id = TypeId::of::<T>();
         let read_guard = self.0.read().unwrap();
-        let retval = read_guard
-            .get(&type_id)
-            .map(|v| unsafe { Value::get_transmute_lifetime(v) });
+        let retval = read_guard.get(&type_id).map(|v| *v);
         drop(read_guard);
         let retval = match retval {
             Some(retval) => retval,
-            None => unsafe { self.insert_slow(type_id, move || Box::new(T::default())) },
+            None => self.insert_slow(type_id, move || Box::new(T::default())),
         };
-        unsafe { &*(retval as *const dyn Any as *const T) }
+        retval.downcast_ref().expect("known to have correct TypeId")
     }
 }
 
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index eedb1bb..932464b 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -11,6 +11,59 @@ extern crate self as fayalite;
 #[doc(hidden)]
 pub use std as __std;
 
+#[doc(hidden)]
+#[macro_export]
+macro_rules! __cfg_expansion_helper {
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        [
+            $cfg:ident($($expr:tt)*),
+            $($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
+        ]
+        // pass as tt so we get right span for attribute
+        $after_evaluation_attr:tt $after_evaluation_body:tt
+    ) => {
+        #[$cfg($($expr)*)]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = true,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            $after_evaluation_attr $after_evaluation_body
+        }
+        #[$cfg(not($($expr)*))]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = false,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            $after_evaluation_attr $after_evaluation_body
+        }
+    };
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        []
+        // don't use #[...] so we get right span for `#` and `[]` of attribute
+        {$($after_evaluation_attr:tt)*} {$($after_evaluation_body:tt)*}
+    ) => {
+        $($after_evaluation_attr)*
+        #[__evaluated_cfgs([
+            $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+        ])]
+        $($after_evaluation_body)*
+    };
+}
+
 #[doc(inline)]
 /// The `#[hdl_module]` attribute is applied to a Rust function so that that function creates
 /// a [`Module`][`::fayalite::module::Module`] when called.
@@ -23,6 +76,8 @@ pub use fayalite_proc_macros::hdl_module;
 #[doc(inline)]
 pub use fayalite_proc_macros::hdl;
 
+pub use bitvec;
+
 /// struct used as a placeholder when applying defaults
 #[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
 pub struct __;
@@ -43,9 +98,11 @@ pub mod int;
 pub mod intern;
 pub mod memory;
 pub mod module;
+pub mod phantom_const;
 pub mod prelude;
 pub mod reg;
 pub mod reset;
+pub mod sim;
 pub mod source_location;
 pub mod testing;
 pub mod ty;
diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index f583a8c..622ffc6 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -22,7 +22,7 @@ use std::{
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    num::NonZeroU32,
+    num::NonZeroUsize,
     rc::Rc,
 };
 
@@ -470,7 +470,7 @@ pub enum ReadUnderWrite {
     Undefined,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct MemImpl<Element: Type, Len: Size, P> {
     scoped_name: ScopedNameId,
     source_location: SourceLocation,
@@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
     initial_value: Option<Interned<BitSlice>>,
     ports: P,
     read_latency: usize,
-    write_latency: NonZeroU32,
+    write_latency: NonZeroUsize,
     read_under_write: ReadUnderWrite,
     port_annotations: Interned<[TargetedAnnotation]>,
     mem_annotations: Interned<[Annotation]>,
@@ -519,7 +519,12 @@ impl<Element: Type, Len: Size> fmt::Debug for Mem<Element, Len> {
         f.debug_struct("Mem")
             .field("name", scoped_name)
             .field("array_type", array_type)
-            .field("initial_value", initial_value)
+            .field(
+                "initial_value",
+                &initial_value.as_ref().map(|initial_value| {
+                    DebugMemoryData::from_bit_slice(*array_type, initial_value)
+                }),
+            )
             .field("read_latency", read_latency)
             .field("write_latency", write_latency)
             .field("read_under_write", read_under_write)
@@ -562,7 +567,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
         initial_value: Option<Interned<BitSlice>>,
         ports: Interned<[MemPort<DynPortType>]>,
         read_latency: usize,
-        write_latency: NonZeroU32,
+        write_latency: NonZeroUsize,
         read_under_write: ReadUnderWrite,
         port_annotations: Interned<[TargetedAnnotation]>,
         mem_annotations: Interned<[Annotation]>,
@@ -645,7 +650,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
     pub fn read_latency(self) -> usize {
         self.0.read_latency
     }
-    pub fn write_latency(self) -> NonZeroU32 {
+    pub fn write_latency(self) -> NonZeroUsize {
         self.0.write_latency
     }
     pub fn read_under_write(self) -> ReadUnderWrite {
@@ -707,7 +712,7 @@ pub(crate) struct MemBuilderTarget {
     pub(crate) initial_value: Option<Interned<BitSlice>>,
     pub(crate) ports: Vec<MemPort<DynPortType>>,
     pub(crate) read_latency: usize,
-    pub(crate) write_latency: NonZeroU32,
+    pub(crate) write_latency: NonZeroUsize,
     pub(crate) read_under_write: ReadUnderWrite,
     pub(crate) port_annotations: Vec<TargetedAnnotation>,
     pub(crate) mem_annotations: Vec<Annotation>,
@@ -867,7 +872,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
             initial_value: None,
             ports: vec![],
             read_latency: 0,
-            write_latency: NonZeroU32::new(1).unwrap(),
+            write_latency: NonZeroUsize::new(1).unwrap(),
             read_under_write: ReadUnderWrite::Old,
             port_annotations: vec![],
             mem_annotations: vec![],
@@ -1030,10 +1035,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
     pub fn read_latency(&mut self, read_latency: usize) {
         self.target.borrow_mut().read_latency = read_latency;
     }
-    pub fn get_write_latency(&self) -> NonZeroU32 {
+    pub fn get_write_latency(&self) -> NonZeroUsize {
         self.target.borrow().write_latency
     }
-    pub fn write_latency(&mut self, write_latency: NonZeroU32) {
+    pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
         self.target.borrow_mut().write_latency = write_latency;
     }
     pub fn get_read_under_write(&self) -> ReadUnderWrite {
@@ -1077,5 +1082,64 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
             )
             .to_expr(),
         )),
+        CanonicalType::PhantomConst(_) => Expr::from_canonical(Expr::canonical(().to_expr())),
+    }
+}
+
+pub trait DebugMemoryDataGetElement {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice;
+}
+
+impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
+        self(element_index, array_type)
+    }
+}
+
+#[derive(Clone)]
+pub struct DebugMemoryData<GetElement: DebugMemoryDataGetElement> {
+    pub array_type: Array,
+    pub get_element: GetElement,
+}
+
+impl DebugMemoryDataGetElement for &'_ BitSlice {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
+        assert!(element_index < array_type.len());
+        let stride = array_type.element().bit_width();
+        let start = element_index
+            .checked_mul(stride)
+            .expect("memory is too big");
+        let end = start.checked_add(stride).expect("memory is too big");
+        &self[start..end]
+    }
+}
+
+impl<'a> DebugMemoryData<&'a BitSlice> {
+    pub fn from_bit_slice<T: Type, Depth: Size>(
+        array_type: ArrayType<T, Depth>,
+        bit_slice: &'a BitSlice,
+    ) -> Self {
+        let array_type = array_type.as_dyn_array();
+        assert_eq!(bit_slice.len(), array_type.type_properties().bit_width);
+        Self {
+            array_type,
+            get_element: bit_slice,
+        }
+    }
+}
+
+impl<GetElement: DebugMemoryDataGetElement> fmt::Debug for DebugMemoryData<GetElement> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if self.array_type.len() == 0 {
+            return f.write_str("[]");
+        }
+        writeln!(f, "[\n    // len = {:#x}", self.array_type.len())?;
+        for element_index in 0..self.array_type.len() {
+            let element = crate::util::BitSliceWriteWithBase(
+                self.get_element.get_element(element_index, self.array_type),
+            );
+            writeln!(f, "    [{element_index:#x}]: {element:#x},")?;
+        }
+        f.write_str("]")
     }
 }
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 7387832..920b0af 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -20,18 +20,21 @@ use crate::{
     intern::{Intern, Interned},
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
+    sim::{ExternModuleSimGenerator, ExternModuleSimulation},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
-    util::ScopedRef,
+    util::{HashMap, HashSet, ScopedRef},
     wire::{IncompleteWire, Wire},
 };
-use hashbrown::{hash_map::Entry, HashMap, HashSet};
+use hashbrown::hash_map::Entry;
 use num_bigint::BigInt;
 use std::{
     cell::RefCell,
     collections::VecDeque,
     convert::Infallible,
     fmt,
+    future::IntoFuture,
     hash::{Hash, Hasher},
     iter::FusedIterator,
     marker::PhantomData,
@@ -180,7 +183,7 @@ impl Block {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct StmtConnect {
     pub lhs: Expr<CanonicalType>,
     pub rhs: Expr<CanonicalType>,
@@ -235,7 +238,7 @@ impl fmt::Debug for StmtConnect {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct StmtFormal {
     pub kind: FormalKind,
     pub clk: Expr<Clock>,
@@ -284,6 +287,8 @@ pub struct StmtIf<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: [S::Block; 2],
 }
 
+impl Copy for StmtIf {}
+
 impl<S: ModuleBuildingStatus> StmtIf<S> {
     pub fn then_block(&self) -> S::Block {
         self.blocks[0]
@@ -315,6 +320,8 @@ pub struct StmtMatch<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: Interned<[S::Block]>,
 }
 
+impl Copy for StmtMatch {}
+
 impl StmtMatch {
     #[track_caller]
     fn assert_validity(&self) {
@@ -346,7 +353,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -358,7 +365,7 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn]
+                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
@@ -385,7 +392,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -397,22 +404,22 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn]
+                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
             }
         }
 
-        $(
+        $($(
             wrapper_enum! {
                 impl $T_to From<$VariantTy> for $to_type {
-                    fn from(value: $VariantTy) -> Self {
+                    fn $from(value: $VariantTy) -> Self {
                         $enum_name::$Variant(value).into()
                     }
                 }
             }
-        )*
+        )?)*
     };
     (
         #[impl()]
@@ -420,7 +427,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -459,13 +466,15 @@ pub struct StmtWire<S: ModuleBuildingStatus = ModuleBuilt> {
     pub wire: Wire<CanonicalType>,
 }
 
+impl Copy for StmtWire {}
+
 #[derive(Hash, Clone, PartialEq, Eq, Debug)]
-pub struct StmtReg<S: ModuleBuildingStatus = ModuleBuilt> {
+pub struct StmtReg<R: ResetType, S: ModuleBuildingStatus = ModuleBuilt> {
     pub annotations: S::StmtAnnotations,
-    pub reg: Reg<CanonicalType>,
+    pub reg: Reg<CanonicalType, R>,
 }
 
-impl Copy for StmtReg {}
+impl<R: ResetType> Copy for StmtReg<R> {}
 
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
 pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
@@ -473,6 +482,8 @@ pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
     pub instance: Instance<Bundle>,
 }
 
+impl Copy for StmtInstance {}
+
 wrapper_enum! {
     #[impl(
         (<S: ModuleBuildingStatus>) self: StmtDeclaration<S> = self,
@@ -481,20 +492,57 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) StmtDeclaration<S>, (<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum StmtDeclaration<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_wire, as_ref = wire]
+        #[is = is_wire, as_ref = wire, from = from]
         Wire(StmtWire<S>),
         #[is = is_reg, as_ref = reg]
-        Reg(StmtReg<S>),
-        #[is = is_instance, as_ref = instance]
+        Reg(StmtReg<Reset, S>),
+        #[is = is_reg_sync, as_ref = reg_sync]
+        RegSync(StmtReg<SyncReset, S>),
+        #[is = is_reg_async, as_ref = reg_async]
+        RegAsync(StmtReg<AsyncReset, S>),
+        #[is = is_instance, as_ref = instance, from = from]
         Instance(StmtInstance<S>),
     }
 }
 
+impl Copy for StmtDeclaration {}
+
+impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for Stmt<S> {
+    fn from(value: StmtReg<R, S>) -> Self {
+        StmtDeclaration::from(value).into()
+    }
+}
+
+impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for StmtDeclaration<S> {
+    fn from(value: StmtReg<R, S>) -> Self {
+        struct Dispatch<S>(PhantomData<S>);
+        impl<S: ModuleBuildingStatus> ResetTypeDispatch for Dispatch<S> {
+            type Input<T: ResetType> = StmtReg<T, S>;
+            type Output<T: ResetType> = StmtDeclaration<S>;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                StmtDeclaration::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                StmtDeclaration::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                StmtDeclaration::RegAsync(input)
+            }
+        }
+        R::dispatch(value, Dispatch(PhantomData))
+    }
+}
+
 impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
     pub fn annotations(&self) -> S::StmtAnnotations {
         match self {
             StmtDeclaration::Wire(v) => v.annotations,
             StmtDeclaration::Reg(v) => v.annotations,
+            StmtDeclaration::RegSync(v) => v.annotations,
+            StmtDeclaration::RegAsync(v) => v.annotations,
             StmtDeclaration::Instance(v) => v.annotations,
         }
     }
@@ -502,6 +550,8 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.source_location(),
             StmtDeclaration::Reg(v) => v.reg.source_location(),
+            StmtDeclaration::RegSync(v) => v.reg.source_location(),
+            StmtDeclaration::RegAsync(v) => v.reg.source_location(),
             StmtDeclaration::Instance(v) => v.instance.source_location(),
         }
     }
@@ -509,20 +559,26 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.scoped_name(),
             StmtDeclaration::Reg(v) => v.reg.scoped_name(),
+            StmtDeclaration::RegSync(v) => v.reg.scoped_name(),
+            StmtDeclaration::RegAsync(v) => v.reg.scoped_name(),
             StmtDeclaration::Instance(v) => v.instance.scoped_name(),
         }
     }
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
-            StmtDeclaration::Wire(_) | StmtDeclaration::Reg(_) | StmtDeclaration::Instance(_) => {
-                &[]
-            }
+            StmtDeclaration::Wire(_)
+            | StmtDeclaration::Reg(_)
+            | StmtDeclaration::RegSync(_)
+            | StmtDeclaration::RegAsync(_)
+            | StmtDeclaration::Instance(_) => &[],
         }
     }
     pub fn canonical_ty(&self) -> CanonicalType {
         match self {
             StmtDeclaration::Wire(v) => v.wire.ty(),
             StmtDeclaration::Reg(v) => v.reg.ty(),
+            StmtDeclaration::RegSync(v) => v.reg.ty(),
+            StmtDeclaration::RegAsync(v) => v.reg.ty(),
             StmtDeclaration::Instance(v) => CanonicalType::Bundle(v.instance.ty()),
         }
     }
@@ -533,19 +589,21 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum Stmt<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_connect, as_ref = connect]
+        #[is = is_connect, as_ref = connect, from = from]
         Connect(StmtConnect),
-        #[is = is_formal, as_ref = formal]
+        #[is = is_formal, as_ref = formal, from = from]
         Formal(StmtFormal),
-        #[is = is_if, as_ref = if_]
+        #[is = is_if, as_ref = if_, from = from]
         If(StmtIf<S>),
-        #[is = is_match, as_ref = match_]
+        #[is = is_match, as_ref = match_, from = from]
         Match(StmtMatch<S>),
-        #[is = is_declaration, as_ref = declaration]
+        #[is = is_declaration, as_ref = declaration, from = from]
         Declaration(StmtDeclaration<S>),
     }
 }
 
+impl Copy for Stmt {}
+
 impl<S: ModuleBuildingStatus> Stmt<S> {
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
@@ -714,6 +772,18 @@ impl<T: BundleType> Instance<T> {
             source_location,
         }
     }
+    pub fn from_canonical(v: Instance<Bundle>) -> Self {
+        let Instance {
+            scoped_name,
+            instantiated,
+            source_location,
+        } = v;
+        Self {
+            scoped_name,
+            instantiated: Module::from_canonical(*instantiated).intern_sized(),
+            source_location,
+        }
+    }
     pub fn containing_module_name(self) -> Interned<str> {
         self.containing_module_name_id().0
     }
@@ -958,6 +1028,14 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
                                 annotations: (),
                                 reg,
                             }) => StmtReg { annotations, reg }.into(),
+                            StmtDeclaration::RegSync(StmtReg {
+                                annotations: (),
+                                reg,
+                            }) => StmtReg { annotations, reg }.into(),
+                            StmtDeclaration::RegAsync(StmtReg {
+                                annotations: (),
+                                reg,
+                            }) => StmtReg { annotations, reg }.into(),
                             StmtDeclaration::Instance(StmtInstance {
                                 annotations: (),
                                 instance,
@@ -1005,6 +1083,7 @@ pub struct ExternModuleBody<
 > {
     pub verilog_name: Interned<str>,
     pub parameters: P,
+    pub simulation: Option<ExternModuleSimulation>,
 }
 
 impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
@@ -1012,11 +1091,13 @@ impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
         let ExternModuleBody {
             verilog_name,
             parameters,
+            simulation,
         } = value;
         let parameters = Intern::intern_owned(parameters);
         Self {
             verilog_name,
             parameters,
+            simulation,
         }
     }
 }
@@ -1207,10 +1288,12 @@ impl<T: BundleType> fmt::Debug for DebugModuleBody<T> {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name,
                 parameters,
+                simulation,
             }) => {
                 debug_struct
                     .field("verilog_name", verilog_name)
-                    .field("parameters", parameters);
+                    .field("parameters", parameters)
+                    .field("simulation", simulation);
             }
         }
         debug_struct.finish_non_exhaustive()
@@ -1414,6 +1497,9 @@ impl TargetState {
                         })
                         .collect(),
                 },
+                CanonicalType::PhantomConst(_) => TargetStateInner::Decomposed {
+                    subtargets: HashMap::default(),
+                },
                 CanonicalType::Array(ty) => TargetStateInner::Decomposed {
                     subtargets: (0..ty.len())
                         .map(|index| {
@@ -1661,6 +1747,14 @@ impl AssertValidityState {
                     annotations: _,
                     reg,
                 })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
+                Stmt::Declaration(StmtDeclaration::RegSync(StmtReg {
+                    annotations: _,
+                    reg,
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
+                Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg {
+                    annotations: _,
+                    reg,
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations: _,
                     instance,
@@ -1674,6 +1768,7 @@ impl AssertValidityState {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name: _,
                 parameters: _,
+                simulation: _,
             }) => {}
             ModuleBody::Normal(NormalModuleBody { body }) => {
                 let body = self.make_block_index(body);
@@ -1769,7 +1864,7 @@ impl<T: BundleType> Module<T> {
         AssertValidityState {
             module: self.canonical(),
             blocks: vec![],
-            target_states: HashMap::with_capacity(64),
+            target_states: HashMap::with_capacity_and_hasher(64, Default::default()),
         }
         .assert_validity();
     }
@@ -1842,10 +1937,10 @@ impl<CD> RegBuilder<CD, (), ()> {
 }
 
 impl<I, T: Type> RegBuilder<(), I, T> {
-    pub fn clock_domain(
+    pub fn clock_domain<R: ResetType>(
         self,
-        clock_domain: impl ToExpr<Type = ClockDomain>,
-    ) -> RegBuilder<Expr<ClockDomain>, I, T> {
+        clock_domain: impl ToExpr<Type = ClockDomain<R>>,
+    ) -> RegBuilder<Expr<ClockDomain<R>>, I, T> {
         let Self {
             name,
             source_location,
@@ -1863,7 +1958,7 @@ impl<I, T: Type> RegBuilder<(), I, T> {
     }
 }
 
-impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
+impl<T: Type, R: ResetType> RegBuilder<Expr<ClockDomain<R>>, Option<Expr<T>>, T> {
     #[track_caller]
     pub fn build(self) -> Expr<T> {
         let Self {
@@ -2021,6 +2116,7 @@ impl ModuleBuilder {
             ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
                 verilog_name: name.0,
                 parameters: vec![],
+                simulation: None,
             }),
             ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody {
                 body: BuilderModuleBody {
@@ -2029,8 +2125,8 @@ impl ModuleBuilder {
                         incomplete_declarations: vec![],
                         stmts: vec![],
                     }],
-                    annotations_map: HashMap::new(),
-                    memory_map: HashMap::new(),
+                    annotations_map: HashMap::default(),
+                    memory_map: HashMap::default(),
                 },
             }),
         };
@@ -2040,7 +2136,7 @@ impl ModuleBuilder {
             impl_: RefCell::new(ModuleBuilderImpl {
                 body,
                 io: vec![],
-                io_indexes: HashMap::new(),
+                io_indexes: HashMap::default(),
                 module_annotations: vec![],
             }),
         };
@@ -2087,6 +2183,7 @@ impl ModuleBuilder {
             .builder_extern_body()
             .verilog_name = name.intern();
     }
+    #[track_caller]
     pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
         let name = name.as_ref();
         self.impl_
@@ -2099,6 +2196,7 @@ impl ModuleBuilder {
                 value,
             });
     }
+    #[track_caller]
     pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
         let name = name.as_ref();
         let value = value.into();
@@ -2112,6 +2210,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::Integer(value),
             });
     }
+    #[track_caller]
     pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
         let name = name.as_ref();
         let value = value.as_ref();
@@ -2125,6 +2224,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::String(value.intern()),
             });
     }
+    #[track_caller]
     pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
         let name = name.as_ref();
         let raw_verilog = raw_verilog.as_ref();
@@ -2138,6 +2238,26 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()),
             });
     }
+    #[track_caller]
+    pub fn extern_module_simulation<G: ExternModuleSimGenerator>(&self, generator: G) {
+        let mut impl_ = self.impl_.borrow_mut();
+        let simulation = &mut impl_.body.builder_extern_body().simulation;
+        if simulation.is_some() {
+            panic!("already added an extern module simulation");
+        }
+        *simulation = Some(ExternModuleSimulation::new(generator));
+    }
+    #[track_caller]
+    pub fn extern_module_simulation_fn<
+        Args: fmt::Debug + Clone + Hash + Eq + Send + Sync + 'static,
+        Fut: IntoFuture<Output = ()> + 'static,
+    >(
+        &self,
+        args: Args,
+        f: fn(Args, crate::sim::ExternModuleSimulationState) -> Fut,
+    ) {
+        self.extern_module_simulation(crate::sim::SimGeneratorFn { args, f });
+    }
 }
 
 #[track_caller]
@@ -2188,6 +2308,16 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
             reg,
         }
         .into(),
+        TargetBase::RegSync(reg) => StmtReg {
+            annotations: (),
+            reg,
+        }
+        .into(),
+        TargetBase::RegAsync(reg) => StmtReg {
+            annotations: (),
+            reg,
+        }
+        .into(),
         TargetBase::Wire(wire) => StmtWire {
             annotations: (),
             wire,
@@ -2629,3 +2759,50 @@ impl<T: Type> ModuleIO<T> {
         self.ty
     }
 }
+
+#[derive(PartialEq, Eq, Hash, Clone, Copy)]
+pub enum InstantiatedModule {
+    Base(Interned<Module<Bundle>>),
+    Child {
+        parent: Interned<InstantiatedModule>,
+        instance: Interned<Instance<Bundle>>,
+    },
+}
+
+impl InstantiatedModule {
+    pub fn leaf_module(self) -> Interned<Module<Bundle>> {
+        match self {
+            InstantiatedModule::Base(base) => base,
+            InstantiatedModule::Child { instance, .. } => instance.instantiated(),
+        }
+    }
+    fn write_path(self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            InstantiatedModule::Base(base) => fmt::Debug::fmt(&base.name_id(), f),
+            InstantiatedModule::Child { parent, instance } => {
+                parent.write_path(f)?;
+                write!(f, ".{}", instance.name_id())
+            }
+        }
+    }
+}
+
+impl fmt::Debug for InstantiatedModule {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "InstantiatedModule(")?;
+        self.write_path(f)?;
+        write!(f, ": {})", self.leaf_module().name_id())
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+pub struct TargetInInstantiatedModule {
+    pub instantiated_module: InstantiatedModule,
+    pub target: Target,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+pub struct ExprInInstantiatedModule<T: Type> {
+    pub instantiated_module: InstantiatedModule,
+    pub expr: Expr<T>,
+}
diff --git a/crates/fayalite/src/module/transform.rs b/crates/fayalite/src/module/transform.rs
index 4117087..063a1a3 100644
--- a/crates/fayalite/src/module/transform.rs
+++ b/crates/fayalite/src/module/transform.rs
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+pub mod deduce_resets;
 pub mod simplify_enums;
 pub mod simplify_memories;
 pub mod visit;
diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
new file mode 100644
index 0000000..5fb829e
--- /dev/null
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -0,0 +1,2281 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    annotations::{Annotation, TargetedAnnotation},
+    bundle::{BundleField, BundleType},
+    enum_::{EnumType, EnumVariant},
+    expr::{
+        ops::{self, ArrayLiteral},
+        target::{
+            Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
+            TargetPathDynArrayElement, TargetPathElement,
+        },
+        ExprEnum,
+    },
+    formal::FormalKind,
+    int::{SIntValue, UIntValue},
+    intern::{Intern, Interned, Memoize},
+    memory::{DynPortType, MemPort},
+    module::{
+        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
+        ModuleBody, ModuleIO, NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration,
+        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+    },
+    prelude::*,
+    reset::{ResetType, ResetTypeDispatch},
+    util::{HashMap, HashSet},
+};
+use hashbrown::hash_map::Entry;
+use num_bigint::BigInt;
+use petgraph::unionfind::UnionFind;
+use std::{fmt, marker::PhantomData};
+
+#[derive(Debug)]
+pub enum DeduceResetsError {
+    ResetIsNotDrivenByAsyncOrSync { source_location: SourceLocation },
+    ResetIsDrivenByBothAsyncAndSync { source_location: SourceLocation },
+}
+
+impl fmt::Display for DeduceResetsError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            DeduceResetsError::ResetIsNotDrivenByAsyncOrSync { source_location } => {
+                write!(f, "deduce_reset failed: Reset signal is not driven by any AsyncReset or SyncReset signals: {source_location}")
+            }
+            DeduceResetsError::ResetIsDrivenByBothAsyncAndSync { source_location } => {
+                write!(f, "deduce_reset failed: Reset signal is driven by both AsyncReset and SyncReset signals: {source_location}")
+            }
+        }
+    }
+}
+
+impl std::error::Error for DeduceResetsError {}
+
+impl From<DeduceResetsError> for std::io::Error {
+    fn from(value: DeduceResetsError) -> Self {
+        std::io::Error::new(std::io::ErrorKind::Other, value)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum AnyReg {
+    Reg(Reg<CanonicalType, Reset>),
+    RegSync(Reg<CanonicalType, SyncReset>),
+    RegAsync(Reg<CanonicalType, AsyncReset>),
+}
+
+macro_rules! match_any_reg {
+    (
+        $match_expr:expr, $fn:expr
+    ) => {
+        match $match_expr {
+            AnyReg::Reg(reg) => $fn(reg),
+            AnyReg::RegSync(reg) => $fn(reg),
+            AnyReg::RegAsync(reg) => $fn(reg),
+        }
+    };
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum ResetsLayout {
+    NoResets,
+    Reset,
+    SyncReset,
+    AsyncReset,
+    Bundle {
+        fields: Interned<[ResetsLayout]>,
+        reset_count: usize,
+    },
+    Enum {
+        variants: Interned<[ResetsLayout]>,
+        reset_count: usize,
+    },
+    Array {
+        element: Interned<ResetsLayout>,
+        reset_count: usize,
+    },
+}
+
+impl ResetsLayout {
+    fn reset_count(self) -> usize {
+        match self {
+            ResetsLayout::NoResets => 0,
+            ResetsLayout::Reset | ResetsLayout::SyncReset | ResetsLayout::AsyncReset => 1,
+            ResetsLayout::Bundle { reset_count, .. }
+            | ResetsLayout::Enum { reset_count, .. }
+            | ResetsLayout::Array { reset_count, .. } => reset_count,
+        }
+    }
+    fn new(ty: CanonicalType) -> Self {
+        #[derive(Clone, Copy, PartialEq, Eq, Hash)]
+        struct MyMemoize;
+        impl Memoize for MyMemoize {
+            type Input = CanonicalType;
+            type InputOwned = CanonicalType;
+            type Output = ResetsLayout;
+
+            fn inner(self, ty: &Self::Input) -> Self::Output {
+                match *ty {
+                    CanonicalType::UInt(_) => ResetsLayout::NoResets,
+                    CanonicalType::SInt(_) => ResetsLayout::NoResets,
+                    CanonicalType::Bool(_) => ResetsLayout::NoResets,
+                    CanonicalType::Array(ty) => {
+                        let element = ResetsLayout::new(ty.element()).intern_sized();
+                        ResetsLayout::Array {
+                            element,
+                            reset_count: element.reset_count(),
+                        }
+                    }
+                    CanonicalType::Enum(ty) => {
+                        let mut reset_count = 0;
+                        let variants = Interned::from_iter(ty.variants().iter().map(|variant| {
+                            let resets_layout =
+                                variant.ty.map_or(ResetsLayout::NoResets, ResetsLayout::new);
+                            reset_count += resets_layout.reset_count();
+                            resets_layout
+                        }));
+                        ResetsLayout::Enum {
+                            variants,
+                            reset_count,
+                        }
+                    }
+                    CanonicalType::Bundle(ty) => {
+                        let mut reset_count = 0;
+                        let fields = Interned::from_iter(ty.fields().iter().map(|field| {
+                            let resets_layout = ResetsLayout::new(field.ty);
+                            reset_count += resets_layout.reset_count();
+                            resets_layout
+                        }));
+                        ResetsLayout::Bundle {
+                            fields,
+                            reset_count,
+                        }
+                    }
+                    CanonicalType::AsyncReset(_) => ResetsLayout::AsyncReset,
+                    CanonicalType::SyncReset(_) => ResetsLayout::SyncReset,
+                    CanonicalType::Reset(_) => ResetsLayout::Reset,
+                    CanonicalType::Clock(_) => ResetsLayout::NoResets,
+                    CanonicalType::PhantomConst(_) => ResetsLayout::NoResets,
+                }
+            }
+        }
+        MyMemoize.get_owned(ty)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct ResetNodeIndex(usize);
+
+#[derive(Copy, Clone, Debug)]
+struct ResetNode {
+    is_async: Option<bool>,
+    source_location: Option<SourceLocation>,
+}
+
+impl ResetNode {
+    fn union(
+        self,
+        other: Self,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<Self, DeduceResetsError> {
+        match (self.is_async, other.is_async) {
+            (None, None) => Ok(Self {
+                is_async: None,
+                source_location: self.source_location.or(other.source_location),
+            }),
+            (None, is_async @ Some(_)) => Ok(Self {
+                is_async,
+                // prioritize `other`
+                source_location: other.source_location.or(self.source_location),
+            }),
+            (is_async @ Some(_), None) => Ok(Self {
+                is_async,
+                // prioritize `self`
+                source_location: self.source_location.or(other.source_location),
+            }),
+            (Some(self_is_async), Some(other_is_async)) => {
+                if self_is_async == other_is_async {
+                    Ok(Self {
+                        is_async: Some(self_is_async),
+                        source_location: self.source_location.or(other.source_location),
+                    })
+                } else {
+                    Err(DeduceResetsError::ResetIsDrivenByBothAsyncAndSync {
+                        source_location: self
+                            .source_location
+                            .or(other.source_location)
+                            .unwrap_or(fallback_error_source_location),
+                    })
+                }
+            }
+        }
+    }
+}
+
+#[derive(Debug, Default)]
+struct ResetGraph {
+    union_find: UnionFind<usize>,
+    nodes: Vec<ResetNode>,
+}
+
+impl ResetGraph {
+    fn new_node(
+        &mut self,
+        is_async: Option<bool>,
+        source_location: Option<SourceLocation>,
+    ) -> ResetNodeIndex {
+        let index = self.union_find.new_set();
+        assert_eq!(index, self.nodes.len());
+        self.nodes.push(ResetNode {
+            is_async,
+            source_location,
+        });
+        ResetNodeIndex(index)
+    }
+    fn union(
+        &mut self,
+        a: ResetNodeIndex,
+        b: ResetNodeIndex,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<(), DeduceResetsError> {
+        let a = self.union_find.find_mut(a.0);
+        let b = self.union_find.find_mut(b.0);
+        if a != b {
+            self.union_find.union(a, b);
+            let merged = self.union_find.find_mut(a);
+            self.nodes[merged] =
+                self.nodes[a].union(self.nodes[b], fallback_error_source_location)?;
+        }
+        Ok(())
+    }
+    fn is_async(
+        &mut self,
+        node: ResetNodeIndex,
+        fallback_to_sync_reset: bool,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<bool, DeduceResetsError> {
+        let ResetNode {
+            is_async,
+            source_location,
+        } = self.nodes[self.union_find.find_mut(node.0)];
+        if let Some(is_async) = is_async {
+            Ok(is_async)
+        } else if fallback_to_sync_reset {
+            Ok(false)
+        } else {
+            Err(DeduceResetsError::ResetIsNotDrivenByAsyncOrSync {
+                source_location: source_location.unwrap_or(fallback_error_source_location),
+            })
+        }
+    }
+    fn append_new_nodes_for_layout(
+        &mut self,
+        layout: ResetsLayout,
+        node_indexes: &mut Vec<ResetNodeIndex>,
+        source_location: Option<SourceLocation>,
+    ) {
+        match layout {
+            ResetsLayout::NoResets => {}
+            ResetsLayout::Reset => node_indexes.push(self.new_node(None, source_location)),
+            ResetsLayout::SyncReset => {
+                node_indexes.push(self.new_node(Some(false), source_location))
+            }
+            ResetsLayout::AsyncReset => {
+                node_indexes.push(self.new_node(Some(true), source_location))
+            }
+            ResetsLayout::Bundle {
+                fields,
+                reset_count: _,
+            } => {
+                for field in fields {
+                    self.append_new_nodes_for_layout(field, node_indexes, source_location);
+                }
+            }
+            ResetsLayout::Enum {
+                variants,
+                reset_count: _,
+            } => {
+                for variant in variants {
+                    self.append_new_nodes_for_layout(variant, node_indexes, source_location);
+                }
+            }
+            ResetsLayout::Array {
+                element,
+                reset_count: _,
+            } => {
+                self.append_new_nodes_for_layout(*element, node_indexes, source_location);
+            }
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct Resets {
+    ty: CanonicalType,
+    layout: ResetsLayout,
+    node_indexes: Interned<[ResetNodeIndex]>,
+}
+
+impl Resets {
+    fn with_new_nodes(
+        reset_graph: &mut ResetGraph,
+        ty: CanonicalType,
+        source_location: Option<SourceLocation>,
+    ) -> Self {
+        let layout = ResetsLayout::new(ty);
+        let mut node_indexes = Vec::with_capacity(layout.reset_count());
+        reset_graph.append_new_nodes_for_layout(layout, &mut node_indexes, source_location);
+        let node_indexes = Intern::intern_owned(node_indexes);
+        Self {
+            ty,
+            layout,
+            node_indexes,
+        }
+    }
+    fn array_elements(self) -> Self {
+        let array = <Array>::from_canonical(self.ty);
+        let ResetsLayout::Array {
+            element,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        Self {
+            ty: array.element(),
+            layout: *element,
+            node_indexes: self.node_indexes,
+        }
+    }
+    fn bundle_fields(self) -> impl Iterator<Item = Self> {
+        let bundle = Bundle::from_canonical(self.ty);
+        let ResetsLayout::Bundle {
+            fields,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        bundle.fields().into_iter().zip(fields).scan(
+            0,
+            move |start_index, (BundleField { ty, .. }, layout)| {
+                let end_index = *start_index + layout.reset_count();
+                let node_indexes = self.node_indexes[*start_index..end_index].intern();
+                *start_index = end_index;
+                Some(Self {
+                    ty,
+                    layout,
+                    node_indexes,
+                })
+            },
+        )
+    }
+    fn enum_variants(self) -> impl Iterator<Item = Option<Self>> {
+        let enum_ = Enum::from_canonical(self.ty);
+        let ResetsLayout::Enum {
+            variants,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        enum_.variants().into_iter().zip(variants).scan(
+            0,
+            move |start_index, (EnumVariant { ty, .. }, layout)| {
+                let end_index = *start_index + layout.reset_count();
+                let node_indexes = self.node_indexes[*start_index..end_index].intern();
+                *start_index = end_index;
+                Some(ty.map(|ty| Self {
+                    ty,
+                    layout,
+                    node_indexes,
+                }))
+            },
+        )
+    }
+    fn substituted_type(
+        self,
+        reset_graph: &mut ResetGraph,
+        fallback_to_sync_reset: bool,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<CanonicalType, DeduceResetsError> {
+        if self.layout.reset_count() == 0 {
+            return Ok(self.ty);
+        }
+        match self.ty {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Clock(_)
+            | CanonicalType::PhantomConst(_) => Ok(self.ty),
+            CanonicalType::Array(ty) => Ok(CanonicalType::Array(Array::new_dyn(
+                self.array_elements().substituted_type(
+                    reset_graph,
+                    fallback_to_sync_reset,
+                    fallback_error_source_location,
+                )?,
+                ty.len(),
+            ))),
+            CanonicalType::Enum(ty) => Ok(CanonicalType::Enum(Enum::new(Result::from_iter(
+                self.enum_variants().zip(ty.variants()).map(
+                    |(resets, EnumVariant { name, ty: _ })| {
+                        Ok(EnumVariant {
+                            name,
+                            ty: resets
+                                .map(|resets| {
+                                    resets.substituted_type(
+                                        reset_graph,
+                                        fallback_to_sync_reset,
+                                        fallback_error_source_location,
+                                    )
+                                })
+                                .transpose()?,
+                        })
+                    },
+                ),
+            )?))),
+            CanonicalType::Bundle(ty) => Ok(CanonicalType::Bundle(Bundle::new(Result::from_iter(
+                self.bundle_fields().zip(ty.fields()).map(
+                    |(
+                        resets,
+                        BundleField {
+                            name,
+                            flipped,
+                            ty: _,
+                        },
+                    )| {
+                        Ok(BundleField {
+                            name,
+                            flipped,
+                            ty: resets.substituted_type(
+                                reset_graph,
+                                fallback_to_sync_reset,
+                                fallback_error_source_location,
+                            )?,
+                        })
+                    },
+                ),
+            )?))),
+            CanonicalType::Reset(_) => Ok(
+                if reset_graph.is_async(
+                    self.node_indexes[0],
+                    fallback_to_sync_reset,
+                    fallback_error_source_location,
+                )? {
+                    CanonicalType::AsyncReset(AsyncReset)
+                } else {
+                    CanonicalType::SyncReset(SyncReset)
+                },
+            ),
+        }
+    }
+}
+
+#[derive(Debug)]
+struct State {
+    modules_added_to_graph: HashSet<InstantiatedModule>,
+    substituted_modules: HashMap<InstantiatedModule, Module<Bundle>>,
+    expr_resets: HashMap<ExprInInstantiatedModule<CanonicalType>, Resets>,
+    reset_graph: ResetGraph,
+    fallback_to_sync_reset: bool,
+}
+
+impl State {
+    fn get_resets(
+        &self,
+        instantiated_module: InstantiatedModule,
+        expr: impl ToExpr,
+    ) -> Option<Resets> {
+        self.expr_resets
+            .get(&ExprInInstantiatedModule {
+                instantiated_module,
+                expr: Expr::canonical(expr.to_expr()),
+            })
+            .copied()
+    }
+    fn get_or_make_resets(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: impl ToExpr,
+        source_location: Option<SourceLocation>,
+    ) -> (Resets, bool) {
+        let expr = Expr::canonical(expr.to_expr());
+        match self.expr_resets.entry(ExprInInstantiatedModule {
+            instantiated_module,
+            expr,
+        }) {
+            Entry::Occupied(entry) => (*entry.get(), false),
+            Entry::Vacant(entry) => (
+                *entry.insert(Resets::with_new_nodes(
+                    &mut self.reset_graph,
+                    Expr::ty(expr),
+                    source_location,
+                )),
+                true,
+            ),
+        }
+    }
+}
+
+struct PassOutput<T, P: Pass>(P::Output<T>);
+
+impl<T, P: Pass> PassOutput<T, P> {
+    fn new(v: T) -> Self {
+        P::output_new(v)
+    }
+    fn from_fn(f: impl FnOnce() -> T) -> Self {
+        PassOutput::new(()).map(|()| f())
+    }
+    fn map<U>(self, f: impl FnOnce(T) -> U) -> PassOutput<U, P> {
+        P::map(self, f)
+    }
+}
+
+trait PassOutputZip<P: Pass>: Sized {
+    type Zipped;
+    fn zip(self) -> PassOutput<Self::Zipped, P>;
+    fn call<U>(self, f: impl FnOnce(Self::Zipped) -> U) -> PassOutput<U, P> {
+        self.zip().map(f)
+    }
+}
+
+impl<P: Pass> PassOutputZip<P> for () {
+    type Zipped = ();
+    fn zip(self) -> PassOutput<Self::Zipped, P> {
+        PassOutput::new(())
+    }
+}
+
+impl<T, P: Pass> PassOutputZip<P> for (PassOutput<T, P>,) {
+    type Zipped = (T,);
+    fn zip(self) -> PassOutput<Self::Zipped, P> {
+        self.0.map(|v| (v,))
+    }
+}
+
+macro_rules! impl_zip {
+    ($first_arg:ident: $first_T:ident, $($arg:ident: $T:ident),* $(,)?) => {
+        impl_zip!(@step [], [($first_arg: $first_T) $(($arg: $T))*], (),);
+    };
+    (
+        @impl($first_arg:tt,),
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @impl(($first_arg:ident: $first_T:ident),
+            $(($arg:ident: $T:ident),)*),
+        $tuple_pat:tt,
+    ) => {
+        impl<$first_T, $($T,)* P: Pass> PassOutputZip<P> for (PassOutput<$first_T, P>, $(PassOutput<$T, P>),*) {
+            type Zipped = ($first_T, $($T),*);
+            fn zip(self) -> PassOutput<($first_T, $($T),*), P> {
+                let (tuples, $($arg),*) = self;
+                $(let tuples = P::zip(tuples, $arg);)*
+                tuples.map(|$tuple_pat| ($first_arg, $($arg),*))
+            }
+        }
+    };
+    (
+        @step [$($cur:tt)*],
+        [],
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        (),
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), $next_arg,);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], $next_arg,);
+    };
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        $tuple_pat:tt,
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), ($tuple_pat, $next_arg),);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], ($tuple_pat, $next_arg),);
+    };
+}
+
+impl_zip!(t0: T0, t1: T1, t2: T2, t3: T3, t4: T4, t5: T5, t6: T6, t7: T7, t8: T8, t9: T9, t10: T10, t11: T11);
+
+impl<T: FromIterator<A>, P: Pass, A> FromIterator<PassOutput<A, P>> for PassOutput<T, P> {
+    fn from_iter<I: IntoIterator<Item = PassOutput<A, P>>>(iter: I) -> Self {
+        P::output_from_iter(iter)
+    }
+}
+
+trait PassDispatch: Sized {
+    type Input<P: Pass>;
+    type Output<P: Pass>;
+    fn build_reset_graph(
+        self,
+        input: Self::Input<BuildResetGraph>,
+    ) -> Self::Output<BuildResetGraph>;
+    fn substitute_resets(
+        self,
+        input: Self::Input<SubstituteResets>,
+    ) -> Self::Output<SubstituteResets>;
+}
+
+trait Pass: Sized {
+    type Output<T>;
+    fn output_new<T>(v: T) -> PassOutput<T, Self>;
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self>;
+    fn try_array_from_fn<T, const N: usize, E>(
+        f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E>;
+    fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self>;
+    fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self>;
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self>;
+}
+
+struct BuildResetGraph;
+
+impl Pass for BuildResetGraph {
+    type Output<T> = ();
+
+    fn output_new<T>(_v: T) -> PassOutput<T, Self> {
+        PassOutput(())
+    }
+
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self> {
+        iter.into_iter().for_each(|_| {});
+        PassOutput(())
+    }
+
+    fn try_array_from_fn<T, const N: usize, E>(
+        mut f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E> {
+        for i in 0..N {
+            f(i)?;
+        }
+        Ok(PassOutput(()))
+    }
+
+    fn map<T, U>(_v: PassOutput<T, Self>, _f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
+        PassOutput(())
+    }
+
+    fn zip<T, U>(_t: PassOutput<T, Self>, _u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
+        PassOutput(())
+    }
+
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self> {
+        dispatch.build_reset_graph(input)
+    }
+}
+
+struct SubstituteResets;
+
+impl Pass for SubstituteResets {
+    type Output<T> = T;
+
+    fn output_new<T>(v: T) -> PassOutput<T, Self> {
+        PassOutput(v)
+    }
+
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self> {
+        PassOutput(T::from_iter(iter.into_iter().map(|PassOutput(v)| v)))
+    }
+
+    fn try_array_from_fn<T, const N: usize, E>(
+        mut f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E> {
+        let mut retval = [const { None }; N];
+        for i in 0..N {
+            retval[i] = Some(f(i)?.0);
+        }
+        Ok(PassOutput(
+            retval.map(|v| v.expect("just wrote Some to all elements")),
+        ))
+    }
+
+    fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
+        PassOutput(f(v.0))
+    }
+
+    fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
+        PassOutput((t.0, u.0))
+    }
+
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self> {
+        dispatch.substitute_resets(input)
+    }
+}
+
+struct PassArgs<'a, P: Pass> {
+    state: &'a mut State,
+    instantiated_module: InstantiatedModule,
+    fallback_error_source_location: SourceLocation,
+    _phantom: PhantomData<P>,
+}
+
+impl<'a, P: Pass> fmt::Debug for PassArgs<'a, P> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: _,
+        } = self;
+        f.debug_struct("PassArgs")
+            .field("state", state)
+            .field("instantiated_module", instantiated_module)
+            .field(
+                "fallback_error_source_location",
+                fallback_error_source_location,
+            )
+            .finish()
+    }
+}
+
+impl<'a, P: Pass> PassArgs<'a, P> {
+    fn as_mut(&mut self) -> PassArgs<'_, P> {
+        let PassArgs {
+            ref mut state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: _,
+        } = *self;
+        PassArgs {
+            state: &mut **state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: PhantomData,
+        }
+    }
+    fn get_resets(&self, expr: impl ToExpr) -> Option<Resets> {
+        self.state.get_resets(self.instantiated_module, expr)
+    }
+    fn get_or_make_resets(
+        &mut self,
+        expr: impl ToExpr,
+        source_location: Option<SourceLocation>,
+    ) -> (Resets, bool) {
+        self.state
+            .get_or_make_resets(self.instantiated_module, expr, source_location)
+    }
+    fn union(
+        &mut self,
+        a: Resets,
+        b: Resets,
+        fallback_error_source_location: Option<SourceLocation>,
+    ) -> Result<(), DeduceResetsError> {
+        assert_eq!(a.layout, b.layout);
+        assert!(
+            a.ty.can_connect(b.ty),
+            "can't connect types! a:\n{a:?}\nb:\n{b:?}"
+        );
+        for (a_node_index, b_node_index) in a.node_indexes.into_iter().zip(b.node_indexes) {
+            self.state.reset_graph.union(
+                a_node_index,
+                b_node_index,
+                fallback_error_source_location.unwrap_or(self.fallback_error_source_location),
+            )?;
+        }
+        Ok(())
+    }
+}
+
+trait RunPass<P: Pass>: Sized {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError>;
+}
+
+trait RunPassDispatch: Sized {
+    fn build_reset_graph(
+        &self,
+        pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError>;
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError>;
+    fn dispatch<P: Pass>(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        struct Dispatch<'a, T>(T, PhantomData<&'a mut ()>);
+        impl<'a, T: RunPassDispatch> PassDispatch for Dispatch<'a, &'_ T> {
+            type Input<P: Pass> = PassArgs<'a, P>;
+            type Output<P: Pass> = Result<PassOutput<T, P>, DeduceResetsError>;
+
+            fn build_reset_graph(
+                self,
+                input: Self::Input<BuildResetGraph>,
+            ) -> Self::Output<BuildResetGraph> {
+                self.0.build_reset_graph(input)
+            }
+            fn substitute_resets(
+                self,
+                input: Self::Input<SubstituteResets>,
+            ) -> Self::Output<SubstituteResets> {
+                self.0.substitute_resets(input)
+            }
+        }
+        P::dispatch(Dispatch(self, PhantomData), pass_args)
+    }
+}
+
+impl<T: RunPassDispatch, P: Pass> RunPass<P> for T {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        T::dispatch(self, pass_args)
+    }
+}
+
+trait RunPassExpr: ToExpr + Sized {
+    type Args<'a>: IntoIterator<Item = Expr<CanonicalType>> + 'a
+    where
+        Self: 'a;
+    fn args<'a>(&'a self) -> Self::Args<'a>;
+    fn source_location(&self) -> Option<SourceLocation>;
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError>;
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError>;
+}
+
+impl<T: RunPassExpr> RunPassDispatch for T {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        let source_location = self.source_location();
+        let (resets, _) = pass_args.get_or_make_resets(self, source_location);
+        let args_resets = Result::from_iter(self.args().into_iter().map(|arg| {
+            arg.run_pass(pass_args.as_mut())?;
+            let (resets, _) = pass_args.get_or_make_resets(arg, source_location);
+            Ok(resets)
+        }))?;
+        self.union_parts(resets, args_resets, pass_args)?;
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let source_location = self.source_location();
+        let (resets, _) = pass_args.get_or_make_resets(self, source_location);
+        let ty = resets.substituted_type(
+            &mut pass_args.state.reset_graph,
+            pass_args.state.fallback_to_sync_reset,
+            pass_args.fallback_error_source_location,
+        )?;
+        let new_args = Result::from_iter(
+            self.args()
+                .into_iter()
+                .map(|arg| Ok(arg.run_pass(pass_args.as_mut())?.0)),
+        )?;
+        Ok(PassOutput(self.new(ty, new_args)?))
+    }
+}
+
+impl<T: RunPass<P> + Intern + Clone, P: Pass> RunPass<P> for Interned<T> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(T::run_pass(self, pass_args)?.map(Intern::intern_sized))
+    }
+}
+
+impl<T: RunPass<P> + Clone, P: Pass> RunPass<P> for Interned<[T]>
+where
+    [T]: Intern,
+{
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Result::from_iter(self.iter().map(|v| v.run_pass(pass_args.as_mut())))
+    }
+}
+
+impl<T: RunPass<P>, P: Pass, const N: usize> RunPass<P> for [T; N] {
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        P::try_array_from_fn(|i| self[i].run_pass(pass_args.as_mut()))
+    }
+}
+
+impl<T: RunPass<P>, P: Pass> RunPass<P> for Option<T> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        match self {
+            Some(v) => Ok(v.run_pass(pass_args)?.map(Some)),
+            None => Ok(PassOutput::new(None)),
+        }
+    }
+}
+
+fn reg_expr_run_pass<P: Pass, R: ResetType>(
+    reg: &Reg<CanonicalType, R>,
+    pass_args: PassArgs<'_, P>,
+) -> Result<PassOutput<ExprEnum, P>, DeduceResetsError> {
+    Ok(AnyReg::from(*reg)
+        .run_pass(pass_args)?
+        .map(|reg| match_any_reg!(reg, ExprEnum::from)))
+}
+
+fn cast_bit_op<P: Pass, T: Type, A: Type>(
+    expr: impl ToExpr<Type = T>,
+    arg: Expr<A>,
+    pass_args: PassArgs<'_, P>,
+) -> Result<PassOutput<ExprEnum, P>, DeduceResetsError> {
+    struct Dispatch<'a, T: Type, A: Type> {
+        expr: Expr<T>,
+        arg: Expr<A>,
+        _phantom: PhantomData<&'a mut ()>,
+    }
+    impl<'a, T: Type, A: Type> PassDispatch for Dispatch<'a, T, A> {
+        type Input<P: Pass> = PassArgs<'a, P>;
+        type Output<P: Pass> = Result<PassOutput<ExprEnum, P>, DeduceResetsError>;
+
+        fn build_reset_graph(
+            self,
+            mut pass_args: Self::Input<BuildResetGraph>,
+        ) -> Self::Output<BuildResetGraph> {
+            Expr::canonical(self.arg).run_pass(pass_args.as_mut())?;
+            let (expr_resets, _) = pass_args.get_or_make_resets(self.expr, None);
+            let (arg_resets, _) = pass_args.get_or_make_resets(self.arg, None);
+            // don't use PassArgs::union since types don't match and we want to just union resets if they exist
+            for (expr_node_index, arg_node_index) in expr_resets
+                .node_indexes
+                .into_iter()
+                .zip(arg_resets.node_indexes)
+            {
+                pass_args.state.reset_graph.union(
+                    expr_node_index,
+                    arg_node_index,
+                    pass_args.fallback_error_source_location,
+                )?;
+            }
+            Ok(PassOutput(()))
+        }
+
+        fn substitute_resets(
+            self,
+            mut pass_args: Self::Input<SubstituteResets>,
+        ) -> Self::Output<SubstituteResets> {
+            let resets = pass_args
+                .get_resets(self.expr)
+                .expect("added resets in build_reset_graph");
+            let arg = Expr::canonical(self.arg).run_pass(pass_args.as_mut())?;
+            let ty = resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                pass_args.fallback_error_source_location,
+            )?;
+            Ok(arg.map(|arg| {
+                macro_rules! match_expr_ty {
+                    ($arg:ident, $($Variant:ident),*) => {
+                        match ty {
+                            CanonicalType::Array(_)
+                            | CanonicalType::Enum(_)
+                            | CanonicalType::Bundle(_)
+                            | CanonicalType::Reset(_)
+                            | CanonicalType::PhantomConst(_) => unreachable!(),
+                            $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)*
+                        }
+                    };
+                }
+                macro_rules! match_arg_ty {
+                    ($($Variant:ident),*) => {
+                        *match Expr::ty(arg) {
+                            CanonicalType::Array(_)
+                            | CanonicalType::Enum(_)
+                            | CanonicalType::Bundle(_)
+                            | CanonicalType::Reset(_) => unreachable!(),
+                            CanonicalType::PhantomConst(_) => Expr::expr_enum(arg),
+                            $(CanonicalType::$Variant(_) => {
+                                let arg = Expr::<$Variant>::from_canonical(arg);
+                                match_expr_ty!(arg, UInt, SInt, Bool, AsyncReset, SyncReset, Clock)
+                            })*
+                        }
+                    };
+                }
+                match_arg_ty!(UInt, SInt, Bool, AsyncReset, SyncReset, Clock)
+            }))
+        }
+    }
+    P::dispatch(
+        Dispatch {
+            expr: expr.to_expr(),
+            arg,
+            _phantom: PhantomData,
+        },
+        pass_args,
+    )
+}
+
+impl<P: Pass> RunPass<P> for ExprEnum {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        match self {
+            ExprEnum::UIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BoolLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::PhantomConst(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BundleLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ArrayLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::EnumLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Uninit(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Neg(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::AddU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::AddS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SubU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SubS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::MulU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::MulS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DivU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DivS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::RemU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::RemS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShlU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShlS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShlU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShlS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastUIntToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSIntToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastBoolToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastUIntToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSIntToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastBoolToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FieldAccess(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::VariantAccess(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ArrayIndex(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynArrayIndex(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitAndU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitAndS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitOrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitOrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitXorU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitXorS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SliceUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SliceSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastToBits(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBitsTo(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ModuleIO(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Instance(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Wire(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Reg(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::RegSync(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::RegAsync(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::MemPort(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+        }
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<CanonicalType> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::expr_enum(*self)
+            .run_pass(pass_args)?
+            .map(|expr_enum| expr_enum.to_expr()))
+    }
+}
+
+impl<P: Pass, Width: Size> RunPass<P> for Expr<UIntType<Width>> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass, Width: Size> RunPass<P> for Expr<SIntType<Width>> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<Bool> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<Enum> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<Clock> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl RunPassExpr for ops::Uninit {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(ops::Uninit::new(ty))
+    }
+}
+
+impl RunPassExpr for ops::BundleLiteral {
+    type Args<'a> = Interned<[Expr<CanonicalType>]>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.field_values()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        for (resets_field, field_expr_resets) in resets.bundle_fields().zip(args_resets) {
+            pass_args.union(resets_field, field_expr_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(ops::BundleLiteral::new(
+            Bundle::from_canonical(ty),
+            Intern::intern_owned(new_args),
+        ))
+    }
+}
+
+impl RunPassExpr for ArrayLiteral<CanonicalType, DynSize> {
+    type Args<'a> = Interned<[Expr<CanonicalType>]>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.element_values()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        let resets_elements = resets.array_elements();
+        for arg_resets in args_resets {
+            pass_args.union(resets_elements, arg_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            <Array>::from_canonical(ty).element(),
+            Intern::intern_owned(new_args),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::EnumLiteral {
+    type Args<'a> = Option<Expr<CanonicalType>>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.variant_value()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        if let Some(Some(variant_resets)) = resets.enum_variants().nth(self.variant_index()) {
+            pass_args.union(variant_resets, args_resets[0], None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Enum::from_canonical(ty),
+            self.variant_index(),
+            new_args.get(0).copied(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::FieldAccess {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        let Some(field_resets) = args_resets[0].bundle_fields().nth(self.field_index()) else {
+            unreachable!();
+        };
+        pass_args.union(resets, field_resets, None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Expr::from_canonical(new_args[0]),
+            self.field_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::VariantAccess {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        if let Some(Some(variant_resets)) = args_resets[0].enum_variants().nth(self.variant_index())
+        {
+            pass_args.union(resets, variant_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Expr::from_canonical(new_args[0]),
+            self.variant_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::ArrayIndex {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        pass_args.union(resets, args_resets[0].array_elements(), None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            Expr::from_canonical(new_args[0]),
+            self.element_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::DynArrayIndex {
+    type Args<'a> = [Expr<CanonicalType>; 2];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [
+            Expr::canonical(self.base()),
+            Expr::canonical(self.element_index()),
+        ]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        pass_args.union(resets, args_resets[0].array_elements(), None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            Expr::from_canonical(new_args[0]),
+            Expr::from_canonical(new_args[1]),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::CastBitsTo {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.arg())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(Expr::from_canonical(new_args[0]), ty))
+    }
+}
+
+impl RunPassExpr for ModuleIO<CanonicalType> {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        Some(self.source_location())
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_unchecked(
+            self.containing_module_name_id(),
+            self.name_id(),
+            self.source_location(),
+            self.is_input(),
+            ty,
+        ))
+    }
+}
+
+impl RunPassExpr for Wire<CanonicalType> {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        Some(self.source_location())
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_unchecked(
+            self.scoped_name(),
+            self.source_location(),
+            ty,
+        ))
+    }
+}
+
+impl<T: ResetType> From<Reg<CanonicalType, T>> for AnyReg {
+    fn from(value: Reg<CanonicalType, T>) -> Self {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = AnyReg;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                AnyReg::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                AnyReg::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                AnyReg::RegAsync(input)
+            }
+        }
+        T::dispatch(value, Dispatch)
+    }
+}
+
+impl RunPassDispatch for AnyReg {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        match_any_reg!(self, |reg: &Reg<CanonicalType, _>| {
+            pass_args
+                .get_or_make_resets(Expr::canonical(reg.to_expr()), Some(reg.source_location()));
+            reg.init().run_pass(pass_args.as_mut())?;
+            Expr::canonical(reg.clock_domain()).run_pass(pass_args)?;
+            Ok(PassOutput(()))
+        })
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        match_any_reg!(self, |reg: &Reg<CanonicalType, _>| {
+            let scoped_name = reg.scoped_name();
+            let source_location = reg.source_location();
+            let resets = pass_args
+                .get_resets(Expr::canonical(reg.to_expr()))
+                .expect("added resets in build_reset_graph");
+            let ty = resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                source_location,
+            )?;
+            let init = reg.init().run_pass(pass_args.as_mut())?.0;
+            let clock_domain = Expr::<Bundle>::from_canonical(
+                Expr::canonical(reg.clock_domain()).run_pass(pass_args)?.0,
+            );
+            match Expr::ty(clock_domain)
+                .field_by_name("rst".intern())
+                .expect("ClockDomain has rst field")
+                .ty
+            {
+                CanonicalType::AsyncReset(_) => {
+                    Ok(PassOutput(AnyReg::RegAsync(Reg::new_unchecked(
+                        scoped_name,
+                        source_location,
+                        ty,
+                        Expr::from_bundle(clock_domain),
+                        init,
+                    ))))
+                }
+                CanonicalType::SyncReset(_) => Ok(PassOutput(AnyReg::RegSync(Reg::new_unchecked(
+                    scoped_name,
+                    source_location,
+                    ty,
+                    Expr::from_bundle(clock_domain),
+                    init,
+                )))),
+                CanonicalType::UInt(_)
+                | CanonicalType::SInt(_)
+                | CanonicalType::Bool(_)
+                | CanonicalType::Array(_)
+                | CanonicalType::Enum(_)
+                | CanonicalType::Bundle(_)
+                | CanonicalType::Reset(_)
+                | CanonicalType::Clock(_)
+                | CanonicalType::PhantomConst(_) => unreachable!(),
+            }
+        })
+    }
+}
+
+impl RunPassDispatch for Instance<Bundle> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        self.instantiated().run_pass(PassArgs::<BuildResetGraph> {
+            state: pass_args.state,
+            instantiated_module: InstantiatedModule::Child {
+                parent: pass_args.instantiated_module.intern_sized(),
+                instance: self.intern(),
+            },
+            fallback_error_source_location: self.instantiated().source_location(),
+            _phantom: PhantomData,
+        })?;
+        let (resets, _) = pass_args.get_or_make_resets(self, Some(self.source_location()));
+        for (resets_field, module_io) in resets.bundle_fields().zip(self.instantiated().module_io())
+        {
+            let (module_io_resets, _) = pass_args.get_or_make_resets(
+                module_io.module_io,
+                Some(self.instantiated().source_location()),
+            );
+            pass_args.union(resets_field, module_io_resets, Some(self.source_location()))?;
+        }
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let PassOutput(instantiated) =
+            self.instantiated().run_pass(PassArgs::<SubstituteResets> {
+                state: pass_args.state,
+                instantiated_module: InstantiatedModule::Child {
+                    parent: pass_args.instantiated_module.intern_sized(),
+                    instance: self.intern(),
+                },
+                fallback_error_source_location: self.instantiated().source_location(),
+                _phantom: PhantomData,
+            })?;
+        Ok(PassOutput(Self::new_unchecked(
+            self.scoped_name(),
+            instantiated,
+            self.source_location(),
+        )))
+    }
+}
+
+macro_rules! impl_run_pass_copy {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<P: Pass, $($generics)*> RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                _pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                Ok(PassOutput::new(*self))
+            }
+        }
+    };
+}
+
+macro_rules! impl_run_pass_clone {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<P: Pass, $($generics)*> RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                _pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                Ok(PassOutput::from_fn(|| self.clone()))
+            }
+        }
+    };
+}
+
+impl_run_pass_clone!([] BigInt);
+impl_run_pass_clone!([] SIntValue);
+impl_run_pass_clone!([] std::ops::Range<usize>);
+impl_run_pass_clone!([] UIntValue);
+impl_run_pass_copy!([] BlackBoxInlineAnnotation);
+impl_run_pass_copy!([] BlackBoxPathAnnotation);
+impl_run_pass_copy!([] bool);
+impl_run_pass_copy!([] CustomFirrtlAnnotation);
+impl_run_pass_copy!([] DocStringAnnotation);
+impl_run_pass_copy!([] DontTouchAnnotation);
+impl_run_pass_copy!([] ExternModuleBody);
+impl_run_pass_copy!([] Interned<str>);
+impl_run_pass_copy!([] NameId);
+impl_run_pass_copy!([] SInt);
+impl_run_pass_copy!([] SourceLocation);
+impl_run_pass_copy!([] SVAttributeAnnotation);
+impl_run_pass_copy!([] UInt);
+impl_run_pass_copy!([] usize);
+impl_run_pass_copy!([] FormalKind);
+impl_run_pass_copy!([] PhantomConst);
+
+macro_rules! impl_run_pass_for_struct {
+    (
+        $(#[adjust_pass_args = $adjust_pass_args:expr])?
+        #[constructor = $constructor:expr]
+        impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+            $($field:ident $(($($args:tt)*))?: _,)*
+        }
+    ) => {
+        impl<P: Pass, $($generics)*> $RunPass<P> for $ty {
+            #[allow(unused_mut, unused_variables)]
+            fn run_pass(
+                &self,
+                mut pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                $($adjust_pass_args(self, &mut pass_args);)?
+                Ok(($(self.$field$(($($args)*))?.run_pass(pass_args.as_mut())?,)*).call(|($($field,)*)| $constructor))
+            }
+        }
+    };
+    (
+        $(#[adjust_pass_args = $adjust_pass_args:expr])?
+        impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+            $($field:ident: _,)*
+        }
+    ) => {
+        impl_run_pass_for_struct! {
+            $(#[adjust_pass_args = $adjust_pass_args])?
+            #[constructor = {
+                type Ty<T> = T;
+                Ty::<$ty> { $($field,)* }
+            }]
+            impl[$($generics)*] $RunPass for $ty {
+                $($field: _,)*
+            }
+        }
+    };
+}
+
+macro_rules! impl_run_pass_for_enum {
+    (impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+        $($variant:ident($arg:ident),)*
+    }) => {
+        impl<P: Pass, $($generics)*> $RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                type Ty<T> = T;
+                match self {
+                    $(Ty::<$ty>::$variant($arg) => Ok($arg.run_pass(pass_args)?.map(<$ty>::$variant)),)*
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_run_pass_for_unary_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(arg)]
+            impl[] RunPass for $path {
+                arg(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_unary_op!(ops::NotU);
+impl_run_pass_for_unary_op!(ops::NotS);
+impl_run_pass_for_unary_op!(ops::NotB);
+impl_run_pass_for_unary_op!(ops::Neg);
+impl_run_pass_for_unary_op!(ops::CastBoolToUInt);
+impl_run_pass_for_unary_op!(ops::CastBoolToSInt);
+impl_run_pass_for_unary_op!(ops::CastUIntToBool);
+impl_run_pass_for_unary_op!(ops::CastSIntToBool);
+impl_run_pass_for_unary_op!(ops::CastBoolToClock);
+impl_run_pass_for_unary_op!(ops::CastUIntToClock);
+impl_run_pass_for_unary_op!(ops::CastSIntToClock);
+impl_run_pass_for_unary_op!(ops::CastClockToBool);
+impl_run_pass_for_unary_op!(ops::CastClockToUInt);
+impl_run_pass_for_unary_op!(ops::CastClockToSInt);
+impl_run_pass_for_unary_op!(ops::ReduceBitAndU);
+impl_run_pass_for_unary_op!(ops::ReduceBitAndS);
+impl_run_pass_for_unary_op!(ops::ReduceBitOrU);
+impl_run_pass_for_unary_op!(ops::ReduceBitOrS);
+impl_run_pass_for_unary_op!(ops::ReduceBitXorU);
+impl_run_pass_for_unary_op!(ops::ReduceBitXorS);
+
+macro_rules! impl_run_pass_for_binary_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(lhs, rhs)]
+            impl[] RunPass for $path {
+                lhs(): _,
+                rhs(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_binary_op!(ops::BitAndU);
+impl_run_pass_for_binary_op!(ops::BitAndS);
+impl_run_pass_for_binary_op!(ops::BitAndB);
+impl_run_pass_for_binary_op!(ops::BitOrU);
+impl_run_pass_for_binary_op!(ops::BitOrS);
+impl_run_pass_for_binary_op!(ops::BitOrB);
+impl_run_pass_for_binary_op!(ops::BitXorU);
+impl_run_pass_for_binary_op!(ops::BitXorS);
+impl_run_pass_for_binary_op!(ops::BitXorB);
+impl_run_pass_for_binary_op!(ops::AddU);
+impl_run_pass_for_binary_op!(ops::AddS);
+impl_run_pass_for_binary_op!(ops::SubU);
+impl_run_pass_for_binary_op!(ops::SubS);
+impl_run_pass_for_binary_op!(ops::MulU);
+impl_run_pass_for_binary_op!(ops::MulS);
+impl_run_pass_for_binary_op!(ops::DivU);
+impl_run_pass_for_binary_op!(ops::DivS);
+impl_run_pass_for_binary_op!(ops::RemU);
+impl_run_pass_for_binary_op!(ops::RemS);
+impl_run_pass_for_binary_op!(ops::DynShlU);
+impl_run_pass_for_binary_op!(ops::DynShlS);
+impl_run_pass_for_binary_op!(ops::DynShrU);
+impl_run_pass_for_binary_op!(ops::DynShrS);
+impl_run_pass_for_binary_op!(ops::FixedShlU);
+impl_run_pass_for_binary_op!(ops::FixedShlS);
+impl_run_pass_for_binary_op!(ops::FixedShrU);
+impl_run_pass_for_binary_op!(ops::FixedShrS);
+impl_run_pass_for_binary_op!(ops::CmpLtB);
+impl_run_pass_for_binary_op!(ops::CmpLeB);
+impl_run_pass_for_binary_op!(ops::CmpGtB);
+impl_run_pass_for_binary_op!(ops::CmpGeB);
+impl_run_pass_for_binary_op!(ops::CmpEqB);
+impl_run_pass_for_binary_op!(ops::CmpNeB);
+impl_run_pass_for_binary_op!(ops::CmpLtU);
+impl_run_pass_for_binary_op!(ops::CmpLeU);
+impl_run_pass_for_binary_op!(ops::CmpGtU);
+impl_run_pass_for_binary_op!(ops::CmpGeU);
+impl_run_pass_for_binary_op!(ops::CmpEqU);
+impl_run_pass_for_binary_op!(ops::CmpNeU);
+impl_run_pass_for_binary_op!(ops::CmpLtS);
+impl_run_pass_for_binary_op!(ops::CmpLeS);
+impl_run_pass_for_binary_op!(ops::CmpGtS);
+impl_run_pass_for_binary_op!(ops::CmpGeS);
+impl_run_pass_for_binary_op!(ops::CmpEqS);
+impl_run_pass_for_binary_op!(ops::CmpNeS);
+
+macro_rules! impl_run_pass_for_int_cast_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(arg, ty)]
+            impl[] RunPass for $path {
+                arg(): _,
+                ty(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_int_cast_op!(ops::CastUIntToUInt);
+impl_run_pass_for_int_cast_op!(ops::CastUIntToSInt);
+impl_run_pass_for_int_cast_op!(ops::CastSIntToUInt);
+impl_run_pass_for_int_cast_op!(ops::CastSIntToSInt);
+
+impl_run_pass_for_struct! {
+    #[constructor = ops::SliceUInt::new(base, range)]
+    impl[] RunPass for ops::SliceUInt {
+        base(): _,
+        range(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = ops::SliceSInt::new(base, range)]
+    impl[] RunPass for ops::SliceSInt {
+        base(): _,
+        range(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = ops::CastToBits::new(arg)]
+    impl[] RunPass for ops::CastToBits {
+        arg(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtFormal {
+        kind: _,
+        clk: _,
+        pred: _,
+        en: _,
+        text: _,
+        source_location: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtIf {
+        cond: _,
+        source_location: _,
+        blocks: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtMatch {
+        expr: _,
+        source_location: _,
+        blocks: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtWire {
+        annotations: _,
+        wire: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtInstance {
+        annotations: _,
+        instance: _,
+    }
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for Stmt {
+        Connect(v),
+        Formal(v),
+        If(v),
+        Match(v),
+        Declaration(v),
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for Block {
+        memories: _,
+        stmts: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for NormalModuleBody {
+        body: _,
+    }
+}
+
+impl_run_pass_copy!([] MemPort<DynPortType>); // Mem can't contain any `Reset` types
+impl_run_pass_copy!([] Mem); // Mem can't contain any `Reset` types
+
+impl RunPassDispatch for StmtConnect {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        let Self {
+            lhs,
+            rhs,
+            source_location,
+        } = *self;
+        pass_args.fallback_error_source_location = source_location;
+        lhs.run_pass(pass_args.as_mut())?;
+        rhs.run_pass(pass_args.as_mut())?;
+        let (lhs_resets, _) = pass_args.get_or_make_resets(lhs, Some(source_location));
+        let (rhs_resets, _) = pass_args.get_or_make_resets(rhs, Some(source_location));
+        pass_args.union(lhs_resets, rhs_resets, Some(source_location))?;
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let StmtConnect {
+            lhs,
+            rhs,
+            source_location,
+        } = *self;
+        pass_args.fallback_error_source_location = source_location;
+        let lhs = lhs.run_pass(pass_args.as_mut())?.0;
+        let rhs = rhs.run_pass(pass_args)?.0;
+        Ok(PassOutput(StmtConnect {
+            lhs,
+            rhs,
+            source_location,
+        }))
+    }
+}
+
+impl<P: Pass> RunPass<P> for TargetBase {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        let reg: AnyReg = match self {
+            TargetBase::ModuleIO(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::ModuleIO)),
+            TargetBase::MemPort(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::MemPort)),
+            &TargetBase::Reg(v) => v.into(),
+            &TargetBase::RegSync(v) => v.into(),
+            &TargetBase::RegAsync(v) => v.into(),
+            TargetBase::Wire(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Wire)),
+            TargetBase::Instance(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Instance)),
+        };
+        Ok(reg.run_pass(pass_args)?.map(|reg| match reg {
+            AnyReg::Reg(reg) => TargetBase::Reg(reg),
+            AnyReg::RegSync(reg) => TargetBase::RegSync(reg),
+            AnyReg::RegAsync(reg) => TargetBase::RegAsync(reg),
+        }))
+    }
+}
+
+impl<P: Pass> RunPass<P> for StmtDeclaration {
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        let (annotations, reg) = match self {
+            StmtDeclaration::Wire(v) => {
+                return Ok(v.run_pass(pass_args)?.map(StmtDeclaration::Wire))
+            }
+            &StmtDeclaration::Reg(StmtReg { annotations, reg }) => (annotations, AnyReg::from(reg)),
+            &StmtDeclaration::RegSync(StmtReg { annotations, reg }) => {
+                (annotations, AnyReg::from(reg))
+            }
+            &StmtDeclaration::RegAsync(StmtReg { annotations, reg }) => {
+                (annotations, AnyReg::from(reg))
+            }
+            StmtDeclaration::Instance(v) => {
+                return Ok(v.run_pass(pass_args)?.map(StmtDeclaration::Instance))
+            }
+        };
+        let annotations = annotations.run_pass(pass_args.as_mut())?;
+        let reg = reg.run_pass(pass_args)?;
+        Ok((annotations, reg).call(|(annotations, reg)| match reg {
+            AnyReg::Reg(reg) => StmtReg { annotations, reg }.into(),
+            AnyReg::RegSync(reg) => StmtReg { annotations, reg }.into(),
+            AnyReg::RegAsync(reg) => StmtReg { annotations, reg }.into(),
+        }))
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathBundleField {
+        name: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathArrayElement {
+        index: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathDynArrayElement {}
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for TargetPathElement {
+        BundleField(v),
+        ArrayElement(v),
+        DynArrayElement(v),
+    }
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for Target {
+        Base(v),
+        Child(v),
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = TargetChild::new(parent, path_element)]
+    impl[] RunPass for TargetChild {
+        parent(): _,
+        path_element(): _,
+    }
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for Annotation {
+        DontTouch(v),
+        SVAttribute(v),
+        BlackBoxInline(v),
+        BlackBoxPath(v),
+        DocString(v),
+        CustomFirrtl(v),
+    }
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for ModuleBody {
+        Normal(v),
+        Extern(v),
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = TargetedAnnotation::new(target, annotation)]
+    impl[] RunPass for TargetedAnnotation {
+        target(): _,
+        annotation(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for AnnotatedModuleIO {
+        annotations: _,
+        module_io: _,
+    }
+}
+
+impl RunPassDispatch for Module<Bundle> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        pass_args.fallback_error_source_location = self.source_location();
+        if pass_args
+            .state
+            .modules_added_to_graph
+            .insert(pass_args.instantiated_module)
+        {
+            self.name_id().run_pass(pass_args.as_mut())?;
+            self.source_location().run_pass(pass_args.as_mut())?;
+            self.module_io().run_pass(pass_args.as_mut())?;
+            self.body().run_pass(pass_args.as_mut())?;
+            self.module_annotations().run_pass(pass_args.as_mut())?;
+        }
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        pass_args.fallback_error_source_location = self.source_location();
+        if let Some(&retval) = pass_args
+            .state
+            .substituted_modules
+            .get(&pass_args.instantiated_module)
+        {
+            return Ok(PassOutput(retval));
+        }
+        let PassOutput(name_id) = self.name_id().run_pass(pass_args.as_mut())?;
+        let PassOutput(source_location) = self.source_location().run_pass(pass_args.as_mut())?;
+        let PassOutput(module_io) = self.module_io().run_pass(pass_args.as_mut())?;
+        let PassOutput(body) = self.body().run_pass(pass_args.as_mut())?;
+        let PassOutput(module_annotations) =
+            self.module_annotations().run_pass(pass_args.as_mut())?;
+        let retval = Module::new_unchecked(
+            name_id,
+            source_location,
+            body,
+            module_io,
+            module_annotations,
+        );
+        pass_args
+            .state
+            .substituted_modules
+            .insert(pass_args.instantiated_module, retval);
+        Ok(PassOutput(retval))
+    }
+}
+
+pub fn deduce_resets(
+    module: Interned<Module<Bundle>>,
+    fallback_to_sync_reset: bool,
+) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
+    let mut state = State {
+        modules_added_to_graph: HashSet::default(),
+        substituted_modules: HashMap::default(),
+        expr_resets: HashMap::default(),
+        reset_graph: ResetGraph::default(),
+        fallback_to_sync_reset,
+    };
+    RunPass::<BuildResetGraph>::run_pass(
+        &*module,
+        PassArgs {
+            state: &mut state,
+            instantiated_module: InstantiatedModule::Base(module),
+            fallback_error_source_location: module.source_location(),
+            _phantom: PhantomData,
+        },
+    )?;
+    Ok(RunPass::<SubstituteResets>::run_pass(
+        &*module,
+        PassArgs {
+            state: &mut state,
+            instantiated_module: InstantiatedModule::Base(module),
+            fallback_error_source_location: module.source_location(),
+            _phantom: PhantomData,
+        },
+    )?
+    .0
+    .intern_sized())
+}
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index bb57cf0..333451d 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -18,10 +18,10 @@ use crate::{
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
+    util::HashMap,
     wire::Wire,
 };
 use core::fmt;
-use hashbrown::HashMap;
 
 #[derive(Debug)]
 pub enum SimplifyEnumsError {
@@ -69,7 +69,8 @@ fn contains_any_enum_types(ty: CanonicalType) -> bool {
                 | CanonicalType::AsyncReset(_)
                 | CanonicalType::SyncReset(_)
                 | CanonicalType::Reset(_)
-                | CanonicalType::Clock(_) => false,
+                | CanonicalType::Clock(_)
+                | CanonicalType::PhantomConst(_) => false,
             }
         }
     }
@@ -512,7 +513,8 @@ impl State {
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
             | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => unreachable!(),
+            | CanonicalType::Clock(_)
+            | CanonicalType::PhantomConst(_) => unreachable!(),
         }
     }
 }
@@ -577,7 +579,8 @@ fn connect_port(
         | (CanonicalType::Clock(_), _)
         | (CanonicalType::AsyncReset(_), _)
         | (CanonicalType::SyncReset(_), _)
-        | (CanonicalType::Reset(_), _) => unreachable!(
+        | (CanonicalType::Reset(_), _)
+        | (CanonicalType::PhantomConst(_), _) => unreachable!(
             "trying to connect memory ports:\n{:?}\n{:?}",
             Expr::ty(lhs),
             Expr::ty(rhs),
@@ -665,6 +668,7 @@ impl Folder for State {
             ExprEnum::UIntLiteral(_)
             | ExprEnum::SIntLiteral(_)
             | ExprEnum::BoolLiteral(_)
+            | ExprEnum::PhantomConst(_)
             | ExprEnum::BundleLiteral(_)
             | ExprEnum::ArrayLiteral(_)
             | ExprEnum::Uninit(_)
@@ -764,7 +768,9 @@ impl Folder for State {
             | ExprEnum::ModuleIO(_)
             | ExprEnum::Instance(_)
             | ExprEnum::Wire(_)
-            | ExprEnum::Reg(_) => op.default_fold(self),
+            | ExprEnum::Reg(_)
+            | ExprEnum::RegSync(_)
+            | ExprEnum::RegAsync(_) => op.default_fold(self),
         }
     }
 
@@ -921,7 +927,8 @@ impl Folder for State {
             | CanonicalType::Clock(_)
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
-            | CanonicalType::Reset(_) => canonical_type.default_fold(self),
+            | CanonicalType::Reset(_)
+            | CanonicalType::PhantomConst(_) => canonical_type.default_fold(self),
         }
     }
 
@@ -958,8 +965,8 @@ pub fn simplify_enums(
     kind: SimplifyEnumsKind,
 ) -> Result<Interned<Module<Bundle>>, SimplifyEnumsError> {
     module.fold(&mut State {
-        enum_types: HashMap::new(),
-        replacement_mem_ports: HashMap::new(),
+        enum_types: HashMap::default(),
+        replacement_mem_ports: HashMap::default(),
         kind,
         module_state_stack: vec![],
     })
diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index e8f9cbf..6357843 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -14,11 +14,10 @@ use crate::{
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
-    util::MakeMutSlice,
+    util::{HashMap, MakeMutSlice},
     wire::Wire,
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
-use hashbrown::HashMap;
 use std::{
     convert::Infallible,
     fmt::Write,
@@ -62,6 +61,7 @@ enum MemSplit {
     Bundle {
         fields: Rc<[MemSplit]>,
     },
+    PhantomConst,
     Single {
         output_mem: Option<Mem>,
         element_type: SingleType,
@@ -76,6 +76,7 @@ impl MemSplit {
     fn mark_changed_element_type(self) -> Self {
         match self {
             MemSplit::Bundle { fields: _ } => self,
+            MemSplit::PhantomConst => self,
             MemSplit::Single {
                 output_mem,
                 element_type,
@@ -97,6 +98,7 @@ impl MemSplit {
                     .map(|field| Self::new(field.ty).mark_changed_element_type())
                     .collect(),
             },
+            CanonicalType::PhantomConst(_) => MemSplit::PhantomConst,
             CanonicalType::Array(ty) => {
                 let element = MemSplit::new(ty.element());
                 if let Self::Single {
@@ -339,6 +341,7 @@ impl SplitMemState<'_, '_> {
                     self.split_state_stack.pop();
                 }
             }
+            MemSplit::PhantomConst => {}
             MemSplit::Single {
                 output_mem,
                 element_type: single_type,
@@ -538,7 +541,12 @@ impl ModuleState {
             };
         loop {
             match input_element_type {
-                CanonicalType::Bundle(_) => unreachable!("bundle types are always split"),
+                CanonicalType::Bundle(_) => {
+                    unreachable!("bundle types are always split")
+                }
+                CanonicalType::PhantomConst(_) => {
+                    unreachable!("PhantomConst are always removed")
+                }
                 CanonicalType::Enum(_)
                     if input_array_types
                         .first()
@@ -743,7 +751,8 @@ impl ModuleState {
                 ..
             }
             | MemSplit::Bundle { .. }
-            | MemSplit::Array { .. } => {
+            | MemSplit::Array { .. }
+            | MemSplit::PhantomConst => {
                 let mut replacement_ports = Vec::with_capacity(input_mem.ports().len());
                 let mut wire_port_rdata = Vec::with_capacity(input_mem.ports().len());
                 let mut wire_port_wdata = Vec::with_capacity(input_mem.ports().len());
@@ -887,7 +896,7 @@ impl Folder for State {
             module,
             ModuleState {
                 output_module: None,
-                memories: HashMap::new(),
+                memories: HashMap::default(),
             },
         );
         let mut this = PushedState::push_module(self, module);
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 2e1e48f..526a62c 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -28,8 +28,10 @@ use crate::{
         NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
         StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
-    reset::{AsyncReset, Reset, SyncReset},
+    reset::{AsyncReset, Reset, ResetType, SyncReset},
+    sim::ExternModuleSimulation,
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
new file mode 100644
index 0000000..c481692
--- /dev/null
+++ b/crates/fayalite/src/phantom_const.rs
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    expr::{
+        ops::{ExprPartialEq, ExprPartialOrd},
+        Expr, ToExpr,
+    },
+    int::Bool,
+    intern::{Intern, Interned, InternedCompare, LazyInterned, LazyInternedTrait, Memoize},
+    sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
+    source_location::SourceLocation,
+    ty::{
+        impl_match_variant_as_self,
+        serde_impls::{SerdeCanonicalType, SerdePhantomConst},
+        CanonicalType, StaticType, Type, TypeProperties,
+    },
+};
+use bitvec::slice::BitSlice;
+use serde::{
+    de::{DeserializeOwned, Error},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
+use std::{
+    any::Any,
+    fmt,
+    hash::{Hash, Hasher},
+    marker::PhantomData,
+    ops::Index,
+};
+
+#[derive(Clone)]
+pub struct PhantomConstCanonicalValue {
+    parsed: serde_json::Value,
+    serialized: Interned<str>,
+}
+
+impl PhantomConstCanonicalValue {
+    pub fn from_json_value(parsed: serde_json::Value) -> Self {
+        let serialized = Intern::intern_owned(
+            serde_json::to_string(&parsed)
+                .expect("conversion from json value to text shouldn't fail"),
+        );
+        Self { parsed, serialized }
+    }
+    pub fn as_json_value(&self) -> &serde_json::Value {
+        &self.parsed
+    }
+    pub fn as_str(&self) -> Interned<str> {
+        self.serialized
+    }
+}
+
+impl fmt::Debug for PhantomConstCanonicalValue {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(&self.serialized)
+    }
+}
+
+impl fmt::Display for PhantomConstCanonicalValue {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(&self.serialized)
+    }
+}
+
+impl PartialEq for PhantomConstCanonicalValue {
+    fn eq(&self, other: &Self) -> bool {
+        self.serialized == other.serialized
+    }
+}
+
+impl Eq for PhantomConstCanonicalValue {}
+
+impl Hash for PhantomConstCanonicalValue {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        self.serialized.hash(state);
+    }
+}
+
+impl Serialize for PhantomConstCanonicalValue {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: serde::Serializer,
+    {
+        self.parsed.serialize(serializer)
+    }
+}
+
+impl<'de> Deserialize<'de> for PhantomConstCanonicalValue {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        Ok(Self::from_json_value(serde_json::Value::deserialize(
+            deserializer,
+        )?))
+    }
+}
+
+pub trait PhantomConstValue: Intern + InternedCompare + Serialize + fmt::Debug {
+    fn deserialize_value<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    where
+        D: serde::Deserializer<'de>;
+}
+
+impl<T> PhantomConstValue for T
+where
+    T: ?Sized + Intern + InternedCompare + Serialize + fmt::Debug,
+    Interned<T>: DeserializeOwned,
+{
+    fn deserialize_value<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        <Interned<T> as Deserialize<'de>>::deserialize(deserializer)
+    }
+}
+
+/// Wrapper type that allows any Rust value to be smuggled as a HDL [`Type`].
+/// This only works for values that can be [serialized][Serialize] to and [deserialized][Deserialize] from [JSON][serde_json].
+pub struct PhantomConst<T: ?Sized + PhantomConstValue = PhantomConstCanonicalValue> {
+    value: LazyInterned<T>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct PhantomConstWithoutGenerics;
+
+#[allow(non_upper_case_globals)]
+pub const PhantomConst: PhantomConstWithoutGenerics = PhantomConstWithoutGenerics;
+
+impl<T: Type + PhantomConstValue> Index<T> for PhantomConstWithoutGenerics {
+    type Output = PhantomConst<T>;
+
+    fn index(&self, value: T) -> &Self::Output {
+        Interned::into_inner(PhantomConst::new(value.intern()).intern_sized())
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> fmt::Debug for PhantomConst<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("PhantomConst").field(&self.get()).finish()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Clone for PhantomConst<T> {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Copy for PhantomConst<T> {}
+
+impl<T: ?Sized + PhantomConstValue> PartialEq for PhantomConst<T> {
+    fn eq(&self, other: &Self) -> bool {
+        self.get() == other.get()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Eq for PhantomConst<T> {}
+
+impl<T: ?Sized + PhantomConstValue> Hash for PhantomConst<T> {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        self.get().hash(state);
+    }
+}
+
+struct PhantomConstCanonicalMemoize<T: ?Sized, const IS_FROM_CANONICAL: bool>(PhantomData<T>);
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Copy
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Clone
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Eq
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> PartialEq
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn eq(&self, _other: &Self) -> bool {
+        true
+    }
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Hash
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn hash<H: Hasher>(&self, _state: &mut H) {}
+}
+
+impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T, false> {
+    type Input = Interned<T>;
+    type InputOwned = Interned<T>;
+    type Output = Interned<PhantomConstCanonicalValue>;
+
+    fn inner(self, input: &Self::Input) -> Self::Output {
+        Intern::intern_sized(PhantomConstCanonicalValue::from_json_value(
+            serde_json::to_value(input)
+                .expect("serialization failed when constructing a canonical PhantomConst"),
+        ))
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T, true> {
+    type Input = Interned<PhantomConstCanonicalValue>;
+    type InputOwned = Interned<PhantomConstCanonicalValue>;
+    type Output = Interned<T>;
+
+    fn inner(self, input: &Self::Input) -> Self::Output {
+        PhantomConstValue::deserialize_value(input.as_json_value())
+            .expect("deserialization failed ")
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
+    pub fn new(value: Interned<T>) -> Self {
+        Self {
+            value: LazyInterned::Interned(value),
+        }
+    }
+    pub const fn new_lazy(v: &'static dyn LazyInternedTrait<T>) -> Self {
+        Self {
+            value: LazyInterned::new_lazy(v),
+        }
+    }
+    pub fn get(self) -> Interned<T> {
+        self.value.interned()
+    }
+    pub fn type_properties(self) -> TypeProperties {
+        <()>::TYPE_PROPERTIES
+    }
+    pub fn can_connect(self, other: Self) -> bool {
+        self == other
+    }
+    pub fn canonical_phantom_const(self) -> PhantomConst {
+        if let Some(&retval) = <dyn Any>::downcast_ref::<PhantomConst>(&self) {
+            return retval;
+        }
+        <PhantomConst>::new(
+            PhantomConstCanonicalMemoize::<T, false>(PhantomData).get_owned(self.get()),
+        )
+    }
+    pub fn from_canonical_phantom_const(canonical_type: PhantomConst) -> Self {
+        if let Some(&retval) = <dyn Any>::downcast_ref::<Self>(&canonical_type) {
+            return retval;
+        }
+        Self::new(
+            PhantomConstCanonicalMemoize::<T, true>(PhantomData).get_owned(canonical_type.get()),
+        )
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
+    type BaseType = PhantomConst;
+    type MaskType = ();
+    type SimValue = PhantomConst<T>;
+    impl_match_variant_as_self!();
+
+    fn mask_type(&self) -> Self::MaskType {
+        ()
+    }
+
+    fn canonical(&self) -> CanonicalType {
+        CanonicalType::PhantomConst(self.canonical_phantom_const())
+    }
+
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let CanonicalType::PhantomConst(phantom_const) = canonical_type else {
+            panic!("expected PhantomConst");
+        };
+        Self::from_canonical_phantom_const(phantom_const)
+    }
+
+    fn source_location() -> SourceLocation {
+        SourceLocation::builtin()
+    }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert!(bits.is_empty());
+        *self
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert!(bits.is_empty());
+        assert_eq!(*value, *self);
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert!(bits.is_empty());
+        assert_eq!(*value, *self);
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Default for PhantomConst<T>
+where
+    Interned<T>: Default,
+{
+    fn default() -> Self {
+        Self::TYPE
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> StaticType for PhantomConst<T>
+where
+    Interned<T>: Default,
+{
+    const TYPE: Self = PhantomConst {
+        value: LazyInterned::new_lazy(&Interned::<T>::default),
+    };
+    const MASK_TYPE: Self::MaskType = ();
+    const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+    const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+}
+
+type SerdeType<T> = SerdeCanonicalType<CanonicalType, SerdePhantomConst<Interned<T>>>;
+
+impl<T: ?Sized + PhantomConstValue> Serialize for PhantomConst<T> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeType::<T>::PhantomConst(SerdePhantomConst(self.get())).serialize(serializer)
+    }
+}
+
+impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for PhantomConst<T> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        match SerdeType::<T>::deserialize(deserializer)? {
+            SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => Ok(Self::new(value)),
+            ty => Err(Error::invalid_value(
+                serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                &"a PhantomConst",
+            )),
+        }
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprPartialEq<Self> for PhantomConst<T> {
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprPartialOrd<Self> for PhantomConst<T> {
+    fn cmp_lt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+
+    fn cmp_le(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+
+    fn cmp_gt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+
+    fn cmp_ge(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> SimValuePartialEq<Self> for PhantomConst<T> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        assert_eq!(SimValue::ty(this), SimValue::ty(other));
+        true
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ToSimValue for PhantomConst<T> {
+    type Type = PhantomConst<T>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_value(*self, *self)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ToSimValueWithType<PhantomConst<T>> for PhantomConst<T> {
+    fn to_sim_value_with_type(&self, ty: PhantomConst<T>) -> SimValue<PhantomConst<T>> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ToSimValueWithType<CanonicalType> for PhantomConst<T> {
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_value(Self::from_canonical(ty), *self))
+    }
+}
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 9e7a85e..519210f 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -20,17 +20,24 @@ pub use crate::{
         hdl_cover_with_enable, MakeFormalExpr,
     },
     hdl, hdl_module,
-    int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
+    int::{Bool, DynSize, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
         annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
         memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
+    sim::{
+        time::{SimDuration, SimInstant},
+        value::{SimValue, ToSimValue, ToSimValueWithType},
+        ExternModuleSimulationState, Simulation,
+    },
     source_location::SourceLocation,
     ty::{AsMask, CanonicalType, Type},
     util::{ConstUsize, GenericConstUsize},
     wire::Wire,
     __,
 };
+pub use bitvec::{slice::BitSlice, vec::BitVec};
diff --git a/crates/fayalite/src/reg.rs b/crates/fayalite/src/reg.rs
index 8f757f2..20e0b94 100644
--- a/crates/fayalite/src/reg.rs
+++ b/crates/fayalite/src/reg.rs
@@ -5,21 +5,22 @@ use crate::{
     expr::{Expr, Flow},
     intern::Interned,
     module::{NameId, ScopedNameId},
+    reset::{Reset, ResetType},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
 };
 use std::fmt;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct Reg<T: Type> {
+pub struct Reg<T: Type, R: ResetType = Reset> {
     name: ScopedNameId,
     source_location: SourceLocation,
     ty: T,
-    clock_domain: Expr<ClockDomain>,
+    clock_domain: Expr<ClockDomain<R>>,
     init: Option<Expr<T>>,
 }
 
-impl<T: Type + fmt::Debug> fmt::Debug for Reg<T> {
+impl<T: Type + fmt::Debug, R: ResetType> fmt::Debug for Reg<T, R> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             name,
@@ -37,8 +38,8 @@ impl<T: Type + fmt::Debug> fmt::Debug for Reg<T> {
     }
 }
 
-impl<T: Type> Reg<T> {
-    pub fn canonical(&self) -> Reg<CanonicalType> {
+impl<T: Type, R: ResetType> Reg<T, R> {
+    pub fn canonical(&self) -> Reg<CanonicalType, R> {
         let Self {
             name,
             source_location,
@@ -59,7 +60,7 @@ impl<T: Type> Reg<T> {
         scoped_name: ScopedNameId,
         source_location: SourceLocation,
         ty: T,
-        clock_domain: Expr<ClockDomain>,
+        clock_domain: Expr<ClockDomain<R>>,
         init: Option<Expr<T>>,
     ) -> Self {
         assert!(
@@ -98,7 +99,7 @@ impl<T: Type> Reg<T> {
     pub fn scoped_name(&self) -> ScopedNameId {
         self.name
     }
-    pub fn clock_domain(&self) -> Expr<ClockDomain> {
+    pub fn clock_domain(&self) -> Expr<ClockDomain<R>> {
         self.clock_domain
     }
     pub fn init(&self) -> Option<Expr<T>> {
diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs
index 70d5f02..312a8ea 100644
--- a/crates/fayalite/src/reset.rs
+++ b/crates/fayalite/src/reset.rs
@@ -1,26 +1,52 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    expr::{Expr, ToExpr},
-    int::Bool,
+    clock::Clock,
+    expr::{ops, Expr, ToExpr},
+    int::{Bool, SInt, UInt},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
+use bitvec::slice::BitSlice;
 
 mod sealed {
     pub trait ResetTypeSealed {}
 }
 
-pub trait ResetType: StaticType<MaskType = Bool> + sealed::ResetTypeSealed {}
+pub trait ResetType:
+    StaticType<MaskType = Bool>
+    + sealed::ResetTypeSealed
+    + ops::ExprCastTo<Bool>
+    + ops::ExprCastTo<Reset>
+    + ops::ExprCastTo<SyncReset>
+    + ops::ExprCastTo<AsyncReset>
+    + ops::ExprCastTo<Clock>
+    + ops::ExprCastTo<UInt<1>>
+    + ops::ExprCastTo<SInt<1>>
+    + ops::ExprCastTo<UInt>
+    + ops::ExprCastTo<SInt>
+{
+    fn dispatch<D: ResetTypeDispatch>(input: D::Input<Self>, dispatch: D) -> D::Output<Self>;
+}
+
+pub trait ResetTypeDispatch: Sized {
+    type Input<T: ResetType>;
+    type Output<T: ResetType>;
+
+    fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset>;
+    fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset>;
+    fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset>;
+}
 
 macro_rules! reset_type {
-    ($name:ident, $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal) => {
+    ($name:ident, $(#[$impl_trait:ident])? $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal, $dispatch_fn:ident) => {
         #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
         pub struct $name;
 
         impl Type for $name {
             type BaseType = $name;
             type MaskType = Bool;
+            type SimValue = bool;
 
             impl_match_variant_as_self!();
 
@@ -42,6 +68,21 @@ macro_rules! reset_type {
                 };
                 retval
             }
+
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                assert_eq!(bits.len(), 1);
+                bits[0]
+            }
+
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                assert_eq!(bits.len(), 1);
+                *value = bits[0];
+            }
+
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                assert_eq!(bits.len(), 1);
+                bits.set(0, *value);
+            }
         }
 
         impl $name {
@@ -67,7 +108,14 @@ macro_rules! reset_type {
 
         impl sealed::ResetTypeSealed for $name {}
 
-        impl ResetType for $name {}
+        impl ResetType for $name {
+            fn dispatch<D: ResetTypeDispatch>(
+                input: D::Input<Self>,
+                dispatch: D,
+            ) -> D::Output<Self> {
+                dispatch.$dispatch_fn(input)
+            }
+        }
 
         pub trait $Trait {
             fn $trait_fn(&self) -> Expr<$name>;
@@ -91,20 +139,21 @@ macro_rules! reset_type {
             }
         }
 
-        impl $Trait for Expr<$name> {
+        $($impl_trait $Trait for Expr<$name> {
             fn $trait_fn(&self) -> Expr<$name> {
                 *self
             }
-        }
+        })?
     };
 }
 
-reset_type!(AsyncReset, ToAsyncReset::to_async_reset, true);
-reset_type!(SyncReset, ToSyncReset::to_sync_reset, true);
+reset_type!(AsyncReset, #[impl] ToAsyncReset::to_async_reset, true, async_reset);
+reset_type!(SyncReset, #[impl] ToSyncReset::to_sync_reset, true, sync_reset);
 reset_type!(
     Reset,
     ToReset::to_reset,
-    false // Reset is not castable from bits because we don't know if it's async or sync
+    false, // Reset is not castable from bits because we don't know if it's async or sync
+    reset
 );
 
 impl ToSyncReset for bool {
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
new file mode 100644
index 0000000..6659391
--- /dev/null
+++ b/crates/fayalite/src/sim.rs
@@ -0,0 +1,7812 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+//! Fayalite Simulation
+
+use crate::{
+    bundle::{BundleField, BundleType},
+    enum_::{EnumType, EnumVariant},
+    expr::{
+        ops,
+        target::{
+            GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
+            TargetPathElement,
+        },
+        ExprEnum, Flow, ToLiteralBits,
+    },
+    int::{BoolOrIntType, UIntValue},
+    intern::{
+        Intern, Interned, InternedCompare, Memoize, PtrEqWithTypeId, SupportsPtrEqWithTypeId,
+    },
+    memory::PortKind,
+    module::{
+        transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, ExternModuleBody, Id,
+        InstantiatedModule, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect,
+        StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+        TargetInInstantiatedModule,
+    },
+    prelude::*,
+    reset::{ResetType, ResetTypeDispatch},
+    sim::{
+        interpreter::{
+            BreakAction, BreakpointsSet, Insn, InsnField, InsnFieldKind, InsnFieldType,
+            InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label,
+            MemoryData, RunResult, SlotDebugData, SmallUInt, State, StatePartArrayIndex,
+            StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, StatePartKind,
+            StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout,
+            StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex,
+            TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+        },
+        time::{SimDuration, SimInstant},
+        value::SimValue,
+    },
+    ty::StaticType,
+    util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet},
+};
+use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
+use num_bigint::BigInt;
+use num_traits::{Signed, Zero};
+use petgraph::{
+    data::FromElements,
+    visit::{
+        EdgeRef, GraphBase, IntoEdgeReferences, IntoNeighbors, IntoNeighborsDirected,
+        IntoNodeIdentifiers, IntoNodeReferences, NodeRef, VisitMap, Visitable,
+    },
+};
+use std::{
+    any::Any,
+    borrow::Cow,
+    cell::RefCell,
+    collections::BTreeSet,
+    fmt,
+    future::{Future, IntoFuture},
+    hash::Hash,
+    marker::PhantomData,
+    mem,
+    ops::IndexMut,
+    pin::Pin,
+    rc::Rc,
+    sync::Arc,
+    task::Poll,
+};
+
+mod interpreter;
+pub mod time;
+pub mod value;
+pub mod vcd;
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+enum CondBody {
+    IfTrue {
+        cond: CompiledValue<Bool>,
+    },
+    IfFalse {
+        cond: CompiledValue<Bool>,
+    },
+    MatchArm {
+        discriminant: StatePartIndex<StatePartKindSmallSlots>,
+        variant_index: usize,
+    },
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct Cond {
+    body: CondBody,
+    source_location: SourceLocation,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledBundleField {
+    offset: TypeIndex,
+    ty: CompiledTypeLayout<CanonicalType>,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+enum CompiledTypeLayoutBody {
+    Scalar,
+    Array {
+        /// debug names are ignored, use parent's layout instead
+        element: Interned<CompiledTypeLayout<CanonicalType>>,
+    },
+    Bundle {
+        /// debug names are ignored, use parent's layout instead
+        fields: Interned<[CompiledBundleField]>,
+    },
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledTypeLayout<T: Type> {
+    ty: T,
+    layout: TypeLayout<InsnsBuildingDone>,
+    body: CompiledTypeLayoutBody,
+}
+
+impl<T: Type> CompiledTypeLayout<T> {
+    fn with_prefixed_debug_names(self, prefix: &str) -> Self {
+        let Self { ty, layout, body } = self;
+        Self {
+            ty,
+            layout: layout.with_prefixed_debug_names(prefix),
+            body,
+        }
+    }
+    fn with_anonymized_debug_info(self) -> Self {
+        let Self { ty, layout, body } = self;
+        Self {
+            ty,
+            layout: layout.with_anonymized_debug_info(),
+            body,
+        }
+    }
+    fn get(ty: T) -> Self {
+        #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize;
+        impl Memoize for MyMemoize {
+            type Input = CanonicalType;
+            type InputOwned = CanonicalType;
+            type Output = CompiledTypeLayout<CanonicalType>;
+
+            fn inner(self, input: &Self::Input) -> Self::Output {
+                match input {
+                    CanonicalType::UInt(_)
+                    | CanonicalType::SInt(_)
+                    | CanonicalType::Bool(_)
+                    | CanonicalType::Enum(_)
+                    | CanonicalType::AsyncReset(_)
+                    | CanonicalType::SyncReset(_)
+                    | CanonicalType::Reset(_)
+                    | CanonicalType::Clock(_) => {
+                        let mut layout = TypeLayout::empty();
+                        let debug_data = SlotDebugData {
+                            name: Interned::default(),
+                            ty: *input,
+                        };
+                        layout.big_slots = StatePartLayout::scalar(debug_data, ());
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Scalar,
+                        }
+                    }
+                    CanonicalType::Array(array) => {
+                        let mut layout = TypeLayout::empty();
+                        let element = CompiledTypeLayout::get(array.element()).intern_sized();
+                        for index in 0..array.len() {
+                            layout.allocate(
+                                &element
+                                    .layout
+                                    .with_prefixed_debug_names(&format!("[{index}]")),
+                            );
+                        }
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Array { element },
+                        }
+                    }
+                    CanonicalType::PhantomConst(_) => {
+                        let unit_layout = CompiledTypeLayout::get(());
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: unit_layout.layout,
+                            body: unit_layout.body,
+                        }
+                    }
+                    CanonicalType::Bundle(bundle) => {
+                        let mut layout = TypeLayout::empty();
+                        let fields = bundle
+                            .fields()
+                            .iter()
+                            .map(
+                                |BundleField {
+                                     name,
+                                     flipped: _,
+                                     ty,
+                                 }| {
+                                    let ty = CompiledTypeLayout::get(*ty);
+                                    let offset = layout
+                                        .allocate(
+                                            &ty.layout
+                                                .with_prefixed_debug_names(&format!(".{name}")),
+                                        )
+                                        .start();
+                                    CompiledBundleField { offset, ty }
+                                },
+                            )
+                            .collect();
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Bundle { fields },
+                        }
+                    }
+                }
+            }
+        }
+        let CompiledTypeLayout {
+            ty: _,
+            layout,
+            body,
+        } = MyMemoize.get_owned(ty.canonical());
+        Self { ty, layout, body }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledValue<T: Type> {
+    layout: CompiledTypeLayout<T>,
+    range: TypeIndexRange,
+    write: Option<(CompiledTypeLayout<T>, TypeIndexRange)>,
+}
+
+impl<T: Type> CompiledValue<T> {
+    fn write(self) -> (CompiledTypeLayout<T>, TypeIndexRange) {
+        self.write.unwrap_or((self.layout, self.range))
+    }
+    fn write_value(self) -> Self {
+        let (layout, range) = self.write();
+        Self {
+            layout,
+            range,
+            write: None,
+        }
+    }
+    fn map<U: Type>(
+        self,
+        mut f: impl FnMut(
+            CompiledTypeLayout<T>,
+            TypeIndexRange,
+        ) -> (CompiledTypeLayout<U>, TypeIndexRange),
+    ) -> CompiledValue<U> {
+        let (layout, range) = f(self.layout, self.range);
+        CompiledValue {
+            layout,
+            range,
+            write: self.write.map(|(layout, range)| f(layout, range)),
+        }
+    }
+    fn map_ty<U: Type>(self, mut f: impl FnMut(T) -> U) -> CompiledValue<U> {
+        self.map(|CompiledTypeLayout { ty, layout, body }, range| {
+            (
+                CompiledTypeLayout {
+                    ty: f(ty),
+                    layout,
+                    body,
+                },
+                range,
+            )
+        })
+    }
+}
+
+impl CompiledValue<Bundle> {
+    fn field_by_index(self, field_index: usize) -> CompiledValue<CanonicalType> {
+        self.map(|layout, range| {
+            let CompiledTypeLayout {
+                ty: _,
+                layout: _,
+                body: CompiledTypeLayoutBody::Bundle { fields },
+            } = layout
+            else {
+                unreachable!();
+            };
+            (
+                fields[field_index].ty,
+                range.slice(TypeIndexRange::new(
+                    fields[field_index].offset,
+                    fields[field_index].ty.layout.len(),
+                )),
+            )
+        })
+    }
+    fn field_by_name(self, name: Interned<str>) -> CompiledValue<CanonicalType> {
+        self.field_by_index(self.layout.ty.name_indexes()[&name])
+    }
+}
+
+impl CompiledValue<Array> {
+    fn element(self, index: usize) -> CompiledValue<CanonicalType> {
+        self.map(|layout, range| {
+            let CompiledTypeLayoutBody::Array { element } = layout.body else {
+                unreachable!();
+            };
+            (*element, range.index_array(element.layout.len(), index))
+        })
+    }
+    fn element_dyn(
+        self,
+        index_slot: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> CompiledExpr<CanonicalType> {
+        CompiledExpr::from(self).element_dyn(index_slot)
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
+struct CompiledExpr<T: Type> {
+    static_part: CompiledValue<T>,
+    indexes: TypeArrayIndexes,
+}
+
+impl<T: Type> From<CompiledValue<T>> for CompiledExpr<T> {
+    fn from(static_part: CompiledValue<T>) -> Self {
+        Self {
+            static_part,
+            indexes: TypeArrayIndexes::default(),
+        }
+    }
+}
+
+impl<T: Type> CompiledExpr<T> {
+    fn map_ty<U: Type>(self, f: impl FnMut(T) -> U) -> CompiledExpr<U> {
+        let Self {
+            static_part,
+            indexes,
+        } = self;
+        CompiledExpr {
+            static_part: static_part.map_ty(f),
+            indexes,
+        }
+    }
+    fn add_target_without_indexes_to_set(self, inputs: &mut SlotSet) {
+        let Self {
+            static_part,
+            indexes,
+        } = self;
+        indexes.as_ref().for_each_offset(|offset| {
+            inputs.extend([static_part.range.offset(offset)]);
+        });
+    }
+    fn add_target_and_indexes_to_set(self, inputs: &mut SlotSet) {
+        let Self {
+            static_part: _,
+            indexes,
+        } = self;
+        self.add_target_without_indexes_to_set(inputs);
+        inputs.extend(indexes.as_ref().iter());
+    }
+}
+
+impl CompiledExpr<Bundle> {
+    fn field_by_index(self, field_index: usize) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.field_by_index(field_index),
+            indexes: self.indexes,
+        }
+    }
+    fn field_by_name(self, name: Interned<str>) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.field_by_name(name),
+            indexes: self.indexes,
+        }
+    }
+}
+
+impl CompiledExpr<Array> {
+    fn element(self, index: usize) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.element(index),
+            indexes: self.indexes,
+        }
+    }
+    fn element_dyn(
+        self,
+        index_slot: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> CompiledExpr<CanonicalType> {
+        let CompiledTypeLayoutBody::Array { element } = self.static_part.layout.body else {
+            unreachable!();
+        };
+        let stride = element.layout.len();
+        let indexes = self.indexes.join(TypeArrayIndex::from_parts(
+            index_slot,
+            self.static_part.layout.ty.len(),
+            stride,
+        ));
+        CompiledExpr {
+            static_part: self.static_part.map(|layout, range| {
+                let CompiledTypeLayoutBody::Array { element } = layout.body else {
+                    unreachable!();
+                };
+                (*element, range.index_array(stride, 0))
+            }),
+            indexes,
+        }
+    }
+}
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentOrSlotIndex {
+    AssignmentIndex(usize),
+    SmallSlot(StatePartIndex<StatePartKindSmallSlots>),
+    BigSlot(StatePartIndex<StatePartKindBigSlots>),
+}
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentIO {
+    BigInput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallInput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    BigOutput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallOutput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindSmallSlots>,
+    },
+}
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentsEdge {
+    IO(AssignmentIO),
+    AssignmentImmediatePredecessor {
+        predecessor_assignment_index: usize,
+        assignment_index: usize,
+    },
+}
+
+#[derive(Debug)]
+enum Assignments {
+    Accumulating {
+        assignments: Vec<Assignment>,
+    },
+    Finalized {
+        assignments: Box<[Assignment]>,
+        slots_layout: TypeLayout<InsnsBuildingDone>,
+        slot_readers: SlotToAssignmentIndexFullMap,
+        slot_writers: SlotToAssignmentIndexFullMap,
+        assignment_immediate_predecessors: Box<[Box<[usize]>]>,
+        assignment_immediate_successors: Box<[Box<[usize]>]>,
+    },
+}
+
+impl Default for Assignments {
+    fn default() -> Self {
+        Self::Accumulating {
+            assignments: Vec::new(),
+        }
+    }
+}
+
+impl Assignments {
+    fn finalize(&mut self, slots_layout: TypeLayout<InsnsBuildingDone>) {
+        let Self::Accumulating { assignments } = self else {
+            unreachable!("already finalized");
+        };
+        let assignments = mem::take(assignments).into_boxed_slice();
+        let mut slot_readers = SlotToAssignmentIndexFullMap::new(slots_layout.len());
+        let mut slot_writers = SlotToAssignmentIndexFullMap::new(slots_layout.len());
+        let mut assignment_immediate_predecessors = vec![BTreeSet::new(); assignments.len()];
+        let mut assignment_immediate_successors = vec![BTreeSet::new(); assignments.len()];
+        for (assignment_index, assignment) in assignments.iter().enumerate() {
+            slot_readers
+                .keys_for_assignment(assignment_index)
+                .extend([&assignment.inputs]);
+            slot_readers
+                .keys_for_assignment(assignment_index)
+                .extend(&assignment.conditions);
+            let SlotSet(TypeParts {
+                small_slots,
+                big_slots,
+            }) = &assignment.outputs;
+            for &slot in small_slots {
+                if let Some(&pred) = slot_writers[slot].last() {
+                    assignment_immediate_predecessors[assignment_index].insert(pred);
+                    assignment_immediate_successors[pred].insert(assignment_index);
+                }
+                slot_writers[slot].push(assignment_index);
+            }
+            for &slot in big_slots {
+                if let Some(&pred) = slot_writers[slot].last() {
+                    assignment_immediate_predecessors[assignment_index].insert(pred);
+                    assignment_immediate_successors[pred].insert(assignment_index);
+                }
+                slot_writers[slot].push(assignment_index);
+            }
+        }
+        *self = Self::Finalized {
+            assignments,
+            slots_layout,
+            slot_readers,
+            slot_writers,
+            assignment_immediate_predecessors: assignment_immediate_predecessors
+                .into_iter()
+                .map(Box::from_iter)
+                .collect(),
+            assignment_immediate_successors: assignment_immediate_successors
+                .into_iter()
+                .map(Box::from_iter)
+                .collect(),
+        };
+    }
+    fn push(&mut self, v: Assignment) {
+        let Self::Accumulating { assignments } = self else {
+            unreachable!("already finalized");
+        };
+        assignments.push(v);
+    }
+    fn assignments(&self) -> &[Assignment] {
+        let Self::Finalized { assignments, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignments
+    }
+    fn slots_layout(&self) -> TypeLayout<InsnsBuildingDone> {
+        let Self::Finalized { slots_layout, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        *slots_layout
+    }
+    fn slot_readers(&self) -> &SlotToAssignmentIndexFullMap {
+        let Self::Finalized { slot_readers, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        slot_readers
+    }
+    fn slot_writers(&self) -> &SlotToAssignmentIndexFullMap {
+        let Self::Finalized { slot_writers, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        slot_writers
+    }
+    fn assignment_immediate_predecessors(&self) -> &[Box<[usize]>] {
+        let Self::Finalized {
+            assignment_immediate_predecessors,
+            ..
+        } = self
+        else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignment_immediate_predecessors
+    }
+    fn assignment_immediate_successors(&self) -> &[Box<[usize]>] {
+        let Self::Finalized {
+            assignment_immediate_successors,
+            ..
+        } = self
+        else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignment_immediate_successors
+    }
+    fn elements(&self) -> AssignmentsElements<'_> {
+        let SlotToAssignmentIndexFullMap(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self.slot_readers();
+        AssignmentsElements {
+            node_indexes: HashMap::with_capacity_and_hasher(
+                self.assignments().len() + small_slots.len() + big_slots.len(),
+                Default::default(),
+            ),
+            nodes: self.node_references(),
+            edges: self.edge_references(),
+        }
+    }
+}
+
+impl GraphBase for Assignments {
+    type EdgeId = AssignmentsEdge;
+    type NodeId = AssignmentOrSlotIndex;
+}
+
+#[derive(Debug, Clone, Copy)]
+enum AssignmentsNodeRef<'a> {
+    Assignment {
+        index: usize,
+        assignment: &'a Assignment,
+    },
+    SmallSlot(StatePartIndex<StatePartKindSmallSlots>, SlotDebugData),
+    BigSlot(StatePartIndex<StatePartKindBigSlots>, SlotDebugData),
+}
+
+impl<'a> NodeRef for AssignmentsNodeRef<'a> {
+    type NodeId = AssignmentOrSlotIndex;
+    type Weight = AssignmentsNodeRef<'a>;
+
+    fn id(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsNodeRef::Assignment {
+                index,
+                assignment: _,
+            } => AssignmentOrSlotIndex::AssignmentIndex(index),
+            AssignmentsNodeRef::SmallSlot(slot, _) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsNodeRef::BigSlot(slot, _) => AssignmentOrSlotIndex::BigSlot(slot),
+        }
+    }
+
+    fn weight(&self) -> &Self::Weight {
+        self
+    }
+}
+
+impl<'a> petgraph::visit::Data for &'a Assignments {
+    type NodeWeight = AssignmentsNodeRef<'a>;
+    type EdgeWeight = AssignmentsEdge;
+}
+
+struct AssignmentsElements<'a> {
+    node_indexes: HashMap<AssignmentOrSlotIndex, usize>,
+    nodes: AssignmentsNodes<'a>,
+    edges: AssignmentsEdges<'a>,
+}
+
+impl<'a> Iterator for AssignmentsElements<'a> {
+    type Item = petgraph::data::Element<
+        <&'a Assignments as petgraph::visit::Data>::NodeWeight,
+        <&'a Assignments as petgraph::visit::Data>::EdgeWeight,
+    >;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        let Self {
+            node_indexes,
+            nodes,
+            edges,
+        } = self;
+        if let Some(node) = nodes.next() {
+            node_indexes.insert(node.id(), node_indexes.len());
+            return Some(petgraph::data::Element::Node { weight: node });
+        }
+        let edge = edges.next()?;
+        Some(petgraph::data::Element::Edge {
+            source: node_indexes[&edge.source()],
+            target: node_indexes[&edge.target()],
+            weight: *edge.weight(),
+        })
+    }
+}
+
+#[derive(Clone)]
+struct AssignmentsNodeIdentifiers {
+    assignment_indexes: std::ops::Range<usize>,
+    small_slots: std::ops::Range<u32>,
+    big_slots: std::ops::Range<u32>,
+}
+
+impl AssignmentsNodeIdentifiers {
+    fn internal_iter<'a>(&'a mut self) -> impl Iterator<Item = AssignmentOrSlotIndex> + 'a {
+        let Self {
+            assignment_indexes,
+            small_slots,
+            big_slots,
+        } = self;
+        assignment_indexes
+            .map(AssignmentOrSlotIndex::AssignmentIndex)
+            .chain(small_slots.map(|value| {
+                AssignmentOrSlotIndex::SmallSlot(StatePartIndex {
+                    value,
+                    _phantom: PhantomData,
+                })
+            }))
+            .chain(big_slots.map(|value| {
+                AssignmentOrSlotIndex::BigSlot(StatePartIndex {
+                    value,
+                    _phantom: PhantomData,
+                })
+            }))
+    }
+}
+
+impl Iterator for AssignmentsNodeIdentifiers {
+    type Item = AssignmentOrSlotIndex;
+    fn next(&mut self) -> Option<Self::Item> {
+        self.internal_iter().next()
+    }
+
+    fn nth(&mut self, n: usize) -> Option<Self::Item> {
+        self.internal_iter().nth(n)
+    }
+}
+
+impl<'a> IntoNodeIdentifiers for &'a Assignments {
+    type NodeIdentifiers = AssignmentsNodeIdentifiers;
+
+    fn node_identifiers(self) -> Self::NodeIdentifiers {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = self.slot_readers().len();
+        AssignmentsNodeIdentifiers {
+            assignment_indexes: 0..self.assignments().len(),
+            small_slots: 0..small_slots.value,
+            big_slots: 0..big_slots.value,
+        }
+    }
+}
+
+struct AssignmentsNodes<'a> {
+    assignments: &'a Assignments,
+    nodes: AssignmentsNodeIdentifiers,
+}
+
+impl<'a> Iterator for AssignmentsNodes<'a> {
+    type Item = AssignmentsNodeRef<'a>;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.nodes.next().map(|node| match node {
+            AssignmentOrSlotIndex::AssignmentIndex(index) => AssignmentsNodeRef::Assignment {
+                index,
+                assignment: &self.assignments.assignments()[index],
+            },
+            AssignmentOrSlotIndex::SmallSlot(slot) => AssignmentsNodeRef::SmallSlot(
+                slot,
+                *self.assignments.slots_layout().small_slots.debug_data(slot),
+            ),
+            AssignmentOrSlotIndex::BigSlot(slot) => AssignmentsNodeRef::BigSlot(
+                slot,
+                *self.assignments.slots_layout().big_slots.debug_data(slot),
+            ),
+        })
+    }
+}
+
+impl<'a> IntoNodeReferences for &'a Assignments {
+    type NodeRef = AssignmentsNodeRef<'a>;
+    type NodeReferences = AssignmentsNodes<'a>;
+
+    fn node_references(self) -> Self::NodeReferences {
+        AssignmentsNodes {
+            assignments: self,
+            nodes: self.node_identifiers(),
+        }
+    }
+}
+
+struct AssignmentsNeighborsDirected<'a> {
+    assignment_indexes: std::slice::Iter<'a, usize>,
+    small_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindSmallSlots>>,
+    big_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindBigSlots>>,
+}
+
+impl Iterator for AssignmentsNeighborsDirected<'_> {
+    type Item = AssignmentOrSlotIndex;
+    fn next(&mut self) -> Option<Self::Item> {
+        let Self {
+            assignment_indexes,
+            small_slots,
+            big_slots,
+        } = self;
+        if let retval @ Some(_) = assignment_indexes
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::AssignmentIndex)
+        {
+            retval
+        } else if let retval @ Some(_) = small_slots
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::SmallSlot)
+        {
+            retval
+        } else if let retval @ Some(_) = big_slots
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::BigSlot)
+        {
+            retval
+        } else {
+            None
+        }
+    }
+}
+
+impl<'a> IntoNeighbors for &'a Assignments {
+    type Neighbors = AssignmentsNeighborsDirected<'a>;
+
+    fn neighbors(self, n: Self::NodeId) -> Self::Neighbors {
+        self.neighbors_directed(n, petgraph::Direction::Outgoing)
+    }
+}
+
+impl<'a> IntoNeighborsDirected for &'a Assignments {
+    type NeighborsDirected = AssignmentsNeighborsDirected<'a>;
+
+    fn neighbors_directed(
+        self,
+        n: Self::NodeId,
+        d: petgraph::Direction,
+    ) -> Self::NeighborsDirected {
+        use petgraph::Direction::*;
+        let slot_map = match d {
+            Outgoing => self.slot_readers(),
+            Incoming => self.slot_writers(),
+        };
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                let assignment = &self.assignments()[assignment_index];
+                let (
+                    assignment_indexes,
+                    SlotSet(TypeParts {
+                        small_slots,
+                        big_slots,
+                    }),
+                ) = match d {
+                    Outgoing => (
+                        &self.assignment_immediate_successors()[assignment_index],
+                        &assignment.outputs,
+                    ),
+                    Incoming => (
+                        &self.assignment_immediate_predecessors()[assignment_index],
+                        &assignment.inputs,
+                    ),
+                };
+                AssignmentsNeighborsDirected {
+                    assignment_indexes: assignment_indexes.iter(),
+                    small_slots: small_slots.iter(),
+                    big_slots: big_slots.iter(),
+                }
+            }
+            AssignmentOrSlotIndex::SmallSlot(slot) => AssignmentsNeighborsDirected {
+                assignment_indexes: slot_map[slot].iter(),
+                small_slots: Default::default(),
+                big_slots: Default::default(),
+            },
+            AssignmentOrSlotIndex::BigSlot(slot) => AssignmentsNeighborsDirected {
+                assignment_indexes: slot_map[slot].iter(),
+                small_slots: Default::default(),
+                big_slots: Default::default(),
+            },
+        }
+    }
+}
+
+impl EdgeRef for AssignmentsEdge {
+    type NodeId = AssignmentOrSlotIndex;
+    type EdgeId = AssignmentsEdge;
+    type Weight = AssignmentsEdge;
+
+    fn source(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsEdge::IO(AssignmentIO::BigInput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::BigSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::AssignmentImmediatePredecessor {
+                predecessor_assignment_index,
+                assignment_index: _,
+            } => AssignmentOrSlotIndex::AssignmentIndex(predecessor_assignment_index),
+        }
+    }
+
+    fn target(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsEdge::IO(AssignmentIO::BigInput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::BigSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsEdge::AssignmentImmediatePredecessor {
+                predecessor_assignment_index: _,
+                assignment_index,
+            } => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+        }
+    }
+
+    fn weight(&self) -> &Self::Weight {
+        self
+    }
+
+    fn id(&self) -> Self::EdgeId {
+        *self
+    }
+}
+
+struct AssignmentsEdges<'a> {
+    assignments: &'a Assignments,
+    nodes: AssignmentsNodeIdentifiers,
+    outgoing_neighbors: Option<(AssignmentOrSlotIndex, AssignmentsNeighborsDirected<'a>)>,
+}
+
+impl Iterator for AssignmentsEdges<'_> {
+    type Item = AssignmentsEdge;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        loop {
+            if let Some((node, outgoing_neighbors)) = &mut self.outgoing_neighbors {
+                if let Some(outgoing_neighbor) = outgoing_neighbors.next() {
+                    return Some(match (*node, outgoing_neighbor) {
+                        (
+                            AssignmentOrSlotIndex::SmallSlot(_) | AssignmentOrSlotIndex::BigSlot(_),
+                            AssignmentOrSlotIndex::SmallSlot(_) | AssignmentOrSlotIndex::BigSlot(_),
+                        ) => unreachable!(),
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(predecessor_assignment_index),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::AssignmentImmediatePredecessor {
+                            predecessor_assignment_index,
+                            assignment_index,
+                        },
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                            AssignmentOrSlotIndex::SmallSlot(slot),
+                        ) => AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                            AssignmentOrSlotIndex::BigSlot(slot),
+                        ) => AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::SmallSlot(slot),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::BigSlot(slot),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::IO(AssignmentIO::BigInput {
+                            assignment_index,
+                            slot,
+                        }),
+                    });
+                }
+            }
+            let node = self.nodes.next()?;
+            self.outgoing_neighbors = Some((
+                node,
+                self.assignments
+                    .neighbors_directed(node, petgraph::Direction::Outgoing),
+            ));
+        }
+    }
+}
+
+impl<'a> IntoEdgeReferences for &'a Assignments {
+    type EdgeRef = AssignmentsEdge;
+    type EdgeReferences = AssignmentsEdges<'a>;
+
+    fn edge_references(self) -> Self::EdgeReferences {
+        AssignmentsEdges {
+            assignments: self,
+            nodes: self.node_identifiers(),
+            outgoing_neighbors: None,
+        }
+    }
+}
+
+struct AssignmentsVisitMap {
+    assignments: Vec<bool>,
+    slots: DenseSlotSet,
+}
+
+impl VisitMap<AssignmentOrSlotIndex> for AssignmentsVisitMap {
+    fn visit(&mut self, n: AssignmentOrSlotIndex) -> bool {
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                !mem::replace(&mut self.assignments[assignment_index], true)
+            }
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.insert(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.insert(slot),
+        }
+    }
+
+    fn is_visited(&self, n: &AssignmentOrSlotIndex) -> bool {
+        match *n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                self.assignments[assignment_index]
+            }
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.contains(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.contains(slot),
+        }
+    }
+
+    fn unvisit(&mut self, n: AssignmentOrSlotIndex) -> bool {
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                mem::replace(&mut self.assignments[assignment_index], false)
+            }
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.remove(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.remove(slot),
+        }
+    }
+}
+
+impl Visitable for Assignments {
+    type Map = AssignmentsVisitMap;
+
+    fn visit_map(self: &Self) -> Self::Map {
+        AssignmentsVisitMap {
+            assignments: vec![false; self.assignments().len()],
+            slots: DenseSlotSet::new(self.slot_readers().len()),
+        }
+    }
+
+    fn reset_map(self: &Self, map: &mut Self::Map) {
+        let AssignmentsVisitMap { assignments, slots } = map;
+        assignments.clear();
+        assignments.resize(self.assignments().len(), false);
+        if slots.len() != self.slot_readers().len() {
+            *slots = DenseSlotSet::new(self.slot_readers().len());
+        } else {
+            slots.clear();
+        }
+    }
+}
+
+#[derive(Clone, Debug, PartialEq, Eq, Hash)]
+struct DenseSlotSet(TypeParts<Self>);
+
+impl DenseSlotSet {
+    fn new(len: TypeLen) -> Self {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = len;
+        Self(TypeParts {
+            small_slots: vec![false; small_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+            big_slots: vec![false; big_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+        })
+    }
+    fn len(&self) -> TypeLen {
+        TypeLen {
+            small_slots: StatePartLen {
+                value: self.0.small_slots.len() as _,
+                _phantom: PhantomData,
+            },
+            big_slots: StatePartLen {
+                value: self.0.big_slots.len() as _,
+                _phantom: PhantomData,
+            },
+        }
+    }
+    fn clear(&mut self) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.fill(false);
+        big_slots.fill(false);
+    }
+}
+
+impl StatePartsValue for DenseSlotSet {
+    type Value<K: StatePartKind> = Box<[bool]>;
+}
+
+trait DenseSlotSetMethods<K: StatePartKind>: Extend<StatePartIndex<K>> {
+    fn contains(&self, k: StatePartIndex<K>) -> bool;
+    fn remove(&mut self, k: StatePartIndex<K>) -> bool {
+        self.take(k).is_some()
+    }
+    fn take(&mut self, k: StatePartIndex<K>) -> Option<StatePartIndex<K>>;
+    fn replace(&mut self, k: StatePartIndex<K>) -> Option<StatePartIndex<K>>;
+    fn insert(&mut self, k: StatePartIndex<K>) -> bool {
+        self.replace(k).is_none()
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndex<K>> for DenseSlotSet
+where
+    Self: DenseSlotSetMethods<K>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndex<K>>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|v| {
+            self.insert(v);
+        });
+    }
+}
+
+impl DenseSlotSetMethods<StatePartKindSmallSlots> for DenseSlotSet {
+    fn contains(&self, k: StatePartIndex<StatePartKindSmallSlots>) -> bool {
+        self.0.small_slots[k.as_usize()]
+    }
+
+    fn take(
+        &mut self,
+        k: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> Option<StatePartIndex<StatePartKindSmallSlots>> {
+        mem::replace(self.0.small_slots.get_mut(k.as_usize())?, false).then_some(k)
+    }
+
+    fn replace(
+        &mut self,
+        k: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> Option<StatePartIndex<StatePartKindSmallSlots>> {
+        mem::replace(&mut self.0.small_slots[k.as_usize()], true).then_some(k)
+    }
+}
+
+impl DenseSlotSetMethods<StatePartKindBigSlots> for DenseSlotSet {
+    fn contains(&self, k: StatePartIndex<StatePartKindBigSlots>) -> bool {
+        self.0.big_slots[k.as_usize()]
+    }
+
+    fn take(
+        &mut self,
+        k: StatePartIndex<StatePartKindBigSlots>,
+    ) -> Option<StatePartIndex<StatePartKindBigSlots>> {
+        mem::replace(self.0.big_slots.get_mut(k.as_usize())?, false).then_some(k)
+    }
+
+    fn replace(
+        &mut self,
+        k: StatePartIndex<StatePartKindBigSlots>,
+    ) -> Option<StatePartIndex<StatePartKindBigSlots>> {
+        mem::replace(&mut self.0.big_slots[k.as_usize()], true).then_some(k)
+    }
+}
+
+#[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
+struct SlotVec(TypeParts<Self>);
+
+impl SlotVec {
+    fn is_empty(&self) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.is_empty() && big_slots.is_empty()
+    }
+}
+
+impl StatePartsValue for SlotVec {
+    type Value<K: StatePartKind> = Vec<StatePartIndex<K>>;
+}
+
+#[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
+struct SlotSet(TypeParts<Self>);
+
+impl SlotSet {
+    fn is_empty(&self) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.is_empty() && big_slots.is_empty()
+    }
+    fn for_each(
+        &self,
+        small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>),
+        big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>),
+    ) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().copied().for_each(small_slots_fn);
+        big_slots.iter().copied().for_each(big_slots_fn);
+    }
+    fn all(
+        &self,
+        small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>) -> bool,
+        big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>) -> bool,
+    ) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().copied().all(small_slots_fn)
+            && big_slots.iter().copied().all(big_slots_fn)
+    }
+}
+
+impl StatePartsValue for SlotSet {
+    type Value<K: StatePartKind> = BTreeSet<StatePartIndex<K>>;
+}
+
+impl Extend<StatePartIndex<StatePartKindSmallSlots>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindSmallSlots>>>(&mut self, iter: T) {
+        self.0.small_slots.extend(iter);
+    }
+}
+
+impl Extend<StatePartIndex<StatePartKindBigSlots>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindBigSlots>>>(&mut self, iter: T) {
+        self.0.big_slots.extend(iter);
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndexRange<K>> for SlotSet
+where
+    Self: Extend<StatePartIndex<K>>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndexRange<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().flat_map(|v| v.iter()));
+    }
+}
+
+impl Extend<TypeIndexRange> for SlotSet {
+    fn extend<T: IntoIterator<Item = TypeIndexRange>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |TypeIndexRange {
+                 small_slots,
+                 big_slots,
+             }| {
+                self.extend(small_slots.iter());
+                self.extend(big_slots.iter());
+            },
+        )
+    }
+}
+
+impl Extend<TypeArrayIndex> for SlotSet {
+    fn extend<T: IntoIterator<Item = TypeArrayIndex>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |TypeArrayIndex {
+                 small_slots,
+                 big_slots,
+             }| {
+                self.extend([small_slots]);
+                self.extend([big_slots]);
+            },
+        )
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartArrayIndex<K>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartArrayIndex<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().map(|v| v.index));
+    }
+}
+
+impl Extend<CondBody> for SlotSet {
+    fn extend<T: IntoIterator<Item = CondBody>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|cond_body| match cond_body {
+            CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
+                self.extend([cond.range]);
+            }
+            CondBody::MatchArm {
+                discriminant,
+                variant_index: _,
+            } => self.extend([discriminant]),
+        })
+    }
+}
+
+impl Extend<Cond> for SlotSet {
+    fn extend<T: IntoIterator<Item = Cond>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().map(|v| v.body))
+    }
+}
+
+#[derive(Debug)]
+struct Assignment {
+    inputs: SlotSet,
+    outputs: SlotSet,
+    conditions: Interned<[Cond]>,
+    insns: Vec<InsnOrLabel>,
+    source_location: SourceLocation,
+}
+
+#[derive(Debug)]
+struct SlotToAssignmentIndexFullMap(TypeParts<Self>);
+
+impl StatePartsValue for SlotToAssignmentIndexFullMap {
+    type Value<K: StatePartKind> = Box<[Vec<usize>]>;
+}
+
+impl SlotToAssignmentIndexFullMap {
+    fn new(len: TypeLen) -> Self {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = len;
+        Self(TypeParts {
+            small_slots: vec![Vec::new(); small_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+            big_slots: vec![Vec::new(); big_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+        })
+    }
+    fn len(&self) -> TypeLen {
+        TypeLen {
+            small_slots: StatePartLen {
+                value: self.0.small_slots.len() as _,
+                _phantom: PhantomData,
+            },
+            big_slots: StatePartLen {
+                value: self.0.big_slots.len() as _,
+                _phantom: PhantomData,
+            },
+        }
+    }
+    fn keys_for_assignment(
+        &mut self,
+        assignment_index: usize,
+    ) -> SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+        SlotToAssignmentIndexFullMapKeysForAssignment {
+            map: self,
+            assignment_index,
+        }
+    }
+    fn for_each(
+        &self,
+        mut small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>, &[usize]),
+        mut big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>, &[usize]),
+    ) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().enumerate().for_each(|(k, v)| {
+            small_slots_fn(
+                StatePartIndex {
+                    value: k as _,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        });
+        big_slots.iter().enumerate().for_each(|(k, v)| {
+            big_slots_fn(
+                StatePartIndex {
+                    value: k as _,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        });
+    }
+}
+
+impl std::ops::Index<StatePartIndex<StatePartKindSmallSlots>> for SlotToAssignmentIndexFullMap {
+    type Output = Vec<usize>;
+
+    fn index(&self, index: StatePartIndex<StatePartKindSmallSlots>) -> &Self::Output {
+        &self.0.small_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::IndexMut<StatePartIndex<StatePartKindSmallSlots>> for SlotToAssignmentIndexFullMap {
+    fn index_mut(&mut self, index: StatePartIndex<StatePartKindSmallSlots>) -> &mut Self::Output {
+        &mut self.0.small_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::Index<StatePartIndex<StatePartKindBigSlots>> for SlotToAssignmentIndexFullMap {
+    type Output = Vec<usize>;
+
+    fn index(&self, index: StatePartIndex<StatePartKindBigSlots>) -> &Self::Output {
+        &self.0.big_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::IndexMut<StatePartIndex<StatePartKindBigSlots>> for SlotToAssignmentIndexFullMap {
+    fn index_mut(&mut self, index: StatePartIndex<StatePartKindBigSlots>) -> &mut Self::Output {
+        &mut self.0.big_slots[index.as_usize()]
+    }
+}
+
+struct SlotToAssignmentIndexFullMapKeysForAssignment<'a> {
+    map: &'a mut SlotToAssignmentIndexFullMap,
+    assignment_index: usize,
+}
+
+impl<'a, K: StatePartKind> Extend<&'a StatePartIndex<K>>
+    for SlotToAssignmentIndexFullMapKeysForAssignment<'_>
+where
+    Self: Extend<StatePartIndex<K>>,
+{
+    fn extend<T: IntoIterator<Item = &'a StatePartIndex<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().copied());
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndex<K>>
+    for SlotToAssignmentIndexFullMapKeysForAssignment<'_>
+where
+    SlotToAssignmentIndexFullMap: IndexMut<StatePartIndex<K>, Output = Vec<usize>>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndex<K>>>(&mut self, iter: T) {
+        iter.into_iter()
+            .for_each(|slot| self.map[slot].push(self.assignment_index));
+    }
+}
+
+impl<'a> Extend<&'a SlotSet> for SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = &'a SlotSet>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |SlotSet(TypeParts {
+                 small_slots,
+                 big_slots,
+             })| {
+                self.extend(small_slots);
+                self.extend(big_slots);
+            },
+        );
+    }
+}
+
+impl<'a> Extend<&'a Cond> for SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = &'a Cond>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|cond| match cond.body {
+            CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
+                let CompiledValue {
+                    range:
+                        TypeIndexRange {
+                            small_slots,
+                            big_slots,
+                        },
+                    layout: _,
+                    write: _,
+                } = cond;
+                self.extend(small_slots.iter());
+                self.extend(big_slots.iter());
+            }
+            CondBody::MatchArm {
+                discriminant,
+                variant_index: _,
+            } => self.extend([discriminant]),
+        });
+    }
+}
+
+impl Assignment {
+    fn new(
+        conditions: Interned<[Cond]>,
+        insns: Vec<InsnOrLabel>,
+        source_location: SourceLocation,
+    ) -> Self {
+        let mut inputs = SlotSet::default();
+        let mut outputs = SlotSet::default();
+        for insn in &insns {
+            let insn = match insn {
+                InsnOrLabel::Insn(insn) => insn,
+                InsnOrLabel::Label(_) => continue,
+            };
+            for InsnField { ty, kind } in insn.fields() {
+                match (kind, ty) {
+                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&slot)) => {
+                        inputs.extend([slot]);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&slot)) => {
+                        inputs.extend([slot]);
+                    }
+                    (
+                        InsnFieldKind::Input,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&slot)) => {
+                        outputs.extend([slot]);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&slot)) => {
+                        outputs.extend([slot]);
+                    }
+                    (
+                        InsnFieldKind::Output,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| {
+                            outputs.extend([slot]);
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| {
+                            outputs.extend([slot]);
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (
+                        _,
+                        InsnFieldType::Memory(_)
+                        | InsnFieldType::SmallUInt(_)
+                        | InsnFieldType::SmallSInt(_)
+                        | InsnFieldType::InternedBigInt(_)
+                        | InsnFieldType::U8(_)
+                        | InsnFieldType::USize(_)
+                        | InsnFieldType::Empty(_),
+                    )
+                    | (
+                        InsnFieldKind::Immediate
+                        | InsnFieldKind::Memory
+                        | InsnFieldKind::BranchTarget,
+                        _,
+                    ) => {}
+                }
+            }
+        }
+        Self {
+            inputs,
+            outputs,
+            conditions,
+            insns,
+            source_location,
+        }
+    }
+}
+
+#[derive(Debug)]
+struct RegisterReset {
+    is_async: bool,
+    init: CompiledValue<CanonicalType>,
+    rst: StatePartIndex<StatePartKindSmallSlots>,
+}
+
+#[derive(Debug, Clone, Copy)]
+struct ClockTrigger {
+    last_clk_was_low: StatePartIndex<StatePartKindSmallSlots>,
+    clk: StatePartIndex<StatePartKindSmallSlots>,
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    source_location: SourceLocation,
+}
+
+#[derive(Debug)]
+struct Register {
+    value: CompiledValue<CanonicalType>,
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    reset: Option<RegisterReset>,
+    source_location: SourceLocation,
+}
+
+#[derive(Debug)]
+
+struct MemoryPort {
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    addr_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    en_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    data_layout: CompiledTypeLayout<CanonicalType>,
+    read_data_delayed: Vec<TypeIndexRange>,
+    write_data_delayed: Vec<TypeIndexRange>,
+    write_mask_delayed: Vec<TypeIndexRange>,
+    write_mode_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    write_insns: Vec<InsnOrLabel>,
+}
+
+struct MemoryPortReadInsns<'a> {
+    addr: StatePartIndex<StatePartKindSmallSlots>,
+    en: StatePartIndex<StatePartKindSmallSlots>,
+    write_mode: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    data: TypeIndexRange,
+    insns: &'a mut Vec<InsnOrLabel>,
+}
+
+struct MemoryPortWriteInsns<'a> {
+    addr: StatePartIndex<StatePartKindSmallSlots>,
+    en: StatePartIndex<StatePartKindSmallSlots>,
+    write_mode: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    data: TypeIndexRange,
+    mask: TypeIndexRange,
+    insns: &'a mut Vec<InsnOrLabel>,
+}
+
+#[derive(Debug)]
+struct Memory {
+    mem: Mem,
+    memory: StatePartIndex<StatePartKindMemories>,
+    trace: TraceMem,
+    ports: Vec<MemoryPort>,
+}
+
+#[derive(Copy, Clone)]
+enum MakeTraceDeclTarget {
+    Expr(Expr<CanonicalType>),
+    Memory {
+        id: TraceMemoryId,
+        depth: usize,
+        stride: usize,
+        start: usize,
+        ty: CanonicalType,
+    },
+}
+
+impl MakeTraceDeclTarget {
+    fn flow(self) -> Flow {
+        match self {
+            MakeTraceDeclTarget::Expr(expr) => Expr::flow(expr),
+            MakeTraceDeclTarget::Memory { .. } => Flow::Duplex,
+        }
+    }
+    fn ty(self) -> CanonicalType {
+        match self {
+            MakeTraceDeclTarget::Expr(expr) => Expr::ty(expr),
+            MakeTraceDeclTarget::Memory { ty, .. } => ty,
+        }
+    }
+}
+
+struct DebugOpaque<T>(T);
+
+impl<T> fmt::Debug for DebugOpaque<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str("<...>")
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct CompiledExternModule {
+    module_io_targets: Interned<[Target]>,
+    module_io: Interned<[CompiledValue<CanonicalType>]>,
+    simulation: ExternModuleSimulation,
+}
+
+#[derive(Debug)]
+pub struct Compiler {
+    insns: Insns<InsnsBuilding>,
+    original_base_module: Interned<Module<Bundle>>,
+    base_module: Interned<Module<Bundle>>,
+    modules: HashMap<InstantiatedModule, CompiledModule>,
+    extern_modules: Vec<CompiledExternModule>,
+    compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
+    compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
+    compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
+    decl_conditions: HashMap<TargetInInstantiatedModule, Interned<[Cond]>>,
+    compiled_values_to_dyn_array_indexes:
+        HashMap<CompiledValue<UInt>, StatePartIndex<StatePartKindSmallSlots>>,
+    compiled_value_bool_dest_is_small_map:
+        HashMap<CompiledValue<CanonicalType>, StatePartIndex<StatePartKindSmallSlots>>,
+    assignments: Assignments,
+    clock_triggers: Vec<ClockTrigger>,
+    compiled_value_to_clock_trigger_map: HashMap<CompiledValue<Clock>, ClockTrigger>,
+    enum_discriminants: HashMap<CompiledValue<Enum>, StatePartIndex<StatePartKindSmallSlots>>,
+    registers: Vec<Register>,
+    traces: SimTraces<Vec<SimTrace<SimTraceKind, ()>>>,
+    memories: Vec<Memory>,
+    dump_assignments_dot: Option<DebugOpaque<Box<dyn Fn(&dyn fmt::Debug)>>>,
+}
+
+impl Compiler {
+    pub fn new(base_module: Interned<Module<Bundle>>) -> Self {
+        let original_base_module = base_module;
+        let base_module = deduce_resets(base_module, true)
+            .unwrap_or_else(|e| panic!("failed to deduce reset types: {e}"));
+        Self {
+            insns: Insns::new(),
+            original_base_module,
+            base_module,
+            modules: HashMap::default(),
+            extern_modules: Vec::new(),
+            compiled_values: HashMap::default(),
+            compiled_exprs: HashMap::default(),
+            compiled_exprs_to_values: HashMap::default(),
+            decl_conditions: HashMap::default(),
+            compiled_values_to_dyn_array_indexes: HashMap::default(),
+            compiled_value_bool_dest_is_small_map: HashMap::default(),
+            assignments: Assignments::default(),
+            clock_triggers: Vec::new(),
+            compiled_value_to_clock_trigger_map: HashMap::default(),
+            enum_discriminants: HashMap::default(),
+            registers: Vec::new(),
+            traces: SimTraces(Vec::new()),
+            memories: Vec::new(),
+            dump_assignments_dot: None,
+        }
+    }
+    #[doc(hidden)]
+    /// This is explicitly unstable and may be changed/removed at any time
+    pub fn dump_assignments_dot(&mut self, callback: Box<dyn Fn(&dyn fmt::Debug)>) {
+        self.dump_assignments_dot = Some(DebugOpaque(callback));
+    }
+    fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
+        let id = TraceScalarId(self.traces.0.len());
+        self.traces.0.push(SimTrace {
+            kind,
+            state: (),
+            last_state: (),
+        });
+        id
+    }
+    fn make_trace_scalar_helper(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        target: MakeTraceDeclTarget,
+        source_location: SourceLocation,
+        small_kind: impl FnOnce(StatePartIndex<StatePartKindSmallSlots>) -> SimTraceKind,
+        big_kind: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> SimTraceKind,
+    ) -> TraceLocation {
+        match target {
+            MakeTraceDeclTarget::Expr(target) => {
+                let compiled_value = self.compile_expr(instantiated_module, target);
+                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
+                TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len() {
+                    TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
+                    TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
+                    _ => unreachable!(),
+                }))
+            }
+            MakeTraceDeclTarget::Memory {
+                id,
+                depth,
+                stride,
+                start,
+                ty,
+            } => TraceLocation::Memory(TraceMemoryLocation {
+                id,
+                depth,
+                stride,
+                start,
+                len: ty.bit_width(),
+            }),
+        }
+    }
+    fn make_trace_scalar(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        target: MakeTraceDeclTarget,
+        name: Interned<str>,
+        source_location: SourceLocation,
+    ) -> TraceDecl {
+        let flow = target.flow();
+        match target.ty() {
+            CanonicalType::UInt(ty) => TraceUInt {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallUInt { index, ty },
+                    |index| SimTraceKind::BigUInt { index, ty },
+                ),
+                name,
+                ty,
+                flow,
+            }
+            .into(),
+            CanonicalType::SInt(ty) => TraceSInt {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallSInt { index, ty },
+                    |index| SimTraceKind::BigSInt { index, ty },
+                ),
+                name,
+                ty,
+                flow,
+            }
+            .into(),
+            CanonicalType::Bool(_) => TraceBool {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallBool { index },
+                    |index| SimTraceKind::BigBool { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::Array(_) => unreachable!(),
+            CanonicalType::Enum(ty) => {
+                assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width);
+                let location = match target {
+                    MakeTraceDeclTarget::Expr(target) => {
+                        let compiled_value = self.compile_expr(instantiated_module, target);
+                        let compiled_value =
+                            self.compiled_expr_to_value(compiled_value, source_location);
+                        let discriminant = self.compile_enum_discriminant(
+                            compiled_value.map_ty(Enum::from_canonical),
+                            source_location,
+                        );
+                        TraceLocation::Scalar(self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                            index: discriminant,
+                            ty,
+                        }))
+                    }
+                    MakeTraceDeclTarget::Memory {
+                        id,
+                        depth,
+                        stride,
+                        start,
+                        ty: _,
+                    } => TraceLocation::Memory(TraceMemoryLocation {
+                        id,
+                        depth,
+                        stride,
+                        start,
+                        len: ty.type_properties().bit_width,
+                    }),
+                };
+                TraceFieldlessEnum {
+                    location,
+                    name,
+                    ty,
+                    flow,
+                }
+                .into()
+            }
+            CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) => unreachable!(),
+            CanonicalType::AsyncReset(_) => TraceAsyncReset {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallAsyncReset { index },
+                    |index| SimTraceKind::BigAsyncReset { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::SyncReset(_) => TraceSyncReset {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallSyncReset { index },
+                    |index| SimTraceKind::BigSyncReset { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::Reset(_) => unreachable!(),
+            CanonicalType::Clock(_) => TraceClock {
+                location: self.make_trace_scalar_helper(
+                    instantiated_module,
+                    target,
+                    source_location,
+                    |index| SimTraceKind::SmallClock { index },
+                    |index| SimTraceKind::BigClock { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+        }
+    }
+    fn make_trace_decl_child(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        target: MakeTraceDeclTarget,
+        name: Interned<str>,
+        source_location: SourceLocation,
+    ) -> TraceDecl {
+        match target.ty() {
+            CanonicalType::Array(ty) => {
+                let elements = Interned::from_iter((0..ty.len()).map(|index| {
+                    self.make_trace_decl_child(
+                        instantiated_module,
+                        match target {
+                            MakeTraceDeclTarget::Expr(target) => MakeTraceDeclTarget::Expr(
+                                Expr::<Array>::from_canonical(target)[index],
+                            ),
+                            MakeTraceDeclTarget::Memory {
+                                id,
+                                depth,
+                                stride,
+                                start,
+                                ty: _,
+                            } => MakeTraceDeclTarget::Memory {
+                                id,
+                                depth,
+                                stride,
+                                start: start + ty.element().bit_width() * index,
+                                ty: ty.element(),
+                            },
+                        },
+                        Intern::intern_owned(format!("[{index}]")),
+                        source_location,
+                    )
+                }));
+                TraceArray {
+                    name,
+                    elements,
+                    ty,
+                    flow: target.flow(),
+                }
+                .into()
+            }
+            CanonicalType::Enum(ty) => {
+                if ty.variants().iter().all(|v| v.ty.is_none()) {
+                    self.make_trace_scalar(instantiated_module, target, name, source_location)
+                } else {
+                    let flow = target.flow();
+                    let location = match target {
+                        MakeTraceDeclTarget::Expr(target) => {
+                            let compiled_value = self.compile_expr(instantiated_module, target);
+                            let compiled_value =
+                                self.compiled_expr_to_value(compiled_value, source_location);
+                            let discriminant = self.compile_enum_discriminant(
+                                compiled_value.map_ty(Enum::from_canonical),
+                                source_location,
+                            );
+                            TraceLocation::Scalar(self.new_sim_trace(
+                                SimTraceKind::EnumDiscriminant {
+                                    index: discriminant,
+                                    ty,
+                                },
+                            ))
+                        }
+                        MakeTraceDeclTarget::Memory {
+                            id,
+                            depth,
+                            stride,
+                            start,
+                            ty: _,
+                        } => TraceLocation::Memory(TraceMemoryLocation {
+                            id,
+                            depth,
+                            stride,
+                            start,
+                            len: ty.discriminant_bit_width(),
+                        }),
+                    };
+                    let discriminant = TraceEnumDiscriminant {
+                        location,
+                        name: "$tag".intern(),
+                        ty,
+                        flow,
+                    };
+                    let non_empty_fields =
+                        Interned::from_iter(ty.variants().into_iter().enumerate().flat_map(
+                            |(variant_index, variant)| {
+                                variant.ty.map(|variant_ty| {
+                                    self.make_trace_decl_child(
+                                        instantiated_module,
+                                        match target {
+                                            MakeTraceDeclTarget::Expr(target) => {
+                                                MakeTraceDeclTarget::Expr(
+                                                    ops::VariantAccess::new_by_index(
+                                                        Expr::<Enum>::from_canonical(target),
+                                                        variant_index,
+                                                    )
+                                                    .to_expr(),
+                                                )
+                                            }
+                                            MakeTraceDeclTarget::Memory {
+                                                id,
+                                                depth,
+                                                stride,
+                                                start,
+                                                ty: _,
+                                            } => MakeTraceDeclTarget::Memory {
+                                                id,
+                                                depth,
+                                                stride,
+                                                start: start + ty.discriminant_bit_width(),
+                                                ty: variant_ty,
+                                            },
+                                        },
+                                        variant.name,
+                                        source_location,
+                                    )
+                                })
+                            },
+                        ));
+                    TraceEnumWithFields {
+                        name,
+                        discriminant,
+                        non_empty_fields,
+                        ty,
+                        flow,
+                    }
+                    .into()
+                }
+            }
+            CanonicalType::Bundle(ty) => {
+                let fields = Interned::from_iter(ty.fields().iter().zip(ty.field_offsets()).map(
+                    |(field, field_offset)| {
+                        self.make_trace_decl_child(
+                            instantiated_module,
+                            match target {
+                                MakeTraceDeclTarget::Expr(target) => {
+                                    MakeTraceDeclTarget::Expr(Expr::field(
+                                        Expr::<Bundle>::from_canonical(target),
+                                        &field.name,
+                                    ))
+                                }
+                                MakeTraceDeclTarget::Memory {
+                                    id,
+                                    depth,
+                                    stride,
+                                    start,
+                                    ty: _,
+                                } => MakeTraceDeclTarget::Memory {
+                                    id,
+                                    depth,
+                                    stride,
+                                    start: start + field_offset,
+                                    ty: field.ty,
+                                },
+                            },
+                            field.name,
+                            source_location,
+                        )
+                    },
+                ));
+                TraceBundle {
+                    name,
+                    fields,
+                    ty,
+                    flow: target.flow(),
+                }
+                .into()
+            }
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => {
+                self.make_trace_scalar(instantiated_module, target, name, source_location)
+            }
+            CanonicalType::PhantomConst(_) => TraceBundle {
+                name,
+                fields: Interned::default(),
+                ty: Bundle::new(Interned::default()),
+                flow: target.flow(),
+            }
+            .into(),
+        }
+    }
+    fn make_trace_decl(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        target_base: TargetBase,
+    ) -> TraceDecl {
+        let target = MakeTraceDeclTarget::Expr(target_base.to_expr());
+        match target_base {
+            TargetBase::ModuleIO(module_io) => TraceModuleIO {
+                name: module_io.name(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        module_io.name(),
+                        module_io.source_location(),
+                    )
+                    .intern(),
+                ty: module_io.ty(),
+                flow: module_io.flow(),
+            }
+            .into(),
+            TargetBase::MemPort(mem_port) => {
+                let name = Intern::intern_owned(mem_port.port_name().to_string());
+                let TraceDecl::Scope(TraceScope::Bundle(bundle)) = self.make_trace_decl_child(
+                    instantiated_module,
+                    target,
+                    name,
+                    mem_port.source_location(),
+                ) else {
+                    unreachable!()
+                };
+                TraceMemPort {
+                    name,
+                    bundle,
+                    ty: mem_port.ty(),
+                }
+                .into()
+            }
+            TargetBase::Reg(reg) => TraceReg {
+                name: reg.name(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
+                ty: reg.ty(),
+            }
+            .into(),
+            TargetBase::RegSync(reg) => TraceReg {
+                name: reg.name(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
+                ty: reg.ty(),
+            }
+            .into(),
+            TargetBase::RegAsync(reg) => TraceReg {
+                name: reg.name(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
+                ty: reg.ty(),
+            }
+            .into(),
+            TargetBase::Wire(wire) => TraceWire {
+                name: wire.name(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        wire.name(),
+                        wire.source_location(),
+                    )
+                    .intern(),
+                ty: wire.ty(),
+            }
+            .into(),
+            TargetBase::Instance(instance) => {
+                let TraceDecl::Scope(TraceScope::Bundle(instance_io)) = self.make_trace_decl_child(
+                    instantiated_module,
+                    target,
+                    instance.name(),
+                    instance.source_location(),
+                ) else {
+                    unreachable!()
+                };
+                let compiled_module = &self.modules[&InstantiatedModule::Child {
+                    parent: instantiated_module.intern(),
+                    instance: instance.intern(),
+                }];
+                TraceInstance {
+                    name: instance.name(),
+                    instance_io,
+                    module: compiled_module.trace_decls,
+                    ty: instance.ty(),
+                }
+                .into()
+            }
+        }
+    }
+    fn compile_value(
+        &mut self,
+        target: TargetInInstantiatedModule,
+    ) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.compiled_values.get(&target) {
+            return retval;
+        }
+        let retval = match target.target {
+            Target::Base(base) => {
+                let unprefixed_layout = CompiledTypeLayout::get(base.canonical_ty());
+                let layout = unprefixed_layout.with_prefixed_debug_names(&format!(
+                    "{:?}.{:?}",
+                    target.instantiated_module,
+                    base.target_name()
+                ));
+                let range = self.insns.allocate_variable(&layout.layout);
+                let write = match *base {
+                    TargetBase::ModuleIO(_)
+                    | TargetBase::MemPort(_)
+                    | TargetBase::Wire(_)
+                    | TargetBase::Instance(_) => None,
+                    TargetBase::Reg(_) | TargetBase::RegSync(_) | TargetBase::RegAsync(_) => {
+                        let write_layout = unprefixed_layout.with_prefixed_debug_names(&format!(
+                            "{:?}.{:?}$next",
+                            target.instantiated_module,
+                            base.target_name()
+                        ));
+                        Some((
+                            write_layout,
+                            self.insns.allocate_variable(&write_layout.layout),
+                        ))
+                    }
+                };
+                CompiledValue {
+                    range,
+                    layout,
+                    write,
+                }
+            }
+            Target::Child(target_child) => {
+                let parent = self.compile_value(TargetInInstantiatedModule {
+                    instantiated_module: target.instantiated_module,
+                    target: *target_child.parent(),
+                });
+                match *target_child.path_element() {
+                    TargetPathElement::BundleField(TargetPathBundleField { name }) => {
+                        parent.map_ty(Bundle::from_canonical).field_by_name(name)
+                    }
+                    TargetPathElement::ArrayElement(TargetPathArrayElement { index }) => {
+                        parent.map_ty(Array::from_canonical).element(index)
+                    }
+                    TargetPathElement::DynArrayElement(_) => unreachable!(),
+                }
+            }
+        };
+        self.compiled_values.insert(target, retval);
+        retval
+    }
+    fn compiled_expr_to_value(
+        &mut self,
+        expr: CompiledExpr<CanonicalType>,
+        source_location: SourceLocation,
+    ) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.compiled_exprs_to_values.get(&expr) {
+            return retval;
+        }
+        assert!(
+            expr.static_part.layout.ty.is_passive(),
+            "invalid expression passed to compiled_expr_to_value -- type must be passive",
+        );
+        let CompiledExpr {
+            static_part,
+            indexes,
+        } = expr;
+        let retval = if indexes.as_ref().is_empty() {
+            CompiledValue {
+                layout: static_part.layout,
+                range: static_part.range,
+                write: None,
+            }
+        } else {
+            let layout = static_part.layout.with_anonymized_debug_info();
+            let retval = CompiledValue {
+                layout,
+                range: self.insns.allocate_variable(&layout.layout),
+                write: None,
+            };
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = retval.range;
+            self.add_assignment(
+                Interned::default(),
+                small_slots
+                    .iter()
+                    .zip(static_part.range.small_slots.iter())
+                    .map(|(dest, base)| Insn::ReadSmallIndexed {
+                        dest,
+                        src: StatePartArrayIndexed {
+                            base,
+                            indexes: indexes.small_slots,
+                        },
+                    })
+                    .chain(
+                        big_slots
+                            .iter()
+                            .zip(static_part.range.big_slots.iter())
+                            .map(|(dest, base)| Insn::ReadIndexed {
+                                dest,
+                                src: StatePartArrayIndexed {
+                                    base,
+                                    indexes: indexes.big_slots,
+                                },
+                            }),
+                    ),
+                source_location,
+            );
+            retval
+        };
+        self.compiled_exprs_to_values.insert(expr, retval);
+        retval
+    }
+    fn add_assignment<T: Into<InsnOrLabel>>(
+        &mut self,
+        conditions: Interned<[Cond]>,
+        insns: impl IntoIterator<Item = T>,
+        source_location: SourceLocation,
+    ) {
+        let insns = Vec::from_iter(insns.into_iter().map(Into::into));
+        self.assignments
+            .push(Assignment::new(conditions, insns, source_location));
+    }
+    fn simple_big_expr_input(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        input: Expr<CanonicalType>,
+    ) -> StatePartIndex<StatePartKindBigSlots> {
+        let input = self.compile_expr(instantiated_module, input);
+        let input =
+            self.compiled_expr_to_value(input, instantiated_module.leaf_module().source_location());
+        assert_eq!(input.range.len(), TypeLen::A_BIG_SLOT);
+        input.range.big_slots.start
+    }
+    fn compile_expr_helper(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        make_insns: impl FnOnce(&mut Self, TypeIndexRange) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        let layout = CompiledTypeLayout::get(dest_ty);
+        let range = self.insns.allocate_variable(&layout.layout);
+        let retval = CompiledValue {
+            layout,
+            range,
+            write: None,
+        };
+        let insns = make_insns(self, range);
+        self.add_assignment(
+            Interned::default(),
+            insns,
+            instantiated_module.leaf_module().source_location(),
+        );
+        retval
+    }
+    fn simple_nary_big_expr_helper(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        make_insns: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        self.compile_expr_helper(instantiated_module, dest_ty, |_, dest| {
+            assert_eq!(dest.len(), TypeLen::A_BIG_SLOT);
+            make_insns(dest.big_slots.start)
+        })
+    }
+    fn simple_nary_big_expr<const N: usize>(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        inputs: [Expr<CanonicalType>; N],
+        make_insns: impl FnOnce(
+            StatePartIndex<StatePartKindBigSlots>,
+            [StatePartIndex<StatePartKindBigSlots>; N],
+        ) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        let inputs = inputs.map(|input| self.simple_big_expr_input(instantiated_module, input));
+        self.simple_nary_big_expr_helper(instantiated_module, dest_ty, |dest| {
+            make_insns(dest, inputs)
+        })
+    }
+    fn compiled_value_to_dyn_array_index(
+        &mut self,
+        compiled_value: CompiledValue<UInt>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self
+            .compiled_values_to_dyn_array_indexes
+            .get(&compiled_value)
+        {
+            return retval;
+        }
+        let mut ty = compiled_value.layout.ty;
+        ty.width = ty.width.min(SmallUInt::BITS as usize);
+        let retval = match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => compiled_value.range.small_slots.start,
+            TypeLen::A_BIG_SLOT => {
+                let debug_data = SlotDebugData {
+                    name: Interned::default(),
+                    ty: ty.canonical(),
+                };
+                let dest = self
+                    .insns
+                    .allocate_variable(&TypeLayout {
+                        small_slots: StatePartLayout::scalar(debug_data, ()),
+                        big_slots: StatePartLayout::empty(),
+                    })
+                    .small_slots
+                    .start;
+                self.add_assignment(
+                    Interned::default(),
+                    vec![Insn::CastBigToArrayIndex {
+                        dest,
+                        src: compiled_value.range.big_slots.start,
+                    }],
+                    source_location,
+                );
+                dest
+            }
+            _ => unreachable!(),
+        };
+        self.compiled_values_to_dyn_array_indexes
+            .insert(compiled_value, retval);
+        retval
+    }
+    fn compiled_value_bool_dest_is_small(
+        &mut self,
+        compiled_value: CompiledValue<CanonicalType>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self
+            .compiled_value_bool_dest_is_small_map
+            .get(&compiled_value)
+        {
+            return retval;
+        }
+        let retval = match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => compiled_value.range.small_slots.start,
+            TypeLen::A_BIG_SLOT => {
+                let debug_data = SlotDebugData {
+                    name: Interned::default(),
+                    ty: Bool.canonical(),
+                };
+                let dest = self
+                    .insns
+                    .allocate_variable(&TypeLayout {
+                        small_slots: StatePartLayout::scalar(debug_data, ()),
+                        big_slots: StatePartLayout::empty(),
+                    })
+                    .small_slots
+                    .start;
+                self.add_assignment(
+                    Interned::default(),
+                    vec![Insn::IsNonZeroDestIsSmall {
+                        dest,
+                        src: compiled_value.range.big_slots.start,
+                    }],
+                    source_location,
+                );
+                dest
+            }
+            _ => unreachable!(),
+        };
+        self.compiled_value_bool_dest_is_small_map
+            .insert(compiled_value, retval);
+        retval
+    }
+    fn compile_cast_scalar_to_bits<T: Type>(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        arg: Expr<CanonicalType>,
+        cast_fn: impl FnOnce(Expr<T>) -> Expr<UInt>,
+    ) -> CompiledValue<UInt> {
+        let arg = Expr::<T>::from_canonical(arg);
+        let retval = cast_fn(arg);
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        let retval = self
+            .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location());
+        retval.map_ty(UInt::from_canonical)
+    }
+    fn compile_cast_aggregate_to_bits(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        parts: impl IntoIterator<Item = Expr<CanonicalType>>,
+    ) -> CompiledValue<UInt> {
+        let retval = parts
+            .into_iter()
+            .map(|part| part.cast_to_bits())
+            .reduce(|accumulator, part| accumulator | (part << Expr::ty(accumulator).width))
+            .unwrap_or_else(|| UInt[0].zero().to_expr());
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        let retval = self
+            .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location());
+        retval.map_ty(UInt::from_canonical)
+    }
+    fn compile_cast_to_bits(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: ops::CastToBits,
+    ) -> CompiledValue<UInt> {
+        match Expr::ty(expr.arg()) {
+            CanonicalType::UInt(_) => {
+                self.compile_cast_scalar_to_bits(instantiated_module, expr.arg(), |arg| arg)
+            }
+            CanonicalType::SInt(ty) => self.compile_cast_scalar_to_bits(
+                instantiated_module,
+                expr.arg(),
+                |arg: Expr<SInt>| arg.cast_to(ty.as_same_width_uint()),
+            ),
+            CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => self.compile_cast_scalar_to_bits(
+                instantiated_module,
+                expr.arg(),
+                |arg: Expr<Bool>| arg.cast_to(UInt[1]),
+            ),
+            CanonicalType::Array(ty) => self.compile_cast_aggregate_to_bits(
+                instantiated_module,
+                (0..ty.len()).map(|index| Expr::<Array>::from_canonical(expr.arg())[index]),
+            ),
+            CanonicalType::Enum(ty) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt[ty.type_properties().bit_width].canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Copy { dest, src }],
+                )
+                .map_ty(UInt::from_canonical),
+            CanonicalType::Bundle(ty) => self.compile_cast_aggregate_to_bits(
+                instantiated_module,
+                ty.fields().iter().map(|field| {
+                    Expr::field(Expr::<Bundle>::from_canonical(expr.arg()), &field.name)
+                }),
+            ),
+            CanonicalType::PhantomConst(_) => {
+                self.compile_cast_aggregate_to_bits(instantiated_module, [])
+            }
+        }
+    }
+    fn compile_cast_bits_to(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: ops::CastBitsTo,
+    ) -> CompiledValue<CanonicalType> {
+        let retval = match expr.ty() {
+            CanonicalType::UInt(_) => Expr::canonical(expr.arg()),
+            CanonicalType::SInt(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Bool(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Array(ty) => {
+                let stride = ty.element().bit_width();
+                Expr::<Array>::canonical(
+                    ops::ArrayLiteral::new(
+                        ty.element(),
+                        Interned::from_iter((0..ty.len()).map(|index| {
+                            let start = stride * index;
+                            let end = start + stride;
+                            expr.arg()[start..end].cast_bits_to(ty.element())
+                        })),
+                    )
+                    .to_expr(),
+                )
+            }
+            ty @ CanonicalType::Enum(_) => {
+                return self.simple_nary_big_expr(
+                    instantiated_module,
+                    ty,
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Copy { dest, src }],
+                );
+            }
+            CanonicalType::Bundle(ty) => Expr::canonical(
+                ops::BundleLiteral::new(
+                    ty,
+                    Interned::from_iter(ty.field_offsets().iter().zip(&ty.fields()).map(
+                        |(&offset, &field)| {
+                            let end = offset + field.ty.bit_width();
+                            expr.arg()[offset..end].cast_bits_to(field.ty)
+                        },
+                    )),
+                )
+                .to_expr(),
+            ),
+            CanonicalType::AsyncReset(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::SyncReset(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Reset(_) => unreachable!(),
+            CanonicalType::Clock(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::PhantomConst(ty) => {
+                let _ = self.compile_expr(instantiated_module, Expr::canonical(expr.arg()));
+                Expr::canonical(ty.to_expr())
+            }
+        };
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        self.compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location())
+    }
+    fn compile_aggregate_literal(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        inputs: Interned<[Expr<CanonicalType>]>,
+    ) -> CompiledValue<CanonicalType> {
+        self.compile_expr_helper(instantiated_module, dest_ty, |this, dest| {
+            let mut insns = Vec::new();
+            let mut offset = TypeIndex::ZERO;
+            for input in inputs {
+                let input = this.compile_expr(instantiated_module, input);
+                let input = this
+                    .compiled_expr_to_value(
+                        input,
+                        instantiated_module.leaf_module().source_location(),
+                    )
+                    .range;
+                insns.extend(
+                    input.insns_for_copy_to(dest.slice(TypeIndexRange::new(offset, input.len()))),
+                );
+                offset = offset.offset(input.len().as_index());
+            }
+            insns
+        })
+    }
+    fn compile_expr(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: Expr<CanonicalType>,
+    ) -> CompiledExpr<CanonicalType> {
+        if let Some(&retval) = self.compiled_exprs.get(&expr) {
+            return retval;
+        }
+        let mut cast_bit = |arg: Expr<CanonicalType>| {
+            let src_signed = match Expr::ty(arg) {
+                CanonicalType::UInt(_) => false,
+                CanonicalType::SInt(_) => true,
+                CanonicalType::Bool(_) => false,
+                CanonicalType::Array(_) => unreachable!(),
+                CanonicalType::Enum(_) => unreachable!(),
+                CanonicalType::Bundle(_) => unreachable!(),
+                CanonicalType::AsyncReset(_) => false,
+                CanonicalType::SyncReset(_) => false,
+                CanonicalType::Reset(_) => false,
+                CanonicalType::Clock(_) => false,
+                CanonicalType::PhantomConst(_) => unreachable!(),
+            };
+            let dest_signed = match Expr::ty(expr) {
+                CanonicalType::UInt(_) => false,
+                CanonicalType::SInt(_) => true,
+                CanonicalType::Bool(_) => false,
+                CanonicalType::Array(_) => unreachable!(),
+                CanonicalType::Enum(_) => unreachable!(),
+                CanonicalType::Bundle(_) => unreachable!(),
+                CanonicalType::AsyncReset(_) => false,
+                CanonicalType::SyncReset(_) => false,
+                CanonicalType::Reset(_) => false,
+                CanonicalType::Clock(_) => false,
+                CanonicalType::PhantomConst(_) => unreachable!(),
+            };
+            self.simple_nary_big_expr(instantiated_module, Expr::ty(expr), [arg], |dest, [src]| {
+                match (src_signed, dest_signed) {
+                    (false, false) | (true, true) => {
+                        vec![Insn::Copy { dest, src }]
+                    }
+                    (false, true) => vec![Insn::CastToSInt {
+                        dest,
+                        src,
+                        dest_width: 1,
+                    }],
+                    (true, false) => vec![Insn::CastToUInt {
+                        dest,
+                        src,
+                        dest_width: 1,
+                    }],
+                }
+            })
+            .into()
+        };
+        let retval: CompiledExpr<_> = match *Expr::expr_enum(expr) {
+            ExprEnum::UIntLiteral(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::Const {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SIntLiteral(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::Const {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::BoolLiteral(expr) => self
+                .simple_nary_big_expr(instantiated_module, Bool.canonical(), [], |dest, []| {
+                    vec![Insn::Const {
+                        dest,
+                        value: BigInt::from(expr).intern_sized(),
+                    }]
+                })
+                .into(),
+            ExprEnum::PhantomConst(_) => self
+                .compile_aggregate_literal(instantiated_module, Expr::ty(expr), Interned::default())
+                .into(),
+            ExprEnum::BundleLiteral(literal) => self
+                .compile_aggregate_literal(
+                    instantiated_module,
+                    Expr::ty(expr),
+                    literal.field_values(),
+                )
+                .into(),
+            ExprEnum::ArrayLiteral(literal) => self
+                .compile_aggregate_literal(
+                    instantiated_module,
+                    Expr::ty(expr),
+                    literal.element_values(),
+                )
+                .into(),
+            ExprEnum::EnumLiteral(expr) => {
+                let enum_bits_ty = UInt[expr.ty().type_properties().bit_width];
+                let enum_bits = if let Some(variant_value) = expr.variant_value() {
+                    (
+                        UInt[expr.ty().discriminant_bit_width()]
+                            .from_int_wrapping(expr.variant_index()),
+                        variant_value,
+                    )
+                        .cast_to_bits()
+                        .cast_to(enum_bits_ty)
+                } else {
+                    enum_bits_ty
+                        .from_int_wrapping(expr.variant_index())
+                        .to_expr()
+                };
+                self.compile_expr(
+                    instantiated_module,
+                    enum_bits.cast_bits_to(expr.ty().canonical()),
+                )
+            }
+            ExprEnum::Uninit(expr) => self.compile_expr(
+                instantiated_module,
+                UInt[expr.ty().bit_width()].zero().cast_bits_to(expr.ty()),
+            ),
+            ExprEnum::NotU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Expr::ty(expr.arg()).canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::NotU {
+                            dest,
+                            src,
+                            width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::NotS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Expr::ty(expr.arg()).canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::NotS { dest, src }],
+                )
+                .into(),
+            ExprEnum::NotB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Expr::ty(expr.arg()).canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::NotU {
+                            dest,
+                            src,
+                            width: 1,
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::Neg(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Neg { dest, src }],
+                )
+                .into(),
+            ExprEnum::BitAndU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitAndS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitAndB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::AddU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::AddS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::SubU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| {
+                        vec![Insn::SubU {
+                            dest,
+                            lhs,
+                            rhs,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SubS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::SubS { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::MulU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::MulS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DivU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DivS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::RemU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::RemS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShlU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShlS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShrU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShrS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::FixedShlU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shl {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShlS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shl {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShrU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shr {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShrS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shr {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CmpLtB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeB(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLtU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLtS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CastUIntToUInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToUInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CastUIntToSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToSInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CastSIntToUInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToUInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CastSIntToSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToSInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CastBoolToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::FieldAccess(expr) => self
+                .compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                .map_ty(Bundle::from_canonical)
+                .field_by_index(expr.field_index()),
+            ExprEnum::VariantAccess(variant_access) => {
+                let start = Expr::ty(variant_access.base()).discriminant_bit_width();
+                let len = Expr::ty(expr).bit_width();
+                self.compile_expr(
+                    instantiated_module,
+                    variant_access.base().cast_to_bits()[start..start + len]
+                        .cast_bits_to(Expr::ty(expr)),
+                )
+            }
+            ExprEnum::ArrayIndex(expr) => self
+                .compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                .map_ty(Array::from_canonical)
+                .element(expr.element_index()),
+            ExprEnum::DynArrayIndex(expr) => {
+                let element_index =
+                    self.compile_expr(instantiated_module, Expr::canonical(expr.element_index()));
+                let element_index = self.compiled_expr_to_value(
+                    element_index,
+                    instantiated_module.leaf_module().source_location(),
+                );
+                let index_slot = self.compiled_value_to_dyn_array_index(
+                    element_index.map_ty(UInt::from_canonical),
+                    instantiated_module.leaf_module().source_location(),
+                );
+                self.compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                    .map_ty(Array::from_canonical)
+                    .element_dyn(index_slot)
+            }
+            ExprEnum::ReduceBitAndU(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(true.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(
+                        expr.arg()
+                            .cmp_eq(Expr::ty(expr.arg()).from_int_wrapping(-1)),
+                    ),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitAndS(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(true.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(
+                        expr.arg()
+                            .cmp_eq(Expr::ty(expr.arg()).from_int_wrapping(-1)),
+                    ),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitOrU(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(false.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(expr.arg().cmp_ne(Expr::ty(expr.arg()).from_int_wrapping(0))),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitOrS(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(false.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(expr.arg().cmp_ne(Expr::ty(expr.arg()).from_int_wrapping(0))),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitXorU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::<1>::TYPE.canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::ReduceBitXor {
+                            dest,
+                            src,
+                            input_width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::ReduceBitXorS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::<1>::TYPE.canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::ReduceBitXor {
+                            dest,
+                            src,
+                            input_width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SliceUInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::new_dyn(expr.range().len()).canonical(),
+                    [Expr::canonical(expr.base())],
+                    |dest, [src]| {
+                        vec![Insn::SliceInt {
+                            dest,
+                            src,
+                            start: expr.range().start,
+                            len: expr.range().len(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SliceSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::new_dyn(expr.range().len()).canonical(),
+                    [Expr::canonical(expr.base())],
+                    |dest, [src]| {
+                        vec![Insn::SliceInt {
+                            dest,
+                            src,
+                            start: expr.range().start,
+                            len: expr.range().len(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CastToBits(expr) => self
+                .compile_cast_to_bits(instantiated_module, expr)
+                .map_ty(CanonicalType::UInt)
+                .into(),
+            ExprEnum::CastBitsTo(expr) => {
+                self.compile_cast_bits_to(instantiated_module, expr).into()
+            }
+            ExprEnum::ModuleIO(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Instance(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Wire(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Reg(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::RegSync(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::RegAsync(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::MemPort(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+        };
+        self.compiled_exprs.insert(expr, retval);
+        retval
+    }
+    fn compile_simple_connect(
+        &mut self,
+        conditions: Interned<[Cond]>,
+        lhs: CompiledExpr<CanonicalType>,
+        rhs: CompiledValue<CanonicalType>,
+        source_location: SourceLocation,
+    ) {
+        let CompiledExpr {
+            static_part: lhs_static_part,
+            indexes,
+        } = lhs;
+        let (lhs_layout, lhs_range) = lhs_static_part.write();
+        assert!(
+            lhs_layout.ty.is_passive(),
+            "invalid expression passed to compile_simple_connect -- type must be passive",
+        );
+        let TypeIndexRange {
+            small_slots,
+            big_slots,
+        } = lhs_range;
+        self.add_assignment(
+            conditions,
+            small_slots
+                .iter()
+                .zip(rhs.range.small_slots.iter())
+                .map(|(base, src)| {
+                    if indexes.small_slots.is_empty() {
+                        Insn::CopySmall { dest: base, src }
+                    } else {
+                        Insn::WriteSmallIndexed {
+                            dest: StatePartArrayIndexed {
+                                base,
+                                indexes: indexes.small_slots,
+                            },
+                            src,
+                        }
+                    }
+                })
+                .chain(
+                    big_slots
+                        .iter()
+                        .zip(rhs.range.big_slots.iter())
+                        .map(|(base, src)| {
+                            if indexes.big_slots.is_empty() {
+                                Insn::Copy { dest: base, src }
+                            } else {
+                                Insn::WriteIndexed {
+                                    dest: StatePartArrayIndexed {
+                                        base,
+                                        indexes: indexes.big_slots,
+                                    },
+                                    src,
+                                }
+                            }
+                        }),
+                ),
+            source_location,
+        );
+    }
+    fn compile_connect(
+        &mut self,
+        lhs_instantiated_module: InstantiatedModule,
+        lhs_conditions: Interned<[Cond]>,
+        lhs: Expr<CanonicalType>,
+        rhs_instantiated_module: InstantiatedModule,
+        rhs_conditions: Interned<[Cond]>,
+        mut rhs: Expr<CanonicalType>,
+        source_location: SourceLocation,
+    ) {
+        if Expr::ty(lhs) != Expr::ty(rhs) || !Expr::ty(lhs).is_passive() {
+            match Expr::ty(lhs) {
+                CanonicalType::UInt(lhs_ty) => {
+                    rhs = Expr::canonical(Expr::<UInt>::from_canonical(rhs).cast_to(lhs_ty));
+                }
+                CanonicalType::SInt(lhs_ty) => {
+                    rhs = Expr::canonical(Expr::<SInt>::from_canonical(rhs).cast_to(lhs_ty));
+                }
+                CanonicalType::Bool(_) => unreachable!(),
+                CanonicalType::Array(lhs_ty) => {
+                    let CanonicalType::Array(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    assert_eq!(lhs_ty.len(), rhs_ty.len());
+                    let lhs = Expr::<Array>::from_canonical(lhs);
+                    let rhs = Expr::<Array>::from_canonical(rhs);
+                    for index in 0..lhs_ty.len() {
+                        self.compile_connect(
+                            lhs_instantiated_module,
+                            lhs_conditions,
+                            lhs[index],
+                            rhs_instantiated_module,
+                            rhs_conditions,
+                            rhs[index],
+                            source_location,
+                        );
+                    }
+                    return;
+                }
+                CanonicalType::Enum(lhs_ty) => {
+                    let CanonicalType::Enum(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    todo!("handle connect with different enum types");
+                }
+                CanonicalType::Bundle(lhs_ty) => {
+                    let CanonicalType::Bundle(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    assert_eq!(lhs_ty.fields().len(), rhs_ty.fields().len());
+                    let lhs = Expr::<Bundle>::from_canonical(lhs);
+                    let rhs = Expr::<Bundle>::from_canonical(rhs);
+                    for (
+                        field_index,
+                        (
+                            BundleField {
+                                name,
+                                flipped,
+                                ty: _,
+                            },
+                            rhs_field,
+                        ),
+                    ) in lhs_ty.fields().into_iter().zip(rhs_ty.fields()).enumerate()
+                    {
+                        assert_eq!(name, rhs_field.name);
+                        assert_eq!(flipped, rhs_field.flipped);
+                        let lhs_expr = ops::FieldAccess::new_by_index(lhs, field_index).to_expr();
+                        let rhs_expr = ops::FieldAccess::new_by_index(rhs, field_index).to_expr();
+                        if flipped {
+                            // swap lhs/rhs
+                            self.compile_connect(
+                                rhs_instantiated_module,
+                                rhs_conditions,
+                                rhs_expr,
+                                lhs_instantiated_module,
+                                lhs_conditions,
+                                lhs_expr,
+                                source_location,
+                            );
+                        } else {
+                            self.compile_connect(
+                                lhs_instantiated_module,
+                                lhs_conditions,
+                                lhs_expr,
+                                rhs_instantiated_module,
+                                rhs_conditions,
+                                rhs_expr,
+                                source_location,
+                            );
+                        }
+                    }
+                    return;
+                }
+                CanonicalType::AsyncReset(_) => unreachable!(),
+                CanonicalType::SyncReset(_) => unreachable!(),
+                CanonicalType::Reset(_) => unreachable!(),
+                CanonicalType::Clock(_) => unreachable!(),
+                CanonicalType::PhantomConst(_) => unreachable!("PhantomConst mismatch"),
+            }
+        }
+        let Some(target) = lhs.target() else {
+            unreachable!("connect lhs must have target");
+        };
+        let lhs_decl_conditions = self.decl_conditions[&TargetInInstantiatedModule {
+            instantiated_module: lhs_instantiated_module,
+            target: target.base().into(),
+        }];
+        let lhs = self.compile_expr(lhs_instantiated_module, lhs);
+        let rhs = self.compile_expr(rhs_instantiated_module, rhs);
+        let rhs = self.compiled_expr_to_value(rhs, source_location);
+        self.compile_simple_connect(
+            lhs_conditions[lhs_decl_conditions.len()..].intern(),
+            lhs,
+            rhs,
+            source_location,
+        );
+    }
+    fn compile_clock(
+        &mut self,
+        clk: CompiledValue<Clock>,
+        source_location: SourceLocation,
+    ) -> ClockTrigger {
+        if let Some(&retval) = self.compiled_value_to_clock_trigger_map.get(&clk) {
+            return retval;
+        }
+        let mut alloc_small_slot = |part_name: &str| {
+            self.insns
+                .state_layout
+                .ty
+                .small_slots
+                .allocate(&StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty: Bool.canonical(),
+                    },
+                    (),
+                ))
+                .start
+        };
+        let last_clk_was_low = alloc_small_slot("last_clk_was_low");
+        let clk_triggered = alloc_small_slot("clk_triggered");
+        let retval = ClockTrigger {
+            last_clk_was_low,
+            clk: self.compiled_value_bool_dest_is_small(
+                clk.map_ty(CanonicalType::Clock),
+                source_location,
+            ),
+            clk_triggered,
+            source_location,
+        };
+        self.add_assignment(
+            Interned::default(),
+            [Insn::AndSmall {
+                dest: clk_triggered,
+                lhs: retval.clk,
+                rhs: last_clk_was_low,
+            }],
+            source_location,
+        );
+        self.clock_triggers.push(retval);
+        self.compiled_value_to_clock_trigger_map.insert(clk, retval);
+        retval
+    }
+    fn compile_enum_discriminant(
+        &mut self,
+        enum_value: CompiledValue<Enum>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self.enum_discriminants.get(&enum_value) {
+            return retval;
+        }
+        let retval_ty = Enum::new(
+            enum_value
+                .layout
+                .ty
+                .variants()
+                .iter()
+                .map(|variant| EnumVariant {
+                    name: variant.name,
+                    ty: None,
+                })
+                .collect(),
+        );
+        let retval = if retval_ty == enum_value.layout.ty
+            && enum_value.range.len() == TypeLen::A_SMALL_SLOT
+        {
+            enum_value.range.small_slots.start
+        } else {
+            let retval = self
+                .insns
+                .state_layout
+                .ty
+                .small_slots
+                .allocate(&StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty: retval_ty.canonical(),
+                    },
+                    (),
+                ))
+                .start;
+            let discriminant_bit_width = enum_value.layout.ty.discriminant_bit_width();
+            let discriminant_mask = !(!0u64 << discriminant_bit_width);
+            let insn = match enum_value.range.len() {
+                TypeLen::A_BIG_SLOT => Insn::AndBigWithSmallImmediate {
+                    dest: retval,
+                    lhs: enum_value.range.big_slots.start,
+                    rhs: discriminant_mask,
+                },
+                TypeLen::A_SMALL_SLOT => {
+                    if discriminant_bit_width == enum_value.layout.ty.type_properties().bit_width {
+                        Insn::CopySmall {
+                            dest: retval,
+                            src: enum_value.range.small_slots.start,
+                        }
+                    } else {
+                        Insn::AndSmallImmediate {
+                            dest: retval,
+                            lhs: enum_value.range.small_slots.start,
+                            rhs: discriminant_mask,
+                        }
+                    }
+                }
+                _ => unreachable!(),
+            };
+            self.add_assignment(Interned::default(), [insn], source_location);
+            retval
+        };
+        self.enum_discriminants.insert(enum_value, retval);
+        retval
+    }
+    fn compile_stmt_reg<R: ResetType>(
+        &mut self,
+        stmt_reg: StmtReg<R>,
+        instantiated_module: InstantiatedModule,
+        value: CompiledValue<CanonicalType>,
+    ) {
+        let StmtReg { annotations, reg } = stmt_reg;
+        let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk));
+        let clk = self
+            .compiled_expr_to_value(clk, reg.source_location())
+            .map_ty(Clock::from_canonical);
+        let clk = self.compile_clock(clk, reg.source_location());
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = ();
+
+            type Output<T: ResetType> = bool;
+
+            fn reset(self, _input: Self::Input<Reset>) -> Self::Output<Reset> {
+                unreachable!()
+            }
+
+            fn sync_reset(self, _input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                false
+            }
+
+            fn async_reset(self, _input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                true
+            }
+        }
+        let reset = if let Some(init) = reg.init() {
+            let init = self.compile_expr(instantiated_module, init);
+            let init = self.compiled_expr_to_value(init, reg.source_location());
+            let rst =
+                self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().rst));
+            let rst = self.compiled_expr_to_value(rst, reg.source_location());
+            let rst = self.compiled_value_bool_dest_is_small(rst, reg.source_location());
+            let is_async = R::dispatch((), Dispatch);
+            if is_async {
+                let cond = Expr::canonical(reg.clock_domain().rst.cast_to(Bool));
+                let cond = self.compile_expr(instantiated_module, cond);
+                let cond = self.compiled_expr_to_value(cond, reg.source_location());
+                let cond = cond.map_ty(Bool::from_canonical);
+                // write to the register's current value since asynchronous reset is combinational
+                let lhs = CompiledValue {
+                    layout: value.layout,
+                    range: value.range,
+                    write: None,
+                }
+                .into();
+                self.compile_simple_connect(
+                    [Cond {
+                        body: CondBody::IfTrue { cond },
+                        source_location: reg.source_location(),
+                    }][..]
+                        .intern(),
+                    lhs,
+                    init,
+                    reg.source_location(),
+                );
+            }
+            Some(RegisterReset {
+                is_async,
+                init,
+                rst,
+            })
+        } else {
+            None
+        };
+        self.registers.push(Register {
+            value,
+            clk_triggered: clk.clk_triggered,
+            reset,
+            source_location: reg.source_location(),
+        });
+    }
+    fn compile_declaration(
+        &mut self,
+        declaration: StmtDeclaration,
+        parent_module: Interned<InstantiatedModule>,
+        conditions: Interned<[Cond]>,
+    ) -> TraceDecl {
+        let target_base: TargetBase = match &declaration {
+            StmtDeclaration::Wire(v) => v.wire.into(),
+            StmtDeclaration::Reg(v) => v.reg.into(),
+            StmtDeclaration::RegSync(v) => v.reg.into(),
+            StmtDeclaration::RegAsync(v) => v.reg.into(),
+            StmtDeclaration::Instance(v) => v.instance.into(),
+        };
+        let target = TargetInInstantiatedModule {
+            instantiated_module: *parent_module,
+            target: target_base.into(),
+        };
+        self.decl_conditions.insert(target, conditions);
+        let compiled_value = self.compile_value(target);
+        match declaration {
+            StmtDeclaration::Wire(StmtWire { annotations, wire }) => {}
+            StmtDeclaration::Reg(_) => {
+                unreachable!("Reset types were already replaced by SyncReset or AsyncReset");
+            }
+            StmtDeclaration::RegSync(stmt_reg) => {
+                self.compile_stmt_reg(stmt_reg, *parent_module, compiled_value)
+            }
+            StmtDeclaration::RegAsync(stmt_reg) => {
+                self.compile_stmt_reg(stmt_reg, *parent_module, compiled_value)
+            }
+            StmtDeclaration::Instance(StmtInstance {
+                annotations,
+                instance,
+            }) => {
+                let inner_instantiated_module = InstantiatedModule::Child {
+                    parent: parent_module,
+                    instance: instance.intern_sized(),
+                }
+                .intern_sized();
+                let instance_expr = instance.to_expr();
+                self.compile_module(inner_instantiated_module);
+                for (field_index, module_io) in
+                    instance.instantiated().module_io().into_iter().enumerate()
+                {
+                    let instance_field =
+                        ops::FieldAccess::new_by_index(instance_expr, field_index).to_expr();
+                    match Expr::flow(instance_field) {
+                        Flow::Source => {
+                            // we need to supply the value to the instance since the
+                            // parent module expects to read from the instance
+                            self.compile_connect(
+                                *parent_module,
+                                conditions,
+                                instance_field,
+                                *inner_instantiated_module,
+                                Interned::default(),
+                                module_io.module_io.to_expr(),
+                                instance.source_location(),
+                            );
+                        }
+                        Flow::Sink => {
+                            // we need to take the value from the instance since the
+                            // parent module expects to write to the instance
+                            self.compile_connect(
+                                *inner_instantiated_module,
+                                Interned::default(),
+                                module_io.module_io.to_expr(),
+                                *parent_module,
+                                conditions,
+                                instance_field,
+                                instance.source_location(),
+                            );
+                        }
+                        Flow::Duplex => unreachable!(),
+                    }
+                }
+            }
+        }
+        self.make_trace_decl(*parent_module, target_base)
+    }
+    fn allocate_delay_chain<T, BK: InsnsBuildingKind>(
+        &mut self,
+        len: usize,
+        layout: &TypeLayout<BK>,
+        first: Option<T>,
+        last: Option<T>,
+        mut from_allocation: impl FnMut(TypeIndexRange) -> T,
+    ) -> Vec<T> {
+        match (len, first, last) {
+            (0, _, _) => Vec::new(),
+            (1, Some(v), _) | (1, None, Some(v)) => vec![v],
+            (2, Some(first), Some(last)) => vec![first, last],
+            (len, first, last) => {
+                let inner_len = len - first.is_some() as usize - last.is_some() as usize;
+                first
+                    .into_iter()
+                    .chain(
+                        (0..inner_len)
+                            .map(|_| from_allocation(self.insns.allocate_variable(layout))),
+                    )
+                    .chain(last)
+                    .collect()
+            }
+        }
+    }
+    fn allocate_delay_chain_small(
+        &mut self,
+        len: usize,
+        ty: CanonicalType,
+        first: Option<StatePartIndex<StatePartKindSmallSlots>>,
+        last: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    ) -> Vec<StatePartIndex<StatePartKindSmallSlots>> {
+        self.allocate_delay_chain(
+            len,
+            &TypeLayout {
+                small_slots: StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty,
+                    },
+                    (),
+                ),
+                big_slots: StatePartLayout::empty(),
+            },
+            first,
+            last,
+            |range| range.small_slots.start,
+        )
+    }
+    fn compile_memory_port_rw_helper(
+        &mut self,
+        memory: StatePartIndex<StatePartKindMemories>,
+        stride: usize,
+        mut start: usize,
+        data_layout: CompiledTypeLayout<CanonicalType>,
+        mask_layout: CompiledTypeLayout<CanonicalType>,
+        mut read: Option<MemoryPortReadInsns<'_>>,
+        mut write: Option<MemoryPortWriteInsns<'_>>,
+    ) {
+        match data_layout.body {
+            CompiledTypeLayoutBody::Scalar => {
+                let CompiledTypeLayoutBody::Scalar = mask_layout.body else {
+                    unreachable!();
+                };
+                let signed = match data_layout.ty {
+                    CanonicalType::UInt(_) => false,
+                    CanonicalType::SInt(_) => true,
+                    CanonicalType::Bool(_) => false,
+                    CanonicalType::Array(_) => unreachable!(),
+                    CanonicalType::Enum(_) => false,
+                    CanonicalType::Bundle(_) => unreachable!(),
+                    CanonicalType::AsyncReset(_) => false,
+                    CanonicalType::SyncReset(_) => false,
+                    CanonicalType::Reset(_) => false,
+                    CanonicalType::Clock(_) => false,
+                    CanonicalType::PhantomConst(_) => unreachable!(),
+                };
+                let width = data_layout.ty.bit_width();
+                if let Some(MemoryPortReadInsns {
+                    addr,
+                    en: _,
+                    write_mode: _,
+                    data,
+                    insns,
+                }) = read
+                {
+                    insns.push(
+                        match data.len() {
+                            TypeLen::A_BIG_SLOT => {
+                                let dest = data.big_slots.start;
+                                if signed {
+                                    Insn::MemoryReadSInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                } else {
+                                    Insn::MemoryReadUInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                }
+                            }
+                            TypeLen::A_SMALL_SLOT => {
+                                let _dest = data.small_slots.start;
+                                todo!("memory ports' data are always big for now");
+                            }
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                }
+                if let Some(MemoryPortWriteInsns {
+                    addr,
+                    en: _,
+                    write_mode: _,
+                    data,
+                    mask,
+                    insns,
+                }) = write
+                {
+                    let end_label = self.insns.new_label();
+                    insns.push(
+                        match mask.len() {
+                            TypeLen::A_BIG_SLOT => Insn::BranchIfZero {
+                                target: end_label.0,
+                                value: mask.big_slots.start,
+                            },
+                            TypeLen::A_SMALL_SLOT => Insn::BranchIfSmallZero {
+                                target: end_label.0,
+                                value: mask.small_slots.start,
+                            },
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                    insns.push(
+                        match data.len() {
+                            TypeLen::A_BIG_SLOT => {
+                                let value = data.big_slots.start;
+                                if signed {
+                                    Insn::MemoryWriteSInt {
+                                        value,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                } else {
+                                    Insn::MemoryWriteUInt {
+                                        value,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                }
+                            }
+                            TypeLen::A_SMALL_SLOT => {
+                                let _value = data.small_slots.start;
+                                todo!("memory ports' data are always big for now");
+                            }
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                    insns.push(end_label.into());
+                }
+            }
+            CompiledTypeLayoutBody::Array { element } => {
+                let CompiledTypeLayoutBody::Array {
+                    element: mask_element,
+                } = mask_layout.body
+                else {
+                    unreachable!();
+                };
+                let ty = <Array>::from_canonical(data_layout.ty);
+                let element_bit_width = ty.element().bit_width();
+                let element_size = element.layout.len();
+                let mask_element_size = mask_element.layout.len();
+                for element_index in 0..ty.len() {
+                    self.compile_memory_port_rw_helper(
+                        memory,
+                        stride,
+                        start,
+                        *element,
+                        *mask_element,
+                        read.as_mut().map(
+                            |MemoryPortReadInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 insns,
+                             }| MemoryPortReadInsns {
+                                addr: *addr,
+                                en: *en,
+                                write_mode: *write_mode,
+                                data: data.index_array(element_size, element_index),
+                                insns,
+                            },
+                        ),
+                        write.as_mut().map(
+                            |MemoryPortWriteInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 mask,
+                                 insns,
+                             }| {
+                                MemoryPortWriteInsns {
+                                    addr: *addr,
+                                    en: *en,
+                                    write_mode: *write_mode,
+                                    data: data.index_array(element_size, element_index),
+                                    mask: mask.index_array(mask_element_size, element_index),
+                                    insns,
+                                }
+                            },
+                        ),
+                    );
+                    start += element_bit_width;
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { fields } => {
+                let CompiledTypeLayoutBody::Bundle {
+                    fields: mask_fields,
+                } = mask_layout.body
+                else {
+                    unreachable!();
+                };
+                assert_eq!(fields.len(), mask_fields.len());
+                for (field, mask_field) in fields.into_iter().zip(mask_fields) {
+                    let field_index_range =
+                        TypeIndexRange::new(field.offset, field.ty.layout.len());
+                    let mask_field_index_range =
+                        TypeIndexRange::new(mask_field.offset, mask_field.ty.layout.len());
+                    self.compile_memory_port_rw_helper(
+                        memory,
+                        stride,
+                        start,
+                        field.ty,
+                        mask_field.ty,
+                        read.as_mut().map(
+                            |MemoryPortReadInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 insns,
+                             }| MemoryPortReadInsns {
+                                addr: *addr,
+                                en: *en,
+                                write_mode: *write_mode,
+                                data: data.slice(field_index_range),
+                                insns,
+                            },
+                        ),
+                        write.as_mut().map(
+                            |MemoryPortWriteInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 mask,
+                                 insns,
+                             }| {
+                                MemoryPortWriteInsns {
+                                    addr: *addr,
+                                    en: *en,
+                                    write_mode: *write_mode,
+                                    data: data.slice(field_index_range),
+                                    mask: mask.slice(mask_field_index_range),
+                                    insns,
+                                }
+                            },
+                        ),
+                    );
+                    start = start + field.ty.ty.bit_width();
+                }
+            }
+        }
+    }
+    fn compile_memory_port_rw(
+        &mut self,
+        memory: StatePartIndex<StatePartKindMemories>,
+        data_layout: CompiledTypeLayout<CanonicalType>,
+        mask_layout: CompiledTypeLayout<CanonicalType>,
+        mut read: Option<MemoryPortReadInsns<'_>>,
+        mut write: Option<MemoryPortWriteInsns<'_>>,
+    ) {
+        let read_else_label = read.as_mut().map(
+            |MemoryPortReadInsns {
+                 addr: _,
+                 en,
+                 write_mode,
+                 data: _,
+                 insns,
+             }| {
+                let else_label = self.insns.new_label();
+                insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: else_label.0,
+                        value: *en,
+                    }
+                    .into(),
+                );
+                if let Some(write_mode) = *write_mode {
+                    insns.push(
+                        Insn::BranchIfSmallNonZero {
+                            target: else_label.0,
+                            value: write_mode,
+                        }
+                        .into(),
+                    );
+                }
+                else_label
+            },
+        );
+        let write_end_label = write.as_mut().map(
+            |MemoryPortWriteInsns {
+                 addr: _,
+                 en,
+                 write_mode,
+                 data: _,
+                 mask: _,
+                 insns,
+             }| {
+                let end_label = self.insns.new_label();
+                insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: end_label.0,
+                        value: *en,
+                    }
+                    .into(),
+                );
+                if let Some(write_mode) = *write_mode {
+                    insns.push(
+                        Insn::BranchIfSmallZero {
+                            target: end_label.0,
+                            value: write_mode,
+                        }
+                        .into(),
+                    );
+                }
+                end_label
+            },
+        );
+        self.compile_memory_port_rw_helper(
+            memory,
+            data_layout.ty.bit_width(),
+            0,
+            data_layout,
+            mask_layout,
+            read.as_mut().map(
+                |MemoryPortReadInsns {
+                     addr,
+                     en,
+                     write_mode,
+                     data,
+                     insns,
+                 }| MemoryPortReadInsns {
+                    addr: *addr,
+                    en: *en,
+                    write_mode: *write_mode,
+                    data: *data,
+                    insns: *insns,
+                },
+            ),
+            write.as_mut().map(
+                |MemoryPortWriteInsns {
+                     addr,
+                     en,
+                     write_mode,
+                     data,
+                     mask,
+                     insns,
+                 }| MemoryPortWriteInsns {
+                    addr: *addr,
+                    en: *en,
+                    write_mode: *write_mode,
+                    data: *data,
+                    mask: *mask,
+                    insns: *insns,
+                },
+            ),
+        );
+        if let (
+            Some(else_label),
+            Some(MemoryPortReadInsns {
+                addr: _,
+                en: _,
+                write_mode: _,
+                data,
+                insns,
+            }),
+        ) = (read_else_label, read)
+        {
+            let end_label = self.insns.new_label();
+            insns.push(
+                Insn::Branch {
+                    target: end_label.0,
+                }
+                .into(),
+            );
+            insns.push(else_label.into());
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = data;
+            for dest in small_slots.iter() {
+                insns.push(Insn::ConstSmall { dest, value: 0 }.into());
+            }
+            for dest in big_slots.iter() {
+                insns.push(
+                    Insn::Const {
+                        dest,
+                        value: BigInt::ZERO.intern_sized(),
+                    }
+                    .into(),
+                );
+            }
+            insns.push(end_label.into());
+        }
+        if let (Some(end_label), Some(write)) = (write_end_label, write) {
+            write.insns.push(end_label.into());
+        }
+    }
+    fn compile_memory(
+        &mut self,
+        mem: Mem,
+        instantiated_module: InstantiatedModule,
+        conditions: Interned<[Cond]>,
+        trace_decls: &mut Vec<TraceDecl>,
+    ) {
+        let data_layout = CompiledTypeLayout::get(mem.array_type().element());
+        let mask_layout = CompiledTypeLayout::get(mem.array_type().element().mask_type());
+        let read_latency_plus_1 = mem
+            .read_latency()
+            .checked_add(1)
+            .expect("read latency too big");
+        let write_latency_plus_1 = mem
+            .write_latency()
+            .get()
+            .checked_add(1)
+            .expect("write latency too big");
+        let read_cycle = match mem.read_under_write() {
+            ReadUnderWrite::Old => 0,
+            ReadUnderWrite::New => mem.read_latency(),
+            ReadUnderWrite::Undefined => mem.read_latency() / 2, // something other than Old or New
+        };
+        let memory = self
+            .insns
+            .state_layout
+            .memories
+            .allocate(&StatePartLayout::scalar(
+                (),
+                MemoryData {
+                    array_type: mem.array_type(),
+                    data: mem.initial_value().unwrap_or_else(|| {
+                        Intern::intern_owned(BitVec::repeat(
+                            false,
+                            mem.array_type().type_properties().bit_width,
+                        ))
+                    }),
+                },
+            ))
+            .start;
+        let (ports, trace_ports) = mem
+            .ports()
+            .iter()
+            .map(|&port| {
+                let target_base = TargetBase::MemPort(port);
+                let target = TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: target_base.into(),
+                };
+                self.decl_conditions.insert(target, conditions);
+                let TraceDecl::Scope(TraceScope::MemPort(trace_port)) =
+                    self.make_trace_decl(instantiated_module, target_base)
+                else {
+                    unreachable!();
+                };
+                let clk = Expr::field(port.to_expr(), "clk");
+                let clk = self.compile_expr(instantiated_module, clk);
+                let clk = self.compiled_expr_to_value(clk, mem.source_location());
+                let clk_triggered = self
+                    .compile_clock(clk.map_ty(Clock::from_canonical), mem.source_location())
+                    .clk_triggered;
+                let en = Expr::field(port.to_expr(), "en");
+                let en = self.compile_expr(instantiated_module, en);
+                let en = self.compiled_expr_to_value(en, mem.source_location());
+                let en = self.compiled_value_bool_dest_is_small(en, mem.source_location());
+                let addr = Expr::field(port.to_expr(), "addr");
+                let addr = self.compile_expr(instantiated_module, addr);
+                let addr = self.compiled_expr_to_value(addr, mem.source_location());
+                let addr_ty = addr.layout.ty;
+                let addr = self.compiled_value_to_dyn_array_index(
+                    addr.map_ty(UInt::from_canonical),
+                    mem.source_location(),
+                );
+                let read_data = port.port_kind().rdata_name().map(|name| {
+                    let read_data =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let read_data = self.compiled_expr_to_value(read_data, mem.source_location());
+                    read_data.range
+                });
+                let write_data = port.port_kind().wdata_name().map(|name| {
+                    let write_data =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_data = self.compiled_expr_to_value(write_data, mem.source_location());
+                    write_data.range
+                });
+                let write_mask = port.port_kind().wmask_name().map(|name| {
+                    let write_mask =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_mask = self.compiled_expr_to_value(write_mask, mem.source_location());
+                    write_mask.range
+                });
+                let write_mode = port.port_kind().wmode_name().map(|name| {
+                    let write_mode =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_mode = self.compiled_expr_to_value(write_mode, mem.source_location());
+                    self.compiled_value_bool_dest_is_small(write_mode, mem.source_location())
+                });
+                struct PortParts {
+                    en_delayed_len: usize,
+                    addr_delayed_len: usize,
+                    read_data_delayed_len: usize,
+                    write_data_delayed_len: usize,
+                    write_mask_delayed_len: usize,
+                    write_mode_delayed_len: usize,
+                    read_cycle: Option<usize>,
+                    write_cycle: Option<usize>,
+                }
+                let PortParts {
+                    en_delayed_len,
+                    addr_delayed_len,
+                    read_data_delayed_len,
+                    write_data_delayed_len,
+                    write_mask_delayed_len,
+                    write_mode_delayed_len,
+                    read_cycle,
+                    write_cycle,
+                } = match port.port_kind() {
+                    PortKind::ReadOnly => PortParts {
+                        en_delayed_len: read_cycle + 1,
+                        addr_delayed_len: read_cycle + 1,
+                        read_data_delayed_len: read_latency_plus_1 - read_cycle,
+                        write_data_delayed_len: 0,
+                        write_mask_delayed_len: 0,
+                        write_mode_delayed_len: 0,
+                        read_cycle: Some(read_cycle),
+                        write_cycle: None,
+                    },
+                    PortKind::WriteOnly => PortParts {
+                        en_delayed_len: write_latency_plus_1,
+                        addr_delayed_len: write_latency_plus_1,
+                        read_data_delayed_len: 0,
+                        write_data_delayed_len: write_latency_plus_1,
+                        write_mask_delayed_len: write_latency_plus_1,
+                        write_mode_delayed_len: 0,
+                        read_cycle: None,
+                        write_cycle: Some(mem.write_latency().get()),
+                    },
+                    PortKind::ReadWrite => {
+                        let can_rw_at_end = match mem.read_under_write() {
+                            ReadUnderWrite::Old => false,
+                            ReadUnderWrite::New | ReadUnderWrite::Undefined => true,
+                        };
+                        let latency_plus_1 = read_latency_plus_1;
+                        if latency_plus_1 != write_latency_plus_1 || !can_rw_at_end {
+                            todo!(
+                                "not sure what to do, issue: \
+                                https://github.com/chipsalliance/firrtl-spec/issues/263"
+                            );
+                        }
+                        PortParts {
+                            en_delayed_len: latency_plus_1,
+                            addr_delayed_len: latency_plus_1,
+                            read_data_delayed_len: 1,
+                            write_data_delayed_len: latency_plus_1,
+                            write_mask_delayed_len: latency_plus_1,
+                            write_mode_delayed_len: latency_plus_1,
+                            read_cycle: Some(latency_plus_1 - 1),
+                            write_cycle: Some(latency_plus_1 - 1),
+                        }
+                    }
+                };
+                let addr_delayed = self.allocate_delay_chain_small(
+                    addr_delayed_len,
+                    addr_ty.canonical(),
+                    Some(addr),
+                    None,
+                );
+                let en_delayed = self.allocate_delay_chain_small(
+                    en_delayed_len,
+                    Bool.canonical(),
+                    Some(en),
+                    None,
+                );
+                let read_data_delayed = self.allocate_delay_chain(
+                    read_data_delayed_len,
+                    &data_layout.layout,
+                    None,
+                    read_data,
+                    |v| v,
+                );
+                let write_data_delayed = self.allocate_delay_chain(
+                    write_data_delayed_len,
+                    &data_layout.layout,
+                    write_data,
+                    None,
+                    |v| v,
+                );
+                let write_mask_delayed = self.allocate_delay_chain(
+                    write_mask_delayed_len,
+                    &mask_layout.layout,
+                    write_mask,
+                    None,
+                    |v| v,
+                );
+                let write_mode_delayed = self.allocate_delay_chain_small(
+                    write_mode_delayed_len,
+                    Bool.canonical(),
+                    write_mode,
+                    None,
+                );
+                let mut read_insns = Vec::new();
+                let mut write_insns = Vec::new();
+                self.compile_memory_port_rw(
+                    memory,
+                    data_layout,
+                    mask_layout,
+                    read_cycle.map(|read_cycle| MemoryPortReadInsns {
+                        addr: addr_delayed[read_cycle],
+                        en: en_delayed[read_cycle],
+                        write_mode: write_mode_delayed.get(read_cycle).copied(),
+                        data: read_data_delayed[0],
+                        insns: &mut read_insns,
+                    }),
+                    write_cycle.map(|write_cycle| MemoryPortWriteInsns {
+                        addr: addr_delayed[write_cycle],
+                        en: en_delayed[write_cycle],
+                        write_mode: write_mode_delayed.get(write_cycle).copied(),
+                        data: write_data_delayed[write_cycle],
+                        mask: write_mask_delayed[write_cycle],
+                        insns: &mut write_insns,
+                    }),
+                );
+                self.add_assignment(Interned::default(), read_insns, mem.source_location());
+                (
+                    MemoryPort {
+                        clk_triggered,
+                        addr_delayed,
+                        en_delayed,
+                        data_layout,
+                        read_data_delayed,
+                        write_data_delayed,
+                        write_mask_delayed,
+                        write_mode_delayed,
+                        write_insns,
+                    },
+                    trace_port,
+                )
+            })
+            .unzip();
+        let name = mem.scoped_name().1 .0;
+        let id = TraceMemoryId(self.memories.len());
+        let stride = mem.array_type().element().bit_width();
+        let trace = TraceMem {
+            id,
+            name,
+            stride,
+            element_type: self
+                .make_trace_decl_child(
+                    instantiated_module,
+                    MakeTraceDeclTarget::Memory {
+                        id,
+                        depth: mem.array_type().len(),
+                        stride,
+                        start: 0,
+                        ty: mem.array_type().element(),
+                    },
+                    name,
+                    mem.source_location(),
+                )
+                .intern_sized(),
+            ports: Intern::intern_owned(trace_ports),
+            array_type: mem.array_type(),
+        };
+        trace_decls.push(trace.into());
+        self.memories.push(Memory {
+            mem,
+            memory,
+            trace,
+            ports,
+        });
+    }
+    fn compile_block(
+        &mut self,
+        parent_module: Interned<InstantiatedModule>,
+        block: Block,
+        conditions: Interned<[Cond]>,
+        trace_decls: &mut Vec<TraceDecl>,
+    ) {
+        let Block { memories, stmts } = block;
+        for memory in memories {
+            self.compile_memory(memory, *parent_module, conditions, trace_decls);
+        }
+        for stmt in stmts {
+            match stmt {
+                Stmt::Connect(StmtConnect {
+                    lhs,
+                    rhs,
+                    source_location,
+                }) => self.compile_connect(
+                    *parent_module,
+                    conditions,
+                    lhs,
+                    *parent_module,
+                    conditions,
+                    rhs,
+                    source_location,
+                ),
+                Stmt::Formal(StmtFormal { .. }) => todo!("implement simulating formal statements"),
+                Stmt::If(StmtIf {
+                    cond,
+                    source_location,
+                    blocks: [then_block, else_block],
+                }) => {
+                    let cond = self.compile_expr(*parent_module, Expr::canonical(cond));
+                    let cond = self.compiled_expr_to_value(cond, source_location);
+                    let cond = cond.map_ty(Bool::from_canonical);
+                    self.compile_block(
+                        parent_module,
+                        then_block,
+                        Interned::from_iter(conditions.iter().copied().chain([Cond {
+                            body: CondBody::IfTrue { cond },
+                            source_location,
+                        }])),
+                        trace_decls,
+                    );
+                    self.compile_block(
+                        parent_module,
+                        else_block,
+                        Interned::from_iter(conditions.iter().copied().chain([Cond {
+                            body: CondBody::IfFalse { cond },
+                            source_location,
+                        }])),
+                        trace_decls,
+                    );
+                }
+                Stmt::Match(StmtMatch {
+                    expr,
+                    source_location,
+                    blocks,
+                }) => {
+                    let enum_expr = self.compile_expr(*parent_module, Expr::canonical(expr));
+                    let enum_expr = self.compiled_expr_to_value(enum_expr, source_location);
+                    let enum_expr = enum_expr.map_ty(Enum::from_canonical);
+                    let discriminant = self.compile_enum_discriminant(enum_expr, source_location);
+                    for (variant_index, block) in blocks.into_iter().enumerate() {
+                        self.compile_block(
+                            parent_module,
+                            block,
+                            Interned::from_iter(conditions.iter().copied().chain([Cond {
+                                body: CondBody::MatchArm {
+                                    discriminant,
+                                    variant_index,
+                                },
+                                source_location,
+                            }])),
+                            trace_decls,
+                        );
+                    }
+                }
+                Stmt::Declaration(declaration) => {
+                    trace_decls.push(self.compile_declaration(
+                        declaration,
+                        parent_module,
+                        conditions,
+                    ));
+                }
+            }
+        }
+    }
+    fn compile_module(&mut self, module: Interned<InstantiatedModule>) -> &CompiledModule {
+        let mut trace_decls = Vec::new();
+        let module_io = module
+            .leaf_module()
+            .module_io()
+            .iter()
+            .map(
+                |&AnnotatedModuleIO {
+                     annotations: _,
+                     module_io,
+                 }| {
+                    let target = TargetInInstantiatedModule {
+                        instantiated_module: *module,
+                        target: Target::from(module_io),
+                    };
+                    self.decl_conditions.insert(target, Interned::default());
+                    trace_decls.push(self.make_trace_decl(*module, module_io.into()));
+                    self.compile_value(target)
+                },
+            )
+            .collect();
+        match module.leaf_module().body() {
+            ModuleBody::Normal(NormalModuleBody { body }) => {
+                self.compile_block(module, body, Interned::default(), &mut trace_decls);
+            }
+            ModuleBody::Extern(ExternModuleBody {
+                verilog_name: _,
+                parameters: _,
+                simulation,
+            }) => {
+                let Some(simulation) = simulation else {
+                    panic!(
+                        "can't simulate extern module without extern_module_simulation: {}",
+                        module.leaf_module().source_location()
+                    );
+                };
+                self.extern_modules.push(CompiledExternModule {
+                    module_io_targets: module
+                        .leaf_module()
+                        .module_io()
+                        .iter()
+                        .map(|v| Target::from(v.module_io))
+                        .collect(),
+                    module_io,
+                    simulation,
+                });
+            }
+        }
+        let hashbrown::hash_map::Entry::Vacant(entry) = self.modules.entry(*module) else {
+            unreachable!("compiled same instantiated module twice");
+        };
+        entry.insert(CompiledModule {
+            module_io,
+            trace_decls: TraceModule {
+                name: module.leaf_module().name(),
+                children: Intern::intern_owned(trace_decls),
+            },
+        })
+    }
+    fn process_assignments(&mut self) {
+        self.assignments
+            .finalize(self.insns.state_layout().ty.clone().into());
+        if let Some(DebugOpaque(dump_assignments_dot)) = &self.dump_assignments_dot {
+            let graph =
+                petgraph::graph::DiGraph::<_, _, usize>::from_elements(self.assignments.elements());
+            dump_assignments_dot(&petgraph::dot::Dot::new(&graph));
+        }
+        let assignments_order: Vec<_> = match petgraph::algo::toposort(&self.assignments, None) {
+            Ok(nodes) => nodes
+                .into_iter()
+                .filter_map(|n| match n {
+                    AssignmentOrSlotIndex::AssignmentIndex(v) => Some(v),
+                    _ => None,
+                })
+                .collect(),
+            Err(e) => match e.node_id() {
+                AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => panic!(
+                    "combinatorial logic cycle detected at: {}",
+                    self.assignments.assignments()[assignment_index].source_location,
+                ),
+                AssignmentOrSlotIndex::SmallSlot(slot) => panic!(
+                    "combinatorial logic cycle detected through: {}",
+                    self.insns.state_layout().ty.small_slots.debug_data[slot.as_usize()].name,
+                ),
+                AssignmentOrSlotIndex::BigSlot(slot) => panic!(
+                    "combinatorial logic cycle detected through: {}",
+                    self.insns.state_layout().ty.big_slots.debug_data[slot.as_usize()].name,
+                ),
+            },
+        };
+        struct CondStackEntry<'a> {
+            cond: &'a Cond,
+            end_label: Label,
+        }
+        let mut cond_stack = Vec::<CondStackEntry<'_>>::new();
+        for assignment_index in assignments_order {
+            let Assignment {
+                inputs: _,
+                outputs: _,
+                conditions,
+                insns,
+                source_location,
+            } = &self.assignments.assignments()[assignment_index];
+            let mut same_len = 0;
+            for (index, (entry, cond)) in cond_stack.iter().zip(conditions).enumerate() {
+                if entry.cond != cond {
+                    break;
+                }
+                same_len = index + 1;
+            }
+            while cond_stack.len() > same_len {
+                let CondStackEntry { cond: _, end_label } =
+                    cond_stack.pop().expect("just checked len");
+                self.insns.define_label_at_next_insn(end_label);
+            }
+            for cond in &conditions[cond_stack.len()..] {
+                let end_label = self.insns.new_label();
+                match cond.body {
+                    CondBody::IfTrue { cond: cond_value }
+                    | CondBody::IfFalse { cond: cond_value } => {
+                        let (branch_if_zero, branch_if_non_zero) = match cond_value.range.len() {
+                            TypeLen::A_SMALL_SLOT => (
+                                Insn::BranchIfSmallZero {
+                                    target: end_label.0,
+                                    value: cond_value.range.small_slots.start,
+                                },
+                                Insn::BranchIfSmallNonZero {
+                                    target: end_label.0,
+                                    value: cond_value.range.small_slots.start,
+                                },
+                            ),
+                            TypeLen::A_BIG_SLOT => (
+                                Insn::BranchIfZero {
+                                    target: end_label.0,
+                                    value: cond_value.range.big_slots.start,
+                                },
+                                Insn::BranchIfNonZero {
+                                    target: end_label.0,
+                                    value: cond_value.range.big_slots.start,
+                                },
+                            ),
+                            _ => unreachable!(),
+                        };
+                        self.insns.push(
+                            if let CondBody::IfTrue { .. } = cond.body {
+                                branch_if_zero
+                            } else {
+                                branch_if_non_zero
+                            },
+                            cond.source_location,
+                        );
+                    }
+                    CondBody::MatchArm {
+                        discriminant,
+                        variant_index,
+                    } => {
+                        self.insns.push(
+                            Insn::BranchIfSmallNeImmediate {
+                                target: end_label.0,
+                                lhs: discriminant,
+                                rhs: variant_index as _,
+                            },
+                            cond.source_location,
+                        );
+                    }
+                }
+                cond_stack.push(CondStackEntry { cond, end_label });
+            }
+            self.insns.extend(insns.iter().copied(), *source_location);
+        }
+        for CondStackEntry { cond: _, end_label } in cond_stack {
+            self.insns.define_label_at_next_insn(end_label);
+        }
+    }
+    fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
+        mem::take(&mut self.clock_triggers)
+            .into_iter()
+            .map(
+                |ClockTrigger {
+                     last_clk_was_low,
+                     clk,
+                     clk_triggered,
+                     source_location,
+                 }| {
+                    self.insns.push(
+                        Insn::XorSmallImmediate {
+                            dest: last_clk_was_low,
+                            lhs: clk,
+                            rhs: 1,
+                        },
+                        source_location,
+                    );
+                    clk_triggered
+                },
+            )
+            .collect()
+    }
+    fn process_registers(&mut self) {
+        for Register {
+            value,
+            clk_triggered,
+            reset,
+            source_location,
+        } in mem::take(&mut self.registers)
+        {
+            match reset {
+                Some(RegisterReset {
+                    is_async,
+                    init,
+                    rst,
+                }) => {
+                    let reg_end = self.insns.new_label();
+                    let reg_reset = self.insns.new_label();
+                    let branch_if_reset = Insn::BranchIfSmallNonZero {
+                        target: reg_reset.0,
+                        value: rst,
+                    };
+                    let branch_if_not_triggered = Insn::BranchIfSmallZero {
+                        target: reg_end.0,
+                        value: clk_triggered,
+                    };
+                    if is_async {
+                        self.insns.push(branch_if_reset, source_location);
+                        self.insns.push(branch_if_not_triggered, source_location);
+                    } else {
+                        self.insns.push(branch_if_not_triggered, source_location);
+                        self.insns.push(branch_if_reset, source_location);
+                    }
+                    self.insns.extend(
+                        value.range.insns_for_copy_from(value.write_value().range),
+                        source_location,
+                    );
+                    self.insns
+                        .push(Insn::Branch { target: reg_end.0 }, source_location);
+                    self.insns.define_label_at_next_insn(reg_reset);
+                    self.insns
+                        .extend(value.range.insns_for_copy_from(init.range), source_location);
+                    self.insns.define_label_at_next_insn(reg_end);
+                }
+                None => {
+                    let reg_end = self.insns.new_label();
+                    self.insns.push(
+                        Insn::BranchIfSmallZero {
+                            target: reg_end.0,
+                            value: clk_triggered,
+                        },
+                        source_location,
+                    );
+                    self.insns.extend(
+                        value.range.insns_for_copy_from(value.write_value().range),
+                        source_location,
+                    );
+                    self.insns.define_label_at_next_insn(reg_end);
+                }
+            }
+        }
+    }
+    fn process_memories(&mut self) {
+        for memory_index in 0..self.memories.len() {
+            let Memory {
+                mem,
+                memory: _,
+                trace: _,
+                ref mut ports,
+            } = self.memories[memory_index];
+            for MemoryPort {
+                clk_triggered,
+                addr_delayed,
+                en_delayed,
+                data_layout: _,
+                read_data_delayed,
+                write_data_delayed,
+                write_mask_delayed,
+                write_mode_delayed,
+                write_insns,
+            } in mem::take(ports)
+            {
+                let port_end = self.insns.new_label();
+                let small_shift_reg =
+                    |this: &mut Self, values: &[StatePartIndex<StatePartKindSmallSlots>]| {
+                        for pair in values.windows(2).rev() {
+                            this.insns.push(
+                                Insn::CopySmall {
+                                    dest: pair[1],
+                                    src: pair[0],
+                                },
+                                mem.source_location(),
+                            );
+                        }
+                    };
+                let shift_reg = |this: &mut Self, values: &[TypeIndexRange]| {
+                    for pair in values.windows(2).rev() {
+                        this.insns
+                            .extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location());
+                    }
+                };
+                self.insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: port_end.0,
+                        value: clk_triggered,
+                    },
+                    mem.source_location(),
+                );
+                small_shift_reg(self, &addr_delayed);
+                small_shift_reg(self, &en_delayed);
+                shift_reg(self, &write_data_delayed);
+                shift_reg(self, &write_mask_delayed);
+                small_shift_reg(self, &write_mode_delayed);
+                shift_reg(self, &read_data_delayed);
+                self.insns.extend(write_insns, mem.source_location());
+                self.insns.define_label_at_next_insn(port_end);
+            }
+        }
+    }
+    pub fn compile(mut self) -> Compiled<Bundle> {
+        let base_module =
+            *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
+        self.process_assignments();
+        self.process_registers();
+        self.process_memories();
+        let clocks_triggered = self.process_clocks();
+        self.insns
+            .push(Insn::Return, self.base_module.source_location());
+        Compiled {
+            insns: Insns::from(self.insns).intern_sized(),
+            base_module,
+            extern_modules: Intern::intern_owned(self.extern_modules),
+            io: Instance::new_unchecked(
+                ScopedNameId(
+                    NameId("<simulator>".intern(), Id::new()),
+                    self.original_base_module.name_id(),
+                ),
+                self.original_base_module,
+                self.original_base_module.source_location(),
+            ),
+            traces: SimTraces(Intern::intern_owned(self.traces.0)),
+            trace_memories: Interned::from_iter(self.memories.iter().map(
+                |&Memory {
+                     mem: _,
+                     memory,
+                     trace,
+                     ports: _,
+                 }| (memory, trace),
+            )),
+            clocks_triggered,
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct CompiledModule {
+    module_io: Interned<[CompiledValue<CanonicalType>]>,
+    trace_decls: TraceModule,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub struct Compiled<T: BundleType> {
+    insns: Interned<Insns<InsnsBuildingDone>>,
+    base_module: CompiledModule,
+    extern_modules: Interned<[CompiledExternModule]>,
+    io: Instance<T>,
+    traces: SimTraces<Interned<[SimTrace<SimTraceKind, ()>]>>,
+    trace_memories: Interned<[(StatePartIndex<StatePartKindMemories>, TraceMem)]>,
+    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
+}
+
+impl<T: BundleType> Compiled<T> {
+    pub fn new(module: Interned<Module<T>>) -> Self {
+        Self::from_canonical(Compiler::new(module.canonical().intern()).compile())
+    }
+    pub fn canonical(self) -> Compiled<Bundle> {
+        let Self {
+            insns,
+            base_module,
+            extern_modules,
+            io,
+            traces,
+            trace_memories,
+            clocks_triggered,
+        } = self;
+        Compiled {
+            insns,
+            base_module,
+            extern_modules,
+            io: Instance::from_canonical(io.canonical()),
+            traces,
+            trace_memories,
+            clocks_triggered,
+        }
+    }
+    pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
+        let Compiled {
+            insns,
+            base_module,
+            extern_modules,
+            io,
+            traces,
+            trace_memories,
+            clocks_triggered,
+        } = canonical;
+        Self {
+            insns,
+            base_module,
+            extern_modules,
+            io: Instance::from_canonical(io.canonical()),
+            traces,
+            trace_memories,
+            clocks_triggered,
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct TraceScalarId(usize);
+
+impl fmt::Debug for TraceScalarId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "TraceScalarId({})", self.0)
+    }
+}
+
+impl TraceScalarId {
+    pub fn as_usize(self) -> usize {
+        self.0
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct TraceMemoryId(usize);
+
+impl fmt::Debug for TraceMemoryId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "TraceMemoryId({})", self.0)
+    }
+}
+
+impl TraceMemoryId {
+    pub fn as_usize(self) -> usize {
+        self.0
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct TraceMemoryLocation {
+    pub id: TraceMemoryId,
+    pub depth: usize,
+    pub stride: usize,
+    pub start: usize,
+    pub len: usize,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub enum TraceLocation {
+    Scalar(TraceScalarId),
+    Memory(TraceMemoryLocation),
+}
+
+impl fmt::Debug for TraceLocation {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::Scalar(v) => v.fmt(f),
+            Self::Memory(v) => v.fmt(f),
+        }
+    }
+}
+
+macro_rules! impl_trace_decl {
+    (
+        $(
+            #[kind = $category_kind:ident]
+            $(#[$category_meta:meta])*
+            $category_variant:ident($category_enum:ident {
+                fn $category_property_fn:ident(self) -> $category_property_fn_ret_ty:ty;
+                $(
+                    $(#[$meta:meta])*
+                    $variant:ident($struct:ident {
+                        fn $property_fn:ident($property_fn_self:ident) -> _ $property_fn_block:block
+                        $($(#[$field_meta:meta])*
+                        $field_name:ident: $field_ty:ty,)*
+                    }),
+                )*
+            }),
+        )*
+    ) => {
+        $(
+            #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+            #[non_exhaustive]
+            $(#[$category_meta])*
+            pub enum $category_kind {
+                $($(#[$meta])*
+                $variant,)*
+            }
+
+            impl From<$category_kind> for TraceKind {
+                fn from(v: $category_kind) -> Self {
+                    TraceKind::$category_variant(v)
+                }
+            }
+
+            #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+            #[non_exhaustive]
+            $(#[$category_meta])*
+            pub enum $category_enum {
+                $($(#[$meta])*
+                $variant($struct),)*
+            }
+
+            impl fmt::Debug for $category_enum {
+                fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                    match *self {
+                        $(Self::$variant(v) => v.fmt(f),)*
+                    }
+                }
+            }
+
+            impl $category_enum {
+                pub fn kind(self) -> $category_kind {
+                    match self {
+                        $(Self::$variant(_) => $category_kind::$variant,)*
+                    }
+                }
+                pub fn name(self) -> Interned<str> {
+                    match self {
+                        $(Self::$variant(v) => v.name,)*
+                    }
+                }
+                pub fn $category_property_fn(self) -> $category_property_fn_ret_ty {
+                    match self {
+                        $(Self::$variant(v) => v.$property_fn(),)*
+                    }
+                }
+            }
+
+            impl From<$category_enum> for TraceDecl {
+                fn from(v: $category_enum) -> Self {
+                    TraceDecl::$category_variant(v)
+                }
+            }
+
+            $(
+                #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+                #[non_exhaustive]
+                $(#[$meta])*
+                pub struct $struct {
+                    $($(#[$field_meta])*
+                    pub $field_name: $field_ty,)*
+                }
+
+                impl $struct {
+                    pub fn $property_fn($property_fn_self) -> $category_property_fn_ret_ty $property_fn_block
+                }
+
+                impl From<$struct> for $category_enum {
+                    fn from(v: $struct) -> Self {
+                        $category_enum::$variant(v)
+                    }
+                }
+
+                impl From<$struct> for TraceDecl {
+                    fn from(v: $struct) -> Self {
+                        TraceDecl::$category_variant($category_enum::$variant(v))
+                    }
+                }
+            )*
+        )*
+
+        #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+        pub enum TraceKind {
+            $($(#[$category_meta])*
+            $category_variant($category_kind),)*
+        }
+
+        impl fmt::Debug for TraceKind {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                match *self {
+                    $(Self::$category_variant(v) => v.fmt(f),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+        pub enum TraceDecl {
+            $($(#[$category_meta])*
+            $category_variant($category_enum),)*
+        }
+
+        impl fmt::Debug for TraceDecl {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                match *self {
+                    $(Self::$category_variant(v) => v.fmt(f),)*
+                }
+            }
+        }
+    };
+}
+
+impl_trace_decl! {
+    #[kind = TraceScopeKind]
+    Scope(TraceScope {
+        fn children(self) -> Interned<[TraceDecl]>;
+        Module(TraceModule {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+        }),
+        Instance(TraceInstance {
+            fn children(self) -> _ {
+                [self.instance_io.into(), self.module.into()][..].intern()
+            }
+            name: Interned<str>,
+            instance_io: TraceBundle,
+            module: TraceModule,
+            ty: Bundle,
+        }),
+        Mem(TraceMem {
+            fn children(self) -> _ {
+                Interned::from_iter([*self.element_type].into_iter().chain(self.ports.iter().map(|&v| v.into())))
+            }
+            id: TraceMemoryId,
+            name: Interned<str>,
+            stride: usize,
+            element_type: Interned<TraceDecl>,
+            ports: Interned<[TraceMemPort]>,
+            array_type: Array,
+        }),
+        MemPort(TraceMemPort {
+            fn children(self) -> _ {
+                [self.bundle.into()][..].intern()
+            }
+            name: Interned<str>,
+            bundle: TraceBundle,
+            ty: Bundle,
+        }),
+        Wire(TraceWire {
+            fn children(self) -> _ {
+                [*self.child][..].intern()
+            }
+            name: Interned<str>,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
+        }),
+        Reg(TraceReg {
+            fn children(self) -> _ {
+                [*self.child][..].intern()
+            }
+            name: Interned<str>,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
+        }),
+        ModuleIO(TraceModuleIO {
+            fn children(self) -> _ {
+                [*self.child][..].intern()
+            }
+            name: Interned<str>,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
+            flow: Flow,
+        }),
+        Bundle(TraceBundle {
+            fn children(self) -> _ {
+                self.fields
+            }
+            name: Interned<str>,
+            fields: Interned<[TraceDecl]>,
+            ty: Bundle,
+            flow: Flow,
+        }),
+        Array(TraceArray {
+            fn children(self) -> _ {
+                self.elements
+            }
+            name: Interned<str>,
+            elements: Interned<[TraceDecl]>,
+            ty: Array,
+            flow: Flow,
+        }),
+        EnumWithFields(TraceEnumWithFields {
+            fn children(self) -> _ {
+                Interned::from_iter([self.discriminant.into()].into_iter().chain(self.non_empty_fields))
+            }
+            name: Interned<str>,
+            discriminant: TraceEnumDiscriminant,
+            non_empty_fields: Interned<[TraceDecl]>,
+            ty: Enum,
+            flow: Flow,
+        }),
+    }),
+    #[kind = TraceScalarKind]
+    Scalar(TraceScalar {
+        fn location(self) -> TraceLocation;
+        UInt(TraceUInt {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            ty: UInt,
+            flow: Flow,
+        }),
+        SInt(TraceSInt {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            ty: SInt,
+            flow: Flow,
+        }),
+        Bool(TraceBool {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            flow: Flow,
+        }),
+        FieldlessEnum(TraceFieldlessEnum {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            ty: Enum,
+            flow: Flow,
+        }),
+        EnumDiscriminant(TraceEnumDiscriminant {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            ty: Enum,
+            flow: Flow,
+        }),
+        Clock(TraceClock {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            flow: Flow,
+        }),
+        SyncReset(TraceSyncReset {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            flow: Flow,
+        }),
+        AsyncReset(TraceAsyncReset {
+            fn location(self) -> _ {
+                self.location
+            }
+            location: TraceLocation,
+            name: Interned<str>,
+            flow: Flow,
+        }),
+    }),
+}
+
+pub trait TraceWriterDecls: fmt::Debug + 'static + Sized {
+    type Error: std::error::Error + Send + Sync + 'static;
+    type TraceWriter: TraceWriter<Error = Self::Error>;
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error>;
+}
+
+trait TraceWriterDeclsDynTrait: fmt::Debug {
+    fn write_decls_dyn(
+        self: Box<Self>,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> std::io::Result<DynTraceWriter>;
+}
+
+fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::Error {
+    match <dyn std::error::Error + Send + Sync>::downcast::<std::io::Error>(Box::new(e)) {
+        Ok(retval) => *retval,
+        Err(e) => std::io::Error::other(e),
+    }
+}
+
+impl<T: TraceWriterDecls> TraceWriterDeclsDynTrait for T {
+    fn write_decls_dyn(
+        self: Box<Self>,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> std::io::Result<DynTraceWriter> {
+        Ok(DynTraceWriter(Box::new(
+            TraceWriterDecls::write_decls(
+                *self,
+                module,
+                trace_scalar_id_count,
+                trace_memory_id_count,
+            )
+            .map_err(err_into_io)?,
+        )))
+    }
+}
+
+pub trait TraceWriter: fmt::Debug + 'static {
+    type Error: std::error::Error + Send + Sync + 'static;
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        let _ = instant;
+        Ok(())
+    }
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+    fn close(self) -> Result<(), Self::Error>
+    where
+        Self: Sized,
+    {
+        Ok(())
+    }
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error>;
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
+    fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        if value {
+            self.set_signal_uint(id, bits![1])
+        } else {
+            self.set_signal_uint(id, bits![0])
+        }
+    }
+    fn set_signal_clock(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+    fn set_signal_sync_reset(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+    fn set_signal_async_reset(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error>;
+}
+
+pub struct DynTraceWriterDecls(Box<dyn TraceWriterDeclsDynTrait>);
+
+impl DynTraceWriterDecls {
+    pub fn new<W: TraceWriterDecls>(writer: W) -> Self {
+        Self(Box::new(writer))
+    }
+}
+
+impl fmt::Debug for DynTraceWriterDecls {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(f)
+    }
+}
+
+impl TraceWriterDecls for DynTraceWriterDecls {
+    type Error = std::io::Error;
+    type TraceWriter = DynTraceWriter;
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error> {
+        self.0
+            .write_decls_dyn(module, trace_scalar_id_count, trace_memory_id_count)
+    }
+}
+
+trait TraceWriterDynTrait: fmt::Debug + 'static {
+    fn finish_init_dyn(&mut self) -> std::io::Result<()>;
+    fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()>;
+    fn flush_dyn(&mut self) -> std::io::Result<()>;
+    fn close_dyn(self: Box<Self>) -> std::io::Result<()>;
+    fn set_memory_element_dyn(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> std::io::Result<()>;
+    fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
+    fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
+    fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_clock_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_sync_reset_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_async_reset_dyn(&mut self, id: TraceScalarId, value: bool)
+        -> std::io::Result<()>;
+    fn set_signal_enum_discriminant_dyn(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> std::io::Result<()>;
+}
+
+impl<T: TraceWriter> TraceWriterDynTrait for T {
+    fn finish_init_dyn(&mut self) -> std::io::Result<()> {
+        Ok(TraceWriter::finish_init(self).map_err(err_into_io)?)
+    }
+    fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()> {
+        Ok(TraceWriter::change_time_to(self, instant).map_err(err_into_io)?)
+    }
+    fn flush_dyn(&mut self) -> std::io::Result<()> {
+        Ok(TraceWriter::flush(self).map_err(err_into_io)?)
+    }
+    fn close_dyn(self: Box<Self>) -> std::io::Result<()> {
+        Ok(TraceWriter::close(*self).map_err(err_into_io)?)
+    }
+    fn set_memory_element_dyn(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> std::io::Result<()> {
+        Ok(
+            TraceWriter::set_memory_element(self, memory, element_index, element_data)
+                .map_err(err_into_io)?,
+        )
+    }
+    fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_uint(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_sint(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_bool(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_clock_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_clock(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_sync_reset_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_sync_reset(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_async_reset_dyn(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_async_reset(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_enum_discriminant_dyn(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> std::io::Result<()> {
+        Ok(
+            TraceWriter::set_signal_enum_discriminant(self, id, variant_index, ty)
+                .map_err(err_into_io)?,
+        )
+    }
+}
+
+pub struct DynTraceWriter(Box<dyn TraceWriterDynTrait>);
+
+impl fmt::Debug for DynTraceWriter {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(f)
+    }
+}
+
+impl TraceWriter for DynTraceWriter {
+    type Error = std::io::Error;
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        self.0.finish_init_dyn()
+    }
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.0.flush_dyn()
+    }
+    fn close(self) -> Result<(), Self::Error> {
+        self.0.close_dyn()
+    }
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error> {
+        self.0
+            .set_memory_element_dyn(memory, element_index, element_data)
+    }
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        self.0.change_time_to_dyn(instant)
+    }
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        self.0.set_signal_uint_dyn(id, value)
+    }
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        self.0.set_signal_sint_dyn(id, value)
+    }
+    fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_bool_dyn(id, value)
+    }
+    fn set_signal_clock(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_clock_dyn(id, value)
+    }
+    fn set_signal_sync_reset(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_sync_reset_dyn(id, value)
+    }
+    fn set_signal_async_reset(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> Result<(), Self::Error> {
+        self.0.set_signal_async_reset_dyn(id, value)
+    }
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error> {
+        self.0
+            .set_signal_enum_discriminant_dyn(id, variant_index, ty)
+    }
+}
+
+#[derive(Debug)]
+enum TraceWriterState<T: TraceWriterDecls> {
+    Decls(T),
+    Init(T::TraceWriter),
+    Running(T::TraceWriter),
+    Errored(Option<T::Error>),
+}
+
+trait SimTraceDebug<I> {
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result;
+}
+
+struct SimTraceDebugAsDebug<T, I>(T, I);
+
+impl<T: ?Sized, I: Copy> fmt::Debug for SimTraceDebugAsDebug<&'_ T, I>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(self.1, f)
+    }
+}
+
+impl<T, I> SimTraceDebug<I> for Vec<T>
+where
+    [T]: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        <[T]>::fmt(&**self, id, f)
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Interned<T>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        T::fmt(&**self, id, f)
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Box<T>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        T::fmt(&**self, id, f)
+    }
+}
+
+impl<T> SimTraceDebug<()> for [T]
+where
+    T: SimTraceDebug<TraceScalarId>,
+{
+    fn fmt(&self, _id: (), f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_list()
+            .entries(
+                self.iter()
+                    .enumerate()
+                    .map(|(id, v)| SimTraceDebugAsDebug(v, TraceScalarId(id))),
+            )
+            .finish()
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+struct SimTrace<K, S> {
+    kind: K,
+    state: S,
+    last_state: S,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+struct SimTraces<T>(T);
+
+impl<T> fmt::Debug for SimTraces<T>
+where
+    T: SimTraceDebug<()>,
+{
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt((), f)
+    }
+}
+
+impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, ()> {
+    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            kind,
+            state,
+            last_state,
+        } = self;
+        f.debug_struct("SimTrace")
+            .field("id", &id)
+            .field("kind", kind)
+            .field("state", state)
+            .field("last_state", last_state)
+            .finish()
+    }
+}
+
+impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, BitVec> {
+    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            kind,
+            state,
+            last_state,
+        } = self;
+        f.debug_struct("SimTrace")
+            .field("id", &id)
+            .field("kind", kind)
+            .field("state", &BitSliceWriteWithBase(state))
+            .field("last_state", &BitSliceWriteWithBase(last_state))
+            .finish()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum SimTraceKind {
+    BigUInt {
+        index: StatePartIndex<StatePartKindBigSlots>,
+        ty: UInt,
+    },
+    BigSInt {
+        index: StatePartIndex<StatePartKindBigSlots>,
+        ty: SInt,
+    },
+    BigBool {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigAsyncReset {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigSyncReset {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigClock {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallUInt {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: UInt,
+    },
+    SmallSInt {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: SInt,
+    },
+    SmallBool {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallAsyncReset {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallSyncReset {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallClock {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    EnumDiscriminant {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: Enum,
+    },
+}
+
+impl SimTraceKind {
+    fn make_state(self) -> BitVec {
+        match self {
+            SimTraceKind::BigUInt { index: _, ty } | SimTraceKind::SmallUInt { index: _, ty } => {
+                BitVec::repeat(false, ty.width)
+            }
+            SimTraceKind::BigSInt { index: _, ty } | SimTraceKind::SmallSInt { index: _, ty } => {
+                BitVec::repeat(false, ty.width)
+            }
+            SimTraceKind::BigBool { index: _ }
+            | SimTraceKind::BigAsyncReset { index: _ }
+            | SimTraceKind::BigSyncReset { index: _ }
+            | SimTraceKind::BigClock { index: _ }
+            | SimTraceKind::SmallBool { index: _ }
+            | SimTraceKind::SmallAsyncReset { index: _ }
+            | SimTraceKind::SmallSyncReset { index: _ }
+            | SimTraceKind::SmallClock { index: _ } => BitVec::repeat(false, 1),
+            SimTraceKind::EnumDiscriminant { index: _, ty } => {
+                BitVec::repeat(false, ty.discriminant_bit_width())
+            }
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum MaybeNeedsSettle<S, N = S> {
+    NeedsSettle(S),
+    NoSettleNeeded(N),
+}
+
+impl<T> MaybeNeedsSettle<T> {
+    fn map<U>(self, f: impl FnOnce(T) -> U) -> MaybeNeedsSettle<U> {
+        match self {
+            MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(f(v)),
+            MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)),
+        }
+    }
+}
+
+// workaround implementing FnOnce not being stable
+trait MaybeNeedsSettleFn<A> {
+    type Output;
+
+    fn call(self, arg: A) -> Self::Output;
+}
+
+impl<T: FnOnce(A) -> O, A, O> MaybeNeedsSettleFn<A> for T {
+    type Output = O;
+
+    fn call(self, arg: A) -> Self::Output {
+        self(arg)
+    }
+}
+
+impl<S, N> MaybeNeedsSettle<S, N> {
+    fn apply_no_settle<T>(self, arg: T) -> MaybeNeedsSettle<S, N::Output>
+    where
+        N: MaybeNeedsSettleFn<T>,
+    {
+        match self {
+            MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(v),
+            MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(v.call(arg)),
+        }
+    }
+}
+
+struct SimulationModuleState {
+    base_targets: Vec<Target>,
+    uninitialized_ios: HashMap<Target, Vec<Target>>,
+    io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
+    did_initial_settle: bool,
+}
+
+impl fmt::Debug for SimulationModuleState {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            base_targets,
+            uninitialized_ios,
+            io_targets,
+            did_initial_settle,
+        } = self;
+        f.debug_struct("SimulationModuleState")
+            .field("base_targets", base_targets)
+            .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios))
+            .field("io_targets", &SortedSetDebug(io_targets))
+            .field("did_initial_settle", did_initial_settle)
+            .finish()
+    }
+}
+
+impl SimulationModuleState {
+    fn new(base_targets: impl IntoIterator<Item = (Target, CompiledValue<CanonicalType>)>) -> Self {
+        let mut retval = Self {
+            base_targets: Vec::new(),
+            uninitialized_ios: HashMap::default(),
+            io_targets: HashMap::default(),
+            did_initial_settle: false,
+        };
+        for (base_target, value) in base_targets {
+            retval.base_targets.push(base_target);
+            retval.parse_io(base_target, value);
+        }
+        retval
+    }
+    /// returns `true` if `target` or any sub-targets are uninitialized inputs
+    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) -> bool {
+        self.io_targets.insert(target, value);
+        match value.layout.body {
+            CompiledTypeLayoutBody::Scalar => match target.flow() {
+                Flow::Source => false,
+                Flow::Sink => {
+                    self.uninitialized_ios.insert(target, vec![]);
+                    true
+                }
+                Flow::Duplex => unreachable!(),
+            },
+            CompiledTypeLayoutBody::Array { .. } => {
+                let value = value.map_ty(Array::from_canonical);
+                let mut sub_targets = Vec::new();
+                for index in 0..value.layout.ty.len() {
+                    let sub_target = target.join(
+                        TargetPathElement::from(TargetPathArrayElement { index }).intern_sized(),
+                    );
+                    if self.parse_io(sub_target, value.element(index)) {
+                        sub_targets.push(sub_target);
+                    }
+                }
+                if sub_targets.is_empty() {
+                    false
+                } else {
+                    self.uninitialized_ios.insert(target, sub_targets);
+                    true
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { .. } => {
+                let value = value.map_ty(Bundle::from_canonical);
+                let mut sub_targets = Vec::new();
+                for BundleField { name, .. } in value.layout.ty.fields() {
+                    let sub_target = target.join(
+                        TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
+                    );
+                    if self.parse_io(sub_target, value.field_by_name(name)) {
+                        sub_targets.push(sub_target);
+                    }
+                }
+                if sub_targets.is_empty() {
+                    false
+                } else {
+                    self.uninitialized_ios.insert(target, sub_targets);
+                    true
+                }
+            }
+        }
+    }
+    fn mark_target_as_initialized(&mut self, mut target: Target) {
+        fn remove_target_and_children(
+            uninitialized_ios: &mut HashMap<Target, Vec<Target>>,
+            target: Target,
+        ) {
+            let Some(children) = uninitialized_ios.remove(&target) else {
+                return;
+            };
+            for child in children {
+                remove_target_and_children(uninitialized_ios, child);
+            }
+        }
+        remove_target_and_children(&mut self.uninitialized_ios, target);
+        while let Some(target_child) = target.child() {
+            let parent = target_child.parent();
+            for child in self
+                .uninitialized_ios
+                .get(&*parent)
+                .map(|v| &**v)
+                .unwrap_or(&[])
+            {
+                if self.uninitialized_ios.contains_key(child) {
+                    return;
+                }
+            }
+            target = *parent;
+            self.uninitialized_ios.remove(&target);
+        }
+    }
+    #[track_caller]
+    fn get_io(
+        &self,
+        mut target: Target,
+        which_module: WhichModule,
+    ) -> CompiledValue<CanonicalType> {
+        assert!(
+            target.canonical_ty().is_passive(),
+            "simulator read/write expression must have a passive type \
+            (recursively contains no fields with `#[hdl(flip)]`)"
+        );
+        if let Some(&retval) = self.io_targets.get(&target) {
+            return retval;
+        }
+        loop {
+            target = match target {
+                Target::Base(_) => break,
+                Target::Child(child) => {
+                    match *child.path_element() {
+                        TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {}
+                        TargetPathElement::DynArrayElement(_) => panic!(
+                            "simulator read/write expression must not have dynamic array indexes"
+                        ),
+                    }
+                    *child.parent()
+                }
+            };
+        }
+        match which_module {
+            WhichModule::Main => panic!(
+                "simulator read/write expression must be \
+                an array element/field of `Simulation::io()`"
+            ),
+            WhichModule::Extern { .. } => panic!(
+                "simulator read/write expression must be \
+                one of this module's inputs/outputs or an \
+                array element/field of one of this module's inputs/outputs"
+            ),
+        }
+    }
+    #[track_caller]
+    fn read_helper(
+        &self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<CompiledValue<CanonicalType>> {
+        let Some(target) = io.target() else {
+            match which_module {
+                WhichModule::Main => panic!(
+                    "can't read from an expression that's not a field/element of `Simulation::io()`"
+                ),
+                WhichModule::Extern { .. } => panic!(
+                    "can't read from an expression that's not based on one of this module's inputs/outputs"
+                ),
+            }
+        };
+        let compiled_value = self.get_io(*target, which_module);
+        match target.flow() {
+            Flow::Source => {
+                if !self.uninitialized_ios.is_empty() {
+                    match which_module {
+                        WhichModule::Main => {
+                            panic!("can't read from an output before initializing all inputs");
+                        }
+                        WhichModule::Extern { .. } => {
+                            panic!("can't read from an input before initializing all outputs");
+                        }
+                    }
+                }
+                MaybeNeedsSettle::NeedsSettle(compiled_value)
+            }
+            Flow::Sink => {
+                if self.uninitialized_ios.contains_key(&*target) {
+                    match which_module {
+                        WhichModule::Main => panic!("can't read from an uninitialized input"),
+                        WhichModule::Extern { .. } => {
+                            panic!("can't read from an uninitialized output");
+                        }
+                    }
+                }
+                MaybeNeedsSettle::NoSettleNeeded(compiled_value)
+            }
+            Flow::Duplex => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn write_helper(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> CompiledValue<CanonicalType> {
+        let Some(target) = io.target() else {
+            match which_module {
+                WhichModule::Main => panic!(
+                    "can't write to an expression that's not a field/element of `Simulation::io()`"
+                ),
+                WhichModule::Extern { .. } => panic!(
+                    "can't write to an expression that's not based on one of this module's outputs"
+                ),
+            }
+        };
+        let compiled_value = self.get_io(*target, which_module);
+        match target.flow() {
+            Flow::Source => match which_module {
+                WhichModule::Main => panic!("can't write to an output"),
+                WhichModule::Extern { .. } => panic!("can't write to an input"),
+            },
+            Flow::Sink => {}
+            Flow::Duplex => unreachable!(),
+        }
+        if !self.did_initial_settle {
+            self.mark_target_as_initialized(*target);
+        }
+        compiled_value
+    }
+}
+
+#[derive(Copy, Clone, Debug)]
+enum WaitTarget<ChangeKey, ChangeValue> {
+    Settle,
+    Instant(SimInstant),
+    Change { key: ChangeKey, value: ChangeValue },
+}
+
+#[derive(Clone)]
+struct EarliestWaitTargets {
+    settle: bool,
+    instant: Option<SimInstant>,
+    changes: HashMap<CompiledValue<CanonicalType>, SimValue<CanonicalType>>,
+}
+
+impl fmt::Debug for EarliestWaitTargets {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_set().entries(self.iter()).finish()
+    }
+}
+
+impl Default for EarliestWaitTargets {
+    fn default() -> Self {
+        Self {
+            settle: false,
+            instant: None,
+            changes: HashMap::default(),
+        }
+    }
+}
+
+impl EarliestWaitTargets {
+    fn settle() -> Self {
+        Self {
+            settle: true,
+            instant: None,
+            changes: HashMap::default(),
+        }
+    }
+    fn instant(instant: SimInstant) -> Self {
+        Self {
+            settle: false,
+            instant: Some(instant),
+            changes: HashMap::default(),
+        }
+    }
+    fn len(&self) -> usize {
+        self.settle as usize + self.instant.is_some() as usize + self.changes.len()
+    }
+    fn is_empty(&self) -> bool {
+        self.len() == 0
+    }
+    fn clear(&mut self) {
+        let Self {
+            settle,
+            instant,
+            changes,
+        } = self;
+        *settle = false;
+        *instant = None;
+        changes.clear();
+    }
+    fn insert<ChangeValue>(
+        &mut self,
+        value: impl std::borrow::Borrow<WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>,
+    ) where
+        ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>,
+    {
+        let value = value.borrow();
+        match value {
+            WaitTarget::Settle => self.settle = true,
+            WaitTarget::Instant(instant) => {
+                if self.instant.is_none_or(|v| v > *instant) {
+                    self.instant = Some(*instant);
+                }
+            }
+            WaitTarget::Change { key, value } => {
+                self.changes
+                    .entry(*key)
+                    .or_insert_with(|| value.borrow().clone());
+            }
+        }
+    }
+    fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) {
+        if self.instant.is_some_and(|v| v <= instant) {
+            self.settle = true;
+            self.instant = None;
+        }
+    }
+    fn iter<'a>(
+        &'a self,
+    ) -> impl Clone
+           + Iterator<Item = WaitTarget<CompiledValue<CanonicalType>, &'a SimValue<CanonicalType>>>
+           + 'a {
+        self.settle
+            .then_some(WaitTarget::Settle)
+            .into_iter()
+            .chain(self.instant.map(|instant| WaitTarget::Instant(instant)))
+            .chain(
+                self.changes
+                    .iter()
+                    .map(|(&key, value)| WaitTarget::Change { key, value }),
+            )
+    }
+}
+
+impl<ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>>
+    Extend<WaitTarget<CompiledValue<CanonicalType>, ChangeValue>> for EarliestWaitTargets
+{
+    fn extend<T: IntoIterator<Item = WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>>(
+        &mut self,
+        iter: T,
+    ) {
+        iter.into_iter().for_each(|v| self.insert(v))
+    }
+}
+
+impl<'a, ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>>
+    Extend<&'a WaitTarget<CompiledValue<CanonicalType>, ChangeValue>> for EarliestWaitTargets
+{
+    fn extend<T: IntoIterator<Item = &'a WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>>(
+        &mut self,
+        iter: T,
+    ) {
+        iter.into_iter().for_each(|v| self.insert(v))
+    }
+}
+
+impl<A> FromIterator<A> for EarliestWaitTargets
+where
+    Self: Extend<A>,
+{
+    fn from_iter<T: IntoIterator<Item = A>>(iter: T) -> Self {
+        let mut retval = Self::default();
+        retval.extend(iter);
+        retval
+    }
+}
+
+struct SimulationExternModuleState {
+    module_state: SimulationModuleState,
+    sim: ExternModuleSimulation,
+    running_generator: Option<Pin<Box<dyn Future<Output = ()> + 'static>>>,
+    wait_targets: EarliestWaitTargets,
+}
+
+impl fmt::Debug for SimulationExternModuleState {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            module_state,
+            sim,
+            running_generator,
+            wait_targets,
+        } = self;
+        f.debug_struct("SimulationExternModuleState")
+            .field("module_state", module_state)
+            .field("sim", sim)
+            .field(
+                "running_generator",
+                &running_generator.as_ref().map(|_| DebugAsDisplay("...")),
+            )
+            .field("wait_targets", wait_targets)
+            .finish()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum WhichModule {
+    Main,
+    Extern { module_index: usize },
+}
+
+struct ReadBitFn {
+    compiled_value: CompiledValue<CanonicalType>,
+}
+
+impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBitFn {
+    type Output = bool;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        match self.compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                state.small_slots[self.compiled_value.range.small_slots.start] != 0
+            }
+            TypeLen::A_BIG_SLOT => !state.big_slots[self.compiled_value.range.big_slots.start]
+                .clone()
+                .is_zero(),
+            _ => unreachable!(),
+        }
+    }
+}
+
+struct ReadBoolOrIntFn<I: BoolOrIntType> {
+    compiled_value: CompiledValue<CanonicalType>,
+    io: Expr<I>,
+}
+
+impl<I: BoolOrIntType> MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBoolOrIntFn<I> {
+    type Output = I::Value;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        let Self { compiled_value, io } = self;
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => Expr::ty(io)
+                .value_from_int_wrapping(state.small_slots[compiled_value.range.small_slots.start]),
+            TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping(
+                state.big_slots[compiled_value.range.big_slots.start].clone(),
+            ),
+            _ => unreachable!(),
+        }
+    }
+}
+
+struct ReadFn {
+    compiled_value: CompiledValue<CanonicalType>,
+    io: Expr<CanonicalType>,
+}
+
+impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn {
+    type Output = SimValue<CanonicalType>;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        let Self { compiled_value, io } = self;
+        SimulationImpl::read_no_settle_helper(
+            state,
+            io,
+            compiled_value,
+            UIntValue::new(Arc::new(BitVec::repeat(false, Expr::ty(io).bit_width()))),
+        )
+    }
+}
+
+struct GeneratorWaker;
+
+impl std::task::Wake for GeneratorWaker {
+    fn wake(self: Arc<Self>) {
+        panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation");
+    }
+}
+
+#[derive(Default)]
+struct ReadyToRunSet {
+    state_ready_to_run: bool,
+    extern_modules_ready_to_run: Vec<usize>,
+}
+
+impl ReadyToRunSet {
+    fn clear(&mut self) {
+        let Self {
+            state_ready_to_run,
+            extern_modules_ready_to_run,
+        } = self;
+        *state_ready_to_run = false;
+        extern_modules_ready_to_run.clear();
+    }
+}
+
+struct SimulationImpl {
+    state: interpreter::State,
+    io: Expr<Bundle>,
+    main_module: SimulationModuleState,
+    extern_modules: Box<[SimulationExternModuleState]>,
+    state_ready_to_run: bool,
+    trace_decls: TraceModule,
+    traces: SimTraces<Box<[SimTrace<SimTraceKind, BitVec>]>>,
+    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
+    trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
+    instant: SimInstant,
+    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
+    breakpoints: Option<BreakpointsSet>,
+    generator_waker: std::task::Waker,
+}
+
+impl fmt::Debug for SimulationImpl {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(None, f)
+    }
+}
+
+impl SimulationImpl {
+    fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            state,
+            io: self_io,
+            main_module,
+            extern_modules,
+            state_ready_to_run,
+            trace_decls,
+            traces,
+            trace_memories,
+            trace_writers,
+            instant,
+            clocks_triggered,
+            breakpoints: _,
+            generator_waker: _,
+        } = self;
+        f.debug_struct("Simulation")
+            .field("state", state)
+            .field("io", io.unwrap_or(self_io))
+            .field("main_module", main_module)
+            .field("extern_modules", extern_modules)
+            .field("state_ready_to_run", state_ready_to_run)
+            .field("trace_decls", trace_decls)
+            .field("traces", traces)
+            .field("trace_memories", trace_memories)
+            .field("trace_writers", trace_writers)
+            .field("instant", instant)
+            .field("clocks_triggered", clocks_triggered)
+            .finish_non_exhaustive()
+    }
+    fn new(compiled: Compiled<Bundle>) -> Self {
+        let io_target = Target::from(compiled.io);
+        let extern_modules = Box::from_iter(compiled.extern_modules.iter().map(
+            |&CompiledExternModule {
+                 module_io_targets,
+                 module_io,
+                 simulation,
+             }| {
+                SimulationExternModuleState {
+                    module_state: SimulationModuleState::new(
+                        module_io_targets
+                            .iter()
+                            .copied()
+                            .zip(module_io.iter().copied()),
+                    ),
+                    sim: simulation,
+                    running_generator: None,
+                    wait_targets: EarliestWaitTargets::settle(),
+                }
+            },
+        ));
+        Self {
+            state: State::new(compiled.insns),
+            io: compiled.io.to_expr(),
+            main_module: SimulationModuleState::new(
+                compiled
+                    .io
+                    .ty()
+                    .fields()
+                    .into_iter()
+                    .zip(compiled.base_module.module_io)
+                    .map(|(BundleField { name, .. }, value)| {
+                        (
+                            io_target.join(
+                                TargetPathElement::from(TargetPathBundleField { name })
+                                    .intern_sized(),
+                            ),
+                            value,
+                        )
+                    }),
+            ),
+            extern_modules,
+            state_ready_to_run: true,
+            trace_decls: compiled.base_module.trace_decls,
+            traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map(
+                |&SimTrace {
+                     kind,
+                     state: _,
+                     last_state: _,
+                 }| SimTrace {
+                    kind,
+                    state: kind.make_state(),
+                    last_state: kind.make_state(),
+                },
+            ))),
+            trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()),
+            trace_writers: vec![],
+            instant: SimInstant::START,
+            clocks_triggered: compiled.clocks_triggered,
+            breakpoints: None,
+            generator_waker: Arc::new(GeneratorWaker).into(),
+        }
+    }
+    fn write_traces<const ONLY_IF_CHANGED: bool>(
+        &mut self,
+        mut trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        let mut set_memory_element = |memory: StatePartIndex<StatePartKindMemories>,
+                                      trace_mem: &TraceMem,
+                                      element_index: usize| {
+            let start = trace_mem.stride * element_index;
+            let end = start + trace_mem.stride;
+            trace_writer.set_memory_element(
+                self.trace_memories[&memory].id,
+                element_index,
+                &self.state.memories[memory].data[start..end],
+            )
+        };
+        if ONLY_IF_CHANGED {
+            for &(memory, element_index) in &self.state.memory_write_log {
+                set_memory_element(memory, &self.trace_memories[&memory], element_index)?;
+            }
+        } else {
+            for (&memory, trace_mem) in &self.trace_memories {
+                for element_index in 0..trace_mem.array_type.len() {
+                    set_memory_element(memory, trace_mem, element_index)?;
+                }
+            }
+        }
+        for (
+            id,
+            &SimTrace {
+                kind,
+                ref state,
+                ref last_state,
+            },
+        ) in self.traces.0.iter().enumerate()
+        {
+            if ONLY_IF_CHANGED && state == last_state {
+                continue;
+            }
+            let id = TraceScalarId(id);
+            match kind {
+                SimTraceKind::BigUInt { .. } | SimTraceKind::SmallUInt { .. } => {
+                    trace_writer.set_signal_uint(id, state)?;
+                }
+                SimTraceKind::BigSInt { .. } | SimTraceKind::SmallSInt { .. } => {
+                    trace_writer.set_signal_sint(id, state)?;
+                }
+                SimTraceKind::BigBool { .. } | SimTraceKind::SmallBool { .. } => {
+                    trace_writer.set_signal_bool(id, state[0])?;
+                }
+                SimTraceKind::BigAsyncReset { .. } | SimTraceKind::SmallAsyncReset { .. } => {
+                    trace_writer.set_signal_async_reset(id, state[0])?;
+                }
+                SimTraceKind::BigSyncReset { .. } | SimTraceKind::SmallSyncReset { .. } => {
+                    trace_writer.set_signal_sync_reset(id, state[0])?;
+                }
+                SimTraceKind::BigClock { .. } | SimTraceKind::SmallClock { .. } => {
+                    trace_writer.set_signal_clock(id, state[0])?;
+                }
+                SimTraceKind::EnumDiscriminant { ty, .. } => {
+                    let mut variant_index = [0; mem::size_of::<usize>()];
+                    variant_index.view_bits_mut::<Lsb0>()[0..state.len()]
+                        .clone_from_bitslice(state);
+                    trace_writer.set_signal_enum_discriminant(
+                        id,
+                        usize::from_le_bytes(variant_index),
+                        ty,
+                    )?;
+                }
+            }
+        }
+        Ok(trace_writer)
+    }
+    fn init_trace_writer(
+        &mut self,
+        trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        let mut trace_writer = self.write_traces::<false>(trace_writer)?;
+        trace_writer.finish_init()?;
+        Ok(trace_writer)
+    }
+    fn update_trace_writer(
+        &mut self,
+        trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        self.write_traces::<true>(trace_writer)
+    }
+    #[inline(never)]
+    fn read_traces<const IS_INITIAL_STEP: bool>(&mut self) {
+        for &mut SimTrace {
+            kind,
+            ref mut state,
+            ref mut last_state,
+        } in &mut self.traces.0
+        {
+            if !IS_INITIAL_STEP {
+                mem::swap(state, last_state);
+            }
+            match kind {
+                SimTraceKind::BigUInt { index, ty: _ } | SimTraceKind::BigSInt { index, ty: _ } => {
+                    let bigint = &self.state.big_slots[index];
+                    let mut bytes = bigint.to_signed_bytes_le();
+                    bytes.resize(
+                        state.len().div_ceil(8),
+                        if bigint.is_negative() { 0xFF } else { 0 },
+                    );
+                    let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                    let bitslice = &bitslice[..state.len()];
+                    state.clone_from_bitslice(bitslice);
+                }
+                SimTraceKind::BigBool { index }
+                | SimTraceKind::BigAsyncReset { index }
+                | SimTraceKind::BigSyncReset { index }
+                | SimTraceKind::BigClock { index } => {
+                    state.set(0, !self.state.big_slots[index].is_zero());
+                }
+                SimTraceKind::SmallUInt { index, ty: _ }
+                | SimTraceKind::SmallSInt { index, ty: _ }
+                | SimTraceKind::EnumDiscriminant { index, ty: _ } => {
+                    let bytes = self.state.small_slots[index].to_le_bytes();
+                    let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                    let bitslice = &bitslice[..state.len()];
+                    state.clone_from_bitslice(bitslice);
+                }
+                SimTraceKind::SmallBool { index }
+                | SimTraceKind::SmallAsyncReset { index }
+                | SimTraceKind::SmallSyncReset { index }
+                | SimTraceKind::SmallClock { index } => {
+                    state.set(0, self.state.small_slots[index] != 0);
+                }
+            }
+            if IS_INITIAL_STEP {
+                last_state.copy_from_bitslice(state);
+            }
+        }
+    }
+    #[track_caller]
+    fn advance_time(this_ref: &Rc<RefCell<Self>>, duration: SimDuration) {
+        let run_target = this_ref.borrow().instant + duration;
+        Self::run_until(this_ref, run_target);
+    }
+    /// clears `targets`
+    #[must_use]
+    fn yield_wait<'a>(
+        this: Rc<RefCell<Self>>,
+        module_index: usize,
+        targets: &'a mut EarliestWaitTargets,
+    ) -> impl Future<Output = ()> + 'a {
+        struct MyGenerator<'a> {
+            sim: Rc<RefCell<SimulationImpl>>,
+            yielded_at_all: bool,
+            module_index: usize,
+            targets: &'a mut EarliestWaitTargets,
+        }
+        impl Future for MyGenerator<'_> {
+            type Output = ();
+
+            fn poll(
+                mut self: Pin<&mut Self>,
+                cx: &mut std::task::Context<'_>,
+            ) -> Poll<Self::Output> {
+                let this = &mut *self;
+                let mut sim = this.sim.borrow_mut();
+                let sim = &mut *sim;
+                assert!(cx.waker().will_wake(&sim.generator_waker), "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation");
+                this.targets.convert_earlier_instants_to_settle(sim.instant);
+                if this.targets.is_empty() {
+                    this.targets.settle = true;
+                }
+                if this.targets.settle {
+                    if this.yielded_at_all {
+                        this.targets.clear();
+                        return Poll::Ready(());
+                    }
+                }
+                sim.extern_modules[this.module_index]
+                    .wait_targets
+                    .extend(this.targets.iter());
+                this.targets.clear();
+                this.yielded_at_all = true;
+                Poll::Pending
+            }
+        }
+        MyGenerator {
+            sim: this,
+            yielded_at_all: false,
+            module_index,
+            targets,
+        }
+    }
+    async fn yield_advance_time_or_settle(
+        this: Rc<RefCell<Self>>,
+        module_index: usize,
+        duration: Option<SimDuration>,
+    ) {
+        let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| {
+            EarliestWaitTargets::instant(this.borrow().instant + duration)
+        });
+        Self::yield_wait(this, module_index, &mut targets).await;
+    }
+    fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option<SimInstant> {
+        let module = &self.extern_modules[module_index];
+        let mut retval = None;
+        for wait_target in module.wait_targets.iter() {
+            retval = match (wait_target, retval) {
+                (WaitTarget::Settle, _) => Some(self.instant),
+                (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant),
+                (WaitTarget::Instant(instant), None) => Some(instant),
+                (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)),
+                (WaitTarget::Change { key, value }, retval) => {
+                    if Self::value_changed(&mut self.state, key, SimValue::bits(value).bits()) {
+                        Some(self.instant)
+                    } else {
+                        retval
+                    }
+                }
+            };
+            if retval == Some(self.instant) {
+                break;
+            }
+        }
+        retval
+    }
+    fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option<SimInstant> {
+        ready_to_run_set.clear();
+        let mut retval = None;
+        if self.state_ready_to_run {
+            ready_to_run_set.state_ready_to_run = true;
+            retval = Some(self.instant);
+        }
+        for module_index in 0..self.extern_modules.len() {
+            let Some(instant) = self.is_extern_module_ready_to_run(module_index) else {
+                continue;
+            };
+            if let Some(retval) = &mut retval {
+                match instant.cmp(retval) {
+                    std::cmp::Ordering::Less => ready_to_run_set.clear(),
+                    std::cmp::Ordering::Equal => {}
+                    std::cmp::Ordering::Greater => continue,
+                }
+            } else {
+                retval = Some(instant);
+            }
+            ready_to_run_set
+                .extern_modules_ready_to_run
+                .push(module_index);
+        }
+        retval
+    }
+    fn set_instant_no_sim(&mut self, instant: SimInstant) {
+        self.instant = instant;
+        self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
+            match &mut trace_writer_state {
+                TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(),
+                TraceWriterState::Running(trace_writer) => {
+                    trace_writer.change_time_to(this.instant)?;
+                }
+                TraceWriterState::Errored(_) => {}
+            }
+            Ok(trace_writer_state)
+        });
+    }
+    #[must_use]
+    #[track_caller]
+    fn run_state_settle_cycle(&mut self) -> bool {
+        self.state_ready_to_run = false;
+        self.state.setup_call(0);
+        if self.breakpoints.is_some() {
+            loop {
+                match self
+                    .state
+                    .run(self.breakpoints.as_mut().expect("just checked"))
+                {
+                    RunResult::Break(break_action) => {
+                        println!(
+                            "hit breakpoint at:\n{:?}",
+                            self.state.debug_insn_at(self.state.pc),
+                        );
+                        match break_action {
+                            BreakAction::DumpStateAndContinue => {
+                                println!("{self:#?}");
+                            }
+                            BreakAction::Continue => {}
+                        }
+                    }
+                    RunResult::Return(()) => break,
+                }
+            }
+        } else {
+            let RunResult::Return(()) = self.state.run(());
+        }
+        if self
+            .clocks_triggered
+            .iter()
+            .any(|i| self.state.small_slots[*i] != 0)
+        {
+            self.state_ready_to_run = true;
+            true
+        } else {
+            false
+        }
+    }
+    #[track_caller]
+    fn run_extern_modules_cycle(
+        this_ref: &Rc<RefCell<Self>>,
+        generator_waker: &std::task::Waker,
+        extern_modules_ready_to_run: &[usize],
+    ) {
+        let mut this = this_ref.borrow_mut();
+        for module_index in extern_modules_ready_to_run.iter().copied() {
+            let extern_module = &mut this.extern_modules[module_index];
+            extern_module.wait_targets.clear();
+            let mut generator = if !extern_module.module_state.did_initial_settle {
+                let sim = extern_module.sim;
+                drop(this);
+                Box::into_pin(sim.run(ExternModuleSimulationState {
+                    sim_impl: this_ref.clone(),
+                    module_index,
+                    wait_for_changes_wait_targets: EarliestWaitTargets::default(),
+                }))
+            } else if let Some(generator) = extern_module.running_generator.take() {
+                drop(this);
+                generator
+            } else {
+                continue;
+            };
+            let generator = match generator
+                .as_mut()
+                .poll(&mut std::task::Context::from_waker(generator_waker))
+            {
+                Poll::Ready(()) => None,
+                Poll::Pending => Some(generator),
+            };
+            this = this_ref.borrow_mut();
+            this.extern_modules[module_index]
+                .module_state
+                .did_initial_settle = true;
+            if !this.extern_modules[module_index]
+                .module_state
+                .uninitialized_ios
+                .is_empty()
+            {
+                panic!(
+                    "extern module didn't initialize all outputs before \
+                    waiting, settling, or reading any inputs: {}",
+                    this.extern_modules[module_index].sim.source_location
+                );
+            }
+            this.extern_modules[module_index].running_generator = generator;
+        }
+    }
+    /// clears `targets`
+    #[track_caller]
+    fn run_until(this_ref: &Rc<RefCell<Self>>, run_target: SimInstant) {
+        let mut this = this_ref.borrow_mut();
+        let mut ready_to_run_set = ReadyToRunSet::default();
+        let generator_waker = this.generator_waker.clone();
+        assert!(
+            this.main_module.uninitialized_ios.is_empty(),
+            "didn't initialize all inputs",
+        );
+        let run_target = run_target.max(this.instant);
+        let mut settle_cycle = 0;
+        let mut run_extern_modules = true;
+        loop {
+            assert!(settle_cycle < 100000, "settle(): took too many steps");
+            settle_cycle += 1;
+            let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) {
+                Some(next_wait_target) if next_wait_target <= run_target => next_wait_target,
+                _ => break,
+            };
+            if next_wait_target > this.instant {
+                settle_cycle = 0;
+                this.set_instant_no_sim(next_wait_target);
+            }
+            if run_extern_modules {
+                drop(this);
+                Self::run_extern_modules_cycle(
+                    this_ref,
+                    &generator_waker,
+                    &ready_to_run_set.extern_modules_ready_to_run,
+                );
+                this = this_ref.borrow_mut();
+            }
+            if ready_to_run_set.state_ready_to_run {
+                if this.run_state_settle_cycle() {
+                    // wait for clocks to settle before running extern modules again
+                    run_extern_modules = false;
+                } else {
+                    run_extern_modules = true;
+                }
+            }
+            if this.main_module.did_initial_settle {
+                this.read_traces::<false>();
+            } else {
+                this.read_traces::<true>();
+            }
+            this.state.memory_write_log.sort_unstable();
+            this.state.memory_write_log.dedup();
+            this.main_module.did_initial_settle = true;
+            this.for_each_trace_writer_storing_error(|this, trace_writer_state| {
+                Ok(match trace_writer_state {
+                    TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
+                        this.init_trace_writer(trace_writer_decls.write_decls(
+                            this.trace_decls,
+                            this.traces.0.len(),
+                            this.trace_memories.len(),
+                        )?)?,
+                    ),
+                    TraceWriterState::Init(trace_writer) => {
+                        TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
+                    }
+                    TraceWriterState::Running(trace_writer) => {
+                        TraceWriterState::Running(this.update_trace_writer(trace_writer)?)
+                    }
+                    TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
+                })
+            });
+            this.state.memory_write_log.clear();
+        }
+        if run_target > this.instant {
+            this.set_instant_no_sim(run_target);
+        }
+    }
+    #[track_caller]
+    fn settle(this_ref: &Rc<RefCell<Self>>) {
+        let run_target = this_ref.borrow().instant;
+        Self::run_until(this_ref, run_target);
+    }
+    fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState {
+        match which_module {
+            WhichModule::Main => &self.main_module,
+            WhichModule::Extern { module_index } => &self.extern_modules[module_index].module_state,
+        }
+    }
+    fn get_module_mut(&mut self, which_module: WhichModule) -> &mut SimulationModuleState {
+        match which_module {
+            WhichModule::Main => &mut self.main_module,
+            WhichModule::Extern { module_index } => {
+                &mut self.extern_modules[module_index].module_state
+            }
+        }
+    }
+    #[track_caller]
+    fn read_bit(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<ReadBitFn, bool> {
+        self.get_module(which_module)
+            .read_helper(Expr::canonical(io), which_module)
+            .map(|compiled_value| ReadBitFn { compiled_value })
+            .apply_no_settle(&mut self.state)
+    }
+    #[track_caller]
+    fn write_bit(&mut self, io: Expr<CanonicalType>, value: bool, which_module: WhichModule) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(io, which_module);
+        self.state_ready_to_run = true;
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                self.state.small_slots[compiled_value.range.small_slots.start] = value as _;
+            }
+            TypeLen::A_BIG_SLOT => {
+                self.state.big_slots[compiled_value.range.big_slots.start] = value.into()
+            }
+            _ => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn read_bool_or_int<I: BoolOrIntType>(
+        &mut self,
+        io: Expr<I>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<ReadBoolOrIntFn<I>, I::Value> {
+        self.get_module(which_module)
+            .read_helper(Expr::canonical(io), which_module)
+            .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io })
+            .apply_no_settle(&mut self.state)
+    }
+    #[track_caller]
+    fn write_bool_or_int<I: BoolOrIntType>(
+        &mut self,
+        io: Expr<I>,
+        value: I::Value,
+        which_module: WhichModule,
+    ) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(Expr::canonical(io), which_module);
+        self.state_ready_to_run = true;
+        let value: BigInt = value.into();
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                let mut small_value = value.iter_u64_digits().next().unwrap_or(0);
+                if value.is_negative() {
+                    small_value = small_value.wrapping_neg();
+                }
+                self.state.small_slots[compiled_value.range.small_slots.start] = small_value;
+            }
+            TypeLen::A_BIG_SLOT => {
+                self.state.big_slots[compiled_value.range.big_slots.start] = value
+            }
+            _ => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn read_write_sim_value_helper<Bits: ?Sized>(
+        state: &mut interpreter::State,
+        compiled_value: CompiledValue<CanonicalType>,
+        start_bit_index: usize,
+        bits: &mut Bits,
+        read_write_big_scalar: impl Fn(bool, std::ops::Range<usize>, &mut Bits, &mut BigInt) + Copy,
+        read_write_small_scalar: impl Fn(bool, std::ops::Range<usize>, &mut Bits, &mut SmallUInt) + Copy,
+    ) {
+        match compiled_value.layout.body {
+            CompiledTypeLayoutBody::Scalar => {
+                let signed = match compiled_value.layout.ty {
+                    CanonicalType::UInt(_) => false,
+                    CanonicalType::SInt(_) => true,
+                    CanonicalType::Bool(_) => false,
+                    CanonicalType::Array(_) => unreachable!(),
+                    CanonicalType::Enum(_) => false,
+                    CanonicalType::Bundle(_) => unreachable!(),
+                    CanonicalType::AsyncReset(_) => false,
+                    CanonicalType::SyncReset(_) => false,
+                    CanonicalType::Reset(_) => false,
+                    CanonicalType::Clock(_) => false,
+                    CanonicalType::PhantomConst(_) => unreachable!(),
+                };
+                let bit_indexes =
+                    start_bit_index..start_bit_index + compiled_value.layout.ty.bit_width();
+                match compiled_value.range.len() {
+                    TypeLen::A_SMALL_SLOT => read_write_small_scalar(
+                        signed,
+                        bit_indexes,
+                        bits,
+                        &mut state.small_slots[compiled_value.range.small_slots.start],
+                    ),
+                    TypeLen::A_BIG_SLOT => read_write_big_scalar(
+                        signed,
+                        bit_indexes,
+                        bits,
+                        &mut state.big_slots[compiled_value.range.big_slots.start],
+                    ),
+                    _ => unreachable!(),
+                }
+            }
+            CompiledTypeLayoutBody::Array { element } => {
+                let ty = <Array>::from_canonical(compiled_value.layout.ty);
+                let element_bit_width = ty.element().bit_width();
+                for element_index in 0..ty.len() {
+                    Self::read_write_sim_value_helper(
+                        state,
+                        CompiledValue {
+                            layout: *element,
+                            range: compiled_value
+                                .range
+                                .index_array(element.layout.len(), element_index),
+                            write: None,
+                        },
+                        start_bit_index + element_index * element_bit_width,
+                        bits,
+                        read_write_big_scalar,
+                        read_write_small_scalar,
+                    );
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { fields } => {
+                let ty = Bundle::from_canonical(compiled_value.layout.ty);
+                for (
+                    (_field, offset),
+                    CompiledBundleField {
+                        offset: layout_offset,
+                        ty: field_layout,
+                    },
+                ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields)
+                {
+                    Self::read_write_sim_value_helper(
+                        state,
+                        CompiledValue {
+                            layout: field_layout,
+                            range: compiled_value.range.slice(TypeIndexRange::new(
+                                layout_offset,
+                                field_layout.layout.len(),
+                            )),
+                            write: None,
+                        },
+                        start_bit_index + offset,
+                        bits,
+                        read_write_big_scalar,
+                        read_write_small_scalar,
+                    );
+                }
+            }
+        }
+    }
+    #[track_caller]
+    fn read_no_settle_helper(
+        state: &mut interpreter::State,
+        io: Expr<CanonicalType>,
+        compiled_value: CompiledValue<CanonicalType>,
+        mut bits: UIntValue,
+    ) -> SimValue<CanonicalType> {
+        SimulationImpl::read_write_sim_value_helper(
+            state,
+            compiled_value,
+            0,
+            bits.bits_mut(),
+            |_signed, bit_range, bits, value| {
+                <UInt>::copy_bits_from_bigint_wrapping(value, &mut bits[bit_range]);
+            },
+            |_signed, bit_range, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                let bitslice = &bitslice[..bit_range.len()];
+                bits[bit_range].clone_from_bitslice(bitslice);
+            },
+        );
+        SimValue::from_bits(Expr::ty(io), bits)
+    }
+    /// doesn't modify `bits`
+    fn value_changed(
+        state: &mut interpreter::State,
+        compiled_value: CompiledValue<CanonicalType>,
+        mut bits: &BitSlice,
+    ) -> bool {
+        assert_eq!(bits.len(), compiled_value.layout.ty.bit_width());
+        let any_change = std::cell::Cell::new(false);
+        SimulationImpl::read_write_sim_value_helper(
+            state,
+            compiled_value,
+            0,
+            &mut bits,
+            |_signed, bit_range, bits, value| {
+                if !<UInt>::bits_equal_bigint_wrapping(value, &bits[bit_range]) {
+                    any_change.set(true);
+                }
+            },
+            |_signed, bit_range, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                let bitslice = &bitslice[..bit_range.len()];
+                if bits[bit_range] != *bitslice {
+                    any_change.set(true);
+                }
+            },
+        );
+        any_change.get()
+    }
+    #[track_caller]
+    fn read(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> (
+        CompiledValue<CanonicalType>,
+        MaybeNeedsSettle<ReadFn, SimValue<CanonicalType>>,
+    ) {
+        let compiled_value = self.get_module(which_module).read_helper(io, which_module);
+        let value = compiled_value
+            .map(|compiled_value| ReadFn { compiled_value, io })
+            .apply_no_settle(&mut self.state);
+        let (MaybeNeedsSettle::NeedsSettle(compiled_value)
+        | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value;
+        (compiled_value, value)
+    }
+    #[track_caller]
+    fn write(
+        &mut self,
+        io: Expr<CanonicalType>,
+        value: &SimValue<CanonicalType>,
+        which_module: WhichModule,
+    ) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(io, which_module);
+        self.state_ready_to_run = true;
+        assert_eq!(Expr::ty(io), SimValue::ty(value));
+        Self::read_write_sim_value_helper(
+            &mut self.state,
+            compiled_value,
+            0,
+            &mut value.bits().bits(),
+            |signed, bit_range, bits, value| {
+                if signed {
+                    *value = SInt::bits_to_bigint(&bits[bit_range]);
+                } else {
+                    *value = UInt::bits_to_bigint(&bits[bit_range]);
+                }
+            },
+            |signed, bit_range, bits, value| {
+                let mut small_value = [0; mem::size_of::<SmallUInt>()];
+                if signed && bits[bit_range.clone()].last().as_deref().copied() == Some(true) {
+                    small_value.fill(u8::MAX);
+                }
+                small_value.view_bits_mut::<Lsb0>()[0..bit_range.len()]
+                    .clone_from_bitslice(&bits[bit_range]);
+                *value = SmallUInt::from_le_bytes(small_value);
+            },
+        );
+    }
+    #[track_caller]
+    fn settle_if_needed<F, O>(this_ref: &Rc<RefCell<Self>>, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        match v {
+            MaybeNeedsSettle::NeedsSettle(v) => {
+                Self::settle(this_ref);
+                v.call(&mut this_ref.borrow_mut().state)
+            }
+            MaybeNeedsSettle::NoSettleNeeded(v) => v,
+        }
+    }
+    async fn yield_settle_if_needed<F, O>(
+        this_ref: &Rc<RefCell<Self>>,
+        module_index: usize,
+        v: MaybeNeedsSettle<F, O>,
+    ) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        match v {
+            MaybeNeedsSettle::NeedsSettle(v) => {
+                Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await;
+                v.call(&mut this_ref.borrow_mut().state)
+            }
+            MaybeNeedsSettle::NoSettleNeeded(v) => v,
+        }
+    }
+    fn close_all_trace_writers(&mut self) -> std::io::Result<()> {
+        let trace_writers = mem::take(&mut self.trace_writers);
+        let mut retval = Ok(());
+        let close_trace_writer =
+            |trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
+                TraceWriterState::Decls(v) => v
+                    .write_decls(
+                        self.trace_decls,
+                        self.traces.0.len(),
+                        self.trace_memories.len(),
+                    )?
+                    .close(),
+                TraceWriterState::Init(v) => v.close(),
+                TraceWriterState::Running(v) => v.close(),
+                TraceWriterState::Errored(Some(e)) => Err(e),
+                TraceWriterState::Errored(None) => Ok(()),
+            };
+        for trace_writer in trace_writers {
+            retval = retval.and(close_trace_writer(trace_writer));
+        }
+        retval
+    }
+    fn for_each_trace_writer_storing_error(
+        &mut self,
+        mut f: impl FnMut(
+            &mut Self,
+            TraceWriterState<DynTraceWriterDecls>,
+        ) -> std::io::Result<TraceWriterState<DynTraceWriterDecls>>,
+    ) {
+        let mut trace_writers = mem::take(&mut self.trace_writers);
+        for trace_writer in &mut trace_writers {
+            *trace_writer = match f(
+                self,
+                mem::replace(trace_writer, TraceWriterState::Errored(None)),
+            ) {
+                Ok(v) => v,
+                Err(e) => TraceWriterState::Errored(Some(e)),
+            };
+        }
+        self.trace_writers = trace_writers;
+    }
+    fn for_each_trace_writer_getting_error(
+        &mut self,
+        mut f: impl FnMut(
+            &mut Self,
+            TraceWriterState<DynTraceWriterDecls>,
+        ) -> std::io::Result<TraceWriterState<DynTraceWriterDecls>>,
+    ) -> std::io::Result<()> {
+        let mut retval = Ok(());
+        let mut trace_writers = mem::take(&mut self.trace_writers);
+        for trace_writer in &mut trace_writers {
+            *trace_writer = match f(
+                self,
+                mem::replace(trace_writer, TraceWriterState::Errored(None)),
+            ) {
+                Ok(v) => v,
+                Err(e) => {
+                    if retval.is_ok() {
+                        retval = Err(e);
+                        TraceWriterState::Errored(None)
+                    } else {
+                        TraceWriterState::Errored(Some(e))
+                    }
+                }
+            };
+        }
+        self.trace_writers = trace_writers;
+        retval
+    }
+    fn close(this: Rc<RefCell<Self>>) -> std::io::Result<()> {
+        if this.borrow().main_module.did_initial_settle {
+            Self::settle(&this);
+        }
+        this.borrow_mut().close_all_trace_writers()
+    }
+    fn flush_traces(this_ref: &Rc<RefCell<Self>>) -> std::io::Result<()> {
+        if this_ref.borrow().main_module.did_initial_settle {
+            Self::settle(this_ref);
+        }
+        this_ref.borrow_mut().for_each_trace_writer_getting_error(
+            |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
+                TraceWriterState::Decls(v) => {
+                    let mut v = v.write_decls(
+                        this.trace_decls,
+                        this.traces.0.len(),
+                        this.trace_memories.len(),
+                    )?;
+                    v.flush()?;
+                    Ok(TraceWriterState::Init(v))
+                }
+                TraceWriterState::Init(mut v) => {
+                    v.flush()?;
+                    Ok(TraceWriterState::Init(v))
+                }
+                TraceWriterState::Running(mut v) => {
+                    v.flush()?;
+                    Ok(TraceWriterState::Running(v))
+                }
+                TraceWriterState::Errored(Some(e)) => Err(e),
+                TraceWriterState::Errored(None) => Ok(TraceWriterState::Errored(None)),
+            },
+        )
+    }
+}
+
+impl Drop for SimulationImpl {
+    fn drop(&mut self) {
+        self.close_all_trace_writers()
+            .expect("error closing trace writers");
+    }
+}
+
+pub struct Simulation<T: BundleType> {
+    sim_impl: Rc<RefCell<SimulationImpl>>,
+    io: Expr<T>,
+}
+
+struct SortedSetDebug<'a, T, V>(&'a HashMap<T, V>);
+
+impl<T: fmt::Debug, V> fmt::Debug for SortedSetDebug<'_, T, V> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let mut entries = Vec::from_iter(self.0.iter().map(|(v, _)| {
+            if f.alternate() {
+                format!("{v:#?}")
+            } else {
+                format!("{v:?}")
+            }
+        }));
+        entries.sort();
+        f.debug_set()
+            .entries(entries.iter().map(DebugAsDisplay))
+            .finish()
+    }
+}
+
+struct SortedMapDebug<'a, K, V>(&'a HashMap<K, V>);
+
+impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| {
+            if f.alternate() {
+                (format!("{k:#?}"), format!("{v:#?}"))
+            } else {
+                (format!("{k:?}"), format!("{v:?}"))
+            }
+        }));
+        entries.sort();
+        f.debug_map()
+            .entries(
+                entries
+                    .iter()
+                    .map(|(k, v)| (DebugAsDisplay(k), DebugAsDisplay(v))),
+            )
+            .finish()
+    }
+}
+
+impl<T: BundleType> fmt::Debug for Simulation<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self { sim_impl, io } = self;
+        sim_impl.borrow().debug_fmt(Some(io), f)
+    }
+}
+
+macro_rules! impl_simulation_methods {
+    (
+        async_await = ($($async:tt, $await:tt)?),
+        track_caller = ($(#[$track_caller:tt])?),
+        which_module = |$self:ident| $which_module:expr,
+    ) => {
+        $(#[$track_caller])?
+        pub $($async)? fn read_bool_or_int<I: BoolOrIntType>(&mut $self, io: Expr<I>) -> I::Value {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bool_or_int(io, $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_bool_or_int<I: BoolOrIntType>(
+            &mut $self,
+            io: Expr<I>,
+            value: impl ToExpr<Type = I>,
+        ) {
+            let value = value.to_expr();
+            assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch");
+            let value = value
+                .to_literal_bits()
+                .expect("the value that is being written to an input must be a literal");
+            $self.sim_impl.borrow_mut().write_bool_or_int(
+                io,
+                I::bits_to_value(Cow::Borrowed(&value)),
+                $which_module,
+            );
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_clock(&mut $self, io: Expr<Clock>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_clock(&mut $self, io: Expr<Clock>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_bool(&mut $self, io: Expr<Bool>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_bool(&mut $self, io: Expr<Bool>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_reset<R: ResetType>(&mut $self, io: Expr<R>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_reset<R: ResetType>(&mut $self, io: Expr<R>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read<IO: Type>(&mut $self, io: Expr<IO>) -> SimValue<IO> {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read(Expr::canonical(io), $which_module).1;
+            SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?)
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write<IO: Type, V: value::ToSimValueWithType<IO>>(&mut $self, io: Expr<IO>, value: V) {
+            $self.sim_impl.borrow_mut().write(
+                Expr::canonical(io),
+                &SimValue::into_canonical(value.into_sim_value_with_type(Expr::ty(io))),
+                $which_module,
+            );
+        }
+    };
+}
+
+impl<T: BundleType> Simulation<T> {
+    pub fn new(module: Interned<Module<T>>) -> Self {
+        Self::from_compiled(Compiled::new(module))
+    }
+    pub fn add_trace_writer<W: TraceWriterDecls>(&mut self, writer: W) {
+        self.sim_impl
+            .borrow_mut()
+            .trace_writers
+            .push(TraceWriterState::Decls(DynTraceWriterDecls::new(writer)));
+    }
+    pub fn flush_traces(&mut self) -> std::io::Result<()> {
+        SimulationImpl::flush_traces(&self.sim_impl)
+    }
+    pub fn close(self) -> std::io::Result<()> {
+        SimulationImpl::close(self.sim_impl)
+    }
+    pub fn canonical(self) -> Simulation<Bundle> {
+        let Self { sim_impl, io } = self;
+        Simulation {
+            sim_impl,
+            io: Expr::as_bundle(io),
+        }
+    }
+    pub fn from_canonical(canonical: Simulation<Bundle>) -> Self {
+        let Simulation { sim_impl, io } = canonical;
+        Self {
+            sim_impl,
+            io: Expr::from_bundle(io),
+        }
+    }
+    pub fn io(&self) -> Expr<T> {
+        self.io.to_expr()
+    }
+    pub fn from_compiled(compiled: Compiled<T>) -> Self {
+        let sim_impl = SimulationImpl::new(compiled.canonical());
+        Self {
+            io: Expr::from_bundle(sim_impl.io),
+            sim_impl: Rc::new(RefCell::new(sim_impl)),
+        }
+    }
+    #[track_caller]
+    pub fn settle(&mut self) {
+        SimulationImpl::settle(&self.sim_impl);
+    }
+    #[track_caller]
+    pub fn advance_time(&mut self, duration: SimDuration) {
+        SimulationImpl::advance_time(&self.sim_impl, duration);
+    }
+    #[track_caller]
+    fn settle_if_needed<F, O>(&mut self, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        SimulationImpl::settle_if_needed(&self.sim_impl, v)
+    }
+    impl_simulation_methods!(
+        async_await = (),
+        track_caller = (#[track_caller]),
+        which_module = |self| WhichModule::Main,
+    );
+    #[doc(hidden)]
+    /// This is explicitly unstable and may be changed/removed at any time
+    pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
+        self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet {
+            last_was_break: false,
+            set: pcs,
+            trace,
+        });
+    }
+}
+
+pub struct ExternModuleSimulationState {
+    sim_impl: Rc<RefCell<SimulationImpl>>,
+    module_index: usize,
+    wait_for_changes_wait_targets: EarliestWaitTargets,
+}
+
+impl fmt::Debug for ExternModuleSimulationState {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            sim_impl: _,
+            module_index,
+            wait_for_changes_wait_targets: _,
+        } = self;
+        f.debug_struct("ExternModuleSimulationState")
+            .field("sim_impl", &DebugAsDisplay("..."))
+            .field("module_index", module_index)
+            .finish_non_exhaustive()
+    }
+}
+
+impl ExternModuleSimulationState {
+    pub async fn settle(&mut self) {
+        SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None)
+            .await
+    }
+    pub async fn advance_time(&mut self, duration: SimDuration) {
+        SimulationImpl::yield_advance_time_or_settle(
+            self.sim_impl.clone(),
+            self.module_index,
+            Some(duration),
+        )
+        .await
+    }
+    pub async fn wait_for_changes<I: IntoIterator<Item: ToExpr>>(
+        &mut self,
+        iter: I,
+        timeout: Option<SimDuration>,
+    ) {
+        self.wait_for_changes_wait_targets.clear();
+        let which_module = WhichModule::Extern {
+            module_index: self.module_index,
+        };
+        for io in iter {
+            let io = Expr::canonical(io.to_expr());
+            let (key, value) = self.sim_impl.borrow_mut().read(io, which_module);
+            let value = self.settle_if_needed(value).await;
+            self.wait_for_changes_wait_targets
+                .insert(WaitTarget::Change { key, value });
+        }
+        if let Some(timeout) = timeout {
+            self.wait_for_changes_wait_targets.instant =
+                Some(self.sim_impl.borrow().instant + timeout);
+        }
+        SimulationImpl::yield_wait(
+            self.sim_impl.clone(),
+            self.module_index,
+            &mut self.wait_for_changes_wait_targets,
+        )
+        .await;
+    }
+    pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr<Type = Clock>) {
+        let clk = clk.to_expr();
+        while self.read_clock(clk).await {
+            self.wait_for_changes([clk], None).await;
+        }
+        while !self.read_clock(clk).await {
+            self.wait_for_changes([clk], None).await;
+        }
+    }
+    async fn settle_if_needed<F, O>(&mut self, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await
+    }
+    impl_simulation_methods!(
+        async_await = (async, await),
+        track_caller = (),
+        which_module = |self| WhichModule::Extern { module_index: self.module_index },
+    );
+}
+
+pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug {
+    fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture<Output = ()> + 'a;
+}
+
+pub struct SimGeneratorFn<Args, Fut> {
+    pub args: Args,
+    pub f: fn(Args, ExternModuleSimulationState) -> Fut,
+}
+
+impl<Args: fmt::Debug, Fut> fmt::Debug for SimGeneratorFn<Args, Fut> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self { args, f: _ } = self;
+        f.debug_struct("SimGeneratorFn")
+            .field("args", args)
+            .field("f", &DebugAsDisplay("..."))
+            .finish()
+    }
+}
+
+impl<Args: Hash, Fut> Hash for SimGeneratorFn<Args, Fut> {
+    fn hash<H: std::hash::Hasher>(&self, state: &mut H) {
+        let Self { args, f } = self;
+        args.hash(state);
+        f.hash(state);
+    }
+}
+
+impl<Args: Eq, Fut> Eq for SimGeneratorFn<Args, Fut> {}
+
+impl<Args: PartialEq, Fut> PartialEq for SimGeneratorFn<Args, Fut> {
+    fn eq(&self, other: &Self) -> bool {
+        let Self { args, f } = self;
+        *args == other.args && *f == other.f
+    }
+}
+
+impl<Args: Clone, Fut> Clone for SimGeneratorFn<Args, Fut> {
+    fn clone(&self) -> Self {
+        Self {
+            args: self.args.clone(),
+            f: self.f,
+        }
+    }
+}
+
+impl<Args: Copy, Fut> Copy for SimGeneratorFn<Args, Fut> {}
+
+impl<
+        T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static,
+        Fut: IntoFuture<Output = ()> + 'static,
+    > ExternModuleSimGenerator for SimGeneratorFn<T, Fut>
+{
+    fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture<Output = ()> + 'a {
+        (self.f)(self.args.clone(), sim)
+    }
+}
+
+trait DynExternModuleSimGenerator: Any + Send + Sync + SupportsPtrEqWithTypeId + fmt::Debug {
+    fn dyn_run<'a>(&'a self, sim: ExternModuleSimulationState)
+        -> Box<dyn Future<Output = ()> + 'a>;
+}
+
+impl<T: ExternModuleSimGenerator> DynExternModuleSimGenerator for T {
+    fn dyn_run<'a>(
+        &'a self,
+        sim: ExternModuleSimulationState,
+    ) -> Box<dyn Future<Output = ()> + 'a> {
+        Box::new(self.run(sim).into_future())
+    }
+}
+
+impl InternedCompare for dyn DynExternModuleSimGenerator {
+    type InternedCompareKey = PtrEqWithTypeId;
+
+    fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
+        this.get_ptr_eq_with_type_id()
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+pub struct ExternModuleSimulation {
+    generator: Interned<dyn DynExternModuleSimGenerator>,
+    source_location: SourceLocation,
+}
+
+impl ExternModuleSimulation {
+    pub fn new_with_loc<G: ExternModuleSimGenerator>(
+        source_location: SourceLocation,
+        generator: G,
+    ) -> Self {
+        Self {
+            generator: Interned::cast_unchecked(
+                generator.intern(),
+                |v| -> &dyn DynExternModuleSimGenerator { v },
+            ),
+            source_location,
+        }
+    }
+    #[track_caller]
+    pub fn new<G: ExternModuleSimGenerator>(generator: G) -> Self {
+        Self::new_with_loc(SourceLocation::caller(), generator)
+    }
+    fn run(&self, sim: ExternModuleSimulationState) -> Box<dyn Future<Output = ()> + 'static> {
+        Interned::into_inner(self.generator).dyn_run(sim)
+    }
+}
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
new file mode 100644
index 0000000..de582f0
--- /dev/null
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -0,0 +1,3184 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    array::Array,
+    int::{BoolOrIntType, SInt, UInt},
+    intern::{Intern, Interned, Memoize},
+    source_location::SourceLocation,
+    ty::CanonicalType,
+    util::{get_many_mut, HashMap, HashSet},
+};
+use bitvec::{boxed::BitBox, slice::BitSlice};
+use num_bigint::BigInt;
+use num_traits::{One, Signed, ToPrimitive, Zero};
+use std::{
+    any::TypeId,
+    borrow::BorrowMut,
+    convert::Infallible,
+    fmt::{self, Write},
+    hash::{Hash, Hasher},
+    marker::PhantomData,
+    ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
+};
+use vec_map::VecMap;
+
+pub(crate) type SmallUInt = u64;
+pub(crate) type SmallSInt = i64;
+pub(crate) const MIN_BITS_FOR_NEEDING_BIG: usize = SmallUInt::BITS as usize + 1;
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) enum InsnFieldKind {
+    Input,
+    Output,
+    Memory,
+    Immediate,
+    BranchTarget,
+}
+
+pub(crate) trait InsnFieldTypeTransform: Eq + Hash + fmt::Debug + Send + Sync {
+    type Type<FieldType: InsnFieldTrait>: Eq + Hash + fmt::Debug + Send + Sync;
+    fn empty_type() -> Self::Type<[(); 0]>;
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnFieldTypeTransformUnit;
+
+impl InsnFieldTypeTransform for InsnFieldTypeTransformUnit {
+    type Type<FieldType: InsnFieldTrait> = ();
+    fn empty_type() -> Self::Type<[(); 0]> {
+        ()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformRef<'a>(PhantomData<&'a ()>);
+
+impl<'a> InsnFieldTypeTransform for InsnFieldTypeTransformRef<'a> {
+    type Type<FieldType: InsnFieldTrait> = &'a FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        &[]
+    }
+}
+
+#[derive(PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformRefMut<'a>(PhantomData<&'a mut ()>);
+
+impl<'a> InsnFieldTypeTransform for InsnFieldTypeTransformRefMut<'a> {
+    type Type<FieldType: InsnFieldTrait> = &'a mut FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        &mut []
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformValue;
+
+impl InsnFieldTypeTransform for InsnFieldTypeTransformValue {
+    type Type<FieldType: InsnFieldTrait> = FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        []
+    }
+}
+
+pub trait InsnFieldTrait: Send + Sync + 'static + Copy + Eq + Hash + fmt::Debug {
+    const UNIT: InsnFieldType<InsnFieldTypeTransformUnit>;
+    fn variant<Transform: InsnFieldTypeTransform>(
+        v: Transform::Type<Self>,
+    ) -> InsnFieldType<Transform>;
+}
+
+macro_rules! insn_field_enum {
+    (
+        $enum_vis:vis enum $InsnFieldType:ident<$Transform:ident: $InsnFieldTypeTransform:ident> {
+            $($Variant:ident($Transform2:ident::$Type:ident<$variant_ty:ty>),)*
+        }
+    ) => {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        $enum_vis enum $InsnFieldType<$Transform: $InsnFieldTypeTransform> {
+            $($Variant($Transform2::$Type<$variant_ty>),)*
+        }
+
+        $(impl InsnFieldTrait for $variant_ty {
+            const UNIT: $InsnFieldType<InsnFieldTypeTransformUnit> = $InsnFieldType::$Variant(());
+            fn variant<$Transform2: $InsnFieldTypeTransform>(
+                v: $Transform2::$Type<Self>,
+            ) -> $InsnFieldType<$Transform2> {
+                $InsnFieldType::$Variant(v)
+            }
+        })*
+    };
+}
+
+insn_field_enum! {
+    pub(crate) enum InsnFieldType<Transform: InsnFieldTypeTransform> {
+        Memory(Transform::Type<StatePartIndex<StatePartKindMemories>>),
+        SmallSlot(Transform::Type<StatePartIndex<StatePartKindSmallSlots>>),
+        BigSlot(Transform::Type<StatePartIndex<StatePartKindBigSlots>>),
+        SmallSlotArrayIndexed(Transform::Type<StatePartArrayIndexed<StatePartKindSmallSlots>>),
+        BigSlotArrayIndexed(Transform::Type<StatePartArrayIndexed<StatePartKindBigSlots>>),
+        SmallUInt(Transform::Type<SmallUInt>),
+        SmallSInt(Transform::Type<SmallSInt>),
+        InternedBigInt(Transform::Type<Interned<BigInt>>),
+        U8(Transform::Type<u8>),
+        USize(Transform::Type<usize>),
+        Empty(Transform::Type<[(); 0]>),
+    }
+}
+
+impl<Transform: InsnFieldTypeTransform> InsnFieldType<Transform> {
+    pub(crate) fn empty() -> Self {
+        Self::Empty(Transform::empty_type())
+    }
+}
+
+#[derive(PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnField<Transform: InsnFieldTypeTransform> {
+    pub(crate) ty: InsnFieldType<Transform>,
+    pub(crate) kind: InsnFieldKind,
+}
+
+impl<Transform: InsnFieldTypeTransform> Clone for InsnField<Transform>
+where
+    InsnFieldType<Transform>: Clone,
+{
+    fn clone(&self) -> Self {
+        Self {
+            ty: self.ty.clone(),
+            kind: self.kind.clone(),
+        }
+    }
+}
+
+impl<Transform: InsnFieldTypeTransform> Copy for InsnField<Transform> where
+    InsnFieldType<Transform>: Copy
+{
+}
+
+fn make_array_into_iter<T, const I: usize, const N: usize>(
+    input: [T; I],
+    mut default: impl FnMut() -> T,
+) -> std::array::IntoIter<T, N> {
+    const {
+        assert!(I <= N);
+    };
+    let mut input = input.into_iter();
+    let array = std::array::from_fn(|_| input.next().unwrap_or_else(&mut default));
+    let mut retval = array.into_iter();
+    // remove unneeded trailing elements
+    if I < N {
+        retval.nth_back(N - I - 1);
+    }
+    retval
+}
+
+impl fmt::Debug for Insn {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt::<InsnsBuildingDone>(f, None, None, None)
+    }
+}
+
+struct PrefixLinesWrapper<'a, W> {
+    writer: W,
+    at_beginning_of_line: bool,
+    blank_line_prefix: &'a str,
+    line_prefix: &'a str,
+}
+
+impl<T: fmt::Write> fmt::Write for PrefixLinesWrapper<'_, T> {
+    fn write_str(&mut self, input: &str) -> fmt::Result {
+        for part in input.split_inclusive('\n') {
+            if part.is_empty() {
+                continue;
+            }
+            if self.at_beginning_of_line {
+                let prefix = match part {
+                    "\n" => self.blank_line_prefix,
+                    _ => self.line_prefix,
+                };
+                if !prefix.is_empty() {
+                    self.writer.write_str(prefix)?;
+                }
+                self.at_beginning_of_line = false;
+            }
+            self.writer.write_str(part)?;
+            self.at_beginning_of_line = part.ends_with('\n');
+        }
+        Ok(())
+    }
+}
+
+impl Insn {
+    fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut fmt::Formatter<'_>,
+        labels: Option<&Labels>,
+        state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
+    ) -> fmt::Result {
+        let (insn_name, fields) = self.fields_with_names();
+        write!(f, "{insn_name}")?;
+        if fields.len() == 0 {
+            return Ok(());
+        }
+        let mut f = PrefixLinesWrapper {
+            writer: f,
+            at_beginning_of_line: false,
+            blank_line_prefix: "",
+            line_prefix: "    ",
+        };
+        writeln!(f, " {{")?;
+        for (field_name, field) in fields {
+            write!(f, "{field_name}: ")?;
+            match field.kind {
+                InsnFieldKind::BranchTarget => match field.ty {
+                    InsnFieldType::USize(&label_index) => {
+                        if let Some(labels) = labels {
+                            write!(f, "L{label_index}")?;
+                            if let Some(label) = labels.labels.get(label_index) {
+                                if let Some(address) = label.address {
+                                    write!(f, " (at {address})")?;
+                                } else {
+                                    write!(f, " (not yet defined)")?;
+                                }
+                            } else {
+                                write!(f, " (invalid)")?;
+                            }
+                            writeln!(f, ",")?;
+                            continue;
+                        }
+                    }
+                    InsnFieldType::Memory(_)
+                    | InsnFieldType::SmallSlot(_)
+                    | InsnFieldType::BigSlot(_)
+                    | InsnFieldType::SmallSlotArrayIndexed(_)
+                    | InsnFieldType::BigSlotArrayIndexed(_)
+                    | InsnFieldType::SmallUInt(_)
+                    | InsnFieldType::SmallSInt(_)
+                    | InsnFieldType::InternedBigInt(_)
+                    | InsnFieldType::U8(_)
+                    | InsnFieldType::Empty(_) => {}
+                },
+                InsnFieldKind::Input
+                | InsnFieldKind::Memory
+                | InsnFieldKind::Output
+                | InsnFieldKind::Immediate => {}
+            }
+            macro_rules! debug_fmt_state_part {
+                ($v:expr) => {
+                    $v.debug_fmt(&mut f, ",", " // ", "        // ", "", state_layout, state)
+                };
+            }
+            match field.ty {
+                InsnFieldType::Memory(v) => {
+                    debug_fmt_state_part!(v)?;
+                }
+                InsnFieldType::SmallSlot(v) => {
+                    debug_fmt_state_part!(v)?;
+                }
+                InsnFieldType::BigSlot(v) => {
+                    debug_fmt_state_part!(v)?;
+                }
+                InsnFieldType::SmallSlotArrayIndexed(v) => {
+                    debug_fmt_state_part!(v)?;
+                }
+                InsnFieldType::BigSlotArrayIndexed(v) => {
+                    debug_fmt_state_part!(v)?;
+                }
+                InsnFieldType::SmallUInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::SmallSInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::InternedBigInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::U8(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::USize(v) => write!(f, "{v}")?,
+                InsnFieldType::Empty(v) => write!(f, "{v:?}")?,
+            }
+            writeln!(f, ",")?;
+        }
+        write!(f.writer, "}}")
+    }
+}
+
+pub(crate) trait Breakpoints {
+    type Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break>;
+}
+
+impl<T: ?Sized + Breakpoints> Breakpoints for &'_ mut T {
+    type Break = T::Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        T::check_for_breakpoint(self, pc)
+    }
+}
+
+impl<T: ?Sized + Breakpoints> Breakpoints for Box<T> {
+    type Break = T::Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        T::check_for_breakpoint(self, pc)
+    }
+}
+
+impl Breakpoints for () {
+    type Break = Infallible;
+    fn check_for_breakpoint(&mut self, _pc: usize) -> ControlFlow<Self::Break> {
+        ControlFlow::Continue(())
+    }
+}
+
+pub(crate) struct BreakpointsSet {
+    pub(crate) last_was_break: bool,
+    pub(crate) set: HashSet<usize>,
+    pub(crate) trace: bool,
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+pub(crate) enum BreakAction {
+    DumpStateAndContinue,
+    Continue,
+}
+
+impl Breakpoints for BreakpointsSet {
+    type Break = BreakAction;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        let retval = if self.last_was_break {
+            ControlFlow::Continue(())
+        } else if self.set.contains(&pc) {
+            ControlFlow::Break(BreakAction::DumpStateAndContinue)
+        } else if self.trace {
+            ControlFlow::Break(BreakAction::Continue)
+        } else {
+            ControlFlow::Continue(())
+        };
+        self.last_was_break = retval.is_break();
+        retval
+    }
+}
+
+pub(crate) enum RunResult<Break, Return> {
+    Break(Break),
+    Return(Return),
+}
+
+macro_rules! impl_insns {
+    (
+        #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
+        $vis:vis fn $State:ident::$run:ident(&mut $self:ident) -> $run_ret_ty:ty {
+            #[state]
+            let mut $state:ident = $state_init:expr;
+            setup! {
+                $($setup:tt)*
+            }
+            main_loop!();
+            cleanup! {
+                $($cleanup:tt)*
+            }
+        }
+        $(
+            $(#[$insn_meta:meta])*
+            $insn_name:ident $({
+                $(
+                    #[kind = $field_kind:ident]
+                    $(#[$field_meta:meta])*
+                    $field_name:ident: $field_ty:ty,
+                )*
+            })? => $block:block
+        )*
+    ) => {
+        #[derive(Copy, Clone, Eq, PartialEq, Hash)]
+        $vis enum $Insn {
+            $(
+                $(#[$insn_meta])*
+                $insn_name $({
+                    $(
+                        $(#[$field_meta])*
+                        $field_name: $field_ty,
+                    )*
+                })?,
+            )*
+        }
+
+        impl $Insn {
+            $vis const MAX_FIELDS: usize = {
+                let mut retval = 0;
+                $($(
+                    let fields = [$(stringify!($field_name),)*].len();
+                    if retval < fields {
+                        retval = fields;
+                    }
+                )?)*
+                retval
+            };
+        }
+
+        impl $Insn {
+            $vis const fn fields_unit(&self) -> &'static [InsnField<InsnFieldTypeTransformUnit>] {
+                match self {
+                    $(
+                        $Insn::$insn_name {..} => &[
+                            $($(InsnField {
+                                ty: <$field_ty as InsnFieldTrait>::UNIT,
+                                kind: InsnFieldKind::$field_kind,
+                            },)*)?
+                        ],
+                    )*
+                }
+            }
+            $vis fn fields<'a>(&'a self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformRef<'a>>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+            $vis fn fields_with_names<'a>(&'a self) -> (&'static str, std::array::IntoIter<(&'static str, InsnField<InsnFieldTypeTransformRef<'a>>), { $Insn::MAX_FIELDS }>) {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => (
+                            stringify!($insn_name),
+                            make_array_into_iter([
+                                    $($((stringify!($field_name), InsnField {
+                                        ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                        kind: InsnFieldKind::$field_kind,
+                                    }),)*)?
+                                ],
+                                || ("", InsnField {
+                                    ty: InsnFieldType::empty(),
+                                    kind: InsnFieldKind::Immediate,
+                                }),
+                            ),
+                        ),
+                    )*
+                }
+            }
+            $vis fn fields_mut<'a>(&'a mut self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformRefMut<'a>>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+            $vis fn into_fields(self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformValue>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+        }
+
+        impl $State {
+            $vis fn $run<B: Breakpoints>(&mut $self, mut breakpoints: B) -> RunResult<B::Break, $run_ret_ty> {
+                let mut $state = $state_init;
+                $($setup)*
+                let mut insn = $state.insns[$state.pc];
+                let retval = 'main_loop: loop {
+                    if let ControlFlow::Break(b) = breakpoints.check_for_breakpoint($state.pc) {
+                        break RunResult::Break(b);
+                    }
+                    macro_rules! $next_macro {
+                        () => {
+                            $state.pc += 1;
+                            insn = $state.insns[$state.pc];
+                            continue 'main_loop;
+                        };
+                    }
+                    macro_rules! $branch_macro {
+                        ($next_pc:expr) => {
+                            $state.pc = $next_pc;
+                            insn = $state.insns[$state.pc];
+                            continue 'main_loop;
+                        };
+                    }
+                    let _: Infallible = match insn {
+                        $(
+                            $Insn::$insn_name $({
+                                $(
+                                    $field_name,
+                                )*
+                            })? => {
+                                $block
+                            }
+                        )*
+                    };
+                };
+                $($cleanup)*
+                retval
+            }
+        }
+    };
+}
+
+pub(crate) trait InsnsBuildingKind: Copy + Eq + fmt::Debug + Hash + Default {
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static>: fmt::Debug
+        + Clone
+        + Eq
+        + Hash
+        + Send
+        + Sync
+        + 'static
+        + Default
+        + Deref<Target = [T]>
+        + FromIterator<T>;
+    type Labels: Default;
+    fn labels(labels: &Self::Labels) -> Option<&Labels>;
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnsBuildingDone;
+
+impl InsnsBuildingKind for InsnsBuildingDone {
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Interned<[T]>;
+    type Labels = ();
+    fn labels(_labels: &Self::Labels) -> Option<&Labels> {
+        None
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnsBuilding;
+
+impl InsnsBuildingKind for InsnsBuilding {
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Vec<T>;
+    type Labels = Labels;
+    fn labels(labels: &Self::Labels) -> Option<&Labels> {
+        Some(labels)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) struct Label(pub(crate) usize);
+
+impl fmt::Debug for Label {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "L{}:", self.0)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) enum InsnOrLabel {
+    Insn(Insn),
+    Label(Label),
+}
+
+impl From<Insn> for InsnOrLabel {
+    fn from(value: Insn) -> Self {
+        Self::Insn(value)
+    }
+}
+
+impl From<Label> for InsnOrLabel {
+    fn from(value: Label) -> Self {
+        Self::Label(value)
+    }
+}
+
+impl fmt::Debug for InsnOrLabel {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::Insn(v) => v.fmt(f),
+            Self::Label(v) => v.fmt(f),
+        }
+    }
+}
+
+struct LabelData {
+    address: Option<usize>,
+}
+
+#[derive(Default)]
+pub(crate) struct Labels {
+    labels: Vec<LabelData>,
+    address_to_label_map: HashMap<usize, Vec<Label>>,
+}
+
+#[derive(Clone, PartialEq, Eq, Hash)]
+pub(crate) struct Insns<BK: InsnsBuildingKind> {
+    pub(crate) insns: BK::Vec<Insn>,
+    pub(crate) insn_source_locations: BK::Vec<SourceLocation>,
+    pub(crate) labels: BK::Labels,
+    pub(crate) state_layout: StateLayout<BK>,
+}
+
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    pub(crate) fn state_layout(&self) -> &StateLayout<BK> {
+        &self.state_layout
+    }
+}
+
+struct InsnsDebug<'a, BK: InsnsBuildingKind> {
+    insns: &'a [Insn],
+    insn_source_locations: &'a [SourceLocation],
+    labels: &'a BK::Labels,
+    state_layout: &'a StateLayout<BK>,
+    state: Option<&'a State>,
+}
+
+struct InsnDebug<'a, BK: InsnsBuildingKind> {
+    address: usize,
+    source_location: Option<SourceLocation>,
+    insn: &'a Insn,
+    labels: Option<&'a Labels>,
+    state_layout: &'a StateLayout<BK>,
+    state: Option<&'a State>,
+}
+
+impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if let Some(labels) = self
+            .labels
+            .and_then(|labels| labels.address_to_label_map.get(&self.address))
+        {
+            for &label in labels {
+                writeln!(f, "{label:?}")?;
+            }
+        }
+        if let Some(source_location) = self.source_location {
+            writeln!(f, "// at: {source_location}")?;
+        }
+        write!(f, "{}: ", self.address)?;
+        self.insn
+            .debug_fmt(f, self.labels, Some(self.state_layout), self.state)
+    }
+}
+
+impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let labels = BK::labels(&self.labels);
+        let mut debug_list = f.debug_list();
+        let mut last_source_location = None;
+        for (address, (insn, &source_location)) in self
+            .insns
+            .iter()
+            .zip(self.insn_source_locations)
+            .enumerate()
+        {
+            debug_list.entry(&InsnDebug {
+                address,
+                source_location: if Some(source_location) != last_source_location {
+                    Some(source_location)
+                } else {
+                    None
+                },
+                insn,
+                labels,
+                state_layout: self.state_layout,
+                state: self.state,
+            });
+            last_source_location = Some(source_location);
+        }
+        debug_list.finish()
+    }
+}
+
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    pub(crate) fn debug_insn_at<'a>(
+        &'a self,
+        address: usize,
+        state: Option<&'a State>,
+    ) -> impl fmt::Debug + 'a {
+        let Self {
+            insns,
+            insn_source_locations,
+            labels,
+            state_layout,
+        } = self;
+        InsnDebug {
+            address,
+            source_location: Some(insn_source_locations[address]),
+            insn: &insns[address],
+            labels: BK::labels(labels),
+            state_layout,
+            state,
+        }
+    }
+}
+
+impl State {
+    pub(crate) fn debug_insn_at(&self, address: usize) -> impl fmt::Debug + '_ {
+        self.insns.debug_insn_at(address, Some(self))
+    }
+}
+
+struct InsnsOfState<'a>(&'a State);
+
+impl fmt::Debug for InsnsOfState<'_> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.insns.debug_fmt(Some(self.0), f)
+    }
+}
+
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    fn debug_fmt(&self, state: Option<&State>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            insns,
+            insn_source_locations,
+            labels,
+            state_layout,
+        } = self;
+        f.debug_struct("Insns")
+            .field("state_layout", state_layout)
+            .field(
+                "insns",
+                &InsnsDebug::<BK> {
+                    insns,
+                    insn_source_locations,
+                    labels,
+                    state_layout,
+                    state,
+                },
+            )
+            .finish_non_exhaustive()
+    }
+}
+
+impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(None, f)
+    }
+}
+
+pub(crate) trait StatePartKind:
+    Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default
+{
+    const NAME: &'static str;
+    type DebugData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
+    type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
+    type State: fmt::Debug + 'static + Clone;
+    type BorrowedState<'a>: 'a;
+    fn new_state(layout_data: &[Self::LayoutData]) -> Self::State;
+    fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
+    fn part_debug_data<BK: InsnsBuildingKind>(
+        state_layout: &StateLayout<BK>,
+        part_index: StatePartIndex<Self>,
+    ) -> Option<&Self::DebugData>;
+    fn debug_fmt_state_value(
+        state: &State,
+        index: StatePartIndex<Self>,
+        f: &mut impl fmt::Write,
+    ) -> fmt::Result;
+}
+
+pub(crate) trait StatePartsValue {
+    type Value<K: StatePartKind>;
+}
+
+macro_rules! impl_state_parts_traits {
+    (
+        struct $Struct:ident<$V:ident: $StatePartsValue:ident> {
+            $(#[flatten]
+            $flattened_field:ident: $flattened_field_ty:ty,
+            $(#[field_in_flattened]
+            $field_in_flattened:ident: $field_in_flattened_ty:ty,)*
+            )?
+            $($field:ident: $field_ty:ty,)*
+        }
+    ) => {
+        impl<$V: $StatePartsValue> Copy for $Struct<$V>
+        where
+            $($flattened_field_ty: Copy,)?
+            $($field_ty: Copy,)*
+        {
+        }
+
+        impl<$V: $StatePartsValue> Clone for $Struct<$V>
+        where
+            $($flattened_field_ty: Clone,)?
+            $($field_ty: Clone,)*
+        {
+            fn clone(&self) -> Self {
+                Self {
+                    $($flattened_field: self.$flattened_field.clone(),)?
+                    $($field: self.$field.clone(),)*
+                }
+            }
+        }
+
+        impl<$V: $StatePartsValue> fmt::Debug for $Struct<$V>
+        where
+            $($($field_in_flattened_ty: fmt::Debug,)*)?
+            $($field_ty: fmt::Debug,)*
+        {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                f.debug_struct(stringify!($Struct))
+                    $($(.field(stringify!($field_in_flattened), &self.$flattened_field.$field_in_flattened))*)?
+                    $(.field(stringify!($field), &self.$field))*
+                    .finish()
+            }
+        }
+
+        impl<$V: $StatePartsValue> PartialEq for $Struct<$V>
+        where
+            $($flattened_field_ty: PartialEq,)?
+            $($field_ty: PartialEq,)*
+        {
+            fn eq(&self, other: &Self) -> bool {
+                true $(&& self.$flattened_field == other.$flattened_field)? $(&& self.$field == other.$field)*
+            }
+        }
+
+        impl<$V: $StatePartsValue> Eq for $Struct<$V>
+        where
+            $($flattened_field_ty: Eq,)?
+            $($field_ty: Eq,)*
+        {
+        }
+
+        impl<$V: $StatePartsValue> Hash for $Struct<$V>
+        where
+            $($flattened_field_ty: Hash,)?
+            $($field_ty: Hash,)*
+        {
+            fn hash<H: Hasher>(&self, h: &mut H) {
+                $(self.$flattened_field.hash(h);)?
+                $(self.$field.hash(h);)*
+            }
+        }
+
+        impl<$V: $StatePartsValue> Default for $Struct<$V>
+        where
+            $($flattened_field_ty: Default,)?
+            $($field_ty: Default,)*
+        {
+            fn default() -> Self {
+                Self {
+                    $($flattened_field: Default::default(),)?
+                    $($field: Default::default(),)*
+                }
+            }
+        }
+    };
+}
+
+macro_rules! make_state_part_kinds {
+    (
+        $(
+            #[state, field = $state_field:ident]
+            impl $StateStatePartKind:ident for $StateKind:ident $state_impl_body:tt
+        )*
+        $(
+            #[type, field = $type_field:ident]
+            impl $TypeStatePartKind:ident for $TypeKind:ident $type_impl_body:tt
+        )*
+    ) => {
+        $(
+            #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
+            pub(crate) struct $StateKind;
+
+            impl $StateStatePartKind for $StateKind $state_impl_body
+        )*
+
+        $(
+            #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
+            pub(crate) struct $TypeKind;
+
+            impl $TypeStatePartKind for $TypeKind $type_impl_body
+        )*
+
+        pub(crate) struct StateParts<V: StatePartsValue> {
+            pub(crate) ty: TypeParts<V>,
+            $(pub(crate) $state_field: V::Value<$StateKind>,)*
+        }
+
+        impl_state_parts_traits! {
+            struct StateParts<V: StatePartsValue> {
+                #[flatten]
+                ty: TypeParts<V>,
+                $(#[field_in_flattened]
+                $type_field: V::Value<$TypeKind>,)*
+                $($state_field: V::Value<$StateKind>,)*
+            }
+        }
+
+        pub(crate) struct TypeParts<V: StatePartsValue> {
+            $(pub(crate) $type_field: V::Value<$TypeKind>,)*
+        }
+
+        impl_state_parts_traits! {
+            struct TypeParts<V: StatePartsValue> {
+                $($type_field: V::Value<$TypeKind>,)*
+            }
+        }
+
+        #[derive(Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateLayout<BK: InsnsBuildingKind> {
+            pub(crate) ty: TypeLayout<BK>,
+            $(pub(crate) $state_field: StatePartLayout<$StateKind, BK>,)*
+        }
+
+        impl Copy for StateLayout<InsnsBuildingDone> {}
+
+        impl<BK: InsnsBuildingKind> StateLayout<BK> {
+            pub(crate) fn len(&self) -> StateLen {
+                StateLen {
+                    ty: self.ty.len(),
+                    $($state_field: self.$state_field.len(),)*
+                }
+            }
+            pub(crate) fn is_empty(&self) -> bool {
+                self.ty.is_empty() $(&& self.$state_field.is_empty())*
+            }
+            pub(crate) fn empty() -> Self {
+                Self {
+                    ty: TypeLayout::empty(),
+                    $($state_field: StatePartLayout::empty(),)*
+                }
+            }
+        }
+
+        impl StateLayout<InsnsBuilding> {
+            pub(crate) fn next_index(&self) -> StateIndex {
+                StateIndex {
+                    ty: self.ty.next_index(),
+                    $($state_field: self.$state_field.next_index(),)*
+                }
+            }
+            pub(crate) fn allocate<BK: InsnsBuildingKind>(
+                &mut self,
+                layout: &StateLayout<BK>,
+            ) -> StateIndexRange {
+                StateIndexRange {
+                    ty: self.ty.allocate(&layout.ty),
+                    $($state_field: self.$state_field.allocate(&layout.$state_field),)*
+                }
+            }
+        }
+
+        impl From<StateLayout<InsnsBuilding>> for StateLayout<InsnsBuildingDone> {
+            fn from(v: StateLayout<InsnsBuilding>) -> Self {
+                Self {
+                    ty: v.ty.into(),
+                    $($state_field: v.$state_field.into(),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateIndexRange {
+            pub(crate) ty: TypeIndexRange,
+            $(pub(crate) $state_field: StatePartIndexRange<$StateKind>,)*
+        }
+
+        impl StateIndexRange {
+            pub(crate) fn start(self) -> StateIndex {
+                StateIndex {
+                    ty: self.ty.start(),
+                    $($state_field: self.$state_field.start(),)*
+                }
+            }
+            pub(crate) fn len(self) -> StateLen {
+                StateLen {
+                    ty: self.ty.len(),
+                    $($state_field: self.$state_field.len(),)*
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.ty.is_empty() $(&& self.$state_field.is_empty())*
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateLen {
+            pub(crate) ty: TypeLen,
+            $(pub(crate) $state_field: StatePartLen<$StateKind>,)*
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateIndex {
+            pub(crate) ty: TypeIndex,
+            $(pub(crate) $state_field: StatePartIndex<$StateKind>,)*
+        }
+
+        #[derive(Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeLayout<BK: InsnsBuildingKind> {
+            $(pub(crate) $type_field: StatePartLayout<$TypeKind, BK>,)*
+        }
+
+        impl Copy for TypeLayout<InsnsBuildingDone> {}
+
+        impl<BK: InsnsBuildingKind> TypeLayout<BK> {
+            pub(crate) fn len(&self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.len(),)*
+                }
+            }
+            pub(crate) fn is_empty(&self) -> bool {
+                $(self.$type_field.is_empty())&&+
+            }
+            pub(crate) fn empty() -> Self {
+                Self {
+                    $($type_field: StatePartLayout::empty(),)*
+                }
+            }
+        }
+
+        impl TypeLayout<InsnsBuilding> {
+            pub(crate) fn next_index(&self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.next_index(),)*
+                }
+            }
+            pub(crate) fn allocate<BK: InsnsBuildingKind>(
+                &mut self,
+                layout: &TypeLayout<BK>,
+            ) -> TypeIndexRange {
+                TypeIndexRange {
+                    $($type_field: self.$type_field.allocate(&layout.$type_field),)*
+                }
+            }
+        }
+
+        impl From<TypeLayout<InsnsBuilding>> for TypeLayout<InsnsBuildingDone> {
+            fn from(v: TypeLayout<InsnsBuilding>) -> Self {
+                Self {
+                    $($type_field: v.$type_field.into(),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeIndexRange {
+            $(pub(crate) $type_field: StatePartIndexRange<$TypeKind>,)*
+        }
+
+        impl TypeIndexRange {
+            pub(crate) fn new(start: TypeIndex, len: TypeLen) -> Self {
+                Self {
+                    $($type_field: StatePartIndexRange {
+                        start: start.$type_field,
+                        len: len.$type_field,
+                    },)*
+                }
+            }
+            pub(crate) fn start(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.start(),)*
+                }
+            }
+            pub(crate) fn len(self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.len(),)*
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                $(self.$type_field.is_empty()) &&+
+            }
+            pub(crate) fn slice(self, index: TypeIndexRange) -> Self {
+                Self {
+                    $($type_field: self.$type_field.slice(index.$type_field),)*
+                }
+            }
+            pub(crate) fn index_array(self, element_size: TypeLen, index: usize) -> Self {
+                Self {
+                    $($type_field: self.$type_field.index_array(element_size.$type_field, index),)*
+                }
+            }
+            pub(crate) fn offset(self, offset: TypeIndex) -> Self {
+                Self {
+                    $($type_field: self.$type_field.offset(offset.$type_field),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeLen {
+            $(pub(crate) $type_field: StatePartLen<$TypeKind>,)*
+        }
+
+        impl TypeLen {
+            pub(crate) const fn as_index(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.as_index(),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeIndex {
+            $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)*
+        }
+
+        impl TypeIndex {
+            pub(crate) const ZERO: Self = Self {
+                $($type_field: StatePartIndex::ZERO,)*
+            };
+            pub(crate) fn offset(self, offset: TypeIndex) -> Self {
+                Self {
+                    $($type_field: self.$type_field.offset(offset.$type_field),)*
+                }
+            }
+        }
+
+        pub(crate) struct State {
+            pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
+            pub(crate) pc: usize,
+            pub(crate) memory_write_log: Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
+            $(pub(crate) $state_field: StatePart<$StateKind>,)*
+            $(pub(crate) $type_field: StatePart<$TypeKind>,)*
+        }
+
+        impl fmt::Debug for State {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self {
+                    insns: _,
+                    pc,
+                    memory_write_log,
+                    $($state_field,)*
+                    $($type_field,)*
+                } = self;
+                f.debug_struct("State")
+                    .field("insns", &InsnsOfState(self))
+                    .field("pc", pc)
+                    .field("memory_write_log", memory_write_log)
+                    $(.field(stringify!($state_field), $state_field))*
+                    $(.field(stringify!($type_field), $type_field))*
+                    .finish()
+            }
+        }
+
+        impl State {
+            pub(crate) fn new(insns: Interned<Insns<InsnsBuildingDone>>) -> Self {
+                Self {
+                    insns,
+                    pc: 0,
+                    memory_write_log: Vec::with_capacity(32),
+                    $($state_field: StatePart::new(&insns.state_layout.$state_field.layout_data),)*
+                    $($type_field: StatePart::new(&insns.state_layout.ty.$type_field.layout_data),)*
+                }
+            }
+            pub(crate) fn borrow(&mut self) -> BorrowedState<'_> {
+                BorrowedState {
+                    orig_insns: self.insns,
+                    insns: &self.insns.insns,
+                    pc: self.pc,
+                    orig_pc: &mut self.pc,
+                    memory_write_log: &mut self.memory_write_log,
+                    $($state_field: self.$state_field.borrow(),)*
+                    $($type_field: self.$type_field.borrow(),)*
+                }
+            }
+        }
+
+        #[derive(Debug)]
+        pub(crate) struct BorrowedState<'a> {
+            pub(crate) orig_insns: Interned<Insns<InsnsBuildingDone>>,
+            pub(crate) insns: &'a [Insn],
+            pub(crate) orig_pc: &'a mut usize,
+            pub(crate) pc: usize,
+            pub(crate) memory_write_log: &'a mut Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
+            $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)*
+            $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)*
+        }
+
+        impl Drop for BorrowedState<'_> {
+            fn drop(&mut self) {
+                *self.orig_pc = self.pc;
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub(crate) struct TypeArrayIndexes {
+            $(pub(crate) $type_field: Interned<[StatePartArrayIndex<$TypeKind>]>,)*
+        }
+
+        impl TypeArrayIndexes {
+            pub(crate) fn as_ref(&self) -> TypeArrayIndexesRef<'_> {
+                TypeArrayIndexesRef {
+                    $($type_field: &self.$type_field,)*
+                }
+            }
+            #[must_use]
+            pub(crate) fn join(self, next: TypeArrayIndex) -> TypeArrayIndexes {
+                TypeArrayIndexes {
+                    $($type_field: Interned::from_iter(self.$type_field.iter().copied().chain([next.$type_field])),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeArrayIndex {
+            $(pub(crate) $type_field: StatePartArrayIndex<$TypeKind>,)*
+        }
+
+        impl TypeArrayIndex {
+            pub(crate) fn from_parts(index: StatePartIndex<StatePartKindSmallSlots>, len: usize, stride: TypeLen) -> Self {
+                Self {
+                    $($type_field: StatePartArrayIndex {
+                        index,
+                        len,
+                        stride: stride.$type_field,
+                    },)*
+                }
+            }
+            pub(crate) fn len(self) -> usize {
+                let len = self.small_slots.len;
+                $(assert_eq!(self.$type_field.len, len, "array length mismatch");)*
+                len
+            }
+            pub(crate) fn index(self) -> StatePartIndex<StatePartKindSmallSlots> {
+                let index = self.small_slots.index;
+                $(assert_eq!(self.$type_field.index, index, "array index mismatch");)*
+                index
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.len() == 0
+            }
+            pub(crate) fn stride(self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.stride,)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub(crate) struct TypeArrayIndexesRef<'a> {
+            $(pub(crate) $type_field: &'a [StatePartArrayIndex<$TypeKind>],)*
+        }
+
+        impl<'a> TypeArrayIndexesRef<'a> {
+            pub(crate) fn len(self) -> usize {
+                let len = self.small_slots.len();
+                $(assert_eq!(self.$type_field.len(), len, "indexes count mismatch");)*
+                len
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.len() == 0
+            }
+            pub(crate) fn iter(self) -> impl Iterator<Item = TypeArrayIndex> + 'a {
+                (0..self.len()).map(move |i| TypeArrayIndex {
+                    $($type_field: self.$type_field[i],)*
+                })
+            }
+            pub(crate) fn for_each_offset(
+                self,
+                mut f: impl FnMut(TypeIndex),
+            ) {
+                self.for_each_offset2(TypeIndex {
+                    $($type_field: StatePartIndex {
+                        value: 0,
+                        _phantom: PhantomData,
+                    },)*
+                }, &mut f);
+            }
+            pub(crate) fn split_first(self) -> Option<(TypeArrayIndex, Self)> {
+                $(let $type_field = self.$type_field.split_first()?;)*
+                let next = TypeArrayIndex {
+                    $($type_field: *$type_field.0,)*
+                };
+                let rest = TypeArrayIndexesRef {
+                    $($type_field: $type_field.1,)*
+                };
+                Some((next, rest))
+            }
+            pub(crate) fn for_each_offset2(
+                self,
+                base_offset: TypeIndex,
+                f: &mut (impl FnMut(TypeIndex) + ?Sized),
+            ) {
+                if let Some((next, rest)) = self.split_first() {
+                    let stride = next.stride();
+                    for index in 0..next.len().try_into().expect("array too big") {
+                        let mut offset = TypeIndex {
+                            $($type_field: StatePartIndex {
+                                value: stride
+                                    .$type_field
+                                    .value
+                                    .checked_mul(index)
+                                    .expect("array too big"),
+                                _phantom: PhantomData,
+                            },)*
+                        };
+                        $(offset.$type_field.value =
+                            base_offset
+                                .$type_field
+                                .value
+                                .checked_add(offset.$type_field.value)
+                                .expect("array too big");)*
+                        rest.for_each_offset2(offset, f);
+                    }
+                } else {
+                    $(assert!(self.$type_field.is_empty(), "indexes count mismatch");)*
+                    f(base_offset);
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeArrayIndexed {
+            $(pub(crate) $type_field: StatePartArrayIndexed<$TypeKind>,)*
+        }
+
+        impl TypeArrayIndexed {
+            pub(crate) fn from_parts(base: TypeIndex, indexes: TypeArrayIndexes) -> Self {
+                Self {
+                    $($type_field: StatePartArrayIndexed {
+                        base: base.$type_field,
+                        indexes: indexes.$type_field,
+                    },)*
+                }
+            }
+            pub(crate) fn base(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.base,)*
+                }
+            }
+            pub(crate) fn indexes(self) -> TypeArrayIndexes {
+                TypeArrayIndexes {
+                    $($type_field: self.$type_field.indexes,)*
+                }
+            }
+        }
+
+        impl From<TypeIndex> for TypeArrayIndexed {
+            fn from(value: TypeIndex) -> Self {
+                TypeArrayIndexed {
+                    $($type_field: value.$type_field.into(),)*
+                }
+            }
+        }
+    };
+}
+
+#[derive(Copy, Clone, Hash, PartialEq, Eq)]
+pub(crate) struct MemoryData<T: Deref<Target = BitSlice>> {
+    pub(crate) array_type: Array,
+    pub(crate) data: T,
+}
+
+impl<T: Deref<Target = BitSlice>> fmt::Debug for MemoryData<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self { array_type, data } = self;
+        f.debug_struct("MemoryData")
+            .field("array_type", array_type)
+            .field(
+                "data",
+                &crate::memory::DebugMemoryData::from_bit_slice(*array_type, data),
+            )
+            .finish()
+    }
+}
+
+make_state_part_kinds! {
+    /*#[state, field = small_stack]
+    impl StatePartKind for StatePartKindSmallStack {
+        const NAME: &'static str = "SmallStack";
+        type DebugData = ();
+        type LayoutData = ();
+        type State = Stack<SmallUInt>;
+        type BorrowedState<'a> = BorrowedStack<'a, SmallUInt>;
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            Stack::new(layout_data.len())
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state.borrow()
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.small_stack.debug_data.get(part_index.as_usize())
+        }
+    }
+    #[state, field = big_stack]
+    impl StatePartKind for StatePartKindBigStack {
+        const NAME: &'static str = "BigStack";
+        type DebugData = ();
+        type LayoutData = ();
+        type State = Stack<BigInt>;
+        type BorrowedState<'a> = BorrowedStack<'a, BigInt>;
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            Stack::new(layout_data.len())
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state.borrow()
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.big_stack.debug_data.get(part_index.as_usize())
+        }
+    }*/
+    #[state, field = memories]
+    impl StatePartKind for StatePartKindMemories {
+        const NAME: &'static str = "Memories";
+        type DebugData = ();
+        type LayoutData = MemoryData<Interned<BitSlice>>;
+        type State = Box<[MemoryData<BitBox>]>;
+        type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            layout_data.iter().map(|MemoryData { array_type, data }| MemoryData {
+                array_type: *array_type,
+                data: BitBox::from_bitslice(data),
+            }).collect()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.memories.debug_data.get(part_index.as_usize())
+        }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            write!(f, "{:#?}", &state.memories[index])
+        }
+    }
+    #[type, field = small_slots]
+    impl StatePartKind for StatePartKindSmallSlots {
+        const NAME: &'static str = "SmallSlots";
+        type DebugData = SlotDebugData;
+        type LayoutData = ();
+        type State = Box<[SmallUInt]>;
+        type BorrowedState<'a> = &'a mut [SmallUInt];
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            vec![0; layout_data.len()].into_boxed_slice()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.ty.small_slots.debug_data.get(part_index.as_usize())
+        }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            let value = state.small_slots[index];
+            write!(f, "{value:#x} {}", value as SmallSInt)?;
+            Ok(())
+        }
+    }
+    #[type, field = big_slots]
+    impl StatePartKind for StatePartKindBigSlots {
+        const NAME: &'static str = "BigSlots";
+        type DebugData = SlotDebugData;
+        type LayoutData = ();
+        type State = Box<[BigInt]>;
+        type BorrowedState<'a> = &'a mut [BigInt];
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            layout_data.iter().map(|_| BigInt::default()).collect()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.ty.big_slots.debug_data.get(part_index.as_usize())
+        }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            write!(f, "{:#x}", state.big_slots[index])
+        }
+    }
+}
+
+impl TypeLen {
+    pub(crate) fn only_small(self) -> Option<StatePartLen<StatePartKindSmallSlots>> {
+        let Self {
+            small_slots,
+            big_slots:
+                StatePartLen {
+                    value: 0,
+                    _phantom: _,
+                },
+        } = self
+        else {
+            return None;
+        };
+        Some(small_slots)
+    }
+    pub(crate) const A_SMALL_SLOT: Self = TypeLen {
+        small_slots: StatePartLen {
+            value: 1,
+            _phantom: PhantomData,
+        },
+        big_slots: StatePartLen {
+            value: 0,
+            _phantom: PhantomData,
+        },
+    };
+    pub(crate) const A_BIG_SLOT: Self = TypeLen {
+        small_slots: StatePartLen {
+            value: 0,
+            _phantom: PhantomData,
+        },
+        big_slots: StatePartLen {
+            value: 1,
+            _phantom: PhantomData,
+        },
+    };
+}
+
+#[derive(Debug, Clone)]
+pub(crate) struct Stack<T> {
+    storage: Box<[T]>,
+    cur_len: usize,
+}
+
+impl<T> Stack<T> {
+    pub(crate) fn new(len: usize) -> Self
+    where
+        T: Default,
+    {
+        Self {
+            storage: std::iter::repeat_with(T::default).take(len).collect(),
+            cur_len: 0,
+        }
+    }
+    pub(crate) fn borrow(&mut self) -> BorrowedStack<'_, T> {
+        BorrowedStack {
+            storage: &mut self.storage,
+            cur_len: self.cur_len,
+            stack_cur_len: &mut self.cur_len,
+        }
+    }
+    pub(crate) fn clear(&mut self) {
+        self.cur_len = 0;
+    }
+}
+
+#[derive(Debug)]
+pub(crate) struct BorrowedStack<'a, T> {
+    storage: &'a mut [T],
+    cur_len: usize,
+    stack_cur_len: &'a mut usize,
+}
+
+impl<'a, T> BorrowedStack<'a, T> {
+    pub(crate) fn push(&mut self, value: T) {
+        self.storage[self.cur_len] = value;
+        self.cur_len += 1;
+    }
+    pub(crate) fn pop(&mut self) -> T
+    where
+        T: Default,
+    {
+        self.cur_len -= 1;
+        std::mem::take(&mut self.storage[self.cur_len])
+    }
+}
+
+impl<T> Drop for BorrowedStack<'_, T> {
+    fn drop(&mut self) {
+        *self.stack_cur_len = self.cur_len;
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+pub(crate) struct SlotDebugData {
+    pub(crate) name: Interned<str>,
+    pub(crate) ty: CanonicalType,
+}
+
+impl SlotDebugData {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        let mut name = String::with_capacity(self.name.len() + prefix.len());
+        name.push_str(prefix);
+        name.push_str(&self.name);
+        Self {
+            name: Intern::intern_owned(name),
+            ty: self.ty,
+        }
+    }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            name: Interned::default(),
+            ty: self.ty,
+        }
+    }
+}
+
+impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        Self {
+            debug_data: self
+                .debug_data
+                .iter()
+                .map(|v| v.with_prefixed_debug_names(prefix))
+                .collect(),
+            layout_data: self.layout_data.clone(),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            debug_data: self
+                .debug_data
+                .iter()
+                .map(|v| v.with_anonymized_debug_info())
+                .collect(),
+            layout_data: self.layout_data.clone(),
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<BK: InsnsBuildingKind> TypeLayout<BK> {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        Self {
+            small_slots: self.small_slots.with_prefixed_debug_names(prefix),
+            big_slots: self.big_slots.with_prefixed_debug_names(prefix),
+        }
+    }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            small_slots: self.small_slots.with_anonymized_debug_info(),
+            big_slots: self.big_slots.with_anonymized_debug_info(),
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct StatePartArrayIndex<K: StatePartKind> {
+    pub(crate) index: StatePartIndex<StatePartKindSmallSlots>,
+    pub(crate) len: usize,
+    pub(crate) stride: StatePartLen<K>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
+    pub(crate) base: StatePartIndex<K>,
+    pub(crate) indexes: Interned<[StatePartArrayIndex<K>]>,
+}
+
+impl<K: StatePartKind> StatePartArrayIndexed<K> {
+    pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut impl fmt::Write,
+        before_debug_info_text: &str,
+        comment_start: &str,
+        comment_line_start: &str,
+        comment_end: &str,
+        state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
+    ) -> fmt::Result {
+        let Self { base, indexes } = *self;
+        if indexes.is_empty() {
+            base.debug_fmt(
+                f,
+                before_debug_info_text,
+                comment_start,
+                comment_line_start,
+                comment_end,
+                state_layout,
+                state,
+            )
+        } else {
+            base.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
+            for StatePartArrayIndex { index, len, stride } in indexes {
+                f.write_str("[")?;
+                index.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
+                write!(f, ", len={len}, stride={}]", stride.value)?;
+            }
+            f.write_str(before_debug_info_text)
+        }
+    }
+}
+
+impl<K: StatePartKind + fmt::Debug> fmt::Debug for StatePartArrayIndexed<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
+    }
+}
+
+impl<K: StatePartKind> From<StatePartIndex<K>> for StatePartArrayIndexed<K> {
+    fn from(base: StatePartIndex<K>) -> Self {
+        Self {
+            base,
+            indexes: Interned::default(),
+        }
+    }
+}
+
+impl<K: StatePartKind> StatePartArrayIndexed<K> {
+    pub(crate) fn for_each_target2(
+        base: StatePartIndex<K>,
+        indexes: &[StatePartArrayIndex<K>],
+        f: &mut (impl FnMut(StatePartIndex<K>) + ?Sized),
+    ) {
+        if let [next, rest @ ..] = indexes {
+            for i in 0..next.len.try_into().expect("array too big") {
+                Self::for_each_target2(
+                    StatePartIndex {
+                        value: base
+                            .value
+                            .checked_add(next.stride.value.checked_mul(i).expect("array too big"))
+                            .expect("array too big"),
+                        _phantom: PhantomData,
+                    },
+                    rest,
+                    f,
+                );
+            }
+        } else {
+            f(base);
+        }
+    }
+    pub(crate) fn for_each_target(self, mut f: impl FnMut(StatePartIndex<K>)) {
+        Self::for_each_target2(self.base, &self.indexes, &mut f);
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub(crate) struct StatePartIndex<K: StatePartKind> {
+    pub(crate) value: u32,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> StatePartIndex<K> {
+    pub(crate) const ZERO: Self = Self {
+        value: 0,
+        _phantom: PhantomData,
+    };
+    pub(crate) fn as_usize(self) -> usize {
+        self.value.try_into().expect("index too big")
+    }
+    pub(crate) fn offset(self, offset: StatePartIndex<K>) -> Self {
+        Self {
+            value: self
+                .value
+                .checked_add(offset.value)
+                .expect("offset too big"),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut impl fmt::Write,
+        before_debug_info_text: &str,
+        comment_start: &str,
+        comment_line_start: &str,
+        comment_end: &str,
+        state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
+    ) -> fmt::Result {
+        write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?;
+        f.write_str(before_debug_info_text)?;
+        let debug_data =
+            state_layout.and_then(|state_layout| K::part_debug_data(state_layout, *self));
+        if state.is_some() || debug_data.is_some() {
+            f.write_str(comment_start)?;
+        }
+        let mut f = PrefixLinesWrapper {
+            writer: f,
+            at_beginning_of_line: false,
+            blank_line_prefix: comment_line_start.trim_end(),
+            line_prefix: comment_line_start,
+        };
+        if let Some(state) = state {
+            f.write_str("(")?;
+            K::debug_fmt_state_value(state, *self, &mut f)?;
+            f.write_str(")")?;
+        }
+        if state.is_some() && debug_data.is_some() {
+            f.write_str(" ")?;
+        }
+        if let Some(debug_data) = debug_data {
+            write!(f, "{debug_data:?}")?;
+        }
+        if state.is_some() || debug_data.is_some() {
+            f.writer.write_str(comment_end)?;
+        }
+        Ok(())
+    }
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub(crate) struct StatePartLen<K: StatePartKind> {
+    pub(crate) value: u32,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> StatePartLen<K> {
+    pub(crate) const fn new(value: u32) -> Self {
+        Self {
+            value,
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) const fn as_index(self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self.value,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartLen<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "StatePartLen<{}>({})", K::NAME, self.value)
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash)]
+pub(crate) struct StatePartLayout<K: StatePartKind, BK: InsnsBuildingKind> {
+    pub(crate) debug_data: BK::Vec<K::DebugData>,
+    pub(crate) layout_data: BK::Vec<K::LayoutData>,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> Copy for StatePartLayout<K, InsnsBuildingDone> {}
+
+impl<K: StatePartKind, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
+    pub(crate) fn len(&self) -> StatePartLen<K> {
+        StatePartLen::new(
+            self.debug_data
+                .len()
+                .try_into()
+                .expect("state part allocation layout is too big"),
+        )
+    }
+    pub(crate) fn is_empty(&self) -> bool {
+        self.debug_data.is_empty()
+    }
+    pub(crate) fn empty() -> Self {
+        Self {
+            debug_data: Default::default(),
+            layout_data: Default::default(),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn debug_data(&self, index: StatePartIndex<K>) -> &K::DebugData {
+        &self.debug_data[index.as_usize()]
+    }
+}
+
+impl<K: StatePartKind> From<StatePartLayout<K, InsnsBuilding>>
+    for StatePartLayout<K, InsnsBuildingDone>
+{
+    fn from(value: StatePartLayout<K, InsnsBuilding>) -> Self {
+        Self {
+            debug_data: Intern::intern_owned(value.debug_data),
+            layout_data: Intern::intern_owned(value.layout_data),
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<K: StatePartKind> StatePartLayout<K, InsnsBuilding> {
+    pub(crate) fn scalar(debug_data: K::DebugData, layout_data: K::LayoutData) -> Self {
+        Self {
+            debug_data: vec![debug_data],
+            layout_data: vec![layout_data],
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn next_index(&self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self.len().value,
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn allocate<BK: InsnsBuildingKind>(
+        &mut self,
+        layout: &StatePartLayout<K, BK>,
+    ) -> StatePartIndexRange<K> {
+        let start = self.next_index();
+        let len = layout.len();
+        let Self {
+            debug_data,
+            layout_data,
+            _phantom: _,
+        } = self;
+        debug_data.extend_from_slice(&layout.debug_data);
+        layout_data.extend_from_slice(&layout.layout_data);
+        StatePartIndexRange { start, len }
+    }
+}
+
+impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K, BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            debug_data,
+            layout_data,
+            _phantom: _,
+        } = self;
+        write!(f, "StatePartLayout<{}>", K::NAME)?;
+        let mut debug_struct = f.debug_struct("");
+        debug_struct
+            .field("len", &debug_data.len())
+            .field("debug_data", debug_data);
+        if TypeId::of::<K::LayoutData>() != TypeId::of::<()>() {
+            debug_struct.field("layout_data", layout_data);
+        }
+        debug_struct.finish_non_exhaustive()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) struct StatePartIndexRange<K: StatePartKind> {
+    pub(crate) start: StatePartIndex<K>,
+    pub(crate) len: StatePartLen<K>,
+}
+
+impl<K: StatePartKind> StatePartIndexRange<K> {
+    pub(crate) fn start(self) -> StatePartIndex<K> {
+        self.start
+    }
+    pub(crate) fn end(self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self
+                .start
+                .value
+                .checked_add(self.len.value)
+                .expect("state part allocation layout is too big"),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn len(self) -> StatePartLen<K> {
+        self.len
+    }
+    pub(crate) fn is_empty(self) -> bool {
+        self.len.value == 0
+    }
+    pub(crate) fn iter(self) -> impl Iterator<Item = StatePartIndex<K>> {
+        (self.start.value..self.end().value).map(|value| StatePartIndex {
+            value,
+            _phantom: PhantomData,
+        })
+    }
+    pub(crate) fn offset(self, offset: StatePartIndex<K>) -> Self {
+        self.end().offset(offset); // check for overflow
+        Self {
+            start: self.start.offset(offset),
+            len: self.len,
+        }
+    }
+    pub(crate) fn slice(self, index: StatePartIndexRange<K>) -> Self {
+        assert!(index.end().value <= self.len.value, "index out of range");
+        Self {
+            start: StatePartIndex {
+                value: self.start.value + index.start.value,
+                _phantom: PhantomData,
+            },
+            len: index.len,
+        }
+    }
+    pub(crate) fn index_array(self, element_size: StatePartLen<K>, index: usize) -> Self {
+        if element_size.value == 0 {
+            assert_eq!(
+                self.len.value, 0,
+                "array with zero-sized element must also be zero-sized",
+            );
+            return self;
+        }
+        assert!(
+            self.len.value % element_size.value == 0,
+            "array's size must be a multiple of its element size",
+        );
+        self.slice(StatePartIndexRange {
+            start: StatePartIndex {
+                value: index
+                    .try_into()
+                    .ok()
+                    .and_then(|index| element_size.value.checked_mul(index))
+                    .expect("index out of range"),
+                _phantom: PhantomData,
+            },
+            len: element_size,
+        })
+    }
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartIndexRange<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "StatePartIndexRange<{}> {{ start: {}, len: {} }}",
+            K::NAME,
+            self.start.value,
+            self.len.value
+        )
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct StatePart<K: StatePartKind> {
+    pub(crate) value: K::State,
+}
+
+impl<K: StatePartKind> StatePart<K> {
+    pub(crate) fn new(layout_data: &[K::LayoutData]) -> Self {
+        Self {
+            value: K::new_state(layout_data),
+        }
+    }
+    pub(crate) fn borrow<'a>(&'a mut self) -> BorrowedStatePart<'a, K> {
+        BorrowedStatePart {
+            value: K::borrow_state(&mut self.value),
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> {
+    pub(crate) value: K::BorrowedState<'a>,
+}
+
+impl<
+        'a,
+        K: StatePartKind<
+            BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T> + BorrowMut<[T]>>,
+        >,
+        T,
+    > BorrowedStatePart<'a, K>
+{
+    pub(crate) fn get_many_mut<const N: usize>(
+        &mut self,
+        indexes: [StatePartIndex<K>; N],
+    ) -> [&mut T; N] {
+        get_many_mut(
+            (*self.value).borrow_mut(),
+            indexes.map(|v| v.value as usize),
+        )
+    }
+}
+
+impl<K: StatePartKind<State: Deref<Target: Index<usize, Output = T>>>, T> Index<StatePartIndex<K>>
+    for StatePart<K>
+{
+    type Output = T;
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.value[index.value as usize]
+    }
+}
+
+impl<K: StatePartKind<State: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for StatePart<K>
+{
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.value[index.value as usize]
+    }
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
+    Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
+    type Output = T;
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.value[index.value as usize]
+    }
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.value[index.value as usize]
+    }
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a> = BorrowedStack<'a, T>>, T: 'a>
+    BorrowedStatePart<'a, K>
+{
+    pub(crate) fn push(&mut self, value: T) {
+        self.value.push(value)
+    }
+    pub(crate) fn pop(&mut self) -> T
+    where
+        T: Default,
+    {
+        self.value.pop()
+    }
+}
+
+#[derive(PartialEq, Eq, Hash, Clone)]
+pub(crate) struct StatePartIndexMap<K: StatePartKind, V> {
+    pub(crate) map: VecMap<V>,
+    _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind, V: fmt::Debug> fmt::Debug for StatePartIndexMap<K, V> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_map().entries(self.iter()).finish()
+    }
+}
+
+impl<K: StatePartKind, V> Extend<(StatePartIndex<K>, V)> for StatePartIndexMap<K, V> {
+    fn extend<T: IntoIterator<Item = (StatePartIndex<K>, V)>>(&mut self, iter: T) {
+        self.map
+            .extend(iter.into_iter().map(|(k, v)| (k.as_usize(), v)));
+    }
+}
+
+impl<K: StatePartKind, V> StatePartIndexMap<K, V> {
+    pub(crate) fn new() -> Self {
+        Self {
+            map: VecMap::new(),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn get(&self, key: StatePartIndex<K>) -> Option<&V> {
+        self.map.get(key.as_usize())
+    }
+    pub(crate) fn get_mut(&mut self, key: StatePartIndex<K>) -> Option<&mut V> {
+        self.map.get_mut(key.as_usize())
+    }
+    pub(crate) fn keys(&self) -> impl Iterator<Item = StatePartIndex<K>> + '_ {
+        self.map.keys().map(|k| StatePartIndex {
+            value: k as u32,
+            _phantom: PhantomData,
+        })
+    }
+    pub(crate) fn values(&self) -> vec_map::Values<'_, V> {
+        self.map.values()
+    }
+    pub(crate) fn values_mut(&mut self) -> vec_map::ValuesMut<'_, V> {
+        self.map.values_mut()
+    }
+    pub(crate) fn iter(&self) -> impl Iterator<Item = (StatePartIndex<K>, &V)> + '_ {
+        self.map.iter().map(|(k, v)| {
+            (
+                StatePartIndex {
+                    value: k as u32,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        })
+    }
+    pub(crate) fn iter_mut(&mut self) -> impl Iterator<Item = (StatePartIndex<K>, &mut V)> + '_ {
+        self.map.iter_mut().map(|(k, v)| {
+            (
+                StatePartIndex {
+                    value: k as u32,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        })
+    }
+    pub(crate) fn len(&self) -> usize {
+        self.map.len()
+    }
+    pub(crate) fn is_empty(&self) -> bool {
+        self.map.is_empty()
+    }
+    pub(crate) fn insert(&mut self, key: StatePartIndex<K>, value: V) -> Option<V> {
+        self.map.insert(key.as_usize(), value)
+    }
+    pub(crate) fn remove(&mut self, key: StatePartIndex<K>) -> Option<V> {
+        self.map.remove(key.as_usize())
+    }
+    pub(crate) fn entry(&mut self, key: StatePartIndex<K>) -> StatePartIndexMapEntry<'_, K, V> {
+        match self.map.entry(key.as_usize()) {
+            vec_map::Entry::Vacant(v) => {
+                StatePartIndexMapEntry::Vacant(StatePartIndexMapVacantEntry(v, PhantomData))
+            }
+            vec_map::Entry::Occupied(v) => {
+                StatePartIndexMapEntry::Occupied(StatePartIndexMapOccupiedEntry(v, PhantomData))
+            }
+        }
+    }
+}
+
+impl<K: StatePartKind, V> Default for StatePartIndexMap<K, V> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl<K: StatePartKind, V> Index<StatePartIndex<K>> for StatePartIndexMap<K, V> {
+    type Output = V;
+
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.map[index.as_usize()]
+    }
+}
+
+impl<K: StatePartKind, V> IndexMut<StatePartIndex<K>> for StatePartIndexMap<K, V> {
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.map[index.as_usize()]
+    }
+}
+
+pub(crate) struct StatePartIndexMapVacantEntry<'a, K: StatePartKind, V>(
+    vec_map::VacantEntry<'a, V>,
+    PhantomData<K>,
+);
+
+pub(crate) struct StatePartIndexMapOccupiedEntry<'a, K: StatePartKind, V>(
+    vec_map::OccupiedEntry<'a, V>,
+    PhantomData<K>,
+);
+
+pub(crate) enum StatePartIndexMapEntry<'a, K: StatePartKind, V> {
+    Vacant(StatePartIndexMapVacantEntry<'a, K, V>),
+    Occupied(StatePartIndexMapOccupiedEntry<'a, K, V>),
+}
+
+impl<'a, K: StatePartKind, V> StatePartIndexMapEntry<'a, K, V> {
+    pub(crate) fn or_insert(self, default: V) -> &'a mut V {
+        match self {
+            StatePartIndexMapEntry::Vacant(v) => v.0.insert(default),
+            StatePartIndexMapEntry::Occupied(v) => v.0.into_mut(),
+        }
+    }
+    pub(crate) fn or_insert_with(self, f: impl FnOnce() -> V) -> &'a mut V {
+        match self {
+            StatePartIndexMapEntry::Vacant(v) => v.0.insert(f()),
+            StatePartIndexMapEntry::Occupied(v) => v.0.into_mut(),
+        }
+    }
+}
+
+impl Insns<InsnsBuilding> {
+    pub(crate) fn new() -> Self {
+        Self {
+            insns: Vec::new(),
+            insn_source_locations: Vec::new(),
+            labels: Labels::default(),
+            state_layout: StateLayout::empty(),
+        }
+    }
+    pub(crate) fn last_insn_pc(&self) -> usize {
+        self.insns
+            .len()
+            .checked_sub(1)
+            .expect("no last instruction")
+    }
+    pub(crate) fn next_insn_pc(&self) -> usize {
+        self.insns.len()
+    }
+    pub(crate) fn push(&mut self, insn: Insn, source_location: SourceLocation) {
+        self.insns.push(insn);
+        self.insn_source_locations.push(source_location);
+    }
+    pub(crate) fn extend<T: Into<InsnOrLabel>>(
+        &mut self,
+        insns_or_labels: impl IntoIterator<Item = T>,
+        source_location: SourceLocation,
+    ) {
+        for insn_or_label in insns_or_labels {
+            match insn_or_label.into() {
+                InsnOrLabel::Insn(insn) => self.push(insn, source_location),
+                InsnOrLabel::Label(label) => self.define_label_at_next_insn(label),
+            }
+        }
+    }
+    pub(crate) fn allocate_variable<BK: InsnsBuildingKind>(
+        &mut self,
+        layout: &TypeLayout<BK>,
+    ) -> TypeIndexRange {
+        self.state_layout.ty.allocate(layout)
+    }
+    pub(crate) fn new_label(&mut self) -> Label {
+        let retval = Label(self.labels.labels.len());
+        self.labels.labels.push(LabelData { address: None });
+        retval
+    }
+    #[track_caller]
+    pub(crate) fn define_label_at_next_insn(&mut self, label: Label) {
+        let address = self.next_insn_pc();
+        let label_data = &mut self.labels.labels[label.0];
+        assert!(label_data.address.is_none(), "label already defined");
+        label_data.address = Some(address);
+        self.labels
+            .address_to_label_map
+            .entry(address)
+            .or_default()
+            .push(label);
+    }
+}
+
+impl From<Insns<InsnsBuilding>> for Insns<InsnsBuildingDone> {
+    fn from(input: Insns<InsnsBuilding>) -> Self {
+        let Insns {
+            mut insns,
+            insn_source_locations,
+            labels,
+            state_layout,
+        } = input;
+        for insn in &mut insns {
+            for field in insn.fields_mut() {
+                match field.kind {
+                    InsnFieldKind::BranchTarget => match field.ty {
+                        InsnFieldType::USize(value) => {
+                            *value = labels.labels[*value]
+                                .address
+                                .expect("label address not set");
+                        }
+                        InsnFieldType::Memory(_)
+                        | InsnFieldType::SmallSlot(_)
+                        | InsnFieldType::BigSlot(_)
+                        | InsnFieldType::SmallSlotArrayIndexed(_)
+                        | InsnFieldType::BigSlotArrayIndexed(_)
+                        | InsnFieldType::SmallUInt(_)
+                        | InsnFieldType::SmallSInt(_)
+                        | InsnFieldType::InternedBigInt(_)
+                        | InsnFieldType::U8(_)
+                        | InsnFieldType::Empty(_) => {
+                            unreachable!()
+                        }
+                    },
+                    InsnFieldKind::Input
+                    | InsnFieldKind::Memory
+                    | InsnFieldKind::Output
+                    | InsnFieldKind::Immediate => {}
+                }
+            }
+        }
+        Insns {
+            insns: Intern::intern_owned(insns),
+            insn_source_locations: Intern::intern_owned(insn_source_locations),
+            labels: (),
+            state_layout: state_layout.into(),
+        }
+    }
+}
+
+impl State {
+    pub(crate) fn setup_call(&mut self, entry_pc: usize) {
+        let Self {
+            insns: _,
+            pc,
+            memory_write_log: _,
+            memories: _,
+            small_slots: _,
+            big_slots: _,
+        } = self;
+        *pc = entry_pc;
+    }
+}
+
+impl BorrowedState<'_> {
+    fn eval_array_indexed<K: StatePartKind>(
+        &self,
+        array_indexed: StatePartArrayIndexed<K>,
+    ) -> Option<StatePartIndex<K>> {
+        let StatePartArrayIndexed {
+            base: mut retval,
+            indexes,
+        } = array_indexed;
+        for StatePartArrayIndex { index, len, stride } in indexes {
+            let index = self.small_slots[index];
+            if index >= len as SmallUInt {
+                return None;
+            }
+            retval.value += stride.value * index as u32;
+        }
+        Some(retval)
+    }
+    fn log_memory_write(&mut self, memory: StatePartIndex<StatePartKindMemories>, addr: SmallUInt) {
+        let Ok(addr) = usize::try_from(addr) else {
+            return;
+        };
+        if addr < self.memories[memory].array_type.len() {
+            let log_entry = (memory, addr);
+            if self.memory_write_log.last().copied() == Some(log_entry) {
+                return;
+            }
+            self.memory_write_log.push(log_entry);
+        }
+    }
+}
+
+impl TypeIndexRange {
+    #[must_use]
+    pub(crate) fn insns_for_copy_to(self, dest: TypeIndexRange) -> impl Iterator<Item = Insn> {
+        assert_eq!(self.len(), dest.len());
+        let Self {
+            small_slots,
+            big_slots,
+        } = self;
+        small_slots
+            .iter()
+            .zip(dest.small_slots.iter())
+            .map(|(src, dest)| Insn::CopySmall { dest, src })
+            .chain(
+                big_slots
+                    .iter()
+                    .zip(dest.big_slots.iter())
+                    .map(|(src, dest)| Insn::Copy { dest, src }),
+            )
+    }
+    #[must_use]
+    pub(crate) fn insns_for_copy_from(self, src: TypeIndexRange) -> impl Iterator<Item = Insn> {
+        src.insns_for_copy_to(self)
+    }
+}
+
+fn bigint_pow2(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            (BigInt::one() << *input).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn bigint_mask(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            ((BigInt::one() << *input) - BigInt::one()).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn bigint_not_mask(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            (-BigInt::one() << *input).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn cast_bigint_to_sint(src: &BigInt, dest_width: usize) -> BigInt {
+    if dest_width == 0 {
+        BigInt::ZERO
+    } else if src.bit((dest_width - 1) as u64) {
+        src | &*bigint_not_mask(dest_width)
+    } else {
+        src & &*bigint_mask(dest_width)
+    }
+}
+
+fn cast_bigint_to_uint(src: &BigInt, dest_width: usize) -> BigInt {
+    src & &*bigint_mask(dest_width)
+}
+
+fn memory_get_mut(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+) -> Option<&mut BitSlice> {
+    let start = usize::try_from(addr)
+        .ok()?
+        .checked_mul(stride)?
+        .checked_add(start)?;
+    memory.get_mut(start..start.checked_add(width)?)
+}
+
+fn memory_read_big<T: BoolOrIntType>(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+) -> Option<BigInt> {
+    let bits = memory_get_mut(memory, addr, stride, start, width)?;
+    Some(T::bits_to_bigint(bits))
+}
+
+fn memory_write_big<T: BoolOrIntType>(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+    value: &BigInt,
+) -> Option<()> {
+    let bits = memory_get_mut(memory, addr, stride, start, width)?;
+    T::copy_bits_from_bigint_wrapping(value, bits);
+    Some(())
+}
+
+impl_insns! {
+    #[insn = Insn, next_macro = next, branch_macro = branch]
+    pub(crate) fn State::run(&mut self) -> () {
+        #[state]
+        let mut state = self.borrow();
+        setup! {}
+        main_loop!();
+        cleanup! {}
+    }
+    Copy {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if dest != src {
+            let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+            dest.clone_from(src);
+        }
+        next!();
+    }
+    CopySmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        state.small_slots[dest] = state.small_slots[src];
+        next!();
+    }
+    ReadIndexed {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartArrayIndexed<StatePartKindBigSlots>,
+    } => {
+        if let Some(src) = state.eval_array_indexed(src) {
+            if dest != src {
+                let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+                dest.clone_from(src);
+            }
+        } else {
+            state.big_slots[dest] = BigInt::ZERO;
+        }
+        next!();
+    }
+    ReadSmallIndexed {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartArrayIndexed<StatePartKindSmallSlots>,
+    } => {
+        if let Some(src) = state.eval_array_indexed(src) {
+            state.small_slots[dest] = state.small_slots[src];
+        } else {
+            state.small_slots[dest] = 0;
+        }
+        next!();
+    }
+    WriteIndexed {
+        #[kind = Output]
+        dest: StatePartArrayIndexed<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if let Some(dest) = state.eval_array_indexed(dest) {
+            if dest != src {
+                let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+                dest.clone_from(src);
+            }
+        }
+        next!();
+    }
+    WriteSmallIndexed {
+        #[kind = Output]
+        dest: StatePartArrayIndexed<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if let Some(dest) = state.eval_array_indexed(dest) {
+            state.small_slots[dest] = state.small_slots[src];
+        }
+        next!();
+    }
+    CastBigToArrayIndex {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let src = &state.big_slots[src];
+        let value = src.try_into().unwrap_or(SmallUInt::MAX);
+        state.small_slots[dest] = value;
+        next!();
+    }
+    IsNonZeroDestIsSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let src = &state.big_slots[src];
+        let value = !src.is_zero();
+        state.small_slots[dest] = value as SmallUInt;
+        next!();
+    }
+    CastToSInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
+    } => {
+        let value = cast_bigint_to_sint(&state.big_slots[src], dest_width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CastToUInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
+    } => {
+        let value = cast_bigint_to_uint(&state.big_slots[src], dest_width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    And {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] & &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    AndSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = state.small_slots[lhs] & state.small_slots[rhs];
+        state.small_slots[dest] = value;
+        next!();
+    }
+    AndSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let value = state.small_slots[lhs] & rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
+    AndBigWithSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let mut lhs_lsb64 = lhs.iter_u64_digits().next().unwrap_or(0);
+        if lhs.is_negative() {
+            lhs_lsb64 = lhs_lsb64.wrapping_neg();
+        }
+        let value = lhs_lsb64 & rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
+    Or {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] | &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Xor {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] ^ &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    XorSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let value = state.small_slots[lhs] ^ rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
+    NotS {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = !&state.big_slots[src];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    NotU {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let value = &state.big_slots[src] ^ &*bigint_mask(width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Neg {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = -&state.big_slots[src];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Add {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] + &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    SubS {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] - &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    SubU {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
+    } => {
+        let mut value = &state.big_slots[lhs] - &state.big_slots[rhs];
+        value &= &*bigint_mask(dest_width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Mul {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] * &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Div {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = state.big_slots[lhs].checked_div(&state.big_slots[rhs]).unwrap_or(BigInt::ZERO);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Rem {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        // no checked_rem?!
+        let value = if state.big_slots[rhs].is_zero() {
+            BigInt::ZERO
+        } else {
+            &state.big_slots[lhs] % &state.big_slots[rhs]
+        };
+        state.big_slots[dest] = value;
+        next!();
+    }
+    DynShl {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] << state.big_slots[rhs].to_usize().expect("shl by invalid value");
+        state.big_slots[dest] = value;
+        next!();
+    }
+    DynShr {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        assert!(!state.big_slots[rhs].is_negative(), "shr by invalid value");
+        let value = state.big_slots[rhs].to_usize().map_or(BigInt::ZERO, |rhs| &state.big_slots[lhs] >> rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Shl {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: usize,
+    } => {
+        let value = &state.big_slots[lhs] << rhs;
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Shr {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: usize,
+    } => {
+        let value = &state.big_slots[lhs] >> rhs;
+        state.big_slots[dest] = value;
+        next!();
+    }
+    SliceInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        len: usize,
+    } => {
+        let value = &state.big_slots[src] >> start;
+        state.big_slots[dest] = value & &*bigint_mask(len);
+        next!();
+    }
+    CmpEq {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs == rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpNe {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs != rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpLt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs < rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpLe {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs <= rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    ReduceBitXor {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        input_width: usize,
+    } => {
+        let src = &state.big_slots[src];
+        let src = src & &*bigint_mask(input_width);
+        let value = BigInt::from(
+            src.to_biguint().expect("known to be non-negative").count_ones() % 2,
+        );
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Const {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        value: Interned<BigInt>,
+    } => {
+        state.big_slots[dest].clone_from(&value);
+        next!();
+    }
+    ConstSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        value: SmallUInt,
+    } => {
+        state.small_slots[dest] = value;
+        next!();
+    }
+    Branch {
+        #[kind = BranchTarget]
+        target: usize,
+    } => {
+        branch!(target);
+    }
+    BranchIfZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if state.big_slots[value].is_zero() {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
+    BranchIfNonZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if state.big_slots[value].is_zero() {
+            next!();
+        } else {
+            branch!(target);
+        }
+    }
+    BranchIfSmallZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if state.small_slots[value] == 0 {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
+    BranchIfSmallNonZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if state.small_slots[value] == 0 {
+            next!();
+        } else {
+            branch!(target);
+        }
+    }
+    BranchIfSmallNeImmediate {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        if state.small_slots[lhs] != rhs {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
+    MemoryReadUInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
+        next!();
+    }
+    MemoryReadSInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
+        next!();
+    }
+    MemoryWriteUInt {
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        memory_write_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
+        state.log_memory_write(memory, addr);
+        next!();
+    }
+    MemoryWriteSInt {
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        memory_write_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
+        state.log_memory_write(memory, addr);
+        next!();
+    }
+    Return => {
+        break RunResult::Return(());
+    }
+}
diff --git a/crates/fayalite/src/sim/time.rs b/crates/fayalite/src/sim/time.rs
new file mode 100644
index 0000000..7c85d8f
--- /dev/null
+++ b/crates/fayalite/src/sim/time.rs
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use std::{
+    fmt,
+    ops::{Add, AddAssign, Sub, SubAssign},
+    time::Duration,
+};
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
+pub struct SimInstant {
+    time_since_start: SimDuration,
+}
+
+impl SimInstant {
+    pub const fn checked_add(self, duration: SimDuration) -> Option<Self> {
+        let Some(time_since_start) = self.time_since_start.checked_add(duration) else {
+            return None;
+        };
+        Some(SimInstant { time_since_start })
+    }
+    pub const fn checked_duration_since(self, earlier: Self) -> Option<SimDuration> {
+        self.time_since_start.checked_sub(earlier.time_since_start)
+    }
+    pub const fn checked_sub(self, duration: SimDuration) -> Option<Self> {
+        let Some(time_since_start) = self.time_since_start.checked_sub(duration) else {
+            return None;
+        };
+        Some(SimInstant { time_since_start })
+    }
+    #[track_caller]
+    pub const fn duration_since(self, earlier: Self) -> SimDuration {
+        let Some(retval) = self.checked_duration_since(earlier) else {
+            panic!(
+                "tried to compute the duration since a later time -- durations can't be negative"
+            );
+        };
+        retval
+    }
+    pub const fn saturating_duration_since(self, earlier: Self) -> SimDuration {
+        let Some(retval) = self.checked_duration_since(earlier) else {
+            return SimDuration::ZERO;
+        };
+        retval
+    }
+}
+
+impl Add<SimDuration> for SimInstant {
+    type Output = SimInstant;
+
+    #[track_caller]
+    fn add(mut self, rhs: SimDuration) -> Self::Output {
+        self += rhs;
+        self
+    }
+}
+
+impl AddAssign<SimDuration> for SimInstant {
+    #[track_caller]
+    fn add_assign(&mut self, rhs: SimDuration) {
+        self.time_since_start += rhs;
+    }
+}
+
+impl Add<SimInstant> for SimDuration {
+    type Output = SimInstant;
+
+    #[track_caller]
+    fn add(self, rhs: SimInstant) -> Self::Output {
+        rhs.add(self)
+    }
+}
+
+impl Sub for SimInstant {
+    type Output = SimDuration;
+
+    #[track_caller]
+    fn sub(self, rhs: SimInstant) -> Self::Output {
+        self.duration_since(rhs)
+    }
+}
+
+impl Sub<SimDuration> for SimInstant {
+    type Output = SimInstant;
+
+    #[track_caller]
+    fn sub(self, rhs: SimDuration) -> Self::Output {
+        let Some(retval) = self.checked_sub(rhs) else {
+            panic!("SimInstant underflow");
+        };
+        retval
+    }
+}
+
+impl SubAssign<SimDuration> for SimInstant {
+    #[track_caller]
+    fn sub_assign(&mut self, rhs: SimDuration) {
+        *self = *self - rhs;
+    }
+}
+
+impl SimInstant {
+    pub const START: SimInstant = SimInstant {
+        time_since_start: SimDuration::ZERO,
+    };
+}
+
+impl fmt::Debug for SimInstant {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.time_since_start.fmt(f)
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
+pub struct SimDuration {
+    attos: u128,
+}
+
+impl AddAssign for SimDuration {
+    #[track_caller]
+    fn add_assign(&mut self, rhs: SimDuration) {
+        *self = *self + rhs;
+    }
+}
+
+impl Add for SimDuration {
+    type Output = SimDuration;
+
+    #[track_caller]
+    fn add(self, rhs: SimDuration) -> Self::Output {
+        SimDuration {
+            attos: self
+                .attos
+                .checked_add(rhs.attos)
+                .expect("overflow adding durations"),
+        }
+    }
+}
+
+impl Sub for SimDuration {
+    type Output = Self;
+
+    #[track_caller]
+    fn sub(self, rhs: Self) -> Self::Output {
+        SimDuration {
+            attos: self
+                .attos
+                .checked_add(rhs.attos)
+                .expect("underflow subtracting durations -- durations can't be negative"),
+        }
+    }
+}
+
+impl SubAssign for SimDuration {
+    #[track_caller]
+    fn sub_assign(&mut self, rhs: Self) {
+        *self = *self - rhs;
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
+pub struct SimDurationParts {
+    pub attos: u16,
+    pub femtos: u16,
+    pub picos: u16,
+    pub nanos: u16,
+    pub micros: u16,
+    pub millis: u16,
+    pub secs: u128,
+}
+
+macro_rules! impl_duration_units {
+    (
+        $(
+            #[unit_const = $UNIT:ident, from_units = $from_units:ident, as_units = $as_units:ident, units = $units:ident, suffix = $suffix:literal]
+            const $log10_units_per_sec:ident: u32 = $log10_units_per_sec_value:expr;
+        )*
+    ) => {
+        impl SimDuration {
+            $(
+                const $log10_units_per_sec: u32 = $log10_units_per_sec_value;
+                pub const fn $from_units($units: u128) -> Self {
+                    Self::from_units_helper::<{ Self::$log10_units_per_sec }>($units)
+                }
+                pub const fn $as_units(self) -> u128 {
+                    self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }
+                }
+            )*
+            pub const fn to_parts(mut self) -> SimDurationParts {
+                $(
+                    let $units = self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                    self.attos %= const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                )*
+                SimDurationParts {
+                    $($units: $units as _,)*
+                }
+            }
+            pub const fn from_parts_checked(parts: SimDurationParts) -> Option<Self> {
+                let attos = 0u128;
+                $(
+                    let Some(product) = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }.checked_mul(parts.$units as u128) else {
+                        return None;
+                    };
+                    let Some(attos) = attos.checked_add(product) else {
+                        return None;
+                    };
+                )*
+                Some(Self {
+                    attos,
+                })
+            }
+        }
+
+        impl fmt::Debug for SimDuration {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let ilog10_attos = match self.attos.checked_ilog10() {
+                    Some(v) => v,
+                    None => Self::LOG10_ATTOS_PER_SEC,
+                };
+                let (suffix, int, fraction, fraction_digits) =
+                    match Self::LOG10_ATTOS_PER_SEC.saturating_sub(ilog10_attos) {
+                    $(
+                        ..=Self::$log10_units_per_sec => {
+                            let divisor = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                            (
+                                $suffix,
+                                self.attos / divisor,
+                                self.attos % divisor,
+                                (Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) as usize,
+                            )
+                        },
+                    )*
+                    _ => unreachable!(),
+                };
+                write!(f, "{int}")?;
+                if fraction != 0 {
+                    write!(f, ".{fraction:0fraction_digits$}")?;
+                }
+                write!(f, " {suffix}")
+            }
+        }
+
+        #[cfg(test)]
+        #[test]
+        fn test_duration_debug() {
+            $(
+                assert_eq!(
+                    format!("{:?}", SimDuration::$from_units(123)),
+                    concat!("123 ", $suffix)
+                );
+                assert_eq!(
+                    format!("{:?}", SimDuration::$from_units(1)),
+                    concat!("1 ", $suffix),
+                );
+                let mut v = SimDuration::$from_units(1);
+                if v.attos < 1 << 53 {
+                    v.attos += 1;
+                    assert_eq!(
+                        format!("{v:?}"),
+                        format!("{} {}", v.attos as f64 / 10.0f64.powf((SimDuration::LOG10_ATTOS_PER_SEC - SimDuration::$log10_units_per_sec) as f64), $suffix),
+                        "1 {} + 1 as == {} as", $suffix, v.attos,
+                    );
+                }
+            )*
+        }
+    };
+}
+
+impl_duration_units! {
+    #[unit_const = SECOND, from_units = from_secs, as_units = as_secs, units = secs, suffix = "s"]
+    const LOG10_SECS_PER_SEC: u32 = 0;
+    #[unit_const = MILLISECOND, from_units = from_millis, as_units = as_millis, units = millis, suffix = "ms"]
+    const LOG10_MILLIS_PER_SEC: u32 = 3;
+    #[unit_const = MICROSECOND, from_units = from_micros, as_units = as_micros, units = micros, suffix = "μs"]
+    const LOG10_MICROS_PER_SEC: u32 = 6;
+    #[unit_const = NANOSECOND, from_units = from_nanos, as_units = as_nanos, units = nanos, suffix = "ns"]
+    const LOG10_NANOS_PER_SEC: u32 = 9;
+    #[unit_const = PICOSECOND, from_units = from_picos, as_units = as_picos, units = picos, suffix = "ps"]
+    const LOG10_PICOS_PER_SEC: u32 = 12;
+    #[unit_const = FEMTOSECOND, from_units = from_femtos, as_units = as_femtos, units = femtos, suffix = "fs"]
+    const LOG10_FEMTOS_PER_SEC: u32 = 15;
+    #[unit_const = ATTOSECOND, from_units = from_attos, as_units = as_attos, units = attos, suffix = "as"]
+    const LOG10_ATTOS_PER_SEC: u32 = 18;
+}
+
+impl SimDuration {
+    const fn from_units_helper<const UNITS_PER_SEC: u32>(units: u128) -> Self {
+        let Some(attos) =
+            units.checked_mul(const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - UNITS_PER_SEC) })
+        else {
+            panic!("duration too big");
+        };
+        Self { attos }
+    }
+    pub const ZERO: SimDuration = SimDuration::from_secs(0);
+    pub const fn from_parts(parts: SimDurationParts) -> Self {
+        match Self::from_parts_checked(parts) {
+            Some(v) => v,
+            None => panic!("duration too big"),
+        }
+    }
+    pub const fn abs_diff(self, other: Self) -> Self {
+        Self {
+            attos: self.attos.abs_diff(other.attos),
+        }
+    }
+    pub const fn checked_add(self, rhs: Self) -> Option<Self> {
+        let Some(attos) = self.attos.checked_add(rhs.attos) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
+        let Some(attos) = self.attos.checked_sub(rhs.attos) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    pub const fn is_zero(self) -> bool {
+        self.attos == 0
+    }
+    pub const fn saturating_add(self, rhs: Self) -> Self {
+        Self {
+            attos: self.attos.saturating_add(rhs.attos),
+        }
+    }
+    pub const fn saturating_sub(self, rhs: Self) -> Self {
+        Self {
+            attos: self.attos.saturating_sub(rhs.attos),
+        }
+    }
+    pub const fn checked_ilog10(self) -> Option<i32> {
+        let Some(ilog10_attos) = self.attos.checked_ilog10() else {
+            return None;
+        };
+        Some(ilog10_attos as i32 - Self::LOG10_ATTOS_PER_SEC as i32)
+    }
+    #[track_caller]
+    pub const fn ilog10(self) -> i32 {
+        let Some(retval) = self.checked_ilog10() else {
+            panic!("tried to take the ilog10 of 0");
+        };
+        retval
+    }
+    pub const fn checked_pow10(log10: i32, underflow_is_zero: bool) -> Option<Self> {
+        let Some(log10) = Self::LOG10_ATTOS_PER_SEC.checked_add_signed(log10) else {
+            return if log10 < 0 && underflow_is_zero {
+                Some(Self::ZERO)
+            } else {
+                None
+            };
+        };
+        let Some(attos) = 10u128.checked_pow(log10) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    #[track_caller]
+    pub const fn pow10(log10: i32) -> Self {
+        let Some(retval) = Self::checked_pow10(log10, true) else {
+            panic!("pow10 overflowed");
+        };
+        retval
+    }
+    pub const fn is_power_of_ten(self) -> bool {
+        const TEN: u128 = 10;
+        const NUMBER_OF_POWERS_OF_TEN: usize = {
+            let mut n = 0;
+            while let Some(_) = TEN.checked_pow(n as u32) {
+                n += 1;
+            }
+            n
+        };
+        const POWERS_OF_TEN: [u128; NUMBER_OF_POWERS_OF_TEN] = {
+            let mut retval = [0; NUMBER_OF_POWERS_OF_TEN];
+            let mut i = 0;
+            while i < NUMBER_OF_POWERS_OF_TEN {
+                retval[i] = TEN.pow(i as u32);
+                i += 1;
+            }
+            retval
+        };
+        let mut i = 0;
+        while i < NUMBER_OF_POWERS_OF_TEN {
+            if self.attos == POWERS_OF_TEN[i] {
+                return true;
+            }
+            i += 1;
+        }
+        false
+    }
+}
+
+impl From<Duration> for SimDuration {
+    fn from(duration: Duration) -> Self {
+        Self::from_nanos(duration.as_nanos())
+    }
+}
diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
new file mode 100644
index 0000000..8dace78
--- /dev/null
+++ b/crates/fayalite/src/sim/value.rs
@@ -0,0 +1,913 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    array::{Array, ArrayType},
+    bundle::{Bundle, BundleType},
+    clock::Clock,
+    enum_::{Enum, EnumType},
+    expr::{CastBitsTo, Expr, ToExpr},
+    int::{Bool, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
+    reset::{AsyncReset, Reset, SyncReset},
+    ty::{CanonicalType, StaticType, Type},
+    util::{
+        alternating_cell::{AlternatingCell, AlternatingCellMethods},
+        ConstUsize,
+    },
+};
+use bitvec::{slice::BitSlice, vec::BitVec};
+use serde::{Deserialize, Deserializer, Serialize, Serializer};
+use std::{
+    fmt,
+    ops::{Deref, DerefMut},
+    sync::Arc,
+};
+
+#[derive(Copy, Clone, Eq, PartialEq)]
+enum ValidFlags {
+    BothValid = 0,
+    OnlyValueValid = 1,
+    OnlyBitsValid = 2,
+}
+
+#[derive(Clone)]
+struct SimValueInner<T: Type> {
+    value: T::SimValue,
+    bits: UIntValue,
+    valid_flags: ValidFlags,
+    ty: T,
+}
+
+impl<T: Type> SimValueInner<T> {
+    fn fill_bits(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid | ValidFlags::OnlyBitsValid => {}
+            ValidFlags::OnlyValueValid => {
+                self.ty.sim_value_to_bits(&self.value, self.bits.bits_mut());
+                self.valid_flags = ValidFlags::BothValid;
+            }
+        }
+    }
+    fn into_bits(mut self) -> UIntValue {
+        self.fill_bits();
+        self.bits
+    }
+    fn bits_mut(&mut self) -> &mut UIntValue {
+        self.fill_bits();
+        self.valid_flags = ValidFlags::OnlyBitsValid;
+        &mut self.bits
+    }
+    fn fill_value(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid | ValidFlags::OnlyValueValid => {}
+            ValidFlags::OnlyBitsValid => {
+                self.ty
+                    .sim_value_clone_from_bits(&mut self.value, self.bits.bits());
+                self.valid_flags = ValidFlags::BothValid;
+            }
+        }
+    }
+    fn into_value(mut self) -> T::SimValue {
+        self.fill_value();
+        self.value
+    }
+    fn value_mut(&mut self) -> &mut T::SimValue {
+        self.fill_value();
+        self.valid_flags = ValidFlags::OnlyValueValid;
+        &mut self.value
+    }
+}
+
+impl<T: Type> AlternatingCellMethods for SimValueInner<T> {
+    fn unique_to_shared(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid => return,
+            ValidFlags::OnlyValueValid => {
+                self.ty.sim_value_to_bits(&self.value, self.bits.bits_mut())
+            }
+            ValidFlags::OnlyBitsValid => self
+                .ty
+                .sim_value_clone_from_bits(&mut self.value, self.bits.bits()),
+        }
+        self.valid_flags = ValidFlags::BothValid;
+    }
+
+    fn shared_to_unique(&mut self) {}
+}
+
+#[derive(Serialize, Deserialize)]
+#[serde(rename = "SimValue")]
+#[serde(bound(
+    serialize = "T: Type<SimValue: Serialize> + Serialize",
+    deserialize = "T: Type<SimValue: Deserialize<'de>> + Deserialize<'de>"
+))]
+struct SerdeSimValue<'a, T: Type> {
+    ty: T,
+    value: std::borrow::Cow<'a, T::SimValue>,
+}
+
+impl<T: Type<SimValue: Serialize> + Serialize> Serialize for SimValue<T> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeSimValue {
+            ty: SimValue::ty(self),
+            value: std::borrow::Cow::Borrowed(&*self),
+        }
+        .serialize(serializer)
+    }
+}
+
+impl<'de, T: Type<SimValue: Deserialize<'de>> + Deserialize<'de>> Deserialize<'de> for SimValue<T> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let SerdeSimValue { ty, value } = SerdeSimValue::<T>::deserialize(deserializer)?;
+        Ok(SimValue::from_value(ty, value.into_owned()))
+    }
+}
+
+pub struct SimValue<T: Type> {
+    inner: AlternatingCell<SimValueInner<T>>,
+}
+
+impl<T: Type + Clone> Clone for SimValue<T> {
+    fn clone(&self) -> Self {
+        Self {
+            inner: AlternatingCell::new_unique(self.inner.share().clone()),
+        }
+    }
+}
+
+impl<T: Type> SimValue<T> {
+    #[track_caller]
+    pub fn from_bits(ty: T, bits: UIntValue) -> Self {
+        assert_eq!(ty.canonical().bit_width(), bits.width());
+        let inner = SimValueInner {
+            value: ty.sim_value_from_bits(bits.bits()),
+            bits,
+            valid_flags: ValidFlags::BothValid,
+            ty,
+        };
+        Self {
+            inner: AlternatingCell::new_shared(inner),
+        }
+    }
+    #[track_caller]
+    pub fn from_bitslice(ty: T, bits: &BitSlice) -> Self {
+        Self::from_bits(ty, UIntValue::new(Arc::new(bits.to_bitvec())))
+    }
+    pub fn from_value(ty: T, value: T::SimValue) -> Self {
+        let inner = SimValueInner {
+            bits: UIntValue::new_dyn(Arc::new(BitVec::repeat(false, ty.canonical().bit_width()))),
+            value,
+            valid_flags: ValidFlags::OnlyValueValid,
+            ty,
+        };
+        Self {
+            inner: AlternatingCell::new_unique(inner),
+        }
+    }
+    pub fn ty(this: &Self) -> T {
+        this.inner.share().ty
+    }
+    pub fn into_bits(this: Self) -> UIntValue {
+        this.inner.into_inner().into_bits()
+    }
+    pub fn into_ty_and_bits(this: Self) -> (T, UIntValue) {
+        let inner = this.inner.into_inner();
+        (inner.ty, inner.into_bits())
+    }
+    pub fn bits(this: &Self) -> &UIntValue {
+        &this.inner.share().bits
+    }
+    pub fn bits_mut(this: &mut Self) -> &mut UIntValue {
+        this.inner.unique().bits_mut()
+    }
+    pub fn into_value(this: Self) -> T::SimValue {
+        this.inner.into_inner().into_value()
+    }
+    pub fn value(this: &Self) -> &T::SimValue {
+        &this.inner.share().value
+    }
+    pub fn value_mut(this: &mut Self) -> &mut T::SimValue {
+        this.inner.unique().value_mut()
+    }
+    #[track_caller]
+    pub fn from_canonical(v: SimValue<CanonicalType>) -> Self {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        Self::from_bits(T::from_canonical(ty), bits)
+    }
+    pub fn into_canonical(this: Self) -> SimValue<CanonicalType> {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(ty.canonical(), bits)
+    }
+    pub fn canonical(this: &Self) -> SimValue<CanonicalType> {
+        SimValue::from_bits(Self::ty(this).canonical(), Self::bits(this).clone())
+    }
+    #[track_caller]
+    pub fn from_dyn_int(v: SimValue<T::Dyn>) -> Self
+    where
+        T: IntType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_dyn_int(ty), bits)
+    }
+    pub fn into_dyn_int(this: Self) -> SimValue<T::Dyn>
+    where
+        T: IntType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(ty.as_dyn_int(), bits)
+    }
+    pub fn to_dyn_int(this: &Self) -> SimValue<T::Dyn>
+    where
+        T: IntType,
+    {
+        SimValue::from_bits(Self::ty(this).as_dyn_int(), Self::bits(&this).clone())
+    }
+    #[track_caller]
+    pub fn from_bundle(v: SimValue<Bundle>) -> Self
+    where
+        T: BundleType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_canonical(CanonicalType::Bundle(ty)), bits)
+    }
+    pub fn into_bundle(this: Self) -> SimValue<Bundle>
+    where
+        T: BundleType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(Bundle::from_canonical(ty.canonical()), bits)
+    }
+    pub fn to_bundle(this: &Self) -> SimValue<Bundle>
+    where
+        T: BundleType,
+    {
+        SimValue::from_bits(
+            Bundle::from_canonical(Self::ty(this).canonical()),
+            Self::bits(&this).clone(),
+        )
+    }
+    #[track_caller]
+    pub fn from_enum(v: SimValue<Enum>) -> Self
+    where
+        T: EnumType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_canonical(CanonicalType::Enum(ty)), bits)
+    }
+    pub fn into_enum(this: Self) -> SimValue<Enum>
+    where
+        T: EnumType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(Enum::from_canonical(ty.canonical()), bits)
+    }
+    pub fn to_enum(this: &Self) -> SimValue<Enum>
+    where
+        T: EnumType,
+    {
+        SimValue::from_bits(
+            Enum::from_canonical(Self::ty(this).canonical()),
+            Self::bits(&this).clone(),
+        )
+    }
+}
+
+impl<T: Type> Deref for SimValue<T> {
+    type Target = T::SimValue;
+
+    fn deref(&self) -> &Self::Target {
+        Self::value(self)
+    }
+}
+
+impl<T: Type> DerefMut for SimValue<T> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        Self::value_mut(self)
+    }
+}
+
+impl<T: Type> fmt::Debug for SimValue<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let inner = self.inner.share();
+        f.debug_struct("SimValue")
+            .field("ty", &inner.ty)
+            .field("value", &inner.value)
+            .finish()
+    }
+}
+
+impl<T: Type> ToExpr for SimValue<T> {
+    type Type = T;
+
+    #[track_caller]
+    fn to_expr(&self) -> Expr<Self::Type> {
+        let inner = self.inner.share();
+        inner.bits.cast_bits_to(inner.ty)
+    }
+}
+
+pub trait SimValuePartialEq<T: Type = Self>: Type {
+    #[track_caller]
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<T>) -> bool;
+}
+
+impl<T: SimValuePartialEq<U>, U: Type> PartialEq<SimValue<U>> for SimValue<T> {
+    #[track_caller]
+    fn eq(&self, other: &SimValue<U>) -> bool {
+        T::sim_value_eq(self, other)
+    }
+}
+
+impl<Width: Size> SimValuePartialEq<Self> for UIntType<Width> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        **this == **other
+    }
+}
+
+impl<Width: Size> SimValuePartialEq<Self> for SIntType<Width> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        **this == **other
+    }
+}
+
+impl SimValuePartialEq<Bool> for Bool {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Bool>) -> bool {
+        **this == **other
+    }
+}
+
+pub trait ToSimValue: ToSimValueWithType<<Self as ToSimValue>::Type> {
+    type Type: Type;
+
+    #[track_caller]
+    fn to_sim_value(&self) -> SimValue<Self::Type>;
+    #[track_caller]
+    fn into_sim_value(self) -> SimValue<Self::Type>
+    where
+        Self: Sized,
+    {
+        self.to_sim_value()
+    }
+    #[track_caller]
+    fn arc_into_sim_value(self: Arc<Self>) -> SimValue<Self::Type> {
+        self.to_sim_value()
+    }
+    #[track_caller]
+    fn arc_to_sim_value(self: &Arc<Self>) -> SimValue<Self::Type> {
+        self.to_sim_value()
+    }
+}
+
+pub trait ToSimValueWithType<T: Type> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T>;
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T>
+    where
+        Self: Sized,
+    {
+        self.to_sim_value_with_type(ty)
+    }
+    #[track_caller]
+    fn arc_into_sim_value_with_type(self: Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value_with_type(ty)
+    }
+    #[track_caller]
+    fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value_with_type(ty)
+    }
+}
+
+macro_rules! forward_to_sim_value_with_type {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<$($generics)*> ToSimValueWithType<<Self as ToSimValue>::Type> for $ty {
+            fn to_sim_value_with_type(&self, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::to_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type>
+            where
+                Self: Sized,
+            {
+                let retval = Self::into_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn arc_into_sim_value_with_type(self: Arc<Self>, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::arc_into_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::arc_to_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+        }
+    };
+}
+
+impl<T: Type> ToSimValue for SimValue<T> {
+    type Type = T;
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        self.clone()
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        self
+    }
+}
+
+forward_to_sim_value_with_type!([T: Type] SimValue<T>);
+
+impl<T: Type> ToSimValueWithType<T> for BitVec {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value_with_type(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        Arc::new(self).arc_into_sim_value_with_type(ty)
+    }
+
+    #[track_caller]
+    fn arc_into_sim_value_with_type(self: Arc<Self>, ty: T) -> SimValue<T> {
+        SimValue::from_bits(ty, UIntValue::new_dyn(self))
+    }
+
+    #[track_caller]
+    fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: T) -> SimValue<T> {
+        SimValue::from_bits(ty, UIntValue::new_dyn(self.clone()))
+    }
+}
+
+impl<T: Type> ToSimValueWithType<T> for bitvec::boxed::BitBox {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value_with_type(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        self.into_bitvec().into_sim_value_with_type(ty)
+    }
+}
+
+impl<T: Type> ToSimValueWithType<T> for BitSlice {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.to_bitvec().into_sim_value_with_type(ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue> ToSimValue for &'_ This {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
+    }
+}
+
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for &'_ This {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue> ToSimValue for &'_ mut This {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
+    }
+}
+
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for &'_ mut This {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue> ToSimValue for Arc<This> {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::arc_to_sim_value(self)
+    }
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        This::arc_into_sim_value(self)
+    }
+}
+
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for Arc<This> {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::arc_to_sim_value_with_type(self, ty)
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        This::arc_into_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue + Send + Sync + 'static> ToSimValue
+    for crate::intern::Interned<This>
+{
+    type Type = This::Type;
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
+    }
+}
+
+impl<This: ?Sized + ToSimValueWithType<T> + Send + Sync + 'static, T: Type> ToSimValueWithType<T>
+    for crate::intern::Interned<This>
+{
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ToSimValue> ToSimValue for Box<This> {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
+    }
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        This::into_sim_value(*self)
+    }
+}
+
+impl<This: ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for Box<This> {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        This::into_sim_value_with_type(*self, ty)
+    }
+}
+
+impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
+    #[track_caller]
+    pub fn from_array_elements<I: IntoIterator<Item: ToSimValueWithType<T>>>(
+        ty: ArrayType<T, Len>,
+        elements: I,
+    ) -> Self {
+        let element_ty = ty.element();
+        let elements = Vec::from_iter(
+            elements
+                .into_iter()
+                .map(|element| element.into_sim_value_with_type(element_ty)),
+        );
+        assert_eq!(elements.len(), ty.len());
+        SimValue::from_value(ty, elements.try_into().ok().expect("already checked len"))
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for [Element] {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for [Element] {
+    type Type = Array<Element::Type>;
+
+    #[track_caller]
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType> for [Element] {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type, const N: usize> ToSimValueWithType<Array<T, N>>
+    for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>, const N: usize> ToSimValue for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    type Type = Array<Element::Type, N>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(StaticType::TYPE, self)
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(StaticType::TYPE, self)
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type, const N: usize> ToSimValueWithType<Array<T>>
+    for [Element; N]
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>, const N: usize> ToSimValueWithType<CanonicalType>
+    for [Element; N]
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for Vec<Element> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for Vec<Element> {
+    type Type = Array<Element::Type>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType>
+    for Vec<Element>
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for Box<[Element]> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for Box<[Element]> {
+    type Type = Array<Element::Type>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType>
+    for Box<[Element]>
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<T: Type> ToSimValue for Expr<T> {
+    type Type = T;
+    #[track_caller]
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_bitslice(
+            Expr::ty(*self),
+            &crate::expr::ToLiteralBits::to_literal_bits(self)
+                .expect("must be a literal expression"),
+        )
+    }
+}
+
+forward_to_sim_value_with_type!([T: Type] Expr<T>);
+
+macro_rules! impl_to_sim_value_for_bool_like {
+    ($ty:ident) => {
+        impl ToSimValueWithType<$ty> for bool {
+            fn to_sim_value_with_type(&self, ty: $ty) -> SimValue<$ty> {
+                SimValue::from_value(ty, *self)
+            }
+        }
+    };
+}
+
+impl ToSimValue for bool {
+    type Type = Bool;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_value(Bool, *self)
+    }
+}
+
+impl_to_sim_value_for_bool_like!(Bool);
+impl_to_sim_value_for_bool_like!(AsyncReset);
+impl_to_sim_value_for_bool_like!(SyncReset);
+impl_to_sim_value_for_bool_like!(Reset);
+impl_to_sim_value_for_bool_like!(Clock);
+
+impl ToSimValueWithType<CanonicalType> for bool {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        match ty {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Array(_)
+            | CanonicalType::Enum(_)
+            | CanonicalType::Bundle(_)
+            | CanonicalType::PhantomConst(_) => {
+                panic!("can't create SimValue from bool: expected value of type: {ty:?}");
+            }
+            CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => {
+                SimValue::from_bits(ty, UIntValue::new(Arc::new(BitVec::repeat(*self, 1))))
+            }
+        }
+    }
+}
+
+macro_rules! impl_to_sim_value_for_primitive_int {
+    ($prim:ident) => {
+        impl ToSimValue for $prim {
+            type Type = <$prim as ToExpr>::Type;
+
+            #[track_caller]
+            fn to_sim_value(
+                &self,
+            ) -> SimValue<Self::Type> {
+                SimValue::from_value(StaticType::TYPE, (*self).into())
+            }
+        }
+
+        forward_to_sim_value_with_type!([] $prim);
+
+        impl ToSimValueWithType<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
+            #[track_caller]
+            fn to_sim_value_with_type(
+                &self,
+                ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
+            ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
+                SimValue::from_value(
+                    ty,
+                    <<$prim as ToExpr>::Type as Type>::SimValue::from(*self).as_dyn_int(),
+                )
+            }
+        }
+
+        impl ToSimValueWithType<CanonicalType> for $prim {
+            #[track_caller]
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
+                SimValue::into_canonical(self.to_sim_value_with_type(ty))
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_primitive_int!(u8);
+impl_to_sim_value_for_primitive_int!(u16);
+impl_to_sim_value_for_primitive_int!(u32);
+impl_to_sim_value_for_primitive_int!(u64);
+impl_to_sim_value_for_primitive_int!(u128);
+impl_to_sim_value_for_primitive_int!(usize);
+impl_to_sim_value_for_primitive_int!(i8);
+impl_to_sim_value_for_primitive_int!(i16);
+impl_to_sim_value_for_primitive_int!(i32);
+impl_to_sim_value_for_primitive_int!(i64);
+impl_to_sim_value_for_primitive_int!(i128);
+impl_to_sim_value_for_primitive_int!(isize);
+
+macro_rules! impl_to_sim_value_for_int_value {
+    ($IntValue:ident, $Int:ident, $IntType:ident) => {
+        impl<Width: Size> ToSimValue for $IntValue<Width> {
+            type Type = $IntType<Width>;
+
+            fn to_sim_value(&self) -> SimValue<Self::Type> {
+                SimValue::from_value(self.ty(), self.clone())
+            }
+
+            fn into_sim_value(self) -> SimValue<Self::Type> {
+                SimValue::from_value(self.ty(), self)
+            }
+        }
+
+        impl<Width: Size> ToSimValueWithType<$IntType<Width>> for $IntValue<Width> {
+            fn to_sim_value_with_type(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                SimValue::from_value(ty, self.clone())
+            }
+
+            fn into_sim_value_with_type(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                SimValue::from_value(ty, self)
+            }
+        }
+
+        impl<Width: KnownSize> ToSimValueWithType<$Int> for $IntValue<Width> {
+            fn to_sim_value_with_type(&self, ty: $Int) -> SimValue<$Int> {
+                self.bits().to_sim_value_with_type(ty)
+            }
+
+            fn into_sim_value_with_type(self, ty: $Int) -> SimValue<$Int> {
+                self.into_bits().into_sim_value_with_type(ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValueWithType<CanonicalType> for $IntValue<Width> {
+            #[track_caller]
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(
+                    self.to_sim_value_with_type($IntType::<Width>::from_canonical(ty)),
+                )
+            }
+
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(
+                    self.into_sim_value_with_type($IntType::<Width>::from_canonical(ty)),
+                )
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
+impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
new file mode 100644
index 0000000..fcf6743
--- /dev/null
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    enum_::{Enum, EnumType},
+    expr::Flow,
+    int::UInt,
+    intern::{Intern, Interned},
+    sim::{
+        time::{SimDuration, SimInstant},
+        TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
+        TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
+        TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule,
+        TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSyncReset,
+        TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
+    },
+    util::HashMap,
+};
+use bitvec::{order::Lsb0, slice::BitSlice};
+use hashbrown::hash_map::Entry;
+use std::{
+    fmt::{self, Write as _},
+    io, mem,
+};
+
+#[derive(Default)]
+struct Scope {
+    last_inserted: HashMap<Interned<str>, usize>,
+}
+
+#[derive(Copy, Clone)]
+struct VerilogIdentifier {
+    unescaped_name: Interned<str>,
+}
+
+impl VerilogIdentifier {
+    fn needs_escape(self) -> bool {
+        // we only allow ascii, so we can just check bytes
+        let Some((&first, rest)) = self.unescaped_name.as_bytes().split_first() else {
+            unreachable!("Scope::new_identifier guarantees a non-empty name");
+        };
+        if !first.is_ascii_alphabetic() && first != b'_' {
+            true
+        } else {
+            rest.iter()
+                .any(|&ch| !ch.is_ascii_alphanumeric() && ch != b'_' && ch != b'$')
+        }
+    }
+}
+
+impl fmt::Display for VerilogIdentifier {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if self.needs_escape() {
+            f.write_str("\\")?;
+        }
+        write!(f, "{}", Escaped(self.unescaped_name))
+    }
+}
+
+impl Scope {
+    fn new_identifier(&mut self, unescaped_name: Interned<str>) -> VerilogIdentifier {
+        let next_disambiguator = match self.last_inserted.entry(unescaped_name) {
+            Entry::Vacant(entry) => {
+                entry.insert(1);
+                return VerilogIdentifier { unescaped_name };
+            }
+            Entry::Occupied(entry) => entry.get() + 1,
+        };
+        let mut disambiguated_name = String::from(&*unescaped_name);
+        for disambiguator in next_disambiguator.. {
+            disambiguated_name.truncate(unescaped_name.len());
+            write!(disambiguated_name, "_{disambiguator}").expect("can't fail");
+            if let Entry::Vacant(entry) = self.last_inserted.entry((*disambiguated_name).intern()) {
+                let retval = VerilogIdentifier {
+                    unescaped_name: *entry.key(),
+                };
+                entry.insert(1);
+                // speed up future searches
+                self.last_inserted.insert(unescaped_name, disambiguator);
+                return retval;
+            }
+        }
+        panic!("too many names");
+    }
+}
+
+pub struct VcdWriterDecls<W: io::Write + 'static> {
+    writer: W,
+    timescale: SimDuration,
+}
+
+impl<W: io::Write + 'static> VcdWriterDecls<W> {
+    pub fn new(writer: W) -> Self {
+        Self {
+            writer,
+            timescale: SimDuration::from_picos(1),
+        }
+    }
+    pub fn timescale(&self) -> SimDuration {
+        self.timescale
+    }
+    #[track_caller]
+    pub fn with_timescale(mut self, timescale: SimDuration) -> Self {
+        // check timescale validity
+        vcd_timescale(timescale);
+        self.timescale = timescale;
+        self
+    }
+}
+
+#[track_caller]
+const fn vcd_timescale(timescale: SimDuration) -> &'static str {
+    if !timescale.is_power_of_ten() {
+        panic!("VCD timescale must be a power of 10");
+    }
+    macro_rules! timescales {
+        ($($const_name:ident = ($dur:expr, $text:literal),)*) => {
+            $(const $const_name: SimDuration = $dur;)*
+            match timescale {
+                $($const_name => $text,)*
+                _ => panic!("VCD timescale is too big"),
+            }
+        };
+    }
+    timescales! {
+        TIMESCALE_1_AS = (SimDuration::from_attos(1), "1 as"),
+        TIMESCALE_10_AS = (SimDuration::from_attos(10), "10 as"),
+        TIMESCALE_100_AS = (SimDuration::from_attos(100), "100 as"),
+        TIMESCALE_1_FS = (SimDuration::from_femtos(1), "1 fs"),
+        TIMESCALE_10_FS = (SimDuration::from_femtos(10), "10 fs"),
+        TIMESCALE_100_FS = (SimDuration::from_femtos(100), "100 fs"),
+        TIMESCALE_1_PS = (SimDuration::from_picos(1), "1 ps"),
+        TIMESCALE_10_PS = (SimDuration::from_picos(10), "10 ps"),
+        TIMESCALE_100_PS = (SimDuration::from_picos(100), "100 ps"),
+        TIMESCALE_1_NS = (SimDuration::from_nanos(1), "1 ns"),
+        TIMESCALE_10_NS = (SimDuration::from_nanos(10), "10 ns"),
+        TIMESCALE_100_NS = (SimDuration::from_nanos(100), "100 ns"),
+        TIMESCALE_1_US = (SimDuration::from_micros(1), "1 us"),
+        TIMESCALE_10_US = (SimDuration::from_micros(10), "10 us"),
+        TIMESCALE_100_US = (SimDuration::from_micros(100), "100 us"),
+        TIMESCALE_1_MS = (SimDuration::from_millis(1), "1 ms"),
+        TIMESCALE_10_MS = (SimDuration::from_millis(10), "10 ms"),
+        TIMESCALE_100_MS = (SimDuration::from_millis(100), "100 ms"),
+        TIMESCALE_1_S = (SimDuration::from_secs(1), "1 s"),
+        TIMESCALE_10_S = (SimDuration::from_secs(10), "10 s"),
+        TIMESCALE_100_S = (SimDuration::from_secs(100), "100 s"),
+        TIMESCALE_1000_S = (SimDuration::from_secs(1000), "1000 s"),
+    }
+}
+
+impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            writer: _,
+            timescale,
+        } = self;
+        f.debug_struct("VcdWriterDecls")
+            .field("timescale", timescale)
+            .finish_non_exhaustive()
+    }
+}
+
+/// pass in scope to ensure it's not available in child scope
+fn write_vcd_scope<W: io::Write, R>(
+    writer: &mut W,
+    scope_type: &str,
+    scope_name: Interned<str>,
+    scope: &mut Scope,
+    f: impl FnOnce(&mut W, &mut Scope) -> io::Result<R>,
+) -> io::Result<R> {
+    writeln!(
+        writer,
+        "$scope {scope_type} {} $end",
+        scope.new_identifier(scope_name),
+    )?;
+    let retval = f(writer, &mut Scope::default())?;
+    writeln!(writer, "$upscope $end")?;
+    Ok(retval)
+}
+
+macro_rules! trait_arg {
+    (
+        trait $Arg:ident {
+            $(
+                fn $fn:ident(&mut self) -> $ty:ty;
+            )*
+        }
+    ) => {
+        trait $Arg: Sized {
+            $(fn $fn(&mut self) -> $ty {
+                unreachable!()
+            })*
+        }
+
+        $(
+            impl $Arg for $ty {
+                fn $fn(&mut self) -> $ty {
+                    self.reborrow()
+                }
+            }
+        )*
+    };
+}
+
+trait_arg! {
+    trait Arg {
+        fn module(&mut self) -> ArgModule<'_>;
+        fn module_body(&mut self) -> ArgModuleBody<'_>;
+        fn in_type(&mut self) -> ArgInType<'_>;
+    }
+}
+
+struct ArgModule<'a> {
+    properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
+}
+
+impl<'a> ArgModule<'a> {
+    fn reborrow(&mut self) -> ArgModule<'_> {
+        ArgModule {
+            properties: self.properties,
+            scope: self.scope,
+        }
+    }
+}
+
+struct ArgModuleBody<'a> {
+    properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
+}
+
+impl<'a> ArgModuleBody<'a> {
+    fn reborrow(&mut self) -> ArgModuleBody<'_> {
+        ArgModuleBody {
+            properties: self.properties,
+            scope: self.scope,
+        }
+    }
+}
+
+struct ArgInType<'a> {
+    source_var_type: &'static str,
+    sink_var_type: &'static str,
+    duplex_var_type: &'static str,
+    properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
+}
+
+impl<'a> ArgInType<'a> {
+    fn reborrow(&mut self) -> ArgInType<'_> {
+        ArgInType {
+            source_var_type: self.source_var_type,
+            sink_var_type: self.sink_var_type,
+            duplex_var_type: self.duplex_var_type,
+            properties: self.properties,
+            scope: self.scope,
+        }
+    }
+}
+
+trait WriteTrace: Copy {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()>;
+}
+
+impl WriteTrace for TraceDecl {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::Scope(v) => v.write_trace(writer, arg),
+            Self::Scalar(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+impl WriteTrace for TraceScalar {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::UInt(v) => v.write_trace(writer, arg),
+            Self::SInt(v) => v.write_trace(writer, arg),
+            Self::Bool(v) => v.write_trace(writer, arg),
+            Self::FieldlessEnum(v) => v.write_trace(writer, arg),
+            Self::EnumDiscriminant(v) => v.write_trace(writer, arg),
+            Self::Clock(v) => v.write_trace(writer, arg),
+            Self::SyncReset(v) => v.write_trace(writer, arg),
+            Self::AsyncReset(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
+    let min_char = b'!';
+    let max_char = b'~';
+    let base = (max_char - min_char + 1) as usize;
+    loop {
+        let digit = (id % base) as u8 + min_char;
+        id /= base;
+        writer.write_all(&[digit])?;
+        if id == 0 {
+            break;
+        }
+    }
+    Ok(())
+}
+
+struct Escaped<T: fmt::Display>(T);
+
+impl<T: fmt::Display> fmt::Display for Escaped<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        // escaping rules from function GTKWave uses to decode VCD strings:
+        // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
+        struct Wrapper<W>(W);
+        impl<W: fmt::Write> fmt::Write for Wrapper<W> {
+            fn write_str(&mut self, s: &str) -> fmt::Result {
+                for byte in s.bytes() {
+                    match byte {
+                        b'\\' | b'\'' | b'"' | b'?' => {
+                            self.0.write_str("\\")?;
+                            self.0.write_char(byte as char)?;
+                        }
+                        b'\n' => self.0.write_str(r"\n")?,
+                        b'\r' => self.0.write_str(r"\r")?,
+                        b'\t' => self.0.write_str(r"\t")?,
+                        0x7 => self.0.write_str(r"\a")?,
+                        0x8 => self.0.write_str(r"\b")?,
+                        0xC => self.0.write_str(r"\f")?,
+                        0xB => self.0.write_str(r"\v")?,
+                        _ => {
+                            if byte.is_ascii_graphic() {
+                                self.0.write_char(byte as char)?;
+                            } else {
+                                write!(self.0, r"\x{byte:02x}")?;
+                            }
+                        }
+                    }
+                }
+                Ok(())
+            }
+        }
+        write!(Wrapper(f), "{}", self.0)
+    }
+}
+
+fn write_vcd_var<W: io::Write>(
+    properties: &mut VcdWriterProperties,
+    memory_element_part_body: MemoryElementPartBody,
+    writer: &mut W,
+    var_type: &str,
+    size: usize,
+    location: TraceLocation,
+    name: VerilogIdentifier,
+) -> io::Result<()> {
+    let id = match location {
+        TraceLocation::Scalar(id) => id.as_usize(),
+        TraceLocation::Memory(TraceMemoryLocation {
+            id,
+            depth,
+            stride: _,
+            start,
+            len,
+        }) => {
+            let MemoryProperties {
+                element_parts,
+                element_part_index,
+                element_index,
+            } = &mut properties.memory_properties[id.as_usize()];
+            let first_id;
+            if let Some(element_part) = element_parts.get(*element_part_index) {
+                first_id = element_part.first_id;
+            } else {
+                first_id = properties.next_scalar_id;
+                properties.next_scalar_id += depth;
+                element_parts.push(MemoryElementPart {
+                    first_id,
+                    start,
+                    len,
+                    body: memory_element_part_body,
+                });
+            }
+            *element_part_index += 1;
+            first_id + *element_index
+        }
+    };
+    write!(writer, "$var {var_type} {size} ")?;
+    write_vcd_id(writer, id)?;
+    writeln!(writer, " {name} $end")
+}
+
+impl WriteTrace for TraceUInt {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
+        let mut var_type = match flow {
+            Flow::Source => source_var_type,
+            Flow::Sink => sink_var_type,
+            Flow::Duplex => duplex_var_type,
+        };
+        if ty.width() == 0 {
+            var_type = "string";
+        }
+        write_vcd_var(
+            properties,
+            MemoryElementPartBody::Scalar,
+            writer,
+            var_type,
+            ty.width(),
+            location,
+            scope.new_identifier(name),
+        )
+    }
+}
+
+impl WriteTrace for TraceSInt {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
+        TraceUInt {
+            location,
+            name,
+            ty: UInt::new_dyn(ty.width()),
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceBool {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceUInt {
+            location,
+            name,
+            flow,
+            ty: UInt::new_dyn(1),
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceFieldlessEnum {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
+        TraceEnumDiscriminant {
+            location,
+            name,
+            ty,
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceEnumDiscriminant {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type: _,
+            sink_var_type: _,
+            duplex_var_type: _,
+            properties,
+            scope,
+        } = arg.in_type();
+        let Self {
+            location,
+            name,
+            ty,
+            flow: _,
+        } = self;
+        write_vcd_var(
+            properties,
+            MemoryElementPartBody::EnumDiscriminant { ty },
+            writer,
+            "string",
+            1,
+            location,
+            scope.new_identifier(name),
+        )
+    }
+}
+
+impl WriteTrace for TraceClock {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceSyncReset {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceAsyncReset {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceScope {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::Module(v) => v.write_trace(writer, arg),
+            Self::Instance(v) => v.write_trace(writer, arg),
+            Self::Mem(v) => v.write_trace(writer, arg),
+            Self::MemPort(v) => v.write_trace(writer, arg),
+            Self::Wire(v) => v.write_trace(writer, arg),
+            Self::Reg(v) => v.write_trace(writer, arg),
+            Self::ModuleIO(v) => v.write_trace(writer, arg),
+            Self::Bundle(v) => v.write_trace(writer, arg),
+            Self::Array(v) => v.write_trace(writer, arg),
+            Self::EnumWithFields(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+impl WriteTrace for TraceModule {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModule { properties, scope } = arg.module();
+        let Self { name, children } = self;
+        write_vcd_scope(writer, "module", name, scope, |writer, scope| {
+            for child in children {
+                child.write_trace(writer, ArgModuleBody { properties, scope })?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceInstance {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            name: _,
+            instance_io,
+            module,
+            ty: _,
+        } = self;
+        instance_io.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+                properties,
+                scope,
+            },
+        )?;
+        module.write_trace(writer, ArgModule { properties, scope })
+    }
+}
+
+impl WriteTrace for TraceMem {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            id,
+            name,
+            stride: _,
+            element_type,
+            ports,
+            array_type,
+        } = self;
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            write_vcd_scope(
+                writer,
+                "struct",
+                "contents".intern(),
+                scope,
+                |writer, scope| {
+                    for element_index in 0..array_type.len() {
+                        write_vcd_scope(
+                            writer,
+                            "struct",
+                            Intern::intern_owned(format!("[{element_index}]")),
+                            scope,
+                            |writer, scope| {
+                                properties.memory_properties[id.as_usize()].element_index =
+                                    element_index;
+                                properties.memory_properties[id.as_usize()].element_part_index = 0;
+                                element_type.write_trace(
+                                    writer,
+                                    ArgInType {
+                                        source_var_type: "reg",
+                                        sink_var_type: "reg",
+                                        duplex_var_type: "reg",
+                                        properties,
+                                        scope,
+                                    },
+                                )
+                            },
+                        )?;
+                    }
+                    Ok(())
+                },
+            )?;
+            for port in ports {
+                port.write_trace(writer, ArgModuleBody { properties, scope })?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceMemPort {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            name: _,
+            bundle,
+            ty: _,
+        } = self;
+        bundle.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+                properties,
+                scope,
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceWire {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+                properties,
+                scope,
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceReg {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "reg",
+                sink_var_type: "reg",
+                duplex_var_type: "reg",
+                properties,
+                scope,
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceModuleIO {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties, scope } = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+            flow: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+                properties,
+                scope,
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceBundle {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
+        let Self {
+            name,
+            fields,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            for field in fields {
+                field.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceArray {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
+        let Self {
+            name,
+            elements,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            for element in elements {
+                element.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceEnumWithFields {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
+        let Self {
+            name,
+            discriminant,
+            non_empty_fields,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            discriminant.write_trace(
+                writer,
+                ArgInType {
+                    source_var_type,
+                    sink_var_type,
+                    duplex_var_type,
+                    properties,
+                    scope,
+                },
+            )?;
+            for field in non_empty_fields {
+                field.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
+    type Error = io::Error;
+    type TraceWriter = VcdWriter<W>;
+
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error> {
+        let Self {
+            mut writer,
+            timescale,
+        } = self;
+        writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
+        let mut properties = VcdWriterProperties {
+            next_scalar_id: trace_scalar_id_count,
+            memory_properties: (0..trace_memory_id_count)
+                .map(|_| MemoryProperties {
+                    element_parts: Vec::with_capacity(8),
+                    element_part_index: 0,
+                    element_index: 0,
+                })
+                .collect(),
+        };
+        module.write_trace(
+            &mut writer,
+            ArgModule {
+                properties: &mut properties,
+                scope: &mut Scope::default(),
+            },
+        )?;
+        writeln!(writer, "$enddefinitions $end")?;
+        writeln!(writer, "$dumpvars")?;
+        Ok(VcdWriter {
+            writer,
+            finished_init: false,
+            timescale,
+            properties,
+        })
+    }
+}
+
+enum MemoryElementPartBody {
+    Scalar,
+    EnumDiscriminant { ty: Enum },
+}
+
+struct MemoryElementPart {
+    first_id: usize,
+    start: usize,
+    len: usize,
+    body: MemoryElementPartBody,
+}
+
+struct MemoryProperties {
+    element_parts: Vec<MemoryElementPart>,
+    element_part_index: usize,
+    element_index: usize,
+}
+
+struct VcdWriterProperties {
+    next_scalar_id: usize,
+    memory_properties: Box<[MemoryProperties]>,
+}
+
+pub struct VcdWriter<W: io::Write + 'static> {
+    writer: W,
+    finished_init: bool,
+    timescale: SimDuration,
+    properties: VcdWriterProperties,
+}
+
+impl<W: io::Write + 'static> VcdWriter<W> {
+    pub fn timescale(&self) -> SimDuration {
+        self.timescale
+    }
+}
+
+fn write_string_value_change(
+    writer: &mut impl io::Write,
+    value: impl fmt::Display,
+    id: usize,
+) -> io::Result<()> {
+    write!(writer, "s{} ", Escaped(value))?;
+    write_vcd_id(writer, id)?;
+    writer.write_all(b"\n")
+}
+
+fn write_bits_value_change(
+    writer: &mut impl io::Write,
+    value: &BitSlice,
+    id: usize,
+) -> io::Result<()> {
+    match value.len() {
+        0 => writer.write_all(b"s0 ")?,
+        1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
+        _ => {
+            writer.write_all(b"b")?;
+            let mut any_ones = false;
+            for bit in value.iter().rev() {
+                if *bit {
+                    any_ones = true;
+                    writer.write_all(b"1")?;
+                } else if any_ones {
+                    writer.write_all(b"0")?;
+                }
+            }
+            if !any_ones {
+                writer.write_all(b"0")?;
+            }
+            writer.write_all(b" ")?;
+        }
+    }
+    write_vcd_id(writer, id)?;
+    writer.write_all(b"\n")
+}
+
+fn write_enum_discriminant_value_change(
+    writer: &mut impl io::Write,
+    variant_index: usize,
+    ty: Enum,
+    id: usize,
+) -> io::Result<()> {
+    write_string_value_change(
+        writer,
+        format_args!(
+            "{} ({variant_index})",
+            ty.variants()
+                .get(variant_index)
+                .map(|v| &*v.name)
+                .unwrap_or("<invalid>"),
+        ),
+        id,
+    )
+}
+
+impl<W: io::Write> TraceWriter for VcdWriter<W> {
+    type Error = io::Error;
+
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error> {
+        for &MemoryElementPart {
+            first_id,
+            start,
+            len,
+            ref body,
+        } in &self.properties.memory_properties[memory.as_usize()].element_parts
+        {
+            match body {
+                MemoryElementPartBody::Scalar => write_bits_value_change(
+                    &mut self.writer,
+                    &element_data[start..start + len],
+                    first_id + element_index,
+                )?,
+                MemoryElementPartBody::EnumDiscriminant { ty } => {
+                    let mut variant_index = 0;
+                    BitSlice::<usize, Lsb0>::from_element_mut(&mut variant_index)[..len]
+                        .clone_from_bitslice(&element_data[start..start + len]);
+                    write_enum_discriminant_value_change(
+                        &mut self.writer,
+                        variant_index,
+                        *ty,
+                        first_id + element_index,
+                    )?
+                }
+            }
+        }
+        Ok(())
+    }
+
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        write_bits_value_change(&mut self.writer, value, id.as_usize())
+    }
+
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        write_bits_value_change(&mut self.writer, value, id.as_usize())
+    }
+
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        if mem::replace(&mut self.finished_init, true) {
+            return Ok(());
+        }
+        writeln!(self.writer, "$end")
+    }
+
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        assert!(self.finished_init);
+        let mut instant_attos = (instant - SimInstant::START).as_attos();
+        instant_attos += self.timescale.as_attos() / 2;
+        let timestamp = instant_attos / self.timescale.as_attos();
+        writeln!(self.writer, "#{timestamp}")
+    }
+
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.writer.flush()
+    }
+
+    fn close(mut self) -> Result<(), Self::Error> {
+        self.writer.flush()
+    }
+
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error> {
+        write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
+    }
+}
+
+impl<W: io::Write> fmt::Debug for VcdWriter<W> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            writer: _,
+            finished_init,
+            timescale,
+            properties: _,
+        } = self;
+        f.debug_struct("VcdWriter")
+            .field("finished_init", finished_init)
+            .field("timescale", timescale)
+            .finish_non_exhaustive()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_scope() {
+        let mut scope = Scope::default();
+        assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo");
+        assert_eq!(
+            &*scope.new_identifier("foo_0".intern()).unescaped_name,
+            "foo_0"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_1".intern()).unescaped_name,
+            "foo_1"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_3".intern()).unescaped_name,
+            "foo_3"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo".intern()).unescaped_name,
+            "foo_2"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo".intern()).unescaped_name,
+            "foo_4"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_0".intern()).unescaped_name,
+            "foo_0_2"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_1".intern()).unescaped_name,
+            "foo_1_2"
+        );
+        for i in 5..1000u64 {
+            // verify it actually picks the next available identifier with no skips or duplicates
+            assert_eq!(
+                *scope.new_identifier("foo".intern()).unescaped_name,
+                format!("foo_{i}"),
+            );
+        }
+    }
+}
diff --git a/crates/fayalite/src/source_location.rs b/crates/fayalite/src/source_location.rs
index d143f22..1a168b1 100644
--- a/crates/fayalite/src/source_location.rs
+++ b/crates/fayalite/src/source_location.rs
@@ -2,9 +2,8 @@
 // See Notices.txt for copyright information
 use crate::{
     intern::{Intern, Interned},
-    util::DebugAsDisplay,
+    util::{DebugAsDisplay, HashMap},
 };
-use hashbrown::HashMap;
 use std::{cell::RefCell, fmt, num::NonZeroUsize, panic, path::Path};
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
@@ -97,7 +96,7 @@ impl NormalizeFilesForTestsState {
     fn new() -> Self {
         Self {
             test_position: panic::Location::caller(),
-            file_pattern_matches: HashMap::new(),
+            file_pattern_matches: HashMap::default(),
         }
     }
 }
@@ -143,7 +142,7 @@ impl From<&'_ panic::Location<'_>> for SourceLocation {
                         map.entry_ref(file)
                             .or_insert_with(|| NormalizedFileForTestState {
                                 file_name_id: NonZeroUsize::new(len + 1).unwrap(),
-                                positions_map: HashMap::new(),
+                                positions_map: HashMap::default(),
                             });
                     file_str = m.generate_file_name(file_state.file_name_id);
                     file = &file_str;
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
index 4517e34..b81bc3f 100644
--- a/crates/fayalite/src/testing.rs
+++ b/crates/fayalite/src/testing.rs
@@ -3,9 +3,9 @@
 use crate::{
     cli::{FormalArgs, FormalMode, FormalOutput, RunPhase},
     firrtl::ExportOptions,
+    util::HashMap,
 };
 use clap::Parser;
-use hashbrown::HashMap;
 use serde::Deserialize;
 use std::{
     fmt::Write,
@@ -87,7 +87,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
     let index = *DIRS
         .lock()
         .unwrap()
-        .get_or_insert_with(HashMap::new)
+        .get_or_insert_with(HashMap::default)
         .entry_ref(&dir)
         .and_modify(|v| *v += 1)
         .or_insert(0);
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 69080c9..8f41c5c 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -7,12 +7,19 @@ use crate::{
     clock::Clock,
     enum_::Enum,
     expr::Expr,
-    int::{Bool, SInt, UInt},
+    int::{Bool, SInt, UInt, UIntValue},
     intern::{Intern, Interned},
+    phantom_const::PhantomConst,
     reset::{AsyncReset, Reset, SyncReset},
+    sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
+    util::ConstUsize,
 };
-use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index};
+use bitvec::slice::BitSlice;
+use serde::{de::DeserializeOwned, Deserialize, Deserializer, Serialize, Serializer};
+use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index, sync::Arc};
+
+pub(crate) mod serde_impls;
 
 #[derive(Copy, Clone, Hash, PartialEq, Eq, Debug)]
 #[non_exhaustive]
@@ -35,6 +42,7 @@ pub enum CanonicalType {
     SyncReset(SyncReset),
     Reset(Reset),
     Clock(Clock),
+    PhantomConst(PhantomConst),
 }
 
 impl fmt::Debug for CanonicalType {
@@ -50,10 +58,29 @@ impl fmt::Debug for CanonicalType {
             Self::SyncReset(v) => v.fmt(f),
             Self::Reset(v) => v.fmt(f),
             Self::Clock(v) => v.fmt(f),
+            Self::PhantomConst(v) => v.fmt(f),
         }
     }
 }
 
+impl Serialize for CanonicalType {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        serde_impls::SerdeCanonicalType::from(*self).serialize(serializer)
+    }
+}
+
+impl<'de> Deserialize<'de> for CanonicalType {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        Ok(serde_impls::SerdeCanonicalType::deserialize(deserializer)?.into())
+    }
+}
+
 impl CanonicalType {
     pub fn type_properties(self) -> TypeProperties {
         match self {
@@ -67,6 +94,7 @@ impl CanonicalType {
             CanonicalType::SyncReset(v) => v.type_properties(),
             CanonicalType::Reset(v) => v.type_properties(),
             CanonicalType::Clock(v) => v.type_properties(),
+            CanonicalType::PhantomConst(v) => v.type_properties(),
         }
     }
     pub fn is_passive(self) -> bool {
@@ -143,8 +171,17 @@ impl CanonicalType {
                 };
                 lhs.can_connect(rhs)
             }
+            CanonicalType::PhantomConst(lhs) => {
+                let CanonicalType::PhantomConst(rhs) = rhs else {
+                    return false;
+                };
+                lhs.can_connect(rhs)
+            }
         }
     }
+    pub(crate) fn as_serde_unexpected_str(self) -> &'static str {
+        serde_impls::SerdeCanonicalType::from(self).as_serde_unexpected_str()
+    }
 }
 
 pub trait MatchVariantAndInactiveScope: Sized {
@@ -166,7 +203,7 @@ impl<T: 'static + Send + Sync> MatchVariantAndInactiveScope for MatchVariantWith
 }
 
 pub trait FillInDefaultedGenerics {
-    type Type: Type;
+    type Type;
     fn fill_in_defaulted_generics(self) -> Self::Type;
 }
 
@@ -178,6 +215,22 @@ impl<T: Type> FillInDefaultedGenerics for T {
     }
 }
 
+impl FillInDefaultedGenerics for usize {
+    type Type = usize;
+
+    fn fill_in_defaulted_generics(self) -> Self::Type {
+        self
+    }
+}
+
+impl<const V: usize> FillInDefaultedGenerics for ConstUsize<V> {
+    type Type = ConstUsize<V>;
+
+    fn fill_in_defaulted_generics(self) -> Self::Type {
+        self
+    }
+}
+
 mod sealed {
     pub trait TypeOrDefaultSealed {}
     pub trait BaseTypeSealed {}
@@ -195,6 +248,34 @@ macro_rules! impl_base_type {
     };
 }
 
+macro_rules! impl_base_type_serde {
+    ($name:ident, $expected:literal) => {
+        impl Serialize for $name {
+            fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+            where
+                S: Serializer,
+            {
+                self.canonical().serialize(serializer)
+            }
+        }
+
+        impl<'de> Deserialize<'de> for $name {
+            fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+            where
+                D: Deserializer<'de>,
+            {
+                match CanonicalType::deserialize(deserializer)? {
+                    CanonicalType::$name(retval) => Ok(retval),
+                    ty => Err(serde::de::Error::invalid_value(
+                        serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                        &$expected,
+                    )),
+                }
+            }
+        }
+    };
+}
+
 impl_base_type!(UInt);
 impl_base_type!(SInt);
 impl_base_type!(Bool);
@@ -205,6 +286,15 @@ impl_base_type!(AsyncReset);
 impl_base_type!(SyncReset);
 impl_base_type!(Reset);
 impl_base_type!(Clock);
+impl_base_type!(PhantomConst);
+
+impl_base_type_serde!(Bool, "a Bool");
+impl_base_type_serde!(Enum, "an Enum");
+impl_base_type_serde!(Bundle, "a Bundle");
+impl_base_type_serde!(AsyncReset, "an AsyncReset");
+impl_base_type_serde!(SyncReset, "a SyncReset");
+impl_base_type_serde!(Reset, "a Reset");
+impl_base_type_serde!(Clock, "a Clock");
 
 impl sealed::BaseTypeSealed for CanonicalType {}
 
@@ -240,6 +330,7 @@ pub trait Type:
 {
     type BaseType: BaseType;
     type MaskType: Type<MaskType = Self::MaskType>;
+    type SimValue: fmt::Debug + Clone + 'static + ToSimValueWithType<Self>;
     type MatchVariant: 'static + Send + Sync;
     type MatchActiveScope;
     type MatchVariantAndInactiveScope: MatchVariantAndInactiveScope<
@@ -257,9 +348,22 @@ pub trait Type:
     fn canonical(&self) -> CanonicalType;
     fn from_canonical(canonical_type: CanonicalType) -> Self;
     fn source_location() -> SourceLocation;
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue;
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice);
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice);
 }
 
-pub trait BaseType: Type<BaseType = Self> + sealed::BaseTypeSealed + Into<CanonicalType> {}
+pub trait BaseType:
+    Type<
+        BaseType = Self,
+        MaskType: Serialize + DeserializeOwned,
+        SimValue: Serialize + DeserializeOwned,
+    > + sealed::BaseTypeSealed
+    + Into<CanonicalType>
+    + Serialize
+    + DeserializeOwned
+{
+}
 
 macro_rules! impl_match_variant_as_self {
     () => {
@@ -286,6 +390,7 @@ pub trait TypeWithDeref: Type {
 impl Type for CanonicalType {
     type BaseType = CanonicalType;
     type MaskType = CanonicalType;
+    type SimValue = OpaqueSimValue;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         match self {
@@ -299,6 +404,7 @@ impl Type for CanonicalType {
             CanonicalType::SyncReset(v) => v.mask_type().canonical(),
             CanonicalType::Reset(v) => v.mask_type().canonical(),
             CanonicalType::Clock(v) => v.mask_type().canonical(),
+            CanonicalType::PhantomConst(v) => v.mask_type().canonical(),
         }
     }
     fn canonical(&self) -> CanonicalType {
@@ -310,9 +416,60 @@ impl Type for CanonicalType {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.bit_width());
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.bit_width());
+        assert_eq!(value.bit_width(), self.bit_width());
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.bit_width());
+        assert_eq!(value.bit_width(), self.bit_width());
+        bits.copy_from_bitslice(value.bits().bits());
+    }
 }
 
-pub trait StaticType: Type {
+#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
+pub struct OpaqueSimValue {
+    bits: UIntValue,
+}
+
+impl OpaqueSimValue {
+    pub fn bit_width(&self) -> usize {
+        self.bits.width()
+    }
+    pub fn bits(&self) -> &UIntValue {
+        &self.bits
+    }
+    pub fn bits_mut(&mut self) -> &mut UIntValue {
+        &mut self.bits
+    }
+    pub fn into_bits(self) -> UIntValue {
+        self.bits
+    }
+    pub fn from_bits(bits: UIntValue) -> Self {
+        Self { bits }
+    }
+    pub fn from_bitslice(v: &BitSlice) -> Self {
+        Self {
+            bits: UIntValue::new(Arc::new(v.to_bitvec())),
+        }
+    }
+}
+
+impl<T: Type<SimValue = OpaqueSimValue>> ToSimValueWithType<T> for OpaqueSimValue {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        SimValue::from_value(ty, self.clone())
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        SimValue::from_value(ty, self)
+    }
+}
+
+pub trait StaticType: Type + Default {
     const TYPE: Self;
     const MASK_TYPE: Self::MaskType;
     const TYPE_PROPERTIES: TypeProperties;
diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs
new file mode 100644
index 0000000..2ea4362
--- /dev/null
+++ b/crates/fayalite/src/ty/serde_impls.rs
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    array::Array,
+    bundle::{Bundle, BundleType},
+    clock::Clock,
+    enum_::{Enum, EnumType},
+    int::{Bool, SInt, UInt},
+    intern::Interned,
+    phantom_const::{PhantomConstCanonicalValue, PhantomConstValue},
+    prelude::PhantomConst,
+    reset::{AsyncReset, Reset, SyncReset},
+    ty::{BaseType, CanonicalType},
+};
+use serde::{Deserialize, Deserializer, Serialize, Serializer};
+
+pub(crate) struct SerdePhantomConst<T>(pub T);
+
+impl<T: ?Sized + PhantomConstValue> Serialize for SerdePhantomConst<Interned<T>> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        self.0.serialize(serializer)
+    }
+}
+
+impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for SerdePhantomConst<Interned<T>> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        T::deserialize_value(deserializer).map(Self)
+    }
+}
+
+#[derive(Serialize, Deserialize)]
+#[serde(rename = "CanonicalType")]
+pub(crate) enum SerdeCanonicalType<
+    ArrayElement = CanonicalType,
+    ThePhantomConst = SerdePhantomConst<Interned<PhantomConstCanonicalValue>>,
+> {
+    UInt {
+        width: usize,
+    },
+    SInt {
+        width: usize,
+    },
+    Bool,
+    Array {
+        element: ArrayElement,
+        len: usize,
+    },
+    Enum {
+        variants: Interned<[crate::enum_::EnumVariant]>,
+    },
+    Bundle {
+        fields: Interned<[crate::bundle::BundleField]>,
+    },
+    AsyncReset,
+    SyncReset,
+    Reset,
+    Clock,
+    PhantomConst(ThePhantomConst),
+}
+
+impl<ArrayElement, PhantomConstInner> SerdeCanonicalType<ArrayElement, PhantomConstInner> {
+    pub(crate) fn as_serde_unexpected_str(&self) -> &'static str {
+        match self {
+            Self::UInt { .. } => "a UInt",
+            Self::SInt { .. } => "a SInt",
+            Self::Bool => "a Bool",
+            Self::Array { .. } => "an Array",
+            Self::Enum { .. } => "an Enum",
+            Self::Bundle { .. } => "a Bundle",
+            Self::AsyncReset => "an AsyncReset",
+            Self::SyncReset => "a SyncReset",
+            Self::Reset => "a Reset",
+            Self::Clock => "a Clock",
+            Self::PhantomConst(_) => "a PhantomConst",
+        }
+    }
+}
+
+impl<T: BaseType> From<T> for SerdeCanonicalType {
+    fn from(ty: T) -> Self {
+        let ty: CanonicalType = ty.into();
+        match ty {
+            CanonicalType::UInt(ty) => Self::UInt { width: ty.width() },
+            CanonicalType::SInt(ty) => Self::SInt { width: ty.width() },
+            CanonicalType::Bool(Bool {}) => Self::Bool,
+            CanonicalType::Array(ty) => Self::Array {
+                element: ty.element(),
+                len: ty.len(),
+            },
+            CanonicalType::Enum(ty) => Self::Enum {
+                variants: ty.variants(),
+            },
+            CanonicalType::Bundle(ty) => Self::Bundle {
+                fields: ty.fields(),
+            },
+            CanonicalType::AsyncReset(AsyncReset {}) => Self::AsyncReset,
+            CanonicalType::SyncReset(SyncReset {}) => Self::SyncReset,
+            CanonicalType::Reset(Reset {}) => Self::Reset,
+            CanonicalType::Clock(Clock {}) => Self::Clock,
+            CanonicalType::PhantomConst(ty) => Self::PhantomConst(SerdePhantomConst(ty.get())),
+        }
+    }
+}
+
+impl From<SerdeCanonicalType> for CanonicalType {
+    fn from(ty: SerdeCanonicalType) -> Self {
+        match ty {
+            SerdeCanonicalType::UInt { width } => Self::UInt(UInt::new(width)),
+            SerdeCanonicalType::SInt { width } => Self::SInt(SInt::new(width)),
+            SerdeCanonicalType::Bool => Self::Bool(Bool),
+            SerdeCanonicalType::Array { element, len } => Self::Array(Array::new(element, len)),
+            SerdeCanonicalType::Enum { variants } => Self::Enum(Enum::new(variants)),
+            SerdeCanonicalType::Bundle { fields } => Self::Bundle(Bundle::new(fields)),
+            SerdeCanonicalType::AsyncReset => Self::AsyncReset(AsyncReset),
+            SerdeCanonicalType::SyncReset => Self::SyncReset(SyncReset),
+            SerdeCanonicalType::Reset => Self::Reset(Reset),
+            SerdeCanonicalType::Clock => Self::Clock(Clock),
+            SerdeCanonicalType::PhantomConst(value) => {
+                Self::PhantomConst(PhantomConst::new(value.0))
+            }
+        }
+    }
+}
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index f66654f..233867e 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -1,12 +1,23 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
+pub(crate) mod alternating_cell;
 mod const_bool;
 mod const_cmp;
 mod const_usize;
 mod misc;
 mod scoped_ref;
 pub(crate) mod streaming_read_utf8;
+mod test_hasher;
+
+// allow easily switching the hasher crate-wide for testing
+#[cfg(feature = "unstable-test-hasher")]
+pub type DefaultBuildHasher = test_hasher::DefaultBuildHasher;
+#[cfg(not(feature = "unstable-test-hasher"))]
+pub(crate) type DefaultBuildHasher = hashbrown::DefaultHashBuilder;
+
+pub(crate) type HashMap<K, V> = hashbrown::HashMap<K, V, DefaultBuildHasher>;
+pub(crate) type HashSet<T> = hashbrown::HashSet<T, DefaultBuildHasher>;
 
 #[doc(inline)]
 pub use const_bool::{ConstBool, ConstBoolDispatch, ConstBoolDispatchTag, GenericConstBool};
@@ -24,8 +35,10 @@ pub use scoped_ref::ScopedRef;
 
 #[doc(inline)]
 pub use misc::{
-    interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay, DebugAsRawString, MakeMutSlice,
+    get_many_mut, interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay,
+    DebugAsRawString, MakeMutSlice, RcWriter,
 };
 
 pub mod job_server;
+pub mod prefix_sum;
 pub mod ready_valid;
diff --git a/crates/fayalite/src/util/alternating_cell.rs b/crates/fayalite/src/util/alternating_cell.rs
new file mode 100644
index 0000000..17e06a6
--- /dev/null
+++ b/crates/fayalite/src/util/alternating_cell.rs
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::util::DebugAsDisplay;
+use std::{
+    cell::{Cell, UnsafeCell},
+    fmt,
+};
+
+pub(crate) trait AlternatingCellMethods {
+    fn unique_to_shared(&mut self);
+    fn shared_to_unique(&mut self);
+}
+
+#[derive(Copy, Clone, Debug)]
+enum State {
+    Unique,
+    Shared,
+    Locked,
+}
+
+pub(crate) struct AlternatingCell<T: ?Sized> {
+    state: Cell<State>,
+    value: UnsafeCell<T>,
+}
+
+impl<T: ?Sized + fmt::Debug + AlternatingCellMethods> fmt::Debug for AlternatingCell<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("AlternatingCell")
+            .field(
+                self.try_share()
+                    .as_ref()
+                    .map(|v| -> &dyn fmt::Debug { v })
+                    .unwrap_or(&DebugAsDisplay("<...>")),
+            )
+            .finish()
+    }
+}
+
+impl<T: ?Sized> AlternatingCell<T> {
+    pub(crate) const fn new_shared(value: T) -> Self
+    where
+        T: Sized,
+    {
+        Self {
+            state: Cell::new(State::Shared),
+            value: UnsafeCell::new(value),
+        }
+    }
+    pub(crate) const fn new_unique(value: T) -> Self
+    where
+        T: Sized,
+    {
+        Self {
+            state: Cell::new(State::Unique),
+            value: UnsafeCell::new(value),
+        }
+    }
+    pub(crate) fn is_unique(&self) -> bool {
+        matches!(self.state.get(), State::Unique)
+    }
+    pub(crate) fn is_shared(&self) -> bool {
+        matches!(self.state.get(), State::Shared)
+    }
+    pub(crate) fn into_inner(self) -> T
+    where
+        T: Sized,
+    {
+        self.value.into_inner()
+    }
+    pub(crate) fn try_share(&self) -> Option<&T>
+    where
+        T: AlternatingCellMethods,
+    {
+        match self.state.get() {
+            State::Shared => {}
+            State::Unique => {
+                struct Locked<'a>(&'a Cell<State>);
+                impl Drop for Locked<'_> {
+                    fn drop(&mut self) {
+                        self.0.set(State::Shared);
+                    }
+                }
+                self.state.set(State::Locked);
+                let lock = Locked(&self.state);
+                // Safety: state is Locked, so nothing else will
+                // access value while calling unique_to_shared.
+                unsafe { &mut *self.value.get() }.unique_to_shared();
+                drop(lock);
+            }
+            State::Locked => return None,
+        }
+
+        // Safety: state is Shared so nothing will create any mutable
+        // references until the returned reference's lifetime expires.
+        Some(unsafe { &*self.value.get() })
+    }
+    #[track_caller]
+    pub(crate) fn share(&self) -> &T
+    where
+        T: AlternatingCellMethods,
+    {
+        let Some(retval) = self.try_share() else {
+            panic!("`share` called recursively");
+        };
+        retval
+    }
+    pub(crate) fn unique(&mut self) -> &mut T
+    where
+        T: AlternatingCellMethods,
+    {
+        match self.state.get() {
+            State::Shared => {
+                self.state.set(State::Unique);
+                self.value.get_mut().shared_to_unique();
+            }
+            State::Unique => {}
+            State::Locked => unreachable!(),
+        }
+        self.value.get_mut()
+    }
+}
diff --git a/crates/fayalite/src/util/const_bool.rs b/crates/fayalite/src/util/const_bool.rs
index 7033d6a..7def3b5 100644
--- a/crates/fayalite/src/util/const_bool.rs
+++ b/crates/fayalite/src/util/const_bool.rs
@@ -1,5 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+use serde::{
+    de::{DeserializeOwned, Error, Unexpected},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{fmt::Debug, hash::Hash, mem::ManuallyDrop, ptr};
 
 mod sealed {
@@ -9,7 +13,17 @@ mod sealed {
 /// # Safety
 /// the only implementation is `ConstBool<Self::VALUE>`
 pub unsafe trait GenericConstBool:
-    sealed::Sealed + Copy + Ord + Hash + Default + Debug + 'static + Send + Sync
+    sealed::Sealed
+    + Copy
+    + Ord
+    + Hash
+    + Default
+    + Debug
+    + 'static
+    + Send
+    + Sync
+    + Serialize
+    + DeserializeOwned
 {
     const VALUE: bool;
 }
@@ -30,6 +44,32 @@ unsafe impl<const VALUE: bool> GenericConstBool for ConstBool<VALUE> {
     const VALUE: bool = VALUE;
 }
 
+impl<const VALUE: bool> Serialize for ConstBool<VALUE> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        VALUE.serialize(serializer)
+    }
+}
+
+impl<'de, const VALUE: bool> Deserialize<'de> for ConstBool<VALUE> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let value = bool::deserialize(deserializer)?;
+        if value == VALUE {
+            Ok(ConstBool)
+        } else {
+            Err(D::Error::invalid_value(
+                Unexpected::Bool(value),
+                &if VALUE { "true" } else { "false" },
+            ))
+        }
+    }
+}
+
 pub trait ConstBoolDispatchTag {
     type Type<Select: GenericConstBool>;
 }
diff --git a/crates/fayalite/src/util/const_usize.rs b/crates/fayalite/src/util/const_usize.rs
index a605336..e098a12 100644
--- a/crates/fayalite/src/util/const_usize.rs
+++ b/crates/fayalite/src/util/const_usize.rs
@@ -1,5 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+use serde::{
+    de::{DeserializeOwned, Error, Unexpected},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{fmt::Debug, hash::Hash};
 
 mod sealed {
@@ -8,7 +12,17 @@ mod sealed {
 
 /// the only implementation is `ConstUsize<Self::VALUE>`
 pub trait GenericConstUsize:
-    sealed::Sealed + Copy + Ord + Hash + Default + Debug + 'static + Send + Sync
+    sealed::Sealed
+    + Copy
+    + Ord
+    + Hash
+    + Default
+    + Debug
+    + 'static
+    + Send
+    + Sync
+    + Serialize
+    + DeserializeOwned
 {
     const VALUE: usize;
 }
@@ -27,3 +41,29 @@ impl<const VALUE: usize> sealed::Sealed for ConstUsize<VALUE> {}
 impl<const VALUE: usize> GenericConstUsize for ConstUsize<VALUE> {
     const VALUE: usize = VALUE;
 }
+
+impl<const VALUE: usize> Serialize for ConstUsize<VALUE> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        VALUE.serialize(serializer)
+    }
+}
+
+impl<'de, const VALUE: usize> Deserialize<'de> for ConstUsize<VALUE> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let value = usize::deserialize(deserializer)?;
+        if value == VALUE {
+            Ok(ConstUsize)
+        } else {
+            Err(D::Error::invalid_value(
+                Unexpected::Unsigned(value as u64),
+                &&*VALUE.to_string(),
+            ))
+        }
+    }
+}
diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs
index 884458f..f482eaa 100644
--- a/crates/fayalite/src/util/misc.rs
+++ b/crates/fayalite/src/util/misc.rs
@@ -3,6 +3,7 @@
 use crate::intern::{Intern, Interned};
 use bitvec::{bits, order::Lsb0, slice::BitSlice, view::BitView};
 use std::{
+    cell::Cell,
     fmt::{self, Debug, Write},
     rc::Rc,
     sync::{Arc, OnceLock},
@@ -94,9 +95,15 @@ pub fn interned_bit(v: bool) -> Interned<BitSlice> {
     RETVAL.get_or_init(|| [bits![0; 1].intern(), bits![1; 1].intern()])[v as usize]
 }
 
-#[derive(Copy, Clone, Debug)]
+#[derive(Copy, Clone)]
 pub struct BitSliceWriteWithBase<'a>(pub &'a BitSlice);
 
+impl<'a> Debug for BitSliceWriteWithBase<'a> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "{self:#x}")
+    }
+}
+
 impl BitSliceWriteWithBase<'_> {
     fn fmt_with_base<const BITS_PER_DIGIT: usize, const UPPER_CASE: bool>(
         self,
@@ -155,3 +162,66 @@ impl fmt::UpperHex for BitSliceWriteWithBase<'_> {
         self.fmt_with_base::<4, true>(f)
     }
 }
+
+#[inline]
+#[track_caller]
+pub fn get_many_mut<T, const N: usize>(slice: &mut [T], indexes: [usize; N]) -> [&mut T; N] {
+    for i in 0..N {
+        for j in 0..i {
+            assert!(indexes[i] != indexes[j], "duplicate index");
+        }
+        assert!(indexes[i] < slice.len(), "index out of bounds");
+    }
+    // Safety: checked that no indexes are duplicates and no indexes are out of bounds
+    unsafe {
+        let base = slice.as_mut_ptr(); // convert to a raw pointer before loop to avoid aliasing with &mut [T]
+        std::array::from_fn(|i| &mut *base.add(indexes[i]))
+    }
+}
+
+#[derive(Clone, Default)]
+pub struct RcWriter(Rc<Cell<Vec<u8>>>);
+
+impl Debug for RcWriter {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.borrow_impl(|buf| {
+            f.debug_tuple("RcWriter")
+                .field(&DebugAsDisplay(format_args!("b\"{}\"", buf.escape_ascii())))
+                .finish()
+        })
+    }
+}
+
+impl RcWriter {
+    fn borrow_impl<R>(&self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
+        let buf = Cell::take(&self.0);
+        struct PutBackOnDrop<'a> {
+            buf: Vec<u8>,
+            this: &'a RcWriter,
+        }
+        impl Drop for PutBackOnDrop<'_> {
+            fn drop(&mut self) {
+                self.this.0.set(std::mem::take(&mut self.buf));
+            }
+        }
+        let mut buf = PutBackOnDrop { buf, this: self };
+        f(&mut buf.buf)
+    }
+    pub fn borrow<R>(&mut self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
+        self.borrow_impl(f)
+    }
+    pub fn take(&mut self) -> Vec<u8> {
+        Cell::take(&self.0)
+    }
+}
+
+impl std::io::Write for RcWriter {
+    fn write(&mut self, buf: &[u8]) -> std::io::Result<usize> {
+        self.borrow(|v| v.extend_from_slice(buf));
+        Ok(buf.len())
+    }
+
+    fn flush(&mut self) -> std::io::Result<()> {
+        Ok(())
+    }
+}
diff --git a/crates/fayalite/src/util/prefix_sum.rs b/crates/fayalite/src/util/prefix_sum.rs
new file mode 100644
index 0000000..98e6d95
--- /dev/null
+++ b/crates/fayalite/src/util/prefix_sum.rs
@@ -0,0 +1,839 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+// code derived from:
+// https://web.archive.org/web/20250303054010/https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/prefix_sum.py;hb=effeb28e5848392adddcdad1f6e7a098f2a44c9c
+
+use crate::intern::{Intern, Interned, Memoize};
+use std::{borrow::Cow, num::NonZeroUsize};
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct PrefixSumOp {
+    pub lhs_index: usize,
+    pub rhs_and_dest_index: NonZeroUsize,
+    pub row: u32,
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+#[non_exhaustive]
+pub struct DiagramConfig {
+    pub space: Cow<'static, str>,
+    pub vertical_bar: Cow<'static, str>,
+    pub plus: Cow<'static, str>,
+    pub slant: Cow<'static, str>,
+    pub connect: Cow<'static, str>,
+    pub no_connect: Cow<'static, str>,
+    pub padding: usize,
+}
+
+impl DiagramConfig {
+    pub const fn new() -> Self {
+        Self {
+            space: Cow::Borrowed(" "),
+            vertical_bar: Cow::Borrowed("|"),
+            plus: Cow::Borrowed("\u{2295}"), // ⊕
+            slant: Cow::Borrowed(r"\"),
+            connect: Cow::Borrowed("\u{25CF}"), // ●
+            no_connect: Cow::Borrowed("X"),
+            padding: 1,
+        }
+    }
+    pub fn draw(self, ops: impl IntoIterator<Item = PrefixSumOp>, item_count: usize) -> String {
+        #[derive(Copy, Clone, Debug)]
+        struct DiagramCell {
+            slant: bool,
+            plus: bool,
+            tee: bool,
+        }
+        let mut ops_by_row: Vec<Vec<PrefixSumOp>> = Vec::new();
+        let mut last_row = 0;
+        ops.into_iter().for_each(|op| {
+            assert!(
+                op.lhs_index < op.rhs_and_dest_index.get(),
+                "invalid PrefixSumOp! lhs_index must be less \
+                than rhs_and_dest_index: {op:?}",
+            );
+            assert!(
+                op.row >= last_row,
+                "invalid PrefixSumOp! row must \
+                not decrease (row last was: {last_row}): {op:?}",
+            );
+            let ops = if op.row > last_row || ops_by_row.is_empty() {
+                ops_by_row.push(vec![]);
+                ops_by_row.last_mut().expect("just pushed")
+            } else {
+                ops_by_row
+                    .last_mut()
+                    .expect("just checked if ops_by_row is empty")
+            };
+            if let Some(last) = ops.last() {
+                assert!(
+                    op.rhs_and_dest_index < last.rhs_and_dest_index,
+                    "invalid PrefixSumOp! rhs_and_dest_index must strictly \
+                    decrease in a row:\nthis op: {op:?}\nlast op: {last:?}",
+                );
+            }
+            ops.push(op);
+            last_row = op.row;
+        });
+        let blank_row = || {
+            vec![
+                DiagramCell {
+                    slant: false,
+                    plus: false,
+                    tee: false
+                };
+                item_count
+            ]
+        };
+        let mut cells = vec![blank_row()];
+        for ops in ops_by_row {
+            let max_distance = ops
+                .iter()
+                .map(
+                    |&PrefixSumOp {
+                         lhs_index,
+                         rhs_and_dest_index,
+                         ..
+                     }| { rhs_and_dest_index.get() - lhs_index },
+                )
+                .max()
+                .expect("ops is known to be non-empty");
+            cells.extend((0..max_distance).map(|_| blank_row()));
+            for op in ops {
+                let mut y = cells.len() - 1;
+                assert!(
+                    op.rhs_and_dest_index.get() < item_count,
+                    "invalid PrefixSumOp! rhs_and_dest_index must be \
+                    less than item_count ({item_count}): {op:?}",
+                );
+                let mut x = op.rhs_and_dest_index.get();
+                cells[y][x].plus = true;
+                x -= 1;
+                y -= 1;
+                while op.lhs_index < x {
+                    cells[y][x].slant = true;
+                    x -= 1;
+                    y -= 1;
+                }
+                cells[y][x].tee = true;
+            }
+        }
+        let mut retval = String::new();
+        let mut row_text = vec![String::new(); 2 * self.padding + 1];
+        for cells_row in cells {
+            for cell in cells_row {
+                // top padding
+                for y in 0..self.padding {
+                    // top left padding
+                    for x in 0..self.padding {
+                        row_text[y] += if x == y && (cell.plus || cell.slant) {
+                            &self.slant
+                        } else {
+                            &self.space
+                        };
+                    }
+                    // top vertical bar
+                    row_text[y] += &self.vertical_bar;
+                    // top right padding
+                    for _ in 0..self.padding {
+                        row_text[y] += &self.space;
+                    }
+                }
+                // center left padding
+                for _ in 0..self.padding {
+                    row_text[self.padding] += &self.space;
+                }
+                // center
+                row_text[self.padding] += if cell.plus {
+                    &self.plus
+                } else if cell.tee {
+                    &self.connect
+                } else if cell.slant {
+                    &self.no_connect
+                } else {
+                    &self.vertical_bar
+                };
+                // center right padding
+                for _ in 0..self.padding {
+                    row_text[self.padding] += &self.space;
+                }
+                let bottom_padding_start = self.padding + 1;
+                let bottom_padding_last = self.padding * 2;
+                // bottom padding
+                for y in bottom_padding_start..=bottom_padding_last {
+                    // bottom left padding
+                    for _ in 0..self.padding {
+                        row_text[y] += &self.space;
+                    }
+                    // bottom vertical bar
+                    row_text[y] += &self.vertical_bar;
+                    // bottom right padding
+                    for x in bottom_padding_start..=bottom_padding_last {
+                        row_text[y] += if x == y && (cell.tee || cell.slant) {
+                            &self.slant
+                        } else {
+                            &self.space
+                        };
+                    }
+                }
+            }
+            for line in &mut row_text {
+                retval += line.trim_end();
+                retval += "\n";
+                line.clear();
+            }
+        }
+        retval
+    }
+}
+
+impl Default for DiagramConfig {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl PrefixSumOp {
+    pub fn diagram(ops: impl IntoIterator<Item = Self>, item_count: usize) -> String {
+        Self::diagram_with_config(ops, item_count, DiagramConfig::new())
+    }
+    pub fn diagram_with_config(
+        ops: impl IntoIterator<Item = Self>,
+        item_count: usize,
+        config: DiagramConfig,
+    ) -> String {
+        config.draw(ops, item_count)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub enum PrefixSumAlgorithm {
+    /// Uses the algorithm from:
+    /// <https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_1:_Shorter_span,_more_parallel>
+    LowLatency,
+    /// Uses the algorithm from:
+    /// <https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_2:_Work-efficient>
+    WorkEfficient,
+}
+
+impl PrefixSumAlgorithm {
+    fn ops_impl(self, item_count: usize) -> Vec<PrefixSumOp> {
+        let mut retval = Vec::new();
+        let mut distance = 1;
+        let mut row = 0;
+        while distance < item_count {
+            let double_distance = distance
+                .checked_mul(2)
+                .expect("prefix-sum item_count is too big");
+            let (start, step) = match self {
+                Self::LowLatency => (distance, 1),
+                Self::WorkEfficient => (double_distance - 1, double_distance),
+            };
+            for rhs_and_dest_index in (start..item_count).step_by(step).rev() {
+                let Some(rhs_and_dest_index) = NonZeroUsize::new(rhs_and_dest_index) else {
+                    unreachable!();
+                };
+                let lhs_index = rhs_and_dest_index.get() - distance;
+                retval.push(PrefixSumOp {
+                    lhs_index,
+                    rhs_and_dest_index,
+                    row,
+                });
+            }
+            distance = double_distance;
+            row += 1;
+        }
+        match self {
+            Self::LowLatency => {}
+            Self::WorkEfficient => {
+                distance /= 2;
+                while distance >= 1 {
+                    let start = distance
+                        .checked_mul(3)
+                        .expect("prefix-sum item_count is too big")
+                        - 1;
+                    for rhs_and_dest_index in (start..item_count).step_by(distance * 2).rev() {
+                        let Some(rhs_and_dest_index) = NonZeroUsize::new(rhs_and_dest_index) else {
+                            unreachable!();
+                        };
+                        let lhs_index = rhs_and_dest_index.get() - distance;
+                        retval.push(PrefixSumOp {
+                            lhs_index,
+                            rhs_and_dest_index,
+                            row,
+                        });
+                    }
+                    row += 1;
+                    distance /= 2;
+                }
+            }
+        }
+        retval
+    }
+    pub fn ops(self, item_count: usize) -> Interned<[PrefixSumOp]> {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize(PrefixSumAlgorithm);
+        impl Memoize for MyMemoize {
+            type Input = usize;
+            type InputOwned = usize;
+            type Output = Interned<[PrefixSumOp]>;
+
+            fn inner(self, item_count: &Self::Input) -> Self::Output {
+                Intern::intern_owned(self.0.ops_impl(*item_count))
+            }
+        }
+        MyMemoize(self).get_owned(item_count)
+    }
+    pub fn run<T>(self, items: impl IntoIterator<Item = T>, f: impl FnMut(&T, &T) -> T) -> Vec<T> {
+        let mut items = Vec::from_iter(items);
+        self.run_on_slice(&mut items, f);
+        items
+    }
+    pub fn run_on_slice<T>(self, items: &mut [T], mut f: impl FnMut(&T, &T) -> T) -> &mut [T] {
+        self.ops(items.len()).into_iter().for_each(
+            |PrefixSumOp {
+                 lhs_index,
+                 rhs_and_dest_index,
+                 row: _,
+             }| {
+                items[rhs_and_dest_index.get()] =
+                    f(&items[lhs_index], &items[rhs_and_dest_index.get()]);
+            },
+        );
+        items
+    }
+    pub fn filtered_ops(
+        self,
+        item_live_out_flags: impl IntoIterator<Item = bool>,
+    ) -> Vec<PrefixSumOp> {
+        let mut item_live_out_flags = Vec::from_iter(item_live_out_flags);
+        let prefix_sum_ops = self.ops(item_live_out_flags.len());
+        let mut ops_live_flags = vec![false; prefix_sum_ops.len()];
+        for (
+            op_index,
+            &PrefixSumOp {
+                lhs_index,
+                rhs_and_dest_index,
+                row: _,
+            },
+        ) in prefix_sum_ops.iter().enumerate().rev()
+        {
+            let live = item_live_out_flags[rhs_and_dest_index.get()];
+            item_live_out_flags[lhs_index] |= live;
+            ops_live_flags[op_index] = live;
+        }
+        prefix_sum_ops
+            .into_iter()
+            .zip(ops_live_flags)
+            .filter_map(|(op, live)| live.then_some(op))
+            .collect()
+    }
+    pub fn reduce_ops(self, item_count: usize) -> Interned<[PrefixSumOp]> {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize(PrefixSumAlgorithm);
+        impl Memoize for MyMemoize {
+            type Input = usize;
+            type InputOwned = usize;
+            type Output = Interned<[PrefixSumOp]>;
+
+            fn inner(self, item_count: &Self::Input) -> Self::Output {
+                let mut item_live_out_flags = vec![false; *item_count];
+                let Some(last_item_live_out_flag) = item_live_out_flags.last_mut() else {
+                    return Interned::default();
+                };
+                *last_item_live_out_flag = true;
+                Intern::intern_owned(self.0.filtered_ops(item_live_out_flags))
+            }
+        }
+        MyMemoize(self).get_owned(item_count)
+    }
+}
+
+pub fn reduce_ops(item_count: usize) -> Interned<[PrefixSumOp]> {
+    PrefixSumAlgorithm::LowLatency.reduce_ops(item_count)
+}
+
+pub fn reduce<T>(items: impl IntoIterator<Item = T>, mut f: impl FnMut(T, T) -> T) -> Option<T> {
+    let mut items: Vec<_> = items.into_iter().map(Some).collect();
+    for op in reduce_ops(items.len()) {
+        let (Some(lhs), Some(rhs)) = (
+            items[op.lhs_index].take(),
+            items[op.rhs_and_dest_index.get()].take(),
+        ) else {
+            unreachable!();
+        };
+        items[op.rhs_and_dest_index.get()] = Some(f(lhs, rhs));
+    }
+    items.last_mut().and_then(Option::take)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    fn input_strings() -> [String; 9] {
+        std::array::from_fn(|i| String::from_utf8(vec![b'a' + i as u8]).unwrap())
+    }
+
+    #[test]
+    fn test_prefix_sum_strings() {
+        let input = input_strings();
+        let expected: Vec<String> = input
+            .iter()
+            .scan(String::new(), |l, r| {
+                *l += r;
+                Some(l.clone())
+            })
+            .collect();
+        println!("expected: {expected:?}");
+        assert_eq!(
+            *PrefixSumAlgorithm::WorkEfficient
+                .run_on_slice(&mut input.clone(), |l, r| l.to_string() + r),
+            *expected
+        );
+        assert_eq!(
+            *PrefixSumAlgorithm::LowLatency
+                .run_on_slice(&mut input.clone(), |l, r| l.to_string() + r),
+            *expected
+        );
+    }
+
+    #[test]
+    fn test_reduce_string() {
+        let input = input_strings();
+        let expected = input.clone().into_iter().reduce(|l, r| l + &r);
+        assert_eq!(reduce(input, |l, r| l + &r), expected);
+    }
+
+    fn op(lhs_index: usize, rhs_and_dest_index: usize, row: u32) -> PrefixSumOp {
+        PrefixSumOp {
+            lhs_index,
+            rhs_and_dest_index: NonZeroUsize::new(rhs_and_dest_index).expect("should be non-zero"),
+            row,
+        }
+    }
+
+    #[test]
+    fn test_reduce_ops_9() {
+        let expected = vec![
+            op(7, 8, 0),
+            op(5, 6, 0),
+            op(3, 4, 0),
+            op(1, 2, 0),
+            op(6, 8, 1),
+            op(2, 4, 1),
+            op(4, 8, 2),
+            op(0, 8, 3),
+        ];
+        println!("expected: {expected:#?}");
+        let ops = reduce_ops(9);
+        println!("ops: {ops:#?}");
+        assert_eq!(*ops, *expected);
+    }
+
+    #[test]
+    fn test_reduce_ops_8() {
+        let expected = vec![
+            op(6, 7, 0),
+            op(4, 5, 0),
+            op(2, 3, 0),
+            op(0, 1, 0),
+            op(5, 7, 1),
+            op(1, 3, 1),
+            op(3, 7, 2),
+        ];
+        println!("expected: {expected:#?}");
+        let ops = reduce_ops(8);
+        println!("ops: {ops:#?}");
+        assert_eq!(*ops, *expected);
+    }
+
+    #[test]
+    fn test_count_ones() {
+        for width in 0..=10u32 {
+            for v in 0..1u32 << width {
+                let expected = v.count_ones();
+                assert_eq!(
+                    reduce((0..width).map(|i| (v >> i) & 1), |l, r| l + r).unwrap_or(0),
+                    expected,
+                    "v={v:#X}"
+                );
+            }
+        }
+    }
+
+    #[track_caller]
+    fn test_diagram(ops: impl IntoIterator<Item = PrefixSumOp>, item_count: usize, expected: &str) {
+        let text = PrefixSumOp::diagram_with_config(
+            ops,
+            item_count,
+            DiagramConfig {
+                plus: Cow::Borrowed("@"),
+                ..Default::default()
+            },
+        );
+        println!("text:\n{text}\n");
+        assert_eq!(text, expected);
+    }
+
+    #[test]
+    fn test_work_efficient_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            PrefixSumAlgorithm::WorkEfficient.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |
+ |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |
+ | \|  | \|  | \|  | \|  | \|  | \|  | \|  | \|
+ |  @  |  @  |  @  |  @  |  @  |  @  |  @  |  @
+ |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |
+ |  | \|  |  |  | \|  |  |  | \|  |  |  | \|  |
+ |  |  X  |  |  |  X  |  |  |  X  |  |  |  X  |
+ |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |
+ |  |  | \|  |  |  | \|  |  |  | \|  |  |  | \|
+ |  |  |  @  |  |  |  @  |  |  |  @  |  |  |  @
+ |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  X  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  | \|  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  X  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  | \|  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  @  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  X  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  ●  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  ●  |  |  |  ●  |  |  |  @  |  |  |  |
+ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  | \|  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  X  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  | \|  |  |  | \|  |  |
+ |  ●  |  ●  |  @  |  ●  |  @  |  ●  |  @  |  |
+ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |
+ |  | \|  | \|  | \|  | \|  | \|  | \|  | \|  |
+ |  |  @  |  @  |  @  |  @  |  @  |  @  |  @  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_low_latency_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            PrefixSumAlgorithm::LowLatency.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  |
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ | \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  @  @  @  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ | \| \| \| \| \| \| \| \| \| \| \| \| \| \|  |
+ |  X  X  X  X  X  X  X  X  X  X  X  X  X  X  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  | \| \| \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  ●  @  @  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |
+ | \| \| \| \| \| \| \| \| \| \| \| \|  |  |  |
+ |  X  X  X  X  X  X  X  X  X  X  X  X  |  |  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |
+ |  | \| \| \| \| \| \| \| \| \| \| \| \|  |  |
+ |  |  X  X  X  X  X  X  X  X  X  X  X  X  |  |
+ |  |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ |  |  | \| \| \| \| \| \| \| \| \| \| \| \|  |
+ |  |  |  X  X  X  X  X  X  X  X  X  X  X  X  |
+ |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  |  |  | \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  ●  ●  ●  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |  |  |
+ | \| \| \| \| \| \| \| \|  |  |  |  |  |  |  |
+ |  X  X  X  X  X  X  X  X  |  |  |  |  |  |  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |  |
+ |  | \| \| \| \| \| \| \| \|  |  |  |  |  |  |
+ |  |  X  X  X  X  X  X  X  X  |  |  |  |  |  |
+ |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |
+ |  |  | \| \| \| \| \| \| \| \|  |  |  |  |  |
+ |  |  |  X  X  X  X  X  X  X  X  |  |  |  |  |
+ |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |
+ |  |  |  | \| \| \| \| \| \| \| \|  |  |  |  |
+ |  |  |  |  X  X  X  X  X  X  X  X  |  |  |  |
+ |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |
+ |  |  |  |  | \| \| \| \| \| \| \| \|  |  |  |
+ |  |  |  |  |  X  X  X  X  X  X  X  X  |  |  |
+ |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |
+ |  |  |  |  |  | \| \| \| \| \| \| \| \|  |  |
+ |  |  |  |  |  |  X  X  X  X  X  X  X  X  |  |
+ |  |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ |  |  |  |  |  |  | \| \| \| \| \| \| \| \|  |
+ |  |  |  |  |  |  |  X  X  X  X  X  X  X  X  |
+ |  |  |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  |  |  |  |  |  |  | \| \| \| \| \| \| \| \|
+ |  |  |  |  |  |  |  |  @  @  @  @  @  @  @  @
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_work_efficient_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            PrefixSumAlgorithm::WorkEfficient.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  |
+ |\ |  |\ |  |\ |  |\ |  |
+ | \|  | \|  | \|  | \|  |
+ |  @  |  @  |  @  |  @  |
+ |  |\ |  |  |  |\ |  |  |
+ |  | \|  |  |  | \|  |  |
+ |  |  X  |  |  |  X  |  |
+ |  |  |\ |  |  |  |\ |  |
+ |  |  | \|  |  |  | \|  |
+ |  |  |  @  |  |  |  @  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  ●  |  |  |  @  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  ●  |  ●  |  @  |  ●  |
+ |  |\ |  |\ |  |\ |  |\ |
+ |  | \|  | \|  | \|  | \|
+ |  |  @  |  @  |  @  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_low_latency_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            PrefixSumAlgorithm::LowLatency.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ ●  ●  ●  ●  ●  ●  ●  ●  |
+ |\ |\ |\ |\ |\ |\ |\ |\ |
+ | \| \| \| \| \| \| \| \|
+ ●  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |  |
+ | \| \| \| \| \| \| \|  |
+ |  X  X  X  X  X  X  X  |
+ |  |\ |\ |\ |\ |\ |\ |\ |
+ |  | \| \| \| \| \| \| \|
+ ●  ●  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |  |  |  |
+ | \| \| \| \| \|  |  |  |
+ |  X  X  X  X  X  |  |  |
+ |  |\ |\ |\ |\ |\ |  |  |
+ |  | \| \| \| \| \|  |  |
+ |  |  X  X  X  X  X  |  |
+ |  |  |\ |\ |\ |\ |\ |  |
+ |  |  | \| \| \| \| \|  |
+ |  |  |  X  X  X  X  X  |
+ |  |  |  |\ |\ |\ |\ |\ |
+ |  |  |  | \| \| \| \| \|
+ ●  |  |  |  @  @  @  @  @
+ |\ |  |  |  |  |  |  |  |
+ | \|  |  |  |  |  |  |  |
+ |  X  |  |  |  |  |  |  |
+ |  |\ |  |  |  |  |  |  |
+ |  | \|  |  |  |  |  |  |
+ |  |  X  |  |  |  |  |  |
+ |  |  |\ |  |  |  |  |  |
+ |  |  | \|  |  |  |  |  |
+ |  |  |  X  |  |  |  |  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_reduce_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            reduce_ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |
+ |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |
+ | \|  | \|  | \|  | \|  | \|  | \|  | \|  | \|
+ |  @  |  @  |  @  |  @  |  @  |  @  |  @  |  @
+ |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |
+ |  | \|  |  |  | \|  |  |  | \|  |  |  | \|  |
+ |  |  X  |  |  |  X  |  |  |  X  |  |  |  X  |
+ |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |
+ |  |  | \|  |  |  | \|  |  |  | \|  |  |  | \|
+ |  |  |  @  |  |  |  @  |  |  |  @  |  |  |  @
+ |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  X  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  | \|  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  X  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  | \|  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  @  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  X  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_reduce_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            reduce_ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ |  ●  |  ●  |  ●  |  ●  |
+ |  |\ |  |\ |  |\ |  |\ |
+ |  | \|  | \|  | \|  | \|
+ |  |  @  |  @  |  @  |  @
+ |  |  |\ |  |  |  |\ |  |
+ |  |  | \|  |  |  | \|  |
+ |  |  |  X  |  |  |  X  |
+ |  |  |  |\ |  |  |  |\ |
+ |  |  |  | \|  |  |  | \|
+ |  |  |  |  @  |  |  |  @
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ ●  |  |  |  |  |  |  |  @
+ |\ |  |  |  |  |  |  |  |
+ | \|  |  |  |  |  |  |  |
+ |  X  |  |  |  |  |  |  |
+ |  |\ |  |  |  |  |  |  |
+ |  | \|  |  |  |  |  |  |
+ |  |  X  |  |  |  |  |  |
+ |  |  |\ |  |  |  |  |  |
+ |  |  | \|  |  |  |  |  |
+ |  |  |  X  |  |  |  |  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+}
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 82d3f1e..ac08a64 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -49,6 +49,18 @@ impl<T: Type> ReadyValid<T> {
     }
 }
 
+/// This debug port is only meant to assist the formal proof of the queue.
+#[cfg(test)]
+#[doc(hidden)]
+#[hdl]
+pub struct QueueDebugPort<Element, Index> {
+    #[hdl(flip)]
+    index_to_check: Index,
+    stored: Element,
+    inp_index: Index,
+    out_index: Index,
+}
+
 #[hdl_module]
 pub fn queue<T: Type>(
     ty: T,
@@ -178,6 +190,22 @@ pub fn queue<T: Type>(
             }
         }
     }
+    // These debug ports expose some internal state during the Induction phase
+    // of Formal Verification. They are not present in normal use.
+    #[cfg(test)]
+    {
+        #[hdl]
+        let dbg: QueueDebugPort<T, UInt> = m.output(QueueDebugPort[ty][index_ty]);
+        // read the memory word currently stored at some fixed index
+        let debug_port = mem.new_read_port();
+        connect(debug_port.addr, dbg.index_to_check);
+        connect(debug_port.en, true);
+        connect(debug_port.clk, cd.clk);
+        connect(dbg.stored, debug_port.data);
+        // also expose the current read and write indices
+        connect(dbg.inp_index, inp_index_reg);
+        connect(dbg.out_index, out_index_reg);
+    }
 }
 
 #[cfg(test)]
@@ -196,13 +224,23 @@ mod tests {
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
             FormalMode::Prove,
-            14,
+            2,
             None,
             ExportOptions {
                 simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
                 ..ExportOptions::default()
             },
         );
+        /// Formal verification of the FIFO queue
+        ///
+        /// The strategy derives from the observation that, if we filter its
+        /// input and output streams to consider just one in every N reads and
+        /// writes (where N is the FIFO capacity), then the FIFO effectively
+        /// behaves as a one-entry FIFO.
+        ///
+        /// In particular, any counterexample of the full FIFO behaving badly
+        /// will also be caught by one of the filtered versions (one which
+        /// happens to be in phase with the offending input or output).
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
             #[hdl]
@@ -217,6 +255,8 @@ mod tests {
                     rst: formal_reset().to_reset(),
                 },
             );
+
+            // random input data
             #[hdl]
             let inp_data: HdlOption<UInt<8>> = wire();
             #[hdl]
@@ -225,16 +265,26 @@ mod tests {
             } else {
                 connect(inp_data, HdlNone());
             }
+
+            // assert output ready at random
             #[hdl]
             let out_ready: Bool = wire();
             connect(out_ready, any_seq(Bool));
-            let index_ty: UInt<32> = UInt::TYPE;
+
+            // The current number of elements in the FIFO ranges from zero to
+            // maximum capacity, inclusive.
+            let count_ty = UInt::range_inclusive(0..=capacity.get());
+            // type for counters that wrap around at the FIFO capacity
+            let index_ty = UInt::range(0..capacity.get());
+
+            // among all entries of the FIFO internal circular memory, choose
+            // one at random to check
             #[hdl]
-            let index_to_check = wire();
+            let index_to_check = wire(index_ty);
             connect(index_to_check, any_const(index_ty));
-            let index_max = !index_ty.zero();
-            // we saturate at index_max, so only check indexes where we properly maintain position
-            hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
+            hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), "");
+
+            // instantiate and connect the queue
             #[hdl]
             let dut = instance(queue(
                 UInt[ConstUsize::<8>],
@@ -245,109 +295,172 @@ mod tests {
             connect(dut.cd, cd);
             connect(dut.inp.data, inp_data);
             connect(dut.out.ready, out_ready);
-            hdl_assume(
-                clk,
-                index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
-                "",
-            );
 
+            // Keep an independent count of words in the FIFO. Ensure that
+            // it's always correct, and never overflows.
             #[hdl]
-            let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
-            #[hdl]
-            let next_expected_count = wire();
-            connect(next_expected_count, expected_count_reg);
-            connect(expected_count_reg, next_expected_count);
+            let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero());
             #[hdl]
             if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg + 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), "");
+                connect_any(expected_count_reg, expected_count_reg + 1u8);
             } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg - 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
+                connect_any(expected_count_reg, expected_count_reg - 1u8);
             }
-            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
-
-            #[hdl]
-            let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_out_ready_reg,
-                (prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
-            );
-            #[hdl]
-            let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_inp_valid_reg,
-                (prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
-            );
-            hdl_assume(
-                clk,
-                (prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
-                "",
-            );
+            hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), "");
 
+            // keep an independent write index into the FIFO's circular buffer
             #[hdl]
             let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
+            if ReadyValid::firing(dut.inp) {
                 #[hdl]
-                if inp_index_reg.cmp_lt(index_max) {
+                if inp_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(inp_index_reg, inp_index_reg + 1u8);
-                    #[hdl]
-                    if inp_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_inp_data_reg, data);
-                    }
+                } else {
+                    connect_any(inp_index_reg, 0_hdl_u0);
                 }
             }
 
-            #[hdl]
-            if inp_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
-            }
-
+            // keep an independent read index into the FIFO's circular buffer
             #[hdl]
             let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
+            if ReadyValid::firing(dut.out) {
                 #[hdl]
-                if out_index_reg.cmp_lt(index_max) {
+                if out_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(out_index_reg, out_index_reg + 1u8);
+                } else {
+                    connect_any(out_index_reg, 0_hdl_u0);
+                }
+            }
+
+            // filter the input data stream, predicated by the read index
+            // matching the chosen position in the FIFO's circular buffer
+            #[hdl]
+            let inp_index_matches = wire();
+            connect(inp_index_matches, inp_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let inp_firing_data = wire();
+            connect(inp_firing_data, HdlNone());
+            #[hdl]
+            if inp_index_matches {
+                connect(inp_firing_data, ReadyValid::firing_data(dut.inp));
+            }
+
+            // filter the output data stream, predicated by the write index
+            // matching the chosen position in the FIFO's circular buffer
+            #[hdl]
+            let out_index_matches = wire();
+            connect(out_index_matches, out_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let out_firing_data = wire();
+            connect(out_firing_data, HdlNone());
+            #[hdl]
+            if out_index_matches {
+                connect(out_firing_data, ReadyValid::firing_data(dut.out));
+            }
+
+            // Implement a one-entry FIFO and ensure its equivalence to the
+            // filtered FIFO.
+            //
+            // the holding register for our one-entry FIFO
+            #[hdl]
+            let stored_reg = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            match stored_reg {
+                // If the holding register is empty...
+                HdlNone => {
                     #[hdl]
-                    if out_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_out_data_reg, data);
+                    match inp_firing_data {
+                        // ... and we are not receiving data, then we must not
+                        // transmit any data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""),
+                        // If we are indeed receiving some data...
+                        HdlSome(data_in) => {
+                            #[hdl]
+                            match out_firing_data {
+                                // ... and transmitting at the same time, we
+                                // must be transmitting the input data itself,
+                                // since the holding register is empty.
+                                HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""),
+                                // If we are receiving, but not transmitting,
+                                // store the received data in the holding
+                                // register.
+                                HdlNone => connect(stored_reg, HdlSome(data_in)),
+                            }
+                        }
+                    }
+                }
+                // If there is some value stored in the holding register...
+                HdlSome(stored) => {
+                    #[hdl]
+                    match out_firing_data {
+                        // ... and we are not transmitting it, we cannot
+                        // receive any more data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""),
+                        // If we are transmitting a previously stored value...
+                        HdlSome(data_out) => {
+                            // ... it must be the same data we stored earlier.
+                            hdl_assert(clk, data_out.cmp_eq(stored), "");
+                            // Also, accept new data, if any. Otherwise,
+                            // let the holding register become empty.
+                            connect(stored_reg, inp_firing_data);
+                        }
                     }
                 }
             }
 
+            // from now on, some extra assertions in order to pass induction
+
+            // sync the holding register, when it's occupied, to the
+            // corresponding entry in the FIFO's circular buffer
+            connect(dut.dbg.index_to_check, index_to_check);
             #[hdl]
-            if out_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
+            if let HdlSome(stored) = stored_reg {
+                hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
             }
 
-            hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
+            // sync the read and write indices
+            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
+            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
 
+            // the indices should never go past the capacity, but induction
+            // doesn't know that...
+            hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), "");
+            hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), "");
+
+            // strongly constrain the state of the holding register
+            //
+            // The holding register is full if and only if the corresponding
+            // FIFO entry was written to and not yet read. In other words, if
+            // the number of pending reads until the chosen entry is read out
+            // is greater than the current FIFO count, then the entry couldn't
+            // be in the FIFO in the first place.
             #[hdl]
-            if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
-                    "",
-                );
+            let pending_reads: UInt = wire(index_ty);
+            // take care of wrap-around when subtracting indices, add the
+            // capacity amount to keep the result positive if necessary
+            #[hdl]
+            if index_to_check.cmp_ge(out_index_reg) {
+                connect(pending_reads, index_to_check - out_index_reg);
             } else {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
-                    "",
+                connect(
+                    pending_reads,
+                    index_to_check + capacity.get() - out_index_reg,
                 );
             }
-
+            // check whether the chosen entry is in the FIFO
             #[hdl]
-            if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
-            }
+            let expected_stored: Bool = wire();
+            connect(expected_stored, pending_reads.cmp_lt(dut.count));
+            // sync with the state of the holding register
+            hdl_assert(
+                clk,
+                expected_stored.cmp_eq(HdlOption::is_some(stored_reg)),
+                "",
+            );
         }
     }
 
@@ -430,4 +543,24 @@ mod tests {
     fn test_4_true_true() {
         test_queue(NonZero::new(4).unwrap(), true, true);
     }
+
+    #[test]
+    fn test_many_false_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, false);
+    }
+
+    #[test]
+    fn test_many_false_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, true);
+    }
+
+    #[test]
+    fn test_many_true_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, false);
+    }
+
+    #[test]
+    fn test_many_true_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, true);
+    }
 }
diff --git a/crates/fayalite/src/util/test_hasher.rs b/crates/fayalite/src/util/test_hasher.rs
new file mode 100644
index 0000000..20df5b7
--- /dev/null
+++ b/crates/fayalite/src/util/test_hasher.rs
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+#![cfg(feature = "unstable-test-hasher")]
+
+use std::{
+    fmt::Write as _,
+    hash::{BuildHasher, Hash, Hasher},
+    io::Write as _,
+    marker::PhantomData,
+    sync::LazyLock,
+};
+
+type BoxDynHasher = Box<dyn Hasher + Send + Sync>;
+type BoxDynBuildHasher = Box<dyn DynBuildHasherTrait + Send + Sync>;
+type BoxDynMakeBuildHasher = Box<dyn Fn() -> BoxDynBuildHasher + Send + Sync>;
+
+trait TryGetDynBuildHasher: Copy {
+    type Type;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher>;
+}
+
+impl<T> TryGetDynBuildHasher for PhantomData<T> {
+    type Type = T;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher> {
+        None
+    }
+}
+
+impl<T: Default + BuildHasher<Hasher: Send + Sync + 'static> + Send + Sync + 'static + Clone>
+    TryGetDynBuildHasher for &'_ PhantomData<T>
+{
+    type Type = T;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher> {
+        Some(Box::new(|| Box::<DynBuildHasher<T>>::default()))
+    }
+}
+
+#[derive(Default, Clone)]
+struct DynBuildHasher<T>(T);
+
+trait DynBuildHasherTrait: BuildHasher<Hasher = BoxDynHasher> {
+    fn clone_dyn_build_hasher(&self) -> BoxDynBuildHasher;
+}
+
+impl<BH: BuildHasher<Hasher: Send + Sync + 'static>> BuildHasher for DynBuildHasher<BH> {
+    type Hasher = BoxDynHasher;
+
+    fn build_hasher(&self) -> Self::Hasher {
+        Box::new(self.0.build_hasher())
+    }
+
+    fn hash_one<T: Hash>(&self, x: T) -> u64 {
+        self.0.hash_one(x)
+    }
+}
+
+impl<BH> DynBuildHasherTrait for DynBuildHasher<BH>
+where
+    Self: Clone + BuildHasher<Hasher = BoxDynHasher> + Send + Sync + 'static,
+{
+    fn clone_dyn_build_hasher(&self) -> BoxDynBuildHasher {
+        Box::new(self.clone())
+    }
+}
+
+pub struct DefaultBuildHasher(BoxDynBuildHasher);
+
+impl Clone for DefaultBuildHasher {
+    fn clone(&self) -> Self {
+        DefaultBuildHasher(self.0.clone_dyn_build_hasher())
+    }
+}
+
+const ENV_VAR_NAME: &'static str = "FAYALITE_TEST_HASHER";
+
+struct EnvVarValue {
+    key: &'static str,
+    try_get_make_build_hasher: fn() -> Option<BoxDynMakeBuildHasher>,
+    description: &'static str,
+}
+
+macro_rules! env_var_value {
+    (
+        key: $key:literal,
+        build_hasher: $build_hasher:ty,
+        description: $description:literal,
+    ) => {
+        EnvVarValue {
+            key: $key,
+            try_get_make_build_hasher: || {
+                // use rust method resolution to detect if $build_hasher is usable
+                // (e.g. hashbrown's hasher won't be usable without the right feature enabled)
+                (&PhantomData::<DynBuildHasher<$build_hasher>>).try_get_make_build_hasher()
+            },
+            description: $description,
+        }
+    };
+}
+
+#[derive(Default)]
+struct AlwaysZeroHasher;
+
+impl Hasher for AlwaysZeroHasher {
+    fn write(&mut self, _bytes: &[u8]) {}
+    fn finish(&self) -> u64 {
+        0
+    }
+}
+
+const ENV_VAR_VALUES: &'static [EnvVarValue] = &[
+    env_var_value! {
+        key: "std",
+        build_hasher: std::hash::RandomState,
+        description: "use std::hash::RandomState",
+    },
+    env_var_value! {
+        key: "hashbrown",
+        build_hasher: hashbrown::DefaultHashBuilder,
+        description: "use hashbrown's DefaultHashBuilder",
+    },
+    env_var_value! {
+        key: "always_zero",
+        build_hasher: std::hash::BuildHasherDefault<AlwaysZeroHasher>,
+        description: "use a hasher that always returns 0 for all hashes,\n    \
+        this is useful for checking that PartialEq impls are correct",
+    },
+];
+
+fn report_bad_env_var(msg: impl std::fmt::Display) -> ! {
+    let mut msg = format!("{ENV_VAR_NAME}: {msg}\n");
+    for &EnvVarValue {
+        key,
+        try_get_make_build_hasher,
+        description,
+    } in ENV_VAR_VALUES
+    {
+        let availability = match try_get_make_build_hasher() {
+            Some(_) => "available",
+            None => "unavailable",
+        };
+        writeln!(msg, "{key}: ({availability})\n    {description}").expect("can't fail");
+    }
+    std::io::stderr()
+        .write_all(msg.as_bytes())
+        .expect("should be able to write to stderr");
+    std::process::abort();
+}
+
+impl Default for DefaultBuildHasher {
+    fn default() -> Self {
+        static DEFAULT_FN: LazyLock<BoxDynMakeBuildHasher> = LazyLock::new(|| {
+            let var = std::env::var_os(ENV_VAR_NAME);
+            let var = var.as_deref().unwrap_or("std".as_ref());
+            for &EnvVarValue {
+                key,
+                try_get_make_build_hasher,
+                description: _,
+            } in ENV_VAR_VALUES
+            {
+                if var.as_encoded_bytes().eq_ignore_ascii_case(key.as_bytes()) {
+                    return try_get_make_build_hasher().unwrap_or_else(|| {
+                        report_bad_env_var(format_args!(
+                            "unavailable hasher: {key} (is the appropriate feature enabled?)"
+                        ));
+                    });
+                }
+            }
+            report_bad_env_var(format_args!("unrecognized hasher: {var:?}"));
+        });
+        Self(DEFAULT_FN())
+    }
+}
+
+pub struct DefaultHasher(BoxDynHasher);
+
+impl BuildHasher for DefaultBuildHasher {
+    type Hasher = DefaultHasher;
+
+    fn build_hasher(&self) -> Self::Hasher {
+        DefaultHasher(self.0.build_hasher())
+    }
+}
+
+impl Hasher for DefaultHasher {
+    fn finish(&self) -> u64 {
+        self.0.finish()
+    }
+
+    fn write(&mut self, bytes: &[u8]) {
+        self.0.write(bytes)
+    }
+
+    fn write_u8(&mut self, i: u8) {
+        self.0.write_u8(i)
+    }
+
+    fn write_u16(&mut self, i: u16) {
+        self.0.write_u16(i)
+    }
+
+    fn write_u32(&mut self, i: u32) {
+        self.0.write_u32(i)
+    }
+
+    fn write_u64(&mut self, i: u64) {
+        self.0.write_u64(i)
+    }
+
+    fn write_u128(&mut self, i: u128) {
+        self.0.write_u128(i)
+    }
+
+    fn write_usize(&mut self, i: usize) {
+        self.0.write_usize(i)
+    }
+
+    fn write_i8(&mut self, i: i8) {
+        self.0.write_i8(i)
+    }
+
+    fn write_i16(&mut self, i: i16) {
+        self.0.write_i16(i)
+    }
+
+    fn write_i32(&mut self, i: i32) {
+        self.0.write_i32(i)
+    }
+
+    fn write_i64(&mut self, i: i64) {
+        self.0.write_i64(i)
+    }
+
+    fn write_i128(&mut self, i: i128) {
+        self.0.write_i128(i)
+    }
+
+    fn write_isize(&mut self, i: isize) {
+        self.0.write_isize(i)
+    }
+}
diff --git a/crates/fayalite/src/wire.rs b/crates/fayalite/src/wire.rs
index 85ab342..51f8cf7 100644
--- a/crates/fayalite/src/wire.rs
+++ b/crates/fayalite/src/wire.rs
@@ -37,6 +37,18 @@ impl<T: Type> Wire<T> {
             ty: ty.canonical(),
         }
     }
+    pub fn from_canonical(v: Wire<CanonicalType>) -> Self {
+        let Wire {
+            name,
+            source_location,
+            ty,
+        } = v;
+        Self {
+            name,
+            source_location,
+            ty: T::from_canonical(ty),
+        }
+    }
     pub fn ty(&self) -> T {
         self.ty
     }
diff --git a/crates/fayalite/tests/formal.rs b/crates/fayalite/tests/formal.rs
index 46b8292..65264dc 100644
--- a/crates/fayalite/tests/formal.rs
+++ b/crates/fayalite/tests/formal.rs
@@ -7,12 +7,13 @@ use fayalite::{
     clock::{Clock, ClockDomain},
     expr::{CastTo, HdlPartialEq},
     firrtl::ExportOptions,
-    formal::{any_seq, formal_reset, hdl_assert, hdl_assume},
-    hdl_module,
-    int::{Bool, UInt},
-    module::{connect, connect_any, reg_builder, wire},
+    formal::{any_const, any_seq, formal_reset, hdl_assert, hdl_assume},
+    hdl, hdl_module,
+    int::{Bool, DynSize, Size, UInt, UIntType},
+    module::{connect, connect_any, instance, memory, reg_builder, wire},
     reset::ToReset,
     testing::assert_formal,
+    ty::StaticType,
 };
 
 /// Test hidden state
@@ -131,3 +132,164 @@ mod hidden_state {
         );
     }
 }
+
+/// Formal verification of designs containing memories
+///
+/// There is a trick for memories, described in the [Zipcpu blog].
+/// First, select a fixed but arbitrary memory address, monitoring all reads
+/// and writes made to it. Then, assert that anything read from that location
+/// matches the last stored value.
+///
+/// A difficulty for induction is that the memory represents [hidden_state]. A
+/// solution is to include an additional read port to the memory and assert
+/// that the memory location effectively contains the last stored value.
+/// This additional debug port is present only to assist the proof and is
+/// unused (optimized out) in actual use.
+///
+/// [Zipcpu blog]: <https://zipcpu.com/zipcpu/2018/07/13/memories.html>
+mod memory {
+    use super::*;
+
+    /// Test a simple 8-bit SRAM model
+    #[test]
+    fn test_sram() {
+        #[hdl]
+        struct WritePort<AddrWidth: Size> {
+            addr: UIntType<AddrWidth>,
+            data: UInt<8>,
+            en: Bool,
+        }
+        #[hdl]
+        struct ReadPort<AddrWidth: Size> {
+            addr: UIntType<AddrWidth>,
+            #[hdl(flip)]
+            data: UInt<8>,
+        }
+        /// This debug port is only meant to assist the proof.
+        /// For normal use in a design, a wrapper could be provided,
+        /// omitting this port.
+        /// The implementation is forbidden to use any information
+        /// provided on this port in its internal workings.
+        #[hdl]
+        struct DebugPort<AddrWidth: Size> {
+            selected: UIntType<AddrWidth>,
+            stored: UInt<8>,
+            wrote: Bool,
+        }
+        /// simple 1R1W SRAM model (one asynchronous read port and one
+        /// independent write port) with `n`-bit address width
+        #[hdl_module]
+        fn example_sram(n: usize) {
+            #[hdl]
+            let wr: WritePort<DynSize> = m.input(WritePort[n]);
+            #[hdl]
+            let rd: ReadPort<DynSize> = m.input(ReadPort[n]);
+            #[hdl]
+            let cd: ClockDomain = m.input();
+
+            // declare and connect the backing memory
+            #[hdl]
+            let mut mem = memory();
+            mem.depth(1 << n);
+            let read_port = mem.new_read_port();
+            let write_port = mem.new_write_port();
+            connect(write_port.clk, cd.clk);
+            connect(write_port.addr, wr.addr);
+            connect(write_port.en, wr.en);
+            connect(write_port.data, wr.data);
+            connect(write_port.mask, true);
+            connect(read_port.clk, cd.clk);
+            connect(read_port.addr, rd.addr);
+            connect(read_port.en, true);
+            connect(rd.data, read_port.data);
+
+            // To assist with induction, ensure that the chosen memory location
+            // really contains, always, the last value written to it.
+            #[hdl]
+            let dbg: DebugPort<DynSize> = m.input(DebugPort[n]);
+            let debug_port = mem.new_read_port();
+            connect(debug_port.en, true);
+            connect(debug_port.clk, cd.clk);
+            connect(debug_port.addr, dbg.selected);
+            #[hdl]
+            if dbg.wrote {
+                hdl_assert(cd.clk, debug_port.data.cmp_eq(dbg.stored), "");
+                // Try commenting out the assert above, induction will fail.
+                // Opening the trace, it can be seen that the memory contents
+                // and the stored value don't match, which is an unreachable
+                // state. By asserting the above, it will become invalid
+                // as well, so induction will skip this kind of situation.
+            }
+        }
+
+        /// formal verification of the SRAM module, parametrized by the
+        /// address bit-width
+        #[hdl_module]
+        fn test_module(n: usize) {
+            #[hdl]
+            let clk: Clock = m.input();
+            let cd = #[hdl]
+            ClockDomain {
+                clk,
+                rst: formal_reset().to_reset(),
+            };
+
+            // instantiate the SRAM model, connecting its inputs to
+            // a random sequence
+            #[hdl]
+            let rd: ReadPort<DynSize> = wire(ReadPort[n]);
+            connect(rd.addr, any_seq(UInt[n]));
+            #[hdl]
+            let wr: WritePort<DynSize> = wire(WritePort[n]);
+            connect(wr.addr, any_seq(UInt[n]));
+            connect(wr.data, any_seq(UInt::<8>::TYPE));
+            connect(wr.en, any_seq(Bool));
+            #[hdl]
+            let dut = instance(example_sram(n));
+            connect(dut.cd, cd);
+            connect(dut.rd, rd);
+            connect(dut.wr, wr);
+
+            // select a fixed but arbitrary test address
+            #[hdl]
+            let selected = wire(UInt[n]);
+            connect(selected, any_const(UInt[n]));
+            // store the last value written to that address
+            #[hdl]
+            let stored: UInt<8> = reg_builder().clock_domain(cd).reset(0u8);
+            // since memories are not initialized, track whether we wrote to the
+            // memory at least once
+            #[hdl]
+            let wrote: Bool = reg_builder().clock_domain(cd).reset(false);
+            // on a write, capture the last written value
+            #[hdl]
+            if wr.en & wr.addr.cmp_eq(selected) {
+                connect(stored, wr.data);
+                connect(wrote, true);
+            }
+            // on a read, assert that the read value is the same which was stored
+            #[hdl]
+            if rd.addr.cmp_eq(selected) & wrote {
+                hdl_assert(clk, rd.data.cmp_eq(stored), "");
+            }
+
+            // to assist induction, pass our state to the underlying instance
+            let dbg = #[hdl]
+            DebugPort {
+                selected,
+                stored,
+                wrote,
+            };
+            connect(dut.dbg, dbg);
+        }
+
+        assert_formal(
+            "sram",
+            test_module(8),
+            FormalMode::Prove,
+            2,
+            None,
+            ExportOptions::default(),
+        );
+    }
+}
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index b191016..8802fd4 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -4,11 +4,17 @@ use fayalite::{
     bundle::BundleType,
     enum_::EnumType,
     int::{BoolOrIntType, IntType},
+    phantom_const::PhantomConst,
     prelude::*,
     ty::StaticType,
 };
 use std::marker::PhantomData;
 
+#[hdl(outline_generated)]
+pub struct MyConstSize<V: Size> {
+    pub size: PhantomConst<UIntType<V>>,
+}
+
 #[hdl(outline_generated)]
 pub struct S<T, Len: Size, T2> {
     pub a: T,
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 222f7ba..c2dc24e 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -1,8 +1,14 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
+    assert_export_firrtl,
+    firrtl::ExportOptions,
+    int::{UIntInRange, UIntInRangeInclusive},
+    intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind,
+    prelude::*,
+    reset::ResetType,
+    ty::StaticType,
 };
 use serde_json::json;
 
@@ -190,10 +196,14 @@ circuit check_array_repeat:
     };
 }
 
+pub trait UnknownTrait {}
+
+impl<T: ?Sized> UnknownTrait for T {}
+
 #[hdl_module(outline_generated)]
 pub fn check_skipped_generics<T, #[hdl(skip)] U, const N: usize, #[hdl(skip)] const M: usize>(v: U)
 where
-    T: StaticType,
+    T: StaticType + UnknownTrait,
     ConstUsize<N>: KnownSize,
     U: std::fmt::Display,
 {
@@ -375,18 +385,18 @@ circuit check_written_inside_both_if_else:
     };
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct<T> {
     pub a: T,
     pub b: UInt<8>,
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct2 {
     pub v: UInt<8>,
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct3 {}
 
 #[hdl_module(outline_generated)]
@@ -4026,3 +4036,598 @@ circuit check_enum_connect_any:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_deduce_resets<T: ResetType>(ty: T) {
+    #[hdl]
+    let cd: ClockDomain<T> = m.input(ClockDomain[ty]);
+    #[hdl]
+    let my_reg = reg_builder().reset(0u8).clock_domain(cd);
+    #[hdl]
+    let u8_in: UInt<8> = m.input();
+    connect(my_reg, u8_in);
+    #[hdl]
+    let u8_out: UInt<8> = m.output();
+    connect(u8_out, my_reg);
+    #[hdl]
+    let enum_in: OneOfThree<Reset, AsyncReset, SyncReset> = m.input();
+    #[hdl]
+    let enum_out: OneOfThree<Reset, AsyncReset, SyncReset> = m.output();
+    #[hdl]
+    let reset_out: Reset = m.output();
+    connect(reset_out, cd.rst.to_reset());
+    #[hdl]
+    match enum_in {
+        OneOfThree::<_, _, _>::A(v) => {
+            connect(
+                enum_out,
+                OneOfThree[Reset][AsyncReset][SyncReset].A(cd.rst.to_reset()),
+            );
+            connect(reset_out, v);
+        }
+        OneOfThree::<_, _, _>::B(v) => {
+            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].B(v))
+        }
+        OneOfThree::<_, _, _>::C(v) => {
+            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].C(v))
+        }
+    }
+}
+
+#[test]
+fn test_deduce_resets() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_deduce_resets(Reset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: Reset}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    fayalite::module::transform::deduce_resets::deduce_resets(m.canonical().intern_sized(), false)
+        .unwrap_err();
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        true,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = check_deduce_resets(SyncReset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        false,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = check_deduce_resets(AsyncReset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: AsyncReset}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        false,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: AsyncReset}
+    type Ty1 = {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: AsyncReset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}
+
+// intentionally not outline_generated to ensure we get correct macro hygiene
+#[hdl_module]
+pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
+    #[cfg(cfg_false_for_tests)] a: A,
+    #[cfg(cfg_true_for_tests)] b: B,
+) {
+    #[hdl]
+    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
+        #[cfg(cfg_false_for_tests)]
+        a: A,
+        #[cfg(cfg_true_for_tests)]
+        b: B,
+    }
+    #[hdl]
+    #[cfg(cfg_false_for_tests)]
+    let i_a: A = m.input(a);
+    #[hdl]
+    #[cfg(cfg_true_for_tests)]
+    let i_b: B = m.input(b);
+    #[hdl]
+    let w: S<UInt<8>> = wire();
+    #[cfg(cfg_false_for_tests)]
+    {
+        #[hdl]
+        let o_a: A = m.output(a);
+        connect(o_a, w.a.cast_bits_to(a));
+        connect_any(w.a, i_a.cast_to_bits());
+    }
+    #[cfg(cfg_true_for_tests)]
+    {
+        #[hdl]
+        let o_b: B = m.output(b);
+        connect(o_b, w.b.cast_bits_to(b));
+        connect_any(w.b, i_b.cast_to_bits());
+    }
+}
+
+#[test]
+fn test_cfgs() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_cfgs(UInt[8]);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
+circuit check_cfgs:
+    type Ty0 = {b: UInt<8>}
+    module check_cfgs: @[the_test_file.rs 9962:1]
+        input i_b: UInt<8> @[the_test_file.rs 9979:20]
+        output o_b: UInt<8> @[the_test_file.rs 9992:24]
+        wire w: Ty0 @[the_test_file.rs 9981:25]
+        connect o_b, w.b @[the_test_file.rs 9993:9]
+        connect w.b, i_b @[the_test_file.rs 9994:9]
+",
+    };
+}
+
+#[hdl_module(outline_generated)]
+pub fn check_let_patterns() {
+    #[hdl]
+    let tuple_in: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let (tuple_0, tuple_1, tuple_2) = tuple_in;
+    #[hdl]
+    let tuple_0_out: UInt<1> = m.output();
+    connect(tuple_0_out, tuple_0);
+    #[hdl]
+    let tuple_1_out: SInt<1> = m.output();
+    connect(tuple_1_out, tuple_1);
+    #[hdl]
+    let tuple_2_out: Bool = m.output();
+    connect(tuple_2_out, tuple_2);
+
+    #[hdl]
+    let test_struct_in: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let TestStruct::<_> { a, b } = test_struct_in;
+    #[hdl]
+    let test_struct_a_out: SInt<8> = m.output();
+    connect(test_struct_a_out, a);
+    #[hdl]
+    let test_struct_b_out: UInt<8> = m.output();
+    connect(test_struct_b_out, b);
+
+    #[hdl]
+    let test_struct_2_in: TestStruct2 = m.input();
+    #[hdl]
+    let TestStruct2 { v } = test_struct_2_in;
+    #[hdl]
+    let test_struct_2_v_out: UInt<8> = m.output();
+    connect(test_struct_2_v_out, v);
+
+    #[hdl]
+    let test_struct_3_in: TestStruct3 = m.input();
+    #[hdl]
+    let TestStruct3 {} = test_struct_3_in;
+}
+
+#[test]
+fn test_let_patterns() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_let_patterns();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_let_patterns.fir": r"FIRRTL version 3.2.0
+circuit check_let_patterns:
+    type Ty0 = {`0`: UInt<1>, `1`: SInt<1>, `2`: UInt<1>}
+    type Ty1 = {a: SInt<8>, b: UInt<8>}
+    type Ty2 = {v: UInt<8>}
+    type Ty3 = {}
+    module check_let_patterns: @[module-XXXXXXXXXX.rs 1:1]
+        input tuple_in: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        output tuple_0_out: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
+        output tuple_1_out: SInt<1> @[module-XXXXXXXXXX.rs 6:1]
+        output tuple_2_out: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+        input test_struct_in: Ty1 @[module-XXXXXXXXXX.rs 10:1]
+        output test_struct_a_out: SInt<8> @[module-XXXXXXXXXX.rs 12:1]
+        output test_struct_b_out: UInt<8> @[module-XXXXXXXXXX.rs 14:1]
+        input test_struct_2_in: Ty2 @[module-XXXXXXXXXX.rs 16:1]
+        output test_struct_2_v_out: UInt<8> @[module-XXXXXXXXXX.rs 18:1]
+        input test_struct_3_in: Ty3 @[module-XXXXXXXXXX.rs 20:1]
+        connect tuple_0_out, tuple_in.`0` @[module-XXXXXXXXXX.rs 5:1]
+        connect tuple_1_out, tuple_in.`1` @[module-XXXXXXXXXX.rs 7:1]
+        connect tuple_2_out, tuple_in.`2` @[module-XXXXXXXXXX.rs 9:1]
+        connect test_struct_a_out, test_struct_in.a @[module-XXXXXXXXXX.rs 13:1]
+        connect test_struct_b_out, test_struct_in.b @[module-XXXXXXXXXX.rs 15:1]
+        connect test_struct_2_v_out, test_struct_2_in.v @[module-XXXXXXXXXX.rs 19:1]
+",
+    };
+}
+
+#[hdl_module(outline_generated)]
+pub fn check_struct_cmp_eq() {
+    #[hdl]
+    let tuple_lhs: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let tuple_rhs: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let tuple_cmp_eq: Bool = m.output();
+    connect(tuple_cmp_eq, tuple_lhs.cmp_eq(tuple_rhs));
+    #[hdl]
+    let tuple_cmp_ne: Bool = m.output();
+    connect(tuple_cmp_ne, tuple_lhs.cmp_ne(tuple_rhs));
+
+    #[hdl]
+    let test_struct_lhs: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let test_struct_rhs: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let test_struct_cmp_eq: Bool = m.output();
+    connect(test_struct_cmp_eq, test_struct_lhs.cmp_eq(test_struct_rhs));
+    #[hdl]
+    let test_struct_cmp_ne: Bool = m.output();
+    connect(test_struct_cmp_ne, test_struct_lhs.cmp_ne(test_struct_rhs));
+
+    #[hdl]
+    let test_struct_2_lhs: TestStruct2 = m.input();
+    #[hdl]
+    let test_struct_2_rhs: TestStruct2 = m.input();
+    #[hdl]
+    let test_struct_2_cmp_eq: Bool = m.output();
+    connect(
+        test_struct_2_cmp_eq,
+        test_struct_2_lhs.cmp_eq(test_struct_2_rhs),
+    );
+    #[hdl]
+    let test_struct_2_cmp_ne: Bool = m.output();
+    connect(
+        test_struct_2_cmp_ne,
+        test_struct_2_lhs.cmp_ne(test_struct_2_rhs),
+    );
+
+    #[hdl]
+    let test_struct_3_lhs: TestStruct3 = m.input();
+    #[hdl]
+    let test_struct_3_rhs: TestStruct3 = m.input();
+    #[hdl]
+    let test_struct_3_cmp_eq: Bool = m.output();
+    connect(
+        test_struct_3_cmp_eq,
+        test_struct_3_lhs.cmp_eq(test_struct_3_rhs),
+    );
+    #[hdl]
+    let test_struct_3_cmp_ne: Bool = m.output();
+    connect(
+        test_struct_3_cmp_ne,
+        test_struct_3_lhs.cmp_ne(test_struct_3_rhs),
+    );
+}
+
+#[test]
+fn test_struct_cmp_eq() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_struct_cmp_eq();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_struct_cmp_eq.fir": r"FIRRTL version 3.2.0
+circuit check_struct_cmp_eq:
+    type Ty0 = {`0`: UInt<1>, `1`: SInt<1>, `2`: UInt<1>}
+    type Ty1 = {a: SInt<8>, b: UInt<8>}
+    type Ty2 = {v: UInt<8>}
+    type Ty3 = {}
+    module check_struct_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
+        input tuple_lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input tuple_rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
+        output tuple_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
+        output tuple_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
+        input test_struct_lhs: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        input test_struct_rhs: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output test_struct_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        output test_struct_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 12:1]
+        input test_struct_2_lhs: Ty2 @[module-XXXXXXXXXX.rs 14:1]
+        input test_struct_2_rhs: Ty2 @[module-XXXXXXXXXX.rs 15:1]
+        output test_struct_2_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 16:1]
+        output test_struct_2_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 18:1]
+        input test_struct_3_lhs: Ty3 @[module-XXXXXXXXXX.rs 20:1]
+        input test_struct_3_rhs: Ty3 @[module-XXXXXXXXXX.rs 21:1]
+        output test_struct_3_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 22:1]
+        output test_struct_3_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 24:1]
+        wire _array_literal_expr: UInt<1>[3]
+        connect _array_literal_expr[0], eq(tuple_lhs.`0`, tuple_rhs.`0`)
+        connect _array_literal_expr[1], eq(tuple_lhs.`1`, tuple_rhs.`1`)
+        connect _array_literal_expr[2], eq(tuple_lhs.`2`, tuple_rhs.`2`)
+        wire _cast_array_to_bits_expr: UInt<1>[3]
+        connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
+        connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
+        connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
+        wire _cast_to_bits_expr: UInt<3>
+        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
+        connect tuple_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
+        wire _array_literal_expr_1: UInt<1>[3]
+        connect _array_literal_expr_1[0], neq(tuple_lhs.`0`, tuple_rhs.`0`)
+        connect _array_literal_expr_1[1], neq(tuple_lhs.`1`, tuple_rhs.`1`)
+        connect _array_literal_expr_1[2], neq(tuple_lhs.`2`, tuple_rhs.`2`)
+        wire _cast_array_to_bits_expr_1: UInt<1>[3]
+        connect _cast_array_to_bits_expr_1[0], _array_literal_expr_1[0]
+        connect _cast_array_to_bits_expr_1[1], _array_literal_expr_1[1]
+        connect _cast_array_to_bits_expr_1[2], _array_literal_expr_1[2]
+        wire _cast_to_bits_expr_1: UInt<3>
+        connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
+        connect tuple_cmp_ne, orr(_cast_to_bits_expr_1) @[module-XXXXXXXXXX.rs 7:1]
+        connect test_struct_cmp_eq, and(eq(test_struct_lhs.a, test_struct_rhs.a), eq(test_struct_lhs.b, test_struct_rhs.b)) @[module-XXXXXXXXXX.rs 11:1]
+        connect test_struct_cmp_ne, or(neq(test_struct_lhs.a, test_struct_rhs.a), neq(test_struct_lhs.b, test_struct_rhs.b)) @[module-XXXXXXXXXX.rs 13:1]
+        connect test_struct_2_cmp_eq, eq(test_struct_2_lhs.v, test_struct_2_rhs.v) @[module-XXXXXXXXXX.rs 17:1]
+        connect test_struct_2_cmp_ne, neq(test_struct_2_lhs.v, test_struct_2_rhs.v) @[module-XXXXXXXXXX.rs 19:1]
+        connect test_struct_3_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 23:1]
+        connect test_struct_3_cmp_ne, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 25:1]
+",
+    };
+}
+
+#[hdl_module(outline_generated)]
+pub fn check_uint_in_range() {
+    #[hdl]
+    let i_0_to_1: UIntInRange<0, 1> = m.input();
+    #[hdl]
+    let i_0_to_2: UIntInRange<0, 2> = m.input();
+    #[hdl]
+    let i_0_to_3: UIntInRange<0, 3> = m.input();
+    #[hdl]
+    let i_0_to_4: UIntInRange<0, 4> = m.input();
+    #[hdl]
+    let i_0_to_7: UIntInRange<0, 7> = m.input();
+    #[hdl]
+    let i_0_to_8: UIntInRange<0, 8> = m.input();
+    #[hdl]
+    let i_0_to_9: UIntInRange<0, 9> = m.input();
+    #[hdl]
+    let i_0_through_0: UIntInRangeInclusive<0, 0> = m.input();
+    #[hdl]
+    let i_0_through_1: UIntInRangeInclusive<0, 1> = m.input();
+    #[hdl]
+    let i_0_through_2: UIntInRangeInclusive<0, 2> = m.input();
+    #[hdl]
+    let i_0_through_3: UIntInRangeInclusive<0, 3> = m.input();
+    #[hdl]
+    let i_0_through_4: UIntInRangeInclusive<0, 4> = m.input();
+    #[hdl]
+    let i_0_through_7: UIntInRangeInclusive<0, 7> = m.input();
+    #[hdl]
+    let i_0_through_8: UIntInRangeInclusive<0, 8> = m.input();
+    #[hdl]
+    let i_0_through_9: UIntInRangeInclusive<0, 9> = m.input();
+}
+
+#[test]
+fn test_uint_in_range() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_uint_in_range();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_uint_in_range.fir": r"FIRRTL version 3.2.0
+circuit check_uint_in_range:
+    type Ty0 = {value: UInt<0>, range: {}}
+    type Ty1 = {value: UInt<1>, range: {}}
+    type Ty2 = {value: UInt<2>, range: {}}
+    type Ty3 = {value: UInt<2>, range: {}}
+    type Ty4 = {value: UInt<3>, range: {}}
+    type Ty5 = {value: UInt<3>, range: {}}
+    type Ty6 = {value: UInt<4>, range: {}}
+    type Ty7 = {value: UInt<0>, range: {}}
+    type Ty8 = {value: UInt<1>, range: {}}
+    type Ty9 = {value: UInt<2>, range: {}}
+    type Ty10 = {value: UInt<2>, range: {}}
+    type Ty11 = {value: UInt<3>, range: {}}
+    type Ty12 = {value: UInt<3>, range: {}}
+    type Ty13 = {value: UInt<4>, range: {}}
+    type Ty14 = {value: UInt<4>, range: {}}
+    module check_uint_in_range: @[module-XXXXXXXXXX.rs 1:1]
+        input i_0_to_1: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input i_0_to_2: Ty1 @[module-XXXXXXXXXX.rs 3:1]
+        input i_0_to_3: Ty2 @[module-XXXXXXXXXX.rs 4:1]
+        input i_0_to_4: Ty3 @[module-XXXXXXXXXX.rs 5:1]
+        input i_0_to_7: Ty4 @[module-XXXXXXXXXX.rs 6:1]
+        input i_0_to_8: Ty5 @[module-XXXXXXXXXX.rs 7:1]
+        input i_0_to_9: Ty6 @[module-XXXXXXXXXX.rs 8:1]
+        input i_0_through_0: Ty7 @[module-XXXXXXXXXX.rs 9:1]
+        input i_0_through_1: Ty8 @[module-XXXXXXXXXX.rs 10:1]
+        input i_0_through_2: Ty9 @[module-XXXXXXXXXX.rs 11:1]
+        input i_0_through_3: Ty10 @[module-XXXXXXXXXX.rs 12:1]
+        input i_0_through_4: Ty11 @[module-XXXXXXXXXX.rs 13:1]
+        input i_0_through_7: Ty12 @[module-XXXXXXXXXX.rs 14:1]
+        input i_0_through_8: Ty13 @[module-XXXXXXXXXX.rs 15:1]
+        input i_0_through_9: Ty14 @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
new file mode 100644
index 0000000..655a497
--- /dev/null
+++ b/crates/fayalite/tests/sim.rs
@@ -0,0 +1,1628 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use fayalite::{
+    memory::{ReadStruct, ReadWriteStruct, WriteStruct},
+    module::{instance_with_loc, reg_builder_with_loc},
+    prelude::*,
+    reset::ResetType,
+    sim::vcd::VcdWriterDecls,
+    util::RcWriter,
+};
+use std::num::NonZeroUsize;
+
+#[hdl_module(outline_generated)]
+pub fn connect_const() {
+    #[hdl]
+    let o: UInt<8> = m.output();
+    connect(o, 5u8);
+}
+
+#[test]
+fn test_connect_const() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(connect_const());
+    sim.settle();
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/connect_const.txt") {
+        panic!();
+    }
+    assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
+}
+
+#[hdl_module(outline_generated)]
+pub fn connect_const_reset() {
+    #[hdl]
+    let reset_out: Reset = m.output();
+    #[hdl]
+    let bit_out: Bool = m.output();
+    connect(reset_out, true.to_async_reset().to_reset());
+    connect(bit_out, reset_out.cast_to_static());
+}
+
+#[test]
+fn test_connect_const_reset() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(connect_const_reset());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.settle();
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/connect_const_reset.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/connect_const_reset.txt") {
+        panic!();
+    }
+    assert_eq!(sim.read_bool_or_int(sim.io().bit_out), true);
+}
+
+#[hdl_module(outline_generated)]
+pub fn mod1_child() {
+    #[hdl]
+    let i: UInt<4> = m.input();
+    #[hdl]
+    let o: SInt<2> = m.output();
+    #[hdl]
+    let i2: SInt<2> = m.input();
+    #[hdl]
+    let o2: UInt<4> = m.output();
+    connect(o, i.cast_to_static());
+    connect(o2, i2.cast_to_static());
+    #[hdl]
+    if i.cmp_gt(5_hdl_u4) {
+        connect(o2, 0xF_hdl_u4);
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn mod1() {
+    #[hdl]
+    let child = instance(mod1_child());
+    #[hdl]
+    let o: mod1_child = m.output(Expr::ty(child));
+    connect(o, child);
+}
+
+#[hdl]
+#[test]
+fn test_mod1() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(mod1());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_bool_or_int(sim.io().o.i, 0x3_hdl_u4);
+    sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/mod1.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/mod1.txt") {
+        panic!();
+    }
+    let expected = -2_hdl_i2;
+    assert_eq!(sim.read_bool_or_int(sim.io().o.o).to_expr(), expected);
+    let expected = 0xF_hdl_u4;
+    assert_eq!(sim.read_bool_or_int(sim.io().o.o2).to_expr(), expected);
+}
+
+#[hdl_module(outline_generated)]
+pub fn counter<R: ResetType>() {
+    #[hdl]
+    let cd: ClockDomain<R> = m.input();
+    #[hdl]
+    let count_reg: UInt<4> = reg_builder().clock_domain(cd).reset(3_hdl_u4);
+    connect_any(count_reg, count_reg + 1_hdl_u1);
+    #[hdl]
+    let count: UInt<4> = m.output();
+    connect(count, count_reg);
+}
+
+#[hdl]
+#[test]
+fn test_counter_sync() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(counter::<SyncReset>());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.settle();
+    let reset_value = 3_hdl_u4;
+    assert_eq!(
+        reset_value,
+        sim.read_bool_or_int(sim.io().count).to_expr(),
+        "vcd:\n{}",
+        String::from_utf8(writer.take()).unwrap(),
+    );
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    for i in 0..32u32 {
+        assert_eq!(
+            UInt::<4>::new_static().from_int_wrapping(i + 3),
+            sim.read_bool_or_int(sim.io().count),
+            "vcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/counter_sync.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/counter_sync.txt") {
+        panic!();
+    }
+}
+
+#[hdl]
+#[test]
+fn test_counter_async() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(counter::<AsyncReset>());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_reset(sim.io().cd.rst, true);
+    let reset_value = 3_hdl_u4;
+    assert_eq!(
+        reset_value,
+        sim.read_bool_or_int(sim.io().count).to_expr(),
+        "vcd:\n{}",
+        String::from_utf8(writer.take()).unwrap(),
+    );
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(500));
+    for i in 0..32u32 {
+        assert_eq!(
+            UInt::<4>::new_static().from_int_wrapping(i + 3),
+            sim.read_bool_or_int(sim.io().count),
+            "vcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/counter_async.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/counter_async.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn shift_register() {
+    #[hdl]
+    let cd: ClockDomain<SyncReset> = m.input();
+    #[hdl]
+    let d: Bool = m.input();
+    #[hdl]
+    let q: Bool = m.output();
+    #[hdl]
+    let reg0: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg0, d);
+    #[hdl]
+    let reg1: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg1, reg0);
+    #[hdl]
+    let reg2: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg2, reg1);
+    #[hdl]
+    let reg3: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg3, reg2);
+    connect(q, reg3);
+}
+
+#[hdl]
+#[test]
+fn test_shift_register() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(shift_register());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(
+        sim.io().cd,
+        #[hdl]
+        ClockDomain {
+            clk: false.to_clock(),
+            rst: true.to_sync_reset(),
+        },
+    );
+    sim.write_bool(sim.io().d, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(100));
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(900));
+    let data = [
+        false, true, true, false, false, true, false, true, true, true, true,
+    ];
+    for cycle in 0..32usize {
+        if let Some(out_cycle) = cycle.checked_sub(4) {
+            if let Some(expected) = data.get(out_cycle) {
+                assert_eq!(
+                    *expected,
+                    sim.read_bool(sim.io().q),
+                    "vcd:\n{}\ncycle: {cycle}",
+                    String::from_utf8(writer.take()).unwrap(),
+                );
+            }
+        }
+        sim.write_bool(sim.io().d, data.get(cycle).copied().unwrap_or(false));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/shift_register.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/shift_register.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn enums() {
+    #[hdl]
+    let cd: ClockDomain<SyncReset> = m.input();
+    #[hdl]
+    let en: Bool = m.input();
+    #[hdl]
+    let which_in: UInt<2> = m.input();
+    #[hdl]
+    let data_in: UInt<4> = m.input();
+    #[hdl]
+    let which_out: UInt<2> = m.output();
+    #[hdl]
+    let data_out: UInt<4> = m.output();
+    let b_out_ty = HdlOption[(UInt[1], Bool)];
+    #[hdl]
+    let b_out: HdlOption<(UInt, Bool)> = m.output(HdlOption[(UInt[1], Bool)]);
+    #[hdl]
+    let b2_out: HdlOption<(UInt<1>, Bool)> = m.output();
+
+    connect_any(b2_out, b_out);
+
+    #[hdl]
+    struct MyStruct<T> {
+        a: T,
+        b: SInt<2>,
+    }
+
+    #[hdl]
+    enum MyEnum {
+        A,
+        B((UInt<1>, Bool)),
+        C(MyStruct<Array<UInt<1>, 2>>),
+    }
+
+    #[hdl]
+    let the_reg = reg_builder().clock_domain(cd).reset(MyEnum.A());
+
+    #[hdl]
+    if en {
+        #[hdl]
+        if which_in.cmp_eq(0_hdl_u2) {
+            connect(the_reg, MyEnum.A());
+        } else if which_in.cmp_eq(1_hdl_u2) {
+            connect(the_reg, MyEnum.B((data_in[0].cast_to_static(), data_in[1])));
+        } else {
+            connect(
+                the_reg,
+                MyEnum.C(
+                    #[hdl]
+                    MyStruct {
+                        a: #[hdl]
+                        [data_in[0].cast_to_static(), data_in[1].cast_to_static()],
+                        b: data_in[2..4].cast_to_static(),
+                    },
+                ),
+            );
+        }
+    }
+
+    connect(b_out, b_out_ty.HdlNone());
+
+    #[hdl]
+    match the_reg {
+        MyEnum::A => {
+            connect(which_out, 0_hdl_u2);
+            connect(data_out, 0_hdl_u4);
+        }
+        MyEnum::B(v) => {
+            connect(which_out, 1_hdl_u2);
+            connect_any(data_out, v.0 | (v.1.cast_to_static::<UInt<1>>() << 1));
+            connect_any(b_out, HdlSome(v));
+        }
+        MyEnum::C(v) => {
+            connect(which_out, 2_hdl_u2);
+            connect_any(data_out, v.cast_to_bits());
+        }
+    }
+}
+
+#[hdl]
+#[test]
+fn test_enums() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(enums());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().cd.clk, false);
+    sim.write(sim.io().cd.rst, true);
+    sim.write(sim.io().en, false);
+    sim.write(sim.io().which_in, 0_hdl_u2);
+    sim.write(sim.io().data_in, 0_hdl_u4);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(100));
+    sim.write(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(900));
+    #[hdl(cmp_eq)]
+    struct IO<W: Size> {
+        en: Bool,
+        which_in: UInt<2>,
+        data_in: UInt<4>,
+        which_out: UInt<2>,
+        data_out: UInt<4>,
+        b_out: HdlOption<(UIntType<W>, Bool)>,
+        b2_out: HdlOption<(UInt<1>, Bool)>,
+    }
+    let io_ty = IO[1];
+    let io_cycles = [
+        #[hdl(sim)]
+        IO::<_> {
+            en: false,
+            which_in: 0_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 0_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: true,
+            which_in: 1_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 0_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: false,
+            which_in: 0_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((0u8.cast_to(UInt[1]), false)),
+            b2_out: #[hdl(sim)]
+            HdlSome((0_hdl_u1, false)),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: true,
+            which_in: 1_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((0u8.cast_to(UInt[1]), false)),
+            b2_out: #[hdl(sim)]
+            HdlSome((0_hdl_u1, false)),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: true,
+            which_in: 1_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0x3_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((1u8.cast_to(UInt[1]), true)),
+            b2_out: #[hdl(sim)]
+            HdlSome((1_hdl_u1, true)),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: true,
+            which_in: 2_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0x3_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((1u8.cast_to(UInt[1]), true)),
+            b2_out: #[hdl(sim)]
+            HdlSome((1_hdl_u1, true)),
+        },
+        #[hdl(sim)]
+        IO::<_> {
+            en: true,
+            which_in: 2_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 2_hdl_u2,
+            data_out: 0xF_hdl_u4,
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
+        },
+    ];
+    for (cycle, expected) in io_cycles.into_iter().enumerate() {
+        #[hdl(sim)]
+        let IO::<_> {
+            en,
+            which_in,
+            data_in,
+            which_out: _,
+            data_out: _,
+            b_out: _,
+            b2_out: _,
+        } = expected;
+        sim.write(sim.io().en, &en);
+        sim.write(sim.io().which_in, &which_in);
+        sim.write(sim.io().data_in, &data_in);
+        let io = #[hdl(sim)]
+        IO::<_> {
+            en,
+            which_in,
+            data_in,
+            which_out: sim.read(sim.io().which_out),
+            data_out: sim.read(sim.io().data_out),
+            b_out: sim.read(sim.io().b_out),
+            b2_out: sim.read(sim.io().b2_out),
+        };
+        assert_eq!(
+            expected,
+            io,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        // make sure matching on SimValue<SomeEnum> works
+        #[hdl(sim)]
+        match io.b_out {
+            HdlNone => println!("io.b_out is HdlNone"),
+            HdlSome(v) => println!("io.b_out is HdlSome(({:?}, {:?}))", *v.0, *v.1),
+        }
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/enums.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/enums.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn memories() {
+    #[hdl]
+    let r: ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let w: WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
+    mem.read_latency(0);
+    mem.write_latency(NonZeroUsize::new(1).unwrap());
+    mem.read_under_write(ReadUnderWrite::Old);
+    connect_any(mem.new_read_port(), r);
+    connect_any(mem.new_write_port(), w);
+}
+
+#[hdl]
+#[test]
+fn test_memories() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().r.clk, false);
+    sim.write_clock(sim.io().w.clk, false);
+    #[hdl(cmp_eq)]
+    struct IO {
+        r_addr: UInt<4>,
+        r_en: Bool,
+        r_data: (UInt<8>, SInt<8>),
+        w_addr: UInt<4>,
+        w_en: Bool,
+        w_data: (UInt<8>, SInt<8>),
+        w_mask: (Bool, Bool),
+    }
+    let io_cycles = [
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: false,
+            r_data: (0u8, 0i8),
+            w_addr: 0_hdl_u4,
+            w_en: false,
+            w_data: (0u8, 0i8),
+            w_mask: (false, false),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x1u8, 0x23i8),
+            w_addr: 0_hdl_u4,
+            w_en: true,
+            w_data: (0x10u8, 0x20i8),
+            w_mask: (true, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x10u8, 0x20i8),
+            w_addr: 0_hdl_u4,
+            w_en: true,
+            w_data: (0x30u8, 0x40i8),
+            w_mask: (false, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x10u8, 0x40i8),
+            w_addr: 0_hdl_u4,
+            w_en: true,
+            w_data: (0x50u8, 0x60i8),
+            w_mask: (true, false),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 0_hdl_u4,
+            w_en: true,
+            w_data: (0x70u8, -0x80i8),
+            w_mask: (false, false),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 0_hdl_u4,
+            w_en: false,
+            w_data: (0x90u8, 0xA0u8 as i8),
+            w_mask: (false, false),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 1_hdl_u4,
+            w_en: true,
+            w_data: (0x90u8, 0xA0u8 as i8),
+            w_mask: (true, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 2_hdl_u4,
+            w_en: true,
+            w_data: (0xB0u8, 0xC0u8 as i8),
+            w_mask: (true, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 0_hdl_u4,
+            r_en: true,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 2_hdl_u4,
+            w_en: false,
+            w_data: (0xD0u8, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 1_hdl_u4,
+            r_en: true,
+            r_data: (0x90u8, 0xA0u8 as i8),
+            w_addr: 2_hdl_u4,
+            w_en: false,
+            w_data: (0xD0u8, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+        #[hdl(sim)]
+        IO {
+            r_addr: 2_hdl_u4,
+            r_en: true,
+            r_data: (0xB0u8, 0xC0u8 as i8),
+            w_addr: 2_hdl_u4,
+            w_en: false,
+            w_data: (0xD0u8, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+    ];
+    for (cycle, expected) in io_cycles.into_iter().enumerate() {
+        #[hdl(sim)]
+        let IO {
+            r_addr,
+            r_en,
+            r_data: _,
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        } = expected;
+        sim.write(sim.io().r.addr, &r_addr);
+        sim.write(sim.io().r.en, &r_en);
+        sim.write(sim.io().w.addr, &w_addr);
+        sim.write(sim.io().w.en, &w_en);
+        sim.write(sim.io().w.data, &w_data);
+        sim.write(sim.io().w.mask, &w_mask);
+        let io = #[hdl(sim)]
+        IO {
+            r_addr,
+            r_en,
+            r_data: sim.read(sim.io().r.data),
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        };
+        assert_eq!(
+            expected,
+            io,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().r.clk, true);
+        sim.write(sim.io().w.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().r.clk, false);
+        sim.write(sim.io().w.clk, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn memories2() {
+    #[hdl]
+    let rw: ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let mut mem = memory_with_init([HdlSome(true); 5]);
+    mem.read_latency(1);
+    mem.write_latency(NonZeroUsize::new(1).unwrap());
+    mem.read_under_write(ReadUnderWrite::New);
+    let rw_port = mem.new_rw_port();
+    connect_any(rw_port.addr, rw.addr);
+    connect(rw_port.en, rw.en);
+    connect(rw_port.clk, rw.clk);
+    connect_any(rw.rdata, rw_port.rdata.cast_to_bits());
+    connect(rw_port.wmode, rw.wmode);
+    connect(rw_port.wdata, HdlNone());
+    #[hdl]
+    if rw.wdata[0] {
+        connect(rw_port.wdata, HdlSome(rw.wdata[1]));
+    }
+    connect(rw_port.wmask, rw.wmask);
+}
+
+#[hdl]
+#[test]
+fn test_memories2() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories2());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().rw.clk, false);
+    #[derive(Debug, PartialEq, Eq)]
+    struct IO {
+        addr: u8,
+        en: bool,
+        rdata: u8,
+        wmode: bool,
+        wdata: u8,
+        wmask: bool,
+    }
+    let io_cycles = [
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0x3,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 0,
+            wmask: true,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 3,
+            wmask: false,
+        },
+        IO {
+            addr: 1,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 2,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 2,
+            wmask: true,
+        },
+        IO {
+            addr: 3,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 3,
+            wmask: true,
+        },
+        IO {
+            addr: 4,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 2,
+            wmask: true,
+        },
+        IO {
+            addr: 5,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 6,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 7,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 7,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 6,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 5,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 4,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 3,
+            en: true,
+            rdata: 3,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 2,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 1,
+            en: true,
+            rdata: 1,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+    ];
+    for (
+        cycle,
+        expected @ IO {
+            addr,
+            en,
+            rdata: _,
+            wmode,
+            wdata,
+            wmask,
+        },
+    ) in io_cycles.into_iter().enumerate()
+    {
+        sim.write_bool_or_int(sim.io().rw.addr, addr.cast_to_static());
+        sim.write_bool(sim.io().rw.en, en);
+        sim.write_bool(sim.io().rw.wmode, wmode);
+        sim.write_bool_or_int(sim.io().rw.wdata, wdata.cast_to_static());
+        sim.write_bool(sim.io().rw.wmask, wmask);
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().rw.clk, true);
+        sim.advance_time(SimDuration::from_nanos(250));
+        let io = IO {
+            addr,
+            en,
+            rdata: sim
+                .read_bool_or_int(sim.io().rw.rdata)
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range"),
+            wmode,
+            wdata,
+            wmask,
+        };
+        assert_eq!(
+            expected,
+            io,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().rw.clk, false);
+        sim.advance_time(SimDuration::from_nanos(250));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories2.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories2.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn memories3() {
+    #[hdl]
+    let r: ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let w: WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let mut mem: MemBuilder<Array<UInt<8>, 8>> = memory();
+    mem.depth(8);
+    mem.read_latency(2);
+    mem.write_latency(NonZeroUsize::new(2).unwrap());
+    mem.read_under_write(ReadUnderWrite::Old);
+    connect_any(mem.new_read_port(), r);
+    connect_any(mem.new_write_port(), w);
+}
+
+#[hdl]
+#[test]
+fn test_memories3() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories3());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().r.clk, false);
+    sim.write_clock(sim.io().w.clk, false);
+    #[derive(Debug, PartialEq, Eq, Clone, Copy)]
+    struct IO {
+        r_addr: u8,
+        r_en: bool,
+        r_data: [u8; 8],
+        w_addr: u8,
+        w_en: bool,
+        w_data: [u8; 8],
+        w_mask: [bool; 8],
+    }
+    let io_cycles = [
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0],
+            w_mask: [false, true, false, true, true, false, false, true],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0; 8],
+            w_addr: 1,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 1,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 1,
+            w_en: true,
+            w_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 2,
+            w_en: true,
+            w_data: *b"testing!",
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 3,
+            w_en: true,
+            w_data: *b"more tst",
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 1,
+            r_en: true,
+            r_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 2,
+            r_en: true,
+            r_data: *b"testing!",
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 3,
+            r_en: true,
+            r_data: *b"more tst",
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+    ];
+    for cycle in 0..io_cycles.len() + 2 {
+        {
+            let IO {
+                r_addr,
+                r_en,
+                r_data: _,
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            } = io_cycles.get(cycle).copied().unwrap_or(IO {
+                r_addr: 0,
+                r_en: false,
+                r_data: [0; 8],
+                w_addr: 0,
+                w_en: false,
+                w_data: [0; 8],
+                w_mask: [false; 8],
+            });
+            sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
+            sim.write_bool(sim.io().r.en, r_en);
+            sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
+            sim.write_bool(sim.io().w.en, w_en);
+            for (i, v) in w_data.into_iter().enumerate() {
+                sim.write_bool_or_int(sim.io().w.data[i], v);
+            }
+            for (i, v) in w_mask.into_iter().enumerate() {
+                sim.write_bool_or_int(sim.io().w.mask[i], v);
+            }
+        }
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().r.clk, true);
+        sim.write_clock(sim.io().w.clk, true);
+        sim.advance_time(SimDuration::from_nanos(250));
+        if let Some(
+            expected @ IO {
+                r_addr,
+                r_en,
+                r_data: _,
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            },
+        ) = cycle.checked_sub(1).and_then(|i| io_cycles.get(i).copied())
+        {
+            let io = IO {
+                r_addr,
+                r_en,
+                r_data: std::array::from_fn(|i| {
+                    sim.read_bool_or_int(sim.io().r.data[i])
+                        .to_bigint()
+                        .try_into()
+                        .expect("known to be in range")
+                }),
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            };
+            assert_eq!(
+                expected,
+                io,
+                "vcd:\n{}\ncycle: {cycle}",
+                String::from_utf8(writer.take()).unwrap(),
+            );
+        }
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().r.clk, false);
+        sim.write_clock(sim.io().w.clk, false);
+        sim.advance_time(SimDuration::from_nanos(250));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories3.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories3.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn duplicate_names() {
+    #[hdl]
+    let w = wire();
+    connect(w, 5u8);
+    #[hdl]
+    let w = wire();
+    connect(w, 6u8);
+}
+
+#[test]
+fn test_duplicate_names() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(duplicate_names());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/duplicate_names.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/duplicate_names.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn array_rw() {
+    #[hdl]
+    let array_in: Array<UInt<8>, 16> = m.input();
+    #[hdl]
+    let array_out: Array<UInt<8>, 16> = m.output();
+    #[hdl]
+    let read_index: UInt<8> = m.input();
+    #[hdl]
+    let read_data: UInt<8> = m.output();
+    #[hdl]
+    let write_index: UInt<8> = m.input();
+    #[hdl]
+    let write_data: UInt<8> = m.input();
+    #[hdl]
+    let write_en: Bool = m.input();
+    #[hdl]
+    let array_wire = wire();
+    connect(array_wire, array_in);
+    connect(array_out, array_wire);
+    #[hdl]
+    if write_en {
+        connect(array_wire[write_index], write_data);
+    }
+    connect(read_data, array_wire[read_index]);
+}
+
+#[test]
+fn test_array_rw() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(array_rw());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    #[derive(Debug, PartialEq)]
+    struct State {
+        array_in: [u8; 16],
+        array_out: [u8; 16],
+        read_index: u8,
+        read_data: u8,
+        write_index: u8,
+        write_data: u8,
+        write_en: bool,
+    }
+    let mut states = Vec::new();
+    let array_in = [
+        0xFFu8, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, //
+        0x00u8, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE,
+    ];
+    for i in 0..=16 {
+        states.push(State {
+            array_in,
+            array_out: array_in,
+            read_index: i,
+            read_data: array_in.get(i as usize).copied().unwrap_or(0),
+            write_index: 0,
+            write_data: 0,
+            write_en: false,
+        });
+    }
+    for i in 0..=16u8 {
+        let mut array_out = array_in;
+        let write_data = i.wrapping_mul(i);
+        if let Some(v) = array_out.get_mut(i as usize) {
+            *v = write_data;
+        }
+        states.push(State {
+            array_in,
+            array_out,
+            read_index: 0,
+            read_data: array_out[0],
+            write_index: i,
+            write_data,
+            write_en: true,
+        });
+    }
+    for (cycle, expected) in states.into_iter().enumerate() {
+        let State {
+            array_in,
+            array_out: _,
+            read_index,
+            read_data: _,
+            write_index,
+            write_data,
+            write_en,
+        } = expected;
+        sim.write(sim.io().array_in, array_in);
+        sim.write(sim.io().read_index, read_index);
+        sim.write(sim.io().write_index, write_index);
+        sim.write(sim.io().write_data, write_data);
+        sim.write(sim.io().write_en, write_en);
+        sim.advance_time(SimDuration::from_micros(1));
+        let array_out = std::array::from_fn(|index| {
+            sim.read_bool_or_int(sim.io().array_out[index])
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range")
+        });
+        let read_data = sim
+            .read_bool_or_int(sim.io().read_data)
+            .to_bigint()
+            .try_into()
+            .expect("known to be in range");
+        let state = State {
+            array_in,
+            array_out,
+            read_index,
+            read_data,
+            write_index,
+            write_data,
+            write_en,
+        };
+        assert_eq!(
+            state,
+            expected,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/array_rw.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/array_rw.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn conditional_assignment_last() {
+    #[hdl]
+    let i: Bool = m.input();
+    #[hdl]
+    let w = wire();
+    connect(w, true);
+    #[hdl]
+    if i {
+        connect(w, false);
+    }
+}
+
+#[test]
+fn test_conditional_assignment_last() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(conditional_assignment_last());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().i, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write(sim.io().i, true);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/conditional_assignment_last.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/conditional_assignment_last.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated, extern)]
+pub fn extern_module() {
+    #[hdl]
+    let i: Bool = m.input();
+    #[hdl]
+    let o: Bool = m.output();
+    m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
+        sim.write(o, true).await;
+        sim.advance_time(SimDuration::from_nanos(500)).await;
+        let mut invert = false;
+        loop {
+            sim.advance_time(SimDuration::from_micros(1)).await;
+            let v = sim.read_bool(i).await;
+            sim.write(o, v ^ invert).await;
+            invert = !invert;
+        }
+    });
+}
+
+#[test]
+fn test_extern_module() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(extern_module());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().i, false);
+    sim.advance_time(SimDuration::from_micros(10));
+    sim.write(sim.io().i, true);
+    sim.advance_time(SimDuration::from_micros(10));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/extern_module.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/extern_module.txt") {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated, extern)]
+pub fn extern_module2() {
+    #[hdl]
+    let en: Bool = m.input();
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: UInt<8> = m.output();
+    m.extern_module_simulation_fn((en, clk, o), |(en, clk, o), mut sim| async move {
+        for b in "Hello, World!\n".bytes().cycle() {
+            sim.write(o, b).await;
+            loop {
+                sim.wait_for_clock_edge(clk).await;
+                if sim.read_bool(en).await {
+                    break;
+                }
+            }
+        }
+    });
+}
+
+#[test]
+fn test_extern_module2() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(extern_module2());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    for i in 0..30 {
+        sim.write(sim.io().en, i % 10 < 5);
+        sim.write(sim.io().clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/extern_module2.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/extern_module2.txt") {
+        panic!();
+    }
+}
+
+// use an extern module to simulate a register to test that the
+// simulator can handle chains of alternating circuits and extern modules.
+#[hdl_module(outline_generated, extern)]
+pub fn sw_reg() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: Bool = m.output();
+    m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move {
+        let mut state = false;
+        loop {
+            sim.write(o, state).await;
+            sim.wait_for_clock_edge(clk).await;
+            state = !state;
+        }
+    });
+}
+
+#[hdl_module(outline_generated)]
+pub fn ripple_counter() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: UInt<6> = m.output();
+
+    #[hdl]
+    let bits: Array<Bool, 6> = wire();
+
+    connect_any(o, bits.cast_to_bits());
+
+    let mut clk_in = clk;
+    for (i, bit) in bits.into_iter().enumerate() {
+        if i % 2 == 0 {
+            let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller())
+                .clock_domain(
+                    #[hdl]
+                    ClockDomain {
+                        clk: clk_in,
+                        rst: false.to_sync_reset(),
+                    },
+                )
+                .no_reset(Bool)
+                .build();
+            connect(bit, bit_reg);
+            connect(bit_reg, !bit_reg);
+        } else {
+            let bit_reg =
+                instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller());
+            connect(bit_reg.clk, clk_in);
+            connect(bit, bit_reg.o);
+        }
+        clk_in = bit.to_clock();
+    }
+}
+
+#[test]
+fn test_ripple_counter() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(ripple_counter());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    for _ in 0..0x80 {
+        sim.write(sim.io().clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/ripple_counter.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/ripple_counter.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt
new file mode 100644
index 0000000..34643f2
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/array_rw.txt
@@ -0,0 +1,1696 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 54,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index", ty: UInt<8> },
+                },
+                1: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x10 16) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(34), // (0x10) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(0), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]", ty: UInt<8> },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]", ty: UInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(3), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]", ty: UInt<8> },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(41), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]", ty: UInt<8> },
+                },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(42), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(5), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]", ty: UInt<8> },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(6), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]", ty: UInt<8> },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]", ty: UInt<8> },
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]", ty: UInt<8> },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(46), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(9), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]", ty: UInt<8> },
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(47), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(10), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]", ty: UInt<8> },
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(11), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]", ty: UInt<8> },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(12), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]", ty: UInt<8> },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(13), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]", ty: UInt<8> },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(14), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]", ty: UInt<8> },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(52), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                18: BranchIfZero {
+                    target: 20,
+                    value: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                19: WriteIndexed {
+                    dest: StatePartIndex<BigSlots>(37) /* (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> } */ [StatePartIndex<SmallSlots>(0) /* (0x10 16) SlotDebugData { name: "", ty: UInt<8> } */ , len=16, stride=1],,
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(38), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]", ty: UInt<8> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(39), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(40), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]", ty: UInt<8> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(41), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]", ty: UInt<8> },
+                },
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(42), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]", ty: UInt<8> },
+                },
+                26: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]", ty: UInt<8> },
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]", ty: UInt<8> },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]", ty: UInt<8> },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(46), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]", ty: UInt<8> },
+                },
+                30: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(47), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]", ty: UInt<8> },
+                },
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(48), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]", ty: UInt<8> },
+                },
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(28), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(49), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]", ty: UInt<8> },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(50), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]", ty: UInt<8> },
+                },
+                34: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(51), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]", ty: UInt<8> },
+                },
+                35: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(52), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:14:1
+                36: ReadIndexed {
+                    dest: StatePartIndex<BigSlots>(53), // (0xff) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37) /* (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> } */ [StatePartIndex<SmallSlots>(1) /* (0x0 0) SlotDebugData { name: "", ty: UInt<8> } */ , len=16, stride=1],,
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(53), // (0xff) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                38: Return,
+            ],
+            ..
+        },
+        pc: 38,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                16,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                0,
+                255,
+                16,
+                0,
+                1,
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                255,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::array_rw,
+        instantiated: Module {
+            name: array_rw,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_en,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[0],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[10],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[11],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[12],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[13],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[14],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[15],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[1],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[2],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[3],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[4],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[5],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[6],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[7],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[8],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[9],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[0],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[10],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[11],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[12],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[13],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[14],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[15],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[1],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[2],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[3],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[4],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[5],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[6],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[7],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[8],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[9],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_en,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_index,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "array_rw",
+        children: [
+            TraceModuleIO {
+                name: "array_in",
+                child: TraceArray {
+                    name: "array_in",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(1),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(2),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(4),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(6),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(7),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(8),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(9),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(10),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(11),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(12),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(13),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(14),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(15),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Source,
+                },
+                ty: Array<UInt<8>, 16>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "array_out",
+                child: TraceArray {
+                    name: "array_out",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(16),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(17),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(18),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(19),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(20),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(21),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(22),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(23),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(24),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(25),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(26),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(27),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(28),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(29),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(30),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(31),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Sink,
+                },
+                ty: Array<UInt<8>, 16>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "read_index",
+                child: TraceUInt {
+                    location: TraceScalarId(32),
+                    name: "read_index",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "read_data",
+                child: TraceUInt {
+                    location: TraceScalarId(33),
+                    name: "read_data",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "write_index",
+                child: TraceUInt {
+                    location: TraceScalarId(34),
+                    name: "write_index",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "write_data",
+                child: TraceUInt {
+                    location: TraceScalarId(35),
+                    name: "write_data",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "write_en",
+                child: TraceBool {
+                    location: TraceScalarId(36),
+                    name: "write_en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceWire {
+                name: "array_wire",
+                child: TraceArray {
+                    name: "array_wire",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(37),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(38),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(39),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(40),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(41),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(42),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(43),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(44),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(45),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(46),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(47),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(48),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(49),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(50),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(51),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(52),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Duplex,
+                },
+                ty: Array<UInt<8>, 16>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(12),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(13),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(14),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xfe,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(19),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(22),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(23),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(24),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(24),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(25),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(25),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(26),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(26),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(27),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(27),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(28),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(28),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(29),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(29),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(30),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(30),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(31),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(31),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xe1,
+        },
+        SimTrace {
+            id: TraceScalarId(32),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(32),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(33),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(33),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(34),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<8>,
+            },
+            state: 0x10,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(35),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0xe1,
+        },
+        SimTrace {
+            id: TraceScalarId(36),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(36),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(37),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(37),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(38),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(38),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(39),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(39),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(40),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(40),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(41),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(41),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(42),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(42),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(43),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(43),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(44),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(44),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(45),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(45),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(46),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(46),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(47),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(47),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(48),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(48),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(49),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(49),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(50),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(50),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(51),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(51),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(52),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(52),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xe1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 34 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/array_rw.vcd b/crates/fayalite/tests/sim/expected/array_rw.vcd
new file mode 100644
index 0000000..8ede394
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/array_rw.vcd
@@ -0,0 +1,283 @@
+$timescale 1 ps $end
+$scope module array_rw $end
+$scope struct array_in $end
+$var wire 8 ! \[0] $end
+$var wire 8 " \[1] $end
+$var wire 8 # \[2] $end
+$var wire 8 $ \[3] $end
+$var wire 8 % \[4] $end
+$var wire 8 & \[5] $end
+$var wire 8 ' \[6] $end
+$var wire 8 ( \[7] $end
+$var wire 8 ) \[8] $end
+$var wire 8 * \[9] $end
+$var wire 8 + \[10] $end
+$var wire 8 , \[11] $end
+$var wire 8 - \[12] $end
+$var wire 8 . \[13] $end
+$var wire 8 / \[14] $end
+$var wire 8 0 \[15] $end
+$upscope $end
+$scope struct array_out $end
+$var wire 8 1 \[0] $end
+$var wire 8 2 \[1] $end
+$var wire 8 3 \[2] $end
+$var wire 8 4 \[3] $end
+$var wire 8 5 \[4] $end
+$var wire 8 6 \[5] $end
+$var wire 8 7 \[6] $end
+$var wire 8 8 \[7] $end
+$var wire 8 9 \[8] $end
+$var wire 8 : \[9] $end
+$var wire 8 ; \[10] $end
+$var wire 8 < \[11] $end
+$var wire 8 = \[12] $end
+$var wire 8 > \[13] $end
+$var wire 8 ? \[14] $end
+$var wire 8 @ \[15] $end
+$upscope $end
+$var wire 8 A read_index $end
+$var wire 8 B read_data $end
+$var wire 8 C write_index $end
+$var wire 8 D write_data $end
+$var wire 1 E write_en $end
+$scope struct array_wire $end
+$var wire 8 F \[0] $end
+$var wire 8 G \[1] $end
+$var wire 8 H \[2] $end
+$var wire 8 I \[3] $end
+$var wire 8 J \[4] $end
+$var wire 8 K \[5] $end
+$var wire 8 L \[6] $end
+$var wire 8 M \[7] $end
+$var wire 8 N \[8] $end
+$var wire 8 O \[9] $end
+$var wire 8 P \[10] $end
+$var wire 8 Q \[11] $end
+$var wire 8 R \[12] $end
+$var wire 8 S \[13] $end
+$var wire 8 T \[14] $end
+$var wire 8 U \[15] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11111111 !
+b1111111 "
+b111111 #
+b11111 $
+b1111 %
+b111 &
+b11 '
+b1 (
+b0 )
+b10000000 *
+b11000000 +
+b11100000 ,
+b11110000 -
+b11111000 .
+b11111100 /
+b11111110 0
+b11111111 1
+b1111111 2
+b111111 3
+b11111 4
+b1111 5
+b111 6
+b11 7
+b1 8
+b0 9
+b10000000 :
+b11000000 ;
+b11100000 <
+b11110000 =
+b11111000 >
+b11111100 ?
+b11111110 @
+b0 A
+b11111111 B
+b0 C
+b0 D
+0E
+b11111111 F
+b1111111 G
+b111111 H
+b11111 I
+b1111 J
+b111 K
+b11 L
+b1 M
+b0 N
+b10000000 O
+b11000000 P
+b11100000 Q
+b11110000 R
+b11111000 S
+b11111100 T
+b11111110 U
+$end
+#1000000
+b1 A
+b1111111 B
+#2000000
+b10 A
+b111111 B
+#3000000
+b11 A
+b11111 B
+#4000000
+b100 A
+b1111 B
+#5000000
+b101 A
+b111 B
+#6000000
+b110 A
+b11 B
+#7000000
+b111 A
+b1 B
+#8000000
+b1000 A
+b0 B
+#9000000
+b1001 A
+b10000000 B
+#10000000
+b1010 A
+b11000000 B
+#11000000
+b1011 A
+b11100000 B
+#12000000
+b1100 A
+b11110000 B
+#13000000
+b1101 A
+b11111000 B
+#14000000
+b1110 A
+b11111100 B
+#15000000
+b1111 A
+b11111110 B
+#16000000
+b10000 A
+b0 B
+#17000000
+b0 1
+b0 A
+1E
+b0 F
+#18000000
+b11111111 1
+b1 2
+b11111111 B
+b1 C
+b1 D
+b11111111 F
+b1 G
+#19000000
+b1111111 2
+b100 3
+b10 C
+b100 D
+b1111111 G
+b100 H
+#20000000
+b111111 3
+b1001 4
+b11 C
+b1001 D
+b111111 H
+b1001 I
+#21000000
+b11111 4
+b10000 5
+b100 C
+b10000 D
+b11111 I
+b10000 J
+#22000000
+b1111 5
+b11001 6
+b101 C
+b11001 D
+b1111 J
+b11001 K
+#23000000
+b111 6
+b100100 7
+b110 C
+b100100 D
+b111 K
+b100100 L
+#24000000
+b11 7
+b110001 8
+b111 C
+b110001 D
+b11 L
+b110001 M
+#25000000
+b1 8
+b1000000 9
+b1000 C
+b1000000 D
+b1 M
+b1000000 N
+#26000000
+b0 9
+b1010001 :
+b1001 C
+b1010001 D
+b0 N
+b1010001 O
+#27000000
+b10000000 :
+b1100100 ;
+b1010 C
+b1100100 D
+b10000000 O
+b1100100 P
+#28000000
+b11000000 ;
+b1111001 <
+b1011 C
+b1111001 D
+b11000000 P
+b1111001 Q
+#29000000
+b11100000 <
+b10010000 =
+b1100 C
+b10010000 D
+b11100000 Q
+b10010000 R
+#30000000
+b11110000 =
+b10101001 >
+b1101 C
+b10101001 D
+b11110000 R
+b10101001 S
+#31000000
+b11111000 >
+b11000100 ?
+b1110 C
+b11000100 D
+b11111000 S
+b11000100 T
+#32000000
+b11111100 ?
+b11100001 @
+b1111 C
+b11100001 D
+b11111100 T
+b11100001 U
+#33000000
+b11111110 @
+b10000 C
+b0 D
+b11111110 U
+#34000000
diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
new file mode 100644
index 0000000..c4242c4
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
@@ -0,0 +1,174 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
+                },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    value: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                3: BranchIfZero {
+                    target: 5,
+                    value: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: Return,
+            ],
+            ..
+        },
+        pc: 5,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                1,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::conditional_assignment_last,
+        instantiated: Module {
+            name: conditional_assignment_last,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::conditional_assignment_last,
+                instantiated: Module {
+                    name: conditional_assignment_last,
+                    ..
+                },
+            }.i,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::conditional_assignment_last,
+                instantiated: Module {
+                    name: conditional_assignment_last,
+                    ..
+                },
+            }.i,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "conditional_assignment_last",
+        children: [
+            TraceModuleIO {
+                name: "i",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "i",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceBool {
+                    location: TraceScalarId(1),
+                    name: "w",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 2 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd
new file mode 100644
index 0000000..dd9a85a
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd
@@ -0,0 +1,14 @@
+$timescale 1 ps $end
+$scope module conditional_assignment_last $end
+$var wire 1 ! i $end
+$var wire 1 " w $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+$end
+#1000000
+1!
+0"
+#2000000
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
new file mode 100644
index 0000000..d357741
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -0,0 +1,127 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x5,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                2: Return,
+            ],
+            ..
+        },
+        pc: 2,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                5,
+                5,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::connect_const,
+        instantiated: Module {
+            name: connect_const,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::connect_const,
+                instantiated: Module {
+                    name: connect_const,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::connect_const,
+                instantiated: Module {
+                    name: connect_const,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "connect_const",
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    location: TraceScalarId(0),
+                    name: "o",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0x05,
+            last_state: 0x05,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [],
+    instant: 0 s,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
new file mode 100644
index 0000000..b3eb3ea
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -0,0 +1,194 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 5,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    value: 0x1,
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: Return,
+            ],
+            ..
+        },
+        pc: 5,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                1,
+                1,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::connect_const_reset,
+        instantiated: Module {
+            name: connect_const_reset,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.reset_out,
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.bit_out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.bit_out,
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.reset_out,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "connect_const_reset",
+        children: [
+            TraceModuleIO {
+                name: "reset_out",
+                child: TraceAsyncReset {
+                    location: TraceScalarId(0),
+                    name: "reset_out",
+                    flow: Sink,
+                },
+                ty: AsyncReset,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "bit_out",
+                child: TraceBool {
+                    location: TraceScalarId(1),
+                    name: "bit_out",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 1 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd
new file mode 100644
index 0000000..50b427c
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd
@@ -0,0 +1,11 @@
+$timescale 1 ps $end
+$scope module connect_const_reset $end
+$var wire 1 ! reset_out $end
+$var wire 1 " bit_out $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+1!
+1"
+$end
+#1000000
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
new file mode 100644
index 0000000..558d943
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -0,0 +1,367 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 10,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                2: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                3: Const {
+                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                4: BranchIfZero {
+                    target: 6,
+                    value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                6: Add {
+                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                7: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                10: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                11: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                12: BranchIfSmallNonZero {
+                    target: 16,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                13: BranchIfSmallZero {
+                    target: 17,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                15: Branch {
+                    target: 17,
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                17: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                18: Return,
+            ],
+            ..
+        },
+        pc: 18,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                0,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceAsyncReset {
+                            location: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: AsyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: AsyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    location: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    location: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd
new file mode 100644
index 0000000..a4b2ee9
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_async.vcd
@@ -0,0 +1,217 @@
+$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+0"
+b0 #
+b0 $
+$end
+#500000
+1"
+b11 #
+b11 $
+#1000000
+1!
+#1500000
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
new file mode 100644
index 0000000..d31db25
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -0,0 +1,348 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 9,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:6:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                2: Add {
+                    dest: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                3: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                5: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                6: Const {
+                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                7: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                8: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                9: BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                10: BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                12: Branch {
+                    target: 14,
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                14: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                15: Return,
+            ],
+            ..
+        },
+        pc: 15,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            location: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    location: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    location: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd
new file mode 100644
index 0000000..bf6249e
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd
@@ -0,0 +1,214 @@
+$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+b0 #
+b0 $
+$end
+#1000000
+1!
+b11 $
+b11 #
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt
new file mode 100644
index 0000000..5c6c18a
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt
@@ -0,0 +1,157 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(3), // (0x6) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x6,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x6) SlotDebugData { name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(3), // (0x6) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x5,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                4: Return,
+            ],
+            ..
+        },
+        pc: 4,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                5,
+                5,
+                6,
+                6,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::duplicate_names,
+        instantiated: Module {
+            name: duplicate_names,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [],
+        uninitialized_ios: {},
+        io_targets: {},
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "duplicate_names",
+        children: [
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(0),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(1),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0x05,
+            last_state: 0x05,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x06,
+            last_state: 0x06,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 1 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.vcd b/crates/fayalite/tests/sim/expected/duplicate_names.vcd
new file mode 100644
index 0000000..1e9f6c6
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/duplicate_names.vcd
@@ -0,0 +1,11 @@
+$timescale 1 ps $end
+$scope module duplicate_names $end
+$var wire 8 ! w $end
+$var wire 8 " w_2 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b101 !
+b110 "
+$end
+#1000000
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
new file mode 100644
index 0000000..61ce5d5
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -0,0 +1,1923 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 7,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B,
+                                    C,
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 111,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_in",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_in",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_out",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_out",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::b_out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::b2_out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::the_reg",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::the_reg$next",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".1.0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".1.a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(98), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x0,
+                },
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    value: 0x0,
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                // at: module-XXXXXXXXXX.rs:18:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: SliceInt {
+                    dest: StatePartIndex<BigSlots>(77), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 2,
+                    len: 2,
+                },
+                6: CastToSInt {
+                    dest: StatePartIndex<BigSlots>(78), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(77), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                7: Const {
+                    dest: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x2,
+                },
+                8: SliceInt {
+                    dest: StatePartIndex<BigSlots>(57), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 1,
+                    len: 1,
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(57), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(76), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(54), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 0,
+                    len: 1,
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(54), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(53), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(74), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(75), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(76), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(71), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(74), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                },
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(72), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(75), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(73), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(78), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(66), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(71), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(72), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(69), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(73), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                },
+                25: Shl {
+                    dest: StatePartIndex<BigSlots>(79), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    rhs: 1,
+                },
+                26: Or {
+                    dest: StatePartIndex<BigSlots>(80), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(79), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                27: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(81), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(69), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    dest_width: 2,
+                },
+                28: Shl {
+                    dest: StatePartIndex<BigSlots>(82), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(81), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                29: Or {
+                    dest: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(80), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(82), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                30: Shl {
+                    dest: StatePartIndex<BigSlots>(84), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: 2,
+                },
+                31: Or {
+                    dest: StatePartIndex<BigSlots>(85), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(66), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(84), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                32: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(86), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(85), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest_width: 6,
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(86), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                34: Const {
+                    dest: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x1,
+                },
+                35: CmpEq {
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                38: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(53), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                39: Copy {
+                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                40: Shl {
+                    dest: StatePartIndex<BigSlots>(60), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                41: Or {
+                    dest: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(60), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                42: Shl {
+                    dest: StatePartIndex<BigSlots>(62), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                43: Or {
+                    dest: StatePartIndex<BigSlots>(63), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(62), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                44: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(64), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(63), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    dest_width: 6,
+                },
+                45: Copy {
+                    dest: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(64), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                46: Const {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x0,
+                },
+                47: CmpEq {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                48: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                49: SliceInt {
+                    dest: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    start: 2,
+                    len: 2,
+                },
+                50: SliceInt {
+                    dest: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                51: SliceInt {
+                    dest: StatePartIndex<BigSlots>(32), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                52: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                53: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                54: Copy {
+                    dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                55: Copy {
+                    dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                56: Shl {
+                    dest: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                57: Or {
+                    dest: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                58: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(94), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 4,
+                },
+                59: Copy {
+                    dest: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(98), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(96), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                61: Copy {
+                    dest: StatePartIndex<BigSlots>(97), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(97), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                63: Shl {
+                    dest: StatePartIndex<BigSlots>(100), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                64: Or {
+                    dest: StatePartIndex<BigSlots>(101), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(96), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(100), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                65: Shl {
+                    dest: StatePartIndex<BigSlots>(102), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(101), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 1,
+                },
+                66: Or {
+                    dest: StatePartIndex<BigSlots>(103), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(102), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                67: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(104), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(103), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    dest_width: 3,
+                },
+                68: Copy {
+                    dest: StatePartIndex<BigSlots>(105), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(104), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                69: SliceInt {
+                    dest: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    start: 2,
+                    len: 4,
+                },
+                70: SliceInt {
+                    dest: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 0,
+                    len: 2,
+                },
+                71: SliceInt {
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                72: SliceInt {
+                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                73: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                74: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                75: SliceInt {
+                    dest: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 2,
+                    len: 2,
+                },
+                76: CastToSInt {
+                    dest: StatePartIndex<BigSlots>(44), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                77: Copy {
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                },
+                78: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                },
+                79: Copy {
+                    dest: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(44), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                },
+                80: Shl {
+                    dest: StatePartIndex<BigSlots>(106), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    rhs: 1,
+                },
+                81: Or {
+                    dest: StatePartIndex<BigSlots>(107), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(106), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                82: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(108), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest_width: 2,
+                },
+                83: Shl {
+                    dest: StatePartIndex<BigSlots>(109), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(108), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                84: Or {
+                    dest: StatePartIndex<BigSlots>(110), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(107), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(109), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                85: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    rhs: 0x3,
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                86: BranchIfSmallNeImmediate {
+                    target: 89,
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x0,
+                },
+                // at: module-XXXXXXXXXX.rs:20:1
+                87: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:21:1
+                88: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                89: BranchIfSmallNeImmediate {
+                    target: 93,
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:22:1
+                90: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:23:1
+                91: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(94), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:24:1
+                92: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(105), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                93: BranchIfSmallNeImmediate {
+                    target: 96,
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x2,
+                },
+                // at: module-XXXXXXXXXX.rs:25:1
+                94: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:26:1
+                95: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(110), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                96: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                97: Const {
+                    dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    value: 0x0,
+                },
+                98: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                99: BranchIfZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                100: BranchIfZero {
+                    target: 102,
+                    value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:14:1
+                101: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                102: BranchIfNonZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                103: BranchIfZero {
+                    target: 105,
+                    value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:16:1
+                104: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                105: BranchIfNonZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                106: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                107: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
+                },
+                108: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                109: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                110: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                111: SliceInt {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    start: 1,
+                    len: 2,
+                },
+                112: SliceInt {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                113: SliceInt {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                114: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                115: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                116: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                117: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                118: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                119: SliceInt {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    start: 1,
+                    len: 2,
+                },
+                120: SliceInt {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                121: SliceInt {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                122: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                123: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                124: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                125: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                126: BranchIfSmallZero {
+                    target: 131,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                127: BranchIfSmallNonZero {
+                    target: 130,
+                    value: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                128: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                129: Branch {
+                    target: 131,
+                },
+                130: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                131: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                132: Return,
+            ],
+            ..
+        },
+        pc: 132,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                2,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                1,
+                2,
+                15,
+                2,
+                15,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                62,
+                62,
+                0,
+                0,
+                1,
+                1,
+                62,
+                3,
+                1,
+                1,
+                1,
+                1,
+                1,
+                -1,
+                1,
+                1,
+                15,
+                3,
+                1,
+                1,
+                3,
+                -1,
+                0,
+                0,
+                1,
+                0,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                2,
+                3,
+                12,
+                13,
+                13,
+                13,
+                2,
+                1,
+                1,
+                -1,
+                2,
+                1,
+                1,
+                -1,
+                1,
+                1,
+                1,
+                3,
+                -1,
+                2,
+                3,
+                3,
+                12,
+                15,
+                60,
+                62,
+                62,
+                62,
+                0,
+                0,
+                0,
+                1,
+                2,
+                3,
+                3,
+                1,
+                1,
+                1,
+                1,
+                1,
+                2,
+                3,
+                6,
+                7,
+                7,
+                7,
+                2,
+                3,
+                3,
+                12,
+                15,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::enums,
+        instantiated: Module {
+            name: enums,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b2_out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b2_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_out,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "enums",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            location: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "en",
+                child: TraceBool {
+                    location: TraceScalarId(2),
+                    name: "en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "which_in",
+                child: TraceUInt {
+                    location: TraceScalarId(3),
+                    name: "which_in",
+                    ty: UInt<2>,
+                    flow: Source,
+                },
+                ty: UInt<2>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "data_in",
+                child: TraceUInt {
+                    location: TraceScalarId(4),
+                    name: "data_in",
+                    ty: UInt<4>,
+                    flow: Source,
+                },
+                ty: UInt<4>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "which_out",
+                child: TraceUInt {
+                    location: TraceScalarId(5),
+                    name: "which_out",
+                    ty: UInt<2>,
+                    flow: Sink,
+                },
+                ty: UInt<2>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "data_out",
+                child: TraceUInt {
+                    location: TraceScalarId(6),
+                    name: "data_out",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "b_out",
+                child: TraceEnumWithFields {
+                    name: "b_out",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(7),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                        },
+                        flow: Sink,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "HdlSome",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(8),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(9),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "b2_out",
+                child: TraceEnumWithFields {
+                    name: "b2_out",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(10),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                        },
+                        flow: Sink,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "HdlSome",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(11),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(12),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+                flow: Sink,
+            },
+            TraceReg {
+                name: "the_reg",
+                child: TraceEnumWithFields {
+                    name: "the_reg",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(13),
+                        name: "$tag",
+                        ty: Enum {
+                            A,
+                            B(Bundle {0: UInt<1>, 1: Bool}),
+                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "B",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(14),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(15),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "C",
+                            fields: [
+                                TraceArray {
+                                    name: "a",
+                                    elements: [
+                                        TraceUInt {
+                                            location: TraceScalarId(16),
+                                            name: "[0]",
+                                            ty: UInt<1>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(17),
+                                            name: "[1]",
+                                            ty: UInt<1>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Array<UInt<1>, 2>,
+                                    flow: Source,
+                                },
+                                TraceSInt {
+                                    location: TraceScalarId(18),
+                                    name: "b",
+                                    ty: SInt<2>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                a: Array<UInt<1>, 2>,
+                                /* offset = 2 */
+                                b: SInt<2>,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        A,
+                        B(Bundle {0: UInt<1>, 1: Bool}),
+                        C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                    },
+                    flow: Duplex,
+                },
+                ty: Enum {
+                    A,
+                    B(Bundle {0: UInt<1>, 1: Bool}),
+                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<1>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<1>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(17),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(6),
+                ty: Enum {
+                    A,
+                    B(Bundle {0: UInt<1>, 1: Bool}),
+                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                },
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(27),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(28),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(36),
+                ty: SInt<2>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 16 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(3),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
new file mode 100644
index 0000000..aff867b
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/enums.vcd
@@ -0,0 +1,126 @@
+$timescale 1 ps $end
+$scope module enums $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 1 # en $end
+$var wire 2 $ which_in $end
+$var wire 4 % data_in $end
+$var wire 2 & which_out $end
+$var wire 4 ' data_out $end
+$scope struct b_out $end
+$var string 1 ( \$tag $end
+$scope struct HdlSome $end
+$var wire 1 ) \0 $end
+$var wire 1 * \1 $end
+$upscope $end
+$upscope $end
+$scope struct b2_out $end
+$var string 1 + \$tag $end
+$scope struct HdlSome $end
+$var wire 1 , \0 $end
+$var wire 1 - \1 $end
+$upscope $end
+$upscope $end
+$scope struct the_reg $end
+$var string 1 . \$tag $end
+$scope struct B $end
+$var reg 1 / \0 $end
+$var reg 1 0 \1 $end
+$upscope $end
+$scope struct C $end
+$scope struct a $end
+$var reg 1 1 \[0] $end
+$var reg 1 2 \[1] $end
+$upscope $end
+$var reg 2 3 b $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+0#
+b0 $
+b0 %
+b0 &
+b0 '
+sHdlNone\x20(0) (
+0)
+0*
+sHdlNone\x20(0) +
+0,
+0-
+sA\x20(0) .
+0/
+00
+01
+02
+b0 3
+$end
+#1000000
+1!
+#1100000
+0"
+#2000000
+0!
+#3000000
+1!
+#4000000
+1#
+b1 $
+0!
+#5000000
+1!
+b1 &
+sHdlSome\x20(1) (
+sHdlSome\x20(1) +
+sB\x20(1) .
+#6000000
+0#
+b0 $
+0!
+#7000000
+1!
+#8000000
+1#
+b1 $
+b1111 %
+0!
+#9000000
+1!
+b11 '
+1)
+1*
+1,
+1-
+1/
+10
+11
+12
+#10000000
+0!
+#11000000
+1!
+#12000000
+b10 $
+0!
+#13000000
+1!
+b10 &
+b1111 '
+sHdlNone\x20(0) (
+0)
+0*
+sHdlNone\x20(0) +
+0,
+0-
+sC\x20(2) .
+b11 3
+#14000000
+0!
+#15000000
+1!
+#16000000
diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt
new file mode 100644
index 0000000..6cce70b
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module.txt
@@ -0,0 +1,220 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module: extern_module).extern_module::i",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module: extern_module).extern_module::o",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Return,
+            ],
+            ..
+        },
+        pc: 0,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::extern_module,
+        instantiated: Module {
+            name: extern_module,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.i,
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.i,
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: extern_module::i,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: extern_module::i,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: extern_module::i,
+                            is_input: true,
+                            ty: Bool,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Instant(
+                    20.500000000000 μs,
+                ),
+            },
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "extern_module",
+        children: [
+            TraceModuleIO {
+                name: "i",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "i",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceBool {
+                    location: TraceScalarId(1),
+                    name: "o",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 20 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd
new file mode 100644
index 0000000..e026a50
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module.vcd
@@ -0,0 +1,51 @@
+$timescale 1 ps $end
+$scope module extern_module $end
+$var wire 1 ! i $end
+$var wire 1 " o $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+$end
+#500000
+#1500000
+0"
+#2500000
+1"
+#3500000
+0"
+#4500000
+1"
+#5500000
+0"
+#6500000
+1"
+#7500000
+0"
+#8500000
+1"
+#9500000
+0"
+#10000000
+1!
+#10500000
+#11500000
+1"
+#12500000
+0"
+#13500000
+1"
+#14500000
+0"
+#15500000
+1"
+#16500000
+0"
+#17500000
+1"
+#18500000
+0"
+#19500000
+1"
+#20000000
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt
new file mode 100644
index 0000000..ec842ff
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module2.txt
@@ -0,0 +1,310 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 3,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Return,
+            ],
+            ..
+        },
+        pc: 0,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                1,
+                101,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::extern_module2,
+        instantiated: Module {
+            name: extern_module2,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: extern_module2::en,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::o,
+                        is_input: false,
+                        ty: UInt<8>,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: extern_module2::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::en,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::o,
+                        is_input: false,
+                        ty: UInt<8>,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: extern_module2::en,
+                            is_input: true,
+                            ty: Bool,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module2::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module2::o,
+                            is_input: false,
+                            ty: UInt<8>,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX.rs:5:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        value: OpaqueSimValue {
+                            bits: 0x1_u1,
+                        },
+                    },
+                },
+            },
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "extern_module2",
+        children: [
+            TraceModuleIO {
+                name: "en",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "clk",
+                child: TraceClock {
+                    location: TraceScalarId(1),
+                    name: "clk",
+                    flow: Source,
+                },
+                ty: Clock,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    location: TraceScalarId(2),
+                    name: "o",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x65,
+            last_state: 0x65,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 60 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd
new file mode 100644
index 0000000..464f4bd
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd
@@ -0,0 +1,150 @@
+$timescale 1 ps $end
+$scope module extern_module2 $end
+$var wire 1 ! en $end
+$var wire 1 " clk $end
+$var wire 8 # o $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+1!
+0"
+b1001000 #
+$end
+#1000000
+1"
+b1100101 #
+#2000000
+0"
+#3000000
+1"
+b1101100 #
+#4000000
+0"
+#5000000
+1"
+#6000000
+0"
+#7000000
+1"
+b1101111 #
+#8000000
+0"
+#9000000
+1"
+b101100 #
+#10000000
+0!
+0"
+#11000000
+1"
+#12000000
+0"
+#13000000
+1"
+#14000000
+0"
+#15000000
+1"
+#16000000
+0"
+#17000000
+1"
+#18000000
+0"
+#19000000
+1"
+#20000000
+1!
+0"
+#21000000
+1"
+b100000 #
+#22000000
+0"
+#23000000
+1"
+b1010111 #
+#24000000
+0"
+#25000000
+1"
+b1101111 #
+#26000000
+0"
+#27000000
+1"
+b1110010 #
+#28000000
+0"
+#29000000
+1"
+b1101100 #
+#30000000
+0!
+0"
+#31000000
+1"
+#32000000
+0"
+#33000000
+1"
+#34000000
+0"
+#35000000
+1"
+#36000000
+0"
+#37000000
+1"
+#38000000
+0"
+#39000000
+1"
+#40000000
+1!
+0"
+#41000000
+1"
+b1100100 #
+#42000000
+0"
+#43000000
+1"
+b100001 #
+#44000000
+0"
+#45000000
+1"
+b1010 #
+#46000000
+0"
+#47000000
+1"
+b1001000 #
+#48000000
+0"
+#49000000
+1"
+b1100101 #
+#50000000
+0!
+0"
+#51000000
+1"
+#52000000
+0"
+#53000000
+1"
+#54000000
+0"
+#55000000
+1"
+#56000000
+0"
+#57000000
+1"
+#58000000
+0"
+#59000000
+1"
+#60000000
diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt
new file mode 100644
index 0000000..cd778d4
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories.txt
@@ -0,0 +1,1616 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 12,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 28,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            data: [
+                                // len = 0x10
+                                [0x0]: 0x2301,
+                                [0x1]: 0x2301,
+                                [0x2]: 0x2301,
+                                [0x3]: 0x2301,
+                                [0x4]: 0x2301,
+                                [0x5]: 0x2301,
+                                [0x6]: 0x2301,
+                                [0x7]: 0x2301,
+                                [0x8]: 0x2301,
+                                [0x9]: 0x2301,
+                                [0xa]: 0x2301,
+                                [0xb]: 0x2301,
+                                [0xc]: 0x2301,
+                                [0xd]: 0x2301,
+                                [0xe]: 0x2301,
+                                [0xf]: 0x2301,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:8:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.addr", ty: UInt<4> },
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.en", ty: Bool },
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.clk", ty: Clock },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(8), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.0", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(9), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.1", ty: SInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.0", ty: Bool },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.1", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.clk", ty: Clock },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.en", ty: Bool },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.addr", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                10: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
+                },
+                11: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
+                },
+                12: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
+                },
+                13: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                14: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
+                },
+                15: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
+                },
+                16: BranchIfSmallZero {
+                    target: 20,
+                    value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                17: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 0,
+                    width: 8,
+                },
+                18: MemoryReadSInt {
+                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 8,
+                    width: 8,
+                },
+                19: Branch {
+                    target: 22,
+                },
+                20: Const {
+                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                    value: 0x0,
+                },
+                21: Const {
+                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                    value: 0x0,
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                24: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
+                },
+                25: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                26: BranchIfSmallZero {
+                    target: 27,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                27: BranchIfSmallZero {
+                    target: 39,
+                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                28: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                29: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                30: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
+                },
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
+                },
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
+                },
+                34: BranchIfSmallZero {
+                    target: 39,
+                    value: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                35: BranchIfZero {
+                    target: 37,
+                    value: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
+                },
+                36: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 0,
+                    width: 8,
+                },
+                37: BranchIfZero {
+                    target: 39,
+                    value: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                38: MemoryWriteSInt {
+                    value: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 8,
+                    width: 8,
+                },
+                39: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                40: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                41: Return,
+            ],
+            ..
+        },
+        pc: 41,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                    data: [
+                        // len = 0x10
+                        [0x0]: 0x4050,
+                        [0x1]: 0xa090,
+                        [0x2]: 0xc0b0,
+                        [0x3]: 0x2301,
+                        [0x4]: 0x2301,
+                        [0x5]: 0x2301,
+                        [0x6]: 0x2301,
+                        [0x7]: 0x2301,
+                        [0x8]: 0x2301,
+                        [0x9]: 0x2301,
+                        [0xa]: 0x2301,
+                        [0xb]: 0x2301,
+                        [0xc]: 0x2301,
+                        [0xd]: 0x2301,
+                        [0xe]: 0x2301,
+                        [0xf]: 0x2301,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                1,
+                2,
+                1,
+                0,
+                0,
+                0,
+                2,
+                2,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                2,
+                1,
+                0,
+                176,
+                -64,
+                2,
+                0,
+                0,
+                208,
+                -32,
+                1,
+                1,
+                2,
+                1,
+                0,
+                176,
+                -64,
+                2,
+                0,
+                0,
+                208,
+                -32,
+                1,
+                1,
+                208,
+                -32,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories,
+        instantiated: Module {
+            name: memories,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.addr,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.clk,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data.1,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.en,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.addr,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.clk,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data.1,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.en,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask.1,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "memories",
+        children: [
+            TraceModuleIO {
+                name: "r",
+                child: TraceBundle {
+                    name: "r",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "data",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(3),
+                                    name: "0",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceSInt {
+                                    location: TraceScalarId(4),
+                                    name: "1",
+                                    ty: SInt<8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "w",
+                child: TraceBundle {
+                    name: "w",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "addr",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(7),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "data",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(8),
+                                    name: "0",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceSInt {
+                                    location: TraceScalarId(9),
+                                    name: "1",
+                                    ty: SInt<8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "mask",
+                            fields: [
+                                TraceBool {
+                                    location: TraceScalarId(10),
+                                    name: "0",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(11),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                        /* offset = 22 */
+                        mask: Bundle {
+                            /* offset = 0 */
+                            0: Bool,
+                            /* offset = 1 */
+                            1: Bool,
+                        },
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                    /* offset = 22 */
+                    mask: Bundle {
+                        /* offset = 0 */
+                        0: Bool,
+                        /* offset = 1 */
+                        1: Bool,
+                    },
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 16,
+                element_type: TraceBundle {
+                    name: "mem",
+                    fields: [
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 16,
+                                stride: 16,
+                                start: 0,
+                                len: 8,
+                            },
+                            name: "0",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceSInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 16,
+                                stride: 16,
+                                start: 8,
+                                len: 8,
+                            },
+                            name: "1",
+                            ty: SInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "r0",
+                        bundle: TraceBundle {
+                            name: "r0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(12),
+                                    name: "addr",
+                                    ty: UInt<4>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(13),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(14),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "data",
+                                    fields: [
+                                        TraceUInt {
+                                            location: TraceScalarId(15),
+                                            name: "0",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceSInt {
+                                            location: TraceScalarId(16),
+                                            name: "1",
+                                            ty: SInt<8>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: UInt<8>,
+                                        /* offset = 8 */
+                                        1: SInt<8>,
+                                    },
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<4>,
+                                /* offset = 4 */
+                                en: Bool,
+                                /* offset = 5 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 6 */
+                                data: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                        },
+                    },
+                    TraceMemPort {
+                        name: "w1",
+                        bundle: TraceBundle {
+                            name: "w1",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(17),
+                                    name: "addr",
+                                    ty: UInt<4>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(18),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(19),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "data",
+                                    fields: [
+                                        TraceUInt {
+                                            location: TraceScalarId(20),
+                                            name: "0",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceSInt {
+                                            location: TraceScalarId(21),
+                                            name: "1",
+                                            ty: SInt<8>,
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: UInt<8>,
+                                        /* offset = 8 */
+                                        1: SInt<8>,
+                                    },
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "mask",
+                                    fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(22),
+                                            name: "0",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(23),
+                                            name: "1",
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: Bool,
+                                        /* offset = 1 */
+                                        1: Bool,
+                                    },
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<4>,
+                                /* offset = 4 */
+                                en: Bool,
+                                /* offset = 5 */
+                                clk: Clock,
+                                /* offset = 6 */
+                                data: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                /* offset = 22 */
+                                mask: Bundle {
+                                    /* offset = 0 */
+                                    0: Bool,
+                                    /* offset = 1 */
+                                    1: Bool,
+                                },
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            /* offset = 22 */
+                            mask: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                        },
+                    },
+                ],
+                array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0xb0,
+            last_state: 0xb0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: SInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0xd0,
+            last_state: 0xd0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: SInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(10),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(12),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(14),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0xb0,
+            last_state: 0xb0,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: SInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(18),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(19),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0xd0,
+            last_state: 0xd0,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: SInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(22),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(23),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 16,
+            element_type: TraceBundle {
+                name: "mem",
+                fields: [
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 16,
+                            stride: 16,
+                            start: 0,
+                            len: 8,
+                        },
+                        name: "0",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceSInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 16,
+                            stride: 16,
+                            start: 8,
+                            len: 8,
+                        },
+                        name: "1",
+                        ty: SInt<8>,
+                        flow: Duplex,
+                    },
+                ],
+                ty: Bundle {
+                    /* offset = 0 */
+                    0: UInt<8>,
+                    /* offset = 8 */
+                    1: SInt<8>,
+                },
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "r0",
+                    bundle: TraceBundle {
+                        name: "r0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(12),
+                                name: "addr",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(13),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(14),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "data",
+                                fields: [
+                                    TraceUInt {
+                                        location: TraceScalarId(15),
+                                        name: "0",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceSInt {
+                                        location: TraceScalarId(16),
+                                        name: "1",
+                                        ty: SInt<8>,
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                flow: Source,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                    },
+                },
+                TraceMemPort {
+                    name: "w1",
+                    bundle: TraceBundle {
+                        name: "w1",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(17),
+                                name: "addr",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(18),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(19),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "data",
+                                fields: [
+                                    TraceUInt {
+                                        location: TraceScalarId(20),
+                                        name: "0",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceSInt {
+                                        location: TraceScalarId(21),
+                                        name: "1",
+                                        ty: SInt<8>,
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "mask",
+                                fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(22),
+                                        name: "0",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(23),
+                                        name: "1",
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: Bool,
+                                    /* offset = 1 */
+                                    1: Bool,
+                                },
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            /* offset = 22 */
+                            mask: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                        /* offset = 22 */
+                        mask: Bundle {
+                            /* offset = 0 */
+                            0: Bool,
+                            /* offset = 1 */
+                            1: Bool,
+                        },
+                    },
+                },
+            ],
+            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 22 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(6),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd
new file mode 100644
index 0000000..bedc354
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories.vcd
@@ -0,0 +1,408 @@
+$timescale 1 ps $end
+$scope module memories $end
+$scope struct r $end
+$var wire 4 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$scope struct data $end
+$var wire 8 $ \0 $end
+$var wire 8 % \1 $end
+$upscope $end
+$upscope $end
+$scope struct w $end
+$var wire 4 & addr $end
+$var wire 1 ' en $end
+$var wire 1 ( clk $end
+$scope struct data $end
+$var wire 8 ) \0 $end
+$var wire 8 * \1 $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 + \0 $end
+$var wire 1 , \1 $end
+$upscope $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct \[0] $end
+$scope struct mem $end
+$var reg 8 9 \0 $end
+$var reg 8 I \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[1] $end
+$scope struct mem $end
+$var reg 8 : \0 $end
+$var reg 8 J \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[2] $end
+$scope struct mem $end
+$var reg 8 ; \0 $end
+$var reg 8 K \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[3] $end
+$scope struct mem $end
+$var reg 8 < \0 $end
+$var reg 8 L \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[4] $end
+$scope struct mem $end
+$var reg 8 = \0 $end
+$var reg 8 M \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[5] $end
+$scope struct mem $end
+$var reg 8 > \0 $end
+$var reg 8 N \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[6] $end
+$scope struct mem $end
+$var reg 8 ? \0 $end
+$var reg 8 O \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[7] $end
+$scope struct mem $end
+$var reg 8 @ \0 $end
+$var reg 8 P \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[8] $end
+$scope struct mem $end
+$var reg 8 A \0 $end
+$var reg 8 Q \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[9] $end
+$scope struct mem $end
+$var reg 8 B \0 $end
+$var reg 8 R \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[10] $end
+$scope struct mem $end
+$var reg 8 C \0 $end
+$var reg 8 S \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[11] $end
+$scope struct mem $end
+$var reg 8 D \0 $end
+$var reg 8 T \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[12] $end
+$scope struct mem $end
+$var reg 8 E \0 $end
+$var reg 8 U \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[13] $end
+$scope struct mem $end
+$var reg 8 F \0 $end
+$var reg 8 V \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[14] $end
+$scope struct mem $end
+$var reg 8 G \0 $end
+$var reg 8 W \1 $end
+$upscope $end
+$upscope $end
+$scope struct \[15] $end
+$scope struct mem $end
+$var reg 8 H \0 $end
+$var reg 8 X \1 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r0 $end
+$var wire 4 - addr $end
+$var wire 1 . en $end
+$var wire 1 / clk $end
+$scope struct data $end
+$var wire 8 0 \0 $end
+$var wire 8 1 \1 $end
+$upscope $end
+$upscope $end
+$scope struct w1 $end
+$var wire 4 2 addr $end
+$var wire 1 3 en $end
+$var wire 1 4 clk $end
+$scope struct data $end
+$var wire 8 5 \0 $end
+$var wire 8 6 \1 $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 7 \0 $end
+$var wire 1 8 \1 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b1 9
+b100011 I
+b1 :
+b100011 J
+b1 ;
+b100011 K
+b1 <
+b100011 L
+b1 =
+b100011 M
+b1 >
+b100011 N
+b1 ?
+b100011 O
+b1 @
+b100011 P
+b1 A
+b100011 Q
+b1 B
+b100011 R
+b1 C
+b100011 S
+b1 D
+b100011 T
+b1 E
+b100011 U
+b1 F
+b100011 V
+b1 G
+b100011 W
+b1 H
+b100011 X
+b0 !
+0"
+0#
+b0 $
+b0 %
+b0 &
+0'
+0(
+b0 )
+b0 *
+0+
+0,
+b0 -
+0.
+0/
+b0 0
+b0 1
+b0 2
+03
+04
+b0 5
+b0 6
+07
+08
+$end
+#1000000
+1#
+1(
+1/
+14
+#2000000
+1"
+0#
+b1 $
+b100011 %
+1'
+0(
+b10000 )
+b100000 *
+1+
+1,
+1.
+0/
+b1 0
+b100011 1
+13
+04
+b10000 5
+b100000 6
+17
+18
+#3000000
+b10000 9
+b100000 I
+1#
+1(
+1/
+14
+b10000 $
+b100000 %
+b10000 0
+b100000 1
+#4000000
+0#
+0(
+b110000 )
+b1000000 *
+0+
+0/
+04
+b110000 5
+b1000000 6
+07
+#5000000
+b10000 9
+b1000000 I
+1#
+1(
+1/
+14
+b1000000 %
+b1000000 1
+#6000000
+0#
+0(
+b1010000 )
+b1100000 *
+1+
+0,
+0/
+04
+b1010000 5
+b1100000 6
+17
+08
+#7000000
+b1010000 9
+b1000000 I
+1#
+1(
+1/
+14
+b1010000 $
+b1010000 0
+#8000000
+0#
+0(
+b1110000 )
+b10000000 *
+0+
+0/
+04
+b1110000 5
+b10000000 6
+07
+#9000000
+1#
+1(
+1/
+14
+#10000000
+0#
+0'
+0(
+b10010000 )
+b10100000 *
+0/
+03
+04
+b10010000 5
+b10100000 6
+#11000000
+1#
+1(
+1/
+14
+#12000000
+0#
+b1 &
+1'
+0(
+1+
+1,
+0/
+b1 2
+13
+04
+17
+18
+#13000000
+b10010000 :
+b10100000 J
+1#
+1(
+1/
+14
+#14000000
+0#
+b10 &
+0(
+b10110000 )
+b11000000 *
+0/
+b10 2
+04
+b10110000 5
+b11000000 6
+#15000000
+b10110000 ;
+b11000000 K
+1#
+1(
+1/
+14
+#16000000
+0#
+0'
+0(
+b11010000 )
+b11100000 *
+0/
+03
+04
+b11010000 5
+b11100000 6
+#17000000
+1#
+1(
+1/
+14
+#18000000
+b1 !
+0#
+b10010000 $
+b10100000 %
+0(
+b1 -
+0/
+b10010000 0
+b10100000 1
+04
+#19000000
+1#
+1(
+1/
+14
+#20000000
+b10 !
+0#
+b10110000 $
+b11000000 %
+0(
+b10 -
+0/
+b10110000 0
+b11000000 1
+04
+#21000000
+1#
+1(
+1/
+14
+#22000000
+0#
+0(
+0/
+04
diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt
new file mode 100644
index 0000000..2359749
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories2.txt
@@ -0,0 +1,1259 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 11,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 36,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            data: [
+                                // len = 0x5
+                                [0x0]: 0x3,
+                                [0x1]: 0x3,
+                                [0x2]: 0x3,
+                                [0x3]: 0x3,
+                                [0x4]: 0x3,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:13:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                1: SliceInt {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                3: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                },
+                7: Shl {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                8: Or {
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                9: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                13: Const {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x0,
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                16: BranchIfZero {
+                    target: 18,
+                    value: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                22: BranchIfSmallZero {
+                    target: 26,
+                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                23: BranchIfSmallNonZero {
+                    target: 26,
+                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                24: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            //     data: [
+                            //         // len = 0x5
+                            //         [0x0]: 0x0,
+                            //         [0x1]: 0x1,
+                            //         [0x2]: 0x0,
+                            //         [0x3]: 0x3,
+                            //         [0x4]: 0x0,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 2,
+                    start: 0,
+                    width: 2,
+                },
+                25: Branch {
+                    target: 27,
+                },
+                26: Const {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    value: 0x0,
+                },
+                27: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
+                },
+                28: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
+                },
+                29: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
+                },
+                30: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
+                },
+                31: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                33: SliceInt {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                34: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                35: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                37: SliceInt {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                38: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                39: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                40: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                41: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                42: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                43: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                44: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                45: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
+                },
+                46: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                47: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                48: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                49: BranchIfZero {
+                    target: 51,
+                    value: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                50: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            //     data: [
+                            //         // len = 0x5
+                            //         [0x0]: 0x0,
+                            //         [0x1]: 0x1,
+                            //         [0x2]: 0x0,
+                            //         [0x3]: 0x3,
+                            //         [0x4]: 0x0,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 2,
+                    start: 0,
+                    width: 2,
+                },
+                51: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                52: Return,
+            ],
+            ..
+        },
+        pc: 52,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                    data: [
+                        // len = 0x5
+                        [0x0]: 0x0,
+                        [0x1]: 0x1,
+                        [0x2]: 0x0,
+                        [0x3]: 0x3,
+                        [0x4]: 0x0,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                1,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories2,
+        instantiated: Module {
+            name: memories2,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.addr,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.clk,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.en,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.rdata,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wdata,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wmask,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wmode,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "memories2",
+        children: [
+            TraceModuleIO {
+                name: "rw",
+                child: TraceBundle {
+                    name: "rw",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "rdata",
+                            ty: UInt<2>,
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(4),
+                            name: "wmode",
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "wdata",
+                            ty: UInt<2>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "wmask",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        rdata: UInt<2>,
+                        /* offset = 7 */
+                        wmode: Bool,
+                        /* offset = 8 */
+                        wdata: UInt<2>,
+                        /* offset = 10 */
+                        wmask: Bool,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    rdata: UInt<2>,
+                    /* offset = 7 */
+                    wmode: Bool,
+                    /* offset = 8 */
+                    wdata: UInt<2>,
+                    /* offset = 10 */
+                    wmask: Bool,
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 2,
+                element_type: TraceEnumWithFields {
+                    name: "mem",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 5,
+                            stride: 2,
+                            start: 0,
+                            len: 1,
+                        },
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBool {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 5,
+                                stride: 2,
+                                start: 1,
+                                len: 1,
+                            },
+                            name: "HdlSome",
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bool),
+                    },
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "rw0",
+                        bundle: TraceBundle {
+                            name: "rw0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(7),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(8),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(9),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceEnumWithFields {
+                                    name: "rdata",
+                                    discriminant: TraceEnumDiscriminant {
+                                        location: TraceScalarId(10),
+                                        name: "$tag",
+                                        ty: Enum {
+                                            HdlNone,
+                                            HdlSome(Bool),
+                                        },
+                                        flow: Source,
+                                    },
+                                    non_empty_fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(11),
+                                            name: "HdlSome",
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(12),
+                                    name: "wmode",
+                                    flow: Sink,
+                                },
+                                TraceEnumWithFields {
+                                    name: "wdata",
+                                    discriminant: TraceEnumDiscriminant {
+                                        location: TraceScalarId(13),
+                                        name: "$tag",
+                                        ty: Enum {
+                                            HdlNone,
+                                            HdlSome(Bool),
+                                        },
+                                        flow: Sink,
+                                    },
+                                    non_empty_fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(14),
+                                            name: "HdlSome",
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(15),
+                                    name: "wmask",
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 5 */
+                                rdata: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                /* offset = 7 */
+                                wmode: Bool,
+                                /* offset = 8 */
+                                wdata: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                /* offset = 10 */
+                                wmask: Bool,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            rdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 7 */
+                            wmode: Bool,
+                            /* offset = 8 */
+                            wdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 10 */
+                            wmask: Bool,
+                        },
+                    },
+                ],
+                array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<2>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<2>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(8),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(16),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(19),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 2,
+            element_type: TraceEnumWithFields {
+                name: "mem",
+                discriminant: TraceEnumDiscriminant {
+                    location: TraceMemoryLocation {
+                        id: TraceMemoryId(0),
+                        depth: 5,
+                        stride: 2,
+                        start: 0,
+                        len: 1,
+                    },
+                    name: "$tag",
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bool),
+                    },
+                    flow: Duplex,
+                },
+                non_empty_fields: [
+                    TraceBool {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 5,
+                            stride: 2,
+                            start: 1,
+                            len: 1,
+                        },
+                        name: "HdlSome",
+                        flow: Duplex,
+                    },
+                ],
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "rw0",
+                    bundle: TraceBundle {
+                        name: "rw0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(7),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(8),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(9),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceEnumWithFields {
+                                name: "rdata",
+                                discriminant: TraceEnumDiscriminant {
+                                    location: TraceScalarId(10),
+                                    name: "$tag",
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Source,
+                                },
+                                non_empty_fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(11),
+                                        name: "HdlSome",
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                flow: Source,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(12),
+                                name: "wmode",
+                                flow: Sink,
+                            },
+                            TraceEnumWithFields {
+                                name: "wdata",
+                                discriminant: TraceEnumDiscriminant {
+                                    location: TraceScalarId(13),
+                                    name: "$tag",
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Sink,
+                                },
+                                non_empty_fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(14),
+                                        name: "HdlSome",
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(15),
+                                name: "wmask",
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            rdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 7 */
+                            wmode: Bool,
+                            /* offset = 8 */
+                            wdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 10 */
+                            wmask: Bool,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        rdata: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        /* offset = 7 */
+                        wmode: Bool,
+                        /* offset = 8 */
+                        wdata: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        /* offset = 10 */
+                        wmask: Bool,
+                    },
+                },
+            ],
+            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 22 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(3),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd
new file mode 100644
index 0000000..4039754
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories2.vcd
@@ -0,0 +1,363 @@
+$timescale 1 ps $end
+$scope module memories2 $end
+$scope struct rw $end
+$var wire 3 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$var wire 2 $ rdata $end
+$var wire 1 % wmode $end
+$var wire 2 & wdata $end
+$var wire 1 ' wmask $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct \[0] $end
+$scope struct mem $end
+$var string 1 1 \$tag $end
+$var reg 1 6 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct \[1] $end
+$scope struct mem $end
+$var string 1 2 \$tag $end
+$var reg 1 7 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct \[2] $end
+$scope struct mem $end
+$var string 1 3 \$tag $end
+$var reg 1 8 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct \[3] $end
+$scope struct mem $end
+$var string 1 4 \$tag $end
+$var reg 1 9 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct \[4] $end
+$scope struct mem $end
+$var string 1 5 \$tag $end
+$var reg 1 : HdlSome $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct rw0 $end
+$var wire 3 ( addr $end
+$var wire 1 ) en $end
+$var wire 1 * clk $end
+$scope struct rdata $end
+$var string 1 + \$tag $end
+$var wire 1 , HdlSome $end
+$upscope $end
+$var wire 1 - wmode $end
+$scope struct wdata $end
+$var string 1 . \$tag $end
+$var wire 1 / HdlSome $end
+$upscope $end
+$var wire 1 0 wmask $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+sHdlSome\x20(1) 1
+16
+sHdlSome\x20(1) 2
+17
+sHdlSome\x20(1) 3
+18
+sHdlSome\x20(1) 4
+19
+sHdlSome\x20(1) 5
+1:
+b0 !
+0"
+0#
+b0 $
+0%
+b0 &
+0'
+b0 (
+0)
+0*
+sHdlNone\x20(0) +
+0,
+0-
+sHdlNone\x20(0) .
+0/
+00
+$end
+#250000
+1#
+1*
+#500000
+#750000
+0#
+0*
+#1000000
+1"
+1)
+#1250000
+1#
+1*
+b11 $
+sHdlSome\x20(1) +
+1,
+#1500000
+#1750000
+0#
+0*
+#2000000
+0"
+0)
+#2250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+0,
+#2500000
+#2750000
+0#
+0*
+#3000000
+1"
+1%
+1'
+1)
+1-
+10
+#3250000
+sHdlNone\x20(0) 1
+06
+1#
+1*
+#3500000
+#3750000
+0#
+0*
+#4000000
+0%
+0'
+0-
+00
+#4250000
+1#
+1*
+#4500000
+#4750000
+0#
+0*
+#5000000
+1%
+b11 &
+1-
+sHdlSome\x20(1) .
+1/
+#5250000
+1#
+1*
+#5500000
+#5750000
+0#
+0*
+#6000000
+b1 !
+b1 &
+1'
+b1 (
+0/
+10
+#6250000
+sHdlSome\x20(1) 2
+07
+1#
+1*
+#6500000
+#6750000
+0#
+0*
+#7000000
+b10 !
+b10 &
+b10 (
+sHdlNone\x20(0) .
+#7250000
+sHdlNone\x20(0) 3
+08
+1#
+1*
+#7500000
+#7750000
+0#
+0*
+#8000000
+b11 !
+b11 &
+b11 (
+sHdlSome\x20(1) .
+1/
+#8250000
+sHdlSome\x20(1) 4
+19
+1#
+1*
+#8500000
+#8750000
+0#
+0*
+#9000000
+b100 !
+b10 &
+b100 (
+sHdlNone\x20(0) .
+0/
+#9250000
+sHdlNone\x20(0) 5
+0:
+1#
+1*
+#9500000
+#9750000
+0#
+0*
+#10000000
+b101 !
+b1 &
+b101 (
+sHdlSome\x20(1) .
+#10250000
+1#
+1*
+#10500000
+#10750000
+0#
+0*
+#11000000
+b110 !
+b110 (
+#11250000
+1#
+1*
+#11500000
+#11750000
+0#
+0*
+#12000000
+b111 !
+b111 (
+#12250000
+1#
+1*
+#12500000
+#12750000
+0#
+0*
+#13000000
+0%
+b0 &
+0'
+0-
+sHdlNone\x20(0) .
+00
+#13250000
+1#
+1*
+#13500000
+#13750000
+0#
+0*
+#14000000
+b110 !
+b110 (
+#14250000
+1#
+1*
+#14500000
+#14750000
+0#
+0*
+#15000000
+b101 !
+b101 (
+#15250000
+1#
+1*
+#15500000
+#15750000
+0#
+0*
+#16000000
+b100 !
+b100 (
+#16250000
+1#
+1*
+#16500000
+#16750000
+0#
+0*
+#17000000
+b11 !
+b11 (
+#17250000
+1#
+1*
+b11 $
+sHdlSome\x20(1) +
+1,
+#17500000
+#17750000
+0#
+0*
+#18000000
+b10 !
+b10 (
+#18250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+0,
+#18500000
+#18750000
+0#
+0*
+#19000000
+b0 !
+b0 (
+#19250000
+1#
+1*
+#19500000
+#19750000
+0#
+0*
+#20000000
+b1 !
+b1 (
+#20250000
+1#
+1*
+b1 $
+sHdlSome\x20(1) +
+#20500000
+#20750000
+0#
+0*
+#21000000
+b0 !
+0"
+b0 (
+0)
+#21250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+#21500000
+#21750000
+0#
+0*
+#22000000
diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt
new file mode 100644
index 0000000..ad12aa4
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories3.txt
@@ -0,0 +1,3275 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 14,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 108,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Array<UInt<8>, 8>, 8>,
+                            data: [
+                                // len = 0x8
+                                [0x0]: 0x0000000000000000,
+                                [0x1]: 0x0000000000000000,
+                                [0x2]: 0x0000000000000000,
+                                [0x3]: 0x0000000000000000,
+                                [0x4]: 0x0000000000000000,
+                                [0x5]: 0x0000000000000000,
+                                [0x6]: 0x0000000000000000,
+                                [0x7]: 0x0000000000000000,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:8:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.addr", ty: UInt<3> },
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.en", ty: Bool },
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.clk", ty: Clock },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", ty: UInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", ty: UInt<8> },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", ty: UInt<8> },
+                },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", ty: UInt<8> },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", ty: UInt<8> },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", ty: UInt<8> },
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", ty: UInt<8> },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", ty: Bool },
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", ty: Bool },
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", ty: Bool },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", ty: Bool },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", ty: Bool },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", ty: Bool },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", ty: Bool },
+                },
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
+                },
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
+                },
+                26: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.clk", ty: Clock },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.en", ty: Bool },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.addr", ty: UInt<3> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                30: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
+                },
+                31: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
+                },
+                32: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
+                },
+                33: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                34: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
+                },
+                35: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
+                },
+                36: BranchIfSmallZero {
+                    target: 46,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                37: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 0,
+                    width: 8,
+                },
+                38: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 8,
+                    width: 8,
+                },
+                39: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 16,
+                    width: 8,
+                },
+                40: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 24,
+                    width: 8,
+                },
+                41: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 32,
+                    width: 8,
+                },
+                42: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 40,
+                    width: 8,
+                },
+                43: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 48,
+                    width: 8,
+                },
+                44: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 56,
+                    width: 8,
+                },
+                45: Branch {
+                    target: 54,
+                },
+                46: Const {
+                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                47: Const {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                48: Const {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                49: Const {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                50: Const {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                51: Const {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                52: Const {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                53: Const {
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                54: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
+                },
+                55: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                56: BranchIfSmallZero {
+                    target: 73,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                57: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                58: Copy {
+                    dest: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                59: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                61: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                63: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                64: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                65: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                66: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                67: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                68: Copy {
+                    dest: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                69: Copy {
+                    dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                70: Copy {
+                    dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                71: Copy {
+                    dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                72: Copy {
+                    dest: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                73: BranchIfSmallZero {
+                    target: 127,
+                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                74: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                75: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                76: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                77: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                78: Copy {
+                    dest: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                79: Copy {
+                    dest: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                80: Copy {
+                    dest: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                81: Copy {
+                    dest: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                82: Copy {
+                    dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                83: Copy {
+                    dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                84: Copy {
+                    dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                85: Copy {
+                    dest: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                86: Copy {
+                    dest: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
+                },
+                87: Copy {
+                    dest: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
+                },
+                88: Copy {
+                    dest: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
+                },
+                89: Copy {
+                    dest: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
+                },
+                90: Copy {
+                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
+                },
+                91: Copy {
+                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
+                },
+                92: Copy {
+                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
+                },
+                93: Copy {
+                    dest: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
+                },
+                94: Copy {
+                    dest: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                95: Copy {
+                    dest: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                96: Copy {
+                    dest: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                97: Copy {
+                    dest: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                98: Copy {
+                    dest: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                },
+                99: Copy {
+                    dest: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                },
+                100: Copy {
+                    dest: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                },
+                101: Copy {
+                    dest: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                },
+                102: Copy {
+                    dest: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
+                },
+                103: Copy {
+                    dest: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
+                },
+                104: Copy {
+                    dest: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
+                },
+                105: Copy {
+                    dest: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
+                },
+                106: Copy {
+                    dest: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
+                },
+                107: Copy {
+                    dest: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
+                },
+                108: Copy {
+                    dest: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
+                },
+                109: Copy {
+                    dest: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
+                },
+                110: BranchIfSmallZero {
+                    target: 127,
+                    value: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                111: BranchIfZero {
+                    target: 113,
+                    value: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                112: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 0,
+                    width: 8,
+                },
+                113: BranchIfZero {
+                    target: 115,
+                    value: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                114: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 8,
+                    width: 8,
+                },
+                115: BranchIfZero {
+                    target: 117,
+                    value: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                116: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 16,
+                    width: 8,
+                },
+                117: BranchIfZero {
+                    target: 119,
+                    value: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                118: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 24,
+                    width: 8,
+                },
+                119: BranchIfZero {
+                    target: 121,
+                    value: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                },
+                120: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 32,
+                    width: 8,
+                },
+                121: BranchIfZero {
+                    target: 123,
+                    value: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                },
+                122: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 40,
+                    width: 8,
+                },
+                123: BranchIfZero {
+                    target: 125,
+                    value: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                },
+                124: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 48,
+                    width: 8,
+                },
+                125: BranchIfZero {
+                    target: 127,
+                    value: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                },
+                126: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 56,
+                    width: 8,
+                },
+                127: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                128: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                129: Return,
+            ],
+            ..
+        },
+        pc: 129,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Array<UInt<8>, 8>, 8>,
+                    data: [
+                        // len = 0x8
+                        [0x0]: 0x1032547698badcfe,
+                        [0x1]: 0xce8a4602df9b5713,
+                        [0x2]: 0x21676e6974736574,
+                        [0x3]: 0x7473742065726f6d,
+                        [0x4]: 0x0000000000000000,
+                        [0x5]: 0x0000000000000000,
+                        [0x6]: 0x0000000000000000,
+                        [0x7]: 0x0000000000000000,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories3,
+        instantiated: Module {
+            name: memories3,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.addr,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.clk,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[7],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.en,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.addr,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.clk,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[7],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.en,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[7],
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "memories3",
+        children: [
+            TraceModuleIO {
+                name: "r",
+                child: TraceBundle {
+                    name: "r",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "data",
+                            elements: [
+                                TraceUInt {
+                                    location: TraceScalarId(3),
+                                    name: "[0]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(4),
+                                    name: "[1]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(5),
+                                    name: "[2]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(6),
+                                    name: "[3]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(7),
+                                    name: "[4]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(8),
+                                    name: "[5]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(9),
+                                    name: "[6]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(10),
+                                    name: "[7]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Array<UInt<8>, 8>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "w",
+                child: TraceBundle {
+                    name: "w",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(11),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(12),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(13),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "data",
+                            elements: [
+                                TraceUInt {
+                                    location: TraceScalarId(14),
+                                    name: "[0]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(15),
+                                    name: "[1]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(16),
+                                    name: "[2]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(17),
+                                    name: "[3]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(18),
+                                    name: "[4]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(19),
+                                    name: "[5]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(20),
+                                    name: "[6]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(21),
+                                    name: "[7]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<UInt<8>, 8>,
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "mask",
+                            elements: [
+                                TraceBool {
+                                    location: TraceScalarId(22),
+                                    name: "[0]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(23),
+                                    name: "[1]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(24),
+                                    name: "[2]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(25),
+                                    name: "[3]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(26),
+                                    name: "[4]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(27),
+                                    name: "[5]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(28),
+                                    name: "[6]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(29),
+                                    name: "[7]",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<Bool, 8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                        /* offset = 69 */
+                        mask: Array<Bool, 8>,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                    /* offset = 69 */
+                    mask: Array<Bool, 8>,
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 64,
+                element_type: TraceArray {
+                    name: "mem",
+                    elements: [
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 0,
+                                len: 8,
+                            },
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 8,
+                                len: 8,
+                            },
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 16,
+                                len: 8,
+                            },
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 24,
+                                len: 8,
+                            },
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 32,
+                                len: 8,
+                            },
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 40,
+                                len: 8,
+                            },
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 48,
+                                len: 8,
+                            },
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 56,
+                                len: 8,
+                            },
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 8>,
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "r0",
+                        bundle: TraceBundle {
+                            name: "r0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(30),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(31),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(32),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "data",
+                                    elements: [
+                                        TraceUInt {
+                                            location: TraceScalarId(33),
+                                            name: "[0]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(34),
+                                            name: "[1]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(35),
+                                            name: "[2]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(36),
+                                            name: "[3]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(37),
+                                            name: "[4]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(38),
+                                            name: "[5]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(39),
+                                            name: "[6]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(40),
+                                            name: "[7]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Array<UInt<8>, 8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 5 */
+                                data: Array<UInt<8>, 8>,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                        },
+                    },
+                    TraceMemPort {
+                        name: "w1",
+                        bundle: TraceBundle {
+                            name: "w1",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(41),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(42),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(43),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "data",
+                                    elements: [
+                                        TraceUInt {
+                                            location: TraceScalarId(44),
+                                            name: "[0]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(45),
+                                            name: "[1]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(46),
+                                            name: "[2]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(47),
+                                            name: "[3]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(48),
+                                            name: "[4]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(49),
+                                            name: "[5]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(50),
+                                            name: "[6]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(51),
+                                            name: "[7]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Array<UInt<8>, 8>,
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "mask",
+                                    elements: [
+                                        TraceBool {
+                                            location: TraceScalarId(52),
+                                            name: "[0]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(53),
+                                            name: "[1]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(54),
+                                            name: "[2]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(55),
+                                            name: "[3]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(56),
+                                            name: "[4]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(57),
+                                            name: "[5]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(58),
+                                            name: "[6]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(59),
+                                            name: "[7]",
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Array<Bool, 8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                /* offset = 5 */
+                                data: Array<UInt<8>, 8>,
+                                /* offset = 69 */
+                                mask: Array<Bool, 8>,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                            /* offset = 69 */
+                            mask: Array<Bool, 8>,
+                        },
+                    },
+                ],
+                array_type: Array<Array<UInt<8>, 8>, 8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(12),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(14),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(19),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(22),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(23),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(24),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(24),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(25),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(25),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(26),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(26),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(27),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(27),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(28),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(28),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(29),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(29),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(30),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(30),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(31),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(31),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(32),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(32),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(33),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(33),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(34),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(35),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(36),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(36),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(37),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(37),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(38),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(38),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(39),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(39),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(40),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(40),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(41),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(57),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(42),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(58),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(43),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(59),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(44),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(60),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(45),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(61),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(46),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(62),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(47),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(63),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(48),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(64),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(49),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(65),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(50),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(66),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(51),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(67),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(52),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(68),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(53),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(69),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(54),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(70),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(55),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(71),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(56),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(72),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(57),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(73),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(58),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(74),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(59),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(75),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 64,
+            element_type: TraceArray {
+                name: "mem",
+                elements: [
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 0,
+                            len: 8,
+                        },
+                        name: "[0]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 8,
+                            len: 8,
+                        },
+                        name: "[1]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 16,
+                            len: 8,
+                        },
+                        name: "[2]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 24,
+                            len: 8,
+                        },
+                        name: "[3]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 32,
+                            len: 8,
+                        },
+                        name: "[4]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 40,
+                            len: 8,
+                        },
+                        name: "[5]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 48,
+                            len: 8,
+                        },
+                        name: "[6]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 56,
+                            len: 8,
+                        },
+                        name: "[7]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                ],
+                ty: Array<UInt<8>, 8>,
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "r0",
+                    bundle: TraceBundle {
+                        name: "r0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(30),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(31),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(32),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "data",
+                                elements: [
+                                    TraceUInt {
+                                        location: TraceScalarId(33),
+                                        name: "[0]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(34),
+                                        name: "[1]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(35),
+                                        name: "[2]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(36),
+                                        name: "[3]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(37),
+                                        name: "[4]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(38),
+                                        name: "[5]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(39),
+                                        name: "[6]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(40),
+                                        name: "[7]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Array<UInt<8>, 8>,
+                                flow: Source,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                    },
+                },
+                TraceMemPort {
+                    name: "w1",
+                    bundle: TraceBundle {
+                        name: "w1",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(41),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(42),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(43),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "data",
+                                elements: [
+                                    TraceUInt {
+                                        location: TraceScalarId(44),
+                                        name: "[0]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(45),
+                                        name: "[1]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(46),
+                                        name: "[2]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(47),
+                                        name: "[3]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(48),
+                                        name: "[4]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(49),
+                                        name: "[5]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(50),
+                                        name: "[6]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(51),
+                                        name: "[7]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Array<UInt<8>, 8>,
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "mask",
+                                elements: [
+                                    TraceBool {
+                                        location: TraceScalarId(52),
+                                        name: "[0]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(53),
+                                        name: "[1]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(54),
+                                        name: "[2]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(55),
+                                        name: "[3]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(56),
+                                        name: "[4]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(57),
+                                        name: "[5]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(58),
+                                        name: "[6]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(59),
+                                        name: "[7]",
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Array<Bool, 8>,
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                            /* offset = 69 */
+                            mask: Array<Bool, 8>,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                        /* offset = 69 */
+                        mask: Array<Bool, 8>,
+                    },
+                },
+            ],
+            array_type: Array<Array<UInt<8>, 8>, 8>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 15 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(6),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd
new file mode 100644
index 0000000..5768560
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories3.vcd
@@ -0,0 +1,836 @@
+$timescale 1 ps $end
+$scope module memories3 $end
+$scope struct r $end
+$var wire 3 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$scope struct data $end
+$var wire 8 $ \[0] $end
+$var wire 8 % \[1] $end
+$var wire 8 & \[2] $end
+$var wire 8 ' \[3] $end
+$var wire 8 ( \[4] $end
+$var wire 8 ) \[5] $end
+$var wire 8 * \[6] $end
+$var wire 8 + \[7] $end
+$upscope $end
+$upscope $end
+$scope struct w $end
+$var wire 3 , addr $end
+$var wire 1 - en $end
+$var wire 1 . clk $end
+$scope struct data $end
+$var wire 8 / \[0] $end
+$var wire 8 0 \[1] $end
+$var wire 8 1 \[2] $end
+$var wire 8 2 \[3] $end
+$var wire 8 3 \[4] $end
+$var wire 8 4 \[5] $end
+$var wire 8 5 \[6] $end
+$var wire 8 6 \[7] $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 7 \[0] $end
+$var wire 1 8 \[1] $end
+$var wire 1 9 \[2] $end
+$var wire 1 : \[3] $end
+$var wire 1 ; \[4] $end
+$var wire 1 < \[5] $end
+$var wire 1 = \[6] $end
+$var wire 1 > \[7] $end
+$upscope $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct \[0] $end
+$scope struct mem $end
+$var reg 8 ] \[0] $end
+$var reg 8 e \[1] $end
+$var reg 8 m \[2] $end
+$var reg 8 u \[3] $end
+$var reg 8 } \[4] $end
+$var reg 8 '" \[5] $end
+$var reg 8 /" \[6] $end
+$var reg 8 7" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[1] $end
+$scope struct mem $end
+$var reg 8 ^ \[0] $end
+$var reg 8 f \[1] $end
+$var reg 8 n \[2] $end
+$var reg 8 v \[3] $end
+$var reg 8 ~ \[4] $end
+$var reg 8 (" \[5] $end
+$var reg 8 0" \[6] $end
+$var reg 8 8" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[2] $end
+$scope struct mem $end
+$var reg 8 _ \[0] $end
+$var reg 8 g \[1] $end
+$var reg 8 o \[2] $end
+$var reg 8 w \[3] $end
+$var reg 8 !" \[4] $end
+$var reg 8 )" \[5] $end
+$var reg 8 1" \[6] $end
+$var reg 8 9" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[3] $end
+$scope struct mem $end
+$var reg 8 ` \[0] $end
+$var reg 8 h \[1] $end
+$var reg 8 p \[2] $end
+$var reg 8 x \[3] $end
+$var reg 8 "" \[4] $end
+$var reg 8 *" \[5] $end
+$var reg 8 2" \[6] $end
+$var reg 8 :" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[4] $end
+$scope struct mem $end
+$var reg 8 a \[0] $end
+$var reg 8 i \[1] $end
+$var reg 8 q \[2] $end
+$var reg 8 y \[3] $end
+$var reg 8 #" \[4] $end
+$var reg 8 +" \[5] $end
+$var reg 8 3" \[6] $end
+$var reg 8 ;" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[5] $end
+$scope struct mem $end
+$var reg 8 b \[0] $end
+$var reg 8 j \[1] $end
+$var reg 8 r \[2] $end
+$var reg 8 z \[3] $end
+$var reg 8 $" \[4] $end
+$var reg 8 ," \[5] $end
+$var reg 8 4" \[6] $end
+$var reg 8 <" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[6] $end
+$scope struct mem $end
+$var reg 8 c \[0] $end
+$var reg 8 k \[1] $end
+$var reg 8 s \[2] $end
+$var reg 8 { \[3] $end
+$var reg 8 %" \[4] $end
+$var reg 8 -" \[5] $end
+$var reg 8 5" \[6] $end
+$var reg 8 =" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct \[7] $end
+$scope struct mem $end
+$var reg 8 d \[0] $end
+$var reg 8 l \[1] $end
+$var reg 8 t \[2] $end
+$var reg 8 | \[3] $end
+$var reg 8 &" \[4] $end
+$var reg 8 ." \[5] $end
+$var reg 8 6" \[6] $end
+$var reg 8 >" \[7] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r0 $end
+$var wire 3 ? addr $end
+$var wire 1 @ en $end
+$var wire 1 A clk $end
+$scope struct data $end
+$var wire 8 B \[0] $end
+$var wire 8 C \[1] $end
+$var wire 8 D \[2] $end
+$var wire 8 E \[3] $end
+$var wire 8 F \[4] $end
+$var wire 8 G \[5] $end
+$var wire 8 H \[6] $end
+$var wire 8 I \[7] $end
+$upscope $end
+$upscope $end
+$scope struct w1 $end
+$var wire 3 J addr $end
+$var wire 1 K en $end
+$var wire 1 L clk $end
+$scope struct data $end
+$var wire 8 M \[0] $end
+$var wire 8 N \[1] $end
+$var wire 8 O \[2] $end
+$var wire 8 P \[3] $end
+$var wire 8 Q \[4] $end
+$var wire 8 R \[5] $end
+$var wire 8 S \[6] $end
+$var wire 8 T \[7] $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 U \[0] $end
+$var wire 1 V \[1] $end
+$var wire 1 W \[2] $end
+$var wire 1 X \[3] $end
+$var wire 1 Y \[4] $end
+$var wire 1 Z \[5] $end
+$var wire 1 [ \[6] $end
+$var wire 1 \ \[7] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b0 ]
+b0 e
+b0 m
+b0 u
+b0 }
+b0 '"
+b0 /"
+b0 7"
+b0 ^
+b0 f
+b0 n
+b0 v
+b0 ~
+b0 ("
+b0 0"
+b0 8"
+b0 _
+b0 g
+b0 o
+b0 w
+b0 !"
+b0 )"
+b0 1"
+b0 9"
+b0 `
+b0 h
+b0 p
+b0 x
+b0 ""
+b0 *"
+b0 2"
+b0 :"
+b0 a
+b0 i
+b0 q
+b0 y
+b0 #"
+b0 +"
+b0 3"
+b0 ;"
+b0 b
+b0 j
+b0 r
+b0 z
+b0 $"
+b0 ,"
+b0 4"
+b0 <"
+b0 c
+b0 k
+b0 s
+b0 {
+b0 %"
+b0 -"
+b0 5"
+b0 ="
+b0 d
+b0 l
+b0 t
+b0 |
+b0 &"
+b0 ."
+b0 6"
+b0 >"
+b0 !
+0"
+0#
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+b0 ,
+1-
+0.
+b10010 /
+b110100 0
+b1010110 1
+b1111000 2
+b10011010 3
+b10111100 4
+b11011110 5
+b11110000 6
+07
+18
+09
+1:
+1;
+0<
+0=
+1>
+b0 ?
+0@
+0A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+b0 J
+1K
+0L
+b10010 M
+b110100 N
+b1010110 O
+b1111000 P
+b10011010 Q
+b10111100 R
+b11011110 S
+b11110000 T
+0U
+1V
+0W
+1X
+1Y
+0Z
+0[
+1\
+$end
+#250000
+1#
+1.
+1A
+1L
+#500000
+#750000
+0#
+0.
+0A
+0L
+#1000000
+1"
+b1 ,
+0-
+b0 /
+b0 0
+b0 1
+b0 2
+b0 3
+b0 4
+b0 5
+b0 6
+08
+0:
+0;
+0>
+1@
+b1 J
+0K
+b0 M
+b0 N
+b0 O
+b0 P
+b0 Q
+b0 R
+b0 S
+b0 T
+0V
+0X
+0Y
+0\
+#1250000
+b0 ]
+b110100 e
+b0 m
+b1111000 u
+b10011010 }
+b0 '"
+b0 /"
+b11110000 7"
+1#
+1.
+1A
+1L
+#1500000
+#1750000
+0#
+0.
+0A
+0L
+#2000000
+#2250000
+1#
+1.
+1A
+1L
+#2500000
+#2750000
+0#
+0.
+0A
+0L
+#3000000
+b0 ,
+1-
+b11111110 /
+b11011100 0
+b10111010 1
+b10011000 2
+b1110110 3
+b1010100 4
+b110010 5
+b10000 6
+17
+18
+19
+1:
+1;
+1<
+1=
+1>
+b0 J
+1K
+b11111110 M
+b11011100 N
+b10111010 O
+b10011000 P
+b1110110 Q
+b1010100 R
+b110010 S
+b10000 T
+1U
+1V
+1W
+1X
+1Y
+1Z
+1[
+1\
+#3250000
+1#
+1.
+1A
+b110100 C
+b1111000 E
+b10011010 F
+b11110000 I
+1L
+b110100 %
+b1111000 '
+b10011010 (
+b11110000 +
+#3500000
+#3750000
+0#
+0.
+0A
+0L
+#4000000
+#4250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+1L
+#4500000
+#4750000
+0#
+0.
+0A
+0L
+#5000000
+#5250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+1L
+#5500000
+#5750000
+0#
+0.
+0A
+0L
+#6000000
+0"
+b1 ,
+b10011 /
+b1010111 0
+b10011011 1
+b11011111 2
+b10 3
+b1000110 4
+b10001010 5
+b11001110 6
+0@
+b1 J
+b10011 M
+b1010111 N
+b10011011 O
+b11011111 P
+b10 Q
+b1000110 R
+b10001010 S
+b11001110 T
+#6250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+b11111110 B
+b11011100 C
+b10111010 D
+b10011000 E
+b1110110 F
+b1010100 G
+b110010 H
+b10000 I
+1L
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
+#6500000
+#6750000
+0#
+0.
+0A
+0L
+#7000000
+b10 ,
+b1110100 /
+b1100101 0
+b1110011 1
+b1110100 2
+b1101001 3
+b1101110 4
+b1100111 5
+b100001 6
+b10 J
+b1110100 M
+b1100101 N
+b1110011 O
+b1110100 P
+b1101001 Q
+b1101110 R
+b1100111 S
+b100001 T
+#7250000
+b10011 ^
+b1010111 f
+b10011011 n
+b11011111 v
+b10 ~
+b1000110 ("
+b10001010 0"
+b11001110 8"
+1#
+1.
+1A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+1L
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+#7500000
+#7750000
+0#
+0.
+0A
+0L
+#8000000
+b11 ,
+b1101101 /
+b1101111 0
+b1110010 1
+b1100101 2
+b100000 3
+b1110100 4
+b1110011 5
+b1110100 6
+b11 J
+b1101101 M
+b1101111 N
+b1110010 O
+b1100101 P
+b100000 Q
+b1110100 R
+b1110011 S
+b1110100 T
+#8250000
+b1110100 _
+b1100101 g
+b1110011 o
+b1110100 w
+b1101001 !"
+b1101110 )"
+b1100111 1"
+b100001 9"
+1#
+1.
+1A
+1L
+#8500000
+#8750000
+0#
+0.
+0A
+0L
+#9000000
+1"
+b0 ,
+0-
+b0 /
+b0 0
+b0 1
+b0 2
+b0 3
+b0 4
+b0 5
+b0 6
+07
+08
+09
+0:
+0;
+0<
+0=
+0>
+1@
+b0 J
+0K
+b0 M
+b0 N
+b0 O
+b0 P
+b0 Q
+b0 R
+b0 S
+b0 T
+0U
+0V
+0W
+0X
+0Y
+0Z
+0[
+0\
+#9250000
+b1101101 `
+b1101111 h
+b1110010 p
+b1100101 x
+b100000 ""
+b1110100 *"
+b1110011 2"
+b1110100 :"
+1#
+1.
+1A
+1L
+#9500000
+#9750000
+0#
+0.
+0A
+0L
+#10000000
+b1 !
+b1 ?
+#10250000
+1#
+1.
+1A
+b11111110 B
+b11011100 C
+b10111010 D
+b10011000 E
+b1110110 F
+b1010100 G
+b110010 H
+b10000 I
+1L
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
+#10500000
+#10750000
+0#
+0.
+0A
+0L
+#11000000
+b10 !
+b10 ?
+#11250000
+1#
+1.
+1A
+b10011 B
+b1010111 C
+b10011011 D
+b11011111 E
+b10 F
+b1000110 G
+b10001010 H
+b11001110 I
+1L
+b10011 $
+b1010111 %
+b10011011 &
+b11011111 '
+b10 (
+b1000110 )
+b10001010 *
+b11001110 +
+#11500000
+#11750000
+0#
+0.
+0A
+0L
+#12000000
+b11 !
+b11 ?
+#12250000
+1#
+1.
+1A
+b1110100 B
+b1100101 C
+b1110011 D
+b1110100 E
+b1101001 F
+b1101110 G
+b1100111 H
+b100001 I
+1L
+b1110100 $
+b1100101 %
+b1110011 &
+b1110100 '
+b1101001 (
+b1101110 )
+b1100111 *
+b100001 +
+#12500000
+#12750000
+0#
+0.
+0A
+0L
+#13000000
+b0 !
+0"
+b0 ?
+0@
+#13250000
+1#
+1.
+1A
+b1101101 B
+b1101111 C
+b1110010 D
+b1100101 E
+b100000 F
+b1110100 G
+b1110011 H
+b1110100 I
+1L
+b1101101 $
+b1101111 %
+b1110010 &
+b1100101 '
+b100000 (
+b1110100 )
+b1110011 *
+b1110100 +
+#13500000
+#13750000
+0#
+0.
+0A
+0L
+#14000000
+#14250000
+1#
+1.
+1A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+1L
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+#14500000
+#14750000
+0#
+0.
+0A
+0L
+#15000000
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
new file mode 100644
index 0000000..3656247
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -0,0 +1,555 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 17,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:4:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                4: Const {
+                    dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0xf,
+                },
+                5: Const {
+                    dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x5,
+                },
+                6: CmpLt {
+                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                },
+                7: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX-2.rs:7:1
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:8:1
+                9: BranchIfZero {
+                    target: 11,
+                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX-2.rs:9:1
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                13: CastToSInt {
+                    dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    dest_width: 2,
+                },
+                // at: module-XXXXXXXXXX-2.rs:6:1
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                17: Return,
+            ],
+            ..
+        },
+        pc: 17,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                -2,
+                14,
+                5,
+                1,
+                15,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::mod1,
+        instantiated: Module {
+            name: mod1,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.i,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.i2,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.o,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.o2,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "mod1",
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceBundle {
+                    name: "o",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            location: TraceScalarId(1),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            location: TraceScalarId(2),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Sink,
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+                flow: Sink,
+            },
+            TraceInstance {
+                name: "child",
+                instance_io: TraceBundle {
+                    name: "child",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(8),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            location: TraceScalarId(9),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            location: TraceScalarId(10),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(11),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "mod1_child",
+                    children: [
+                        TraceModuleIO {
+                            name: "i",
+                            child: TraceUInt {
+                                location: TraceScalarId(4),
+                                name: "i",
+                                ty: UInt<4>,
+                                flow: Source,
+                            },
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceSInt {
+                                location: TraceScalarId(5),
+                                name: "o",
+                                ty: SInt<2>,
+                                flow: Sink,
+                            },
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceModuleIO {
+                            name: "i2",
+                            child: TraceSInt {
+                                location: TraceScalarId(6),
+                                name: "i2",
+                                ty: SInt<2>,
+                                flow: Source,
+                            },
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o2",
+                            child: TraceUInt {
+                                location: TraceScalarId(7),
+                                name: "o2",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 2 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd
new file mode 100644
index 0000000..0d1a6f4
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/mod1.vcd
@@ -0,0 +1,47 @@
+$timescale 1 ps $end
+$scope module mod1 $end
+$scope struct o $end
+$var wire 4 ! i $end
+$var wire 2 " o $end
+$var wire 2 # i2 $end
+$var wire 4 $ o2 $end
+$upscope $end
+$scope struct child $end
+$var wire 4 ) i $end
+$var wire 2 * o $end
+$var wire 2 + i2 $end
+$var wire 4 , o2 $end
+$upscope $end
+$scope module mod1_child $end
+$var wire 4 % i $end
+$var wire 2 & o $end
+$var wire 2 ' i2 $end
+$var wire 4 ( o2 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11 !
+b11 "
+b10 #
+b1110 $
+b11 %
+b11 &
+b10 '
+b1110 (
+b11 )
+b11 *
+b10 +
+b1110 ,
+$end
+#1000000
+b1010 !
+b10 "
+b1111 $
+b1010 %
+b10 &
+b1111 (
+b1010 )
+b10 *
+b1111 ,
+#2000000
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt
new file mode 100644
index 0000000..5472950
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt
@@ -0,0 +1,1498 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 9,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 58,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:9:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                2: NotU {
+                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                },
+                11: NotU {
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                },
+                20: NotU {
+                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                26: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                30: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                31: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                34: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                35: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                38: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                39: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                40: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
+                },
+                41: Shl {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 5,
+                },
+                42: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                },
+                43: Shl {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 4,
+                },
+                44: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                },
+                45: Shl {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 3,
+                },
+                46: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                },
+                47: Shl {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 2,
+                },
+                48: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                },
+                49: Shl {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                50: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                },
+                51: Or {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                52: Or {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                53: Or {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                54: Or {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                },
+                55: Or {
+                    dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                56: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                57: BranchIfSmallZero {
+                    target: 59,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                58: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                },
+                59: BranchIfSmallZero {
+                    target: 61,
+                    value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                },
+                61: BranchIfSmallZero {
+                    target: 63,
+                    value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                },
+                63: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                64: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                65: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                66: Return,
+            ],
+            ..
+        },
+        pc: 66,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                1,
+                0,
+                0,
+                1,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::ripple_counter,
+        instantiated: Module {
+            name: ripple_counter,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
+                    },
+                },
+            },
+        },
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
+                    },
+                },
+            },
+        },
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
+                    },
+                },
+            },
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "ripple_counter",
+        children: [
+            TraceModuleIO {
+                name: "clk",
+                child: TraceClock {
+                    location: TraceScalarId(0),
+                    name: "clk",
+                    flow: Source,
+                },
+                ty: Clock,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    location: TraceScalarId(1),
+                    name: "o",
+                    ty: UInt<6>,
+                    flow: Sink,
+                },
+                ty: UInt<6>,
+                flow: Sink,
+            },
+            TraceWire {
+                name: "bits",
+                child: TraceArray {
+                    name: "bits",
+                    elements: [
+                        TraceBool {
+                            location: TraceScalarId(2),
+                            name: "[0]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(3),
+                            name: "[1]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(4),
+                            name: "[2]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(5),
+                            name: "[3]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "[4]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(7),
+                            name: "[5]",
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<Bool, 6>,
+                    flow: Duplex,
+                },
+                ty: Array<Bool, 6>,
+            },
+            TraceReg {
+                name: "bit_reg_0",
+                child: TraceBool {
+                    location: TraceScalarId(8),
+                    name: "bit_reg_0",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_1",
+                instance_io: TraceBundle {
+                    name: "bit_reg_1",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(11),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(12),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(9),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(10),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+            TraceReg {
+                name: "bit_reg_2",
+                child: TraceBool {
+                    location: TraceScalarId(13),
+                    name: "bit_reg_2",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_3",
+                instance_io: TraceBundle {
+                    name: "bit_reg_3",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(16),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(17),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(14),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(15),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+            TraceReg {
+                name: "bit_reg_4",
+                child: TraceBool {
+                    location: TraceScalarId(18),
+                    name: "bit_reg_4",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_5",
+                instance_io: TraceBundle {
+                    name: "bit_reg_5",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(21),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(22),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(19),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(20),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: UInt<6>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(5),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(24),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(33),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(34),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(31),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(32),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(36),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(44),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(45),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(42),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(43),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(47),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(55),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(56),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(53),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(54),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 256 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(4),
+        StatePartIndex<SmallSlots>(7),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd
new file mode 100644
index 0000000..6f14a8e
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd
@@ -0,0 +1,1753 @@
+$timescale 1 ps $end
+$scope module ripple_counter $end
+$var wire 1 ! clk $end
+$var wire 6 " o $end
+$scope struct bits $end
+$var wire 1 # \[0] $end
+$var wire 1 $ \[1] $end
+$var wire 1 % \[2] $end
+$var wire 1 & \[3] $end
+$var wire 1 ' \[4] $end
+$var wire 1 ( \[5] $end
+$upscope $end
+$var reg 1 ) bit_reg_0 $end
+$scope struct bit_reg_1 $end
+$var wire 1 , clk $end
+$var wire 1 - o $end
+$upscope $end
+$scope module sw_reg $end
+$var wire 1 * clk $end
+$var wire 1 + o $end
+$upscope $end
+$var reg 1 . bit_reg_2 $end
+$scope struct bit_reg_3 $end
+$var wire 1 1 clk $end
+$var wire 1 2 o $end
+$upscope $end
+$scope module sw_reg_2 $end
+$var wire 1 / clk $end
+$var wire 1 0 o $end
+$upscope $end
+$var reg 1 3 bit_reg_4 $end
+$scope struct bit_reg_5 $end
+$var wire 1 6 clk $end
+$var wire 1 7 o $end
+$upscope $end
+$scope module sw_reg_3 $end
+$var wire 1 4 clk $end
+$var wire 1 5 o $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+b0 "
+0#
+0$
+0%
+0&
+0'
+0(
+0)
+0*
+0+
+0,
+0-
+0.
+0/
+00
+01
+02
+03
+04
+05
+06
+07
+$end
+#1000000
+1!
+1)
+b1 "
+1#
+1*
+1,
+1+
+b11 "
+1$
+1-
+1.
+b111 "
+1%
+1/
+11
+10
+b1111 "
+1&
+12
+13
+b11111 "
+1'
+14
+16
+15
+b111111 "
+1(
+17
+#2000000
+0!
+#3000000
+1!
+0)
+b111110 "
+0#
+0*
+0,
+#4000000
+0!
+#5000000
+1!
+1)
+b111111 "
+1#
+1*
+1,
+0+
+b111101 "
+0$
+0-
+#6000000
+0!
+#7000000
+1!
+0)
+b111100 "
+0#
+0*
+0,
+#8000000
+0!
+#9000000
+1!
+1)
+b111101 "
+1#
+1*
+1,
+1+
+b111111 "
+1$
+1-
+0.
+b111011 "
+0%
+0/
+01
+#10000000
+0!
+#11000000
+1!
+0)
+b111010 "
+0#
+0*
+0,
+#12000000
+0!
+#13000000
+1!
+1)
+b111011 "
+1#
+1*
+1,
+0+
+b111001 "
+0$
+0-
+#14000000
+0!
+#15000000
+1!
+0)
+b111000 "
+0#
+0*
+0,
+#16000000
+0!
+#17000000
+1!
+1)
+b111001 "
+1#
+1*
+1,
+1+
+b111011 "
+1$
+1-
+1.
+b111111 "
+1%
+1/
+11
+00
+b110111 "
+0&
+02
+#18000000
+0!
+#19000000
+1!
+0)
+b110110 "
+0#
+0*
+0,
+#20000000
+0!
+#21000000
+1!
+1)
+b110111 "
+1#
+1*
+1,
+0+
+b110101 "
+0$
+0-
+#22000000
+0!
+#23000000
+1!
+0)
+b110100 "
+0#
+0*
+0,
+#24000000
+0!
+#25000000
+1!
+1)
+b110101 "
+1#
+1*
+1,
+1+
+b110111 "
+1$
+1-
+0.
+b110011 "
+0%
+0/
+01
+#26000000
+0!
+#27000000
+1!
+0)
+b110010 "
+0#
+0*
+0,
+#28000000
+0!
+#29000000
+1!
+1)
+b110011 "
+1#
+1*
+1,
+0+
+b110001 "
+0$
+0-
+#30000000
+0!
+#31000000
+1!
+0)
+b110000 "
+0#
+0*
+0,
+#32000000
+0!
+#33000000
+1!
+1)
+b110001 "
+1#
+1*
+1,
+1+
+b110011 "
+1$
+1-
+1.
+b110111 "
+1%
+1/
+11
+10
+b111111 "
+1&
+12
+03
+b101111 "
+0'
+04
+06
+#34000000
+0!
+#35000000
+1!
+0)
+b101110 "
+0#
+0*
+0,
+#36000000
+0!
+#37000000
+1!
+1)
+b101111 "
+1#
+1*
+1,
+0+
+b101101 "
+0$
+0-
+#38000000
+0!
+#39000000
+1!
+0)
+b101100 "
+0#
+0*
+0,
+#40000000
+0!
+#41000000
+1!
+1)
+b101101 "
+1#
+1*
+1,
+1+
+b101111 "
+1$
+1-
+0.
+b101011 "
+0%
+0/
+01
+#42000000
+0!
+#43000000
+1!
+0)
+b101010 "
+0#
+0*
+0,
+#44000000
+0!
+#45000000
+1!
+1)
+b101011 "
+1#
+1*
+1,
+0+
+b101001 "
+0$
+0-
+#46000000
+0!
+#47000000
+1!
+0)
+b101000 "
+0#
+0*
+0,
+#48000000
+0!
+#49000000
+1!
+1)
+b101001 "
+1#
+1*
+1,
+1+
+b101011 "
+1$
+1-
+1.
+b101111 "
+1%
+1/
+11
+00
+b100111 "
+0&
+02
+#50000000
+0!
+#51000000
+1!
+0)
+b100110 "
+0#
+0*
+0,
+#52000000
+0!
+#53000000
+1!
+1)
+b100111 "
+1#
+1*
+1,
+0+
+b100101 "
+0$
+0-
+#54000000
+0!
+#55000000
+1!
+0)
+b100100 "
+0#
+0*
+0,
+#56000000
+0!
+#57000000
+1!
+1)
+b100101 "
+1#
+1*
+1,
+1+
+b100111 "
+1$
+1-
+0.
+b100011 "
+0%
+0/
+01
+#58000000
+0!
+#59000000
+1!
+0)
+b100010 "
+0#
+0*
+0,
+#60000000
+0!
+#61000000
+1!
+1)
+b100011 "
+1#
+1*
+1,
+0+
+b100001 "
+0$
+0-
+#62000000
+0!
+#63000000
+1!
+0)
+b100000 "
+0#
+0*
+0,
+#64000000
+0!
+#65000000
+1!
+1)
+b100001 "
+1#
+1*
+1,
+1+
+b100011 "
+1$
+1-
+1.
+b100111 "
+1%
+1/
+11
+10
+b101111 "
+1&
+12
+13
+b111111 "
+1'
+14
+16
+05
+b11111 "
+0(
+07
+#66000000
+0!
+#67000000
+1!
+0)
+b11110 "
+0#
+0*
+0,
+#68000000
+0!
+#69000000
+1!
+1)
+b11111 "
+1#
+1*
+1,
+0+
+b11101 "
+0$
+0-
+#70000000
+0!
+#71000000
+1!
+0)
+b11100 "
+0#
+0*
+0,
+#72000000
+0!
+#73000000
+1!
+1)
+b11101 "
+1#
+1*
+1,
+1+
+b11111 "
+1$
+1-
+0.
+b11011 "
+0%
+0/
+01
+#74000000
+0!
+#75000000
+1!
+0)
+b11010 "
+0#
+0*
+0,
+#76000000
+0!
+#77000000
+1!
+1)
+b11011 "
+1#
+1*
+1,
+0+
+b11001 "
+0$
+0-
+#78000000
+0!
+#79000000
+1!
+0)
+b11000 "
+0#
+0*
+0,
+#80000000
+0!
+#81000000
+1!
+1)
+b11001 "
+1#
+1*
+1,
+1+
+b11011 "
+1$
+1-
+1.
+b11111 "
+1%
+1/
+11
+00
+b10111 "
+0&
+02
+#82000000
+0!
+#83000000
+1!
+0)
+b10110 "
+0#
+0*
+0,
+#84000000
+0!
+#85000000
+1!
+1)
+b10111 "
+1#
+1*
+1,
+0+
+b10101 "
+0$
+0-
+#86000000
+0!
+#87000000
+1!
+0)
+b10100 "
+0#
+0*
+0,
+#88000000
+0!
+#89000000
+1!
+1)
+b10101 "
+1#
+1*
+1,
+1+
+b10111 "
+1$
+1-
+0.
+b10011 "
+0%
+0/
+01
+#90000000
+0!
+#91000000
+1!
+0)
+b10010 "
+0#
+0*
+0,
+#92000000
+0!
+#93000000
+1!
+1)
+b10011 "
+1#
+1*
+1,
+0+
+b10001 "
+0$
+0-
+#94000000
+0!
+#95000000
+1!
+0)
+b10000 "
+0#
+0*
+0,
+#96000000
+0!
+#97000000
+1!
+1)
+b10001 "
+1#
+1*
+1,
+1+
+b10011 "
+1$
+1-
+1.
+b10111 "
+1%
+1/
+11
+10
+b11111 "
+1&
+12
+03
+b1111 "
+0'
+04
+06
+#98000000
+0!
+#99000000
+1!
+0)
+b1110 "
+0#
+0*
+0,
+#100000000
+0!
+#101000000
+1!
+1)
+b1111 "
+1#
+1*
+1,
+0+
+b1101 "
+0$
+0-
+#102000000
+0!
+#103000000
+1!
+0)
+b1100 "
+0#
+0*
+0,
+#104000000
+0!
+#105000000
+1!
+1)
+b1101 "
+1#
+1*
+1,
+1+
+b1111 "
+1$
+1-
+0.
+b1011 "
+0%
+0/
+01
+#106000000
+0!
+#107000000
+1!
+0)
+b1010 "
+0#
+0*
+0,
+#108000000
+0!
+#109000000
+1!
+1)
+b1011 "
+1#
+1*
+1,
+0+
+b1001 "
+0$
+0-
+#110000000
+0!
+#111000000
+1!
+0)
+b1000 "
+0#
+0*
+0,
+#112000000
+0!
+#113000000
+1!
+1)
+b1001 "
+1#
+1*
+1,
+1+
+b1011 "
+1$
+1-
+1.
+b1111 "
+1%
+1/
+11
+00
+b111 "
+0&
+02
+#114000000
+0!
+#115000000
+1!
+0)
+b110 "
+0#
+0*
+0,
+#116000000
+0!
+#117000000
+1!
+1)
+b111 "
+1#
+1*
+1,
+0+
+b101 "
+0$
+0-
+#118000000
+0!
+#119000000
+1!
+0)
+b100 "
+0#
+0*
+0,
+#120000000
+0!
+#121000000
+1!
+1)
+b101 "
+1#
+1*
+1,
+1+
+b111 "
+1$
+1-
+0.
+b11 "
+0%
+0/
+01
+#122000000
+0!
+#123000000
+1!
+0)
+b10 "
+0#
+0*
+0,
+#124000000
+0!
+#125000000
+1!
+1)
+b11 "
+1#
+1*
+1,
+0+
+b1 "
+0$
+0-
+#126000000
+0!
+#127000000
+1!
+0)
+b0 "
+0#
+0*
+0,
+#128000000
+0!
+#129000000
+1!
+1)
+b1 "
+1#
+1*
+1,
+1+
+b11 "
+1$
+1-
+1.
+b111 "
+1%
+1/
+11
+10
+b1111 "
+1&
+12
+13
+b11111 "
+1'
+14
+16
+15
+b111111 "
+1(
+17
+#130000000
+0!
+#131000000
+1!
+0)
+b111110 "
+0#
+0*
+0,
+#132000000
+0!
+#133000000
+1!
+1)
+b111111 "
+1#
+1*
+1,
+0+
+b111101 "
+0$
+0-
+#134000000
+0!
+#135000000
+1!
+0)
+b111100 "
+0#
+0*
+0,
+#136000000
+0!
+#137000000
+1!
+1)
+b111101 "
+1#
+1*
+1,
+1+
+b111111 "
+1$
+1-
+0.
+b111011 "
+0%
+0/
+01
+#138000000
+0!
+#139000000
+1!
+0)
+b111010 "
+0#
+0*
+0,
+#140000000
+0!
+#141000000
+1!
+1)
+b111011 "
+1#
+1*
+1,
+0+
+b111001 "
+0$
+0-
+#142000000
+0!
+#143000000
+1!
+0)
+b111000 "
+0#
+0*
+0,
+#144000000
+0!
+#145000000
+1!
+1)
+b111001 "
+1#
+1*
+1,
+1+
+b111011 "
+1$
+1-
+1.
+b111111 "
+1%
+1/
+11
+00
+b110111 "
+0&
+02
+#146000000
+0!
+#147000000
+1!
+0)
+b110110 "
+0#
+0*
+0,
+#148000000
+0!
+#149000000
+1!
+1)
+b110111 "
+1#
+1*
+1,
+0+
+b110101 "
+0$
+0-
+#150000000
+0!
+#151000000
+1!
+0)
+b110100 "
+0#
+0*
+0,
+#152000000
+0!
+#153000000
+1!
+1)
+b110101 "
+1#
+1*
+1,
+1+
+b110111 "
+1$
+1-
+0.
+b110011 "
+0%
+0/
+01
+#154000000
+0!
+#155000000
+1!
+0)
+b110010 "
+0#
+0*
+0,
+#156000000
+0!
+#157000000
+1!
+1)
+b110011 "
+1#
+1*
+1,
+0+
+b110001 "
+0$
+0-
+#158000000
+0!
+#159000000
+1!
+0)
+b110000 "
+0#
+0*
+0,
+#160000000
+0!
+#161000000
+1!
+1)
+b110001 "
+1#
+1*
+1,
+1+
+b110011 "
+1$
+1-
+1.
+b110111 "
+1%
+1/
+11
+10
+b111111 "
+1&
+12
+03
+b101111 "
+0'
+04
+06
+#162000000
+0!
+#163000000
+1!
+0)
+b101110 "
+0#
+0*
+0,
+#164000000
+0!
+#165000000
+1!
+1)
+b101111 "
+1#
+1*
+1,
+0+
+b101101 "
+0$
+0-
+#166000000
+0!
+#167000000
+1!
+0)
+b101100 "
+0#
+0*
+0,
+#168000000
+0!
+#169000000
+1!
+1)
+b101101 "
+1#
+1*
+1,
+1+
+b101111 "
+1$
+1-
+0.
+b101011 "
+0%
+0/
+01
+#170000000
+0!
+#171000000
+1!
+0)
+b101010 "
+0#
+0*
+0,
+#172000000
+0!
+#173000000
+1!
+1)
+b101011 "
+1#
+1*
+1,
+0+
+b101001 "
+0$
+0-
+#174000000
+0!
+#175000000
+1!
+0)
+b101000 "
+0#
+0*
+0,
+#176000000
+0!
+#177000000
+1!
+1)
+b101001 "
+1#
+1*
+1,
+1+
+b101011 "
+1$
+1-
+1.
+b101111 "
+1%
+1/
+11
+00
+b100111 "
+0&
+02
+#178000000
+0!
+#179000000
+1!
+0)
+b100110 "
+0#
+0*
+0,
+#180000000
+0!
+#181000000
+1!
+1)
+b100111 "
+1#
+1*
+1,
+0+
+b100101 "
+0$
+0-
+#182000000
+0!
+#183000000
+1!
+0)
+b100100 "
+0#
+0*
+0,
+#184000000
+0!
+#185000000
+1!
+1)
+b100101 "
+1#
+1*
+1,
+1+
+b100111 "
+1$
+1-
+0.
+b100011 "
+0%
+0/
+01
+#186000000
+0!
+#187000000
+1!
+0)
+b100010 "
+0#
+0*
+0,
+#188000000
+0!
+#189000000
+1!
+1)
+b100011 "
+1#
+1*
+1,
+0+
+b100001 "
+0$
+0-
+#190000000
+0!
+#191000000
+1!
+0)
+b100000 "
+0#
+0*
+0,
+#192000000
+0!
+#193000000
+1!
+1)
+b100001 "
+1#
+1*
+1,
+1+
+b100011 "
+1$
+1-
+1.
+b100111 "
+1%
+1/
+11
+10
+b101111 "
+1&
+12
+13
+b111111 "
+1'
+14
+16
+05
+b11111 "
+0(
+07
+#194000000
+0!
+#195000000
+1!
+0)
+b11110 "
+0#
+0*
+0,
+#196000000
+0!
+#197000000
+1!
+1)
+b11111 "
+1#
+1*
+1,
+0+
+b11101 "
+0$
+0-
+#198000000
+0!
+#199000000
+1!
+0)
+b11100 "
+0#
+0*
+0,
+#200000000
+0!
+#201000000
+1!
+1)
+b11101 "
+1#
+1*
+1,
+1+
+b11111 "
+1$
+1-
+0.
+b11011 "
+0%
+0/
+01
+#202000000
+0!
+#203000000
+1!
+0)
+b11010 "
+0#
+0*
+0,
+#204000000
+0!
+#205000000
+1!
+1)
+b11011 "
+1#
+1*
+1,
+0+
+b11001 "
+0$
+0-
+#206000000
+0!
+#207000000
+1!
+0)
+b11000 "
+0#
+0*
+0,
+#208000000
+0!
+#209000000
+1!
+1)
+b11001 "
+1#
+1*
+1,
+1+
+b11011 "
+1$
+1-
+1.
+b11111 "
+1%
+1/
+11
+00
+b10111 "
+0&
+02
+#210000000
+0!
+#211000000
+1!
+0)
+b10110 "
+0#
+0*
+0,
+#212000000
+0!
+#213000000
+1!
+1)
+b10111 "
+1#
+1*
+1,
+0+
+b10101 "
+0$
+0-
+#214000000
+0!
+#215000000
+1!
+0)
+b10100 "
+0#
+0*
+0,
+#216000000
+0!
+#217000000
+1!
+1)
+b10101 "
+1#
+1*
+1,
+1+
+b10111 "
+1$
+1-
+0.
+b10011 "
+0%
+0/
+01
+#218000000
+0!
+#219000000
+1!
+0)
+b10010 "
+0#
+0*
+0,
+#220000000
+0!
+#221000000
+1!
+1)
+b10011 "
+1#
+1*
+1,
+0+
+b10001 "
+0$
+0-
+#222000000
+0!
+#223000000
+1!
+0)
+b10000 "
+0#
+0*
+0,
+#224000000
+0!
+#225000000
+1!
+1)
+b10001 "
+1#
+1*
+1,
+1+
+b10011 "
+1$
+1-
+1.
+b10111 "
+1%
+1/
+11
+10
+b11111 "
+1&
+12
+03
+b1111 "
+0'
+04
+06
+#226000000
+0!
+#227000000
+1!
+0)
+b1110 "
+0#
+0*
+0,
+#228000000
+0!
+#229000000
+1!
+1)
+b1111 "
+1#
+1*
+1,
+0+
+b1101 "
+0$
+0-
+#230000000
+0!
+#231000000
+1!
+0)
+b1100 "
+0#
+0*
+0,
+#232000000
+0!
+#233000000
+1!
+1)
+b1101 "
+1#
+1*
+1,
+1+
+b1111 "
+1$
+1-
+0.
+b1011 "
+0%
+0/
+01
+#234000000
+0!
+#235000000
+1!
+0)
+b1010 "
+0#
+0*
+0,
+#236000000
+0!
+#237000000
+1!
+1)
+b1011 "
+1#
+1*
+1,
+0+
+b1001 "
+0$
+0-
+#238000000
+0!
+#239000000
+1!
+0)
+b1000 "
+0#
+0*
+0,
+#240000000
+0!
+#241000000
+1!
+1)
+b1001 "
+1#
+1*
+1,
+1+
+b1011 "
+1$
+1-
+1.
+b1111 "
+1%
+1/
+11
+00
+b111 "
+0&
+02
+#242000000
+0!
+#243000000
+1!
+0)
+b110 "
+0#
+0*
+0,
+#244000000
+0!
+#245000000
+1!
+1)
+b111 "
+1#
+1*
+1,
+0+
+b101 "
+0$
+0-
+#246000000
+0!
+#247000000
+1!
+0)
+b100 "
+0#
+0*
+0,
+#248000000
+0!
+#249000000
+1!
+1)
+b101 "
+1#
+1*
+1,
+1+
+b111 "
+1$
+1-
+0.
+b11 "
+0%
+0/
+01
+#250000000
+0!
+#251000000
+1!
+0)
+b10 "
+0#
+0*
+0,
+#252000000
+0!
+#253000000
+1!
+1)
+b11 "
+1#
+1*
+1,
+0+
+b1 "
+0$
+0-
+#254000000
+0!
+#255000000
+1!
+0)
+b0 "
+0#
+0*
+0,
+#256000000
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
new file mode 100644
index 0000000..901cf70
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -0,0 +1,508 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 13,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:13:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                5: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                6: Const {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                7: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
+                },
+                8: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                9: BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                10: BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                },
+                12: Branch {
+                    target: 14,
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                14: BranchIfSmallZero {
+                    target: 19,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                15: BranchIfSmallNonZero {
+                    target: 18,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                },
+                17: Branch {
+                    target: 19,
+                },
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                19: BranchIfSmallZero {
+                    target: 24,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                20: BranchIfSmallNonZero {
+                    target: 23,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                },
+                22: Branch {
+                    target: 24,
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                24: BranchIfSmallZero {
+                    target: 29,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                25: BranchIfSmallNonZero {
+                    target: 28,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                26: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                },
+                27: Branch {
+                    target: 29,
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                29: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                30: Return,
+            ],
+            ..
+        },
+        pc: 30,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::shift_register,
+        instantiated: Module {
+            name: shift_register,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.d,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.q,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.d,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.q,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "shift_register",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            location: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "d",
+                child: TraceBool {
+                    location: TraceScalarId(2),
+                    name: "d",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "q",
+                child: TraceBool {
+                    location: TraceScalarId(3),
+                    name: "q",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "reg0",
+                child: TraceBool {
+                    location: TraceScalarId(4),
+                    name: "reg0",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg1",
+                child: TraceBool {
+                    location: TraceScalarId(5),
+                    name: "reg1",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg2",
+                child: TraceBool {
+                    location: TraceScalarId(6),
+                    name: "reg2",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg3",
+                child: TraceBool {
+                    location: TraceScalarId(7),
+                    name: "reg3",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd
new file mode 100644
index 0000000..0b5f429
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/shift_register.vcd
@@ -0,0 +1,193 @@
+$timescale 1 ps $end
+$scope module shift_register $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 1 # d $end
+$var wire 1 $ q $end
+$var reg 1 % reg0 $end
+$var reg 1 & reg1 $end
+$var reg 1 ' reg2 $end
+$var reg 1 ( reg3 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+0#
+0$
+0%
+0&
+0'
+0(
+$end
+#1000000
+1!
+#1100000
+0"
+#2000000
+0!
+#3000000
+1!
+#4000000
+0!
+1#
+#5000000
+1!
+1%
+#6000000
+0!
+#7000000
+1!
+1&
+#8000000
+0!
+0#
+#9000000
+1!
+0%
+1'
+#10000000
+0!
+#11000000
+1!
+0&
+1(
+1$
+#12000000
+0!
+1#
+#13000000
+1!
+1%
+0'
+#14000000
+0!
+0#
+#15000000
+1!
+0%
+1&
+0(
+0$
+#16000000
+0!
+1#
+#17000000
+1!
+1%
+0&
+1'
+#18000000
+0!
+#19000000
+1!
+1&
+0'
+1(
+1$
+#20000000
+0!
+#21000000
+1!
+1'
+0(
+0$
+#22000000
+0!
+#23000000
+1!
+1(
+1$
+#24000000
+0!
+0#
+#25000000
+1!
+0%
+#26000000
+0!
+#27000000
+1!
+0&
+#28000000
+0!
+#29000000
+1!
+0'
+#30000000
+0!
+#31000000
+1!
+0(
+0$
+#32000000
+0!
+#33000000
+1!
+#34000000
+0!
+#35000000
+1!
+#36000000
+0!
+#37000000
+1!
+#38000000
+0!
+#39000000
+1!
+#40000000
+0!
+#41000000
+1!
+#42000000
+0!
+#43000000
+1!
+#44000000
+0!
+#45000000
+1!
+#46000000
+0!
+#47000000
+1!
+#48000000
+0!
+#49000000
+1!
+#50000000
+0!
+#51000000
+1!
+#52000000
+0!
+#53000000
+1!
+#54000000
+0!
+#55000000
+1!
+#56000000
+0!
+#57000000
+1!
+#58000000
+0!
+#59000000
+1!
+#60000000
+0!
+#61000000
+1!
+#62000000
+0!
+#63000000
+1!
+#64000000
+0!
+#65000000
+1!
+#66000000
diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.rs b/crates/fayalite/tests/ui/simvalue_is_not_internable.rs
new file mode 100644
index 0000000..d40990f
--- /dev/null
+++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.rs
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+//! check that SimValue can't be interned, since equality may ignore types
+
+use fayalite::{
+    intern::{Intern, Interned},
+    sim::value::SimValue,
+};
+
+fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+    Intern::intern_sized(v)
+}
+
+fn main() {}
diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
new file mode 100644
index 0000000..eb8877b
--- /dev/null
+++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
@@ -0,0 +1,178 @@
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:11:26
+   |
+11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+   |                          ^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:11:26
+   |
+11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+   |                          ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: the trait bound `SimValue<()>: Intern` is not satisfied
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ the trait `Hash` is not implemented for `SimValue<()>`, which is required by `SimValue<()>: Intern`
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: the following other types implement trait `Intern`:
+             BitSlice
+             [T]
+             str
+   = note: required for `SimValue<()>` to implement `Intern`
+
+error[E0277]: the trait bound `SimValue<()>: Intern` is not satisfied
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ the trait `std::cmp::Eq` is not implemented for `SimValue<()>`, which is required by `SimValue<()>: Intern`
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: the following other types implement trait `Intern`:
+             BitSlice
+             [T]
+             str
+   = note: required for `SimValue<()>` to implement `Intern`
+
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `intern_sized`
+  --> src/intern.rs
+   |
+   | pub trait Intern: Any + Send + Sync {
+   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   |     fn intern(&self) -> Interned<Self>;
+   |     fn intern_sized(self) -> Interned<Self>
+   |        ------------ required by a bound in this associated function
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `intern_sized`
+  --> src/intern.rs
+   |
+   | pub trait Intern: Any + Send + Sync {
+   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   |     fn intern(&self) -> Interned<Self>;
+   |     fn intern_sized(self) -> Interned<Self>
+   |        ------------ required by a bound in this associated function
+
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:5
+   |
+12 |     Intern::intern_sized(v)
+   |     ^^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:5
+   |
+12 |     Intern::intern_sized(v)
+   |     ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 182efd9..ff2050a 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -49,7 +49,8 @@
                 "AsyncReset": "Visible",
                 "SyncReset": "Visible",
                 "Reset": "Visible",
-                "Clock": "Visible"
+                "Clock": "Visible",
+                "PhantomConst": "Visible"
             }
         },
         "Bundle": {
@@ -159,7 +160,8 @@
             "data": {
                 "$kind": "Struct",
                 "verilog_name": "Visible",
-                "parameters": "Visible"
+                "parameters": "Visible",
+                "simulation": "Visible"
             }
         },
         "ExternModuleParameter": {
@@ -1047,9 +1049,9 @@
                 "clock_domain()": "Visible",
                 "init()": "Visible"
             },
-            "generics": "<T: Type>",
-            "fold_where": "T: Fold<State>",
-            "visit_where": "T: Visit<State>"
+            "generics": "<T: Type, R: ResetType>",
+            "fold_where": "T: Fold<State>, R: Fold<State>",
+            "visit_where": "T: Visit<State>, R: Visit<State>"
         },
         "Wire": {
             "data": {
@@ -1078,6 +1080,8 @@
                 "$kind": "Enum",
                 "Wire": "Visible",
                 "Reg": "Visible",
+                "RegSync": "Visible",
+                "RegAsync": "Visible",
                 "Instance": "Visible"
             }
         },
@@ -1136,7 +1140,10 @@
                 "$kind": "Struct",
                 "annotations": "Visible",
                 "reg": "Visible"
-            }
+            },
+            "generics": "<R: ResetType>",
+            "fold_where": "R: Fold<State>",
+            "visit_where": "R: Visit<State>"
         },
         "StmtWire": {
             "data": {
@@ -1219,6 +1226,8 @@
                 "ModuleIO": "Visible",
                 "MemPort": "Visible",
                 "Reg": "Visible",
+                "RegSync": "Visible",
+                "RegAsync": "Visible",
                 "Wire": "Visible",
                 "Instance": "Visible"
             }
@@ -1255,6 +1264,17 @@
                 "ArrayElement": "Visible",
                 "DynArrayElement": "Visible"
             }
+        },
+        "PhantomConst": {
+            "data": {
+                "$kind": "Opaque"
+            },
+            "generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>"
+        },
+        "ExternModuleSimulation": {
+            "data": {
+                "$kind": "Opaque"
+            }
         }
     }
 }
\ No newline at end of file
diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh
index 8104f9c..3651931 100755
--- a/scripts/check-copyright.sh
+++ b/scripts/check-copyright.sh
@@ -46,7 +46,7 @@ function main()
         */LICENSE.md|*/Notices.txt)
             # copyright file
             ;;
-        /crates/fayalite/tests/ui/*.stderr)
+        /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt)
             # file that can't contain copyright header
             ;;
         /.forgejo/workflows/*.yml|*/.gitignore|*.toml)