forked from libre-chip/fayalite
Simulation::settle_step() works for simple modules
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SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 1221 additions and 166 deletions
524
crates/fayalite/tests/sim.rs
Normal file
524
crates/fayalite/tests/sim.rs
Normal file
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@ -0,0 +1,524 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use fayalite::{prelude::*, sim::Simulation};
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#[hdl_module(outline_generated)]
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pub fn connect_const() {
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#[hdl]
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let o: UInt<8> = m.output();
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connect(o, 5u8);
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}
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#[test]
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fn test_connect_const() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(connect_const());
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sim.settle_step();
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug
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!= r#"Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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value: 5,
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},
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// at: module-XXXXXXXXXX.rs:3:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 2,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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5,
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5,
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],
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},
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},
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base_module: CompiledModule {
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module_io: [
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CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<8>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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],
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},
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base_module_io_ty: connect_const {
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o: UInt<8>,
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},
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}"# {
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panic!();
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}
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}
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#[hdl_module(outline_generated)]
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pub fn mod1_child() {
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#[hdl]
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let i: UInt<4> = m.input();
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#[hdl]
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let o: SInt<2> = m.output();
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#[hdl]
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let i2: SInt<2> = m.input();
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#[hdl]
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let o2: UInt<4> = m.output();
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connect(o, i.cast_to_static());
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connect(o2, i2.cast_to_static());
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#[hdl]
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if i.cmp_gt(5_hdl_u4) {
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connect(o2, 0xF_hdl_u4);
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}
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}
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#[hdl_module(outline_generated)]
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pub fn mod1() {
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#[hdl]
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let child = instance(mod1_child());
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#[hdl]
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let o: mod1_child = m.output(Expr::ty(child));
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connect(o, child);
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}
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#[test]
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fn test_mod1() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(mod1());
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sim.settle_step();
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug
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!= r#"Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 17,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
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value: 15,
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},
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Const {
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dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
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value: 5,
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},
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CmpLt {
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dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
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rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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},
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CastToUInt {
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dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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dest_width: 4,
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},
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// at: module-XXXXXXXXXX-2.rs:7:1
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Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:8:1
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BranchIfZero {
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target: 11,
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value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX-2.rs:9:1
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Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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CastToSInt {
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dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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dest_width: 2,
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},
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// at: module-XXXXXXXXXX-2.rs:6:1
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Copy {
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dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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Copy {
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dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 17,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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5,
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0,
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15,
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],
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},
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},
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base_module: CompiledModule {
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module_io: [
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CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bundle {
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#[hdl(flip)] /* offset = 0 */
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i: UInt<4>,
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/* offset = 4 */
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o: SInt<2>,
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#[hdl(flip)] /* offset = 6 */
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i2: SInt<2>,
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/* offset = 8 */
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o2: UInt<4>,
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},
|
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layout: TypeLayout {
|
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small_slots: StatePartAllocationLayout<SmallSlots> {
|
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len: 0,
|
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debug_data: [],
|
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..
|
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},
|
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big_slots: StatePartAllocationLayout<BigSlots> {
|
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len: 4,
|
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debug_data: [
|
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SlotDebugData {
|
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
|
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ty: UInt<4>,
|
||||
},
|
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SlotDebugData {
|
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
|
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ty: SInt<2>,
|
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},
|
||||
SlotDebugData {
|
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
|
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ty: SInt<2>,
|
||||
},
|
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SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
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},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
],
|
||||
},
|
||||
base_module_io_ty: mod1 {
|
||||
o: mod1_child {
|
||||
i: UInt<4>,
|
||||
o: SInt<2>,
|
||||
i2: SInt<2>,
|
||||
o2: UInt<4>,
|
||||
},
|
||||
},
|
||||
}"# {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue