forked from libre-chip/fayalite
sim: fix "label address not set" bug when the last Assignment is conditional
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parent
404a2ee043
commit
d4ea826051
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
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@ -4773,6 +4773,9 @@ impl Compiler {
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}
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}
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self.insns.extend(insns.iter().copied(), *source_location);
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self.insns.extend(insns.iter().copied(), *source_location);
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}
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}
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for CondStackEntry { cond: _, end_label } in cond_stack {
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self.insns.define_label_at_next_insn(end_label);
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}
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}
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}
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fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
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fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
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mem::take(&mut self.clock_triggers)
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mem::take(&mut self.clock_triggers)
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@ -1407,3 +1407,39 @@ fn test_array_rw() {
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panic!();
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panic!();
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}
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}
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}
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}
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#[hdl_module(outline_generated)]
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pub fn conditional_assignment_last() {
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#[hdl]
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let i: Bool = m.input();
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#[hdl]
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let w = wire();
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connect(w, true);
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#[hdl]
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if i {
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connect(w, false);
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}
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}
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#[test]
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fn test_conditional_assignment_last() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(conditional_assignment_last());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write(sim.io().i, false);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().i, true);
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sim.advance_time(SimDuration::from_micros(1));
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/conditional_assignment_last.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/conditional_assignment_last.txt") {
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panic!();
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}
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}
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@ -0,0 +1,189 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Const {
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dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
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value: 0x0,
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},
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1: Const {
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dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
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value: 0x1,
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},
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// at: module-XXXXXXXXXX.rs:4:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
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src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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3: BranchIfZero {
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target: 5,
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value: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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4: Copy {
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dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
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src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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5: Return,
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],
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..
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},
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pc: 5,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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1,
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0,
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1,
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0,
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],
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},
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},
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io: Instance {
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name: <simulator>::conditional_assignment_last,
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instantiated: Module {
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name: conditional_assignment_last,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::conditional_assignment_last,
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instantiated: Module {
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name: conditional_assignment_last,
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..
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},
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}.i: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bool,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
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ty: Bool,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "conditional_assignment_last",
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children: [
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TraceModuleIO {
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name: "i",
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child: TraceBool {
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location: TraceScalarId(0),
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name: "i",
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flow: Source,
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},
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ty: Bool,
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flow: Source,
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},
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TraceWire {
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name: "w",
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child: TraceBool {
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location: TraceScalarId(1),
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name: "w",
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flow: Duplex,
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},
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ty: Bool,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x1,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x0,
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last_state: 0x1,
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},
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],
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trace_memories: {},
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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instant: 2 μs,
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clocks_triggered: [],
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..
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}
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@ -0,0 +1,14 @@
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$timescale 1 ps $end
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$scope module conditional_assignment_last $end
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$var wire 1 ! i $end
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$var wire 1 " w $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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0!
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1"
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$end
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#1000000
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1!
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0"
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#2000000
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