cesar/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

sim: fix "label address not set" bug when the last Assignment is conditional

Browse source
This commit is contained in:
Jacob Lifshay 2025-01-15 19:04:40 -08:00
parent 404a2ee043
commit d4ea826051
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 242 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

36
crates/fayalite/tests/sim.rs
View file

@ -1407,3 +1407,39 @@ fn test_array_rw() {
panic!();
}
}
#[hdl_module(outline_generated)]
pub fn conditional_assignment_last() {
#[hdl]
let i: Bool = m.input();
#[hdl]
let w = wire();
connect(w, true);
#[hdl]
if i {
connect(w, false);
}
}
#[test]
fn test_conditional_assignment_last() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(conditional_assignment_last());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write(sim.io().i, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().i, true);
sim.advance_time(SimDuration::from_micros(1));
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/conditional_assignment_last.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/conditional_assignment_last.txt") {
panic!();
}
}