cesar/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

add cli option to set verilog dialect

Browse source
This commit is contained in:
Jacob Lifshay 2024-07-24 23:13:56 -07:00
parent f582013c1b
commit c94a437686
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 41 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

47
crates/fayalite/src/cli.rs
View file

@ -6,7 +6,7 @@ use crate::{
}; };
use clap::{ use clap::{
builder::{OsStringValueParser, TypedValueParser}, builder::{OsStringValueParser, TypedValueParser},
Args, Parser, Subcommand, ValueHint, Args, Parser, Subcommand, ValueEnum, ValueHint,
}; };
use eyre::{eyre, Report}; use eyre::{eyre, Report};
use std::{error, ffi::OsString, fmt, io, path::PathBuf, process}; use std::{error, ffi::OsString, fmt, io, path::PathBuf, process};
@ -114,6 +114,35 @@ where
} }
} }
/// based on https://circt.llvm.org/docs/VerilogGeneration/#recommended-loweringoptions-by-target
#[derive(ValueEnum, Copy, Clone, Debug, PartialEq, Eq, Hash)]
#[non_exhaustive]
pub enum VerilogDialect {
Questa,
Spyglass,
Verilator,
Vivado,
Yosys,
}
impl VerilogDialect {
pub fn firtool_extra_args(self) -> &'static [&'static str] {
match self {
VerilogDialect::Questa => &["--lowering-options=emitWireInPorts"],
VerilogDialect::Spyglass => {
&["--lowering-options=explicitBitcast,disallowExpressionInliningInPorts"]
}
VerilogDialect::Verilator => &[
"--lowering-options=locationInfoStyle=wrapInAtSquareBracket,disallowLocalVariables",
],
VerilogDialect::Vivado => &["--lowering-options=mitigateVivadoArrayIndexConstPropBug"],
VerilogDialect::Yosys => {
&["--lowering-options=disallowLocalVariables,disallowPackedArrays"]
}
}
}
}
#[derive(Args, Debug)] #[derive(Args, Debug)]
#[non_exhaustive] #[non_exhaustive]
pub struct VerilogArgs { pub struct VerilogArgs {
@ -129,6 +158,9 @@ pub struct VerilogArgs {
pub firtool: PathBuf, pub firtool: PathBuf,
#[arg(long)] #[arg(long)]
pub firtool_extra_args: Vec<OsString>, pub firtool_extra_args: Vec<OsString>,
/// adapt the generated Verilog for a particular toolchain
#[arg(long)]
pub verilog_dialect: Option<VerilogDialect>,
} }
#[derive(Debug)] #[derive(Debug)]
@ -151,11 +183,14 @@ impl VerilogArgs {
firrtl: firrtl_output, firrtl: firrtl_output,
}; };
let mut cmd = process::Command::new(&self.firtool); let mut cmd = process::Command::new(&self.firtool);
cmd.arg(output.firrtl.firrtl_file(&self.firrtl)) cmd.arg(output.firrtl.firrtl_file(&self.firrtl));
.arg("-o") cmd.arg("-o");
.arg(output.verilog_file(self)) cmd.arg(output.verilog_file(self));
.args(&self.firtool_extra_args) if let Some(dialect) = self.verilog_dialect {
.current_dir(&self.firrtl.base.output); cmd.args(dialect.firtool_extra_args());
}
cmd.args(&self.firtool_extra_args);
cmd.current_dir(&self.firrtl.base.output);
let status = cmd.status()?; let status = cmd.status()?;
if status.success() { if status.success() {
Ok(output) Ok(output)