cesar/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

tests/sim: add test for memory rw port

Browse source
This commit is contained in:
Jacob Lifshay 2024-12-12 20:50:41 -08:00
parent 903ca1bf30
commit c756aeec70
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 2330 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

273
crates/fayalite/tests/sim.rs
View file

@ -694,4 +694,277 @@ fn test_memories() {
}
}
#[hdl_module(outline_generated)]
pub fn memories2() {
#[hdl]
let rw: fayalite::memory::ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
#[hdl]
let mut mem = memory_with_init([HdlSome(true); 5]);
mem.read_latency(1);
mem.write_latency(NonZeroUsize::new(1).unwrap());
mem.read_under_write(ReadUnderWrite::New);
let rw_port = mem.new_rw_port();
connect_any(rw_port.addr, rw.addr);
connect(rw_port.en, rw.en);
connect(rw_port.clk, rw.clk);
connect_any(rw.rdata, rw_port.rdata.cast_to_bits());
connect(rw_port.wmode, rw.wmode);
connect(rw_port.wdata, HdlNone());
#[hdl]
if rw.wdata[0] {
connect(rw_port.wdata, HdlSome(rw.wdata[1]));
}
connect(rw_port.wmask, rw.wmask);
}
#[hdl]
#[test]
fn test_memories2() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(memories2());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write_clock(sim.io().rw.clk, false);
#[derive(Debug, PartialEq, Eq)]
struct IO {
addr: u8,
en: bool,
rdata: u8,
wmode: bool,
wdata: u8,
wmask: bool,
}
let io_cycles = [
IO {
addr: 0,
en: false,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: true,
rdata: 0x3,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: false,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: true,
rdata: 0,
wmode: true,
wdata: 0,
wmask: true,
},
IO {
addr: 0,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: true,
rdata: 0,
wmode: true,
wdata: 3,
wmask: false,
},
IO {
addr: 1,
en: true,
rdata: 0,
wmode: true,
wdata: 1,
wmask: true,
},
IO {
addr: 2,
en: true,
rdata: 0,
wmode: true,
wdata: 2,
wmask: true,
},
IO {
addr: 3,
en: true,
rdata: 0,
wmode: true,
wdata: 3,
wmask: true,
},
IO {
addr: 4,
en: true,
rdata: 0,
wmode: true,
wdata: 2,
wmask: true,
},
IO {
addr: 5,
en: true,
rdata: 0,
wmode: true,
wdata: 1,
wmask: true,
},
IO {
addr: 6,
en: true,
rdata: 0,
wmode: true,
wdata: 1,
wmask: true,
},
IO {
addr: 7,
en: true,
rdata: 0,
wmode: true,
wdata: 1,
wmask: true,
},
IO {
addr: 7,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 6,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 5,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 4,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 3,
en: true,
rdata: 3,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 2,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: true,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 1,
en: true,
rdata: 1,
wmode: false,
wdata: 0,
wmask: false,
},
IO {
addr: 0,
en: false,
rdata: 0,
wmode: false,
wdata: 0,
wmask: false,
},
];
for (
cycle,
expected @ IO {
addr,
en,
rdata: _,
wmode,
wdata,
wmask,
},
) in io_cycles.into_iter().enumerate()
{
sim.write_bool_or_int(sim.io().rw.addr, addr.cast_to_static());
sim.write_bool(sim.io().rw.en, en);
sim.write_bool(sim.io().rw.wmode, wmode);
sim.write_bool_or_int(sim.io().rw.wdata, wdata.cast_to_static());
sim.write_bool(sim.io().rw.wmask, wmask);
sim.advance_time(SimDuration::from_nanos(250));
sim.write_clock(sim.io().rw.clk, true);
sim.advance_time(SimDuration::from_nanos(250));
let io = IO {
addr,
en,
rdata: sim
.read_bool_or_int(sim.io().rw.rdata)
.to_bigint()
.try_into()
.expect("known to be in range"),
wmode,
wdata,
wmask,
};
assert_eq!(
expected,
io,
"cycle: {cycle}\nvcd:\n{}",
String::from_utf8(writer.take()).unwrap(),
);
sim.advance_time(SimDuration::from_nanos(250));
sim.write_clock(sim.io().rw.clk, false);
sim.advance_time(SimDuration::from_nanos(250));
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/memories2.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/memories2.txt") {
panic!();
}
}
// TODO: add more tests for memories