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WIP adding VCD output

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This commit is contained in:
Jacob Lifshay 2024-11-18 03:04:10 -08:00
parent 09aa9fbc78
commit c4b5d00419
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
6 changed files with 801 additions and 14 deletions
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22
crates/fayalite/tests/sim.rs
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@ -1,6 +1,11 @@
// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
use fayalite::{int::UIntValue, prelude::*, sim::Simulation};
use fayalite::{
int::UIntValue,
prelude::*,
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
util::RcWriter,
};
#[hdl_module(outline_generated)]
pub fn connect_const() {
@ -177,14 +182,25 @@ pub fn mod1() {
connect(o, child);
}
#[cfg(todo)]
#[hdl]
#[test]
fn test_mod1() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(mod1());
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write_bool_or_int(sim.io().o.i, 0x3_hdl_u4);
sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
sim.settle_step();
sim.advance_time(SimDuration::from_micros(1));
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
sim.advance_time(SimDuration::from_micros(1));
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
todo!("generated vcd is incorrect");
if vcd != r#""# {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug