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fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s

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Jacob Lifshay 2024-12-29 00:48:15 -08:00
parent b63676d0ca
commit c16726cee6
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 37 additions and 22 deletions
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15
crates/fayalite/tests/module.rs
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@ -4288,7 +4288,8 @@ circuit check_deduce_resets:
};
}
#[hdl_module(outline_generated)]
// intentionally not outline_generated to ensure we get correct macro hygiene
#[hdl_module]
pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
#[cfg(cfg_false_for_tests)] a: A,
#[cfg(cfg_true_for_tests)] b: B,
@ -4335,12 +4336,12 @@ fn test_cfgs() {
"/test/check_cfgs.fir": r"FIRRTL version 3.2.0
circuit check_cfgs:
type Ty0 = {b: UInt<8>}
module check_cfgs: @[module-XXXXXXXXXX.rs 1:1]
input i_b: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
output o_b: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
wire w: Ty0 @[module-XXXXXXXXXX.rs 3:1]
connect o_b, w.b @[module-XXXXXXXXXX.rs 5:1]
connect w.b, i_b @[module-XXXXXXXXXX.rs 6:1]
module check_cfgs: @[the_test_file.rs 9962:1]
input i_b: UInt<8> @[the_test_file.rs 9979:20]
output o_b: UInt<8> @[the_test_file.rs 9992:24]
wire w: Ty0 @[the_test_file.rs 9981:25]
connect o_b, w.b @[the_test_file.rs 9993:9]
connect w.b, i_b @[the_test_file.rs 9994:9]
",
};
}