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simplify setting an extern module simulation

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This commit is contained in:
Jacob Lifshay 2025-03-21 17:08:29 -07:00
parent d1bd176b28
commit ab9ff4f2db
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
5 changed files with 111 additions and 163 deletions
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43
crates/fayalite/tests/sim.rs
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@ -5,14 +5,11 @@ use fayalite::{
int::UIntValue,
prelude::*,
reset::ResetType,
sim::{
time::SimDuration, vcd::VcdWriterDecls, ExternModuleSimGenerator,
ExternModuleSimulationState, Simulation, ToSimValue,
},
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
ty::StaticType,
util::RcWriter,
};
use std::{future::IntoFuture, num::NonZeroUsize};
use std::num::NonZeroUsize;
#[hdl_module(outline_generated)]
pub fn connect_const() {
@ -1453,33 +1450,17 @@ pub fn extern_module() {
let i: Bool = m.input();
#[hdl]
let o: Bool = m.output();
#[derive(Clone, Eq, PartialEq, Hash, Debug)]
struct Sim {
i: Expr<Bool>,
o: Expr<Bool>,
}
impl ExternModuleSimGenerator for Sim {
type IOType = extern_module;
fn run<'a>(
&'a self,
mut sim: ExternModuleSimulationState<Self::IOType>,
) -> impl IntoFuture<Output = ()> + 'a {
let Self { i, o } = *self;
async move {
sim.write(o, true).await;
sim.advance_time(SimDuration::from_nanos(500)).await;
let mut invert = false;
loop {
sim.advance_time(SimDuration::from_micros(1)).await;
let v = sim.read_bool(i).await;
sim.write(o, v ^ invert).await;
invert = !invert;
}
}
m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
sim.write(o, true).await;
sim.advance_time(SimDuration::from_nanos(500)).await;
let mut invert = false;
loop {
sim.advance_time(SimDuration::from_micros(1)).await;
let v = sim.read_bool(i).await;
sim.write(o, v ^ invert).await;
invert = !invert;
}
}
m.extern_module_simulation(Sim { i, o });
});
}
#[test]