From 838bd469ce6247c3f94f404541a7ac1a41c825c6 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 24 Oct 2025 00:53:13 -0700
Subject: [PATCH] change SimulationImpl::trace_memories to a BTreeMap for
 consistent iteration order

---
 crates/fayalite/src/sim.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index fabe6d8..44030c1 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1522,7 +1522,7 @@ struct SimulationImpl {
     state_ready_to_run: bool,
     trace_decls: TraceModule,
     traces: SimTraces<Box<[SimTrace<SimTraceKind, SimTraceState>]>>,
-    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
+    trace_memories: BTreeMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
     instant: SimInstant,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
@@ -1622,7 +1622,7 @@ impl SimulationImpl {
                     last_state: kind.make_state(),
                 },
             ))),
-            trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()),
+            trace_memories: BTreeMap::from_iter(compiled.trace_memories.iter().copied()),
             trace_writers: vec![],
             instant: SimInstant::START,
             clocks_triggered: compiled.clocks_triggered,