forked from libre-chip/fayalite
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
This commit is contained in:
parent
2aa41137d4
commit
80b92c7dd3
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 120 additions and 394 deletions
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@ -26,6 +26,7 @@ use std::{
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collections::BTreeMap,
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fmt::{self, Write as _},
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io, mem,
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num::NonZeroU64,
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};
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#[derive(Default, Clone)]
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@ -186,6 +187,26 @@ impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
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}
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}
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/// pass in scope to ensure it's not available in child scope
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fn try_write_vcd_scope<W: io::Write, R>(
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writer: &mut W,
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scope_type: &str,
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scope_name: Interned<str>,
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scope: Option<&mut Scope>,
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f: impl FnOnce(&mut W, Option<&mut Scope>) -> io::Result<R>,
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) -> io::Result<R> {
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let Some(scope) = scope else {
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return f(writer, None);
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};
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write_vcd_scope(
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writer,
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scope_type,
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scope_name,
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scope,
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move |writer, scope| f(writer, Some(scope)),
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)
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}
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/// pass in scope to ensure it's not available in child scope
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fn write_vcd_scope<W: io::Write, R>(
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writer: &mut W,
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@ -237,6 +258,7 @@ trait_arg! {
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struct ArgModule<'a> {
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properties: &'a mut VcdWriterProperties,
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scope: &'a mut Scope,
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instance_name: Option<Interned<str>>,
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}
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impl<'a> ArgModule<'a> {
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@ -244,6 +266,7 @@ impl<'a> ArgModule<'a> {
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ArgModule {
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properties: self.properties,
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scope: self.scope,
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instance_name: self.instance_name,
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}
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}
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}
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@ -267,7 +290,7 @@ struct ArgInType<'a> {
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sink_var_type: &'static str,
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duplex_var_type: &'static str,
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properties: &'a mut VcdWriterProperties,
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scope: &'a mut Scope,
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scope: Option<&'a mut Scope>,
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}
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impl<'a> ArgInType<'a> {
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@ -277,7 +300,7 @@ impl<'a> ArgInType<'a> {
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sink_var_type: self.sink_var_type,
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duplex_var_type: self.duplex_var_type,
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properties: self.properties,
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scope: self.scope,
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scope: self.scope.as_deref_mut(),
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}
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}
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}
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@ -314,7 +337,7 @@ impl WriteTrace for TraceScalar {
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#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
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#[repr(transparent)]
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struct VcdId(u64);
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struct VcdId(NonZeroU64);
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impl VcdId {
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const CHAR_RANGE: std::ops::RangeInclusive<u8> = b'!'..=b'~';
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@ -344,11 +367,14 @@ impl VcdId {
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};
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retval = v;
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}
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let Some(retval) = NonZeroU64::new(retval) else {
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return None;
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};
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Some(Self(retval))
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}
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#[must_use]
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const fn write(self, out: &mut [u8]) -> usize {
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let mut id = self.0;
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let mut id = self.0.get();
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let mut len = 0;
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loop {
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let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start();
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@ -363,7 +389,7 @@ impl VcdId {
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}
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len
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}
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const MAX_ID_LEN: usize = Self(u64::MAX).write(&mut []);
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const MAX_ID_LEN: usize = Self(NonZeroU64::MAX).write(&mut []);
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}
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/// check that VcdId properly round-trips
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@ -423,7 +449,7 @@ impl<T: fmt::Display> fmt::Display for Escaped<T> {
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fn write_vcd_var<W: io::Write>(
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properties: &mut VcdWriterProperties,
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scope: &mut Scope,
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scope: Option<&mut Scope>,
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memory_element_part_body: MemoryElementPartBody,
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writer: &mut W,
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var_type: &str,
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@ -431,8 +457,6 @@ fn write_vcd_var<W: io::Write>(
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location: TraceLocation,
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name: Interned<str>,
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) -> io::Result<()> {
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let path_hash = scope.path_hash.clone().joined(name);
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let name = scope.new_identifier(name);
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let id = match location {
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TraceLocation::Scalar(id) => id.as_usize(),
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TraceLocation::Memory(TraceMemoryLocation {
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@ -464,12 +488,21 @@ fn write_vcd_var<W: io::Write>(
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first_id + *element_index
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}
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};
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let id = properties
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.scalar_id_to_vcd_id_map
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.builder_get_or_insert(id, &path_hash);
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write!(writer, "$var {var_type} {size} ")?;
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write_vcd_id(writer, id)?;
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writeln!(writer, " {name} $end")
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if let Some(scope) = scope {
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let path_hash = scope.path_hash.clone().joined(name);
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let name = scope.new_identifier(name);
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let id = properties
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.scalar_id_to_vcd_id_map
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.builder_get_or_insert(id, &path_hash);
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write!(writer, "$var {var_type} {size} ")?;
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write_vcd_id(writer, id)?;
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writeln!(writer, " {name} $end")
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} else {
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properties
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.scalar_id_to_vcd_id_map
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.builder_unused_scalar_id(id);
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Ok(())
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}
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}
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impl WriteTrace for TraceUInt {
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@ -712,14 +745,24 @@ impl WriteTrace for TraceScope {
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impl WriteTrace for TraceModule {
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fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
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let ArgModule { properties, scope } = arg.module();
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let ArgModule {
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properties,
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scope,
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instance_name,
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} = arg.module();
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let Self { name, children } = self;
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write_vcd_scope(writer, "module", name, scope, |writer, scope| {
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for child in children {
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child.write_trace(writer, ArgModuleBody { properties, scope })?;
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}
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Ok(())
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})
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write_vcd_scope(
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writer,
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"module",
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instance_name.unwrap_or(name),
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scope,
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|writer, scope| {
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for child in children {
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child.write_trace(writer, ArgModuleBody { properties, scope })?;
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}
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Ok(())
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},
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)
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}
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}
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@ -727,7 +770,7 @@ impl WriteTrace for TraceInstance {
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fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
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let ArgModuleBody { properties, scope } = arg.module_body();
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let Self {
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name: _,
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name,
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instance_io,
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module,
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ty: _,
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@ -739,10 +782,17 @@ impl WriteTrace for TraceInstance {
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sink_var_type: "wire",
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duplex_var_type: "wire",
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properties,
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scope,
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scope: None,
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},
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)?;
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module.write_trace(writer, ArgModule { properties, scope })
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module.write_trace(
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writer,
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ArgModule {
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properties,
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scope,
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instance_name: Some(name),
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},
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)
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}
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}
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@ -781,7 +831,7 @@ impl WriteTrace for TraceMem {
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sink_var_type: "reg",
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duplex_var_type: "reg",
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properties,
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scope,
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scope: Some(scope),
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},
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)
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},
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@ -813,7 +863,7 @@ impl WriteTrace for TraceMemPort {
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sink_var_type: "wire",
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duplex_var_type: "wire",
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properties,
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scope,
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scope: Some(scope),
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},
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)
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}
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@ -834,7 +884,7 @@ impl WriteTrace for TraceWire {
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sink_var_type: "wire",
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duplex_var_type: "wire",
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properties,
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scope,
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scope: Some(scope),
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},
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)
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}
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@ -855,7 +905,7 @@ impl WriteTrace for TraceReg {
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sink_var_type: "reg",
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duplex_var_type: "reg",
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properties,
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scope,
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scope: Some(scope),
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},
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)
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}
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@ -877,7 +927,7 @@ impl WriteTrace for TraceModuleIO {
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sink_var_type: "wire",
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duplex_var_type: "wire",
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properties,
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scope,
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scope: Some(scope),
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},
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)
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}
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@ -898,7 +948,7 @@ impl WriteTrace for TraceBundle {
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ty: _,
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flow: _,
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} = self;
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write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
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try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
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for field in fields {
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field.write_trace(
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writer,
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@ -907,7 +957,7 @@ impl WriteTrace for TraceBundle {
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sink_var_type,
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duplex_var_type,
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properties,
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scope,
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scope: scope.as_deref_mut(),
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},
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)?;
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}
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@ -931,7 +981,7 @@ impl WriteTrace for TraceArray {
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ty: _,
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flow: _,
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} = self;
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write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
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try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
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for element in elements {
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element.write_trace(
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writer,
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@ -940,7 +990,7 @@ impl WriteTrace for TraceArray {
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sink_var_type,
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duplex_var_type,
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properties,
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scope,
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scope: scope.as_deref_mut(),
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},
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)?;
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}
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@ -965,7 +1015,7 @@ impl WriteTrace for TraceEnumWithFields {
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ty: _,
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flow: _,
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} = self;
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write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
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try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
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discriminant.write_trace(
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writer,
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ArgInType {
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@ -973,7 +1023,7 @@ impl WriteTrace for TraceEnumWithFields {
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sink_var_type,
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duplex_var_type,
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properties,
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scope,
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scope: scope.as_deref_mut(),
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},
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)?;
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for field in non_empty_fields {
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@ -984,7 +1034,7 @@ impl WriteTrace for TraceEnumWithFields {
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sink_var_type,
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duplex_var_type,
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properties,
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scope,
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scope: scope.as_deref_mut(),
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},
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)?;
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}
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@ -1026,6 +1076,7 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
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ArgModule {
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properties: &mut properties,
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scope: &mut Scope::new(PathHash::default()),
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instance_name: None,
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},
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)?;
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let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) =
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@ -1065,23 +1116,29 @@ struct MemoryProperties {
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}
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struct ScalarIdToVcdIdMap {
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scalar_id_to_vcd_id_map: Box<[VcdId]>,
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scalar_id_to_vcd_id_map: Box<[Option<VcdId>]>,
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}
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#[derive(Default)]
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struct ScalarIdToVcdIdMapBuilder {
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scalar_id_to_vcd_id_map: BTreeMap<usize, VcdId>,
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scalar_id_to_vcd_id_map: BTreeMap<usize, Option<VcdId>>,
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lower_half_to_next_upper_half_map: HashMap<u64, u64>,
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}
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impl ScalarIdToVcdIdMapBuilder {
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fn unused_scalar_id(&mut self, scalar_id: usize) {
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self.scalar_id_to_vcd_id_map
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.entry(scalar_id)
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.or_insert(None);
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}
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/// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change
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/// when unrelated variables are added/removed, making the generated VCD more friendly for git diff.
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fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
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*self
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.scalar_id_to_vcd_id_map
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.entry(scalar_id)
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.or_insert_with(|| {
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.or_insert(None)
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.get_or_insert_with(|| {
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let hash = u128::from_le_bytes(
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*path_hash
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.0
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@ -1094,7 +1151,7 @@ impl ScalarIdToVcdIdMapBuilder {
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let next_upper_half = self
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.lower_half_to_next_upper_half_map
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.entry(lower_half)
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.or_insert(0);
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.or_insert(if lower_half == 0 { 1 } else { 0 });
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let upper_half = *next_upper_half;
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*next_upper_half += 1;
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let Some(id) = upper_half
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@ -1103,7 +1160,7 @@ impl ScalarIdToVcdIdMapBuilder {
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else {
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panic!("too many VcdIds");
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};
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VcdId(id)
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VcdId(NonZeroU64::new(id).expect("known to not be zero"))
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})
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}
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fn build(self) -> ScalarIdToVcdIdMap {
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|
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@ -1129,7 +1186,7 @@ enum ScalarIdToVcdIdMapOrBuilder {
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}
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impl ScalarIdToVcdIdMapOrBuilder {
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fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> VcdId {
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fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> Option<VcdId> {
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let Self::Built(v) = self else {
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panic!("ScalarIdToVcdIdMap isn't built yet");
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};
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|
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@ -1141,6 +1198,12 @@ impl ScalarIdToVcdIdMapOrBuilder {
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};
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v.get_or_insert(scalar_id, path_hash)
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}
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fn builder_unused_scalar_id(&mut self, scalar_id: usize) {
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let Self::Builder(v) = self else {
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panic!("ScalarIdToVcdIdMap is already built");
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};
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v.unused_scalar_id(scalar_id)
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}
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}
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struct VcdWriterProperties {
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|
|
@ -1165,8 +1228,11 @@ impl<W: io::Write + 'static> VcdWriter<W> {
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fn write_string_value_change(
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writer: &mut impl io::Write,
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value: impl fmt::Display,
|
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id: VcdId,
|
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id: Option<VcdId>,
|
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) -> io::Result<()> {
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let Some(id) = id else {
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return Ok(());
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};
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write!(writer, "s{} ", Escaped(value))?;
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write_vcd_id(writer, id)?;
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writer.write_all(b"\n")
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|
|
@ -1175,8 +1241,11 @@ fn write_string_value_change(
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fn write_bits_value_change(
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writer: &mut impl io::Write,
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value: &BitSlice,
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id: VcdId,
|
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id: Option<VcdId>,
|
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) -> io::Result<()> {
|
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let Some(id) = id else {
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return Ok(());
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};
|
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match value.len() {
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0 => writer.write_all(b"s0 ")?,
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1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
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|
|
@ -1205,7 +1274,7 @@ fn write_enum_discriminant_value_change(
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writer: &mut impl io::Write,
|
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variant_index: usize,
|
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ty: Enum,
|
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id: VcdId,
|
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id: Option<VcdId>,
|
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) -> io::Result<()> {
|
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write_string_value_change(
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writer,
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|
|
|
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|
|
@ -6,18 +6,12 @@ $var wire 2 Q2~aG o $end
|
|||
$var wire 2 DXK'| i2 $end
|
||||
$var wire 4 cPuix o2 $end
|
||||
$upscope $end
|
||||
$scope struct child $end
|
||||
$scope module child $end
|
||||
$var wire 4 ($5K7 i $end
|
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$var wire 2 %6Wv" o $end
|
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$var wire 2 +|-AU i2 $end
|
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$var wire 4 Hw?%j o2 $end
|
||||
$upscope $end
|
||||
$scope module mod1_child $end
|
||||
$var wire 4 4}s%= i $end
|
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$var wire 2 }IY?g o $end
|
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$var wire 2 of42K i2 $end
|
||||
$var wire 4 D9]&= o2 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
|
|
@ -25,10 +19,6 @@ b11 avK(^
|
|||
b11 Q2~aG
|
||||
b10 DXK'|
|
||||
b1110 cPuix
|
||||
b11 4}s%=
|
||||
b11 }IY?g
|
||||
b10 of42K
|
||||
b1110 D9]&=
|
||||
b11 ($5K7
|
||||
b11 %6Wv"
|
||||
b10 +|-AU
|
||||
|
|
@ -38,9 +28,6 @@ $end
|
|||
b1010 avK(^
|
||||
b10 Q2~aG
|
||||
b1111 cPuix
|
||||
b1010 4}s%=
|
||||
b10 }IY?g
|
||||
b1111 D9]&=
|
||||
b1010 ($5K7
|
||||
b10 %6Wv"
|
||||
b1111 Hw?%j
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,7 +8,7 @@ $var string 1 g:xf? inp $end
|
|||
$var string 1 [OKKg out1 $end
|
||||
$var string 1 9pB-> out2 $end
|
||||
$var string 1 8(7-4 out3 $end
|
||||
$scope struct helper1 $end
|
||||
$scope module helper1 $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 $Kwp\ clk $end
|
||||
$var wire 1 nmVq' rst $end
|
||||
|
|
@ -16,17 +16,9 @@ $upscope $end
|
|||
$var string 1 qS)@z inp $end
|
||||
$var string 1 ~je// out $end
|
||||
$upscope $end
|
||||
$scope module sim_only_connects_helper $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 %uCn6 clk $end
|
||||
$var wire 1 Apu`K rst $end
|
||||
$upscope $end
|
||||
$var string 1 $U*lA inp $end
|
||||
$var string 1 !prwC out $end
|
||||
$upscope $end
|
||||
$var string 1 CyjVm delay1 $end
|
||||
$var reg 1 z~g{\ delay1_empty $end
|
||||
$scope struct helper2 $end
|
||||
$scope module helper2 $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 Ph.=# clk $end
|
||||
$var wire 1 !GXK\ rst $end
|
||||
|
|
@ -34,14 +26,6 @@ $upscope $end
|
|||
$var string 1 /YVv: inp $end
|
||||
$var string 1 Kk*{# out $end
|
||||
$upscope $end
|
||||
$scope module sim_only_connects_helper_2 $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 %uCn6" clk $end
|
||||
$var wire 1 Apu`K" rst $end
|
||||
$upscope $end
|
||||
$var string 1 $U*lA" inp $end
|
||||
$var string 1 !prwC" out $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
|
|
@ -51,20 +35,12 @@ s{\"extra\":\x20\"value\"} g:xf?
|
|||
s{} [OKKg
|
||||
s{} 9pB->
|
||||
s{} 8(7-4
|
||||
0%uCn6
|
||||
1Apu`K
|
||||
s{} $U*lA
|
||||
s{} !prwC
|
||||
0$Kwp\
|
||||
1nmVq'
|
||||
s{} qS)@z
|
||||
s{} ~je//
|
||||
s{} CyjVm
|
||||
0z~g{\
|
||||
0%uCn6"
|
||||
1Apu`K"
|
||||
s{} $U*lA"
|
||||
s{} !prwC"
|
||||
0Ph.=#
|
||||
1!GXK\
|
||||
s{} /YVv:
|
||||
|
|
@ -73,110 +49,74 @@ $end
|
|||
#1000000
|
||||
1tq:(w
|
||||
s{\"extra\":\x20\"value\"} [OKKg
|
||||
1%uCn6
|
||||
s{\"extra\":\x20\"value\"} $U*lA
|
||||
1$Kwp\
|
||||
s{\"extra\":\x20\"value\"} qS)@z
|
||||
1z~g{\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB->
|
||||
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC
|
||||
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je//
|
||||
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} $U*lA"
|
||||
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv:
|
||||
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4
|
||||
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC"
|
||||
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{#
|
||||
#2000000
|
||||
0tq:(w
|
||||
0FVlgb
|
||||
0%uCn6
|
||||
0Apu`K
|
||||
0$Kwp\
|
||||
0nmVq'
|
||||
0%uCn6"
|
||||
0Apu`K"
|
||||
0Ph.=#
|
||||
0!GXK\
|
||||
#3000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
s{\"extra\":\x20\"value\"} CyjVm
|
||||
0z~g{\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#4000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#5000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#6000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#7000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#8000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#9000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#10000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#11000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#12000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#13000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#14000000
|
||||
0tq:(w
|
||||
0%uCn6
|
||||
0$Kwp\
|
||||
0%uCn6"
|
||||
0Ph.=#
|
||||
#15000000
|
||||
1tq:(w
|
||||
1%uCn6
|
||||
1$Kwp\
|
||||
1%uCn6"
|
||||
1Ph.=#
|
||||
#16000000
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue