re-export bitvec and add types useful for simulation to the prelude

crates/fayalite/src/lib.rs

@@ -8,8 +8,6 @@
 
 extern crate self as fayalite;
 
-#[doc(hidden)]
-pub use bitvec as __bitvec;
 #[doc(hidden)]
 pub use std as __std;
 
@@ -78,6 +76,8 @@ pub use fayalite_proc_macros::hdl_module;
 #[doc(inline)]
 pub use fayalite_proc_macros::hdl;
 
+pub use bitvec;
+
 /// struct used as a placeholder when applying defaults
 #[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
 pub struct __;

crates/fayalite/src/prelude.rs

@@ -20,7 +20,7 @@ pub use crate::{
         hdl_cover_with_enable, MakeFormalExpr,
     },
     hdl, hdl_module,
-    int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
+    int::{Bool, DynSize, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
         annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
@@ -29,9 +29,15 @@ pub use crate::{
     phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
+    sim::{
+        time::{SimDuration, SimInstant},
+        value::{SimValue, ToSimValue, ToSimValueWithType},
+        ExternModuleSimulationState, Simulation,
+    },
     source_location::SourceLocation,
     ty::{AsMask, CanonicalType, Type},
     util::{ConstUsize, GenericConstUsize},
     wire::Wire,
     __,
 };
+pub use bitvec::{slice::BitSlice, vec::BitVec};

crates/fayalite/tests/sim.rs

@@ -2,12 +2,11 @@
 // See Notices.txt for copyright information
 
 use fayalite::{
-    int::UIntValue,
     memory::{ReadStruct, ReadWriteStruct, WriteStruct},
     module::{instance_with_loc, reg_builder_with_loc},
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
+    sim::vcd::VcdWriterDecls,
     util::RcWriter,
 };
 use std::num::NonZeroUsize;