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vcd: single bit signals have no spaces in their value changes

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This commit is contained in:
Jacob Lifshay 2024-12-01 20:12:43 -08:00
parent 12b3ba57f1
commit 5e0548db26
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 3 additions and 3 deletions
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2
crates/fayalite/src/sim/vcd.rs
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@ -477,7 +477,7 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> { fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
match value.len() { match value.len() {
0 => self.writer.write_all(b"s0 ")?, 0 => self.writer.write_all(b"s0 ")?,
1 => write!(self.writer, "{} ", if value[0] { "1" } else { "0" })?, 1 => self.writer.write_all(if value[0] { b"1" } else { b"0" })?,
_ => { _ => {
self.writer.write_all(b"b")?; self.writer.write_all(b"b")?;
let mut any_ones = false; let mut any_ones = false;

4
crates/fayalite/tests/sim.rs
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@ -185,8 +185,8 @@ $var wire 1 " bit_out $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end
$dumpvars $dumpvars
1 ! 1!
1 " 1"
$end $end
#1000000 #1000000
"# { "# {