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vcd: single bit signals have no spaces in their value changes

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This commit is contained in:
Jacob Lifshay 2024-12-01 20:12:43 -08:00
parent 12b3ba57f1
commit 5e0548db26
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 3 additions and 3 deletions
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4
crates/fayalite/tests/sim.rs
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@ -185,8 +185,8 @@ $var wire 1 " bit_out $end
$upscope $end
$enddefinitions $end
$dumpvars
1 !
1 "
1!
1"
$end
#1000000
"# {