forked from libre-chip/fayalite
change SimValue to contain and deref to a value and not just contain bits
This commit is contained in:
parent
e0f978fbb6
commit
5028401a5a
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
19 changed files with 2065 additions and 820 deletions
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@ -3,10 +3,16 @@
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use fayalite::{
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int::UIntValue,
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memory::{ReadStruct, ReadWriteStruct, WriteStruct},
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module::{instance_with_loc, reg_builder_with_loc},
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prelude::*,
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reset::ResetType,
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sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
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sim::{
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time::SimDuration,
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value::{SimValue, ToSimValue},
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vcd::VcdWriterDecls,
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Simulation,
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},
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ty::StaticType,
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util::RcWriter,
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};
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@ -396,32 +402,14 @@ fn test_enums() {
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sim.write_reset(sim.io().cd.rst, false);
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sim.advance_time(SimDuration::from_nanos(900));
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type BOutTy = HdlOption<(UInt<1>, Bool)>;
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#[derive(Debug)]
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#[derive(Debug, PartialEq)]
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struct IO {
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en: bool,
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which_in: u8,
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data_in: u8,
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which_out: u8,
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data_out: u8,
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b_out: Expr<BOutTy>,
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}
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impl PartialEq for IO {
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fn eq(&self, other: &Self) -> bool {
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let Self {
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en,
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which_in,
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data_in,
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which_out,
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data_out,
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b_out,
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} = *self;
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en == other.en
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&& which_in == other.which_in
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&& data_in == other.data_in
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&& which_out == other.which_out
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&& data_out == other.data_out
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&& b_out.to_sim_value(BOutTy::TYPE) == other.b_out.to_sim_value(BOutTy::TYPE)
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}
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b_out: SimValue<BOutTy>,
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}
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let io_cycles = [
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IO {
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@ -430,7 +418,7 @@ fn test_enums() {
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data_in: 0,
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which_out: 0,
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data_out: 0,
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b_out: HdlNone(),
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b_out: HdlNone().to_sim_value(StaticType::TYPE),
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},
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IO {
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en: true,
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@ -438,7 +426,7 @@ fn test_enums() {
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data_in: 0,
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which_out: 0,
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data_out: 0,
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b_out: HdlNone(),
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b_out: HdlNone().to_sim_value(StaticType::TYPE),
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},
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IO {
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en: false,
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@ -446,7 +434,7 @@ fn test_enums() {
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data_in: 0,
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which_out: 1,
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data_out: 0,
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b_out: HdlSome((0_hdl_u1, false)),
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b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
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},
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IO {
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en: true,
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@ -454,7 +442,7 @@ fn test_enums() {
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data_in: 0xF,
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which_out: 1,
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data_out: 0,
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b_out: HdlSome((0_hdl_u1, false)),
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b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
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},
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IO {
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en: true,
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@ -462,7 +450,7 @@ fn test_enums() {
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data_in: 0xF,
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which_out: 1,
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data_out: 0x3,
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b_out: HdlSome((1_hdl_u1, true)),
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b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
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},
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IO {
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en: true,
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@ -470,7 +458,7 @@ fn test_enums() {
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data_in: 0xF,
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which_out: 1,
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data_out: 0x3,
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b_out: HdlSome((1_hdl_u1, true)),
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b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
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},
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IO {
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en: true,
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@ -478,7 +466,7 @@ fn test_enums() {
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data_in: 0xF,
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which_out: 2,
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data_out: 0xF,
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b_out: HdlNone(),
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b_out: HdlNone().to_sim_value(StaticType::TYPE),
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},
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];
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for (
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@ -510,7 +498,7 @@ fn test_enums() {
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.to_bigint()
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.try_into()
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.expect("known to be in range"),
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b_out: sim.read(sim.io().b_out).to_expr(),
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b_out: sim.read(sim.io().b_out),
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};
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assert_eq!(
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expected,
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@ -539,9 +527,9 @@ fn test_enums() {
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#[hdl_module(outline_generated)]
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pub fn memories() {
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#[hdl]
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let r: fayalite::memory::ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
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let r: ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
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#[hdl]
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let w: fayalite::memory::WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
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let w: WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
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#[hdl]
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let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
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mem.read_latency(0);
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@ -560,120 +548,131 @@ fn test_memories() {
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write_clock(sim.io().r.clk, false);
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sim.write_clock(sim.io().w.clk, false);
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#[derive(Debug, PartialEq, Eq)]
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#[hdl(cmp_eq)]
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struct IO {
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r_addr: u8,
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r_en: bool,
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r_data: (u8, i8),
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w_addr: u8,
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w_en: bool,
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w_data: (u8, i8),
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w_mask: (bool, bool),
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r_addr: UInt<4>,
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r_en: Bool,
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r_data: (UInt<8>, SInt<8>),
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w_addr: UInt<4>,
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w_en: Bool,
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w_data: (UInt<8>, SInt<8>),
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w_mask: (Bool, Bool),
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}
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let io_cycles = [
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: false,
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r_data: (0, 0),
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w_addr: 0,
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r_data: (0u8, 0i8),
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w_addr: 0_hdl_u4,
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w_en: false,
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w_data: (0, 0),
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w_data: (0u8, 0i8),
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w_mask: (false, false),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x1, 0x23),
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w_addr: 0,
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r_data: (0x1u8, 0x23i8),
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w_addr: 0_hdl_u4,
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w_en: true,
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w_data: (0x10, 0x20),
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w_data: (0x10u8, 0x20i8),
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w_mask: (true, true),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x10, 0x20),
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w_addr: 0,
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r_data: (0x10u8, 0x20i8),
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w_addr: 0_hdl_u4,
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w_en: true,
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w_data: (0x30, 0x40),
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w_data: (0x30u8, 0x40i8),
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w_mask: (false, true),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x10, 0x40),
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w_addr: 0,
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r_data: (0x10u8, 0x40i8),
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w_addr: 0_hdl_u4,
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w_en: true,
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w_data: (0x50, 0x60),
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w_data: (0x50u8, 0x60i8),
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w_mask: (true, false),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x50, 0x40),
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w_addr: 0,
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r_data: (0x50u8, 0x40i8),
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w_addr: 0_hdl_u4,
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w_en: true,
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w_data: (0x70, -0x80),
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w_data: (0x70u8, -0x80i8),
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w_mask: (false, false),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x50, 0x40),
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w_addr: 0,
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r_data: (0x50u8, 0x40i8),
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w_addr: 0_hdl_u4,
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w_en: false,
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w_data: (0x90, 0xA0u8 as i8),
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w_data: (0x90u8, 0xA0u8 as i8),
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w_mask: (false, false),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x50, 0x40),
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w_addr: 1,
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r_data: (0x50u8, 0x40i8),
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w_addr: 1_hdl_u4,
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w_en: true,
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w_data: (0x90, 0xA0u8 as i8),
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w_data: (0x90u8, 0xA0u8 as i8),
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w_mask: (true, true),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x50, 0x40),
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w_addr: 2,
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r_data: (0x50u8, 0x40i8),
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w_addr: 2_hdl_u4,
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w_en: true,
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w_data: (0xB0, 0xC0u8 as i8),
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w_data: (0xB0u8, 0xC0u8 as i8),
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w_mask: (true, true),
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},
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#[hdl]
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IO {
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r_addr: 0,
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r_addr: 0_hdl_u4,
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r_en: true,
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r_data: (0x50, 0x40),
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w_addr: 2,
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r_data: (0x50u8, 0x40i8),
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w_addr: 2_hdl_u4,
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w_en: false,
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w_data: (0xD0, 0xE0u8 as i8),
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w_data: (0xD0u8, 0xE0u8 as i8),
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w_mask: (true, true),
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},
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#[hdl]
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IO {
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r_addr: 1,
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r_addr: 1_hdl_u4,
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r_en: true,
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r_data: (0x90, 0xA0u8 as i8),
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w_addr: 2,
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r_data: (0x90u8, 0xA0u8 as i8),
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w_addr: 2_hdl_u4,
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w_en: false,
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w_data: (0xD0, 0xE0u8 as i8),
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w_data: (0xD0u8, 0xE0u8 as i8),
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w_mask: (true, true),
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},
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#[hdl]
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IO {
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r_addr: 2,
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r_addr: 2_hdl_u4,
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r_en: true,
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r_data: (0xB0, 0xC0u8 as i8),
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w_addr: 2,
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r_data: (0xB0u8, 0xC0u8 as i8),
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w_addr: 2_hdl_u4,
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w_en: false,
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w_data: (0xD0, 0xE0u8 as i8),
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w_data: (0xD0u8, 0xE0u8 as i8),
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w_mask: (true, true),
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},
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];
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for (
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cycle,
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expected @ IO {
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for (cycle, expected) in io_cycles.into_iter().enumerate() {
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#[hdl]
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let IO {
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r_addr,
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r_en,
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r_data: _,
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@ -681,37 +680,26 @@ fn test_memories() {
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w_en,
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w_data,
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w_mask,
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},
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) in io_cycles.into_iter().enumerate()
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{
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sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
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sim.write_bool(sim.io().r.en, r_en);
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sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
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sim.write_bool(sim.io().w.en, w_en);
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sim.write_bool_or_int(sim.io().w.data.0, w_data.0);
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sim.write_bool_or_int(sim.io().w.data.1, w_data.1);
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sim.write_bool(sim.io().w.mask.0, w_mask.0);
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sim.write_bool(sim.io().w.mask.1, w_mask.1);
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let io = IO {
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} = expected;
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sim.write(sim.io().r.addr, r_addr);
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sim.write(sim.io().r.en, r_en);
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sim.write(sim.io().w.addr, w_addr);
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sim.write(sim.io().w.en, w_en);
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sim.write(sim.io().w.data, w_data);
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sim.write(sim.io().w.mask, w_mask);
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let io = (#[hdl]
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IO {
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r_addr,
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r_en,
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r_data: (
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sim.read_bool_or_int(sim.io().r.data.0)
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.to_bigint()
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.try_into()
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.expect("known to be in range"),
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sim.read_bool_or_int(sim.io().r.data.1)
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.to_bigint()
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.try_into()
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.expect("known to be in range"),
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),
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r_data: sim.read(sim.io().r.data),
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w_addr,
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w_en,
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w_data,
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w_mask,
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};
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})
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.to_sim_value(StaticType::TYPE);
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assert_eq!(
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expected,
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expected.to_sim_value(StaticType::TYPE),
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io,
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"vcd:\n{}\ncycle: {cycle}",
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String::from_utf8(writer.take()).unwrap(),
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@ -739,7 +727,7 @@ fn test_memories() {
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#[hdl_module(outline_generated)]
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pub fn memories2() {
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#[hdl]
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let rw: fayalite::memory::ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
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let rw: ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
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#[hdl]
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let mut mem = memory_with_init([HdlSome(true); 5]);
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mem.read_latency(1);
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@ -1012,9 +1000,9 @@ fn test_memories2() {
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#[hdl_module(outline_generated)]
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pub fn memories3() {
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#[hdl]
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let r: fayalite::memory::ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
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let r: ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
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#[hdl]
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let w: fayalite::memory::WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
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let w: WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
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#[hdl]
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let mut mem: MemBuilder<Array<UInt<8>, 8>> = memory();
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mem.depth(8);
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