forked from libre-chip/fayalite
add ExternModuleSimulationState::fork_join_scope
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 2325 additions and 1 deletions
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@ -49,7 +49,7 @@ use std::{
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any::Any,
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borrow::Cow,
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cell::{Cell, RefCell},
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collections::BTreeMap,
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collections::{BTreeMap, BTreeSet},
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fmt,
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future::{Future, IntoFuture},
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hash::Hash,
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@ -3347,6 +3347,128 @@ impl ExternModuleSimulationState {
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module_index,
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}
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}
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pub async fn fork_join_scope<'env, F, Fut>(
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&mut self,
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in_scope: F,
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) -> <Fut::IntoFuture as Future>::Output
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where
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F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut,
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Fut: IntoFuture<IntoFuture: 'env + Future<Output: 'env>>,
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{
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let scope = ForkJoinScope {
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new_tasks: Rc::new(RefCell::new(vec![])),
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sim: self.forked_state(),
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};
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let join_handle = scope.spawn(in_scope);
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#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug)]
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struct TaskId(u64);
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struct TasksStateInner {
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next_task_id: u64,
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ready_tasks: BTreeSet<TaskId>,
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not_ready_tasks: BTreeSet<TaskId>,
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base_waker: std::task::Waker,
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}
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impl Default for TasksStateInner {
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fn default() -> Self {
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Self {
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next_task_id: Default::default(),
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ready_tasks: Default::default(),
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not_ready_tasks: Default::default(),
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base_waker: std::task::Waker::noop().clone(),
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}
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}
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}
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#[derive(Default)]
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struct TasksState {
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inner: Mutex<TasksStateInner>,
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}
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#[derive(Clone)]
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struct TaskWaker {
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state: std::sync::Weak<TasksState>,
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task: TaskId,
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}
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impl std::task::Wake for TaskWaker {
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fn wake(self: Arc<Self>) {
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self.wake_by_ref();
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}
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fn wake_by_ref(self: &Arc<Self>) {
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let Some(state) = self.state.upgrade() else {
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return;
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};
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let mut inner = state.inner.lock().expect("not poisoned");
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if inner.not_ready_tasks.remove(&self.task) {
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inner.ready_tasks.insert(self.task);
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inner.base_waker.wake_by_ref();
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}
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}
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}
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struct Task<'env> {
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task: Pin<Box<dyn Future<Output = ()> + 'env>>,
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waker: std::task::Waker,
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}
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let mut tasks: BTreeMap<TaskId, Task> = BTreeMap::new();
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let tasks_state = Arc::new(TasksState::default());
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std::future::poll_fn(move |cx: &mut std::task::Context<'_>| {
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let mut state_inner = tasks_state.inner.lock().expect("not poisoned");
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state_inner.base_waker.clone_from(cx.waker());
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loop {
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for new_task in scope.new_tasks.borrow_mut().drain(..) {
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let task_id = TaskId(state_inner.next_task_id);
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let Some(next_task_id) = state_inner.next_task_id.checked_add(1) else {
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drop(state_inner);
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panic!("spawned too many tasks");
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};
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state_inner.next_task_id = next_task_id;
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state_inner.ready_tasks.insert(task_id);
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tasks.insert(
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task_id,
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Task {
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task: new_task,
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waker: Arc::new(TaskWaker {
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state: Arc::downgrade(&tasks_state),
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task: task_id,
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})
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.into(),
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},
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);
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}
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let Some(task_id) = state_inner.ready_tasks.pop_first() else {
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if state_inner.not_ready_tasks.is_empty() {
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return Poll::Ready(());
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} else {
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return Poll::Pending;
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};
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};
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state_inner.not_ready_tasks.insert(task_id); // task can be woken while we're running poll
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drop(state_inner);
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let std::collections::btree_map::Entry::Occupied(mut entry) = tasks.entry(task_id)
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else {
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unreachable!();
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};
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let Task { task, waker } = entry.get_mut();
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match task.as_mut().poll(&mut std::task::Context::from_waker(
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&std::task::Waker::from(waker.clone()),
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)) {
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Poll::Pending => {
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state_inner = tasks_state.inner.lock().expect("not poisoned");
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continue;
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}
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Poll::Ready(()) => {}
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}
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drop(entry.remove()); // drop outside lock
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state_inner = tasks_state.inner.lock().expect("not poisoned");
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state_inner.not_ready_tasks.remove(&task_id);
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state_inner.ready_tasks.remove(&task_id);
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}
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})
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.await;
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match &mut *join_handle.state.borrow_mut() {
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JoinHandleState::Running(_) => unreachable!(),
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JoinHandleState::Finished(state) => state
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.take()
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.expect("filled by running all futures to completion"),
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}
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}
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impl_simulation_methods!(
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async_await = (async, await),
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track_caller = (),
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@ -3354,6 +3476,125 @@ impl ExternModuleSimulationState {
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);
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}
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pub struct ForkJoinScope<'env> {
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new_tasks: Rc<RefCell<Vec<Pin<Box<dyn Future<Output = ()> + 'env>>>>>,
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sim: ExternModuleSimulationState,
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}
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impl<'env> Clone for ForkJoinScope<'env> {
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fn clone(&self) -> Self {
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Self {
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new_tasks: self.new_tasks.clone(),
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sim: self.sim.forked_state(),
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}
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}
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}
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impl<'env> ForkJoinScope<'env> {
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fn spawn_inner(&self, fut: Pin<Box<dyn Future<Output = ()> + 'env>>) {
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self.new_tasks.borrow_mut().push(fut);
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}
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pub fn spawn_detached_future(
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&self,
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fut: impl IntoFuture<IntoFuture: 'env + Future<Output = ()>>,
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) {
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self.spawn_inner(Box::pin(fut.into_future()));
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}
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pub fn spawn_detached<F, Fut>(&self, f: F)
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where
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F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut,
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Fut: IntoFuture<IntoFuture: 'env + Future<Output = ()>>,
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{
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self.spawn_detached_future(f(self.clone(), self.sim.forked_state()));
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}
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pub fn spawn<F, Fut>(&self, f: F) -> JoinHandle<Fut::Output>
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where
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F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut,
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Fut: IntoFuture<IntoFuture: 'env + Future<Output: 'env>>,
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{
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let join_handle = JoinHandle {
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state: Default::default(),
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};
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let state = Rc::downgrade(&join_handle.state);
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let fut = f(self.clone(), self.sim.forked_state()).into_future();
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self.spawn_detached_future(async move {
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let result = fut.await;
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let Some(state) = state.upgrade() else { return };
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let mut state = state.borrow_mut();
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let waker = match &mut *state {
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JoinHandleState::Running(waker) => waker.take(),
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JoinHandleState::Finished(_) => unreachable!(),
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};
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*state = JoinHandleState::Finished(Some(result));
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drop(state);
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let Some(waker) = waker else { return };
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waker.wake();
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});
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join_handle
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}
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}
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enum JoinHandleState<T> {
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Running(Option<std::task::Waker>),
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Finished(Option<T>),
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}
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impl<T> Default for JoinHandleState<T> {
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fn default() -> Self {
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Self::Running(None)
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}
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}
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pub struct JoinHandle<T> {
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state: Rc<RefCell<JoinHandleState<T>>>,
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}
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impl<T> JoinHandle<T> {
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pub fn is_finished(&self) -> bool {
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matches!(*self.state.borrow(), JoinHandleState::Finished(_))
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}
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pub fn try_join(self) -> Result<T, Self> {
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let mut state = self.state.borrow_mut();
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match &mut *state {
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JoinHandleState::Running(_) => {
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drop(state);
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Err(self)
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}
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JoinHandleState::Finished(retval) => {
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let Some(retval) = retval.take() else {
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panic!("already returned the value in poll");
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};
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Ok(retval)
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}
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}
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}
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pub async fn join(self) -> T {
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self.await
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}
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}
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impl<T> Future for JoinHandle<T> {
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type Output = T;
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fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll<Self::Output> {
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match &mut *self.state.borrow_mut() {
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JoinHandleState::Running(waker) => {
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match waker {
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None => *waker = Some(cx.waker().clone()),
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Some(waker) => waker.clone_from(cx.waker()),
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}
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Poll::Pending
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}
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JoinHandleState::Finished(retval) => {
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let Some(retval) = retval.take() else {
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panic!("already returned Poll::Ready");
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};
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Poll::Ready(retval)
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}
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}
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}
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}
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struct ForkJoinImpl<'a> {
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futures: Vec<Pin<Box<dyn Future<Output = ()> + 'a>>>,
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}
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@ -2109,6 +2109,99 @@ fn test_sim_fork_join() {
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}
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}
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#[hdl_module(outline_generated, extern)]
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pub fn sim_fork_join_scope<const N: usize>()
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where
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ConstUsize<N>: KnownSize,
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{
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#[hdl]
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let clocks: Array<Clock, N> = m.input();
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#[hdl]
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let outputs: Array<UInt<8>, N> = m.output();
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m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move {
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sim.write(outputs, [0u8; N]).await;
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loop {
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let written = vec![std::cell::Cell::new(false); N]; // test shared scope
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let written = &written; // work around move in async move
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sim.fork_join_scope(|scope, _| async move {
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let mut spawned = vec![];
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for i in 0..N {
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let join_handle =
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scope.spawn(move |_, mut sim: ExternModuleSimulationState| async move {
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sim.wait_for_clock_edge(clocks[i]).await;
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let v = sim
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.read_bool_or_int(outputs[i])
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.await
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.to_bigint()
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.try_into()
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.expect("known to be in range");
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sim.write(outputs[i], 1u8.wrapping_add(v)).await;
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written[i].set(true);
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i
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});
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if i % 2 == 0 && i < N - 1 {
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spawned.push((i, join_handle));
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}
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}
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for (i, join_handle) in spawned {
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assert_eq!(i, join_handle.join().await);
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}
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})
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.await;
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for written in written {
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assert!(written.get());
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}
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}
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});
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}
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#[test]
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fn test_sim_fork_join_scope() {
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let _n = SourceLocation::normalize_files_for_tests();
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const N: usize = 3;
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let mut sim = Simulation::new(sim_fork_join_scope::<N>());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write(sim.io().clocks, [false; N]);
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let mut clocks_triggered = [false; N];
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let mut expected = [0u8; N];
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for i0 in 0..N {
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for i1 in 0..N {
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for i2 in 0..N {
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for i3 in 0..N {
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let indexes = [i0, i1, i2, i3];
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for i in indexes {
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().clocks[i], true);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().clocks[i], false);
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if !clocks_triggered[i] {
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expected[i] = expected[i].wrapping_add(1);
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}
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clocks_triggered[i] = true;
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if clocks_triggered == [true; N] {
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clocks_triggered = [false; N];
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}
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let output = sim.read(sim.io().outputs);
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assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}");
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}
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}
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}
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}
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}
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/sim_fork_join_scope.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/sim_fork_join_scope.txt") {
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panic!();
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}
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}
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#[hdl_module(outline_generated, extern)]
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pub fn sim_resettable_counter<R: ResetType>() {
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#[hdl]
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|
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523
crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
Normal file
523
crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
Normal file
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@ -0,0 +1,523 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 6,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[2]",
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ty: UInt<8>,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Return,
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],
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..
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},
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pc: 0,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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0,
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0,
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0,
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49,
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50,
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50,
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],
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},
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sim_only_slots: StatePart {
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value: [],
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},
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},
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io: Instance {
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name: <simulator>::sim_fork_join_scope,
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instantiated: Module {
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name: sim_fork_join_scope,
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..
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},
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},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::sim_fork_join_scope,
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instantiated: Module {
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name: sim_fork_join_scope,
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..
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},
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}.clocks,
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Instance {
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name: <simulator>::sim_fork_join_scope,
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instantiated: Module {
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name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.outputs,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.clocks,
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.clocks[0],
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.clocks[1],
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.clocks[2],
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.outputs,
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.outputs[0],
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.outputs[1],
|
||||
Instance {
|
||||
name: <simulator>::sim_fork_join_scope,
|
||||
instantiated: Module {
|
||||
name: sim_fork_join_scope,
|
||||
..
|
||||
},
|
||||
}.outputs[2],
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
extern_modules: [
|
||||
SimulationExternModuleState {
|
||||
module_state: SimulationModuleState {
|
||||
base_targets: [
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
},
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
}[0],
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
}[1],
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
}[2],
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
}[0],
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
}[1],
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
}[2],
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
sim: ExternModuleSimulation {
|
||||
generator: SimGeneratorFn {
|
||||
args: (
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
},
|
||||
),
|
||||
f: ...,
|
||||
},
|
||||
sim_io_to_generator_map: {
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
}: ModuleIO {
|
||||
name: sim_fork_join_scope::clocks,
|
||||
is_input: true,
|
||||
ty: Array<Clock, 3>,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
}: ModuleIO {
|
||||
name: sim_fork_join_scope::outputs,
|
||||
is_input: false,
|
||||
ty: Array<UInt<8>, 3>,
|
||||
..
|
||||
},
|
||||
},
|
||||
source_location: SourceLocation(
|
||||
module-XXXXXXXXXX.rs:4:1,
|
||||
),
|
||||
},
|
||||
running_generator: Some(
|
||||
...,
|
||||
),
|
||||
},
|
||||
],
|
||||
trace_decls: TraceModule {
|
||||
name: "sim_fork_join_scope",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "clocks",
|
||||
child: TraceArray {
|
||||
name: "clocks",
|
||||
elements: [
|
||||
TraceClock {
|
||||
location: TraceScalarId(0),
|
||||
name: "[0]",
|
||||
flow: Source,
|
||||
},
|
||||
TraceClock {
|
||||
location: TraceScalarId(1),
|
||||
name: "[1]",
|
||||
flow: Source,
|
||||
},
|
||||
TraceClock {
|
||||
location: TraceScalarId(2),
|
||||
name: "[2]",
|
||||
flow: Source,
|
||||
},
|
||||
],
|
||||
ty: Array<Clock, 3>,
|
||||
flow: Source,
|
||||
},
|
||||
ty: Array<Clock, 3>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "outputs",
|
||||
child: TraceArray {
|
||||
name: "outputs",
|
||||
elements: [
|
||||
TraceUInt {
|
||||
location: TraceScalarId(3),
|
||||
name: "[0]",
|
||||
ty: UInt<8>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceUInt {
|
||||
location: TraceScalarId(4),
|
||||
name: "[1]",
|
||||
ty: UInt<8>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceUInt {
|
||||
location: TraceScalarId(5),
|
||||
name: "[2]",
|
||||
ty: UInt<8>,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
ty: Array<UInt<8>, 3>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: Array<UInt<8>, 3>,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(3),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(3),
|
||||
ty: UInt<8>,
|
||||
},
|
||||
state: 0x31,
|
||||
last_state: 0x31,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(4),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(4),
|
||||
ty: UInt<8>,
|
||||
},
|
||||
state: 0x32,
|
||||
last_state: 0x32,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(5),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(5),
|
||||
ty: UInt<8>,
|
||||
},
|
||||
state: 0x32,
|
||||
last_state: 0x32,
|
||||
},
|
||||
],
|
||||
trace_memories: {},
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
clocks_triggered: [],
|
||||
event_queue: EventQueue(EventQueueData {
|
||||
instant: 648 μs,
|
||||
events: {},
|
||||
}),
|
||||
waiting_sensitivity_sets_by_address: {
|
||||
SensitivitySet {
|
||||
id: 198,
|
||||
values: {
|
||||
CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
layout_data: [],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
||||
},
|
||||
write: None,
|
||||
}: SimValue {
|
||||
ty: Clock,
|
||||
value: OpaqueSimValue {
|
||||
bits: 0x0_u1,
|
||||
sim_only_values: [],
|
||||
},
|
||||
},
|
||||
},
|
||||
changed: Cell {
|
||||
value: false,
|
||||
},
|
||||
..
|
||||
},
|
||||
},
|
||||
waiting_sensitivity_sets_by_compiled_value: {
|
||||
CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
layout_data: [],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
||||
},
|
||||
write: None,
|
||||
}: (
|
||||
SimValue {
|
||||
ty: Clock,
|
||||
value: OpaqueSimValue {
|
||||
bits: 0x0_u1,
|
||||
sim_only_values: [],
|
||||
},
|
||||
},
|
||||
{
|
||||
SensitivitySet {
|
||||
id: 198,
|
||||
..
|
||||
},
|
||||
},
|
||||
),
|
||||
},
|
||||
..
|
||||
}
|
||||
1467
crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd
Normal file
1467
crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue