sim: add WIP memory test

crates/fayalite/tests/sim.rs

@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+
 use fayalite::{
     int::UIntValue,
     prelude::*,
@@ -7,6 +8,7 @@ use fayalite::{
     sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
 };
+use std::num::NonZeroUsize;
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -492,4 +494,113 @@ fn test_enums() {
     }
 }
 
-// TODO: add tests for memories
+#[hdl_module(outline_generated)]
+pub fn memories() {
+    #[hdl]
+    let r: fayalite::memory::ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let w: fayalite::memory::WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
+    mem.read_latency(0);
+    mem.write_latency(NonZeroUsize::new(1).unwrap());
+    mem.read_under_write(ReadUnderWrite::Old);
+    connect_any(mem.new_read_port(), r);
+    connect_any(mem.new_write_port(), w);
+}
+
+#[cfg(todo)] // TODO: finish
+#[hdl]
+#[test]
+fn test_memories() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().r.clk, false);
+    sim.write_clock(sim.io().w.clk, false);
+    #[derive(Debug, PartialEq, Eq)]
+    struct IO {
+        r_addr: u8,
+        r_en: bool,
+        r_data: (u8, i8),
+        w_addr: u8,
+        w_en: bool,
+        w_data: (u8, i8),
+        w_mask: (bool, bool),
+    }
+    let io_cycles = [IO {
+        r_addr: 0,
+        r_en: false,
+        r_data: (0, 0),
+        w_addr: 0,
+        w_en: false,
+        w_data: (0, 0),
+        w_mask: (false, false),
+    }];
+    for (
+        cycle,
+        expected @ IO {
+            r_addr,
+            r_en,
+            r_data: _,
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        },
+    ) in io_cycles.into_iter().enumerate()
+    {
+        sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
+        sim.write_bool(sim.io().r.en, r_en);
+        sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
+        sim.write_bool(sim.io().w.en, w_en);
+        sim.write_bool_or_int(sim.io().w.data.0, w_data.0);
+        sim.write_bool_or_int(sim.io().w.data.1, w_data.1);
+        sim.write_bool(sim.io().w.mask.0, w_mask.0);
+        sim.write_bool(sim.io().w.mask.1, w_mask.1);
+        let io = IO {
+            r_addr,
+            r_en,
+            r_data: (
+                sim.read_bool_or_int(sim.io().r.data.0)
+                    .to_bigint()
+                    .try_into()
+                    .expect("known to be in range"),
+                sim.read_bool_or_int(sim.io().r.data.1)
+                    .to_bigint()
+                    .try_into()
+                    .expect("known to be in range"),
+            ),
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        };
+        assert_eq!(
+            expected,
+            io,
+            "cycle: {cycle}\nvcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().r.clk, true);
+        sim.write_clock(sim.io().w.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().r.clk, false);
+        sim.write_clock(sim.io().w.clk, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories.txt") {
+        panic!();
+    }
+}
+
+// TODO: add more tests for memories