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writing VCD for combinatorial circuits works!

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This commit is contained in:
Jacob Lifshay 2024-11-20 22:36:12 -08:00
parent c4b5d00419
commit 11ddbc43c7
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 92 additions and 20 deletions
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85
crates/fayalite/tests/sim.rs
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@ -120,6 +120,7 @@ fn test_connect_const() {
},
},
made_initial_step: true,
needs_settle: false,
trace_decls: TraceModule {
name: "connect_const",
children: [
@ -182,7 +183,6 @@ pub fn mod1() {
connect(o, child);
}
#[cfg(todo)]
#[hdl]
#[test]
fn test_mod1() {
@ -195,10 +195,58 @@ fn test_mod1() {
sim.advance_time(SimDuration::from_micros(1));
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
sim.advance_time(SimDuration::from_micros(1));
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
todo!("generated vcd is incorrect");
if vcd != r#""# {
if vcd
!= r#"$timescale 1 ps $end
$scope module mod1 $end
$scope struct o $end
$var wire 4 ! i $end
$var wire 2 " o $end
$var wire 2 # i2 $end
$var wire 4 $ o2 $end
$upscope $end
$scope struct child $end
$var wire 4 ) i $end
$var wire 2 * o $end
$var wire 2 + i2 $end
$var wire 4 , o2 $end
$upscope $end
$scope module mod1_child $end
$var wire 4 % i $end
$var wire 2 & o $end
$var wire 2 ' i2 $end
$var wire 4 ( o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11 !
b11 "
b10 #
b1110 $
b11 %
b11 &
b10 '
b1110 (
b11 )
b11 *
b10 +
b1110 ,
$end
#1000000
b1010 !
b10 "
b1111 $
b1010 %
b10 &
b1111 (
b1010 )
b10 *
b1111 ,
#2000000
"# {
panic!();
}
let sim_debug = format!("{sim:#?}");
@ -718,6 +766,7 @@ fn test_mod1() {
},
},
made_initial_step: true,
needs_settle: false,
trace_decls: TraceModule {
name: "mod1",
children: [
@ -887,7 +936,7 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(1),
@ -896,7 +945,7 @@ fn test_mod1() {
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(2),
@ -914,7 +963,7 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
last_state: 0xe,
},
SimTrace {
id: TraceScalarId(4),
@ -923,7 +972,7 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(5),
@ -932,7 +981,7 @@ fn test_mod1() {
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(6),
@ -950,7 +999,7 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
last_state: 0xe,
},
SimTrace {
id: TraceScalarId(8),
@ -959,7 +1008,7 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(9),
@ -968,7 +1017,7 @@ fn test_mod1() {
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
last_state: 0x3,
},
SimTrace {
id: TraceScalarId(10),
@ -986,11 +1035,19 @@ fn test_mod1() {
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
last_state: 0xe,
},
],
trace_writers: [],
instant: 0 s,
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
instant: 2 μs,
}"# {
panic!();
}