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array_rw.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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array_rw.vcd
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tests/sim: add test_array_rw
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2025-01-12 21:38:59 -08:00 |
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conditional_assignment_last.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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conditional_assignment_last.vcd
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sim: fix "label address not set" bug when the last Assignment is conditional
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2025-01-15 19:04:40 -08:00 |
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connect_const.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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connect_const_reset.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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connect_const_reset.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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counter_async.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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counter_async.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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counter_sync.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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counter_sync.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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duplicate_names.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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duplicate_names.vcd
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properly handle duplicate names in vcd
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2025-01-09 22:52:22 -08:00 |
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enums.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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enums.vcd
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sim: add SimValue and reading/writing more than just a scalar
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2024-12-18 01:39:35 -08:00 |
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extern_module.txt
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simulator: allow external module generators to wait for value changes and/or clock edges
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2025-03-25 18:26:48 -07:00 |
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extern_module.vcd
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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extern_module2.txt
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change SimValue to contain and deref to a value and not just contain bits
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2025-03-27 23:44:36 -07:00 |
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extern_module2.vcd
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simulator: allow external module generators to wait for value changes and/or clock edges
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2025-03-25 18:26:48 -07:00 |
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memories.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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memories.vcd
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properly handle duplicate names in vcd
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2025-01-09 22:52:22 -08:00 |
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memories2.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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memories2.vcd
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properly handle duplicate names in vcd
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2025-01-09 22:52:22 -08:00 |
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memories3.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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memories3.vcd
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properly handle duplicate names in vcd
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2025-01-09 22:52:22 -08:00 |
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mod1.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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mod1.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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ripple_counter.txt
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change SimValue to contain and deref to a value and not just contain bits
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2025-03-27 23:44:36 -07:00 |
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ripple_counter.vcd
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add ripple counter test to test simulating alternating circuits and extern modules
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2025-03-25 18:56:26 -07:00 |
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shift_register.txt
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implement simulation of extern modules
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2025-03-21 01:47:14 -07:00 |
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shift_register.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
